Re: [gem5-users] PARSEC benchmarks in GEM5
List out all files and folders on terminals(pwd command) and check if blackscholes is listed . If it is not there move to the directory where blackscholes is present and execute it. On Tue, Dec 2, 2014 at 9:16 AM, Thom Popovici via gem5-users < gem5-users@gem5.org> wrote: > Hi all! > > I have one small question regarding gem5 and the parsec benchmarks. > > So I want to run some of the parsec benchmarks on gem5 built with the ARM > architecture. I grabbed parsec-3.0 and compiled some of the benchmarks > (blackscholes, fluidanimate, ferret, swaptions, dedup, streamcluster) on > an actual arm A15 processor (chromebook with a linux on top of it). > Grabbed the necessary libraries (hooks.so) and copied them inside the .img > file from the gem5 website (the 32 bit version). > > So far so good. I managed to enter terminal in FS mode. Set all the > environment variables and tried to launch the benchmarks. That backfired, > all the benchmarks gave me: > > -bash ./blackscholes: No such file or directory found. > > Does anyone know what might have happened or what I might have screwed up? > > Thanks, > Thom > > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -- *Geeta Patil,* Lecturer, CS/IS Department, BITS-Pilani, K.K. Birla, Goa Campus ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] PARSEC benchmarks in GEM5
Hi all! I have one small question regarding gem5 and the parsec benchmarks. So I want to run some of the parsec benchmarks on gem5 built with the ARM architecture. I grabbed parsec-3.0 and compiled some of the benchmarks (blackscholes, fluidanimate, ferret, swaptions, dedup, streamcluster) on an actual arm A15 processor (chromebook with a linux on top of it). Grabbed the necessary libraries (hooks.so) and copied them inside the .img file from the gem5 website (the 32 bit version). So far so good. I managed to enter terminal in FS mode. Set all the environment variables and tried to launch the benchmarks. That backfired, all the benchmarks gave me: -bash ./blackscholes: No such file or directory found. Does anyone know what might have happened or what I might have screwed up? Thanks, Thom ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Changing the L1 TLB on GEM5
Hello all, How do I change the configuration of the L1 TLB on GEM5? I tis currently fully associative. I am trying to change it to set associative but not finding a .py file to change configuration parameters that I can change. Has anyone done this before? I am trying to build GEM5 for x86. Thanks, Hari ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Re-Executing LAS Conflicts
Hi Arthur Thanks a lot for your reply. Your interpretation of LAS is what I require. I want to replay execution starting from the Load. It will be really helpful if you can give me hints on how to replay execution from this load instruction. Thanks On Mon, Dec 1, 2014 at 10:54 PM, Vanchinathan Venkataramani < dcsv...@nus.edu.sg> wrote: > Hi Arthur > > Thanks a lot for your reply. > > Your interpretation of LAS is what I require. > > I want to replay execution starting from the Load. It will be really > helpful if you can give me hints on how to replay execution from this load > instruction. > > Thanks > > > On Mon, Dec 1, 2014 at 10:01 PM, Arthur Perais > wrote: > >> Okay, the next comments assume that you are talking about a load that >> executed before an older store writing to the same address executed, and >> therefore got the wrong value. If what you call LAS refers to something >> else, disregard that. >> >> From what I gathered, the only replay mechanism currently implemented in >> the o3 CPU is there to deal with partial matches with store-to-load >> forwarding. >> For instance, when a load needs data that is part written by a store, and >> part in the dcache. In that case, the instruction is replayed when the >> store writes to the dcache (the mechanism is actually coarser than that but >> you get the idea). >> >> If you want selective replay for memory order violation (which is okay >> but quite complex in my opinion), you need to implement it yourself. This >> entails : >> - Getting all the instructions you need to replay (through register >> dependencies and memory dependencies). >> - Restore their state (clear the Issued flag, clear the Executed flag, >> and so on). >> - Restore dependencies which is non trivial since wakeDependents in >> inst_queue_impl.hh clears dependencies in dep_graph.hh when waking up >> insts. This means that you need to retain dependencies even after >> instructions have issued. You also need to deal with memory dependencies. >> - How do you replay? From the IQ? if so, then you can't free the IQ entry >> upon issue. If not, then you need a particular buffer to replay >> instructions from. >> >> If you want non-selective replay, this should be easier, although >> dependencies still have to be restored and you have to deal with the >> question of where the instructions are replayed from. >> >> Hope this helps, and if anyone sees a gross mistake in what I said, do >> not hesitate. >> >> Le 01/12/2014 14:47, Vanchinathan Venkataramani via gem5-users a écrit : >> >> Hi Andreas >> >> In ARM O3CPU, when there is a load after store violation, the younger >> instructions are being squashed and re-fetched again. >> >> Is it possible to re-execute these instructions instead of squashing >> all the younger instructions? >> >> Thanks >> >> >> >> ___ >> gem5-users mailing >> listgem5-users@gem5.orghttp://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >> >> >> >> -- >> Arthur Perais >> INRIA Bretagne Atlantique >> Bâtiment 12E, Bureau E303, Campus de Beaulieu >> 35042 Rennes, France >> >> > ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Re-Executing LAS Conflicts
Okay, the next comments assume that you are talking about a load that executed before an older store writing to the same address executed, and therefore got the wrong value. If what you call LAS refers to something else, disregard that. From what I gathered, the only replay mechanism currently implemented in the o3 CPU is there to deal with partial matches with store-to-load forwarding. For instance, when a load needs data that is part written by a store, and part in the dcache. In that case, the instruction is replayed when the store writes to the dcache (the mechanism is actually coarser than that but you get the idea). If you want selective replay for memory order violation (which is okay but quite complex in my opinion), you need to implement it yourself. This entails : - Getting all the instructions you need to replay (through register dependencies and memory dependencies). - Restore their state (clear the Issued flag, clear the Executed flag, and so on). - Restore dependencies which is non trivial since wakeDependents in inst_queue_impl.hh clears dependencies in dep_graph.hh when waking up insts. This means that you need to retain dependencies even after instructions have issued. You also need to deal with memory dependencies. - How do you replay? From the IQ? if so, then you can't free the IQ entry upon issue. If not, then you need a particular buffer to replay instructions from. If you want non-selective replay, this should be easier, although dependencies still have to be restored and you have to deal with the question of where the instructions are replayed from. Hope this helps, and if anyone sees a gross mistake in what I said, do not hesitate. Le 01/12/2014 14:47, Vanchinathan Venkataramani via gem5-users a écrit : Hi Andreas In ARM O3CPU, when there is a load after store violation, the younger instructions are being squashed and re-fetched again. Is it possible to re-execute these instructions instead of squashing all the younger instructions? Thanks ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users -- Arthur Perais INRIA Bretagne Atlantique Bâtiment 12E, Bureau E303, Campus de Beaulieu 35042 Rennes, France ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Re-Executing LAS Conflicts
Hi Andreas In ARM O3CPU, when there is a load after store violation, the younger instructions are being squashed and re-fetched again. Is it possible to re-execute these instructions instead of squashing all the younger instructions? Thanks ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
