Re: [gem5-users] Load schedule in O3 CPU
Hi Shyam, If I understand your question correctly, you are wondering whether it supports speculative scheduling? Based on my limited understanding of the DerivO3CPU scheduler, I think the scheduling policy only schedules a instruction once it knows all its dependencies are ready. I don’t think it speculatively schedules subsequent instructions dependent on a load, predicting that the load hits in the cache. More experienced folks may correct me if I am wrong. Cheers, Gururaj From: gem5-users mailto:gem5-users-boun...@gem5.org>> on behalf of Shyam Murthy mailto:shyammurth...@gmail.com>> Reply-To: gem5 users mailing list mailto:gem5-users@gem5.org>> Date: Friday, August 16, 2019 at 4:50 PM To: gem5 users mailing list mailto:gem5-users@gem5.org>> Subject: [gem5-users] Load schedule in O3 CPU Hi All, I had a couple of questions about how loads are scheduled in O3 CPU on gem5. Does the instruction schedule happen for a load expecting a cache hit? Is there a replay in case of a miss? I see that code defers memory instructions on a TLB miss. Is there similar code that handles loads that miss in the cache? Thanks for the help in advance. Thanks, Shyam ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Load schedule in O3 CPU
Hi All, I had a couple of questions about how loads are scheduled in O3 CPU on gem5. Does the instruction schedule happen for a load expecting a cache hit? Is there a replay in case of a miss? I see that code defers memory instructions on a TLB miss. Is there similar code that handles loads that miss in the cache? Thanks for the help in advance. Thanks, Shyam ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Does Risc-V support multi-threaded applications in SE mode?
Does Risc-V support multi-threaded applications in SE mode? I would like to run a multi-core processor using Risc-V. I intend to use pthread to parallelize my code but i don't know if it is supported in Risc-V ISA with SE mode. If not, is already possible to build a full system in RISC-V ISA? can anyone help me with these questions? Thanks in advance. -- Francisco Carlos Silva Junior PhD candidate Computer science Departament University of Brasilia ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] How to debug unexpected silent termination of benchmark program in SE mode
Grant, there is some support on ARM actually, but there are some known
bugs that we have to fix. I'll try to ping you if we manage to solve
it, or let us know if you do, it should not be very hard.
On Thu, Aug 15, 2019 at 9:52 PM Grant Vesely wrote:
>
> Thank you, this helped me find the problem: the benchmark program was
> invoking pthread_create(), and SE mode doesn't support threading.
>
> On Fri, Aug 2, 2019 at 5:15 PM Ciro Santilli wrote:
> >
> > Have you tried logging with build/ARM/gem5.opt --debug-flags ExecAll ?
> >
> > On Fri, Aug 2, 2019 at 4:32 PM Grant Vesely wrote:
> > >
> > > Good morning all,
> > >
> > > I am attempting to measure the performance of the ARM HPI model
> > > shipped with gem5 (in SE mode) using the XSBench
> > > (https://github.com/ANL-CESAR/XSBench) benchmark program.
> > >
> > > gem5 appears to exit normally ("existing with last active thread
> > > context @ n") without the benchmark completing (XSBench prints
> > > benchmark results to stdout that are not present).
> > >
> > > I am using gem5.opt 2.0 with the command-line `build/ARM/gem5.opt
> > > configs/example/arm/starter_se.py --cpu="hpi" --num-cores=1
> > > --mem-size=8GB ~/XSBench/src/XSBench`.
> > >
> > > I don't have a core dump, stack trace, or source code location (e.g.
> > > if an assertion was violated) that I can use, and the simulation takes
> > > several days to reach the failure point, which appears to be in the
> > > main benchmark loop
> > > (XSBench/src/Simulation.c:run_history_based_simulation()), so I can't
> > > step through it in GDB. What can I do to debug this?
> > >
> > > Cheers,
> > >
> > > Grant Vesely
> > > ___
> > > gem5-users mailing list
> > > gem5-users@gem5.org
> > > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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