[gem5-users] how to interpret Commonitor output?
I want to trace Data Movement between CPU and L1DCache, so i
attached Commmonitor of changing BaseCPU.py.
Changed Code is this.
def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
self.monitor = CommMonitor()
self.monitor.trace = MemTraceProbe(trace_file="se_trace.txt",
trace_compress=False)
print("test this build")
self.icache = ic
self.dcache = dc
self.icache_port = ic.cpu_side
#self.dcache_port = dc.cpu_side
self.dcache_port = self.monitor.slave
self.monitor.master = dc.cpu_side
However, this output file "se_trace,txt" can't interpret.
The top part of the output file is like this.
"
gem5<9b>^A
^Xsystem.cpu.monitor.trace^X<80>
<94>¥<8d>^]"^O^H^@^R^K.writebacks"^O^H^A^R^K.functional"^N^H^B^R
.interrupt"^S^H^C^R^O.cpu.dtb.walker"^S^H^D^R^O.cpu.itb.walker"^M^H^E^R
.cpu.inst"^M^H^F^R .cpu. etc ...
"
plz help to interpret Commmonitor output.
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Re: [gem5-users] How to send write requests directly from Ruby L1 controllers?
Thanks ! On Sun, Mar 15, 2020 at 6:48 PM Kevin Dong wrote: > Hi everyone, > > I've solved this problem, and this is a note for the future readers: > > Instead of directly calling queueMemoryWrite() within the L1 controller, > though the type of its parent class, AbstractController, is as same as that > of the directory controller. I found that it may be easier to implement by > creating a new class inherited from the class AbstractController, and > attach it to the L1 controller in the file MESI_Two_Level.py. Besides, its > memory port has to connect to the crossbar port in the file Ruby.py. > > Regards, > Kevin Dong Nai Jia > > > On Sun, Mar 15, 2020 at 2:59 PM Kevin Dong wrote: > >> Hi everyone, >> >> I am using Ruby cache with the MESI 2-level protocol. I found that only >> the directory controller can call queueMemoryWrite() to send memory write >> requests into the memory controller, but not the L1 caches directly. Should >> I add some extra interconnections for Ruby to connect between L1 caches and >> memory controller? Appreciate any help. Thanks! >> >> Regards, >> Kevin Dong >> > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] How to send write requests directly from Ruby L1 controllers?
Hi everyone, I've solved this problem, and this is a note for the future readers: Instead of directly calling queueMemoryWrite() within the L1 controller, though the type of its parent class, AbstractController, is as same as that of the directory controller. I found that it may be easier to implement by creating a new class inherited from the class AbstractController, and attach it to the L1 controller in the file MESI_Two_Level.py. Besides, its memory port has to connect to the crossbar port in the file Ruby.py. Regards, Kevin Dong Nai Jia On Sun, Mar 15, 2020 at 2:59 PM Kevin Dong wrote: > Hi everyone, > > I am using Ruby cache with the MESI 2-level protocol. I found that only > the directory controller can call queueMemoryWrite() to send memory write > requests into the memory controller, but not the L1 caches directly. Should > I add some extra interconnections for Ruby to connect between L1 caches and > memory controller? Appreciate any help. Thanks! > > Regards, > Kevin Dong > ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] modifying x86 macroops
Hi everyone, Am trying to implement a custom macroop, using the already build in microops in the x86 architecture, the problem that I am running into is that when we define a certain macroop we have to implement it in 3 different ways. i.e. one that only uses registers (_R), one that reads one of the operands from the memory (_M) using the address provided in the instruction and the last one uses the address of the instruction pointer to read the operand (_P). is it possible to override this condition and implement it for only one case, for example, for my custom macroop, which is to do a load operation, can i just have it implemented that it reads from memory to registers and not the other two cases? Also, although it is not possible for x86 instructions to move to a single "data entity" from one memory address to another if I wanted to do so, by combining a set of micro ops will it be possible? i would like to implement something like this: MOV_M_M. Will I able to achieve this? Any advise would be of much help Thanks. ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] How to send write requests directly from Ruby L1 controllers?
Hi everyone, I am using Ruby cache with the MESI 2-level protocol. I found that only the directory controller can call queueMemoryWrite() to send memory write requests into the memory controller, but not the L1 caches directly. Should I add some extra interconnections for Ruby to connect between L1 caches and memory controller? Appreciate any help. Thanks! Regards, Kevin Dong ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
