Re: [gem5-users] Problem passing a SimObject as Parameter

[Gabe Black]

Gabe

On Mon, Mar 23, 2020 at 2:05 PM Gabe Black  wrote:

> Hi Fransisco. When creating a parameter, you use Param.{object type name},
> when creating an instance of an object to fill a parameter, you use
> m5.objects.{etc}. Assuming you're doing that part right, then you need to
> make sure the name you're using in m5.objects.{etc} is correct. The first
> part should be the name of the file you passed to scons's SimObject(). For
> instance, if you have an object of type Bar in a file called Foo.py, you
> would import m5.objects.Foo.Bar. Frequently the name of the file and the
> name of the object are the same since it may be the primary or only object
> defined in that file, but it doesn't have to be.
>
> Gane
>
> On Mon, Mar 23, 2020 at 1:58 PM Muhammet Abdullah Soytürk <
> muhammetabdullahsoyt...@gmail.com> wrote:
>
>> Hi Francisco,
>>
>> Apparently gem5 cannot register your object to object list. With the
>> information you gave, I can only guess.
>>
>> - Did you register your object in the SConscript file?
>> - Did you recompile gem5.opt after you created your SimObject? While you
>> compiling the gem5 binary with scons build/RISCV/gem5.opt, you should be
>> able to see your object's name in the list of compiled objects.
>>
>> Best,
>> Muhammet
>>
>> Francisco Carlos , 23 Mar 2020 Pzt, 23:47
>> tarihinde şunu yazdı:
>>
>>> I am facing a problem in passing a simObject as Parameter to DerivO3Cpu
>>> simObject . I create a simObject named DtmObject and it appears when I run
>>> the command for listing the simObjects:
>>> ./build/RISCV/gem5.opt --list-sim-objects.
>>>
>>> However, when I try to import (from m5.objects.DtmObject import *) to
>>> use it as a parameter in other SimObject, in the O3CPU.py file to be more
>>> specific, I get the following error: ImportError: No module named DtmObject.
>>>
>>> Am I missing something? I followed the tutorial in the gem5 page (
>>> http://www.gem5.org/documentation/learning_gem5/part2/parameters/) and
>>> still, I can't figure out what is going on.
>>>
>>> Thanks in advance.
>>>
>>>
>>> --
>>> Francisco Carlos Silva Junior
>>> Phd Student at University of Brasilia
>>> ___
>>> gem5-users mailing list
>>> gem5-users@gem5.org
>>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>>
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>
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Re: [gem5-users] Problem passing a SimObject as Parameter

[Muhammet Abdullah Soytürk]

Hi Francisco,

Apparently gem5 cannot register your object to object list. With the
information you gave, I can only guess.

- Did you register your object in the SConscript file?
- Did you recompile gem5.opt after you created your SimObject? While you
compiling the gem5 binary with scons build/RISCV/gem5.opt, you should be
able to see your object's name in the list of compiled objects.

Best,
Muhammet

Francisco Carlos , 23 Mar 2020 Pzt, 23:47
tarihinde şunu yazdı:

> I am facing a problem in passing a simObject as Parameter to DerivO3Cpu
> simObject . I create a simObject named DtmObject and it appears when I run
> the command for listing the simObjects:
> ./build/RISCV/gem5.opt --list-sim-objects.
>
> However, when I try to import (from m5.objects.DtmObject import *) to use
> it as a parameter in other SimObject, in the O3CPU.py file to be more
> specific, I get the following error: ImportError: No module named DtmObject.
>
> Am I missing something? I followed the tutorial in the gem5 page (
> http://www.gem5.org/documentation/learning_gem5/part2/parameters/) and
> still, I can't figure out what is going on.
>
> Thanks in advance.
>
>
> --
> Francisco Carlos Silva Junior
> Phd Student at University of Brasilia
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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[gem5-users] Problem passing a SimObject as Parameter

[Francisco Carlos]

I am facing a problem in passing a simObject as Parameter to DerivO3Cpu 
simObject . I create a simObject named DtmObject and it appears when I run the 
command for listing the simObjects:
./build/RISCV/gem5.opt --list-sim-objects.

However, when I try to import (from m5.objects.DtmObject import *) to use it as 
a parameter in other SimObject, in the O3CPU.py file to be more specific, I get 
the following error: ImportError: No module named DtmObject.

Am I missing something? I followed the tutorial in the gem5 page 
(http://www.gem5.org/documentation/learning_gem5/part2/parameters/) and still, 
I can't figure out what is going on.

Thanks in advance.

--
Francisco Carlos Silva Junior
Phd Student at University of Brasilia
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Re: [gem5-users] Resources about the x86 microops in gem5

[Boris Shingarov]

> The microcode ISA I used I got mostly from an AMD patent from the K6 I  
> think, extrapolated

This is very interesting, I'd be eager to read that.  Do you approximately 
remember what terms were in the name of the patent, to search for?  AMD owns 
over eleven thousand patents...

-"gem5-users"  wrote: -
To: "gem5 users mailing list" 
From: "Gabe Black" 
Sent by: "gem5-users" 
Date: 03/22/2020 11:33PM
Subject: Re: [gem5-users] Resources about the x86 microops in gem5

I would actually suggest the AMD manuals instead of the Intel ones, although 
neither will tell you how instructions are decoded into microops since that's a 
proprietary implementation detail which varies from CPU to CPU. The microcode 
ISA I used I got mostly from an AMD patent from the K6 I think, extrapolated 
and expanded on slightly (particularly for floating point stuff) since then. If 
you want to see specifically how the instructions are implemented in microcode, 
you can look at src/arch/x86/isa/insts, organized roughly as they are in the 
AMD manuals, or at least as they were 10 or so years ago.

Gabe
On Sun, Mar 22, 2020 at 9:13 AM Abhishek Singh  
wrote:
Hi,

You can refer Intel manual it gives you complete explanation 
Also somewhere in the code I don’t remember exactly but there was a 
reference to particular intel manual
Also refer to older mail threads which tell about x86 instruction deciding 



On Sun, Mar 22, 2020 at 12:02 PM Anis Peysieux  wrote:
Hello,
 
 
 I wonder how the decomposition of macroops in microops were decided for 
 x86 in gem5 (for example, DIV in div1, div2, div2i, br, divq and divr). 
 Are there some resources that helped to know which microops are used in 
 real-world CPU?
 
 
 Thanks,
 
 
 Anis.
 
 -- 
 Anis Peysieux
 Doctorant - Équipe PACAP
 
 Centre de recherche INRIA Rennes - Bretagne Atlantique
 Bâtiment 12E, Bureau E301, Campus de Beaulieu,
 35042 Rennes Cedex, France
 
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Re: [gem5-users] Resources about the x86 microops in gem5

[Anis Peysieux]

Thank you Abhishek and Gabe.

Abhishek: The Intel manual doesn't give many more details than the 
number of micro-ops for some instructions so I'm not sure that it will 
be sufficient for what I am looking for.


Gabe: Thanks for the precisions. Do you remember which patent exactly?


Anis.

Le 23/03/2020 à 04:33, Gabe Black a écrit :
I would actually suggest the AMD manuals instead of the Intel ones, 
although neither will tell you how instructions are decoded into 
microops since that's a proprietary implementation detail which varies 
from CPU to CPU. The microcode ISA I used I got mostly from an AMD 
patent from the K6 I think, extrapolated and expanded on slightly 
(particularly for floating point stuff) since then. If you want to see 
specifically how the instructions are implemented in microcode, you 
can look at src/arch/x86/isa/insts, organized roughly as they are in 
the AMD manuals, or at least as they were 10 or so years ago.


Gabe

On Sun, Mar 22, 2020 at 9:13 AM Abhishek Singh 
> wrote:


Hi,

You can refer Intel manual it gives you complete explanation
Also somewhere in the code I don’t remember exactly but there was
a reference to particular intel manual
Also refer to older mail threads which tell about x86 instruction
deciding



On Sun, Mar 22, 2020 at 12:02 PM Anis Peysieux
mailto:anis.peysi...@inria.fr>> wrote:

Hello,


I wonder how the decomposition of macroops in microops were
decided for
x86 in gem5 (for example, DIV in div1, div2, div2i, br, divq
and divr).
Are there some resources that helped to know which microops
are used in
real-world CPU?


Thanks,


Anis.

-- 
Anis Peysieux

Doctorant - Équipe PACAP

Centre de recherche INRIA Rennes - Bretagne Atlantique
Bâtiment 12E, Bureau E301, Campus de Beaulieu,
35042 Rennes Cedex, France

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--
Anis Peysieux
Doctorant - Équipe PACAP

Centre de recherche INRIA Rennes - Bretagne Atlantique
Bâtiment 12E, Bureau E301, Campus de Beaulieu,
35042 Rennes Cedex, France

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