[gem5-users] dump the data in text file in gem5
Hi All, I made some changes on gem5 source code to collect the performance counters on a text file and I built the gem5 without any error. but I am not able to see the text file in the gem5 directory? Does anyone know how to dump the text file in gem5? any help would be appreciated. Thanks ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: Directly accessing certain regions of memory...
Hi Anuj, Method 1: If you already know the address range, for classic cache model, in the “src/mem/cache/base.cc” file see the recvTimingReq function. When the address lies in your desired address range turn the NonCacheable request flag high for that block. You can find information about this flag in “src/mem/request.hh” or “src/mem/packer.hh” file. Method 2(classic cache model): Search for allocateBlock function call in “src/mem/cache/base.cc” and then do not fill/allocate the desired address range blocks to be filled in cache. Please note that you may want to change the timing of access and response of those blocks depending on whether you want to add cache access timing to that block access or not On Fri, Jun 26, 2020 at 4:19 AM Anuj Falcon via gem5-users < gem5-users@gem5.org> wrote: > With the caches on, is there a way to define certain memory ranges for the > CPU to directly access memory (Not through the L1 or L2) ? Can somebody > provide any example on how to do that ? > > > -- > > - > J ANUJ > > - > ___ > gem5-users mailing list -- gem5-users@gem5.org > To unsubscribe send an email to gem5-users-le...@gem5.org > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: Accessing cache stats during execution
Hi, For now the standard stats file from gem5 using classic cache model does not have MPKI. So you need to declare the stats and you can access the declared stats in cpu, see the how cpu calls LSQ (or cache) objects and using that you can access the MPKI stat from CPU On Fri, Jun 26, 2020 at 4:20 PM Victor Kariofillis via gem5-users < gem5-users@gem5.org> wrote: > Hi, > > Building on top of my previous question and making it a bit more general. > Is there a way to access stats in a somewhat global manner? Let me explain > that with an example. During program execution, I need to know the number > of instructions committed and the MPKIs for L1 and L2. On every commit of > an instruction, I want to check the cache miss rates and see if and how > they changed. (All of these done from a module in the src/cpu directory.) > Do I have to connect the cpu and cache objects to my predictor via the > Python files? Or are the stats saved somewhere so that they are globally > accessible? > > Thanks, > Victor > > On Thu, 18 Jun 2020 at 17:38, Victor Kariofillis > wrote: > >> Hi, >> >> I want to run some tests for phase predictors using cache stats (e.g., L1 >> and L2 MPKIs). I need access to those stats during program execution, in >> order to both keep a log of these and make predictions based on them. What >> is the best way to access them? Would this be done through the cache.cc and >> cache.hh files? >> >> Also, since the phase predictor would be using cache stats is it best for >> it to be implemented in the src/mem/cache directory? >> >> Thanks, >> Victor >> > ___ > gem5-users mailing list -- gem5-users@gem5.org > To unsubscribe send an email to gem5-users-le...@gem5.org > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: Accessing cache stats during execution
Hi, Building on top of my previous question and making it a bit more general. Is there a way to access stats in a somewhat global manner? Let me explain that with an example. During program execution, I need to know the number of instructions committed and the MPKIs for L1 and L2. On every commit of an instruction, I want to check the cache miss rates and see if and how they changed. (All of these done from a module in the src/cpu directory.) Do I have to connect the cpu and cache objects to my predictor via the Python files? Or are the stats saved somewhere so that they are globally accessible? Thanks, Victor On Thu, 18 Jun 2020 at 17:38, Victor Kariofillis wrote: > Hi, > > I want to run some tests for phase predictors using cache stats (e.g., L1 > and L2 MPKIs). I need access to those stats during program execution, in > order to both keep a log of these and make predictions based on them. What > is the best way to access them? Would this be done through the cache.cc and > cache.hh files? > > Also, since the phase predictor would be using cache stats is it best for > it to be implemented in the src/mem/cache directory? > > Thanks, > Victor > ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Directly accessing certain regions of memory...
With the caches on, is there a way to define certain memory ranges for the CPU to directly access memory (Not through the L1 or L2) ? Can somebody provide any example on how to do that ? -- - J ANUJ - ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
