[gem5-users] Problem passing a cache object as parameter

[Saideepak Bejawada via gem5-users]

Hi all,

I was trying to pass BaseCache object as a parameter to TimingSimpleCPU. Here's 
what I did:
1. In TimingSimpleCPU.py, I have added a parameter name 'cache':
from Cache import BaseCache
cache = (BaseCache(),"Passing cache object")
2. I have declared a pointer for this cache object in cpu/simple/timing.hh
   #include "mem/cache/base.hh"
   BaseCache *Cache;
3. In cpu/simple/timing.cc, I have tried to initialize Cache
   Cache(p->cache)
I am getting an attribute error which says ''Class TimingSimpleCPU has no 
parameter 'cache':" even though I have added cache as an option to the .py 
file. Also, I want to know if we can pass an object to any other object as a 
parameter (or) are there any restrictions?  

Thanks,
Saideepak.
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[gem5-users] Re: Address translation in cache

[Saideepak Bejawada via gem5-users]

Alright. Thanks a lot Eliot.
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[gem5-users] Re: gem5 functional mode simulation

[Abhishek Singh via gem5-users]

Hi Yuan,

You can use AtomicSimple CPU, it’s an in order CPU
You can find more information here
https://www.gem5.org//documentation/general_docs/cpu_models/SimpleCPU


On Thu, Jul 2, 2020 at 5:23 PM Shougang Yuan via gem5-users <
gem5-users@gem5.org> wrote:

> Hi, All,
>
> I want to use the functional simulator of gem5 to verify the results of
> some program. But I did not find a  lot of information online about the
> functional mode. So how can we use functional mode in gem5?
>
> Best regards.
> Yuan
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[gem5-users] How to check ...

[Anuj Falcon via gem5-users]

How to know if my CPU model qualifies to be upstreamed with the rest of the
CPU models in gem 5 ?
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[gem5-users] gem5 functional mode simulation

[Shougang Yuan via gem5-users]

Hi, All,

I want to use the functional simulator of gem5 to verify the results of
some program. But I did not find a  lot of information online about the
functional mode. So how can we use functional mode in gem5?

Best regards.
Yuan
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[gem5-users] Re: Address translation in cache

[Eliot Moss via gem5-users]

On 7/1/2020 10:53 PM, Saideepak Bejawada via gem5-users wrote:

Thanks. I will try that. How can I add data TLB to the cache? Is it possible 
using CacheConfig.py?


Add?  Presumably a data TLB already exists. Do you meanL "How do I access the data TLB?"  If so, 
then the sort of thing that works in my code is:


SimObject *obj = SimObject::find("system.cpu.dstage2_mmu.stage2_tlb");
ArmISA::TLB *tlb = (ArmISA::TLB *)(obj);

The specific type may vary of course, as well as the specific name of the 
component, but the
name you can see in your config.ini file output by a simulation run, and it 
should not be
too hard to discover the type.\ (e.g., X86ISA::TLB).  These will have page 
walker classes
associated with them.

Anyway, as you initialize your module you can find and use these connections.  
Not as
general perhaps as doing stuff in your .py files, but maybe easier?

Best wishes - EM
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[gem5-users] Re: How to track the register values of instructions.

[Jason Lowe-Power via gem5-users]

Hi Yuan,

You might find the Exec and ExecAll debug flags useful.

Cheers,
Jason

On Thu, Jul 2, 2020 at 7:48 AM Shougang Yuan via gem5-users <
gem5-users@gem5.org> wrote:

> Hi, All,
>
> I am trying to modify the gem5 code and suffer some memory corruption
> bugs. I want to look at more details of each instruction. So is there a way
> to dump out the register value of each instruction.
>
> Best regards.
> Yuan
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[gem5-users] How to track the register values of instructions.

[Shougang Yuan via gem5-users]

Hi, All,

I am trying to modify the gem5 code and suffer some memory corruption bugs.
I want to look at more details of each instruction. So is there a way to
dump out the register value of each instruction.

Best regards.
Yuan
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