[gem5-users] Gem5 Full System Mode - Memory Allocation Issue

[Hasan, S M Shamimul via gem5-users]

Hello,

I have two C programs. In my first C program I am assigning 2GB memory space to 
an integer array and in my second C program I am assigning 4GB memory space to 
another integer array. I am assigning memory space via C's malloc() function. 
Both my first and second programs work fine on my Linux laptop (with 16GB 
memory).

I have executed both first and second programs inside Gem5 in Full System (FS) 
mode. I observed that the first program was executed properly in Gem5. However, 
for the second program, I am getting the "Out of storage: Cannot allocate 
memory" message from the Gem5. Do you know why I am getting the above message? 
How to simulate more than 2GB memory in the Gem5 Full System mode? Please let 
me know.

Thanks a lot.

Sincerely,
S.M.Shamimul Hasan
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[gem5-users] Unable to find destination for [0x40000008:0x4000000c] on system.iobus

[Liyichao via gem5-users]

Hi All:

I just add a ethernet object in dist-bigLITTLE.py on VEXPRESS_GEM5_V1, but 
AddRange debug print “fatal: Unable to find destination for 
[0x4008:0x400c] on system.iobus

So how to config the mem range in RealView.py or in any other code ?
”

The function of create Ethernet is :
def addEthernet(system, options):
# create NIC
dev = IGbE_e1000()
system.attach_pci(dev)
system.ethernet = dev

# create distributed ethernet link
system.etherlink = DistEtherLink(speed = options.ethernet_linkspeed,
 delay = options.ethernet_linkdelay,
 dist_rank = options.dist_rank,
 dist_size = options.dist_size,
 server_name = options.dist_server_name,
 server_port = options.dist_server_port,
 sync_start = options.dist_sync_start,
 sync_repeat = options.dist_sync_repeat)
system.etherlink.int0 = Parent.system.ethernet.interface
if options.etherdump:
system.etherdump = EtherDump(file=options.etherdump)
system.etherlink.dump = system.etherdump


root@ubuntu-kunpeng920-1:/home/l00515693/gem5_repo/gem5/rundir# tail -f log.0
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x8008
info: Loading DTB file: 
/home/l00515693/gem5_repo/gem5/rundir/m5out.0/system.dtb at address 0x8800
  0: system.etherlink: DistEtherLink::startup() called
  0: global: DistIface::startup() started
  0: global: DistIface::startup() done
info: Dist sync scheduled at 52000 and repeats 1000
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
info: Entering event queue @ 0.  Starting simulation...
warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0
warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
194293121000: system.iobus: Received range change from slave port 
system.pci_vio_block.pio
194293121000: system.iobus: Adding range [0x2f001000:0x2f001020] for id 16
194293121000: system.iobus: Aggregating address ranges
194293121000: system.iobus: -- Adding range [0xc00:0x1000]
194293121000: system.iobus: -- Adding range [0x1000:0x102c]
194293121000: system.iobus: -- Adding range [0x1c01:0x1c0100d4]
194293121000: system.iobus: -- Adding range [0x1c06:0x1c061000]
194293121000: system.iobus: -- Adding range [0x1c07:0x1c071000]
194293121000: system.iobus: -- Adding range [0x1c09:0x1c091000]
194293121000: system.iobus: -- Adding range [0x1c0a:0x1c0a1000]
194293121000: system.iobus: -- Adding range [0x1c0b:0x1c0b1000]
194293121000: system.iobus: -- Adding range [0x1c0c:0x1c0c1000]
194293121000: system.iobus: -- Adding range [0x1c0f:0x1c0f1000]
194293121000: system.iobus: -- Adding range [0x1c10:0x1c101000]
194293121000: system.iobus: -- Adding range [0x1c13:0x1c131000]
194293121000: system.iobus: -- Adding range [0x1c14:0x1c141000]
194293121000: system.iobus: -- Adding range [0x1c17:0x1c171000]
194293121000: system.iobus: -- Adding range [0x2f001000:0x2f001020]
194293121000: system.iobus: -- Adding range [0x3000:0x4000]
194293121000: system.iobus: -- Adding range [0x8000:0x1]
fatal: Unable to find destination for [0x4008:0x400c] on system.iobus
Memory Usage: 2636564 KBytes


李翼超（Charlie）

华为技术有限公司 Huawei Technologies Co., Ltd.
[Company_logo]
部门：计算系统与组件开发部 [云与计算BG]
手　　机：15858232899
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[gem5-users] Re: How to set ROI in the program running in FS

[Hoa Nguyen via gem5-users]

Hi Siqing,

You can find the PARSEC ROI example mentioned in the webpage is here,
https://github.com/darchr/parsec-benchmark/commits/gem5-20-annotations

gem5-resources (https://gem5.googlesource.com/public/gem5-resources/)
has the documentation of setting up full system gem5 experiments with
several benchmarks including PARSEC benchmark, which also uses m5
annotations for ROI.

Regards,
Hoa Nguyen

On 11/3/20, -17 via gem5-users  wrote:
> Hi all：
> What I want to do now is to run a program in FS mode and observe the
> statistical differences among different code segments.
> I know that in SE mode, this work can be easily done with M5ops, for
> example, add a code:
> m5_dump_reset_stats(0,0)
> In the FS mode, M5ops can be input through the shell, for example, to exit
> the simulation:
> m5 exit
> And build checkpoint:
> m5 checkpoint
>
>
> So, for a program running in FS, obviously I cannot use the shell as input.
> In this case, how can I ignore the initialization of the program and some
> other stages and only get the statistics of the Region of Interest?
> This webpage introduces the configuration of ROI in PARSEC, but it seems not
> specific enough. Can anyone have any clear
> guidance?https://www.gem5.org/documentation/general_docs/checkpoints/
>
>
> /**/
>
> NUDT 
> Siqing Fu
>
>
> 
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[gem5-users] Re: How to enable dist-gem5 on GEM5 20.0.0.3 on ARM64

[Bobby Bruce via gem5-users]

Hey Liyichao,

I'm sorry to somewhat avoid answering the question (I don't know enough
about dist-gem5 to comment), but dist-gem5 is grossly under-tested and
hasn't had any decent maintenance in a while, so it really comes with no
guarantees, and it wouldn't surprise me at all if it doesn't work exactly
as intended.

In short, I'd proceed with caution. You may need to play around with the
code to get what you want.

Kind regards,
Bobby
--
Dr. Bobby R. Bruce
Room 2235,
Kemper Hall, UC Davis
Davis,
CA, 95616

web: https://www.bobbybruce.net


On Fri, Oct 30, 2020 at 11:14 PM Liyichao via gem5-users <
gem5-users@gem5.org> wrote:

> Hi All:
>
>
>
>  Any one use dist-gem5 to bootup successfully on GEM5 20.0.0.3 on
> ARM64?
>
>
>
>  In dist-gem5 website, the example only shows for arm32, and the
> kernel/img/boot_emm/vexpress_emm is just matched for arm32.
>
>
>
>
>
>  I want to use the latest 4.14 kernel and
> aarch64-ubuntu-trusty-headless.img from GEM5 website with KVM bootup, how
> to enable it?
>
>
> --
>
> 李翼超（Charlie）
>
>
>
> 华为技术有限公司 Huawei Technologies Co., Ltd.
>
> [image: Company_logo]
>
> 部门：计算系统与组件开发部 [云与计算BG]
>
> 手 机：15858232899
> 电子邮件：liyic...@huawei.com
>
> 地址：中国(China)-杭州(Hangzhou)-滨江区江淑路360号华为杭州研发中心Z4# [3-A06]
> --
>
>  本邮件及其附件含有华为公司的保密信息，仅限于发送给上面地址中列出的个人或群组。禁
> 止任何其他人以任何形式使用（包括但不限于全部或部分地泄露、复制、或散发）本邮件中
> 的信息。如果您错收了本邮件，请您立即电话或邮件通知发件人并删除本邮件！
> This e-mail and its attachments contain confidential information from
> HUAWEI, which
> is intended only for the person or entity whose address is listed above.
> Any use of the
> information contained herein in any way (including, but not limited to,
> total or partial
> disclosure, reproduction, or dissemination) by persons other than the
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> recipient(s) is prohibited. If you receive this e-mail in error, please
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[gem5-users] Re: Why are there still so many decoding-related operations when fetching instructions into the instruction queue?

[Ayaz Akram via gem5-users]

Hi Yujiecui,

The fetch stage in O3CPU fetches cache lines from instruction cache and
also calls ISA specific decoder implementation to decode the raw bytes into
instructions and access the corresponding micro-ops for these instructions
(In other words, fetch stage outputs the micrco-ops). That's why you are
seeing all these decode calls. As far as I understand (specifically for
x86),  the functions you are referring to will decode a machine instruction
corresponding to the given PC, check if the instruction exist across the
cache block boundary and fetch more bytes (i.e. next cache block) etc.  As
far as Rom is concerned, I think it holds the micro-ops.

I will suggest you have a look at the following page:

http://www.m5sim.org/X86_Instruction_decoding

and decoder implementation for some ISA e.g. src/arch/x86/decoder.hh

-Ayaz

On Tue, Nov 3, 2020 at 4:52 AM yujiecui--- via gem5-users <
gem5-users@gem5.org> wrote:

> In the fetch function in the src/cpu/O3/fetch.impl file, when fetching
> instructions to the fetch queue, I saw some operations on the decoder,
> which made me very confused. For example, decoder[tid]->decode(thisPC),
> decoder[tid]->instReady(), decoder[tid]->needMoreBytes(),
> decoder[tid]->moreBytes(thisPC, fetchAddr, inst). Why are there so many
> decoding operations when fetching instructions into the fetch queue? What
> is the role of decoder[tid] here? What does needMoreBytes() do?
>
> Still fetch function in the src/cpu/O3/fetch.impl file, I saw some
> RomMicroPC. I want to know what kind of instructions are in rom?
>
> I stepped through it many times, but I still have trouble understanding.
> All related answers are very welcome. Thanks
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[gem5-users] Ruby - Does SimpleNetwork.setup_bufers() instanciate to many buffers?

[gabriel.busnot--- via gem5-users]

Hi,

In the file SimpleNetwork.py at line 67 (version v20.1.0.0), it is checked that 
the internal side of the network link is connected to ONE OF the routers before 
instantiating a buffer for that link:
if link.int_node in self.routers:

This action is done in a loop on the network routers at line 55.
Shouldn't the test be:
if link.int_node == router:


The binary "threads" under "tests/test-progs/threads/bin/X86/linux/" runs just 
fine w/ and w/o this modification but I am not sure about which version is the 
correct one.

Thanks,
Gabriel
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[gem5-users] Re: How to solve problems when building M5ops

[Hoa Nguyen via gem5-users]

Hi Siqing,

It should be "x86" with a lowercase x rather than "X86".

Regards,
Hoa Nguyen

On Tue, Nov 3, 2020, 12:52 AM -17 via gem5-users 
wrote:

> Hi all：
>
> About a few months ago, I followed the guidelines of this link to
> successfully build M5ops：
>
> https://www.gem5.org/documentation/general_docs/m5ops/
>
> Now I am still using gem5-20.0 and have not updated to the new
> version, but when I run this command again:
>
> scons build/X86/out/m5
>
> I received a bug report, the following is the complete content:
>
> //
> Warning: Your compiler doesn't support incremental linking and lto at the
> same
>  time, so lto is being disabled. To force lto on anyway, use the
>  --force-lto option. That will disable partial linking.
> Info: Using Python config: python2.7-config
> Checking for C header file Python.h... (cached) yes
> Checking for C library python2.7... (cached) yes
> Checking for C library pthread... (cached) yes
> Checking for C library dl... (cached) yes
> Checking for C library util... (cached) yes
> Checking for C library m... (cached) yes
> Checking for accept(0,0,0) in C++ library None... (cached) yes
> Checking for zlibVersion() in C++ library z... (cached) yes
> Checking for GOOGLE_PROTOBUF_VERIFY_VERSION in C++ library protobuf...
> (cached) yes
> Checking for C header file valgrind/valgrind.h... (cached) no
> Checking for clock_nanosleep(0,0,NULL,NULL) in C library None... (cached)
> yes
> Checking for timer_create(CLOCK_MONOTONIC, NULL, NULL) in C library
> None... (cached) no
> Checking for timer_create(CLOCK_MONOTONIC, NULL, NULL) in C library rt...
> (cached) yes
> Checking for C library tcmalloc... (cached) yes
> Checking for char temp; backtrace_symbols_fd((void*), 0, 0) in C
> library None... (cached) yes
> Checking for C header file fenv.h... (cached) yes
> Checking for C header file png.h... (cached) no
> Warning: Header file  not found.
>  This host has no libpng library.
>  Disabling support for PNG framebuffers.
> Checking for C header file linux/kvm.h... (cached) yes
> Checking for C header file linux/if_tun.h... (cached) yes
> Checking size of struct kvm_xsave ... (cached) yes
> Checking for member exclude_host in struct perf_event_attr...(cached) yes
> Checking for hdf5-serial using pkg-config... yes
> Checking for H5Fcreate("", 0, 0, 0) in C library hdf5... (cached) yes
> Checking for H5::H5File("", 0) in C++ library hdf5_cpp... (cached) yes
> Checking whether __i386__ is declared... (cached) no
> Checking whether __x86_64__ is declared... (cached) yes
> Building in /home/fusiqing/GEM5/gem5/build/X86
> Using saved variables file /home/fusiqing/GEM5/gem5/build/variables/X86
> warn: CheckedInt already exists in allParams. This may be caused by the
> Python 2.7 compatibility layer.
> warn: Enum already exists in allParams. This may be caused by the Python
> 2.7 compatibility layer.
> warn: ScopedEnum already exists in allParams. This may be caused by the
> Python 2.7 compatibility layer.
> scons: done reading SConscript files.
> scons: Building targets ...
> scons: *** Do not know how to make File target `build/X86/out/m5'
> (/home/fusiqing/GEM5/gem5/build/X86/out/m5).  Stop.
> scons: building terminated because of errors.
> *** Summary of Warnings ***
> Warning: Your compiler doesn't support incremental linking and lto at the
> same
>  time, so lto is being disabled. To force lto on anyway, use the
>  --force-lto option. That will disable partial linking.
> Warning: Header file  not found.
>  This host has no libpng library.
>  Disabling support for PNG framebuffers.
> /*/
> I want to know if anyone has encountered such a situation.
> Thanks for help.
>
> --
> /**/
>
> NUDTSiqing Fu
>
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[gem5-users] Re: Multi-process shared memory in SE mode

[Jason Lowe-Power via gem5-users]

Hi Pedro,

No, I don't have any specific pointers beyond the code in src/sim/. One
quick note: on develop there is something in flux about how syscalls work.
There's been some recent changes from Gabe to the "Workload" and the
syscall dispatch. I have to admit I don't understand them, but it might be
worth looking into before diving in.

Cheers,
Jason

On Tue, Oct 27, 2020 at 1:39 PM Pedro Becker via gem5-users <
gem5-users@gem5.org> wrote:

> Hi Jason, thanks for the feedback!
>
> About your suggestions:
> - Yes, pthreads worked correctly for the simple examples I tried. But
> still has this drawback of shared memory I was trying to avoid..
> - Do you have any pointers on implementing syscalls on gem5? It could be
> anything I could take as a 'guide' to get started with it since I'm not
> sure about how hard or easy that might be. I'll take a look since it might
> be a good solution for the short-term goals of making multi-processing work.
>
> Again, thank you.
>
> Best,
> Pedro.
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[gem5-users] Re: How to add new instructions for gem5?

[Hoa Nguyen via gem5-users]

Hi,

Though I'm not sure how to add the cache clearing instruction specifically,
those are a few examples that new instructions are added,

https://gem5-review.googlesource.com/c/public/gem5/+/26123

https://gem5-review.googlesource.com/c/public/gem5/+/23262

https://gem5-review.googlesource.com/c/public/gem5/+/26984

Regards,
Hoa Nguyen

On Mon, Oct 26, 2020, 11:53 PM 1258289086--- via gem5-users <
gem5-users@gem5.org> wrote:

> How to add new instructions for gem5? For example, the cflush command was
> not implemented in the old version. But I have done some work on the old
> version of gem5. I need to use the cflush command now. I know I should
> design against the existing instructions. But I am worried that something
> will be missed. Has anyone done a similar tutorial? , Or can I list the
> places I need to modify to prevent me from missing some of the modified
> locations.
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[gem5-users] Re: Configure multi-bank cache in ruby ​mode with MESI coherence protocol

[Jason Lowe-Power via gem5-users]

Hello,

(1) Yes, I believe so.
(2) I thought MOESI_hammer was annotated, but it doesn't look like
(huh...). However, AMD MOESI Base is annotated. See all of the transition
in the core-pair file, for instance:
https://gem5.googlesource.com/public/gem5/+/refs/tags/v20.1.0.0/src/mem/ruby/protocol/MOESI_AMD_Base-CorePair.sm#2480

Cheers,
Jason

On Thu, Oct 29, 2020 at 5:54 AM zhen bang via gem5-users <
gem5-users@gem5.org> wrote:

> Hello Jason:
> (1) Can I use resource stalls to simulate the multi-bank implementation of
> L0 and L1, and  model L2 a distributed cache? By the way, the
> implementation of L2 multi-bank in gem5 is not interleaving (multi-bank),
> right?
> (2) "add annotations to the transitions in the L0 and L1 cache", I am not
> sure how this should be done, could you give me an example?
>
> Looking forward to your reply.
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[gem5-users] Re: What is the role of TimeBuffer in gem5?

[Daniel Gerzhoy via gem5-users]

Hey guys,

I just interacted with it to fix a bug in the O3 cpu. Seems to me
a Timebuffer is how the pipeline stages communicate with each other.
Looks like a wrapper for the datastructures that
communicate between different stages, as "wires."
Each wire within a time buffer communicates between different stages, some
backwards, some forwards, each with a specific latency based on the config.
Every tick you advance() each of the buffers to propagate signals between
the stages.
When the data reaches its endpoint the timebuffer takes care of getting rid
of it.

In O3 its a little confusing because the timeBuffer object which takes care
of backwards communication is of type TimeBuffer ,
and there are the fetchQueue decodeQueue etc which are of type TimeBuffer
as well.

Hope this helps,

Dan

On Tue, Nov 3, 2020 at 11:49 AM Jason Lowe-Power via gem5-users <
gem5-users@gem5.org> wrote:

> Hello,
>
> I've been using gem5 for ~10 years, and this is the first time I've ever
> seen this code :D. It  was committed 14 years ago, and it hasn't been
> touched since.
>
> It looks to me like it's used for gathering statistics about the activity
> of different CPU pipeline stages. However, I *know* it's not actively
> maintained, so I would guess that it doesn't work anymore. As far as what
> it's doing, I think the comment in activity.hh is probably the best
> explanation:
>
> http://doxygen.gem5.org/release/current/classActivityRecorder.html#details
>
> Cheers,
> Jason
>
> On Tue, Nov 3, 2020 at 4:49 AM yujiecui--- via gem5-users <
> gem5-users@gem5.org> wrote:
>
>> What does TimeBuffer in gem5 do? I read its source code, but there are no
>> comments and it is not easy to understand operations. I saw in the tick
>> function in the cpu.cc file that every tick() will proceed
>> timeBuffer.advance();
>> fetchQueue.advance();
>> decodeQueue.advance();
>> renameQueue.advance();
>> iewQueue.advance();
>> But the function of advance is
>> advance()
>> {
>>  if (++base >= size)
>> base = 0;
>> int ptr = base + future;
>> if (ptr >= (int)size)
>> ptr -= size;
>> (reinterpret_cast(index[ptr]))->~T();
>> std::memset(index[ptr], 0, sizeof(T));
>> new (index[ptr]) T;
>> }
>> Just looking at the source code, this is really hard to understand. I
>> think if someone can tell me what it is doing? I think it’s easier for me
>> to understand this code
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[gem5-users] Re: What is the role of TimeBuffer in gem5?

[Jason Lowe-Power via gem5-users]

Hello,

I've been using gem5 for ~10 years, and this is the first time I've ever
seen this code :D. It  was committed 14 years ago, and it hasn't been
touched since.

It looks to me like it's used for gathering statistics about the activity
of different CPU pipeline stages. However, I *know* it's not actively
maintained, so I would guess that it doesn't work anymore. As far as what
it's doing, I think the comment in activity.hh is probably the best
explanation:

http://doxygen.gem5.org/release/current/classActivityRecorder.html#details

Cheers,
Jason

On Tue, Nov 3, 2020 at 4:49 AM yujiecui--- via gem5-users <
gem5-users@gem5.org> wrote:

> What does TimeBuffer in gem5 do? I read its source code, but there are no
> comments and it is not easy to understand operations. I saw in the tick
> function in the cpu.cc file that every tick() will proceed
> timeBuffer.advance();
> fetchQueue.advance();
> decodeQueue.advance();
> renameQueue.advance();
> iewQueue.advance();
> But the function of advance is
> advance()
> {
>  if (++base >= size)
> base = 0;
> int ptr = base + future;
> if (ptr >= (int)size)
> ptr -= size;
> (reinterpret_cast(index[ptr]))->~T();
> std::memset(index[ptr], 0, sizeof(T));
> new (index[ptr]) T;
> }
> Just looking at the source code, this is really hard to understand. I
> think if someone can tell me what it is doing? I think it’s easier for me
> to understand this code
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[gem5-users] Why are there still so many decoding-related operations when fetching instructions into the instruction queue?

[yujiecui--- via gem5-users]

In the fetch function in the src/cpu/O3/fetch.impl file, when fetching 
instructions to the fetch queue, I saw some operations on the decoder, which 
made me very confused. For example, decoder[tid]->decode(thisPC), 
decoder[tid]->instReady(), decoder[tid]->needMoreBytes(), 
decoder[tid]->moreBytes(thisPC, fetchAddr, inst). Why are there so many 
decoding operations when fetching instructions into the fetch queue? What is 
the role of decoder[tid] here? What does needMoreBytes() do?

Still fetch function in the src/cpu/O3/fetch.impl file, I saw some RomMicroPC. 
I want to know what kind of instructions are in rom?

I stepped through it many times, but I still have trouble understanding. All 
related answers are very welcome. Thanks
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[gem5-users] What is the role of TimeBuffer in gem5?

[yujiecui--- via gem5-users]

What does TimeBuffer in gem5 do? I read its source code, but there are no 
comments and it is not easy to understand operations. I saw in the tick 
function in the cpu.cc file that every tick() will proceed
timeBuffer.advance();
fetchQueue.advance();
decodeQueue.advance();
renameQueue.advance();
iewQueue.advance();
But the function of advance is
advance()
{
 if (++base >= size)
base = 0;
int ptr = base + future;
if (ptr >= (int)size)
ptr -= size;
(reinterpret_cast(index[ptr]))->~T();
std::memset(index[ptr], 0, sizeof(T));
new (index[ptr]) T;
}
Just looking at the source code, this is really hard to understand. I think if 
someone can tell me what it is doing? I think it’s easier for me to understand 
this code
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[gem5-users] Re: Introducing myself

[Giacomo Travaglini via gem5-users]

Hi Gabriel,

Welcome on board!

Giacomo

-Original Message-
From: gabriel.busnot--- via gem5-users 
Sent: 03 November 2020 10:03
To: gem5-users@gem5.org
Cc: gabriel.bus...@arteris.com
Subject: [gem5-users] Introducing myself

Hi Gem5 community,

I want to introduce myself as a new Gem5 user.
My name is Gabriel Busnot and I work at Arteris IP, a major network-on-chip IP 
provider.
I am working on a new model for performance evaluation of architectural 
changes, coherence protocol testing and quality-of-service experiments.
We plan on using ruby with the O3 ARM processor model but are still evaluating 
the available options.

Personally, I come from the SystemC community where I was doing research on 
parallel simulation of loosely-timed TLM models.
Thus, I am relatively at ease with the core concepts of gem5 but I will 
definitely appreciate additional insights from you in a close future ;)

Cheers,
Gabriel
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[gem5-users] How to set ROI in the program running in FS

[-17 via gem5-users]

Hi all??
What I want to do now is to run a program in FS mode and observe the 
statistical differences among different code segments.
I know that in SE mode, this work can be easily done with M5ops, for example, 
add a code:
m5_dump_reset_stats(0,0)
In the FS mode, M5ops can be input through the shell, for example, to exit the 
simulation:
m5 exit
And build checkpoint:
m5 checkpoint


So, for a program running in FS, obviously I cannot use the shell as input. In 
this case, how can I ignore the initialization of the program and some other 
stages and only get the statistics of the Region of Interest?
This webpage introduces the configuration of ROI in PARSEC, but it seems not 
specific enough. Can anyone have any clear 
guidance?https://www.gem5.org/documentation/general_docs/checkpoints/


/**/

NUDT  
Siqing Fu


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[gem5-users] Introducing myself

[gabriel.busnot--- via gem5-users]

Hi Gem5 community,

I want to introduce myself as a new Gem5 user.
My name is Gabriel Busnot and I work at Arteris IP, a major network-on-chip IP 
provider.
I am working on a new model for performance evaluation of architectural 
changes, coherence protocol testing and quality-of-service experiments.
We plan on using ruby with the O3 ARM processor model but are still evaluating 
the available options.

Personally, I come from the SystemC community where I was doing research on 
parallel simulation of loosely-timed TLM models.
Thus, I am relatively at ease with the core concepts of gem5 but I will 
definitely appreciate additional insights from you in a close future ;)

Cheers,
Gabriel
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[gem5-users] How to solve problems when building M5ops

[-17 via gem5-users]

Hi all??


  About a few months ago, I followed the guidelines of this link to 
successfully build M5ops??


https://www.gem5.org/documentation/general_docs/m5ops/


  Now I am still using gem5-20.0 and have not updated to the new 
version, but when I run this command again:


scons build/X86/out/m5


  I received a bug report, the following is the complete content:


//
Warning: Your compiler doesn't support incremental linking and lto at the same
time, so lto is being disabled. To force lto 
on anyway, use the
--force-lto option. That will disable partial 
linking.
Info: Using Python config: python2.7-config
Checking for C header file Python.h... (cached) yes
Checking for C library python2.7... (cached) yes
Checking for C library pthread... (cached) yes
Checking for C library dl... (cached) yes
Checking for C library util... (cached) yes
Checking for C library m... (cached) yes
Checking for accept(0,0,0) in C++ library None... (cached) yes
Checking for zlibVersion() in C++ library z... (cached) yes
Checking for GOOGLE_PROTOBUF_VERIFY_VERSION in C++ library protobuf... (cached) 
yes
Checking for C header file valgrind/valgrind.h... (cached) no
Checking for clock_nanosleep(0,0,NULL,NULL) in C library None... (cached) yes
Checking for timer_create(CLOCK_MONOTONIC, NULL, NULL) in C library None... 
(cached) no
Checking for timer_create(CLOCK_MONOTONIC, NULL, NULL) in C library rt... 
(cached) yes
Checking for C library tcmalloc... (cached) yes
Checking for char temp; backtrace_symbols_fd((void*)temp, 0, 0) in C 
library None... (cached) yes
Checking for C header file fenv.h... (cached) yes
Checking for C header file png.h... (cached) no
Warning: Header file ___
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