[gem5-users] Re: Fail to Boot Multicore Arm System with KVM CPU
Hi Giacomo, Just want to follow up a bit on this, any suggestions on what could be causing the kernel failing to bring up all those secondary CPUs? Best, Wenqi > On Apr 1, 2021, at 16:53, Wenqi Yin wrote: > > HI Giacomo, > > I add that line of code you pointed me to to the fs_bigLittle.py, now I can > boot into the terminal, however, the kernel cannot bring all but one cpu > online. It’s also a bit strange in the sense that I specify ‘-smp 12’, and > inside the guest when I check lscpu, it shows total of 13 CPUs and only cpu0 > is online, cpu1-12 are offline. > > I tried both the stock kernel as well as compiling kernel myself following > your suggestions from earlier email, both have the same issue. Do you have > any suggestions on what could be causing the problem? > > Best, > Wenqi > >> On Apr 1, 2021, at 03:28, Giacomo Travaglini >> wrote: >> >> Yes, apologies, I forgot to mention that. >> As your host is likely using a GICv3 interrupt controller, you need to >> entirely emulate the GICv2 and Generic Timer in userspace (gem5). >> >> This is done via the simulate_gic (as you have already done) and by removing >> the system register interface info from the DTB node >> >> Here's an example: >> >> https://github.com/gem5/gem5/blob/stable/tests/gem5/configs/arm_generic.py#L99 >> >> Let me know if this works >> >> Kind Regards >> >> Giacomo >> >> >>> -Original Message- >>> From: wq...@utexas.edu >>> Sent: 31 March 2021 19:18 >>> To: Giacomo Travaglini ; gem5 users mailing >>> list ; wq...@utexas.edu >>> Subject: Re: [gem5-users] Fail to Boot Multicore Arm System with KVM CPU >>> >>> Hi Giacomo, >>> >>> Thanks for your reply. I tried the solution you suggested, but seems there >>> are still problems. Just make sure I understood correctly, I specified the >>> 'machine-type' as 'VExpress_GEM5_V1' and in the VExpress_GEM5_V1_Base >>> class's definition (src/dev/arm/RealView.py), when instantiating the gic, I >>> use: >>> >>> gic = kvm_gicv2_class(dist_addr=0x2c001000, cpu_addr=0x2c002000, >>> it_lines=512, gem5_extensions=True) >>> >>> The kvm_gicv2_class will be resolved as MuxingKvmGic, which inherent from >>> GicV2 class. To make sure the change applied, I also change the default >>> value >>> of gem5_extensions from False to True in the GicV2 class's definition >>> (src/dev/arm/Gic.py). After rebuild, when starting gem5 there will be a >>> panic >>> says "KVM: failed to create virtual CPU" (from /src/cpu/kvm/vm.cc, when >>> using ioctl to create vcpu) >>> >>> Another thing I tried is to set the "simulate_gic" of the MuxingKvmGic class >>> from False to True, this seems help me get around the vCPU creation failure, >>> however, at some point it faces an assertion failure of: >>> >>> gem5.opt: build/ARM/sim/eventq.hh:763: void >>> EventQueue::schedule(Event*, Tick, bool): Assertion `when >= getCurTick()' >>> failed. >>> Program aborted at tick 112565277000 >>> >>> Best, >>> >>> Wenqi >>> >>> On 3/31/21 7:57 AM, Giacomo Travaglini wrote: Hi Wenqi, First of all thanks for the detailed explanation of your problem. > -Original Message- > From: wqyin--- via gem5-users > Sent: 30 March 2021 22:47 > To: gem5-users@gem5.org; wq...@utexas.edu > Cc: wq...@utexas.edu > Subject: [gem5-users] Fail to Boot Multicore Arm System with KVM CPU > > Hello all, > > I am trying to model a multicore arm64 system with the > example/arm/fs_bigLittle.py using kvm cpu. However, when I specify "- > machine-type VExpress_Gem5_V2_XXX", the kernel panic during booting, > giving an error message of: > > [0.00] GICv3: Distributor has Range Selector support [ > 0.00] > GICv3: no VLPI support, direct LPI support [0.00] ITS [mem > 0x2e01-0x2e02] [0.00] ITS@0x2e01: allocated > 262144 Devices > @fc60 (flat, esz 8, psz 64K, shr 1) > [0.00] ITS@0x2e01: allocated 8192 Interrupt >>> Collections > @fc46 (flat, esz 8, psz 64K, shr 1) [0.00] GIC: using LPI > property > table @0xfc47 [0.00] ITS: Allocated 1792 chunks for >>> LPIs > [0.00] GICv3: CPU0: found redistributor 0 region > 0:0x2c01 > [0.00] CPU0: using LPI pending table @0xfc48 >>> [0.00] > GIC: using cache flushing for LPI property table [0.00] GICv3: > GIC: > unable to set SRE (disabled at EL2), panic ahead [0.00] > >>> [ cut > here ] [0.00] kernel BUG at /work/gem5- > scripts/submodules/linux/arch/arm64/kernel/entry.S:602! > [0.00] Internal error: Oops - BUG: 0 [#1] PREEMPT SMP [ > 0.00] > Modules linked in: > [0.00] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.18.0+ #1 > [0.00] Hardware name:
[gem5-users] How to see the sender state information of a response pkt
Hi all, I want to see the sender state information of a response packet “pkt”. I am trying this: Packet::PrintReqState *prs = dynamic_cast (pkt->senderState); prs->printLabels( ); prs->printObj(pkt); This throws segmentation fault. Could anyone please suggest an way to print/see the sender state information of a pkt? Thanks and regards, Aritra ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] RISC-V Full system Linux PCI
Dear community,
I would like to use the IGbE_e1000 card with RISC-V Linux Full System
Simulation. As I read in this link
(https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/RELEASE-NOTES.md) gem5 v21.0 release includes RISC-V Full system Linux boot
support!
So, I contact Peter Yuen and he sends me the binaries, images,
bootloader etc. As a result, I simulate a Full Linux RISCV.
Specifically, I use the prebuilt files from here:
https://github.com/ppeetteerrs/gem5-RISC-V-FS-Linux/ (to be noticed
that following his instructions - Section 4, I build my own files and
working properly).
Here is the cmd: build/RISCV/gem5.opt -d $RISCV/logs
configs/example/riscv/fs_linux.py --kernel=$OUT/bbl --caches
--mem-size=256MB --mem-type=DDR4_2400_8x8 --cpu-type=AtomicSimpleCPU
--disk-image=$OUT/riscv_parsec_disk -n 1
However, as you can see in the file src/dev/riscv/HiFive.py there is
not implemented PCI interface yet. I try to add it in order to connect
the IGbE_e1000 ethernet card but I cannot achieve it. I do the
following:
1) Add the src/dev/riscv/pci_host.hh file:
#ifndef __DEV_RISCV_PCI_HOST_HH__
#define __DEV_RISCV_PCI_HOST_HH__
#include "dev/pci/host.hh"
struct GenericRiscvPciHostParams;
class GenericRiscvPciHost : public GenericPciHost
{
private:
int intBase;
public:
GenericRiscvPciHost(const GenericRiscvPciHostParams );
virtual ~GenericRiscvPciHost() {}
protected:
uint32_t mapPciInterrupt(const PciBusAddr , PciIntPin pin)
const override;
};
#endif // __DEV_RISCV_PCI_HOST_HH__
2) Add the src/dev/riscv/pci_host.cc file:
#include "dev/riscv/pci_host.hh"
#include "params/GenericRiscvPciHost.hh"
GenericRiscvPciHost::GenericRiscvPciHost(const GenericRiscvPciHostParams )
: GenericPciHost(p), intBase(p.int_base)
{
}
uint32_t
GenericRiscvPciHost::mapPciInterrupt(
const PciBusAddr , PciIntPin pin) const
{
return (intBase + (uint8_t)pin);
}
3) Add "Source('pci_host.cc')" to Sconscript
4) Add the following in the src/dev/riscv/HiFive.py
class GenericRiscvPciHost(GenericPciHost):
type = 'GenericRiscvPciHost'
cxx_header = "dev/riscv/pci_host.hh"
int_base = Param.Int(0x20,
"Base number used as interrupt line and PLIC source.")
5) Add in class HiFive(Platform):
pci_host = GenericRiscvPciHost(conf_base=0x3000, conf_size='256MB',
conf_device_bits=12, pci_pio_base=0x2f00)
ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0,
InterruptLine=1, InterruptPin=1)
6) Add in gem5/configs/example/riscv/fs_linux.py the following:
range_list = system.platform._off_chip_ranges()
range_list.append(AddrRange(0x2f00, 0x5fff))
system.bridge.ranges = range_list
system.platform.pci_host.pio = system.iobus.mem_side_ports
system.platform.ethernet.host = system.platform.pci_host
system.platform.ethernet.pio = system.iobus.mem_side_ports
system.platform.ethernet.dma = system.iobus.cpu_side_ports
7) Add the following in the dts which is produced from auto
generateDeviceTree:
pci@3000 {
compatible = "pci-host-ecam-generic";
device_type = "pci";
#address-cells = <0x3>;
#size-cells = <0x2>;
#interrupt-cells = <0x1>;
reg = <0x0 0x3000 0x0 0x1000>;
ranges = <0x100 0x0 0x0 0x0 0x2f00 0x0 0x1 0x200
0x0 0x4000 0x0 0x4000 0x0 0x1000>;
interrupt-map = <0x0 0x0 0x0 0x1 0x2 0x20 0x0 0x0 0x0 0x2 0x2 0x21
0x0 0x0 0x0 0x3 0x2 0x22 0x0 0x0 0x0 0x4 0x2 0x23 0x800 0x0 0x0 0x1
0x2 0x21 0x800 0x0 0x0 0x2 0x2 0x22 0x800 0x0 0x0 0x3 0x2 0x23 0x800
0x0 0x0 0x4 0x2 0x20 0x1000 0x0 0x0 0x1 0x2 0x22 0x1000 0x0 0x0 0x2
0x2 0x23 0x1000 0x0 0x0 0x3 0x2 0x20 0x1000 0x0 0x0 0x4 0x2 0x21
0x1800 0x0 0x0 0x1 0x2 0x23 0x1800 0x0 0x0 0x2 0x2 0x20 0x1800 0x0 0x0
0x3 0x2 0x21 0x1800 0x0 0x0 0x4 0x2 0x22>;
interrupt-map-mask = <0x1800 0x0 0x0 0x>;
dma-coherent;
bus-range = <0x0 0xff>;
linux,pci-domain = <0x0>;
};
However, when I try to connect the IGbE_e1000 I get:
panic: invalid access size(?) for PCI configspace!
I would appreciate it if anyone would like to help me please! :)
Best regards,
Nikolaos
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[gem5-users] Difference between Directory and Snoop filter
Hi, Can someone help me to understand the difference between the snoop filter and the directory? They are very similar in terms of functionality, but I do not understand the differences. Majid ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
