[gem5-users] In-memory processor taking over the contents of host processor in SE mode
Hello,
I am using SE mode in gem5 and trying to implement the concept of processing in
memory. I have added a TimingSimpleCPU in the memory configuration and trying
to make it takeover all the contents of the host processor to be operated in
the memory instead of the host CPU.
I found out that I must include takeOverFrom(), haltContext() and
activateContext() in the host processor constructor code.
So far I have the below constructed function for implementation (in
Out-of-order CPU constructor file as a host CPU), but I am getting a
segmentation fault.
template
void
FullO3CPU::PIMProcess(ThreadContext *tc, int pim_id){
BaseCPU* pim_cpu =(BaseCPU*)SimObject::find("system.pim_cpu");
this->haltContext(tc->contextId());
pim_cpu->takeOverFrom(this);
pim_cpu->host_id=this->_cpuId;
pim_cpu->activateContext(0);
}
REAL SIMULATION
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
warn: ignoring syscall access(...)
takeOverFrom-1
warn: ClockedObject: Already in the requested power state, request ignored
gem5 has encountered a segmentation fault!
--- BEGIN LIBC BACKTRACE ---
build/X86/gem5.opt(_Z15print_backtracev+0x15)[0xfef065]
build/X86/gem5.opt[0xffca7d]
/lib64/libpthread.so.0(+0xf630)[0x7fd9459b6630]
build/X86/gem5.opt(_ZN15TimingSimpleCPU16handleReadPacketEP6Packet+0x157)[0x11350a7]
build/X86/gem5.opt(_ZN15TimingSimpleCPU17finishTranslationEP21WholeTranslationState+0x248)[0x11391a8]
build/X86/gem5.opt(_ZN15DataTranslationIP15TimingSimpleCPUE6finishERKSt10shared_ptrI9FaultBaseERKS3_I7RequestEP13ThreadContextN7BaseTLB4ModeE+0x110)[0x11413a0]
build/X86/gem5.opt(_ZN6X86ISA3TLB15translateTimingERKSt10shared_ptrI7RequestEP13ThreadContextPN7BaseTLB11TranslationENS8_4ModeE+0xaf)[0x9b3b7f]
build/X86/gem5.opt(_ZN15TimingSimpleCPU15initiateMemReadEmj5FlagsImE+0x518)[0x1137098]
build/X86/gem5.opt(_ZN17SimpleExecContext15initiateMemReadEmj5FlagsImE+0x11)[0x1141581]
build/X86/gem5.opt(_ZNK10X86ISAInst7LdisBig11initiateAccEP11ExecContextPN5Trace10InstRecordE+0xc1)[0xd50631]
build/X86/gem5.opt(_ZN15TimingSimpleCPU14completeIfetchEP6Packet+0x373)[0x1137cb3]
build/X86/gem5.opt(_ZN10EventQueue10serviceOneEv+0x125)[0xff6425]
build/X86/gem5.opt(_Z9doSimLoopP10EventQueue+0xf8)[0x10088e8]
build/X86/gem5.opt(_Z8simulatem+0x966)[0x10094d6]
build/X86/gem5.opt[0x940dba]
build/X86/gem5.opt[0x920e55]
/lib64/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x730a)[0x7fd9452b981a]
/lib64/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x7ed)[0x7fd9452bb64d]
/lib64/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x663c)[0x7fd9452b8b4c]
/lib64/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x7ed)[0x7fd9452bb64d]
/lib64/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x663c)[0x7fd9452b8b4c]
/lib64/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x7ed)[0x7fd9452bb64d]
/lib64/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x663c)[0x7fd9452b8b4c]
/lib64/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x7ed)[0x7fd9452bb64d]
/lib64/libpython2.7.so.1.0(PyEval_EvalCode+0x32)[0x7fd9452bb752]
/lib64/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x5513)[0x7fd9452b7a23]
/lib64/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x7ed)[0x7fd9452bb64d]
/lib64/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x663c)[0x7fd9452b8b4c]
/lib64/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x7ed)[0x7fd9452bb64d]
/lib64/libpython2.7.so.1.0(PyEval_EvalCode+0x32)[0x7fd9452bb752]
/lib64/libpython2.7.so.1.0(+0x100b8f)[0x7fd9452d4b8f]
/lib64/libpython2.7.so.1.0(PyRun_StringFlags+0x65)[0x7fd9452d5a05]
--- END LIBC BACKTRACE ---
Anyone can help me with this please?
Thank you,
Hessa.
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[gem5-users] Read request and writebacks in gem5
Hi, Could anybody help me understand what happens in gem5 when a read request reaches a cache (say L3) and L2's write queue has a pending writeback (writeback that has not yet been written to L3) with the same block as the read request? Is the read request gets serviced from the write queue as the writeback has recent data? If so, where in gem5 can I find the code for this? Thanks and regards, Aritra ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: Memory-Intensive C Programs in SE Mode
Hi Sam,
Are the (virtual, physical?) addresses different when you use the larger
arrays? I wonder if the underlying mmap or malloc calls are breaking in SE
mode somehow. Maybe, after you allocate in your guest code you can print
out the virtual address to make sure it looks reasonable. You can also use
a debug flag to print out the virtual->physical mapping that gem5 assigns
in the syscall_emul file, IIRC. That's where I would start.
Cheers,
Jason
On Thu, Jun 17, 2021 at 6:50 AM Thomas, Samuel via gem5-users <
gem5-users@gem5.org> wrote:
> Hi all,
>
> I'm writing because I'm trying to run a relatively simple, but
> memory-intensive C microbenchmark in SE mode. In particular, it allocates
> and randomly fills a 2MB array, then performs *n* random accesses to the
> array and increments the value.
>
> The program outputs that it is increasing the stack size by a page ("info:
> Increasing stack size by one page."), and eventually no more output is
> produced. I tried putting some sanity check code in the LLC logic (i.e.,
> print "Hello, does this work" every 10,000 accesses), and it seems as
> though the system has actually stopped executing.
>
> What's weird about this is that the program works for smaller arrays, such
> as 10kB, but those are somewhat uninteresting for my work. I suspect I'll
> have to turn to full system mode, but ideally I'd like to work with a
> simpler architecture.
>
> Is there any reason why this might be the case?
>
> Thank you for your help!
>
> Best,
> Sam
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[gem5-users] Re: Reserve a chuck of memory space in SE mode
Hi Xijing, You can set specific mappings from virtual to physical addresses by calling the `map()` function on the Process object from your python configuration file. See https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/src/sim/Process.py#37 Then, once you have a virtual->physical mapping set, you can use mmap() in your guest application and allocate memory at a specific virtual address. Then, when you read/write that virtual address it will be translated to the physical address you set in your config file and you can do whatever you want with the address in the simulator. Cheers, Jason On Sat, Jun 19, 2021 at 1:10 PM Xijing Han via gem5-users < gem5-users@gem5.org> wrote: > Hi All, > > I want to reserve a chunk of memory space for other usage so that the > application won't use it. How can I achieve this in SE mode? > > Thanks, > Xijing Han > ___ > gem5-users mailing list -- gem5-users@gem5.org > To unsubscribe send an email to gem5-users-le...@gem5.org > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: Call m5ops writefile when simulation ends
Hi Pedro, No, I don't think there's an easy way to run m5_write_file on the guest from the host. That is an instruction that is executed on the guest, and the host can't easily control what is executing on the guest (especially when you consider that it has to execute in the right context, etc.). Similarly, the host doesn't have any (easy) way of knowing what address or location on the disk to read/write. I'm sure you could devise a way to do this, but it's not going to be straightforward :). I would do what you suggest and just use stdout via the serial tty. Cheers, Jason On Wed, Jun 16, 2021 at 6:52 AM Pedro Becker via gem5-users < gem5-users@gem5.org> wrote: > Hello gem5 community, > > I'm running an application with FS (fs.py), for which I have generated > some checkpoints. > Now I can restore the checkpoints and run for a given number of ticks. All > good. > > My application outputs data to a file as the execution goes on. This file > is written in the image, inside gem5. > Now, I'd like to have the generated file in the host once the simulation > finishes. > > I know that there is the m5op 'm5_write_file', which can 'export' the file > from the simulated image to the host. > However, since my simulation ends abruptly (after a number of ticks), I > cannot make sure I call the m5op to export the file at the very last moment > (collecting the maximum amount of data produced by my program). > > Is there a simple way to request this file transfer from the python > scripts (e.g., fs.py), once I leave the simulation loop (i.e., when the > simulation ends)? > The alternative would be to output the log to the screen (together with > other info already printed there) and filter the output later, which is > what I'm going to do in the lack of a more elegant way. > > Again, > Thank you. > ___ > gem5-users mailing list -- gem5-users@gem5.org > To unsubscribe send an email to gem5-users-le...@gem5.org > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s > ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: Making virtual address range of a PIO device uncacheable in x86 FS simulation.
Hi Deepak, Yeah, the cache disable bit may not work correctly in the page table walker/TLB. You can check the code there to see if that's what's going wrong. You can also try adding an E820 entry to the workload object (e.g., https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/src/boot-exit/configs/system/system.py#305) which marks that physical range as uncachable. I believe that works correctly. Cheers, Jason On Thu, Jun 17, 2021 at 4:02 AM Deepak Mohan via gem5-users < gem5-users@gem5.org> wrote: > Hi, > I'm doing some experiments using gem5 FS mode for x86. > In the FS mode I'm running a custom OS written for the requirements of > my experiment. I have added a PIO device to the x86 system which > responds to reads and writes to an address range. In the OS I have > mapped this device to a range in the PCI memory map region (@3GB). I > don't want this range to be cached, but when I add the cache hierarchy > to my FS simulation it seems that the device range is also cached. I > tried setting the C bit (Cache disable) in page table entries to > prevent this device range from getting cached, but it seems that > doesn't work. What can I do to prevent the address range of my device > from being cached , or am I doing something conceptually wrong ? Any > ideas / suggestions / pointers would be helpful. > > Thanks, > Deepak Mohan. > ___ > gem5-users mailing list -- gem5-users@gem5.org > To unsubscribe send an email to gem5-users-le...@gem5.org > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s > ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: [gem5 version 20.1.0.5] Writing to satp in RISCV FS mode causes error when L1 caches are added.
Hi Deepak, Have you tried the latest gem5? There's been a lot of work in both gem5-21.0 and on gem5-develop to improve the RISC-V FS support. Another option would be to look at how the RISC-V code has changed to see if that helps diagnose this problem. Cheers, Jason On Fri, Jun 18, 2021 at 10:29 AM Deepak Mohan via gem5-users < gem5-users@gem5.org> wrote: > Hi, > I'm working on an older version of gem5 (20.1.0.5), in which I run a > RISCV full system simulation, I have added a minimal platform in this > version of gem5 to run the FS simulation, but when I add cache > hierarchy to the simulation the following error occurs after writing > to the satp CSR. > > void Packet::setCacheResponding(): > Assertion`!flags.isSet(CACHE_RESPONDING)' failed. > > I'm able to switch address spaces by writing to satp CSR when there is > no cache hierarchy. > > Has anyone faced similar problems ?, any pointers/directions would be > appreciated > > Thanks, > Deepak Mohan > ___ > gem5-users mailing list -- gem5-users@gem5.org > To unsubscribe send an email to gem5-users-le...@gem5.org > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s > ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: Queued Ports
Hi Sam, No, there's not good documentation on this (yet ;)). It's relatively easy to set up, though. Instead of using a single packet ptr, you can have a queue (or whatever datastructure you would like), and you can set the blocked flag only when it is "full" (e.g., the number of items in the structure is equal to the max size you want to model. I would caution you against using the `QueuedPort` object in gem5, though. This creates an infinite queue by default, and it difficult to use in a way that models something reasonable. That said, the `PacketQueue` object may come in handy. Cheers, Jason On Fri, Jun 18, 2021 at 12:07 PM Thomas, Samuel via gem5-users < gem5-users@gem5.org> wrote: > Hi all, > > Is there documentation for a conventional way to set up queued ports in > custom memory objects? In learning_gem5, there is really good documentation > for blocking ports, but the blocking port is currently a bottleneck in my > application. > > Thank you in advance! > > Best, > Sam > ___ > gem5-users mailing list -- gem5-users@gem5.org > To unsubscribe send an email to gem5-users-le...@gem5.org > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: [Big, Little] clusters with CHI and SE mode
Many thanks for the pointers, Gabriel. Best Regards J.Osmany -Original Message- From: Gabriel Busnot via gem5-users [mailto:gem5-users@gem5.org] Sent: 21 June 2021 17:02 To: gem5-users@gem5.org Cc: Gabriel Busnot Subject: [gem5-users] Re: [Big, Little] clusters with CHI and SE mode Hi Javed, I don't think that you want to use devices.CpuCluster as it is used to manage classic caches while you want to use Ruby caches. My first approach would be, using se.py as is: 1- Define two more options in CHI.py to specify the number of big (B) and the number of little (L) cpus from the command line 2- Define the L1ICache, L1DCache and L2DCache for each the big and the little cluster 3- Pass the first B cpus as a single list together with the correct caches to the first CHI_RNF. Assign the result to ruby_system.bigCluster. 4- Pass the last L cpus as a single list together with the correct caches to the second CHI_RNF. Assign the result to ruby_system.littleCluster. 5- Add the private L2 cache of the correct type to both cluster. Keep everything else as is. Best, Gabriel ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: [Big, Little] clusters with CHI and SE mode
Hi Javed, I don't think that you want to use devices.CpuCluster as it is used to manage classic caches while you want to use Ruby caches. My first approach would be, using se.py as is: 1- Define two more options in CHI.py to specify the number of big (B) and the number of little (L) cpus from the command line 2- Define the L1ICache, L1DCache and L2DCache for each the big and the little cluster 3- Pass the first B cpus as a single list together with the correct caches to the first CHI_RNF. Assign the result to ruby_system.bigCluster. 4- Pass the last L cpus as a single list together with the correct caches to the second CHI_RNF. Assign the result to ruby_system.littleCluster. 5- Add the private L2 cache of the correct type to both cluster. Keep everything else as is. Best, Gabriel ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] [Big, Little] clusters with CHI and SE mode
Hello
I am trying to model a system such as
1) Initially there are two clusters, [big, little]
a. Have studied fs_bigLITTLE.py to see how the different clusters are
generated.
2) Make use of CHI
3) Run the system in SE mode.
The command I am planning to use is the following (using HelloWorld to
pipeflush initially)
./build/ARM/gem5.opt configs/example/se.py -ruby --topology=Pt2Pt
--cpu-type=DerivO3CPU --num-cpus=2 --num-dirs=1 --num-l3caches=1
--cmd=tests/test-progs/hello/bin/arm/linux/hello
So I started making modifications in CHI.py.
High level the plan being
1) Generate RNF_Big for the number of cpus and the type of CPU in the big
cluster.
2) Then add a private L2$ for each RNF in RNF_Big (intent originally being
to have private L2$ for each RNF. Change this late to have shared L2$)
3) Repeat (1) and (2) for the Little cluster (ie Generate RNF_Little)
The code snippet being:
##
## Map each BigCluster CPU into an
## RNF
##
for i in range(options.num_cpus_bigclust):
ruby_system.rnf_big = [ CHI_RNF([cpu], ruby_system, L1ICache, L1DCache,
system.cache_line_size.value)
for cpu in options.cpu_type_bigclust ]
# Now add a private L2 cache for each RNF in BigCluster
for rnf_big in ruby_system.rnf_big:
rnf_big.addPrivL2Cache(L2Cache)
#
## Map each LittleCluster CPU into an
## RNF
#
for i in range(options.num_cpus_littleclust):
ruby_system.rnf_little = [ CHI_RNF([cpu], ruby_system, L1ICache,
L1DCache,
system.cache_line_size.value)
for cpu in options.cpu_type_littleclust ]
# Now add a private L2 cache for each RNF in LittleCluster
for rnf_little in ruby_system.rnf_little:
rnf_little.addPrivL2Cache(L2Cache)
Next I want to map
1) ruby_system.rnf_big ==> ruby_system.rnf_bigCluster
2) ruby_system.rnf_little ==> ruby_system.rnf_littleCluster.
So from looking in fs_bigLITTLE.py, I have added the following class inside
create_system() of CHI.py for BigCluster:
## Define the class for BigCluster and LittleCluster
## Extracted from fs_bigLITTLE.py
#
# BigCluster class
class BigCluster(devices.CpuCluster):
# This defines the constructor function for the BigCluster class.
def __init__(self, system, num_cpus, cpu_clock, cpu_voltage="1.0V"):
# Dont understand what cpu_config is doing ???
cpu_config = [ ObjectList.cpu_list.get("DerivO3CPU"),
devices.L1I, devices.L1D, devices.WalkCache, devices.L2 ]
# super() allows access to the __init__() (constructor) of the base
class
# namely devices.CpuCluster class.
super(BigCluster, self).__init__(system, num_cpus, cpu_clock,
cpu_voltage, *cpu_config)
And then to instantiate the BigCluster, the tentative code being:
##
## Generate Big Cluster
##
if options.num_cpus_bigclust > 0:
## Call to BigCluster() class
ruby_system.bigCluster = BigCluster(ruby_system,
options.num_cpu_bigclust,
options.big_cpu_clock)
ruby_system.mem_mode = ruby_system.bigCluster.memoryMode()
else:
m5.fatal("Number of CPUs in Big Cluster is Zero.")
Pretty certain this is not going to work. But I don't know how to solve this.
For the class BigCluster(), I would like to pass the following for cpu_config:
cpu_config = [ruby_system.rnf_big, ## this is the actual cpu being used in
the RNF for the big cluster
None, ## L1I$ has
already been define
None, ## L1D$ has
already been defined
devices.WalkCache,
None)## L2$ has
already been defined.
Any thought/pointers as how to get the above resolved will be much appreciated.
Best regards
JO
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[gem5-users] Re: Compiling failure for original code in gem5 book
If you follow each step carefully starting from here, you should be good ;) The tutorial has been updated recently to take the latest API changes into account. https://www.gem5.org/getting_started/ Gabriel ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: Write Buffer Configuration for Ruby
Hi Wang, If by "write buffer queue", you mean the "mandatoryQueue", then you cannot restrict its size wihtout risking an assert error as the sequencer does not check the mandatoryQueue fullness before enqueuing. Still, the maximum number of concurrent tag array and data array lookups can be controlled using the banking mechanism of the CacheMemory used in Ruby cache controllers. Sadly, MOESI CMP Directory does not seem to make use of this mechanism and adding support for it is no easy task. You can still look at MOESI AMD and CHI to get two examples of cache banking support in a Ruby protocol. Again, adding support for that to a protocol will be a hard task and adding it without introducing subtle bugs can be even harder. But if you have no other choice than learning Ruby and adding this feature to the protocol you want to use, here are a few hints to start (based on CHI protocol): 1. Look for the RequestType enumeration in CHI-cache-funcs.sm. It lists the names associated to arbitrary resources like tag and data array banks. These tags are associated to a transition when the corresponding resource is required by this transition. E.g., when CHI needs to read the tag array during a transition, the TagArrayRead tag is associated to the transition (see CHI-cache-transitions.sm). 2. Then the checkResourceAvailable function in the same file tests for resource availability according to the flag passed as arguments. 3. If the later returns true, then recordRequestType (still in CHI-cache-funcs.sm) will be called to record the resource usage. If checkResourceAvailable returns false, a "Resource stall" is triggered, the transition is aborted and the next input port is checked. 4. If you set a resource stall handler (search rsc_stall_handler in CHI-cache-ports.sm), you can customize the behavior of the controller upon Resource stall for each input port. You should not need this feature. Note that while the RequestType enumeration type and checkResourceAvailable and recordRequestTypes function names are magic names that you must conform to, the content of RequestType and the body of these two functions is yours to choose. This is the "fully customized" version of the check_allocate mechanism, if you know it. If not, then check it first to get in touch with the ResourceStall mechanism. Good luck with your experiments, Gabriel ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: Error with gem5 full system simulation
Hi Abhijeeth,
With regards to your first message, it looks like you are using a custom
configuration python script. Often times these errors occur from failing to
import the objects in the same way based on the directory. For example, if
you look at the script "configs/example/se.py" you'll see that they are
loading the caches from module "common.caches" which is only visible by the
"addToPath('../')" command in line 53. I would recommend trying to make
sure that the appropriate path/modules are loaded so that the
"LinuxX86FSSystem" object is defined/imported.
The error from the second message usually happens when the --kernel flag
isn't specified. Try making sure that your bash command has that flag, and
you can use -h for general flag usage.
Hopefully this helps! If so, could you reply all to the mailing list so
that people see it as resolved?
Best,
Sam
On Sat, Jun 19, 2021 at 2:56 PM abhijeeth modi via gem5-users <
gem5-users@gem5.org> wrote:
> Hello
>
> I tried to follow the example given in configs/example/fs.py for running
> full system simulation and I also mentioned the kernel path in
> configs/common/SysPath.py,
>
> I am facing an error as *fatal: fatal condition !kernelObj occurred: No
> kernel to load.*
>
> Has someone tried the full system simulation?
> If yes, please guide me with this.
>
> Thankyou
>
> Regards
> Abhijeeth
>
> On Fri, Jun 18, 2021 at 10:09 PM abhijeeth modi <
> modiabhijeeth2...@gmail.com> wrote:
>
>> Hello
>>
>> I followed the official documentation for running full system simulation
>> for X86 architecture
>>
>> http://learning.gem5.org/book/part5/fs_config.html#running-full-system
>>
>> by executing the command:
>>
>> *build/X86/gem5.opt configs/tutorial_1/system2.py*
>>
>> I am getting an error :
>>
>> *Traceback (most recent call last):*
>> * File "", line 1, in *
>> * File "build/X86/python/m5/main.py", line 455, in main*
>> *exec(filecode, scope)*
>> * File "configs/tutorial_1/system2.py", line 38, in *
>> *class MySystem(LinuxX86System):*
>> *NameError: name 'LinuxX86System' is not defined*
>>
>>
>> I gave kernel path in the script as mentioned.
>>
>> Can someone help me with this please?
>>
>> Thank you
>>
>>
>> Regards
>>
>> Abhijeeth
>>
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[gem5-users] Re: Compiling failure for original code in gem5 book
OK I’ll check it out. I got these code from gem5 book. By the way, could you give me the link for the latest tutorial guide and code so that I can follow them?(gem5 book’s code seems outdated) Thanks for the assistance! Gabriel Busnot via gem5-users 于2021年6月21日 周一09:46写道： > It looks like you are not using the latest version of the tutorial source > code. > Where did you get the tutorial source code from? > > I would recommend checking out the tag v21.0.0.0 and starting from the > code in src/learning_gem5/part2. > gem5 API has recently changed and any file older than a couple of months > is likely incompatible with the latest changes. > > Gabriel > ___ > gem5-users mailing list -- gem5-users@gem5.org > To unsubscribe send an email to gem5-users-le...@gem5.org > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s > ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: Compiling failure for original code in gem5 book
It looks like you are not using the latest version of the tutorial source code. Where did you get the tutorial source code from? I would recommend checking out the tag v21.0.0.0 and starting from the code in src/learning_gem5/part2. gem5 API has recently changed and any file older than a couple of months is likely incompatible with the latest changes. Gabriel ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: Compiling failure for original code in gem5 book
Hi Gabriel:
1. I change the file name from SConscript to hello (deregister
simple_memobj), it could compile successfully.
[LINK] -> X86/gem5.opt
scons: done building targets.
2.I used the downloaded SConscript from the website. I'll show the content
below.
3. I already added it into the source code.
Here are all source code(minor change from the original)
[I] liqi@LQSs-MacBook-Pro ~/D/g/s/l/simple_memobj (stable)> cat SConscript
# -*- coding: utf-8 -*-
# Copyright (c) 2017 Jason Lowe-Power
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Jason Lowe-Power
Import('*')
SimObject('SimpleMemobj.py')
Source('simple_memobj.cc')
DebugFlag('SimpleMemobj')
---
[I] liqi@LQSs-MacBook-Pro ~/D/g/s/l/simple_memobj (stable)> cat
simple_memobj.cc
/*
* Copyright (c) 2017 Jason Lowe-Power
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Jason Lowe-Power
*/
#include "learning_gem5/simple_memobj/simple_memobj.hh"
#include "debug/SimpleMemobj.hh"
SimpleMemobj::SimpleMemobj(SimpleMemobjParams *params) :
MemObject(params),
instPort(params->name + ".inst_port", this),
dataPort(params->name + ".data_port", this),
memPort(params->name + ".mem_side", this),
blocked(false)
{
}
BaseMasterPort&
SimpleMemobj::getMasterPort(const std::string& if_name, PortID idx)
{
panic_if(idx != InvalidPortID, "This object doesn't support vector
ports");
// This is the name from the Python SimObject declaration
(SimpleMemobj.py)
if (if_name == "mem_side") {
return memPort;
} else {
// pass it along to our super class
return MemObject::getMasterPort(if_name, idx);
}
}
BaseSlavePort&
SimpleMemobj::getSlavePort(const std::string& if_name, PortID idx)
{
panic_if(idx != InvalidPortID, "This object doesn't support vector
ports");
// This is the name from the Python SimObject declaration in
SimpleCache.py
if (if_name == "inst_port") {
return instPort;
} else if (if_name ==
[gem5-users] Re: Compiling failure for original code in gem5 book
Hi Qishen, Can you first assert that gem5 compiles on your environment before adding your own code? Then, I would recommend double-checking your SConscript file against src/learning_gem5/part2/SConscript. BTW: at line 248 of simple_memobj.cc: you forgot const ;) Best, Gabriel ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
