[gem5-users] Unable to boot Linux in FS mode
Hello, My OS is Ubuntu 22 and I am using gem5 v22.0.0.1, when I boot a Ubuntu 22 image I got error: *Kernel panic - not syncing: Attempted to kill init! exitcode=0x7f00* Attached are the logs, could anyone help to find the problem? Thanks in advance. Best regards, Zhenwen Hu gem5 Simulator System. https://www.gem5.org gem5 is copyrighted software; use the --copyright option for details. gem5 version 22.0.0.1 gem5 compiled Jul 27 2023 22:11:27 gem5 started Jul 27 2023 23:14:59 gem5 executing on zhewen-B360-M-AORUS-PRO, pid 679626 command line: /home/zhewen/vSwarm-u/resources/gem5/build/X86/gem5.opt --outdir=results/fibonacci-go/ run_sim.py --kernel kernel --disk disk.img --function fibonacci-go --mode=setup /home/zhewen/vSwarm-u Create CPU: X86KvmCPU Created CPU: 2x X86KvmCPU, Mem mode: atomic_noncaching Drive system: 1 X86AtomicSimpleCPU cores Create CPU: X86KvmCPU Created Drive CPU: 1x X86KvmCPU, Mem mode: atomic_noncaching Tick freq = 1 ticks/sec. Set sim quantum to 10 ticks/sec => 1000µs --- Setup Mode --- Global frequency set at 1 ticks per second warn: drivesys.workload.acpi_description_table_pointer.rsdt adopting orphan SimObject param 'entries' warn: testsys.workload.acpi_description_table_pointer.rsdt adopting orphan SimObject param 'entries' build/X86/sim/kernel_workload.cc:46: info: kernel located at: kernel 0: drivesys.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 drivesys.pc.com_1.device: Listening for connections on port 3456 build/X86/mem/dram_interface.cc:690: warn: DRAM device capacity (32768 Mbytes) does not match the address range assigned (2048 Mbytes) build/X86/sim/kernel_workload.cc:46: info: kernel located at: kernel build/X86/cpu/kvm/vm.cc:76: warn: Use of multiple KvmVMs is currently untested! 0: testsys.pc.south_bridge.cmos.rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 testsys.pc.com_1.device: Listening for connections on port 3457 0: drivesys.remote_gdb: listening for remote gdb on port 7000 build/X86/mem/coherent_xbar.cc:140: warn: CoherentXBar drivesys.llc_bus has no snooping ports attached! build/X86/dev/intel_8254_timer.cc:128: warn: Reading current count from inactive timer. 0: testsys.remote_gdb: listening for remote gdb on port 7001 build/X86/mem/coherent_xbar.cc:140: warn: CoherentXBar testsys.llc_bus has no snooping ports attached! Start simulation... build/X86/cpu/kvm/base.cc:150: info: KVM: Coalesced MMIO disabled by config. build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x: unimplemented function 2 build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x: unimplemented function 3 build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x: unimplemented function 4 build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x: unimplemented function 5 build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x: unimplemented function 6 build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x: unimplemented function 8 build/X86/cpu/kvm/base.cc:150: info: KVM: Coalesced MMIO disabled by config. build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x: unimplemented function 2 build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x: unimplemented function 3 build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x: unimplemented function 4 build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x: unimplemented function 5 build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x: unimplemented function 6 build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x: unimplemented function 8 build/X86/cpu/kvm/base.cc:150: info: KVM: Coalesced MMIO disabled by config. build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x: unimplemented function 2 build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x: unimplemented function 3 build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x: unimplemented function 4 build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x: unimplemented function 5 build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x: unimplemented function 6 build/X86/arch/x86/cpuid.cc:180: warn: x86 cpuid family 0x: unimplemented function 8 build/X86/sim/simulate.cc:194: info: Entering event queue @ 0. Starting simulation... build/X86/arch/x86/kvm/x86_cpu.cc:1561: warn: kvm-x86: MSR (0x3a) unsupported by gem5. Skipping. build/X86/arch/x86/kvm/x86_cpu.cc:1561: warn: kvm-x86: MSR (0xd90) unsupported by gem5. Skipping. build/X86/arch/x86/kvm/x86_cpu.cc:1561: warn: kvm-x86: MSR (0x48) unsupported by gem5. Skipping. build/X86/arch/x86/kvm/x86_cpu.cc:1561: warn: kvm-x86: MSR (0x3a) unsupported by gem5. Skipping. build/X86/arch/x86/kvm/x86_cpu.cc:1561: warn: kvm-x86: MSR (0x309) unsupported by gem5. Skipping. build/X86/arch/x86/kvm/x86_cpu.cc:1561: warn: kvm-x86: MSR (0xd90) unsupported by gem5. Skipping. build/X86/arch/x86/kvm/x86_cpu.cc:1561: warn: kvm-x86: MSR (0x30a)
[gem5-users] Re: Using Traffic Generators with Ruby
Hi Vishnu, I do not believe there is any way to direct traffic to a particular message buffer (e.g, `requestToDir`). Ruby is in some sense a "black box" that only has port inputs (which are directed to a sequencer) and port output (via `requestToMemory`). That said, this is a cool idea! I would encourage you to develop this support if it's something that you would find useful for your work. In fact, I think this support could be very useful upstream for testing! Cheers, Jason On Wed, Jul 26, 2023 at 5:52 AM VISHNU RAMADAS via gem5-users < gem5-users@gem5.org> wrote: > Hi, > > I have a few traces that I recorded at the input port of the directory > (CHI protocol). I would like to replay these by injecting them directly > into the Ruby network/directory. Requests in these traces contain > information about the type of coherent request/snoop response they send and > I want to inject traffic that includes this. Looking around, I found that > the Garnet standalone protocol does something similar since all it does is > inject traffic into the network. Is combining the Garnet standalone > protocol with the CHI model the only way to send messages to the > directory? Or are there other approaches that directly inject coherent > traffic into the directory (without the need for a sequencer or dummy > cache)? > > Thanks, > Vishnu > ___ > gem5-users mailing list -- gem5-users@gem5.org > To unsubscribe send an email to gem5-users-le...@gem5.org > ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org
[gem5-users] Re: stopping simulation via ThreadContext::halt()
Hi David, I think you want to call the function `exitSimLoopNow` or `exitSimLoop`. You can call this function from an instruction implementation, (e.g., halt), I believe. See https://github.com/search?q=repo%3Agem5%2Fgem5+exitSimLoop+=code Cheers, Jason On Wed, Jul 26, 2023 at 9:39 AM David Bears via gem5-users < gem5-users@gem5.org> wrote: > Hello, > > I am trying to create a fault which will stop the simulation. I tried > calling ThreadContext::halt from within FaultBase::invoke (or rather a > subclass of FaultBase). This successfully stops simulation of the CPU, > but then it endlessly simulates memory refreshes. > > So how should I properly shut down the simulated system so that the > gem5.opt process finishes? Do I have to do something in addition to > calling ThreadContext::halt? Is ThreadContext::halt the wrong tool for > the job? Or perhaps do I have something else set up wrong? > > For context, I implemented most of the NIOS II ISA in gem5, and I am > running an executable which is designed to run on bare metal. There is a > particular 'magic' instruction which signals that the executable is > finished, and I want to stop the simulation sometime after committing > such an instruction. > > Thanks is advance, > David > > ___ > gem5-users mailing list -- gem5-users@gem5.org > To unsubscribe send an email to gem5-users-le...@gem5.org > ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org
[gem5-users] Re: Facing issue while trying to use PARSEC benchmark using Gem5
Hi Abhinav, I would suggest using the most recent version of gem5 (v23.0) and use the gem5-resources version of parsec. See https://resources.gem5.org/resources/x86-parsec/example?database=gem5-resources=1.0.0 for an example using parsec. Cheers, Jason On Thu, Jul 27, 2023 at 2:14 AM Abhinav Kumar via gem5-users < gem5-users@gem5.org> wrote: > Hi everyone, > I'm trying to run the PARSEC benchmark using gem5. I followed the tutorial > on the site. But, currently I'm facing one issue, the simerr file contains > the following: > Traceback (most recent call last): > File "", line 1, in > File "build/X86/python/m5/main.py", line 457, in main > File "configs-parsec-tests/run_parsec.py", line 49, in > from system import * > File "/home/user-name/parsec-tests/configs-parsec-tests/system.py", line > 37, in > class MySystem(LinuxX86System): > NameError: name 'LinuxX86System' is not defined" > I have downloaded the system configuration file from > https://github.com/darchr/gem5art/tree/master/docs/gem5-configs/configs-parsec-tests/system > . > Can you guys please help me with this? > > Regards, > Abhinav > ___ > gem5-users mailing list -- gem5-users@gem5.org > To unsubscribe send an email to gem5-users-le...@gem5.org > ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org
[gem5-users] Re: Inquiry about using RiscvTimingSimpleCPU to connect with TLM memory in Gem5
Hi Zitai, You should be able to use any CPU model with the TLM interface. You can write your own configuration file / run script that creates a TimingSimpleCPU and connects the I/D ports to the TLM interface. Cheers, Jason On Thu, Jul 27, 2023 at 2:44 AM 泰。 via gem5-users wrote: > Hi： > > I am a Gem5 user and currently working on system-level modeling and > simulation using Gem5. I have encountered an issue and would greatly > appreciate your assistance and advice. > > Currently, I am *using tlm_slave.py to connect with TLM memory > successfully*. However, I noticed that when using tlm_slave.py, it > requires pairing with the _TrafficGen CPU which is not a conventional CPU > model; instead, it is a special module used for generating memory system > stimuli. I would like to use the traditional processor simulator > *RiscvTimingSimpleCPU > instead of the _TrafficGen CPU* to conduct more realistic > instruction-level simulation. > > I am not familiar with the method of connecting RiscvTimingSimpleCPU with > TLM memory and would like to inquire whether it is possible to achieve this > configuration and what specific steps need to be taken. > > During the configuration process, would I need to modify the interface of > RiscvTimingSimpleCPU or perform other customizations? Is the workload > significant? > > Thank you very much for your help and guidance! > > Best regards, > > Zitai > > > ___ > gem5-users mailing list -- gem5-users@gem5.org > To unsubscribe send an email to gem5-users-le...@gem5.org > ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org
[gem5-users] Inquiry about using RiscvTimingSimpleCPU to connect with TLM memory in Gem5
Hi： I am a Gem5 user and currently working on system-level modeling and simulation using Gem5. I have encountered an issue and would greatly appreciate your assistance and advice. Currently, I amusing tlm_slave.py to connect with TLM memory successfully. However, I noticed that when using tlm_slave.py, it requires pairing with the _TrafficGen CPU which is not a conventional CPU model; instead, it is a special module used for generating memory system stimuli. I would like to use the traditional processor simulatorRiscvTimingSimpleCPU instead of the _TrafficGen CPUto conduct more realistic instruction-level simulation. I am not familiar with the method of connecting RiscvTimingSimpleCPU with TLM memory and would like to inquire whether it is possible to achieve this configuration and what specific steps need to be taken. During the configuration process, would I need to modify the interface of RiscvTimingSimpleCPU or perform other customizations? Is the workload significant? Thank you very much for your help and guidance! Best regards, Zitai___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org
[gem5-users] Facing issue while trying to use PARSEC benchmark using Gem5
Hi everyone, I'm trying to run the PARSEC benchmark using gem5. I followed the tutorial on the site. But, currently I'm facing one issue, the simerr file contains the following: Traceback (most recent call last): File "", line 1, in File "build/X86/python/m5/main.py", line 457, in main File "configs-parsec-tests/run_parsec.py", line 49, in from system import * File "/home/user-name/parsec-tests/configs-parsec-tests/system.py", line 37, in class MySystem(LinuxX86System): NameError: name 'LinuxX86System' is not defined" I have downloaded the system configuration file from https://github.com/darchr/gem5art/tree/master/docs/gem5-configs/configs-parsec-tests/system . Can you guys please help me with this? Regards, Abhinav ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org
