[gem5-users] Simulate accelerator-like NoC structure in gem5

[VANI KRISHNA BARLA via gem5-users]

I've limited exposure to gem5 functioning with respect to communication in the 
NoC (NetworkUnit/InputUnit/Routers) at packet level.

My primary objective is to investigate the ramifications of employing an 
alternate number representation system (POSIT) in contrast to the IEEE 754 
floating-point standard. Specifically, while simulating I need to analyse the 
reduced bit width impact in terms of storage in memory and usage of the system 
bus between the memory unit and the nodes, and if possible study the impact of 
an alternate MAC unit which operates for different bit widths with lower power 
and area requirements.

Could anyone kindly provide some starting point or insights on customizing such 
simulations within gem5? Any help would be greatly appreciated. Thank you in 
advance for your assistance. Regards,

Vani
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[gem5-users] Increase in area and power in 3D NoCs in Heterogarnet

[Ali Karazmoodeh via gem5-users]

Dear gem5 community,

I developed and tested several 3D network-on-chips in Garnet using internal
links for inter-layer communication.  As you know, 3D integration is often
touted as a method to reduce power consumption. The rationale is that the
millimeter-length intra-layer links become significantly shorter in the
vertical dimension.

To compare the performance of 3D NoCs with their 2D counterparts, I turned
to the DSENT simulator. However, my findings were contrary to what I
expected. Here are the key observations:

*1. Internal Link Lengths:* DSENT does not differentiate between internal
links and sets them all to a uniform 1mm length. This oversimplification
might have affected the accuracy of my results.
*2. Extra Ports in 3D Integration:* One of the fundamental aspects of 3D
integration involves adding two extra ports (Up & Down) to facilitate
vertical communication. While this enhances connectivity, it also
significantly increases the required buffer space, leading to potential
power and area overhead.

Now, I find myself questioning the validity of my approach. What mistakes
might I have made to obtain these unexpected outcomes? Is there an
alternative way to design 3D NoCs in Garnet that mitigates the impact of
additional ports on power and area?


All the best,
Ali Karazmoodeh
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