[gem5-users] AMD_MOESI core pair controller unhooked memport
Hi All, In the AMD_MOESI protocol, when working with syscall emulation, I run into an issue where the Corepair controller memory port is unconnected, giving me the following message: src/sim/port.cc:62: fatal: system.cp_cntrl0.memory: Unconnected port! After doing some digging, I was able to understand that the memory port is passed down from the RubyController module. From what I can guage, this meant to be hooked up to the next level of the memory hierarchy, but it also seems as though in the AMD_MOESI setup, that comes with gem5, that the corepair calls to the L3 through the ruby network in/out ports, hence why I could work with it in the memory testing example provided. Now, I am quite stuck figuring out what to do with this port. Do I make an additional connection to L3? Can I tie it off somehow? Is my understanding perhaps wrong? Any and all insight is appreciated, I am quite stuck on this issue. Thanks! ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org
[gem5-users] Resource Stalls vs Enqueue latency
Hi All, In some environments, access latencies are set in both SLICC (for enqueueing the latency on responses) and at the same time within cache objects in Python (to create resource stalls when banks are not available in Ruby). I think I'm having trouble figuring out, why do it in both places? Do the controller and cache operate separately, and is this a way to synchronize the two? Or can one take priority over another? Any insight is appreciated. Thanks ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org
[gem5-users] Invoked SLICC functions outside SLICC?
Hi Folks, I am attempting to get a better handle on the statistics collection within the cache protocols, and one thing I noticed while browsing around the MOESI AMD protocol was that some functions, such as functionalRead/Write, checkResourceAvailable and recordRequestType are defined, but never specifically invoked within the .sm protocol itself. I note that there do seem to be default versions of these functions elsewhere within the Ruby/SLICC filesystem, and that these definitions may be overriding the original definitions. However, I am having trouble reconciling where these functions are being called then. As an example, after running a traffic generator on a setup using the MOESI_AMD_Base protocol, I can clearly see cacheMemory statistics that come from the recordRequestType function, but I am having trouble understanding how and where this happens (since it is not happening directly in the .sm file, and a browse through the codebase has left me stuck). Any help is appreciated, Thank you ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org
[gem5-users] Unconnected Port Debugging
Hi Folks, I am working through debugging a bug I am running while trying to run syscall mode in gem5 on the Ruby MOESI_AMD_BASE protocol. To start, the bug I am running into is as follows: src/sim/port.cc:62: fatal: system.cp_cntrl0.memory: Unconnected port! A few notes to describe what I understand thus far: i. This function is called only during an exception, meaning it was not an in/out port such as the triggerQueue which is not hooked up to a virtual network ii. This doesn't arise when running the example configuration for the ruby_mem_test.py on the MOESI_AMD_BASE protocol iii. In this configuration, modeled closely to parts of the now deprecated se.py, the MESI_two_level protocol runs without issue iv. I have verified that in the MOESI_AMD_BASE.py file, all CorePair in/out ports are connected to the ruby network Because the MESI_two_level protocol runs without issue, I currently believe that there is something I must change or configure in the MOESI_AMD_BASE.py configuration to resolve this issue, but I have not succeeded thus far. Though I don't have all the code here, I can share anything as needed. If anyone has insight, your help is much appreciated! thanks ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org
[gem5-users] Ruby SLICC network vs RubyCache latency mechanics
Hi Folks, I am currently working on modeling a system in which the L3 Cache is dynamically set. As a simple example of this, say there were two sets of addresses. If I get a LD/ST request to the first set, it takes twice as long as it would for retrieval in the second set. In any case, I have been able to model this phenomenon in gem5's SLICC structure under the guise of a new protocol and was able to see it working as intended using the protocol debugger. However, when I set up a python configuration file to get things going, I know that the RubyCache python object that my generated controller connects to also has a latency parameter. My question is, to accurately model this phenomenon, is the modification of the SLICC sufficient to model the new delays, or do modifications have to be made to RubyCache as well? I took a look at the RubyCache python object, and was left more puzzled when I didn't see any special methods directly in this class (I understand it pulls some of these from SimObject), which made me think this may a better place to ask in the meantime. Thanks ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org
[gem5-users] Re: GEM5 within SystemC build issue
Looks like this JIRA is low priority and has no progress since 2021.
Thanks a lot!
| |
G
|
|
ginger...@163.com
|
Replied Message
| From | Yu-hsin Wang |
| Date | 7/20/2023 10:47 |
| To | G |
| Cc | gem5-users@gem5.org |
| Subject | Re: [gem5-users] Re: GEM5 within SystemC build issue |
Hi Ginger,
We didn't try to run gem5 as dynamic lib inside SystemC. You may need to reach
the maintainers. Here's a ticket you can refer.
https://gem5.atlassian.net/browse/GEM5-874
Thanks.
On Wed, Jul 19, 2023 at 4:43 PM G wrote:
Hi Yu-hsin,
Thanks for the reply, I'm trying to run gem5 as dynamic lib inside SystemC.
Did tried and can pass build without this option, but hit below assertion so I
suspect it has to go with cxx-config portion.
main.cc:280: fatal: Config problem in sim object root: No sim object type Root
is available
| |
G
|
|
ginger...@163.com
|
Replied Message
| From | Yu-hsin Wang |
| Date | 7/19/2023 15:32 |
| To | G |
| Cc | gem5-users@gem5.org |
| Subject | Re: [gem5-users] Re: GEM5 within SystemC build issue |
Hi Ginger,
I think the issue is --with-cxx-config only works in SimObject case. However
the Gem5-TLM bridges are all sc_modules instead of SimObject. I can get compile
success without --with-cxx-config.
Is that option required in your case?
Thanks.
On Wed, Jul 19, 2023 at 2:43 PM G wrote:
Hello Yu-hsin,
Just saw you are the main edtor of tlm bridge to sysc, maybe you are the right
person? :)
In the bridge, this->create() will return a Gem5ToTlmBridge type which is
incompatible with SimObject as below declared, any comments? Thanks a lot!
SimObject *
Gem5ToTlmBridge32CxxConfigParams::simObjectCreate()
{
return this->create();
}
| |
G
|
|
|
Replied Message
| From | G via gem5-users |
| Date | 7/14/2023 17:24 |
| To | gem5-users@gem5.org |
| Cc | G |
| Subject | [gem5-users] Re: GEM5 within SystemC build issue |
Hello, Anyone hit same issue when building "GEM5 within SystemC"? Or just
succeeding?
| |
G
|
|
ginger...@163.com
|
Replied Message ----
| From | G via gem5-users |
| Date | 7/3/2023 10:35 |
| To | gem5-users@gem5.org |
| Cc | gingerluo |
| Subject | [gem5-users] GEM5 within SystemC build issue |
Hello,
Anyone went well with GEM5 and SystemC integration?
I triied to build libgem5_debug.so so I can integrate GEM5 in a standalone
systemc environment with below commandline:
python3 `which scons` --with-cxx-config --without-python --without-tcmalloc
USE_SYSTEMC=1 build/RISCV/libgem5_$(BUILD_TYPE).so -j 32
But I got below issue with "--with-cxx-config" option.
build/RISCV/cxx_config/Gem5ToTlmBridge32.cc: In member function ‘virtual
gem5::SimObject* gem5::Gem5ToTlmBridge32CxxConfigParams::simObjectCreate()’:
build/RISCV/cxx_config/Gem5ToTlmBridge32.cc:149:24: error: cannot convert
‘sc_gem5::Gem5ToTlmBridge<32>*’ to ‘gem5::SimObject*’ in return
149 | return this->create();
| ^~
| |
| sc_gem5::Gem5ToTlmBridge<32>*
if I do without this option, assertion fired in below, complaining:
main.cc:280: fatal: Config problem in sim object root: No sim object type Root
is available
| |
G
|
|
ginger...@163.com
|___
gem5-users mailing list -- gem5-users@gem5.org
To unsubscribe send an email to gem5-users-le...@gem5.org
[gem5-users] Re: GEM5 within SystemC build issue
Hi Yu-hsin,
Thanks for the reply, I'm trying to run gem5 as dynamic lib inside SystemC.
Did tried and can pass build without this option, but hit below assertion so I
suspect it has to go with cxx-config portion.
main.cc:280: fatal: Config problem in sim object root: No sim object type Root
is available
| |
G
|
|
ginger...@163.com
|
Replied Message
| From | Yu-hsin Wang |
| Date | 7/19/2023 15:32 |
| To | G |
| Cc | gem5-users@gem5.org |
| Subject | Re: [gem5-users] Re: GEM5 within SystemC build issue |
Hi Ginger,
I think the issue is --with-cxx-config only works in SimObject case. However
the Gem5-TLM bridges are all sc_modules instead of SimObject. I can get compile
success without --with-cxx-config.
Is that option required in your case?
Thanks.
On Wed, Jul 19, 2023 at 2:43 PM G wrote:
Hello Yu-hsin,
Just saw you are the main edtor of tlm bridge to sysc, maybe you are the right
person? :)
In the bridge, this->create() will return a Gem5ToTlmBridge type which is
incompatible with SimObject as below declared, any comments? Thanks a lot!
SimObject *
Gem5ToTlmBridge32CxxConfigParams::simObjectCreate()
{
return this->create();
}
| |
G
|
|
|
Replied Message
| From | G via gem5-users |
| Date | 7/14/2023 17:24 |
| To | gem5-users@gem5.org |
| Cc | G |
| Subject | [gem5-users] Re: GEM5 within SystemC build issue |
Hello, Anyone hit same issue when building "GEM5 within SystemC"? Or just
succeeding?
| |
G
|
|
ginger...@163.com
|
Replied Message ----
| From | G via gem5-users |
| Date | 7/3/2023 10:35 |
| To | gem5-users@gem5.org |
| Cc | gingerluo |
| Subject | [gem5-users] GEM5 within SystemC build issue |
Hello,
Anyone went well with GEM5 and SystemC integration?
I triied to build libgem5_debug.so so I can integrate GEM5 in a standalone
systemc environment with below commandline:
python3 `which scons` --with-cxx-config --without-python --without-tcmalloc
USE_SYSTEMC=1 build/RISCV/libgem5_$(BUILD_TYPE).so -j 32
But I got below issue with "--with-cxx-config" option.
build/RISCV/cxx_config/Gem5ToTlmBridge32.cc: In member function ‘virtual
gem5::SimObject* gem5::Gem5ToTlmBridge32CxxConfigParams::simObjectCreate()’:
build/RISCV/cxx_config/Gem5ToTlmBridge32.cc:149:24: error: cannot convert
‘sc_gem5::Gem5ToTlmBridge<32>*’ to ‘gem5::SimObject*’ in return
149 | return this->create();
| ^~
| |
| sc_gem5::Gem5ToTlmBridge<32>*
if I do without this option, assertion fired in below, complaining:
main.cc:280: fatal: Config problem in sim object root: No sim object type Root
is available
| |
G
|
|
ginger...@163.com
|___
gem5-users mailing list -- gem5-users@gem5.org
To unsubscribe send an email to gem5-users-le...@gem5.org
[gem5-users] Re: GEM5 within SystemC build issue
Hello Yu-hsin,
Just saw you are the main edtor of tlm bridge to sysc, maybe you are the right
person? :)
In the bridge, this->create() will return a Gem5ToTlmBridge type which is
incompatible with SimObject as below declared, any comments? Thanks a lot!
SimObject *
Gem5ToTlmBridge32CxxConfigParams::simObjectCreate()
{
return this->create();
}
| |
G
|
|
|
Replied Message
| From | G via gem5-users |
| Date | 7/14/2023 17:24 |
| To | gem5-users@gem5.org |
| Cc | G |
| Subject | [gem5-users] Re: GEM5 within SystemC build issue |
Hello, Anyone hit same issue when building "GEM5 within SystemC"? Or just
succeeding?
| |
G
|
|
ginger...@163.com
|
Replied Message ----
| From | G via gem5-users |
| Date | 7/3/2023 10:35 |
| To | gem5-users@gem5.org |
| Cc | gingerluo |
| Subject | [gem5-users] GEM5 within SystemC build issue |
Hello,
Anyone went well with GEM5 and SystemC integration?
I triied to build libgem5_debug.so so I can integrate GEM5 in a standalone
systemc environment with below commandline:
python3 `which scons` --with-cxx-config --without-python --without-tcmalloc
USE_SYSTEMC=1 build/RISCV/libgem5_$(BUILD_TYPE).so -j 32
But I got below issue with "--with-cxx-config" option.
build/RISCV/cxx_config/Gem5ToTlmBridge32.cc: In member function ‘virtual
gem5::SimObject* gem5::Gem5ToTlmBridge32CxxConfigParams::simObjectCreate()’:
build/RISCV/cxx_config/Gem5ToTlmBridge32.cc:149:24: error: cannot convert
‘sc_gem5::Gem5ToTlmBridge<32>*’ to ‘gem5::SimObject*’ in return
149 | return this->create();
| ^~
| |
| sc_gem5::Gem5ToTlmBridge<32>*
if I do without this option, assertion fired in below, complaining:
main.cc:280: fatal: Config problem in sim object root: No sim object type Root
is available
| |
G
|
|
ginger...@163.com
|___
gem5-users mailing list -- gem5-users@gem5.org
To unsubscribe send an email to gem5-users-le...@gem5.org
[gem5-users] Re: GEM5 within SystemC build issue
Hello, Anyone hit same issue when building "GEM5 within SystemC"? Or just succeeding? | | G | | ginger...@163.com | Replied Message | From | G via gem5-users | | Date | 7/3/2023 10:35 | | To | gem5-users@gem5.org | | Cc | gingerluo | | Subject | [gem5-users] GEM5 within SystemC build issue | Hello, Anyone went well with GEM5 and SystemC integration? I triied to build libgem5_debug.so so I can integrate GEM5 in a standalone systemc environment with below commandline: python3 `which scons` --with-cxx-config --without-python --without-tcmalloc USE_SYSTEMC=1 build/RISCV/libgem5_$(BUILD_TYPE).so -j 32 But I got below issue with "--with-cxx-config" option. build/RISCV/cxx_config/Gem5ToTlmBridge32.cc: In member function ‘virtual gem5::SimObject* gem5::Gem5ToTlmBridge32CxxConfigParams::simObjectCreate()’: build/RISCV/cxx_config/Gem5ToTlmBridge32.cc:149:24: error: cannot convert ‘sc_gem5::Gem5ToTlmBridge<32>*’ to ‘gem5::SimObject*’ in return 149 | return this->create(); | ^~ | | | sc_gem5::Gem5ToTlmBridge<32>* if I do without this option, assertion fired in below, complaining: main.cc:280: fatal: Config problem in sim object root: No sim object type Root is available | | G | | ginger...@163.com |___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org
[gem5-users] GEM5 within SystemC build issue
Hello, Anyone went well with GEM5 and SystemC integration? I triied to build libgem5_debug.so so I can integrate GEM5 in a standalone systemc environment with below commandline: python3 `which scons` --with-cxx-config --without-python --without-tcmalloc USE_SYSTEMC=1 build/RISCV/libgem5_$(BUILD_TYPE).so -j 32 But I got below issue with "--with-cxx-config" option. build/RISCV/cxx_config/Gem5ToTlmBridge32.cc: In member function ‘virtual gem5::SimObject* gem5::Gem5ToTlmBridge32CxxConfigParams::simObjectCreate()’: build/RISCV/cxx_config/Gem5ToTlmBridge32.cc:149:24: error: cannot convert ‘sc_gem5::Gem5ToTlmBridge<32>*’ to ‘gem5::SimObject*’ in return 149 | return this->create(); | ^~ | | | sc_gem5::Gem5ToTlmBridge<32>* if I do without this option, assertion fired in below, complaining: main.cc:280: fatal: Config problem in sim object root: No sim object type Root is available | | G | | ginger...@163.com |___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org
[gem5-users] Re: GEM5 dcache dual-porting
Hi Ayaz, Right, in real implementation we wound need dual LQs that can provide double throughput in loading data, and this can require dual DCACHE ports as well, or the throughput will be throttled eventually. Yes seems O3 CPU side we have to change the source code, but anyone know how to do this at Cache/Ruby side? Is it possible only by pythonic configuring? Replied Message | From | Ayaz Akram via gem5-users | | Date | 5/1/2023 04:22 | | To | The gem5 Users mailing list | | Cc | G , Ayaz Akram | | Subject | [gem5-users] Re: GEM5 dcache dual-porting | Hi, Based on my understanding, I think if you configure multiple load functional units that would be equivalent to multiple dcache ports. However, using multiple LQs might require changes in the source code. -Ayaz On Mon, Apr 24, 2023 at 11:42 PM G via gem5-users wrote: Hello, Seems default O3 CPU has single load queue and have single port to dcache, is there way we can configure dual port dcache and have 2 LQs working in parallel? Thanks | | G | | ginger...@163.com | ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org
[gem5-users] GEM5 dcache dual-porting
Hello, Seems default O3 CPU has single load queue and have single port to dcache, is there way we can configure dual port dcache and have 2 LQs working in parallel? Thanks | | G | | ginger...@163.com |___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org
[gem5-users] debugging python code inside GEM5
Hello, GEM5 seems C++ wrapping Python, means C++ is on top. I can easily debug with gdb setting in VSCODE, but anyone knows how to debug into those emeded python codes? Such as se.py? Thanks! | | G | | ginger...@163.com |___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org
[gem5-users] Re: building of different GEM5 binary type
Thanks! | | G | | ginger...@163.com | Replied Message | From | Eliot Moss | | Date | 3/10/2023 21:00 | | To | The gem5 Users mailing list | | Cc | G | | Subject | Re: [gem5-users] Re: building of different GEM5 binary type | On 3/10/2023 2:18 AM, G via gem5-users wrote: Hello, I build binary of *gem5.opt*firstly output at build/RISCV/gem5.opt, then I build another binary of *gem5.debug*, but seems it's still at build/RISCV dir, looks like all the build outputs shares same directories. Even though I ran both with my workloads an they all worked properly, I'm still not sure if this is expected and would not causing any potential conflicting problems, or shall I specify another output directory for different binary flavor? Entirely normal. Opt builds result in gem5.opt, debug in gem5.debug, and fast in gem5.fast. Note that generated .cc and .hh files are shared, but object files are not - opt generates .o, debug generates .do, and fast generates .fo. All happily co-exist. It's perhaps unusual compared with other software with which I have worked, but it functions just fine and has its own logic. Where you get separate directories is for different ISAs (x86 vs RISCV, for example). Cheers - Eliot Moss ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org
[gem5-users] Re: building of different GEM5 binary type
Hello, I build binary of gem5.opt firstly output at build/RISCV/gem5.opt, then I build another binary of gem5.debug, but seems it's still at build/RISCV dir, looks like all the build outputs shares same directories. Even though I ran both with my workloads an they all worked properly, I'm still not sure if this is expected and would not causing any potential conflicting problems, or shall I specify another output directory for different binary flavor? Thanks! g@SH0010211:~/repos/gem5$ ls build/RISCV/ arch config debug enums gem5.build gem5.opt gem5py_m5 kern mem proto SConscript sst base cpu dev ext gem5.debug gem5py gpu-compute learning_gem5 params python sim systemc | | G | | ginger...@163.com |___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org
