[Intel-gfx] Glamor update
Hi folks， During the last discussion about glamor’s plan in this list, we got a conclusion that to extract glamor from xorg and build a separate glamor library to be used by any possible DDX driver. And Eric suggested I can incrementally merge glamor into Intel video driver. Now here is the update. The separate glamor library is at : git://people.freedesktop.org/~gongzg/glamor，it provides two interfaces: 1. glamor : Rendering library. All the rendering functions are implemented in this package. 2. glamor-egl : EGL support library. This package provides functions to create and initialize OpenGL/EGL context. There are a little bit more details to introduce glamor in the README file. The Intel video driver to merge glamor is at git://people.freedesktop.org/~gongzg/xf86-video-intel’s “glamor” branch. I just started the merging stage. Only finished 3 patches to enable glamor in UXA code path. Currently, only migrate fillspans and polyfillrect to glamor. Will continue to migrate the rest functions. I will submit the patches to intel-gfx mail list soon. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/3] glamor: Initial commit to introduce glamor acceleration.
Added one configuration option --enable-glamor to control
whether use glamor. Added one new file intel_glamor.c to
wrap glamor egl API for intel driver's usage.
This commit doesn't really change the driver's control path.
It just adds necessary files for glamor and change some
configuration.
Signed-off-by: Zhigang Gong zhigang.g...@linux.intel.com
---
configure.ac | 17 +++
src/Makefile.am|5 ++
src/intel_glamor.c | 130
src/intel_glamor.h | 45 ++
4 files changed, 197 insertions(+), 0 deletions(-)
create mode 100644 src/intel_glamor.c
create mode 100644 src/intel_glamor.h
diff --git a/configure.ac b/configure.ac
index fccab56..dc01c46 100644
--- a/configure.ac
+++ b/configure.ac
@@ -126,6 +126,15 @@ AC_ARG_ENABLE(sna,
[SNA=$enableval],
[SNA=no])
AM_CONDITIONAL(SNA, test x$SNA != xno)
+
+AC_ARG_ENABLE(glamor,
+ AS_HELP_STRING([--enable-glamor],
+[Enable glamor, a new GL-based acceleration
[default=no]]),
+ [GLAMOR=$enableval],
+ [GLAMOR=no])
+
+AM_CONDITIONAL(GLAMOR, test x$GLAMOR != xno)
+
AC_MSG_CHECKING([whether to include SNA support])
required_xorg_xserver_version=1.6
@@ -137,6 +146,14 @@ if test x$SNA != xno; then
fi
AC_MSG_RESULT([$SNA])
+if test x$GLAMOR != xno; then
+ PKG_CHECK_MODULES(LIBGLAMOR, [glamor])
+ PKG_CHECK_MODULES(LIBGLAMOR_EGL, [glamor-egl])
+ AC_DEFINE(GLAMOR, 1, [Enable glamor acceleration])
+fi
+
+AC_MSG_CHECKING([whether to include GLAMOR support])
+AC_MSG_RESULT([$GLAMOR])
AC_ARG_ENABLE(vmap,
AS_HELP_STRING([--enable-vmap],
diff --git a/src/Makefile.am b/src/Makefile.am
index cd1bb36..1a29390 100644
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -40,6 +40,10 @@ SUBDIRS += sna
intel_drv_la_LIBADD += sna/libsna.la
endif
+if GLAMOR
+GLAMOR_SOURCE = intel_glamor.c
+endif
+
NULL:=#
intel_drv_la_SOURCES = \
@@ -70,6 +74,7 @@ intel_drv_la_SOURCES = \
i965_3d.c \
i965_video.c \
i965_render.c \
+$(GLAMOR_SOURCE) \
$(NULL)
if DRI
diff --git a/src/intel_glamor.c b/src/intel_glamor.c
new file mode 100644
index 000..cadfc71
--- /dev/null
+++ b/src/intel_glamor.c
@@ -0,0 +1,130 @@
+/*
+ * Copyright © 2011 Intel Corporation.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the Software), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including
+ * the next paragraph) shall be included in all copies or substantial
+ * portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *Zhigang Gong zhigang.g...@linux.intel.com
+ *
+ */
+
+#ifdef HAVE_DIX_CONFIG_H
+#include dix-config.h
+#endif
+#include unistd.h
+#include fcntl.h
+#include sys/ioctl.h
+#include errno.h
+#include xf86drm.h
+
+#define GLAMOR_FOR_XORG 1
+
+#include glamor.h
+#include intel.h
+#include intel_glamor.h
+
+Bool
+intel_glamor_create_screen_resources(ScreenPtr screen)
+{
+ ScrnInfoPtr scrn = xf86Screens[screen-myNum];
+ intel_screen_private *intel = intel_get_screen_private(scrn);
+
+ if (!glamor_glyphs_init(screen))
+ return FALSE;
+ if (!glamor_egl_create_textured_screen(screen,
+ intel-front_buffer-handle,
+ intel-front_pitch))
+ return FALSE;
+ return TRUE;
+}
+
+Bool
+intel_glamor_pre_init(ScrnInfoPtr scrn)
+{
+ intel_screen_private *intel;
+ intel = intel_get_screen_private(scrn);
+ return glamor_egl_init(scrn, intel-drmSubFD);
+}
+
+Bool
+intel_glamor_create_textured_pixmap(PixmapPtr pixmap)
+{
+ struct intel_pixmap *priv;
+ priv = intel_get_pixmap_private(pixmap);
+ return glamor_egl_create_textured_pixmap(pixmap, priv-bo-handle,
+priv-stride);
+}
+
+void
+intel_glamor_destroy_pixmap(PixmapPtr pixmap)
+{
+ glamor_egl_destroy_textured_pixmap(pixmap);
+}
+
+Bool
+intel_glamor_init(ScreenPtr screen)
+{
+
[Intel-gfx] [PATCH 3/3] glamor: Route fillspans and polyfillrects to glamor.
If GLAMOR is enabled, we route UXA's fillspans and polyfillrects to glamor by default. And if glamor fail to accelerate it, UXA continue to handle it. Signed-off-by: Zhigang Gong zhigang.g...@linux.intel.com --- uxa/uxa-accel.c | 13 - 1 files changed, 12 insertions(+), 1 deletions(-) diff --git a/uxa/uxa-accel.c b/uxa/uxa-accel.c index 516834f..18fa63b 100644 --- a/uxa/uxa-accel.c +++ b/uxa/uxa-accel.c @@ -27,7 +27,6 @@ *Michel Dänzer mic...@tungstengraphics.com * */ - #ifdef HAVE_DIX_CONFIG_H #include dix-config.h #endif @@ -37,6 +36,10 @@ #include uxa.h #include mipict.h +#ifdef GLAMOR +#include glamor.h +#endif + static void uxa_fill_spans(DrawablePtr pDrawable, GCPtr pGC, int n, DDXPointPtr ppt, int *pwidth, int fSorted) @@ -49,6 +52,10 @@ uxa_fill_spans(DrawablePtr pDrawable, GCPtr pGC, int n, int nbox; int x1, x2, y; int off_x, off_y; +#ifdef GLAMOR + if (glamor_fill_spans_nf(pDrawable, pGC, n, ppt, pwidth, fSorted)) + return; +#endif if (uxa_screen-swappedOut || uxa_screen-force_fallback) goto fallback; @@ -673,6 +680,10 @@ uxa_poly_fill_rect(DrawablePtr pDrawable, int n; RegionPtr pReg = RECTS_TO_REGION(pScreen, nrect, prect, CT_UNSORTED); +#ifdef GLAMOR + if (glamor_poly_fill_rect_nf(pDrawable, pGC, nrect, prect)) + return; +#endif /* Compute intersection of rects and clip region */ REGION_TRANSLATE(pScreen, pReg, pDrawable-x, pDrawable-y); REGION_INTERSECT(pScreen, pReg, pClip, pReg); -- 1.7.4.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v5] drm/i915: pass ELD to HDMI/DP audio driver
At Fri, 11 Nov 2011 16:22:41 +0800, Wu Fengguang wrote: On Fri, Nov 11, 2011 at 03:40:37PM +0800, Takashi Iwai wrote: At Fri, 11 Nov 2011 10:29:25 +0800, Wu Fengguang wrote: On Thu, Nov 10, 2011 at 10:28:19PM +0800, Takashi Iwai wrote: At Thu, 10 Nov 2011 21:51:50 +0800, Wu Fengguang wrote: So maybe the hardware is in some state that is unable to provide the real ELD content? That's my guess as well. I think the hardware may still be doing some form of data negotiation with the HDMI display device at that stage, and doesn't have the copy of the EDID+ELD buffer until a tiny bit later. Possibly? Look at the below dmesg. The ELD seem to available immediately after the DPMS state setting.. Interesting. Does HDMI audio work at all while HDMI DPMS off? It clears SDVO_ENABLE bit, so this might turn off both video and audio? We normally see transient blank screen and silence of audio when switching the video mode. Well, what I suspected is that ELD won't be transferred while SDVO_ENABLE is cleared. It's not about SDVO_ENABLE. The transient ELD invalid state I see in dmesg is caused by the graphics driver doing ELD_Valid = 0 = trigger 1st unsolicited event But why this triggers at *plugging*? Wasn't it zero beforehand? If I understand correctly, changing AUD_CNTL_ST register triggers the HD-audio codec unsol event. Writing even the same value matters? Sorry I assumed the mode switching context. Ah, I see. But this could be suppressed by your patch drm/i915: don't trigger hotplug events on unchanged ELD no? (snip) Depending on the timing, the 1st unsolicited event may see ELD_Valid=0 (if it's fast enough) or ELD_Valid=1 (if the event handling is delayed after the graphics driver sets ELD_Valid=1). I know that because I literally saw both cases happening in dmesg. The 1st hot plug event itself will send ELD_Valid=0, however the audio driver is not trusting this and always do a status query (the HDMI status line) whose result depends on the timing. The problem in this procedure is that this looks as if you are re-connecting the HDMI from the audio-codec POV. The re-connecting events can be distinguished from the video-mode-switching events by the Presence_Detect bit. Hm, OK, so the codec driver can simply ignore (or postpone) the case when the connection is kept but ELD is invalidated. Here is one hot removal event (I just wrote a patch to trigger this), with Presence_Detect=0: One note that we don't rely on PD bit because not all (non-Intel) hardware report it correctly. [ 91.777028] [drm:ironlake_write_eld], ELD on pipe B [ 91.778561] HDMI hot plug event: Codec=3 Pin=6 Presence_Detect=0 ELD_Valid=1 [ 91.783078] HDMI status: Codec=3 Pin=6 Presence_Detect=0 ELD_Valid=0 [ 91.783083] [drm:ironlake_write_eld], Audio directed to unknown port [ 91.783095] [drm:output_poll_execute], [CONNECTOR:12:HDMI-A-2] status updated from 1 to 2 The HDA spec even mentioned doing some timeout mechanism for the Presence_Detect=1 ELD_Valid=0 state. Well it may help some corner cases, but perhaps not an urgent feature. Yeah, this sounds like the workaround for such a case. We might end up with some delayed probe with a dedicated work_struct (because it's bad to have a too long delay in unsol event handler that run on a single workq). Understand. What if the graphics driver can delay the ELD writing (I can try that), so that the audio driver only need to wait for something like 10ms? Or, we can introduce a dirty flag, and set it when ELD is changed, but don't prase ELD contents yet. First upon the next access, the driver updates the status, and clear the dirty flag. We may put a small delay at this update, too. And I'm not sure whether HDMI audio is played while DPMS is off. I haven't tested it. It will go silence on DPMS. I noticed this while doing long term HDMI audio playback tests. This should better be fixed in future on the graphics side. Hm, but I wonder what could be done alternatively. Hopefully there is a register for video-only control... There may be some mode that can keep video off while still keep minimal signals to play HDMI sound? Let's hope :) thanks, Takashi ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] HDMI monitor hot remove handling
I still think you should do those in hot_plug(), to call detect() for
current
status, write eld and set specific audio enable/disable bit for all audio
stuff.
Just my sense, you may send RFC patch for other's comment.
yeah, mode_set() will only be in normal mode setting path and taking current
monitor's audio capability, but not on hot removal path. And if connector's
DPMS off,
does audio need to care? I think no, as user might still like to hear sound,
right? ;)
So looks currently nobody cares for hot removal, you need to set that by
yourself somewhere.
Zhenyu, according to your comments, here is the patch, tested OK on
HDMI :) DP not tested yet.
This notifies the audio driver of the HDMI/DP monitor hot removal
event.
- clear SDVO_AUDIO_ENABLE/DP_AUDIO_OUTPUT_ENABLE
- clear ELD Valid bit
Signed-off-by: Wu Fengguang fengguang...@intel.com
---
drivers/gpu/drm/drm_crtc_helper.c |4
drivers/gpu/drm/i915/intel_dp.c | 19 +++
drivers/gpu/drm/i915/intel_drv.h |4
drivers/gpu/drm/i915/intel_hdmi.c | 17 +
include/drm/drm_crtc.h|1 +
5 files changed, 45 insertions(+)
--- linux.orig/drivers/gpu/drm/i915/intel_dp.c 2011-11-11 16:42:58.0
+0800
+++ linux/drivers/gpu/drm/i915/intel_dp.c 2011-11-11 16:42:59.0
+0800
@@ -1984,6 +1984,24 @@ intel_dp_detect(struct drm_connector *co
return connector_status_connected;
}
+static void intel_dp_hot_remove(struct drm_connector *connector)
+{
+ struct intel_dp *intel_dp = intel_attached_dp(connector);
+ struct drm_device *dev = intel_dp-base.base.dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct drm_crtc *crtc = intel_dp-base.base.crtc;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+
+ intel_dp-DP = ~DP_AUDIO_OUTPUT_ENABLE;
+ I915_WRITE(intel_dp-output_reg, intel_dp-DP);
+ POSTING_READ(intel_dp-output_reg);
+ intel_wait_for_vblank(dev, intel_crtc-pipe);
+
+ connector-eld[0] = 0;
+ if (dev_priv-display.write_eld)
+ dev_priv-display.write_eld(connector, crtc);
+}
+
static int intel_dp_get_modes(struct drm_connector *connector)
{
struct intel_dp *intel_dp = intel_attached_dp(connector);
@@ -2143,6 +2161,7 @@ static const struct drm_connector_funcs
.detect = intel_dp_detect,
.fill_modes = drm_helper_probe_single_connector_modes,
.set_property = intel_dp_set_property,
+ .hot_remove = intel_dp_hot_remove,
.destroy = intel_dp_destroy,
};
--- linux.orig/drivers/gpu/drm/i915/intel_drv.h 2011-11-11 16:42:58.0
+0800
+++ linux/drivers/gpu/drm/i915/intel_drv.h 2011-11-11 16:42:59.0
+0800
@@ -382,6 +382,10 @@ extern void intel_fb_restore_mode(struct
extern void intel_init_clock_gating(struct drm_device *dev);
extern void intel_write_eld(struct drm_encoder *encoder,
struct drm_display_mode *mode);
+extern void intel_hotplug_status(struct drm_device *dev,
+ struct drm_connector *connector,
+ struct drm_crtc *crtc,
+ enum drm_connector_status status);
extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);
#endif /* __INTEL_DRV_H__ */
--- linux.orig/drivers/gpu/drm/i915/intel_hdmi.c2011-11-11
16:42:58.0 +0800
+++ linux/drivers/gpu/drm/i915/intel_hdmi.c 2011-11-11 16:42:59.0
+0800
@@ -352,6 +352,22 @@ intel_hdmi_detect(struct drm_connector *
return status;
}
+static void intel_hdmi_hot_remove(struct drm_connector *connector)
+{
+ struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
+ struct drm_i915_private *dev_priv = connector-dev-dev_private;
+ u32 temp;
+
+ temp = I915_READ(intel_hdmi-sdvox_reg);
+ I915_WRITE(intel_hdmi-sdvox_reg, temp ~SDVO_AUDIO_ENABLE);
+ POSTING_READ(intel_hdmi-sdvox_reg);
+
+ connector-eld[0] = 0;
+ if (dev_priv-display.write_eld)
+ dev_priv-display.write_eld(connector,
+ intel_hdmi-base.base.crtc);
+}
+
static int intel_hdmi_get_modes(struct drm_connector *connector)
{
struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
@@ -461,6 +477,7 @@ static const struct drm_connector_funcs
.detect = intel_hdmi_detect,
.fill_modes = drm_helper_probe_single_connector_modes,
.set_property = intel_hdmi_set_property,
+ .hot_remove = intel_hdmi_hot_remove,
.destroy = intel_hdmi_destroy,
};
--- linux.orig/drivers/gpu/drm/drm_crtc_helper.c2011-11-11
16:42:58.0 +0800
+++ linux/drivers/gpu/drm/drm_crtc_helper.c 2011-11-11 16:42:59.0
+0800
@@ -907,6 +907,10 @@ static void output_poll_execute(struct w
old_status, connector-status);
if (old_status !=
Re: [Intel-gfx] [PATCH 3/3] glamor: Route fillspans and polyfillrects to glamor.
On Fri, 11 Nov 2011 16:31:21 +0800, Zhigang Gong zhigang.g...@linux.intel.com wrote: If GLAMOR is enabled, we route UXA's fillspans and polyfillrects to glamor by default. And if glamor fail to accelerate it, UXA continue to handle it. How is serialisation handled between the UXA and glamor acceleration routines? Don't you need to flush the UXA batch (if the pixmap is active) before handing over to glamor and similarly flush the glamor pixmap after failure? -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/3] glamor: turn on glamor.
On Fri, 11 Nov 2011 16:31:20 +0800, Zhigang Gong zhigang.g...@linux.intel.com wrote: @@ -965,6 +969,9 @@ void intel_uxa_block_handler(intel_screen_private *intel) * framebuffer until significantly later. */ intel_flush_rendering(intel); +#ifdef GLAMOR + intel_glamor_block_handler(intel); +#endif } I suspect this is the wrong way around as we are not flushing the render cache of glamor's rendering to the scanout until the next block handler. In general, try to keep the #ifdef out of the body of the code. In this case, and others, make intel_glamor_block_handler() be a no-op if GLAMOR is not enabled. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v5] drm/i915: pass ELD to HDMI/DP audio driver
On Fri, Nov 11, 2011 at 04:49:57PM +0800, Takashi Iwai wrote: At Fri, 11 Nov 2011 16:22:41 +0800, Wu Fengguang wrote: On Fri, Nov 11, 2011 at 03:40:37PM +0800, Takashi Iwai wrote: At Fri, 11 Nov 2011 10:29:25 +0800, Wu Fengguang wrote: On Thu, Nov 10, 2011 at 10:28:19PM +0800, Takashi Iwai wrote: At Thu, 10 Nov 2011 21:51:50 +0800, Wu Fengguang wrote: So maybe the hardware is in some state that is unable to provide the real ELD content? That's my guess as well. I think the hardware may still be doing some form of data negotiation with the HDMI display device at that stage, and doesn't have the copy of the EDID+ELD buffer until a tiny bit later. Possibly? Look at the below dmesg. The ELD seem to available immediately after the DPMS state setting.. Interesting. Does HDMI audio work at all while HDMI DPMS off? It clears SDVO_ENABLE bit, so this might turn off both video and audio? We normally see transient blank screen and silence of audio when switching the video mode. Well, what I suspected is that ELD won't be transferred while SDVO_ENABLE is cleared. It's not about SDVO_ENABLE. The transient ELD invalid state I see in dmesg is caused by the graphics driver doing ELD_Valid = 0 = trigger 1st unsolicited event But why this triggers at *plugging*? Wasn't it zero beforehand? If I understand correctly, changing AUD_CNTL_ST register triggers the HD-audio codec unsol event. Writing even the same value matters? Sorry I assumed the mode switching context. Ah, I see. But this could be suppressed by your patch drm/i915: don't trigger hotplug events on unchanged ELD no? Mostly. The ELD may still change if the mode switching changes the av-sync-delay field, or suppresses the bandwidth available to audio samples. (snip) Depending on the timing, the 1st unsolicited event may see ELD_Valid=0 (if it's fast enough) or ELD_Valid=1 (if the event handling is delayed after the graphics driver sets ELD_Valid=1). I know that because I literally saw both cases happening in dmesg. The 1st hot plug event itself will send ELD_Valid=0, however the audio driver is not trusting this and always do a status query (the HDMI status line) whose result depends on the timing. The problem in this procedure is that this looks as if you are re-connecting the HDMI from the audio-codec POV. The re-connecting events can be distinguished from the video-mode-switching events by the Presence_Detect bit. Hm, OK, so the codec driver can simply ignore (or postpone) the case when the connection is kept but ELD is invalidated. Yes. Here is one hot removal event (I just wrote a patch to trigger this), with Presence_Detect=0: One note that we don't rely on PD bit because not all (non-Intel) hardware report it correctly. Oops. Do you imply ELDV is reliable on all platforms? ;-) [ 91.777028] [drm:ironlake_write_eld], ELD on pipe B [ 91.778561] HDMI hot plug event: Codec=3 Pin=6 Presence_Detect=0 ELD_Valid=1 [ 91.783078] HDMI status: Codec=3 Pin=6 Presence_Detect=0 ELD_Valid=0 [ 91.783083] [drm:ironlake_write_eld], Audio directed to unknown port [ 91.783095] [drm:output_poll_execute], [CONNECTOR:12:HDMI-A-2] status updated from 1 to 2 The HDA spec even mentioned doing some timeout mechanism for the Presence_Detect=1 ELD_Valid=0 state. Well it may help some corner cases, but perhaps not an urgent feature. Yeah, this sounds like the workaround for such a case. Yeah, your mentioned DVI case may be always in state Presence_Detect=1 ELD_Valid=0 where audio playback should be denied. And there might be the error case that the 2nd event is lost or not generated at all for changing Presence_Detect=1 ELD_Valid=0 to Presence_Detect=1 ELD_Valid=1 We might end up with some delayed probe with a dedicated work_struct (because it's bad to have a too long delay in unsol event handler that run on a single workq). Understand. What if the graphics driver can delay the ELD writing (I can try that), so that the audio driver only need to wait for something like 10ms? Or, we can introduce a dirty flag, and set it when ELD is changed, but don't prase ELD contents yet. First upon the next access, the driver updates the status, and clear the dirty flag. We may put a small delay at this update, too. It should work fine for cat /proc/asound/card0/eld* and other interfaces, however it could still delay the printks' significantly. And it feels not good that accessing ELD may be blocked for some time.. So I now prefer to avoid the msleep totally and schedule a delayed work for parsing ELD. Thanks, Fengguang
Re: [Intel-gfx] [PATCH v5] drm/i915: pass ELD to HDMI/DP audio driver
At Fri, 11 Nov 2011 17:24:21 +0800, Wu Fengguang wrote: On Fri, Nov 11, 2011 at 04:49:57PM +0800, Takashi Iwai wrote: At Fri, 11 Nov 2011 16:22:41 +0800, Wu Fengguang wrote: On Fri, Nov 11, 2011 at 03:40:37PM +0800, Takashi Iwai wrote: At Fri, 11 Nov 2011 10:29:25 +0800, Wu Fengguang wrote: On Thu, Nov 10, 2011 at 10:28:19PM +0800, Takashi Iwai wrote: At Thu, 10 Nov 2011 21:51:50 +0800, Wu Fengguang wrote: So maybe the hardware is in some state that is unable to provide the real ELD content? That's my guess as well. I think the hardware may still be doing some form of data negotiation with the HDMI display device at that stage, and doesn't have the copy of the EDID+ELD buffer until a tiny bit later. Possibly? Look at the below dmesg. The ELD seem to available immediately after the DPMS state setting.. Interesting. Does HDMI audio work at all while HDMI DPMS off? It clears SDVO_ENABLE bit, so this might turn off both video and audio? We normally see transient blank screen and silence of audio when switching the video mode. Well, what I suspected is that ELD won't be transferred while SDVO_ENABLE is cleared. It's not about SDVO_ENABLE. The transient ELD invalid state I see in dmesg is caused by the graphics driver doing ELD_Valid = 0 = trigger 1st unsolicited event But why this triggers at *plugging*? Wasn't it zero beforehand? If I understand correctly, changing AUD_CNTL_ST register triggers the HD-audio codec unsol event. Writing even the same value matters? Sorry I assumed the mode switching context. Ah, I see. But this could be suppressed by your patch drm/i915: don't trigger hotplug events on unchanged ELD no? Mostly. The ELD may still change if the mode switching changes the av-sync-delay field, or suppresses the bandwidth available to audio samples. OK, that's possible. (snip) Depending on the timing, the 1st unsolicited event may see ELD_Valid=0 (if it's fast enough) or ELD_Valid=1 (if the event handling is delayed after the graphics driver sets ELD_Valid=1). I know that because I literally saw both cases happening in dmesg. The 1st hot plug event itself will send ELD_Valid=0, however the audio driver is not trusting this and always do a status query (the HDMI status line) whose result depends on the timing. The problem in this procedure is that this looks as if you are re-connecting the HDMI from the audio-codec POV. The re-connecting events can be distinguished from the video-mode-switching events by the Presence_Detect bit. Hm, OK, so the codec driver can simply ignore (or postpone) the case when the connection is kept but ELD is invalidated. Yes. Here is one hot removal event (I just wrote a patch to trigger this), with Presence_Detect=0: One note that we don't rely on PD bit because not all (non-Intel) hardware report it correctly. Oops. Do you imply ELDV is reliable on all platforms? ;-) Oh hell, no :) The driver tries to probe explicitly via GET_PIN_SENSE HD-audio verb. [ 91.777028] [drm:ironlake_write_eld], ELD on pipe B [ 91.778561] HDMI hot plug event: Codec=3 Pin=6 Presence_Detect=0 ELD_Valid=1 [ 91.783078] HDMI status: Codec=3 Pin=6 Presence_Detect=0 ELD_Valid=0 [ 91.783083] [drm:ironlake_write_eld], Audio directed to unknown port [ 91.783095] [drm:output_poll_execute], [CONNECTOR:12:HDMI-A-2] status updated from 1 to 2 The HDA spec even mentioned doing some timeout mechanism for the Presence_Detect=1 ELD_Valid=0 state. Well it may help some corner cases, but perhaps not an urgent feature. Yeah, this sounds like the workaround for such a case. Yeah, your mentioned DVI case may be always in state Presence_Detect=1 ELD_Valid=0 where audio playback should be denied. And there might be the error case that the 2nd event is lost or not generated at all for changing Presence_Detect=1 ELD_Valid=0 to Presence_Detect=1 ELD_Valid=1 We might end up with some delayed probe with a dedicated work_struct (because it's bad to have a too long delay in unsol event handler that run on a single workq). Understand. What if the graphics driver can delay the ELD writing (I can try that), so that the audio driver only need to wait for something like 10ms? Or, we can introduce a dirty flag, and set it when ELD is changed, but don't prase ELD contents yet. First upon the next access, the driver updates the status, and clear the dirty flag. We may put a small delay at this update, too. It should work fine for cat
Re: [Intel-gfx] [PATCH 3/3] glamor: Route fillspans and polyfillrects to glamor.
-Original Message- From: Chris Wilson [mailto:ch...@chris-wilson.co.uk] Sent: Friday, November 11, 2011 5:08 PM To: Zhigang Gong; intel-gfx@lists.freedesktop.org Subject: Re: [Intel-gfx] [PATCH 3/3] glamor: Route fillspans and polyfillrects to glamor. On Fri, 11 Nov 2011 16:31:21 +0800, Zhigang Gong zhigang.g...@linux.intel.com wrote: If GLAMOR is enabled, we route UXA's fillspans and polyfillrects to glamor by default. And if glamor fail to accelerate it, UXA continue to handle it. How is serialisation handled between the UXA and glamor acceleration routines? Don't you need to flush the UXA batch (if the pixmap is active) before handing over to glamor and similarly flush the glamor pixmap after failure? Thanks for pointing this issue out. This is something I want to be discussed here. There are three types of access to the pixmap: 1. UXA batch command buffer. 2. Glamor through OpenGL 3. CPU access mapped BO buffer. My understanding is that the leading two types has the queue mechanism and need to be handled carefully. In general, we can treat glamor 's access as another batch buffer. Then in the place where current intel driver need to flush UXA batch buffer, we also need to flush the GL operations there. Right? And besides above places we need to flush glamor, we also need to flush UXA batch buffer before call into glamor and also need to flush glamor after the glamor rendering function really touch the pixmap. Any comments? -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/3] glamor: turn on glamor.
-Original Message- From: Chris Wilson [mailto:ch...@chris-wilson.co.uk] Sent: Friday, November 11, 2011 5:12 PM To: Zhigang Gong; intel-gfx@lists.freedesktop.org Subject: Re: [Intel-gfx] [PATCH 2/3] glamor: turn on glamor. On Fri, 11 Nov 2011 16:31:20 +0800, Zhigang Gong zhigang.g...@linux.intel.com wrote: @@ -965,6 +969,9 @@ void intel_uxa_block_handler(intel_screen_private *intel) * framebuffer until significantly later. */ intel_flush_rendering(intel); +#ifdef GLAMOR + intel_glamor_block_handler(intel); +#endif } I suspect this is the wrong way around as we are not flushing the render cache of glamor's rendering to the scanout until the next block handler. I don't understand here. Would you please explain more detail? Thanks. In general, try to keep the #ifdef out of the body of the code. In this case, and others, make intel_glamor_block_handler() be a no-op if GLAMOR is not enabled. Agreed, will fix it next version. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v5] drm/i915: pass ELD to HDMI/DP audio driver
At Fri, 11 Nov 2011 19:12:57 +0800, Wu Fengguang wrote: (snip) One note that we don't rely on PD bit because not all (non-Intel) hardware report it correctly. Oops. Do you imply ELDV is reliable on all platforms? ;-) Oh hell, no :) The driver tries to probe explicitly via GET_PIN_SENSE HD-audio verb. Yeah the below HDMI status:... line. Can we rely on it then? I guess yes. At least, it worked with Nvidia and ATI, too, so far. The point is that the value passed in the codec unsol event is unreliable for some chips. [ 91.777028] [drm:ironlake_write_eld], ELD on pipe B [ 91.778561] HDMI hot plug event: Codec=3 Pin=6 Presence_Detect=0 ELD_Valid=1 [ 91.783078] HDMI status: Codec=3 Pin=6 Presence_Detect=0 ELD_Valid=0 [ 91.783083] [drm:ironlake_write_eld], Audio directed to unknown port [ 91.783095] [drm:output_poll_execute], [CONNECTOR:12:HDMI-A-2] status updated from 1 to 2 The HDA spec even mentioned doing some timeout mechanism for the Presence_Detect=1 ELD_Valid=0 state. Well it may help some corner cases, but perhaps not an urgent feature. Yeah, this sounds like the workaround for such a case. Yeah, your mentioned DVI case may be always in state Presence_Detect=1 ELD_Valid=0 where audio playback should be denied. And there might be the error case that the 2nd event is lost or not generated at all for changing Presence_Detect=1 ELD_Valid=0 to Presence_Detect=1 ELD_Valid=1 We might end up with some delayed probe with a dedicated work_struct (because it's bad to have a too long delay in unsol event handler that run on a single workq). Understand. What if the graphics driver can delay the ELD writing (I can try that), so that the audio driver only need to wait for something like 10ms? Or, we can introduce a dirty flag, and set it when ELD is changed, but don't prase ELD contents yet. First upon the next access, the driver updates the status, and clear the dirty flag. We may put a small delay at this update, too. It should work fine for cat /proc/asound/card0/eld* and other interfaces, however it could still delay the printks' significantly. Well, this reminds me of another question -- do we need these printks unconditionally? Maybe not. How about the attached patch to remove them all? I'm fine with it (better after debugging the ELD problems :) thanks, Takashi ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v5] drm/i915: pass ELD to HDMI/DP audio driver
On Fri, Nov 11, 2011 at 07:23:05PM +0800, Takashi Iwai wrote: At Fri, 11 Nov 2011 19:12:57 +0800, Wu Fengguang wrote: (snip) One note that we don't rely on PD bit because not all (non-Intel) hardware report it correctly. Oops. Do you imply ELDV is reliable on all platforms? ;-) Oh hell, no :) The driver tries to probe explicitly via GET_PIN_SENSE HD-audio verb. Yeah the below HDMI status:... line. Can we rely on it then? I guess yes. At least, it worked with Nvidia and ATI, too, so far. The point is that the value passed in the codec unsol event is unreliable for some chips. Yeah, for example the below HDMI hot plug event. When device is hot removed, Presence_Detect and ELD_Valid both goes 0, but the driver has to clear them one by one. As I choose to disable SDVO_AUDIO_ENABLE first, we see the strange Presence_Detect=0 ELD_Valid=1 combination below. [ 91.777028] [drm:ironlake_write_eld], ELD on pipe B [ 91.778561] HDMI hot plug event: Codec=3 Pin=6 Presence_Detect=0 ELD_Valid=1 [ 91.783078] HDMI status: Codec=3 Pin=6 Presence_Detect=0 ELD_Valid=0 [ 91.783083] [drm:ironlake_write_eld], Audio directed to unknown port [ 91.783095] [drm:output_poll_execute], [CONNECTOR:12:HDMI-A-2] status updated from 1 to 2 The HDA spec even mentioned doing some timeout mechanism for the Presence_Detect=1 ELD_Valid=0 state. Well it may help some corner cases, but perhaps not an urgent feature. Yeah, this sounds like the workaround for such a case. Yeah, your mentioned DVI case may be always in state Presence_Detect=1 ELD_Valid=0 where audio playback should be denied. And there might be the error case that the 2nd event is lost or not generated at all for changing Presence_Detect=1 ELD_Valid=0 to Presence_Detect=1 ELD_Valid=1 We might end up with some delayed probe with a dedicated work_struct (because it's bad to have a too long delay in unsol event handler that run on a single workq). Understand. What if the graphics driver can delay the ELD writing (I can try that), so that the audio driver only need to wait for something like 10ms? Or, we can introduce a dirty flag, and set it when ELD is changed, but don't prase ELD contents yet. First upon the next access, the driver updates the status, and clear the dirty flag. We may put a small delay at this update, too. It should work fine for cat /proc/asound/card0/eld* and other interfaces, however it could still delay the printks' significantly. Well, this reminds me of another question -- do we need these printks unconditionally? Maybe not. How about the attached patch to remove them all? I'm fine with it (better after debugging the ELD problems :) OK, when all the ELD/hotplug stuff calms down. Thanks, Fengguang ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/3] glamor: Initial commit to introduce glamor acceleration.
On Fri, Nov 11, 2011 at 06:31, Zhigang Gong zhigang.g...@linux.intel.comwrote: Added one configuration option --enable-glamor to control whether use glamor. Added one new file intel_glamor.c to wrap glamor egl API for intel driver's usage. This commit doesn't really change the driver's control path. It just adds necessary files for glamor and change some configuration. For the series, I've reviewed the patches and they seem OK for me. I also like the idea of having Glamor available in main ddx branch, for easier testing. So: Reviewed-by: Eugeni Dodonov eugeni.dodo...@intel.com (However, I think Chris will have more comments, he is The Master of the DDX). -- Eugeni Dodonov http://eugeni.dodonov.net/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/3] glamor: turn on glamor.
On Fri, Nov 11, 2011 at 06:31, Zhigang Gong zhigang.g...@linux.intel.comwrote:
@@ -1109,7 +1127,8 @@ static void I830FreeScreen(int scrnIndex, int flags)
{
ScrnInfoPtr scrn = xf86Screens[scrnIndex];
intel_screen_private *intel = intel_get_screen_private(scrn);
-
+#ifdef GLAMOR
+#endif
Empty #ifdef block?
--
Eugeni Dodonov
http://eugeni.dodonov.net/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/3] glamor: turn on glamor.
On Fri, 11 Nov 2011 18:52:11 +0800, Zhigang Gong zhigang.g...@linux.intel.com wrote: -Original Message- From: Chris Wilson [mailto:ch...@chris-wilson.co.uk] Sent: Friday, November 11, 2011 5:12 PM To: Zhigang Gong; intel-gfx@lists.freedesktop.org Subject: Re: [Intel-gfx] [PATCH 2/3] glamor: turn on glamor. On Fri, 11 Nov 2011 16:31:20 +0800, Zhigang Gong zhigang.g...@linux.intel.com wrote: @@ -965,6 +969,9 @@ void intel_uxa_block_handler(intel_screen_private *intel) * framebuffer until significantly later. */ intel_flush_rendering(intel); +#ifdef GLAMOR + intel_glamor_block_handler(intel); +#endif } I suspect this is the wrong way around as we are not flushing the render cache of glamor's rendering to the scanout until the next block handler. I don't understand here. Would you please explain more detail? Thanks. Whenever we render, the data ends up in the Render Cache and needs to be flushed out to memory before it is coherent with the CPU or in this case the Display Engine (i.e. scanout). intel_flush_rendering() does two tasks. The first is to submit any pending batch, and the second is to flush the Render Cache so that the modifications land on the scanout in a timely manner. It is probably best if those two tasks were separated so that we do: intel_uxa_block_handler(intel); // flush the UXA batch intel_glamor_block_handler(intel); // flush the GL batch intel_flush_rendering(intel); // flush the RenderCache to scanout However, you can simply rearrange the code and achieve it with the existing functions: intel_glamor_block_handler(intel); // mark the front bo as dirty as needbe intel_flush_rendering(intel); // flush UXA batch along with RenderCache -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] iommu/intel: Fix build failure with intel-gtt and !intel-iommu
On Fri, 2011-11-11 at 14:48 +0100, Joerg Roedel wrote: +#define intel_iommu_gfx_mapped 1 That ought to be zero; if the IOMMU code isn't present, it's *definitely* not mapped through the IOMMU :) But I'm fairly sure this was already noticed and a patch is on its way upstream already. It's my fault — my original testing patches to expose this information from the IOMMU code did put it into a header file, but when I sent it upstream I missed that part of the patch, thus leading to the horrid 'extern int intel_iommu_gfx_mapped;' in intel-gtt.c that your patch removes. -- dwmw2 smime.p7s Description: S/MIME cryptographic signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: prevent division by zero when asking for chipset power
On Thu, 10 Nov 2011 10:51:26 -0200 Eugeni Dodonov eugeni.dodo...@intel.com wrote: This prevents an in-kernel division by zero which happens when we are asking for i915_chipset_val too quickly, or within a race condition between the power monitoring thread and userspace accesses via debugfs. The issue can be reproduced easily via the following command: while ``; do cat /sys/kernel/debug/dri/0/i915_emon_status; done This is particularly dangerous because it can be triggered by a non-privileged user by just reading the debugfs entry. This issue was also found independently by Konstantin Belousov kostik...@gmail.com, who proposed a similar patch. Reported-by: Konstantin Belousov kostik...@gmail.com Acked-by: Jesse Barnes jbar...@virtuousgeek.org Acked-by: Keith Packard kei...@keithp.com Cc: sta...@vger.kernel.org Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com --- Yep, looks fine, thanks for pushing this Eugeni. -- Jesse Barnes, Intel Open Source Technology Center signature.asc Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] Intel black screen
On 11/10/11 9:12 AM, Paulo J. Matos wrote: Hi, I got a new PC DELL Vostro 360. This is an all-in-one which uses the Optimus setup. An intel GT1 (Sandybridge) couples with an Nvidia 525m. Ubuntu out of the box shows a black screen unless I add nomodeset to kernel options. One of the things I noticed on a standard start (didn't use nomodeset) was that kworker was eating my processor away (this is ubuntu 11.10, kernel 3.0.0-12) but I sorted this out with: # echo N /sys/module/drm_kms_helper/parameters/poll I blacklisted nvidia and nouveau so that my PC wouldn't go crazy with the optimus setup and restarted and still get a blank screen. Xorg on the other hand looks fine (from the logs). So, what I would like it some help in finding why I just get a blank screen. Can I possibly enable more debug information than that available in Xorg.0.log by default? eDP's kind of flaky in some configurations still. Can you attach your video BIOS so we can see how it's hooked up? $ sudo dd if=/dev/mem of=/tmp/rom bs=64k skip=12 count=1 - ajax ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 9/9] drm/i915: swizzling support for snb/ivb
On Thu, 10 Nov 2011 14:18:07 +0100, Daniel Vetter daniel.vet...@ffwll.ch
wrote:
We have to do this manually. Somebody had a Great Idea.
Signed-Off-by: Daniel Vetter daniel.vet...@ffwll.ch
People playing with this when not strictly required is scary to me.
Manually swizzling was a world of hurt. I got to play with things like
when the management engine is enabled, it carves out the top N MB of
one of the dimms, and the corresponding N MB of the other dimm doesn't
get swizzled, and you lose.
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c
b/drivers/gpu/drm/i915/i915_gem_tiling.c
index 861223b..af0a2fc 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -93,8 +93,20 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
if (INTEL_INFO(dev)-gen = 6) {
- swizzle_x = I915_BIT_6_SWIZZLE_NONE;
- swizzle_y = I915_BIT_6_SWIZZLE_NONE;
+ uint32_t dimm_c0, dimm_c1;
+ dimm_c0 = I915_READ(MAD_DIMM_C0);
+ dimm_c1 = I915_READ(MAD_DIMM_C1);
+ dimm_c0 = MAD_DIMM_A_SIZE_MASK | MAD_DIMM_A_SIZE_MASK;
+ dimm_c1 = MAD_DIMM_A_SIZE_MASK | MAD_DIMM_A_SIZE_MASK;
+ /* Enable swizzling when the channels are populated with
+ * identically sized dimms. */
+ if (dimm_c0 == dimm_c1) {
+ swizzle_x = I915_BIT_6_SWIZZLE_9_10;
+ swizzle_y = I915_BIT_6_SWIZZLE_9;
+ } else {
+ swizzle_x = I915_BIT_6_SWIZZLE_NONE;
+ swizzle_y = I915_BIT_6_SWIZZLE_NONE;
+ }
} else if (IS_GEN5(dev)) {
/* On Ironlake whatever DRAM config, GPU always do
* same swizzling setup.
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0a0b6b1..a62fa95 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -327,6 +327,8 @@
#define ARB_MODE 0x04030
#define ARB_MODE_SWIZZLE_SNB (14)
#define ARB_MODE_SWIZZLE_IVB (15)
+#define ARB_MODE_ENABLE(x) GFX_MODE_ENABLE(x)
+#define ARB_MODE_DISABLE(x)GFX_MODE_DISABLE(x)
#define RENDER_HWS_PGA_GEN7 (0x04080)
#define BSD_HWS_PGA_GEN7 (0x04180)
#define BLT_HWS_PGA_GEN7 (0x04280)
pgp8AJPTIOvVa.pgp
Description: PGP signature
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 9/9] drm/i915: swizzling support for snb/ivb
On Fri, 11 Nov 2011 18:22:25 +0100, Daniel Vetter dan...@ffwll.ch wrote: On Fri, Nov 11, 2011 at 08:50:30AM -0800, Eric Anholt wrote: On Thu, 10 Nov 2011 14:18:07 +0100, Daniel Vetter daniel.vet...@ffwll.ch wrote: We have to do this manually. Somebody had a Great Idea. Signed-Off-by: Daniel Vetter daniel.vet...@ffwll.ch People playing with this when not strictly required is scary to me. Manually swizzling was a world of hurt. I got to play with things like when the management engine is enabled, it carves out the top N MB of one of the dimms, and the corresponding N MB of the other dimm doesn't get swizzled, and you lose. Looks like yet another patch series of mine that scares away people ... Would this patch be less scary when we have a test that slurps in the entire ram to quickly diagnose such issues? We can then either revert this or fix up the detection to not enable swizzling in such cases. Also the manually swizzling is a world of hurt argument is pretty void: Up to very recent kernels we've advertised bit9 swizzling on snb+ without any swizzling actually going on. So userspace clearly doesn't rely on this anymore (the issue was caught by running the pread tests in i-g-t). I was assuming you were working on this because you were planning on building something that *used* this swizzling. We removed all the userland because we never got it to actually work. pgpaNFfNGDdW1.pgp Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 9/9] drm/i915: swizzling support for snb/ivb
On Fri, 11 Nov 2011 20:51:35 +0100, Daniel Vetter dan...@ffwll.ch wrote: On Fri, Nov 11, 2011 at 20:37, Eric Anholt e...@anholt.net wrote: I was assuming you were working on this because you were planning on building something that *used* this swizzling. We removed all the userland because we never got it to actually work. I have started to look into the swizzle test because we absolutely need correct swizzle information for swapout/in. Doing a pread/pwrite instead of forcing the machine to swap simply gets the results much quicker (but I plan to have a separate swap test, too). While wrestling around with swizzling I've just added in the gen6+ stuff here, which I've noticed a while back on bspec review. And it indeed seems to speed things up a wee bit. I certainly don't plan to use this swizzle information in real userspace clients ;-) but hopefully this work leads to a more correct swap code. Oh, yeah, swap. Good point, sounds like a plan. If you manage to get reliable swapping of tiled data on 945g, I'll owe you all the beers. (But not if you use the blitter to untile for swapping or something. That would just be cheating) pgp98bRG9yDiN.pgp Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: there is no pipe CxSR on ironlake
After checking the specs and discussing with Jesse, turns out CxSR is not
available on Ironlake and gen5, and its advertisement on the device
description is misleading.
Acked-by: Jesse Barnes jbar...@virtuousgeek.org
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/i915_drv.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index f07e425..e9349ca 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -197,7 +197,7 @@ static const struct intel_device_info intel_pineview_info =
{
static const struct intel_device_info intel_ironlake_d_info = {
.gen = 5,
- .need_gfx_hws = 1, .has_pipe_cxsr = 1, .has_hotplug = 1,
+ .need_gfx_hws = 1, .has_hotplug = 1,
.has_bsd_ring = 1,
};
--
1.7.7.2
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 9/9] drm/i915: swizzling support for snb/ivb
On Fri, Nov 11, 2011 at 20:58, Eric Anholt e...@anholt.net wrote: Oh, yeah, swap. Good point, sounds like a plan. If you manage to get reliable swapping of tiled data on 945g, I'll owe you all the beers. If you mean i945G as in desktop variant, patch 6/9 should fix the swizzle detection on that one - it can do bit17 swizzling, too. I'd be interested in whether this fixes all the swap issues, if you have that machine still around ... But as I've said there's also the gm45 bug which looks like a part of the main memory in not swizzled. On that topic: Do you still remember details about that machine where parts of the memory can be unswizzled? -Daniel -- Daniel Vetter daniel.vet...@ffwll.ch - +41 (0) 79 364 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: don't set unpin_work if vblank_get fails
On Mon, 19 Sep 2011 21:04:36 -0700 Keith Packard kei...@keithp.com wrote: On Mon, 29 Aug 2011 09:45:28 -0700, Jesse Barnes jbar...@virtuousgeek.org wrote: With patch... It's been a couple of weeks; this patch is ready to merge, yes? Is there a commit message somewhere? Yeah higher up in the message... we should probably get this committed now if people are ok with it. -- Jesse Barnes, Intel Open Source Technology Center signature.asc Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2] drivers: i915: Default backlight PWM frequency
Hi,
A collection of nits below.
Thanks,
-Olof
On Thu, Nov 10, 2011 at 07:48:55PM -0800, Simon Que wrote:
If the firmware did not initialize the backlight PWM registers, set up a
default PWM frequency of 200 Hz. This is determined using the following
formula:
freq = refclk / (128 * pwm_max)
The PWM register allows the max PWM value to be set. So we want to use
the formula, where freq = 200:
pwm_max = refclk / (128 * freq)
This patch will, in the case of missing PWM register initialization
values, look for the reference clock frequency. Based on that, it sets
an appropriate max PWM value for a frequency of 200 Hz.
If no refclk frequency is found, the max PWM will be zero, which results
in no change to the PWM registers.
Signed-off-by: Simon Que s...@chromium.org
---
drivers/gpu/drm/i915/i915_reg.h|1 +
drivers/gpu/drm/i915/intel_panel.c | 37 +--
2 files changed, 31 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5d5def7..a832028 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3275,6 +3275,7 @@
#define PWM_POLARITY_ACTIVE_HIGH2 (0 28)
#define BLC_PWM_PCH_CTL2 0xc8254
+#define BLC_PWM_PCH_FREQ_SHIFT 16
#define PCH_PP_STATUS0xc7200
#define PCH_PP_CONTROL 0xc7204
diff --git a/drivers/gpu/drm/i915/intel_panel.c
b/drivers/gpu/drm/i915/intel_panel.c
index f15388c..f865e52 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -32,6 +32,10 @@
#define PCI_LBPC 0xf4 /* legacy/combination backlight modes */
+/* For computing default PWM settings */
+#define DEFAULT_BACKLIGHT_PWM_FREQ 200
+#define BACKLIGHT_REFCLK_DIVISOR 128
I would a bit more comment above. Maybe something like:
/* These are used to calculate a reasonable default when firmware has not
* configured a maximum PWM frequency, with 200Hz as current target.
*/
+
void
intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
struct drm_display_mode *adjusted_mode)
@@ -129,12 +133,31 @@ static int is_backlight_combination_mode(struct
drm_device *dev)
return 0;
}
+static u32 i915_get_default_max_backlight(struct drm_i915_private *dev_priv)
Having a 'get' function that has side effects is misleading.
'i915_set_default_max_backlight' is a better name (and not returning the new
max).
+{
+ u32 refclk_freq_mhz = 0;
+ u32 max_pwm = 0;
No need to set max_pwm to 0.
Empty line between variables and code.
+ if (HAS_PCH_SPLIT(dev_priv-dev))
+ refclk_freq_mhz = I915_READ(PCH_RAWCLK_FREQ) RAWCLK_FREQ_MASK;
+ else if (dev_priv-lvds_use_ssc)
+ refclk_freq_mhz = dev_priv-lvds_ssc_freq;
+
+ max_pwm = refclk_freq_mhz * 100 /
+ (BACKLIGHT_REFCLK_DIVISOR * DEFAULT_BACKLIGHT_PWM_FREQ);
+
+ if (HAS_PCH_SPLIT(dev_priv-dev))
+ dev_priv-saveBLC_PWM_CTL2 = max_pwm BLC_PWM_PCH_FREQ_SHIFT;
+ else
+ dev_priv-saveBLC_PWM_CTL = max_pwm
+ BACKLIGHT_MODULATION_FREQ_SHIFT;
+ return max_pwm;
+}
+
static u32 i915_read_blc_pwm_ctl(struct drm_i915_private *dev_priv)
{
u32 val;
- /* Restore the CTL value if it lost, e.g. GPU reset */
-
+ /* Restore the CTL value if it was lost, e.g. GPU reset */
if (HAS_PCH_SPLIT(dev_priv-dev)) {
val = I915_READ(BLC_PWM_PCH_CTL2);
if (dev_priv-saveBLC_PWM_CTL2 == 0) {
@@ -168,11 +191,11 @@ u32 intel_panel_get_max_backlight(struct drm_device
*dev)
max = i915_read_blc_pwm_ctl(dev_priv);
if (max == 0) {
- /* XXX add code here to query mode clock or hardware clock
- * and program max PWM appropriately.
- */
- printk_once(KERN_WARNING fixme: max PWM is zero.\n);
- return 1;
+ /* If backlight PWM registers have not been set, set them to */
+ /* default backlight PWM settings. */
/* Kernel multi-line comment style
* is like this.
*/
+ max = i915_get_default_max_backlight(dev_priv);
+ i915_read_blc_pwm_ctl(dev_priv);
max = i915_read_..
+ return max;
If you return here you won't be doing the same math as below, that looks like
a bug.
}
if (HAS_PCH_SPLIT(dev)) {
-Olof
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3] drivers: i915: Default backlight PWM frequency
If the firmware did not initialize the backlight PWM registers, set up a
default PWM frequency of 200 Hz. This is determined using the following
formula:
freq = refclk / (128 * pwm_max)
The PWM register allows the max PWM value to be set. So we want to use
the formula, where freq = 200:
pwm_max = refclk / (128 * freq)
This patch will, in the case of missing PWM register initialization
values, look for the reference clock frequency. Based on that, it sets
an appropriate max PWM value for a frequency of 200 Hz.
If no refclk frequency is found, the max PWM will be zero, which results
in no change to the PWM registers.
Signed-off-by: Simon Que s...@chromium.org
To: intel-gfx@lists.freedesktop.org
To: Jesse Barnes jbar...@virtuousgeek.org
To: Chris Wilson ch...@chris-wilson.co.uk
To: Eric Anholt e...@anholt.net
To: Matthew Garrett mj...@srcf.ucam.org
Cc: Olof Johansson ol...@chromium.org
Cc: Bryan Freed bfr...@chromium.org
Cc: Sameer Nanda sna...@chromium.org
---
drivers/gpu/drm/i915/intel_panel.c | 36 ++--
1 files changed, 30 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_panel.c
b/drivers/gpu/drm/i915/intel_panel.c
index f15388c..98439b3 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -32,6 +32,10 @@
#define PCI_LBPC 0xf4 /* legacy/combination backlight modes */
+/* For computing default PWM settings */
+#define DEFAULT_BACKLIGHT_PWM_FREQ 200
+#define BACKLIGHT_REFCLK_DIVISOR 128
+
void
intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
struct drm_display_mode *adjusted_mode)
@@ -129,12 +133,32 @@ static int is_backlight_combination_mode(struct
drm_device *dev)
return 0;
}
+static void i915_set_default_max_backlight(struct drm_i915_private *dev_priv)
+{
+ u32 refclk_freq_mhz = 0;
+ u32 max_pwm;
+
+ if (HAS_PCH_SPLIT(dev_priv-dev))
+ refclk_freq_mhz = I915_READ(PCH_RAWCLK_FREQ) RAWCLK_FREQ_MASK;
+ else if (dev_priv-lvds_use_ssc)
+ refclk_freq_mhz = dev_priv-lvds_ssc_freq;
+
+ max_pwm = refclk_freq_mhz * 100 /
+ (BACKLIGHT_REFCLK_DIVISOR * DEFAULT_BACKLIGHT_PWM_FREQ);
+
+ if (HAS_PCH_SPLIT(dev_priv-dev))
+ dev_priv-saveBLC_PWM_CTL2 = max_pwm 16;
+ else if (IS_PINEVIEW(dev_priv-dev))
+ dev_priv-saveBLC_PWM_CTL = max_pwm 17;
+ else
+ dev_priv-saveBLC_PWM_CTL = max_pwm 16;
+}
+
static u32 i915_read_blc_pwm_ctl(struct drm_i915_private *dev_priv)
{
u32 val;
- /* Restore the CTL value if it lost, e.g. GPU reset */
-
+ /* Restore the CTL value if it was lost, e.g. GPU reset */
if (HAS_PCH_SPLIT(dev_priv-dev)) {
val = I915_READ(BLC_PWM_PCH_CTL2);
if (dev_priv-saveBLC_PWM_CTL2 == 0) {
@@ -168,11 +192,11 @@ u32 intel_panel_get_max_backlight(struct drm_device *dev)
max = i915_read_blc_pwm_ctl(dev_priv);
if (max == 0) {
- /* XXX add code here to query mode clock or hardware clock
-* and program max PWM appropriately.
+ /* If backlight PWM registers have not been set, set them to
+* default backlight PWM settings.
*/
- printk_once(KERN_WARNING fixme: max PWM is zero.\n);
- return 1;
+ i915_set_default_max_backlight(dev_priv);
+ max = i915_read_blc_pwm_ctl(dev_priv);
}
if (HAS_PCH_SPLIT(dev)) {
--
1.7.2.3
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v4] drivers: i915: Default backlight PWM frequency
If the firmware did not initialize the backlight PWM registers, set up a
default PWM frequency of 200 Hz. This is determined using the following
formula:
freq = refclk / (128 * pwm_max)
The PWM register allows the max PWM value to be set. So we want to use
the formula, where freq = 200:
pwm_max = refclk / (128 * freq)
This patch will, in the case of missing PWM register initialization
values, look for the reference clock frequency. Based on that, it sets
an appropriate max PWM value for a frequency of 200 Hz.
If no refclk frequency is found, the max PWM will be zero, which results
in no change to the PWM registers.
Signed-off-by: Simon Que s...@chromium.org
---
drivers/gpu/drm/i915/intel_panel.c | 38 ++-
1 files changed, 32 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_panel.c
b/drivers/gpu/drm/i915/intel_panel.c
index f15388c..dda5de2 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -32,6 +32,12 @@
#define PCI_LBPC 0xf4 /* legacy/combination backlight modes */
+/* These are used to calculate a reasonable default when firmware has not
+ * configured a maximum PWM frequency, with 200Hz as the current default
target.
+ */
+#define DEFAULT_BACKLIGHT_PWM_FREQ 200
+#define BACKLIGHT_REFCLK_DIVISOR 128
+
void
intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
struct drm_display_mode *adjusted_mode)
@@ -129,12 +135,32 @@ static int is_backlight_combination_mode(struct
drm_device *dev)
return 0;
}
+static void i915_set_default_max_backlight(struct drm_i915_private *dev_priv)
+{
+ u32 refclk_freq_mhz = 0;
+ u32 max_pwm;
+
+ if (HAS_PCH_SPLIT(dev_priv-dev))
+ refclk_freq_mhz = I915_READ(PCH_RAWCLK_FREQ) RAWCLK_FREQ_MASK;
+ else if (dev_priv-lvds_use_ssc)
+ refclk_freq_mhz = dev_priv-lvds_ssc_freq;
+
+ max_pwm = refclk_freq_mhz * 100 /
+ (BACKLIGHT_REFCLK_DIVISOR * DEFAULT_BACKLIGHT_PWM_FREQ);
+
+ if (HAS_PCH_SPLIT(dev_priv-dev))
+ dev_priv-saveBLC_PWM_CTL2 = max_pwm 16;
+ else if (IS_PINEVIEW(dev_priv-dev))
+ dev_priv-saveBLC_PWM_CTL = max_pwm 17;
+ else
+ dev_priv-saveBLC_PWM_CTL = max_pwm 16;
+}
+
static u32 i915_read_blc_pwm_ctl(struct drm_i915_private *dev_priv)
{
u32 val;
- /* Restore the CTL value if it lost, e.g. GPU reset */
-
+ /* Restore the CTL value if it was lost, e.g. GPU reset */
if (HAS_PCH_SPLIT(dev_priv-dev)) {
val = I915_READ(BLC_PWM_PCH_CTL2);
if (dev_priv-saveBLC_PWM_CTL2 == 0) {
@@ -168,11 +194,11 @@ u32 intel_panel_get_max_backlight(struct drm_device *dev)
max = i915_read_blc_pwm_ctl(dev_priv);
if (max == 0) {
- /* XXX add code here to query mode clock or hardware clock
-* and program max PWM appropriately.
+ /* If backlight PWM registers have not been set, set them to
+* default backlight PWM settings.
*/
- printk_once(KERN_WARNING fixme: max PWM is zero.\n);
- return 1;
+ i915_set_default_max_backlight(dev_priv);
+ max = i915_read_blc_pwm_ctl(dev_priv);
}
if (HAS_PCH_SPLIT(dev)) {
--
1.7.2.3
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4] drivers: i915: Default backlight PWM frequency
On Fri, Nov 11, 2011 at 02:12:58PM -0800, Simon Que wrote: If the firmware did not initialize the backlight PWM registers, set up a default PWM frequency of 200 Hz. This is determined using the following formula: freq = refclk / (128 * pwm_max) The PWM register allows the max PWM value to be set. So we want to use the formula, where freq = 200: pwm_max = refclk / (128 * freq) This patch will, in the case of missing PWM register initialization values, look for the reference clock frequency. Based on that, it sets an appropriate max PWM value for a frequency of 200 Hz. If no refclk frequency is found, the max PWM will be zero, which results in no change to the PWM registers. Signed-off-by: Simon Que s...@chromium.org Acked-by: Olof Johansson o...@lixom.net Looks much better. I'm OK with this solution. Matthew? -Olof ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v4] drivers: i915: Default backlight PWM frequency
On Fri, Nov 11, 2011 at 02:17:20PM -0800, Olof Johansson wrote: On Fri, Nov 11, 2011 at 02:12:58PM -0800, Simon Que wrote: If the firmware did not initialize the backlight PWM registers, set up a default PWM frequency of 200 Hz. This is determined using the following formula: freq = refclk / (128 * pwm_max) The PWM register allows the max PWM value to be set. So we want to use the formula, where freq = 200: pwm_max = refclk / (128 * freq) This patch will, in the case of missing PWM register initialization values, look for the reference clock frequency. Based on that, it sets an appropriate max PWM value for a frequency of 200 Hz. If no refclk frequency is found, the max PWM will be zero, which results in no change to the PWM registers. Signed-off-by: Simon Que s...@chromium.org Acked-by: Olof Johansson o...@lixom.net Looks much better. I'm OK with this solution. Matthew? I'd still prefer this to come from the firmware in some way, but in the absence of the awesome let's go with the good. Acked-by: Matthew Garrett m...@redhat.com -- Matthew Garrett | mj...@srcf.ucam.org ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v5] drm/i915: pass ELD to HDMI/DP audio driver
(snip) And I'm not sure whether HDMI audio is played while DPMS is off. I haven't tested it. It will go silence on DPMS. I noticed this while doing long term HDMI audio playback tests. This should better be fixed in future on the graphics side. Hm, but I wonder what could be done alternatively. Hopefully there is a register for video-only control... There may be some mode that can keep video off while still keep minimal signals to play HDMI sound? Let's hope :) Looks very possible, here is the clue of hardware support: TRANS_DP_CTL - Transcoder DisplayPort Control bit 26: Transcoder DP Audio Only Mode Thanks, Fengguang ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 00/18] intel-gpu-tools: intel_audio_dump updates
A bunch of cleanups, fixes and new fields to intel_audio_dump, tested OK on G45, Ironlake and IvyBridge. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 02/18] intel_audio_dump: cleanup ACP DIP name for ironlake and CPT
Signed-off-by: Wu Fengguang fengguang...@intel.com --- tools/intel_audio_dump.c | 16 1 file changed, 8 insertions(+), 8 deletions(-) --- intel-gpu-tools.orig/tools/intel_audio_dump.c 2011-11-12 11:00:39.0 +0800 +++ intel-gpu-tools/tools/intel_audio_dump.c2011-11-12 11:01:08.0 +0800 @@ -666,7 +666,7 @@ static void dump_ironlake(void) printf(AUD_CNTL_ST_A DIP_Port_Select\t\t\t\t[%#lx] %s\n, BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]); printf(AUD_CNTL_ST_A DIP_type_enable_status Audio DIP\t\t%lu\n, BIT(dword, 21)); -printf(AUD_CNTL_ST_A DIP_type_enable_status Generic 1 ACP DIP\t%lu\n, BIT(dword, 22)); +printf(AUD_CNTL_ST_A DIP_type_enable_status ACP DIP\t\t%lu\n, BIT(dword, 22)); printf(AUD_CNTL_ST_A DIP_type_enable_status Generic 2 DIP\t%lu\n, BIT(dword, 23)); printf(AUD_CNTL_ST_A DIP_transmission_frequency\t\t[0x%lx] %s\n, BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]); @@ -677,7 +677,7 @@ static void dump_ironlake(void) printf(AUD_CNTL_ST_B DIP_Port_Select\t\t\t\t[%#lx] %s\n, BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]); printf(AUD_CNTL_ST_B DIP_type_enable_status Audio DIP\t\t%lu\n, BIT(dword, 21)); -printf(AUD_CNTL_ST_B DIP_type_enable_status Generic 1 ACP DIP\t%lu\n, BIT(dword, 22)); +printf(AUD_CNTL_ST_B DIP_type_enable_status ACP DIP\t\t%lu\n, BIT(dword, 22)); printf(AUD_CNTL_ST_B DIP_type_enable_status Generic 2 DIP\t%lu\n, BIT(dword, 23)); printf(AUD_CNTL_ST_B DIP_transmission_frequency\t\t[0x%lx] %s\n, BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]); @@ -1068,8 +1068,8 @@ static void dump_cpt(void) dword = INREG(AUD_CNTL_ST_A); printf(AUD_CNTL_ST_A DIP_Port_Select\t\t\t\t[%#lx] %s\n, BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]); -printf(AUD_CNTL_ST_A DIP_type_enable_status Audio DIP\t\t%lu\n, BIT(dword, 21)); -printf(AUD_CNTL_ST_A DIP_type_enable_status Generic 1 ACP DIP\t%lu\n, BIT(dword, 22)); +printf(AUD_CNTL_ST_A DIP_type_enable_status Audio DIP\t%lu\n, BIT(dword, 21)); +printf(AUD_CNTL_ST_A DIP_type_enable_status ACP DIP\t\t%lu\n, BIT(dword, 22)); printf(AUD_CNTL_ST_A DIP_type_enable_status Generic 2 DIP\t%lu\n, BIT(dword, 23)); printf(AUD_CNTL_ST_A DIP_transmission_frequency\t\t[0x%lx] %s\n, BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]); @@ -1079,8 +1079,8 @@ static void dump_cpt(void) dword = INREG(AUD_CNTL_ST_B); printf(AUD_CNTL_ST_B DIP_Port_Select\t\t\t\t[%#lx] %s\n, BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]); -printf(AUD_CNTL_ST_B DIP_type_enable_status Audio DIP\t\t%lu\n, BIT(dword, 21)); -printf(AUD_CNTL_ST_B DIP_type_enable_status Generic 1 ACP DIP\t%lu\n, BIT(dword, 22)); +printf(AUD_CNTL_ST_B DIP_type_enable_status Audio DIP\t%lu\n, BIT(dword, 21)); +printf(AUD_CNTL_ST_B DIP_type_enable_status ACP DIP\t\t%lu\n, BIT(dword, 22)); printf(AUD_CNTL_ST_B DIP_type_enable_status Generic 2 DIP\t%lu\n, BIT(dword, 23)); printf(AUD_CNTL_ST_B DIP_transmission_frequency\t\t[0x%lx] %s\n, BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]); @@ -1090,8 +1090,8 @@ static void dump_cpt(void) dword = INREG(AUD_CNTL_ST_C); printf(AUD_CNTL_ST_C DIP_Port_Select\t\t\t\t[%#lx] %s\n, BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]); -printf(AUD_CNTL_ST_C DIP_type_enable_status Audio DIP\t\t%lu\n, BIT(dword, 21)); -printf(AUD_CNTL_ST_C DIP_type_enable_status Generic 1 ACP DIP\t%lu\n, BIT(dword, 22)); +printf(AUD_CNTL_ST_C DIP_type_enable_status Audio DIP\t%lu\n, BIT(dword, 21)); +printf(AUD_CNTL_ST_C DIP_type_enable_status ACP DIP\t\t%lu\n, BIT(dword, 22)); printf(AUD_CNTL_ST_C DIP_type_enable_status Generic 2 DIP\t%lu\n, BIT(dword, 23)); printf(AUD_CNTL_ST_C DIP_transmission_frequency\t\t[0x%lx] %s\n, BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]); ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 01/18] intel_audio_dump: cleanup hyphen character
Convert  (Hex 00ad) to - (Hex 2d), the former leads to ugly outputs in some situations. Signed-off-by: Wu Fengguang fengguang...@intel.com --- tools/intel_audio_dump.c | 70 ++--- 1 file changed, 35 insertions(+), 35 deletions(-) --- intel-gpu-tools.orig/tools/intel_audio_dump.c 2011-11-12 11:01:19.0 +0800 +++ intel-gpu-tools/tools/intel_audio_dump.c2011-11-12 11:01:26.0 +0800 @@ -495,31 +495,31 @@ static void dump_ironlake(void) dump_reg(HDMIB,sDVO/HDMI Port B Control); dump_reg(HDMIC,HDMI Port C Control); dump_reg(HDMID,HDMI Port D Control); -dump_reg(AUD_CONFIG_A, Audio Configuration  Transcoder A); -dump_reg(AUD_CONFIG_B, Audio Configuration  Transcoder B); -dump_reg(AUD_CTS_ENABLE_A, Audio CTS Programming Enable  Transcoder A); -dump_reg(AUD_CTS_ENABLE_B, Audio CTS Programming Enable  Transcoder B); +dump_reg(AUD_CONFIG_A, Audio Configuration - Transcoder A); +dump_reg(AUD_CONFIG_B, Audio Configuration - Transcoder B); +dump_reg(AUD_CTS_ENABLE_A, Audio CTS Programming Enable - Transcoder A); +dump_reg(AUD_CTS_ENABLE_B, Audio CTS Programming Enable - Transcoder B); dump_reg(AUD_MISC_CTRL_A, Audio MISC Control for Transcoder A); dump_reg(AUD_MISC_CTRL_B, Audio MISC Control for Transcoder B); dump_reg(AUD_VID_DID, Audio Vendor ID / Device ID); dump_reg(AUD_RID, Audio Revision ID); dump_reg(AUD_PWRST,Audio Power State (Function Group, Convertor, Pin Widget)); dump_reg(AUD_PORT_EN_HD_CFG, Audio Port Enable HDAudio Config); -dump_reg(AUD_OUT_DIG_CNVT_A, Audio Digital Converter  Conv A); -dump_reg(AUD_OUT_DIG_CNVT_B, Audio Digital Converter  Conv B); +dump_reg(AUD_OUT_DIG_CNVT_A, Audio Digital Converter - Conv A); +dump_reg(AUD_OUT_DIG_CNVT_B, Audio Digital Converter - Conv B); dump_reg(AUD_OUT_CH_STR, Audio Channel ID and Stream ID); -dump_reg(AUD_OUT_STR_DESC_A, Audio Stream Descriptor Format  Conv A); -dump_reg(AUD_OUT_STR_DESC_B, Audio Stream Descriptor Format  Conv B); +dump_reg(AUD_OUT_STR_DESC_A, Audio Stream Descriptor Format - Conv A); +dump_reg(AUD_OUT_STR_DESC_B, Audio Stream Descriptor Format - Conv B); dump_reg(AUD_PINW_CONNLNG_LIST,Audio Connection List); dump_reg(AUD_PINW_CONNLNG_SEL, Audio Connection Select); -dump_reg(AUD_CNTL_ST_A,Audio Control State Register  Transcoder A); -dump_reg(AUD_CNTL_ST_B,Audio Control State Register  Transcoder B); +dump_reg(AUD_CNTL_ST_A,Audio Control State Register - Transcoder A); +dump_reg(AUD_CNTL_ST_B,Audio Control State Register - Transcoder B); dump_reg(AUD_CNTL_ST2, Audio Control State 2); dump_reg(AUD_HDMIW_STATUS, Audio HDMI Status); -dump_reg(AUD_HDMIW_HDMIEDID_A, HDMI Data EDID Block  Transcoder A); -dump_reg(AUD_HDMIW_HDMIEDID_B, HDMI Data EDID Block  Transcoder B); -dump_reg(AUD_HDMIW_INFOFR_A, Audio Widget Data Island Packet  Transcoder A); -dump_reg(AUD_HDMIW_INFOFR_B, Audio Widget Data Island Packet  Transcoder B); +dump_reg(AUD_HDMIW_HDMIEDID_A, HDMI Data EDID Block - Transcoder A); +dump_reg(AUD_HDMIW_HDMIEDID_B, HDMI Data EDID Block - Transcoder B); +dump_reg(AUD_HDMIW_INFOFR_A, Audio Widget Data Island Packet - Transcoder A); +dump_reg(AUD_HDMIW_INFOFR_B, Audio Widget Data Island Packet - Transcoder B); printf(\nDetails:\n\n); @@ -825,12 +825,12 @@ static void dump_cpt(void) dump_reg(HDMIB,sDVO/HDMI Port B Control); dump_reg(HDMIC,HDMI Port C Control); dump_reg(HDMID,HDMI Port D Control); -dump_reg(AUD_CONFIG_A, Audio Configuration  Transcoder A); -dump_reg(AUD_CONFIG_B, Audio Configuration  Transcoder B); -dump_reg(AUD_CONFIG_C, Audio Configuration  Transcoder C); -dump_reg(AUD_CTS_ENABLE_A, Audio CTS Programming Enable  Transcoder A); -dump_reg(AUD_CTS_ENABLE_B, Audio CTS Programming Enable  Transcoder B); -dump_reg(AUD_CTS_ENABLE_C, Audio CTS Programming Enable  Transcoder C); +dump_reg(AUD_CONFIG_A, Audio Configuration - Transcoder A); +dump_reg(AUD_CONFIG_B, Audio Configuration - Transcoder B); +dump_reg(AUD_CONFIG_C, Audio Configuration - Transcoder C); +dump_reg(AUD_CTS_ENABLE_A, Audio CTS Programming Enable - Transcoder A); +dump_reg(AUD_CTS_ENABLE_B, Audio CTS Programming Enable - Transcoder B); +
[Intel-gfx] [PATCH 04/18] intel_audio_dump: report effective channel count
The raw channel count is not user friendly and may be misleading. Signed-off-by: Wu Fengguang fengguang...@intel.com --- tools/intel_audio_dump.c | 18 +- 1 file changed, 9 insertions(+), 9 deletions(-) --- intel-gpu-tools.orig/tools/intel_audio_dump.c 2011-11-09 16:21:43.0 +0800 +++ intel-gpu-tools/tools/intel_audio_dump.c2011-11-09 16:22:23.0 +0800 @@ -367,16 +367,16 @@ static void dump_eaglelake(void) dword = INREG(AUD_OUT_CH_STR); printf(AUD_OUT_CH_STR stream id\t\t0x%lx\n,BITS(dword, 7, 4)); -printf(AUD_OUT_CH_STR lowest channel\t\t0x%lx\n, BITS(dword, 3, 0)); +printf(AUD_OUT_CH_STR lowest channel\t\t%lu\n, BITS(dword, 3, 0)); dword = INREG(AUD_OUT_STR_DESC); -printf(AUD_OUT_STR_DESC stream channels\t0x%lx\n, BITS(dword, 3, 0)); +printf(AUD_OUT_STR_DESC stream channels\t%lu\n,BITS(dword, 3, 0) + 1); dword = INREG(AUD_PINW_CAP); printf(AUD_PINW_CAP widget type\t\t0x%lx\n,BITS(dword, 23, 20)); printf(AUD_PINW_CAP sample delay\t\t0x%lx\n, BITS(dword, 19, 16)); -printf(AUD_PINW_CAP channel count\t\t0x%lx\n, - BITS(dword, 15, 13) * 2 + BIT(dword, 0)); +printf(AUD_PINW_CAP channel count\t\t%lu\n, + BITS(dword, 15, 13) * 2 + BIT(dword, 0) + 1); printf(AUD_PINW_CAP HDCP\t\t\t%lu\n, BIT(dword, 12)); printf(AUD_PINW_CAP L-R swap\t\t\t%lu\n, BIT(dword, 11)); printf(AUD_PINW_CAP power control\t\t%lu\n,BIT(dword, 10)); @@ -647,13 +647,13 @@ static void dump_ironlake(void) dword = INREG(AUD_OUT_STR_DESC_A); printf(AUD_OUT_STR_DESC_A HBR_enable\t\t\t\t%lu\n, BITS(dword, 28, 27)); -printf(AUD_OUT_STR_DESC_A Convertor_Channel_Count\t\t%lu\n, BITS(dword, 20, 16)); +printf(AUD_OUT_STR_DESC_A Convertor_Channel_Count\t\t%lu\n, BITS(dword, 20, 16) + 1); printf(AUD_OUT_STR_DESC_A Bits_per_Sample\t\t\t%lu\n,BITS(dword, 6, 4)); printf(AUD_OUT_STR_DESC_A Number_of_Channels_in_a_Stream\t%lu\n, 1 + BITS(dword, 3, 0)); dword = INREG(AUD_OUT_STR_DESC_B); printf(AUD_OUT_STR_DESC_B HBR_enable\t\t\t\t%lu\n, BITS(dword, 28, 27)); -printf(AUD_OUT_STR_DESC_B Convertor_Channel_Count\t\t%lu\n, BITS(dword, 20, 16)); +printf(AUD_OUT_STR_DESC_B Convertor_Channel_Count\t\t%lu\n, BITS(dword, 20, 16) + 1); printf(AUD_OUT_STR_DESC_B Bits_per_Sample\t\t\t%lu\n,BITS(dword, 6, 4)); printf(AUD_OUT_STR_DESC_B Number_of_Channels_in_a_Stream\t%lu\n, 1 + BITS(dword, 3, 0)); @@ -1044,19 +1044,19 @@ static void dump_cpt(void) dword = INREG(AUD_OUT_STR_DESC_A); printf(AUD_OUT_STR_DESC_A HBR_enable\t\t\t\t%lu\n, BITS(dword, 28, 27)); -printf(AUD_OUT_STR_DESC_A Convertor_Channel_Count\t\t%lu\n, BITS(dword, 20, 16)); +printf(AUD_OUT_STR_DESC_A Convertor_Channel_Count\t\t%lu\n, BITS(dword, 20, 16) + 1); printf(AUD_OUT_STR_DESC_A Bits_per_Sample\t\t\t%lu\n,BITS(dword, 6, 4)); printf(AUD_OUT_STR_DESC_A Number_of_Channels_in_a_Stream\t%lu\n, 1 + BITS(dword, 3, 0)); dword = INREG(AUD_OUT_STR_DESC_B); printf(AUD_OUT_STR_DESC_B HBR_enable\t\t\t\t%lu\n, BITS(dword, 28, 27)); -printf(AUD_OUT_STR_DESC_B Convertor_Channel_Count\t\t%lu\n, BITS(dword, 20, 16)); +printf(AUD_OUT_STR_DESC_B Convertor_Channel_Count\t\t%lu\n, BITS(dword, 20, 16) + 1); printf(AUD_OUT_STR_DESC_B Bits_per_Sample\t\t\t%lu\n,BITS(dword, 6, 4)); printf(AUD_OUT_STR_DESC_B Number_of_Channels_in_a_Stream\t%lu\n, 1 + BITS(dword, 3, 0)); dword = INREG(AUD_OUT_STR_DESC_C); printf(AUD_OUT_STR_DESC_C HBR_enable\t\t\t\t%lu\n, BITS(dword, 28, 27)); -printf(AUD_OUT_STR_DESC_C Convertor_Channel_Count\t\t%lu\n, BITS(dword, 20, 16)); +printf(AUD_OUT_STR_DESC_C Convertor_Channel_Count\t\t%lu\n, BITS(dword, 20, 16) + 1); printf(AUD_OUT_STR_DESC_C Bits_per_Sample\t\t\t%lu\n,BITS(dword, 6, 4)); printf(AUD_OUT_STR_DESC_C Number_of_Channels_in_a_Stream\t%lu\n, 1 + BITS(dword, 3, 0)); ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 06/18] intel_audio_dump: fix Digital_Port_D_Detected copypaste error
Signed-off-by: Wu Fengguang fengguang...@intel.com --- tools/intel_audio_dump.c |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) --- intel-gpu-tools.orig/tools/intel_audio_dump.c 2011-11-09 10:35:34.0 +0800 +++ intel-gpu-tools/tools/intel_audio_dump.c2011-11-09 10:35:35.0 +0800 @@ -537,7 +537,7 @@ static void dump_ironlake(void) printf(HDMIB HDMIB_Enable\t\t\t\t\t%u\n, !!(dword SDVO_ENABLE)); printf(HDMIB Transcoder_Select\t\t\t\t\t%s\n, BIT(dword, 30) ? Transcoder B : Transcoder A); printf(HDMIB HDCP_Port_Select\t\t\t\t\t%lu\n, BIT(dword, 5)); -printf(HDMIB Digital_Port_D_Detected\t\t\t\t%lu\n, BIT(dword, 2)); +printf(HDMIB Digital_Port_B_Detected\t\t\t\t%lu\n, BIT(dword, 2)); printf(HDMIB Null_packets_enabled_during_Vsync\t\t\t%u\n, !!(dword SDVO_NULL_PACKETS_DURING_VSYNC)); printf(HDMIB Audio_Output_Enable\t\t\t\t%u\n, !!(dword SDVO_AUDIO_ENABLE)); @@ -545,7 +545,7 @@ static void dump_ironlake(void) printf(HDMIC HDMIC_Enable\t\t\t\t\t%u\n, !!(dword SDVO_ENABLE)); printf(HDMIC Transcoder_Select\t\t\t\t\t%s\n, BIT(dword, 30) ? Transcoder B : Transcoder A); printf(HDMIC HDCP_Port_Select\t\t\t\t\t%lu\n, BIT(dword, 5)); -printf(HDMIC Digital_Port_D_Detected\t\t\t\t%lu\n, BIT(dword, 2)); +printf(HDMIC Digital_Port_C_Detected\t\t\t\t%lu\n, BIT(dword, 2)); printf(HDMIC Null_packets_enabled_during_Vsync\t\t\t%u\n, !!(dword SDVO_NULL_PACKETS_DURING_VSYNC)); printf(HDMIC Audio_Output_Enable\t\t\t\t%u\n, !!(dword SDVO_AUDIO_ENABLE)); ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 03/18] intel_audio_dump: cleanup hex output
- no need to show the 1-bit AUD_OUT_DIG_CNVT_* as hex value - show the Connection_select_Control_* bits as hex values Signed-off-by: Wu Fengguang fengguang...@intel.com --- tools/intel_audio_dump.c | 16 1 file changed, 8 insertions(+), 8 deletions(-) --- intel-gpu-tools.orig/tools/intel_audio_dump.c 2011-11-12 11:11:32.0 +0800 +++ intel-gpu-tools/tools/intel_audio_dump.c2011-11-12 11:11:38.0 +0800 @@ -615,7 +615,7 @@ static void dump_ironlake(void) printf(AUD_OUT_DIG_CNVT_A VCFG\t\t\t\t%lu\n,BIT(dword, 2)); printf(AUD_OUT_DIG_CNVT_A PRE\t\t\t\t\t%lu\n, BIT(dword, 3)); printf(AUD_OUT_DIG_CNVT_A Copy\t\t\t\t%lu\n,BIT(dword, 4)); -printf(AUD_OUT_DIG_CNVT_A Non-Audio\t\t\t\t0x%lx\n, BIT(dword, 5)); +printf(AUD_OUT_DIG_CNVT_A NonAudio\t\t\t\t%lu\n, BIT(dword, 5)); printf(AUD_OUT_DIG_CNVT_A PRO\t\t\t\t\t%lu\n, BIT(dword, 6)); printf(AUD_OUT_DIG_CNVT_A Level\t\t\t\t%lu\n, BIT(dword, 7)); printf(AUD_OUT_DIG_CNVT_A Category_Code\t\t\t%lu\n, BITS(dword, 14, 8)); @@ -627,7 +627,7 @@ static void dump_ironlake(void) printf(AUD_OUT_DIG_CNVT_B VCFG\t\t\t\t%lu\n,BIT(dword, 2)); printf(AUD_OUT_DIG_CNVT_B PRE\t\t\t\t\t%lu\n, BIT(dword, 3)); printf(AUD_OUT_DIG_CNVT_B Copy\t\t\t\t%lu\n,BIT(dword, 4)); -printf(AUD_OUT_DIG_CNVT_B Non-Audio\t\t\t\t0x%lx\n, BIT(dword, 5)); +printf(AUD_OUT_DIG_CNVT_B NonAudio\t\t\t\t%lu\n, BIT(dword, 5)); printf(AUD_OUT_DIG_CNVT_B PRO\t\t\t\t\t%lu\n, BIT(dword, 6)); printf(AUD_OUT_DIG_CNVT_B Level\t\t\t\t%lu\n, BIT(dword, 7)); printf(AUD_OUT_DIG_CNVT_B Category_Code\t\t\t%lu\n, BITS(dword, 14, 8)); @@ -1000,7 +1000,7 @@ static void dump_cpt(void) printf(AUD_OUT_DIG_CNVT_A VCFG\t\t\t\t%lu\n,BIT(dword, 2)); printf(AUD_OUT_DIG_CNVT_A PRE\t\t\t\t\t%lu\n, BIT(dword, 3)); printf(AUD_OUT_DIG_CNVT_A Copy\t\t\t\t%lu\n,BIT(dword, 4)); -printf(AUD_OUT_DIG_CNVT_A NonAudio\t\t\t\t0x%lx\n, BIT(dword, 5)); +printf(AUD_OUT_DIG_CNVT_A NonAudio\t\t\t\t%lu\n, BIT(dword, 5)); printf(AUD_OUT_DIG_CNVT_A PRO\t\t\t\t\t%lu\n, BIT(dword, 6)); printf(AUD_OUT_DIG_CNVT_A Level\t\t\t\t%lu\n, BIT(dword, 7)); printf(AUD_OUT_DIG_CNVT_A Category_Code\t\t\t%lu\n, BITS(dword, 14, 8)); @@ -1012,7 +1012,7 @@ static void dump_cpt(void) printf(AUD_OUT_DIG_CNVT_B VCFG\t\t\t\t%lu\n,BIT(dword, 2)); printf(AUD_OUT_DIG_CNVT_B PRE\t\t\t\t\t%lu\n, BIT(dword, 3)); printf(AUD_OUT_DIG_CNVT_B Copy\t\t\t\t%lu\n,BIT(dword, 4)); -printf(AUD_OUT_DIG_CNVT_B NonAudio\t\t\t\t0x%lx\n, BIT(dword, 5)); +printf(AUD_OUT_DIG_CNVT_B NonAudio\t\t\t\t%lu\n, BIT(dword, 5)); printf(AUD_OUT_DIG_CNVT_B PRO\t\t\t\t\t%lu\n, BIT(dword, 6)); printf(AUD_OUT_DIG_CNVT_B Level\t\t\t\t%lu\n, BIT(dword, 7)); printf(AUD_OUT_DIG_CNVT_B Category_Code\t\t\t%lu\n, BITS(dword, 14, 8)); @@ -1024,7 +1024,7 @@ static void dump_cpt(void) printf(AUD_OUT_DIG_CNVT_C VCFG\t\t\t\t%lu\n,BIT(dword, 2)); printf(AUD_OUT_DIG_CNVT_C PRE\t\t\t\t\t%lu\n, BIT(dword, 3)); printf(AUD_OUT_DIG_CNVT_C Copy\t\t\t\t%lu\n,BIT(dword, 4)); -printf(AUD_OUT_DIG_CNVT_C NonAudio\t\t\t\t0x%lx\n, BIT(dword, 5)); +printf(AUD_OUT_DIG_CNVT_C NonAudio\t\t\t\t%lu\n, BIT(dword, 5)); printf(AUD_OUT_DIG_CNVT_C PRO\t\t\t\t\t%lu\n, BIT(dword, 6)); printf(AUD_OUT_DIG_CNVT_C Level\t\t\t\t%lu\n, BIT(dword, 7)); printf(AUD_OUT_DIG_CNVT_C Category_Code\t\t\t%lu\n, BITS(dword, 14, 8)); @@ -1061,9 +1061,9 @@ static void dump_cpt(void) printf(AUD_OUT_STR_DESC_C Number_of_Channels_in_a_Stream\t%lu\n, 1 + BITS(dword, 3, 0)); dword = INREG(AUD_PINW_CONNLNG_SEL); -printf(AUD_PINW_CONNLNG_SEL Connection_select_Control_B\t%lu\n, BITS(dword, 7, 0)); -printf(AUD_PINW_CONNLNG_SEL Connection_select_Control_C\t%lu\n, BITS(dword, 15, 8)); -printf(AUD_PINW_CONNLNG_SEL Connection_select_Control_D\t%lu\n, BITS(dword, 23, 16)); +printf(AUD_PINW_CONNLNG_SEL Connection_select_Control_B\t%#lx\n, BITS(dword, 7, 0)); +printf(AUD_PINW_CONNLNG_SEL Connection_select_Control_C\t%#lx\n, BITS(dword, 15, 8)); +printf(AUD_PINW_CONNLNG_SEL Connection_select_Control_D\t%#lx\n, BITS(dword, 23, 16)); dword = INREG(AUD_CNTL_ST_A); printf(AUD_CNTL_ST_A DIP_Port_Select\t\t\t\t[%#lx] %s\n, ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 09/18] intel_audio_dump: fix DP port width for CPT
Signed-off-by: Wu Fengguang fengguang...@intel.com
---
tools/intel_audio_dump.c |5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
--- intel-gpu-tools.orig/tools/intel_audio_dump.c 2011-11-09
10:35:35.0 +0800
+++ intel-gpu-tools/tools/intel_audio_dump.c2011-11-09 10:35:35.0
+0800
@@ -142,8 +142,9 @@ static char *transcoder_select[] = {
static char *dp_port_width[] = {
[0] = x1 mode,
[1] = x2 mode,
- [2] = x4 mode,
- [3] = reserved,
+ [2] = reserved,
+ [3] = x4 mode,
+ [4 ... 7] = reserved,
};
static void do_self_tests(void)
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 05/18] intel_audio_dump: fix ironlake Stream_ID indents
Signed-off-by: Wu Fengguang fengguang...@intel.com
---
tools/intel_audio_dump.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
--- intel-gpu-tools.orig/tools/intel_audio_dump.c 2011-11-09
10:35:34.0 +0800
+++ intel-gpu-tools/tools/intel_audio_dump.c2011-11-09 10:35:34.0
+0800
@@ -620,7 +620,7 @@ static void dump_ironlake(void)
printf(AUD_OUT_DIG_CNVT_A Level\t\t\t\t%lu\n, BIT(dword, 7));
printf(AUD_OUT_DIG_CNVT_A Category_Code\t\t\t%lu\n, BITS(dword, 14,
8));
printf(AUD_OUT_DIG_CNVT_A Lowest_Channel_Number\t\t%lu\n,BITS(dword,
19, 16));
-printf(AUD_OUT_DIG_CNVT_A Stream_ID\t\t\t\t\t\t%lu\n, BITS(dword, 23,
20));
+printf(AUD_OUT_DIG_CNVT_A Stream_ID\t\t\t\t%lu\n, BITS(dword, 23,
20));
dword = INREG(AUD_OUT_DIG_CNVT_B);
printf(AUD_OUT_DIG_CNVT_B V\t\t\t\t\t%lu\n, BIT(dword, 1));
@@ -632,7 +632,7 @@ static void dump_ironlake(void)
printf(AUD_OUT_DIG_CNVT_B Level\t\t\t\t%lu\n, BIT(dword, 7));
printf(AUD_OUT_DIG_CNVT_B Category_Code\t\t\t%lu\n, BITS(dword, 14,
8));
printf(AUD_OUT_DIG_CNVT_B Lowest_Channel_Number\t\t%lu\n,BITS(dword,
19, 16));
-printf(AUD_OUT_DIG_CNVT_B Stream_ID\t\t\t%lu\n, BITS(dword, 23,
20));
+printf(AUD_OUT_DIG_CNVT_B Stream_ID\t\t\t\t%lu\n, BITS(dword, 23,
20));
printf(AUD_OUT_CH_STR Converter_Channel_MAP PORTB PORTC
PORTD\n);
for (i = 0; i 8; i++) {
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 08/18] intel_audio_dump: fix DP control registers for CPT
Signed-off-by: Wu Fengguang fengguang...@intel.com --- tools/intel_audio_dump.c | 47 + 1 file changed, 27 insertions(+), 20 deletions(-) --- intel-gpu-tools.orig/tools/intel_audio_dump.c 2011-11-12 10:19:06.0 +0800 +++ intel-gpu-tools/tools/intel_audio_dump.c2011-11-12 10:28:14.0 +0800 @@ -764,6 +764,7 @@ static void dump_ironlake(void) /* * CougarPoint registers */ +#define DP_CTL_B 0xE4100 #define DP_CTL_C 0xE4200 #define DP_AUX_CTL_C 0xE4210 #define DP_AUX_TST_C 0xE4228 @@ -825,6 +826,12 @@ static void dump_cpt(void) dump_reg(HDMIB,sDVO/HDMI Port B Control); dump_reg(HDMIC,HDMI Port C Control); dump_reg(HDMID,HDMI Port D Control); +dump_reg(DP_CTL_B, DisplayPort B Control); +dump_reg(DP_CTL_C, DisplayPort C Control); +dump_reg(DP_CTL_D, DisplayPort D Control); +dump_reg(TRANS_DP_CTL_A, Transcoder A DisplayPort Control); +dump_reg(TRANS_DP_CTL_B, Transcoder B DisplayPort Control); +dump_reg(TRANS_DP_CTL_C, Transcoder C DisplayPort Control); dump_reg(AUD_CONFIG_A, Audio Configuration - Transcoder A); dump_reg(AUD_CONFIG_B, Audio Configuration - Transcoder B); dump_reg(AUD_CONFIG_C, Audio Configuration - Transcoder C); @@ -902,29 +909,29 @@ static void dump_cpt(void) printf(HDMID HDMI_or_DVI_Select\t\t\t\t%s\n, BIT(dword, 9) ? HDMI : DVI); printf(HDMID Audio_Output_Enable\t\t\t\t%u\n, !!(dword SDVO_AUDIO_ENABLE)); -dword = INREG(TRANS_DP_CTL_A); -printf(TRANS_DP_CTL_A DisplayPort_Enable\t\t\t%lu\n, BIT(dword, 31)); -printf(TRANS_DP_CTL_A Port_Width_Selection\t\t\t[0x%lx] %s\n, +dword = INREG(DP_CTL_B); +printf(DP_CTL_B DisplayPort_Enable\t\t\t\t%lu\n, BIT(dword, 31)); +printf(DP_CTL_B Port_Width_Selection\t\t\t\t[0x%lx] %s\n, BITS(dword, 21, 19), dp_port_width[BITS(dword, 21, 19)]); -printf(TRANS_DP_CTL_A Port_Detected\t\t\t\t%lu\n, BIT(dword, 2)); -printf(TRANS_DP_CTL_A HDCP_Port_Select\t\t\t\t%lu\n, BIT(dword, 5)); -printf(TRANS_DP_CTL_A Audio_Output_Enable\t\t\t%lu\n, BIT(dword, 6)); - -dword = INREG(TRANS_DP_CTL_B); -printf(TRANS_DP_CTL_B DisplayPort_Enable\t\t\t%lu\n, BIT(dword, 31)); -printf(TRANS_DP_CTL_B Port_Width_Selection\t\t\t[0x%lx] %s\n, +printf(DP_CTL_B Port_Detected\t\t\t\t\t%lu\n, BIT(dword, 2)); +printf(DP_CTL_B HDCP_Port_Select\t\t\t\t%lu\n, BIT(dword, 5)); +printf(DP_CTL_B Audio_Output_Enable\t\t\t\t%lu\n, BIT(dword, 6)); + +dword = INREG(DP_CTL_C); +printf(DP_CTL_C DisplayPort_Enable\t\t\t\t%lu\n, BIT(dword, 31)); +printf(DP_CTL_C Port_Width_Selection\t\t\t\t[0x%lx] %s\n, BITS(dword, 21, 19), dp_port_width[BITS(dword, 21, 19)]); -printf(TRANS_DP_CTL_B Port_Detected\t\t\t\t%lu\n, BIT(dword, 2)); -printf(TRANS_DP_CTL_B HDCP_Port_Select\t\t\t\t%lu\n, BIT(dword, 5)); -printf(TRANS_DP_CTL_B Audio_Output_Enable\t\t\t%lu\n, BIT(dword, 6)); - -dword = INREG(TRANS_DP_CTL_C); -printf(TRANS_DP_CTL_C DisplayPort_Enable\t\t\t%lu\n, BIT(dword, 31)); -printf(TRANS_DP_CTL_C Port_Width_Selection\t\t\t[0x%lx] %s\n, +printf(DP_CTL_C Port_Detected\t\t\t\t\t%lu\n, BIT(dword, 2)); +printf(DP_CTL_C HDCP_Port_Select\t\t\t\t%lu\n, BIT(dword, 5)); +printf(DP_CTL_C Audio_Output_Enable\t\t\t\t%lu\n, BIT(dword, 6)); + +dword = INREG(DP_CTL_D); +printf(DP_CTL_D DisplayPort_Enable\t\t\t\t%lu\n, BIT(dword, 31)); +printf(DP_CTL_D Port_Width_Selection\t\t\t\t[0x%lx] %s\n, BITS(dword, 21, 19), dp_port_width[BITS(dword, 21, 19)]); -printf(TRANS_DP_CTL_C Port_Detected\t\t\t\t%lu\n, BIT(dword, 2)); -printf(TRANS_DP_CTL_C HDCP_Port_Select\t\t\t\t%lu\n, BIT(dword, 5)); -printf(TRANS_DP_CTL_C Audio_Output_Enable\t\t\t%lu\n, BIT(dword, 6)); +printf(DP_CTL_D Port_Detected\t\t\t\t\t%lu\n, BIT(dword, 2)); +printf(DP_CTL_D HDCP_Port_Select\t\t\t\t%lu\n, BIT(dword, 5)); +printf(DP_CTL_D Audio_Output_Enable\t\t\t\t%lu\n, BIT(dword, 6)); dword = INREG(AUD_CONFIG_A); printf(AUD_CONFIG_A Pixel_Clock_HDMI\t\t\t\t[0x%lx] %s\n, BITS(dword, 19, 16), ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 07/18] intel_audio_dump: fix Ironlake detection
The original test mistakenly calls dump_cpt() for Ironlake,
due to HAS_PCH_SPLIT := IS_GEN5 || IS_GEN6 || IS_GEN7.
Signed-off-by: Wu Fengguang fengguang...@intel.com
---
tools/intel_audio_dump.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- intel-gpu-tools.orig/tools/intel_audio_dump.c 2011-11-09
10:35:35.0 +0800
+++ intel-gpu-tools/tools/intel_audio_dump.c2011-11-09 10:35:35.0
+0800
@@ -1194,7 +1194,7 @@ int main(int argc, char **argv)
else
intel_get_mmio(pci_dev);
- if (HAS_PCH_SPLIT(devid) || getenv(HAS_PCH_SPLIT)) {
+ if (IS_GEN6(devid) || IS_GEN7(devid) || getenv(HAS_PCH_SPLIT)) {
intel_check_pch();
dump_cpt();
} else if (IS_GEN5(devid))
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 13/18] intel_audio_dump: show ELD contents for G45
Signed-off-by: Wu Fengguang fengguang...@intel.com --- tools/intel_audio_dump.c |8 1 file changed, 8 insertions(+) --- intel-gpu-tools.orig/tools/intel_audio_dump.c 2011-11-12 10:52:47.0 +0800 +++ intel-gpu-tools/tools/intel_audio_dump.c2011-11-12 10:52:48.0 +0800 @@ -455,6 +455,14 @@ static void dump_eaglelake(void) printf(\t\t\t\t\t[0x%x] %u = %lu \n, dword, i, BITS(dword, 7, 4)); } +printf(AUD_HDMIW_HDMIEDID HDMI ELD:\n\t); +dword = INREG(AUD_CNTL_ST); +dword = ~BITMASK(8, 5); +OUTREG(AUD_CNTL_ST, dword); +for (i = 0; i BITS(dword, 14, 10) / 4; i++) + printf(%08x , htonl(INREG(AUD_HDMIW_HDMIEDID))); +printf(\n); + printf(AUD_HDMIW_INFOFR HDMI audio Infoframe:\n\t); dword = INREG(AUD_CNTL_ST); dword = ~BITMASK(20, 18); ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 14/18] intel_audio_dump: show ironlake ELD_access_address
Signed-off-by: Wu Fengguang fengguang...@intel.com --- tools/intel_audio_dump.c |2 ++ 1 file changed, 2 insertions(+) --- intel-gpu-tools.orig/tools/intel_audio_dump.c 2011-11-12 10:52:48.0 +0800 +++ intel-gpu-tools/tools/intel_audio_dump.c2011-11-12 10:52:48.0 +0800 @@ -725,6 +725,7 @@ static void dump_ironlake(void) BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]); printf(AUD_CNTL_ST_A ELD_ACK\t\t\t\t\t%lu\n, BIT(dword, 4)); printf(AUD_CNTL_ST_A ELD_buffer_size\t\t\t\t%lu\n, BITS(dword, 14, 10)); +printf(AUD_CNTL_ST_A ELD_access_address\t\t\t%lu\n, BITS(dword, 9, 5)); dword = INREG(AUD_CNTL_ST_B); printf(AUD_CNTL_ST_B DIP_Port_Select\t\t\t\t[%#lx] %s\n, @@ -736,6 +737,7 @@ static void dump_ironlake(void) BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]); printf(AUD_CNTL_ST_B ELD_ACK\t\t\t\t\t%lu\n, BIT(dword, 4)); printf(AUD_CNTL_ST_B ELD_buffer_size\t\t\t\t%lu\n, BITS(dword, 14, 10)); +printf(AUD_CNTL_ST_B ELD_access_address\t\t\t%lu\n, BITS(dword, 9, 5)); dword = INREG(AUD_CNTL_ST2); printf(AUD_CNTL_ST2 CP_ReadyB\t\t\t\t\t%lu\n, BIT(dword, 1)); ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 18/18] intel_audio_dump: show Gamut Metadata DIP
Signed-off-by: Wu Fengguang fengguang...@intel.com
---
tools/intel_audio_dump.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- intel-gpu-tools.orig/tools/intel_audio_dump.c 2011-11-12
10:52:50.0 +0800
+++ intel-gpu-tools/tools/intel_audio_dump.c2011-11-12 10:52:51.0
+0800
@@ -112,7 +112,7 @@ static char *dip_trans[] = {
static char *video_dip_index[] = {
[0] = AVI DIP,
[1] = Vendor-specific DIP,
- [2] = Reserved,
+ [2] = Gamut Metadata DIP,
[3] = Source Product Description DIP,
};
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 17/18] intel_audio_dump: show interrupt enable bit
Signed-off-by: Wu Fengguang fengguang...@intel.com --- tools/intel_audio_dump.c |4 1 file changed, 4 insertions(+) --- intel-gpu-tools.orig/tools/intel_audio_dump.c 2011-11-12 10:52:50.0 +0800 +++ intel-gpu-tools/tools/intel_audio_dump.c2011-11-12 10:52:50.0 +0800 @@ -567,6 +567,7 @@ static void dump_ironlake(void) printf(HDMIB HDMIB_Enable\t\t\t\t\t%u\n, !!(dword SDVO_ENABLE)); printf(HDMIB Transcoder_Select\t\t\t\t\t%s\n, BIT(dword, 30) ? Transcoder B : Transcoder A); printf(HDMIB HDCP_Port_Select\t\t\t\t\t%lu\n, BIT(dword, 5)); +printf(HDMIB SDVOB Hot Plug Interrupt Detect Enable\t\t%lu\n, BIT(dword, 23)); printf(HDMIB Digital_Port_B_Detected\t\t\t\t%lu\n, BIT(dword, 2)); printf(HDMIB Encoding\t\t\t\t\t\t[0x%lx] %s\n, BITS(dword, 11, 10), sdvo_hdmi_encoding[BITS(dword, 11, 10)]); @@ -999,6 +1000,7 @@ static void dump_cpt(void) BITS(dword, 30, 29), transcoder_select[BITS(dword, 30, 29)]); printf(HDMIB sDVO_Border_Enable\t\t\t\t%lu\n, BIT(dword, 7)); printf(HDMIB HDCP_Port_Select\t\t\t\t\t%lu\n, BIT(dword, 5)); +printf(HDMIB SDVO_HPD_Interrupt_Enable\t\t\t\t%lu\n, BIT(dword, 23)); printf(HDMIB Port_Detected\t\t\t\t\t%lu\n, BIT(dword, 2)); printf(HDMIB Encoding\t\t\t\t\t\t[0x%lx] %s\n, BITS(dword, 11, 10), sdvo_hdmi_encoding[BITS(dword, 11, 10)]); @@ -1011,6 +1013,7 @@ static void dump_cpt(void) BITS(dword, 30, 29), transcoder_select[BITS(dword, 30, 29)]); printf(HDMIC sDVO_Border_Enable\t\t\t\t%lu\n, BIT(dword, 7)); printf(HDMIC HDCP_Port_Select\t\t\t\t\t%lu\n, BIT(dword, 5)); +printf(HDMIC SDVO_HPD_Interrupt_Enable\t\t\t\t%lu\n, BIT(dword, 23)); printf(HDMIC Port_Detected\t\t\t\t\t%lu\n, BIT(dword, 2)); printf(HDMIC Encoding\t\t\t\t\t\t[0x%lx] %s\n, BITS(dword, 11, 10), sdvo_hdmi_encoding[BITS(dword, 11, 10)]); @@ -1023,6 +1026,7 @@ static void dump_cpt(void) BITS(dword, 30, 29), transcoder_select[BITS(dword, 30, 29)]); printf(HDMID sDVO_Border_Enable\t\t\t\t%lu\n, BIT(dword, 7)); printf(HDMID HDCP_Port_Select\t\t\t\t\t%lu\n, BIT(dword, 5)); +printf(HDMID SDVO_HPD_Interrupt_Enable\t\t\t\t%lu\n, BIT(dword, 23)); printf(HDMID Port_Detected\t\t\t\t\t%lu\n, BIT(dword, 2)); printf(HDMID Encoding\t\t\t\t\t\t[0x%lx] %s\n, BITS(dword, 11, 10), sdvo_hdmi_encoding[BITS(dword, 11, 10)]); ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 12/18] intel_audio_dump: show detected chipset name
Signed-off-by: Wu Fengguang fengguang...@intel.com
---
tools/intel_audio_dump.c |9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
--- intel-gpu-tools.orig/tools/intel_audio_dump.c 2011-11-12
10:52:46.0 +0800
+++ intel-gpu-tools/tools/intel_audio_dump.c2011-11-12 10:52:47.0
+0800
@@ -1250,12 +1250,17 @@ int main(int argc, char **argv)
intel_get_mmio(pci_dev);
if (IS_GEN6(devid) || IS_GEN7(devid) || getenv(HAS_PCH_SPLIT)) {
+ printf(%s audio registers:\n\n,
+ IS_GEN6(devid) ? SandyBridge : IvyBridge);
intel_check_pch();
dump_cpt();
- } else if (IS_GEN5(devid))
+ } else if (IS_GEN5(devid)) {
+ printf(Ironlake audio registers:\n\n);
dump_ironlake();
- else
+ } else if (IS_G4X(devid)) {
+ printf(G45 audio registers:\n\n);
dump_eaglelake();
+ }
return 0;
}
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 10/18] intel_audio_dump: explain Bits_per_Sample
Signed-off-by: Wu Fengguang fengguang...@intel.com
---
tools/intel_audio_dump.c | 27 ++-
1 file changed, 22 insertions(+), 5 deletions(-)
--- intel-gpu-tools.orig/tools/intel_audio_dump.c 2011-11-12
10:52:39.0 +0800
+++ intel-gpu-tools/tools/intel_audio_dump.c2011-11-12 10:52:40.0
+0800
@@ -147,6 +147,16 @@ static char *dp_port_width[] = {
[4 ... 7] = reserved,
};
+static char *bits_per_sample[] = {
+ [0] = reserved,
+ [1] = 16 bits,
+ [2] = 24 bits,
+ [3] = 32 bits,
+ [4] = 20 bits,
+ [5] = reserved,
+};
+
+
static void do_self_tests(void)
{
if (BIT(1, 0) != 1)
@@ -372,6 +382,8 @@ static void dump_eaglelake(void)
dword = INREG(AUD_OUT_STR_DESC);
printf(AUD_OUT_STR_DESC stream channels\t%lu\n,BITS(dword, 3, 0) +
1);
+printf(AUD_OUT_STR_DESC Bits per Sample\t[%#lx] %s\n,
+ BITS(dword, 6, 4), OPNAME(bits_per_sample, BITS(dword, 6,
4)));
dword = INREG(AUD_PINW_CAP);
printf(AUD_PINW_CAP widget type\t\t0x%lx\n,BITS(dword, 23, 20));
@@ -649,13 +661,15 @@ static void dump_ironlake(void)
dword = INREG(AUD_OUT_STR_DESC_A);
printf(AUD_OUT_STR_DESC_A HBR_enable\t\t\t\t%lu\n, BITS(dword,
28, 27));
printf(AUD_OUT_STR_DESC_A Convertor_Channel_Count\t\t%lu\n, BITS(dword,
20, 16) + 1);
-printf(AUD_OUT_STR_DESC_A Bits_per_Sample\t\t\t%lu\n,BITS(dword, 6,
4));
+printf(AUD_OUT_STR_DESC_A Bits_per_Sample\t\t\t[%#lx] %s\n,
+ BITS(dword, 6, 4), OPNAME(bits_per_sample,
BITS(dword, 6, 4)));
printf(AUD_OUT_STR_DESC_A Number_of_Channels_in_a_Stream\t%lu\n, 1 +
BITS(dword, 3, 0));
dword = INREG(AUD_OUT_STR_DESC_B);
printf(AUD_OUT_STR_DESC_B HBR_enable\t\t\t\t%lu\n, BITS(dword,
28, 27));
printf(AUD_OUT_STR_DESC_B Convertor_Channel_Count\t\t%lu\n, BITS(dword,
20, 16) + 1);
-printf(AUD_OUT_STR_DESC_B Bits_per_Sample\t\t\t%lu\n,BITS(dword, 6,
4));
+printf(AUD_OUT_STR_DESC_B Bits_per_Sample\t\t\t[%#lx] %s\n,
+ BITS(dword, 6, 4), OPNAME(bits_per_sample,
BITS(dword, 6, 4)));
printf(AUD_OUT_STR_DESC_B Number_of_Channels_in_a_Stream\t%lu\n, 1 +
BITS(dword, 3, 0));
dword = INREG(AUD_PINW_CONNLNG_SEL);
@@ -1053,19 +1067,22 @@ static void dump_cpt(void)
dword = INREG(AUD_OUT_STR_DESC_A);
printf(AUD_OUT_STR_DESC_A HBR_enable\t\t\t\t%lu\n, BITS(dword,
28, 27));
printf(AUD_OUT_STR_DESC_A Convertor_Channel_Count\t\t%lu\n, BITS(dword,
20, 16) + 1);
-printf(AUD_OUT_STR_DESC_A Bits_per_Sample\t\t\t%lu\n,BITS(dword, 6,
4));
+printf(AUD_OUT_STR_DESC_A Bits_per_Sample\t\t\t[%#lx] %s\n,
+ BITS(dword, 6, 4), OPNAME(bits_per_sample,
BITS(dword, 6, 4)));
printf(AUD_OUT_STR_DESC_A Number_of_Channels_in_a_Stream\t%lu\n, 1 +
BITS(dword, 3, 0));
dword = INREG(AUD_OUT_STR_DESC_B);
printf(AUD_OUT_STR_DESC_B HBR_enable\t\t\t\t%lu\n, BITS(dword,
28, 27));
printf(AUD_OUT_STR_DESC_B Convertor_Channel_Count\t\t%lu\n, BITS(dword,
20, 16) + 1);
-printf(AUD_OUT_STR_DESC_B Bits_per_Sample\t\t\t%lu\n,BITS(dword, 6,
4));
+printf(AUD_OUT_STR_DESC_B Bits_per_Sample\t\t\t[%#lx] %s\n,
+ BITS(dword, 6, 4), OPNAME(bits_per_sample,
BITS(dword, 6, 4)));
printf(AUD_OUT_STR_DESC_B Number_of_Channels_in_a_Stream\t%lu\n, 1 +
BITS(dword, 3, 0));
dword = INREG(AUD_OUT_STR_DESC_C);
printf(AUD_OUT_STR_DESC_C HBR_enable\t\t\t\t%lu\n, BITS(dword,
28, 27));
printf(AUD_OUT_STR_DESC_C Convertor_Channel_Count\t\t%lu\n, BITS(dword,
20, 16) + 1);
-printf(AUD_OUT_STR_DESC_C Bits_per_Sample\t\t\t%lu\n,BITS(dword, 6,
4));
+printf(AUD_OUT_STR_DESC_C Bits_per_Sample\t\t\t[%#lx] %s\n,
+ BITS(dword, 6, 4), OPNAME(bits_per_sample,
BITS(dword, 6, 4)));
printf(AUD_OUT_STR_DESC_C Number_of_Channels_in_a_Stream\t%lu\n, 1 +
BITS(dword, 3, 0));
dword = INREG(AUD_PINW_CONNLNG_SEL);
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 15/18] intel_audio_dump: show VIDEO_DIP_CTL_* for CPT
Signed-off-by: Wu Fengguang fengguang...@intel.com
---
tools/intel_audio_dump.c | 47 +
1 file changed, 47 insertions(+)
--- intel-gpu-tools.orig/tools/intel_audio_dump.c 2011-11-12
11:11:41.0 +0800
+++ intel-gpu-tools/tools/intel_audio_dump.c2011-11-12 11:11:45.0
+0800
@@ -872,6 +872,11 @@ static void dump_ironlake(void)
#define AUD_OUT_STR_DESC_D0xE5384
#define AUD_CNTL_ST_D 0xE53B4
+#define VIDEO_DIP_CTL_A0xE0200
+#define VIDEO_DIP_CTL_B0xE1200
+#define VIDEO_DIP_CTL_C0xE2200
+#define VIDEO_DIP_CTL_D0xE3200
+
static void dump_cpt(void)
{
@@ -924,6 +929,48 @@ static void dump_cpt(void)
printf(\nDetails:\n\n);
+dword = INREG(VIDEO_DIP_CTL_A);
+printf(VIDEO_DIP_CTL_A Enable_Graphics_DIP\t\t\t%ld\n, BIT(dword,
31)),
+printf(VIDEO_DIP_CTL_A GCP_DIP_enable\t\t\t\t%ld\n, BIT(dword, 25)),
+printf(VIDEO_DIP_CTL_A Video_DIP_type_enable AVI\t\t%lu\n,
BIT(dword, 21));
+printf(VIDEO_DIP_CTL_A Video_DIP_type_enable Vendor\t\t%lu\n,
BIT(dword, 22));
+printf(VIDEO_DIP_CTL_A Video_DIP_type_enable Gamut\t\t%lu\n,
BIT(dword, 23));
+printf(VIDEO_DIP_CTL_A Video_DIP_type_enable Source \t\t%lu\n,
BIT(dword, 24));
+printf(VIDEO_DIP_CTL_A Video_DIP_buffer_index\t\t\t[0x%lx] %s\n,
+ BITS(dword, 20, 19), video_dip_index[BITS(dword, 20, 19)]);
+printf(VIDEO_DIP_CTL_A Video_DIP_frequency\t\t\t[0x%lx] %s\n,
+ BITS(dword, 17, 16), video_dip_trans[BITS(dword, 17, 16)]);
+printf(VIDEO_DIP_CTL_A Video_DIP_buffer_size\t\t\t%lu\n, BITS(dword, 11,
8));
+printf(VIDEO_DIP_CTL_A Video_DIP_access_address\t\t%lu\n, BITS(dword, 3,
0));
+
+dword = INREG(VIDEO_DIP_CTL_B);
+printf(VIDEO_DIP_CTL_B Enable_Graphics_DIP\t\t\t%ld\n, BIT(dword,
31)),
+printf(VIDEO_DIP_CTL_B GCP_DIP_enable\t\t\t\t%ld\n, BIT(dword, 25)),
+printf(VIDEO_DIP_CTL_B Video_DIP_type_enable AVI\t\t%lu\n,
BIT(dword, 21));
+printf(VIDEO_DIP_CTL_B Video_DIP_type_enable Vendor\t\t%lu\n,
BIT(dword, 22));
+printf(VIDEO_DIP_CTL_B Video_DIP_type_enable Gamut\t\t%lu\n,
BIT(dword, 23));
+printf(VIDEO_DIP_CTL_B Video_DIP_type_enable Source \t\t%lu\n,
BIT(dword, 24));
+printf(VIDEO_DIP_CTL_B Video_DIP_buffer_index\t\t\t[0x%lx] %s\n,
+ BITS(dword, 20, 19), video_dip_index[BITS(dword, 20, 19)]);
+printf(VIDEO_DIP_CTL_B Video_DIP_frequency\t\t\t[0x%lx] %s\n,
+ BITS(dword, 17, 16), video_dip_trans[BITS(dword, 17, 16)]);
+printf(VIDEO_DIP_CTL_B Video_DIP_buffer_size\t\t\t%lu\n, BITS(dword, 11,
8));
+printf(VIDEO_DIP_CTL_B Video_DIP_access_address\t\t%lu\n, BITS(dword, 3,
0));
+
+dword = INREG(VIDEO_DIP_CTL_C);
+printf(VIDEO_DIP_CTL_C Enable_Graphics_DIP\t\t\t%ld\n, BIT(dword,
31)),
+printf(VIDEO_DIP_CTL_C GCP_DIP_enable\t\t\t\t%ld\n, BIT(dword, 25)),
+printf(VIDEO_DIP_CTL_C Video_DIP_type_enable AVI\t\t%lu\n,
BIT(dword, 21));
+printf(VIDEO_DIP_CTL_C Video_DIP_type_enable Vendor\t\t%lu\n,
BIT(dword, 22));
+printf(VIDEO_DIP_CTL_C Video_DIP_type_enable Gamut\t\t%lu\n,
BIT(dword, 23));
+printf(VIDEO_DIP_CTL_C Video_DIP_type_enable Source \t\t%lu\n,
BIT(dword, 24));
+printf(VIDEO_DIP_CTL_C Video_DIP_buffer_index\t\t\t[0x%lx] %s\n,
+ BITS(dword, 20, 19), video_dip_index[BITS(dword, 20, 19)]);
+printf(VIDEO_DIP_CTL_C Video_DIP_frequency\t\t\t[0x%lx] %s\n,
+ BITS(dword, 17, 16), video_dip_trans[BITS(dword, 17, 16)]);
+printf(VIDEO_DIP_CTL_C Video_DIP_buffer_size\t\t\t%lu\n, BITS(dword, 11,
8));
+printf(VIDEO_DIP_CTL_C Video_DIP_access_address\t\t%lu\n, BITS(dword, 3,
0));
+
dword = INREG(AUD_VID_DID);
printf(AUD_VID_DID vendor id\t\t\t\t\t0x%x\n, dword 16);
printf(AUD_VID_DID device id\t\t\t\t\t0x%x\n, dword 0x);
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 16/18] intel_audio_dump: show HDMI encoding
Signed-off-by: Wu Fengguang fengguang...@intel.com
---
tools/intel_audio_dump.c | 18 ++
1 file changed, 18 insertions(+)
--- intel-gpu-tools.orig/tools/intel_audio_dump.c 2011-11-12
10:52:49.0 +0800
+++ intel-gpu-tools/tools/intel_audio_dump.c2011-11-12 10:52:50.0
+0800
@@ -156,6 +156,12 @@ static char *bits_per_sample[] = {
[5] = reserved,
};
+static char *sdvo_hdmi_encoding[] = {
+ [0] = SDVO,
+ [1] = reserved,
+ [2] = TMDS,
+ [3] = reserved,
+};
static void do_self_tests(void)
{
@@ -562,6 +568,8 @@ static void dump_ironlake(void)
printf(HDMIB Transcoder_Select\t\t\t\t\t%s\n, BIT(dword, 30) ?
Transcoder B : Transcoder A);
printf(HDMIB HDCP_Port_Select\t\t\t\t\t%lu\n, BIT(dword, 5));
printf(HDMIB Digital_Port_B_Detected\t\t\t\t%lu\n, BIT(dword, 2));
+printf(HDMIB Encoding\t\t\t\t\t\t[0x%lx] %s\n,
+ BITS(dword, 11, 10),
sdvo_hdmi_encoding[BITS(dword, 11, 10)]);
printf(HDMIB Null_packets_enabled_during_Vsync\t\t\t%u\n, !!(dword
SDVO_NULL_PACKETS_DURING_VSYNC));
printf(HDMIB Audio_Output_Enable\t\t\t\t%u\n, !!(dword
SDVO_AUDIO_ENABLE));
@@ -570,6 +578,8 @@ static void dump_ironlake(void)
printf(HDMIC Transcoder_Select\t\t\t\t\t%s\n, BIT(dword, 30) ?
Transcoder B : Transcoder A);
printf(HDMIC HDCP_Port_Select\t\t\t\t\t%lu\n, BIT(dword, 5));
printf(HDMIC Digital_Port_C_Detected\t\t\t\t%lu\n, BIT(dword, 2));
+printf(HDMIC Encoding\t\t\t\t\t\t[0x%lx] %s\n,
+ BITS(dword, 11, 10),
sdvo_hdmi_encoding[BITS(dword, 11, 10)]);
printf(HDMIC Null_packets_enabled_during_Vsync\t\t\t%u\n, !!(dword
SDVO_NULL_PACKETS_DURING_VSYNC));
printf(HDMIC Audio_Output_Enable\t\t\t\t%u\n, !!(dword
SDVO_AUDIO_ENABLE));
@@ -578,6 +588,8 @@ static void dump_ironlake(void)
printf(HDMID Transcoder_Select\t\t\t\t\t%s\n, BIT(dword, 30) ?
Transcoder B : Transcoder A);
printf(HDMID HDCP_Port_Select\t\t\t\t\t%lu\n, BIT(dword, 5));
printf(HDMID Digital_Port_D_Detected\t\t\t\t%lu\n, BIT(dword, 2));
+printf(HDMID Encoding\t\t\t\t\t\t[0x%lx] %s\n,
+ BITS(dword, 11, 10),
sdvo_hdmi_encoding[BITS(dword, 11, 10)]);
printf(HDMID Null_packets_enabled_during_Vsync\t\t\t%u\n, !!(dword
SDVO_NULL_PACKETS_DURING_VSYNC));
printf(HDMID Audio_Output_Enable\t\t\t\t%u\n, !!(dword
SDVO_AUDIO_ENABLE));
@@ -988,6 +1000,8 @@ static void dump_cpt(void)
printf(HDMIB sDVO_Border_Enable\t\t\t\t%lu\n, BIT(dword, 7));
printf(HDMIB HDCP_Port_Select\t\t\t\t\t%lu\n, BIT(dword, 5));
printf(HDMIB Port_Detected\t\t\t\t\t%lu\n, BIT(dword, 2));
+printf(HDMIB Encoding\t\t\t\t\t\t[0x%lx] %s\n,
+ BITS(dword, 11, 10),
sdvo_hdmi_encoding[BITS(dword, 11, 10)]);
printf(HDMIB HDMI_or_DVI_Select\t\t\t\t%s\n, BIT(dword, 9) ? HDMI :
DVI);
printf(HDMIB Audio_Output_Enable\t\t\t\t%u\n, !!(dword
SDVO_AUDIO_ENABLE));
@@ -998,6 +1012,8 @@ static void dump_cpt(void)
printf(HDMIC sDVO_Border_Enable\t\t\t\t%lu\n, BIT(dword, 7));
printf(HDMIC HDCP_Port_Select\t\t\t\t\t%lu\n, BIT(dword, 5));
printf(HDMIC Port_Detected\t\t\t\t\t%lu\n, BIT(dword, 2));
+printf(HDMIC Encoding\t\t\t\t\t\t[0x%lx] %s\n,
+ BITS(dword, 11, 10),
sdvo_hdmi_encoding[BITS(dword, 11, 10)]);
printf(HDMIC HDMI_or_DVI_Select\t\t\t\t%s\n, BIT(dword, 9) ? HDMI :
DVI);
printf(HDMIC Audio_Output_Enable\t\t\t\t%u\n, !!(dword
SDVO_AUDIO_ENABLE));
@@ -1008,6 +1024,8 @@ static void dump_cpt(void)
printf(HDMID sDVO_Border_Enable\t\t\t\t%lu\n, BIT(dword, 7));
printf(HDMID HDCP_Port_Select\t\t\t\t\t%lu\n, BIT(dword, 5));
printf(HDMID Port_Detected\t\t\t\t\t%lu\n, BIT(dword, 2));
+printf(HDMID Encoding\t\t\t\t\t\t[0x%lx] %s\n,
+ BITS(dword, 11, 10),
sdvo_hdmi_encoding[BITS(dword, 11, 10)]);
printf(HDMID HDMI_or_DVI_Select\t\t\t\t%s\n, BIT(dword, 9) ? HDMI :
DVI);
printf(HDMID Audio_Output_Enable\t\t\t\t%u\n, !!(dword
SDVO_AUDIO_ENABLE));
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 11/18] intel_audio_dump: show DP control registers for Ironlake
Signed-off-by: Wu Fengguang fengguang...@intel.com --- tools/intel_audio_dump.c | 30 ++ 1 file changed, 30 insertions(+) --- intel-gpu-tools.orig/tools/intel_audio_dump.c 2011-11-12 10:52:40.0 +0800 +++ intel-gpu-tools/tools/intel_audio_dump.c2011-11-12 10:52:46.0 +0800 @@ -508,6 +508,9 @@ static void dump_ironlake(void) dump_reg(HDMIB,sDVO/HDMI Port B Control); dump_reg(HDMIC,HDMI Port C Control); dump_reg(HDMID,HDMI Port D Control); +dump_reg(PCH_DP_B, DisplayPort B Control Register); +dump_reg(PCH_DP_C, DisplayPort C Control Register); +dump_reg(PCH_DP_D, DisplayPort D Control Register); dump_reg(AUD_CONFIG_A, Audio Configuration - Transcoder A); dump_reg(AUD_CONFIG_B, Audio Configuration - Transcoder B); dump_reg(AUD_CTS_ENABLE_A, Audio CTS Programming Enable - Transcoder A); @@ -570,6 +573,33 @@ static void dump_ironlake(void) printf(HDMID Null_packets_enabled_during_Vsync\t\t\t%u\n, !!(dword SDVO_NULL_PACKETS_DURING_VSYNC)); printf(HDMID Audio_Output_Enable\t\t\t\t%u\n, !!(dword SDVO_AUDIO_ENABLE)); +dword = INREG(PCH_DP_B); +printf(PCH_DP_B DisplayPort_Enable\t\t\t\t%lu\n, BIT(dword, 31)); +printf(PCH_DP_B Transcoder_Select\t\t\t\t%s\n, BIT(dword, 30) ? Transcoder B : Transcoder A); +printf(PCH_DP_B Port_Width_Selection\t\t\t\t[0x%lx] %s\n, + BITS(dword, 21, 19), dp_port_width[BITS(dword, 21, 19)]); +printf(PCH_DP_B Port_Detected\t\t\t\t\t%lu\n, BIT(dword, 2)); +printf(PCH_DP_B HDCP_Port_Select\t\t\t\t%lu\n, BIT(dword, 5)); +printf(PCH_DP_B Audio_Output_Enable\t\t\t\t%lu\n, BIT(dword, 6)); + +dword = INREG(PCH_DP_C); +printf(PCH_DP_C DisplayPort_Enable\t\t\t\t%lu\n, BIT(dword, 31)); +printf(PCH_DP_C Transcoder_Select\t\t\t\t%s\n, BIT(dword, 30) ? Transcoder B : Transcoder A); +printf(PCH_DP_C Port_Width_Selection\t\t\t\t[0x%lx] %s\n, + BITS(dword, 21, 19), dp_port_width[BITS(dword, 21, 19)]); +printf(PCH_DP_C Port_Detected\t\t\t\t\t%lu\n, BIT(dword, 2)); +printf(PCH_DP_C HDCP_Port_Select\t\t\t\t%lu\n, BIT(dword, 5)); +printf(PCH_DP_C Audio_Output_Enable\t\t\t\t%lu\n, BIT(dword, 6)); + +dword = INREG(PCH_DP_D); +printf(PCH_DP_D DisplayPort_Enable\t\t\t\t%lu\n, BIT(dword, 31)); +printf(PCH_DP_D Transcoder_Select\t\t\t\t%s\n, BIT(dword, 30) ? Transcoder B : Transcoder A); +printf(PCH_DP_D Port_Width_Selection\t\t\t\t[0x%lx] %s\n, + BITS(dword, 21, 19), dp_port_width[BITS(dword, 21, 19)]); +printf(PCH_DP_D Port_Detected\t\t\t\t\t%lu\n, BIT(dword, 2)); +printf(PCH_DP_D HDCP_Port_Select\t\t\t\t%lu\n, BIT(dword, 5)); +printf(PCH_DP_D Audio_Output_Enable\t\t\t\t%lu\n, BIT(dword, 6)); + dword = INREG(AUD_CONFIG_A); printf(AUD_CONFIG_A Pixel_Clock\t\t\t\t[0x%lx] %s\n, BITS(dword, 19, 16), OPNAME(pixel_clock, BITS(dword, 19, 16))); ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 00/18] intel-gpu-tools: intel_audio_dump updates
Am Samstag, den 12.11.2011, 11:12 +0800 schrieb Wu Fengguang: A bunch of cleanups, fixes and new fields to intel_audio_dump, tested OK on G45, Ironlake and IvyBridge. Christopher White mentioned some lacks in the documentation like missing dependencies. Could you update that too, please? Thanks, Paul signature.asc Description: This is a digitally signed message part ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] intel-gpu-tools: Please release new version (was: [PATCH 00/18] intel-gpu-tools: intel_audio_dump updates)
Am Samstag, den 12.11.2011, 11:12 +0800 schrieb Wu Fengguang: A bunch of cleanups, fixes and new fields to intel_audio_dump, tested OK on G45, Ironlake and IvyBridge. Christopher White mentioned the last release or tag happened a long time ago. Is a new release planned? Most of the time distributions package those more easily. Thanks, Paul signature.asc Description: This is a digitally signed message part ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
