[Intel-gfx] ✗ Fi.CI.BAT: failure for Pipe level color management (rev10)

[Patchwork]

== Series Details ==

Series: Pipe level color management (rev10)
URL   : https://patchwork.freedesktop.org/series/2720/
State : failure

== Summary ==

Series 2720v10 Pipe level color management
http://patchwork.freedesktop.org/api/1.0/series/2720/revisions/10/mbox/

Test drv_hangman:
Subgroup error-state-basic:
pass   -> FAIL   (ilk-hp8440p)
Test kms_flip:
Subgroup basic-flip-vs-modeset:
pass   -> DMESG-WARN (skl-i7k-2)
incomplete -> PASS   (ilk-hp8440p) UNSTABLE
Test kms_force_connector_basic:
Subgroup force-load-detect:
fail   -> DMESG-FAIL (snb-x220t)
dmesg-fail -> FAIL   (ilk-hp8440p)
fail   -> DMESG-FAIL (ivb-t430s)
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass   -> DMESG-WARN (skl-i7k-2) UNSTABLE
Subgroup suspend-read-crc-pipe-b:
incomplete -> PASS   (hsw-gt2)
pass   -> FAIL   (byt-nuc)
Subgroup suspend-read-crc-pipe-c:
dmesg-warn -> PASS   (skl-i7k-2) UNSTABLE

bdw-nuci7total:166  pass:155  dwarn:0   dfail:0   fail:0   skip:11 
bdw-ultratotal:169  pass:155  dwarn:0   dfail:0   fail:0   skip:14 
bsw-nuc-2total:169  pass:138  dwarn:0   dfail:0   fail:1   skip:30 
byt-nuc  total:169  pass:143  dwarn:0   dfail:0   fail:1   skip:25 
hsw-brixbox  total:169  pass:155  dwarn:0   dfail:0   fail:0   skip:14 
hsw-gt2  total:169  pass:158  dwarn:0   dfail:1   fail:0   skip:10 
ilk-hp8440p  total:169  pass:117  dwarn:1   dfail:0   fail:2   skip:49 
ivb-t430stotal:169  pass:154  dwarn:0   dfail:1   fail:0   skip:14 
skl-i7k-2total:169  pass:151  dwarn:2   dfail:0   fail:0   skip:16 
snb-dellxps  total:169  pass:146  dwarn:0   dfail:0   fail:1   skip:22 
snb-x220ttotal:169  pass:146  dwarn:0   dfail:1   fail:1   skip:21 

Results at /archive/results/CI_IGT_test/Patchwork_1488/

e511a05b4b3bb4d1dbca99b00af6d0dc0a65d295 drm-intel-nightly: 
2016y-02m-26d-13h-42m-46s UTC integration manifest
98cfbc2f18ac844afc715385a3fdc861606b254a drm/i915: Implement color management 
on chv
afd5fa33716f8cfc794b88818fd6ac079012ef6c drm/i915: Implement color management 
on bdw/skl/bxt/kbl
8a266caaef3ea6654a3d60509ee57c0019f4b46b drm: introduce pipe color correction 
properties
11cd68de5909134d1f8e64fd26384efb267b1822 drm/i915: Do not read GAMMA_MODE 
register
a0496cfaaf5b69145f0e8402915e1a433402956c drm/i915: Extract out gamma table and 
CSC to their own file

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Re: [Intel-gfx] [PATCH 3/5] drm: introduce pipe color correction properties

[Emil Velikov]

On 26 February 2016 at 15:43, Lionel Landwerlin
 wrote:
> On 26/02/16 00:36, Emil Velikov wrote:
>>
>> Hi Lionel,
>>
>> A bunch of suggestions - feel free to take or ignore them :-)
>>
>> On 25 February 2016 at 10:58, Lionel Landwerlin
>>  wrote:

> I'm not sure it matters as the drm_crtc_state you're set properties on will
> be discarded if there is an error.
> The current drm_crtc_state that has been applied onto the hardware should be
> untouched.
>
That's the thing - the current drm_crts_state (mode_blob) is being
discarded, as opposed to the newly setup one. Although I could have
misunderstood something.


>
> This is because we accept more than one size of degamma/gamma LUT (legacy ->
> 256 elements, new LUT -> (de)gamma_lut_size elements).
> It's up for the driver the check the size and raise an error in its
> atomic_check() vfunc.
>
Ahh yes the legacy vs atomic difference.


>
> Moving the if (blob == NULL) right after the blob allocation to make it
> simpler.
>
> What about completeness? Is there something inherently wrong here?
The suggestion to reorder things is mostly to keep the setup/teardown
order in reverse order - create_blob, create_state and drop_state,
drop_blob. As you've noticed, I'm kind of a sucker for those :-) There
are no inter-dependencies that would require it here so it's not
required.

>>
>>
>>> +   state->acquire_ctx = crtc->dev->mode_config.acquire_ctx;
>>> +retry:
>>> +   crtc_state = drm_atomic_get_crtc_state(state, crtc);
>>> +   if (IS_ERR(crtc_state)) {
>>> +   ret = PTR_ERR(crtc_state);
>>> +   goto fail;
>>> +   }
>>> +
>>> +   /* Reset DEGAMMA_LUT and CTM properties. */
>>> +   ret = drm_atomic_crtc_set_property(crtc, crtc_state,
>>> +   config->degamma_lut_property, 0);
>>> +   if (ret)
>>> +   goto fail;
>>
>> Add new blank line please.
>
>
> Sure.
>>
>>
>>> +   ret = drm_atomic_crtc_set_property(crtc, crtc_state,
>>> +   config->ctm_property, 0);
>>> +   if (ret)
>>> +   goto fail;
>>> +
>>> +   /* Set GAMMA_LUT with legacy values. */
>>> +   if (blob == NULL) {
>>> +   ret = -ENOMEM;
>>> +   goto fail;
>>> +   }
>>> +
>>> +   blob_data = (struct drm_color_lut *) blob->data;
>>> +   for (i = 0; i < size; i++) {
>>> +   blob_data[i].red = red[i];
>>> +   blob_data[i].green = green[i];
>>> +   blob_data[i].blue = blue[i];
>>> +   }
>>> +
>>
>> Move this loop after create_blob()
>
> Thanks, indeed no need to refill it in case of retry.
>
>>
>>> +   ret = drm_atomic_crtc_set_property(crtc, crtc_state,
>>> +   config->gamma_lut_property, blob->base.id);
>>> +   if (ret)
>>> +   goto fail;
>>> +
>>> +   ret = drm_atomic_commit(state);
>>> +   if (ret != 0)
>>
>> Please check in a consistent way. Currently we have ret != 0 vs ret
>> and foo == NULL vs !foo.
>
>
> Sure.
>
>>
>>> +   goto fail;
>>> +
>>> +   drm_property_unreference_blob(blob);
>>> +
>>> +   /* Driver takes ownership of state on successful commit. */
>>
>> Move the comment before unreference_blob(), so that it's closer to
>> atomic_commit() ?
>
>
> Sure.
>>
>>
>>> --- a/drivers/gpu/drm/drm_crtc.c
>>> +++ b/drivers/gpu/drm/drm_crtc.c
>>> @@ -1554,6 +1554,41 @@ static int
>>> drm_mode_create_standard_properties(struct drm_device *dev)
>>>  return -ENOMEM;
>>>  dev->mode_config.prop_mode_id = prop;
>>>
>>> +   prop = drm_property_create(dev,
>>> +   DRM_MODE_PROP_BLOB,
>>> +   "DEGAMMA_LUT", 0);
>>
>> Just wondering -  don't we want this and the remaining properties to
>> be atomic only ? I doubt we have userspace that [will be updated to]
>> handle these, yet lacks atomic.
>
> This was pointed out by Matt already. Here is Daniel Stone's response :
> https://lists.freedesktop.org/archives/intel-gfx/2016-January/086120.html
>
> I think it's fine to have these properties not atomic because it's not
> really something you update very often (maybe just when starting your UI).
> That's actually how we would like to use them in ChromiumOS as a first step,
> until eventually ChromiumOS switches to atomic.
>
It wasn't a question of "can it be used" but more of "would it make
sense to not switch to atomics once we're here". As is, userspace will
need to have two slightly different code paths. Put the question "how
to deal with if compositor crashes and (re)applying gamma/etc.
multiple times" by Daniel Vettel, on top of it all and things get
extra messy. In both usespace in kernel.

My line of thought is - if there is a high demand for
non-atomic(legacy) degamma/etc. one can easily add it. On the other
hand, once it lands one cannot remove the code from the kernel, ever.

It's up-to you guys really. Just thought I 

Re: [Intel-gfx] [PATCH] drm/i915: Fix bogus dig_port_map[] assignment for pre-HSW

[Ville Syrjälä]

On Wed, Feb 24, 2016 at 03:35:22PM +0100, Takashi Iwai wrote:
> The recent commit [0bdf5a05647a: drm/i915: Add reverse mapping between
> port and intel_encoder] introduced a reverse mapping to retrieve
> intel_dig_port object from the port number.  The code assumed that the
> port vs intel_dig_port are 1:1 mapping.  But in reality, this was a
> too naive assumption.
> 
> As Martin reported about the missing HDMI audio on his SNB machine,
> pre-HSW chips may have multiple intel_dig_port objects corresponding
> to the same port.  Since we assign the mapping statically at the init
> time and the multiple objects override the map, it may not match with
> the actually enabled output.
> 
> This patch tries to address the regression above.  The reverse mapping
> is provided basically only for the audio callbacks, so now we set /
> clear the mapping dynamically at enabling and disabling HDMI/DP audio,
> so that we can always track the latest and correct object
> corresponding to the given port.
> 
> Fixes: 0bdf5a05647a ('drm/i915: Add reverse mapping between port and 
> intel_encoder')
> Reported-and-tested-by: Martin Kepplinger 
> Signed-off-by: Takashi Iwai 

lgtm

Reviewed-by: Ville Syrjälä 

> ---
>  drivers/gpu/drm/i915/intel_audio.c | 3 +++
>  drivers/gpu/drm/i915/intel_ddi.c   | 1 -
>  drivers/gpu/drm/i915/intel_dp.c| 1 -
>  drivers/gpu/drm/i915/intel_hdmi.c  | 2 --
>  4 files changed, 3 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_audio.c 
> b/drivers/gpu/drm/i915/intel_audio.c
> index 31f6d212fb1b..30f921421b0c 100644
> --- a/drivers/gpu/drm/i915/intel_audio.c
> +++ b/drivers/gpu/drm/i915/intel_audio.c
> @@ -527,6 +527,8 @@ void intel_audio_codec_enable(struct intel_encoder 
> *intel_encoder)
>  
>   mutex_lock(_priv->av_mutex);
>   intel_dig_port->audio_connector = connector;
> + /* referred in audio callbacks */
> + dev_priv->dig_port_map[port] = intel_encoder;
>   mutex_unlock(_priv->av_mutex);
>  
>   if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)
> @@ -554,6 +556,7 @@ void intel_audio_codec_disable(struct intel_encoder 
> *intel_encoder)
>  
>   mutex_lock(_priv->av_mutex);
>   intel_dig_port->audio_connector = NULL;
> + dev_priv->dig_port_map[port] = NULL;
>   mutex_unlock(_priv->av_mutex);
>  
>   if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 54a165b9c92d..a50fc452d5f1 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -3312,7 +3312,6 @@ void intel_ddi_init(struct drm_device *dev, enum port 
> port)
>   intel_encoder->get_config = intel_ddi_get_config;
>  
>   intel_dig_port->port = port;
> - dev_priv->dig_port_map[port] = intel_encoder;
>   intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
> (DDI_BUF_PORT_REVERSAL |
>  DDI_A_4_LANES);
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 1bbd67b046da..acf918728492 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -6035,7 +6035,6 @@ intel_dp_init(struct drm_device *dev,
>   }
>  
>   intel_dig_port->port = port;
> - dev_priv->dig_port_map[port] = intel_encoder;
>   intel_dig_port->dp.output_reg = output_reg;
>  
>   intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c 
> b/drivers/gpu/drm/i915/intel_hdmi.c
> index 4a77639a489d..23ee48dc765f 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -2146,7 +2146,6 @@ void intel_hdmi_init_connector(struct 
> intel_digital_port *intel_dig_port,
>  void intel_hdmi_init(struct drm_device *dev,
>i915_reg_t hdmi_reg, enum port port)
>  {
> - struct drm_i915_private *dev_priv = dev->dev_private;
>   struct intel_digital_port *intel_dig_port;
>   struct intel_encoder *intel_encoder;
>   struct intel_connector *intel_connector;
> @@ -2215,7 +2214,6 @@ void intel_hdmi_init(struct drm_device *dev,
>   intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
>  
>   intel_dig_port->port = port;
> - dev_priv->dig_port_map[port] = intel_encoder;
>   intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
>   intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
>  
> -- 
> 2.7.2

-- 
Ville Syrjälä
Intel OTC
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Re: [Intel-gfx] [PATCH v4] drm/i915: Execlists small cleanups and micro-optimisations

[Chris Wilson]

On Fri, Feb 26, 2016 at 04:58:32PM +, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin 
> 
> Assorted changes in the areas of code cleanup, reduction of
> invariant conditional in the interrupt handler and lock
> contention and MMIO access optimisation.
> 
>  * Remove needless initialization.
>  * Improve cache locality by reorganizing code and/or using
>branch hints to keep unexpected or error conditions out
>of line.
>  * Favor busy submit path vs. empty queue.
>  * Less branching in hot-paths.
> 
> v2:
> 
>  * Avoid mmio reads when possible. (Chris Wilson)
>  * Use natural integer size for csb indices.
>  * Remove useless return value from execlists_update_context.
>  * Extract 32-bit ppgtt PDPs update so it is out of line and
>shared with two callers.
>  * Grab forcewake across all mmio operations to ease the
>load on uncore lock and use chepear mmio ops.
> 
> v3:
> 
>  * Removed some more pointless u8 data types.
>  * Removed unused return from execlists_context_queue.
>  * Commit message updates.
> 
> v4:
>  * Unclumsify the unqueue if statement. (Chris Wilson)
>  * Hide forcewake from the queuing function. (Chris Wilson)
> 
> Version 3 now makes the irq handling code path ~20% smaller on
> 48-bit PPGTT hardware, and a little bit less elsewhere. Hot
> paths are mostly in-line now and hammering on the uncore
> spinlock is greatly reduced together with mmio traffic to an
> extent.
> 
> Benchmarking with "gem_latency -n 100" (keep submitting
> batches with 100 nop instruction) shows approximately 4% higher
> throughput, 2% less CPU time and 22% smaller latencies. This was
> on a big-core while small-cores could benefit even more.

Just add a quick comment about "gem_latency -n 0" suggesting an oddity
with synchronous workloads that bears further study (just so that we
have the hint/reminder about the test case to run).
 
> Most likely reason for the improvements are the MMIO
> optimization and uncore lock traffic reduction.
> 
> Signed-off-by: Tvrtko Ursulin 
> Cc: Chris Wilson 
Reviewed-by: Chris Wilson 
-Chris

-- 
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Re: [Intel-gfx] [PATCH] drm/i915: Fix bogus dig_port_map[] assignment for pre-HSW

[Takashi Iwai]

Sorry, Cc to Jani was missing mistakenly.

Please check this.  It's a regression in 4.5-rc.


thanks,

Takashi

On Wed, 24 Feb 2016 15:35:22 +0100,
Takashi Iwai wrote:
> 
> The recent commit [0bdf5a05647a: drm/i915: Add reverse mapping between
> port and intel_encoder] introduced a reverse mapping to retrieve
> intel_dig_port object from the port number.  The code assumed that the
> port vs intel_dig_port are 1:1 mapping.  But in reality, this was a
> too naive assumption.
> 
> As Martin reported about the missing HDMI audio on his SNB machine,
> pre-HSW chips may have multiple intel_dig_port objects corresponding
> to the same port.  Since we assign the mapping statically at the init
> time and the multiple objects override the map, it may not match with
> the actually enabled output.
> 
> This patch tries to address the regression above.  The reverse mapping
> is provided basically only for the audio callbacks, so now we set /
> clear the mapping dynamically at enabling and disabling HDMI/DP audio,
> so that we can always track the latest and correct object
> corresponding to the given port.
> 
> Fixes: 0bdf5a05647a ('drm/i915: Add reverse mapping between port and 
> intel_encoder')
> Reported-and-tested-by: Martin Kepplinger 
> Signed-off-by: Takashi Iwai 
> ---
>  drivers/gpu/drm/i915/intel_audio.c | 3 +++
>  drivers/gpu/drm/i915/intel_ddi.c   | 1 -
>  drivers/gpu/drm/i915/intel_dp.c| 1 -
>  drivers/gpu/drm/i915/intel_hdmi.c  | 2 --
>  4 files changed, 3 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_audio.c 
> b/drivers/gpu/drm/i915/intel_audio.c
> index 31f6d212fb1b..30f921421b0c 100644
> --- a/drivers/gpu/drm/i915/intel_audio.c
> +++ b/drivers/gpu/drm/i915/intel_audio.c
> @@ -527,6 +527,8 @@ void intel_audio_codec_enable(struct intel_encoder 
> *intel_encoder)
>  
>   mutex_lock(_priv->av_mutex);
>   intel_dig_port->audio_connector = connector;
> + /* referred in audio callbacks */
> + dev_priv->dig_port_map[port] = intel_encoder;
>   mutex_unlock(_priv->av_mutex);
>  
>   if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)
> @@ -554,6 +556,7 @@ void intel_audio_codec_disable(struct intel_encoder 
> *intel_encoder)
>  
>   mutex_lock(_priv->av_mutex);
>   intel_dig_port->audio_connector = NULL;
> + dev_priv->dig_port_map[port] = NULL;
>   mutex_unlock(_priv->av_mutex);
>  
>   if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 54a165b9c92d..a50fc452d5f1 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -3312,7 +3312,6 @@ void intel_ddi_init(struct drm_device *dev, enum port 
> port)
>   intel_encoder->get_config = intel_ddi_get_config;
>  
>   intel_dig_port->port = port;
> - dev_priv->dig_port_map[port] = intel_encoder;
>   intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
> (DDI_BUF_PORT_REVERSAL |
>  DDI_A_4_LANES);
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 1bbd67b046da..acf918728492 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -6035,7 +6035,6 @@ intel_dp_init(struct drm_device *dev,
>   }
>  
>   intel_dig_port->port = port;
> - dev_priv->dig_port_map[port] = intel_encoder;
>   intel_dig_port->dp.output_reg = output_reg;
>  
>   intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c 
> b/drivers/gpu/drm/i915/intel_hdmi.c
> index 4a77639a489d..23ee48dc765f 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -2146,7 +2146,6 @@ void intel_hdmi_init_connector(struct 
> intel_digital_port *intel_dig_port,
>  void intel_hdmi_init(struct drm_device *dev,
>i915_reg_t hdmi_reg, enum port port)
>  {
> - struct drm_i915_private *dev_priv = dev->dev_private;
>   struct intel_digital_port *intel_dig_port;
>   struct intel_encoder *intel_encoder;
>   struct intel_connector *intel_connector;
> @@ -2215,7 +2214,6 @@ void intel_hdmi_init(struct drm_device *dev,
>   intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
>  
>   intel_dig_port->port = port;
> - dev_priv->dig_port_map[port] = intel_encoder;
>   intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
>   intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
>  
> -- 
> 2.7.2
> 
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[Intel-gfx] [PATCH igt 2/5] kms_frontbuffer_tracking: don't pass the crtc idx to init_mode_params

[Paulo Zanoni]

We already pass the crtc id, so use the id to retrieve the index.
We'll change the way we pass the crtc id in the next commits, so we'll
have to call a function to calculate the index based on the id at that
point. Do the change now in order to avoid big commits later.

Signed-off-by: Paulo Zanoni 
---
 tests/kms_frontbuffer_tracking.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/tests/kms_frontbuffer_tracking.c b/tests/kms_frontbuffer_tracking.c
index 88bf5a5..d641cc7 100644
--- a/tests/kms_frontbuffer_tracking.c
+++ b/tests/kms_frontbuffer_tracking.c
@@ -368,14 +368,14 @@ static void print_mode_info(const char *screen, struct 
modeset_params *params)
 }
 
 static void init_mode_params(struct modeset_params *params, uint32_t crtc_id,
-int crtc_index, uint32_t connector_id,
-drmModeModeInfoPtr mode)
+uint32_t connector_id, drmModeModeInfoPtr mode)
 {
uint32_t plane_id = 0;
+   int crtc_idx = kmstest_get_crtc_idx(drm.res, crtc_id);
int i;
 
for (i = 0; i < drm.plane_res->count_planes && plane_id == 0; i++)
-   if ((drm.planes[i]->possible_crtcs & (1 << crtc_index)) &&
+   if ((drm.planes[i]->possible_crtcs & (1 << crtc_idx)) &&
drm.plane_types[i] == DRM_PLANE_TYPE_OVERLAY)
plane_id = drm.planes[i]->plane_id;
 
@@ -465,7 +465,7 @@ static bool init_modeset_cached_params(void)
if (!prim_connector_id)
return false;
 
-   init_mode_params(_mode_params, drm.res->crtcs[0], 0,
+   init_mode_params(_mode_params, drm.res->crtcs[0],
 prim_connector_id, prim_mode);
print_mode_info("Primary", _mode_params);
 
@@ -475,7 +475,7 @@ static bool init_modeset_cached_params(void)
}
 
igt_assert(drm.res->count_crtcs >= 2);
-   init_mode_params(_mode_params, drm.res->crtcs[1], 1,
+   init_mode_params(_mode_params, drm.res->crtcs[1],
 scnd_connector_id, scnd_mode);
print_mode_info("Secondary", _mode_params);
 
-- 
2.7.0

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[Intel-gfx] [PATCH igt 3/5] kms_frontbuffer_tracking: extract find_connector function

[Paulo Zanoni]

We're going to make our search for connnectors a little more
complicated, so extract the function since we're going to call it a
few more times.

Signed-off-by: Paulo Zanoni 
---
 tests/kms_frontbuffer_tracking.c | 70 ++--
 1 file changed, 38 insertions(+), 32 deletions(-)

diff --git a/tests/kms_frontbuffer_tracking.c b/tests/kms_frontbuffer_tracking.c
index d641cc7..3b2ca8a 100644
--- a/tests/kms_frontbuffer_tracking.c
+++ b/tests/kms_frontbuffer_tracking.c
@@ -368,7 +368,8 @@ static void print_mode_info(const char *screen, struct 
modeset_params *params)
 }
 
 static void init_mode_params(struct modeset_params *params, uint32_t crtc_id,
-uint32_t connector_id, drmModeModeInfoPtr mode)
+drmModeConnectorPtr connector,
+drmModeModeInfoPtr mode)
 {
uint32_t plane_id = 0;
int crtc_idx = kmstest_get_crtc_idx(drm.res, crtc_id);
@@ -382,7 +383,7 @@ static void init_mode_params(struct modeset_params *params, 
uint32_t crtc_id,
igt_assert(plane_id);
 
params->crtc_id = crtc_id;
-   params->connector_id = connector_id;
+   params->connector_id = connector->connector_id;
params->mode = mode;
params->sprite_id = plane_id;
 
@@ -427,56 +428,61 @@ static bool connector_get_mode(drmModeConnectorPtr c, 
drmModeModeInfoPtr *mode)
return true;
 }
 
-static bool init_modeset_cached_params(void)
+static bool find_connector(bool edp_only, uint32_t forbidden_id,
+  drmModeConnectorPtr *ret_connector,
+  drmModeModeInfoPtr *ret_mode)
 {
+   drmModeConnectorPtr c = NULL;
+   drmModeModeInfoPtr mode = NULL;
int i;
-   uint32_t prim_connector_id = 0, scnd_connector_id = 0;
-   drmModeModeInfoPtr prim_mode = NULL, scnd_mode = NULL;
-   drmModeModeInfoPtr tmp_mode;
 
-   /* First, try to find an eDP monitor since it's the only possible type
-* for PSR.  */
for (i = 0; i < drm.res->count_connectors; i++) {
-   if (drm.connectors[i]->connector_type != DRM_MODE_CONNECTOR_eDP)
-   continue;
+   c = drm.connectors[i];
 
-   if (connector_get_mode(drm.connectors[i], _mode)) {
-   prim_connector_id = drm.res->connectors[i];
-   prim_mode = tmp_mode;
-   }
-   }
-   for (i = 0; i < drm.res->count_connectors; i++) {
-   /* Don't pick again what we just selected on the above loop. */
-   if (drm.res->connectors[i] == prim_connector_id)
+   if (edp_only && c->connector_type != DRM_MODE_CONNECTOR_eDP)
+   continue;
+   if (c->connector_id == forbidden_id)
+   continue;
+   if (!connector_get_mode(c, ))
continue;
 
-   if (connector_get_mode(drm.connectors[i], _mode)) {
-   if (!prim_connector_id) {
-   prim_connector_id = drm.res->connectors[i];
-   prim_mode = tmp_mode;
-   } else if (!scnd_connector_id) {
-   scnd_connector_id = drm.res->connectors[i];
-   scnd_mode = tmp_mode;
-   break;
-   }
-   }
+   *ret_connector = c;
+   *ret_mode = mode;
+   return true;
}
 
-   if (!prim_connector_id)
+   return false;
+}
+
+static bool init_modeset_cached_params(void)
+{
+   drmModeConnectorPtr prim_connector = NULL, scnd_connector = NULL;
+   drmModeModeInfoPtr prim_mode = NULL, scnd_mode = NULL;
+
+   /* First, try to find an eDP monitor since it's the only possible type
+* for PSR.  */
+   find_connector(true, 0, _connector, _mode);
+   if (!prim_connector)
+   find_connector(false, 0, _connector, _mode);
+
+   if (!prim_connector)
return false;
 
+   find_connector(false, prim_connector->connector_id, _connector,
+  _mode);
+
init_mode_params(_mode_params, drm.res->crtcs[0],
-prim_connector_id, prim_mode);
+prim_connector, prim_mode);
print_mode_info("Primary", _mode_params);
 
-   if (!scnd_connector_id) {
+   if (!scnd_connector) {
scnd_mode_params.connector_id = 0;
return true;
}
 
igt_assert(drm.res->count_crtcs >= 2);
init_mode_params(_mode_params, drm.res->crtcs[1],
-scnd_connector_id, scnd_mode);
+scnd_connector, scnd_mode);
print_mode_info("Secondary", _mode_params);
 
return true;
-- 
2.7.0

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[Intel-gfx] [PATCH igt 5/5] tests: fix CRTC assignment for a few tests

[Paulo Zanoni]

All the tests I wrote always assumed that every connector supported
CRTC 0. This is not the case for BSW and possibly others, so fix the
tests before the CI reports more failures.

Signed-off-by: Paulo Zanoni 
---
 lib/igt_kms.c| 32 
 lib/igt_kms.h|  3 +++
 tests/kms_draw_crc.c | 13 +++--
 tests/kms_fbcon_fbt.c| 12 ++--
 tests/kms_frontbuffer_tracking.c | 23 ---
 tests/pm_lpsp.c  | 35 ++-
 tests/pm_rpm.c   | 24 ++--
 tools/intel_residency.c  | 15 ---
 8 files changed, 92 insertions(+), 65 deletions(-)

diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index 285c1b6..f771f29 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -277,6 +277,38 @@ int kmstest_get_pipe_from_crtc_id(int fd, int crtc_id)
return pfci.pipe;
 }
 
+/**
+ * kmstest_find_crtc_for_connector:
+ * @fd: DRM fd
+ * @res: libdrm resources pointer
+ * @connector: libdrm connector pointer
+ * @crtc_blacklist_idx_mask: a mask of CRTC indexes that we can't return
+ *
+ * Returns: the CRTC ID for a CRTC that fits the connector, otherwise it 
asserts
+ * false and never returns. The blacklist mask can be used in case you have
+ * CRTCs that are already in use by other connectors.
+ */
+uint32_t kmstest_find_crtc_for_connector(int fd, drmModeRes *res,
+drmModeConnector *connector,
+uint32_t crtc_blacklist_idx_mask)
+{
+   drmModeEncoder *e;
+   uint32_t possible_crtcs;
+   int i, j;
+
+   for (i = 0; i < connector->count_encoders; i++) {
+   e = drmModeGetEncoder(fd, connector->encoders[i]);
+   possible_crtcs = e->possible_crtcs & ~crtc_blacklist_idx_mask;
+   drmModeFreeEncoder(e);
+
+   for (j = 0; possible_crtcs >> j; j++)
+   if (possible_crtcs & (1 << j))
+   return res->crtcs[j];
+   }
+
+   igt_assert(false);
+}
+
 /*
  * Returns: the previous mode, or KD_GRAPHICS if no /dev/tty0 was
  * found and nothing was done.
diff --git a/lib/igt_kms.h b/lib/igt_kms.h
index 2cb7c1f..5744ed0 100644
--- a/lib/igt_kms.h
+++ b/lib/igt_kms.h
@@ -151,6 +151,9 @@ bool kmstest_get_property(int drm_fd, uint32_t object_id, 
uint32_t object_type,
  drmModePropertyPtr *prop);
 void kmstest_unset_all_crtcs(int drm_fd, drmModeResPtr resources);
 int kmstest_get_crtc_idx(drmModeRes *res, uint32_t crtc_id);
+uint32_t kmstest_find_crtc_for_connector(int fd, drmModeRes *res,
+drmModeConnector *connector,
+uint32_t crtc_blacklist_idx_mask);
 
 /*
  * A small modeset API
diff --git a/tests/kms_draw_crc.c b/tests/kms_draw_crc.c
index 3f80174..9539fe4 100644
--- a/tests/kms_draw_crc.c
+++ b/tests/kms_draw_crc.c
@@ -58,25 +58,26 @@ struct modeset_params ms;
 static void find_modeset_params(void)
 {
int i;
-   uint32_t connector_id = 0, crtc_id;
+   uint32_t crtc_id;
+   drmModeConnectorPtr connector = NULL;
drmModeModeInfoPtr mode = NULL;
 
for (i = 0; i < drm_res->count_connectors; i++) {
drmModeConnectorPtr c = drm_connectors[i];
 
if (c->count_modes) {
-   connector_id = c->connector_id;
+   connector = c;
mode = >modes[0];
break;
}
}
-   igt_require(connector_id);
+   igt_require(connector);
 
-   crtc_id = drm_res->crtcs[0];
-   igt_assert(crtc_id);
+   crtc_id = kmstest_find_crtc_for_connector(drm_fd, drm_res, connector,
+ 0);
igt_assert(mode);
 
-   ms.connector_id = connector_id;
+   ms.connector_id = connector->connector_id;
ms.crtc_id = crtc_id;
ms.mode = mode;
 
diff --git a/tests/kms_fbcon_fbt.c b/tests/kms_fbcon_fbt.c
index 3c93378..586cdf5 100644
--- a/tests/kms_fbcon_fbt.c
+++ b/tests/kms_fbcon_fbt.c
@@ -114,7 +114,7 @@ static void set_mode_for_one_screen(struct drm_info *drm, 
struct igt_fb *fb,
connector_possible_fn connector_possible)
 {
int i, rc;
-   uint32_t connector_id = 0, crtc_id;
+   uint32_t crtc_id;
drmModeModeInfoPtr mode;
uint32_t buffer_id;
drmModeConnectorPtr c = NULL;
@@ -124,14 +124,14 @@ static void set_mode_for_one_screen(struct drm_info *drm, 
struct igt_fb *fb,
 
if (c->connection == DRM_MODE_CONNECTED && c->count_modes &&
connector_possible(c)) {
-   connector_id = c->connector_id;
mode = >modes[0];
break;
}
   

[Intel-gfx] [PATCH igt 4/5] kms_frontbuffer_tracking: try harder to find suitable connectors

[Paulo Zanoni]

Instead of just giving preference to an eDP primary connector, give
preference to one that's eDP and supports pipe A, then try lesser
optimal combinations later.

We could try to make our test suite use different sets of connectors
when testing FBC and PSR, but that would require some rework, and we
would still be helpless when testing the combination of FBC+PSR.

Also notice that we still hardcode pipe A for the primary connector,
regardless of whether it supports it. This will be solved in the next
commits.

Signed-off-by: Paulo Zanoni 
---
 tests/kms_frontbuffer_tracking.c | 69 
 1 file changed, 62 insertions(+), 7 deletions(-)

diff --git a/tests/kms_frontbuffer_tracking.c b/tests/kms_frontbuffer_tracking.c
index 3b2ca8a..47a37f4 100644
--- a/tests/kms_frontbuffer_tracking.c
+++ b/tests/kms_frontbuffer_tracking.c
@@ -152,10 +152,12 @@ struct rect {
 
 #define MAX_CONNECTORS 32
 #define MAX_PLANES 32
+#define MAX_ENCODERS 32
 struct {
int fd;
drmModeResPtr res;
drmModeConnectorPtr connectors[MAX_CONNECTORS];
+   drmModeEncoderPtr encoders[MAX_ENCODERS];
drmModePlaneResPtr plane_res;
drmModePlanePtr planes[MAX_PLANES];
uint64_t plane_types[MAX_PLANES];
@@ -357,6 +359,17 @@ static drmModeConnectorPtr get_connector(uint32_t id)
igt_assert(false);
 }
 
+static drmModeEncoderPtr get_encoder(uint32_t id)
+{
+   int i;
+
+   for (i = 0; i < drm.res->count_encoders; i++)
+   if (drm.res->encoders[i] == id)
+   return drm.encoders[i];
+
+   igt_assert(false);
+}
+
 static void print_mode_info(const char *screen, struct modeset_params *params)
 {
drmModeConnectorPtr c = get_connector(params->connector_id);
@@ -428,7 +441,18 @@ static bool connector_get_mode(drmModeConnectorPtr c, 
drmModeModeInfoPtr *mode)
return true;
 }
 
-static bool find_connector(bool edp_only, uint32_t forbidden_id,
+static bool connector_supports_pipe_a(drmModeConnectorPtr connector)
+{
+   int i;
+
+   for (i = 0; i < connector->count_encoders; i++)
+   if (get_encoder(connector->encoders[i])->possible_crtcs & 1)
+   return true;
+
+   return false;
+}
+
+static bool find_connector(bool edp_only, bool pipe_a, uint32_t forbidden_id,
   drmModeConnectorPtr *ret_connector,
   drmModeModeInfoPtr *ret_mode)
 {
@@ -441,6 +465,8 @@ static bool find_connector(bool edp_only, uint32_t 
forbidden_id,
 
if (edp_only && c->connector_type != DRM_MODE_CONNECTOR_eDP)
continue;
+   if (pipe_a && !connector_supports_pipe_a(c))
+   continue;
if (c->connector_id == forbidden_id)
continue;
if (!connector_get_mode(c, ))
@@ -459,17 +485,27 @@ static bool init_modeset_cached_params(void)
drmModeConnectorPtr prim_connector = NULL, scnd_connector = NULL;
drmModeModeInfoPtr prim_mode = NULL, scnd_mode = NULL;
 
-   /* First, try to find an eDP monitor since it's the only possible type
-* for PSR.  */
-   find_connector(true, 0, _connector, _mode);
+   /*
+* We have this problem where PSR is only present on eDP monitors and
+* FBC is only present on pipe A for some platforms. So we search first
+* for the ideal case of eDP supporting pipe A, and try the less optimal
+* configs later, sacrificing  one of the features.
+* TODO: refactor the code in a way that allows us to have different
+* sets of prim/scnd structs for different features.
+*/
+   find_connector(true, true, 0, _connector, _mode);
+   if (!prim_connector)
+   find_connector(true, false, 0, _connector, _mode);
if (!prim_connector)
-   find_connector(false, 0, _connector, _mode);
+   find_connector(false, true, 0, _connector, _mode);
+   if (!prim_connector)
+   find_connector(false, false, 0, _connector, _mode);
 
if (!prim_connector)
return false;
 
-   find_connector(false, prim_connector->connector_id, _connector,
-  _mode);
+   find_connector(false, false, prim_connector->connector_id,
+  _connector, _mode);
 
init_mode_params(_mode_params, drm.res->crtcs[0],
 prim_connector, prim_mode);
@@ -1291,10 +1327,14 @@ static void setup_drm(void)
 
drm.res = drmModeGetResources(drm.fd);
igt_assert(drm.res->count_connectors <= MAX_CONNECTORS);
+   igt_assert(drm.res->count_encoders <= MAX_ENCODERS);
 
for (i = 0; i < drm.res->count_connectors; i++)
drm.connectors[i] = drmModeGetConnectorCurrent(drm.fd,
drm.res->connectors[i]);
+   for (i = 0; i < 

[Intel-gfx] [PATCH igt 1/5] lib/igt_kms: add kmstest_get_crtc_idx

[Paulo Zanoni]

Move it from pm_rpm.c to lib/igt_kms and remove the hardcoded version
from kms_frontbuffer_tracking. I'm also planning to add other callers.

Signed-off-by: Paulo Zanoni 
---
 lib/igt_kms.c| 18 ++
 lib/igt_kms.h|  1 +
 tests/kms_frontbuffer_tracking.c | 10 +++---
 tests/pm_rpm.c   | 14 ++
 4 files changed, 24 insertions(+), 19 deletions(-)

diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index 90c8da7..285c1b6 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -875,6 +875,24 @@ void kmstest_unset_all_crtcs(int drm_fd, drmModeResPtr 
resources)
}
 }
 
+/**
+ * kmstest_get_crtc_idx: get the CRTC index based on its ID
+ * @res: the libdrm resources
+ * @crtc_id: the CRTC id
+ *
+ * This is useful since a few places of libdrm deal with CRTC masks.
+ */
+int kmstest_get_crtc_idx(drmModeRes *res, uint32_t crtc_id)
+{
+   int i;
+
+   for (i = 0; i < res->count_crtcs; i++)
+   if (res->crtcs[i] == crtc_id)
+   return i;
+
+   igt_assert(false);
+}
+
 /*
  * A small modeset API
  */
diff --git a/lib/igt_kms.h b/lib/igt_kms.h
index 3f7add5..2cb7c1f 100644
--- a/lib/igt_kms.h
+++ b/lib/igt_kms.h
@@ -150,6 +150,7 @@ bool kmstest_get_property(int drm_fd, uint32_t object_id, 
uint32_t object_type,
  const char *name, uint32_t *prop_id, uint64_t *value,
  drmModePropertyPtr *prop);
 void kmstest_unset_all_crtcs(int drm_fd, drmModeResPtr resources);
+int kmstest_get_crtc_idx(drmModeRes *res, uint32_t crtc_id);
 
 /*
  * A small modeset API
diff --git a/tests/kms_frontbuffer_tracking.c b/tests/kms_frontbuffer_tracking.c
index 26e12d0..88bf5a5 100644
--- a/tests/kms_frontbuffer_tracking.c
+++ b/tests/kms_frontbuffer_tracking.c
@@ -2214,16 +2214,12 @@ static void wait_flip_event(void)
 
 static void set_prim_plane_for_params(struct modeset_params *params)
 {
-   int rc, i, crtc_index = -1;
+   int rc, i;
+   int crtc_idx = kmstest_get_crtc_idx(drm.res, params->crtc_id);
uint32_t plane_id = 0;
 
-   for (i = 0; i < drm.res->count_crtcs; i++)
-   if (drm.res->crtcs[i] == params->crtc_id)
-   crtc_index = i;
-   igt_assert(crtc_index >= 0);
-
for (i = 0; i < drm.plane_res->count_planes; i++)
-   if ((drm.planes[i]->possible_crtcs & (1 << crtc_index)) &&
+   if ((drm.planes[i]->possible_crtcs & (1 << crtc_idx)) &&
drm.plane_types[i] == DRM_PLANE_TYPE_PRIMARY)
plane_id = drm.planes[i]->plane_id;
igt_assert(plane_id);
diff --git a/tests/pm_rpm.c b/tests/pm_rpm.c
index 2aa6c10..eeaf324 100644
--- a/tests/pm_rpm.c
+++ b/tests/pm_rpm.c
@@ -1681,17 +1681,6 @@ static void test_one_plane(bool dpms, uint32_t plane_id,
igt_assert(wait_for_suspended());
 }
 
-static int get_crtc_idx(drmModeResPtr res, uint32_t crtc_id)
-{
-   int i;
-
-   for (i = 0; i < res->count_crtcs; i++)
-   if (res->crtcs[i] == crtc_id)
-   return i;
-
-   igt_assert(false);
-}
-
 /* This one also triggered WARNs on our driver at some point in time. */
 static void planes_subtest(bool universal, bool dpms)
 {
@@ -1699,7 +1688,8 @@ static void planes_subtest(bool universal, bool dpms)
drmModePlaneResPtr planes;
 
igt_require(default_mode_params);
-   crtc_idx = get_crtc_idx(ms_data.res, default_mode_params->crtc_id);
+   crtc_idx = kmstest_get_crtc_idx(ms_data.res,
+   default_mode_params->crtc_id);
 
if (universal) {
rc = drmSetClientCap(drm_fd, DRM_CLIENT_CAP_UNIVERSAL_PLANES,
-- 
2.7.0

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Re: [Intel-gfx] Fwd: [PATCH] drm/i915: Avoid vblank counter for gen9+

[Rodrigo Vivi]

On Mon, Feb 22, 2016 at 6:33 AM, Imre Deak  wrote:
> On to, 2016-02-18 at 08:56 -0800, Rodrigo Vivi wrote:
>> Imre, Patrik, do you know if I'm missing something or what I'm doing
>> wrong with this power domain handler for vblanks to avoid DC states
>> when we need a reliable frame counter in place.
>>
>> Do you have better ideas?
>
> Would it be possible to check the DC5/6 entry counters whenever you try
> to access to vblank counter and consider them corrupted if they
> increased since the last access? In this case you could adjust the
> counter based on some timestamp difference.

Imre, thanks a lot for the idea and reviving this topic. I'd like to
know your opinion on the approach with patches 1,2,3 that I wrote
below:

Unfortunately we cannot use those counters for anything.
But anyways, they are just entry counters and for every enter it would
take vblank number to zero.
so, if we waited 100 vblanks and dc entered 100->0
and if we waited 1 vblank and dc entered 1->0
so seems unpredictable...

Well, I have this tree:
https://cgit.freedesktop.org/~vivijim/drm-intel/log/?h=rpm-domains-psr-vblank-counter-full
with mainly:
1 - vblank domain on pre-enable post-disable vblanks hooks as Ville
had suggested
2 - psr domain so we just enable dc state when screen is really in idle.
3 - restore counter on vblank enable.

From what I understood so far of this problem, only the patch 1 should
be enough, but with only this one I don't get the screen frozen but
the typying is so slow that is visible that we have something
wrong Maybe dc state transition with mutexes there are slow?

Patch 2 by iitself also doesn't solve this and I still have frozen
screens, but when combined to  patch 1 everything works really well...
In the point that I believe we really don't need patch 3.

But I didn't submit any series yet because I'd like to understand more
of what is happening here and probably with a good i-g-t coverage for
this case.

Please let me know your thoughts.

Thanks,
Rodrigo.

>
> --Imre
>
>> Thanks,
>> Rodrigo.
>>
>> -- Forwarded message --
>> From: Rodrigo Vivi 
>> Date: Wed, Feb 17, 2016 at 3:14 PM
>> Subject: Re: [Intel-gfx] [PATCH] drm/i915: Avoid vblank counter for
>> gen9+
>> To: Daniel Vetter , Patrik Jakobsson
>> 
>> Cc: Rodrigo Vivi , intel-gfx
>> 
>>
>>
>> On Tue, Feb 16, 2016 at 7:50 AM, Daniel Vetter 
>> wrote:
>> > On Thu, Feb 11, 2016 at 09:00:47AM -0800, Rodrigo Vivi wrote:
>> > > Framecounter register is read-only so DMC cannot restore it
>> > > after exiting DC5 and DC6.
>> > >
>> > > Easiest way to go is to avoid the counter and use vblank
>> > > interruptions for this platform and for all the following
>> > > ones since DMC came to stay. At least while we can't change
>> > > this register to read-write.
>> > >
>> > > Signed-off-by: Rodrigo Vivi 
>> >
>> > Now my comments also in public:
>> > - Do we still get reasonable dc5 residency with this - it means
>> > we'll keep
>> >   vblank irq running forever.
>> >
>> > - I'm a bit unclear on what exactly this fixes - have you tested
>> > that
>> >   long-lasting vblank waits are still accurate? Just want to make
>> > sure we
>> >   don't just paper over the issue and desktops can still get stuck
>> > waiting
>> >   for a vblank.
>>
>> apparently no... so please just ignore this patch for now... after a
>> while with that patch I was seeing the issue again...
>>
>> >
>> > Just a bit suprised that the only problem is the framecounter, and
>> > not
>> > that vblanks stop happening too.
>> >
>> > We need to also know these details for the proper fix, which will
>> > involve
>> > grabbing power well references (might need a new one for vblank
>> > interrupts) to make sure.
>>
>> Yeap, I liked this idea... so combining a power domain reference with
>> a vblank count restore once we know the dc off is blocked we could
>> workaround this case... something like:
>>
>> diff --git a/drivers/gpu/drm/i915/i915_irq.c
>> b/drivers/gpu/drm/i915/i915_irq.c
>> index 25a8937..2b18778 100644
>> --- a/drivers/gpu/drm/i915/i915_irq.c
>> +++ b/drivers/gpu/drm/i915/i915_irq.c
>> @@ -2743,7 +2743,10 @@ static int gen8_enable_vblank(struct
>> drm_device
>> *dev, unsigned int pipe)
>> struct drm_i915_private *dev_priv = dev->dev_private;
>> unsigned long irqflags;
>>
>> +   intel_display_power_get(dev_priv, POWER_DOMAIN_VBLANK);
>> +
>> spin_lock_irqsave(_priv->irq_lock, irqflags);
>> +   dev->vblank[pipe].last = g4x_get_vblank_counter(dev, pipe);
>> bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
>> spin_unlock_irqrestore(_priv->irq_lock, irqflags);
>>
>> @@ -2796,6 +2799,8 @@ static void gen8_disable_vblank(struct
>> drm_device *dev, unsigned int pipe)
>> spin_lock_irqsave(_priv->irq_lock, irqflags);
>> 

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Execlists small cleanups and micro-optimisations (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Execlists small cleanups and micro-optimisations (rev2)
URL   : https://patchwork.freedesktop.org/series/3853/
State : failure

== Summary ==

Series 3853v2 drm/i915: Execlists small cleanups and micro-optimisations
http://patchwork.freedesktop.org/api/1.0/series/3853/revisions/2/mbox/

Test drv_hangman:
Subgroup error-state-basic:
pass   -> FAIL   (ilk-hp8440p)
Test kms_flip:
Subgroup basic-flip-vs-dpms:
dmesg-warn -> PASS   (ilk-hp8440p) UNSTABLE
Subgroup basic-flip-vs-modeset:
incomplete -> PASS   (ilk-hp8440p) UNSTABLE
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass   -> DMESG-WARN (skl-i7k-2) UNSTABLE
Subgroup suspend-read-crc-pipe-b:
incomplete -> PASS   (hsw-gt2)
Subgroup suspend-read-crc-pipe-c:
dmesg-warn -> PASS   (skl-i7k-2) UNSTABLE

bdw-nuci7total:166  pass:155  dwarn:0   dfail:0   fail:0   skip:11 
bdw-ultratotal:169  pass:155  dwarn:0   dfail:0   fail:0   skip:14 
byt-nuc  total:169  pass:144  dwarn:0   dfail:0   fail:0   skip:25 
hsw-brixbox  total:169  pass:155  dwarn:0   dfail:0   fail:0   skip:14 
hsw-gt2  total:169  pass:158  dwarn:0   dfail:1   fail:0   skip:10 
ilk-hp8440p  total:169  pass:118  dwarn:0   dfail:1   fail:1   skip:49 
ivb-t430stotal:169  pass:154  dwarn:0   dfail:0   fail:1   skip:14 
skl-i7k-2total:169  pass:152  dwarn:1   dfail:0   fail:0   skip:16 
snb-dellxps  total:169  pass:146  dwarn:0   dfail:0   fail:1   skip:22 
snb-x220ttotal:169  pass:146  dwarn:0   dfail:0   fail:2   skip:21 

Results at /archive/results/CI_IGT_test/Patchwork_1487/

e511a05b4b3bb4d1dbca99b00af6d0dc0a65d295 drm-intel-nightly: 
2016y-02m-26d-13h-42m-46s UTC integration manifest
b5bf538d5948d2f82c61c92bd452decab535d880 drm/i915: Execlists small cleanups and 
micro-optimisations

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[Intel-gfx] ✗ Fi.CI.BAT: failure for Capture more useful details in error state (rev3)

[Patchwork]

== Series Details ==

Series: Capture more useful details in error state (rev3)
URL   : https://patchwork.freedesktop.org/series/2906/
State : failure

== Summary ==

Series 2906v3 Capture more useful details in error state
http://patchwork.freedesktop.org/api/1.0/series/2906/revisions/3/mbox/

Test drv_hangman:
Subgroup error-state-basic:
pass   -> INCOMPLETE (snb-dellxps)
pass   -> FAIL   (ilk-hp8440p)
Test kms_flip:
Subgroup basic-flip-vs-dpms:
dmesg-warn -> PASS   (ilk-hp8440p) UNSTABLE
Subgroup basic-flip-vs-modeset:
incomplete -> PASS   (ilk-hp8440p) UNSTABLE
Subgroup basic-flip-vs-wf_vblank:
pass   -> FAIL   (snb-x220t)
Test kms_force_connector_basic:
Subgroup force-load-detect:
fail   -> DMESG-FAIL (snb-x220t)
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
incomplete -> PASS   (hsw-gt2)
pass   -> DMESG-WARN (ivb-t430s)
Subgroup suspend-read-crc-pipe-c:
pass   -> DMESG-WARN (bsw-nuc-2)
Test pm_rpm:
Subgroup basic-pci-d3-state:
pass   -> DMESG-WARN (bsw-nuc-2)

bdw-nuci7total:166  pass:155  dwarn:0   dfail:0   fail:0   skip:11 
bdw-ultratotal:169  pass:155  dwarn:0   dfail:0   fail:0   skip:14 
bsw-nuc-2total:169  pass:136  dwarn:2   dfail:0   fail:1   skip:30 
byt-nuc  total:169  pass:144  dwarn:0   dfail:0   fail:0   skip:25 
hsw-brixbox  total:169  pass:155  dwarn:0   dfail:0   fail:0   skip:14 
hsw-gt2  total:169  pass:158  dwarn:0   dfail:1   fail:0   skip:10 
ilk-hp8440p  total:169  pass:118  dwarn:0   dfail:1   fail:1   skip:49 
ivb-t430stotal:169  pass:153  dwarn:1   dfail:0   fail:1   skip:14 
skl-i7k-2total:169  pass:152  dwarn:1   dfail:0   fail:0   skip:16 
snb-dellxps  total:20   pass:18   dwarn:0   dfail:0   fail:0   skip:1  
snb-x220ttotal:169  pass:145  dwarn:0   dfail:1   fail:2   skip:21 

Results at /archive/results/CI_IGT_test/Patchwork_1486/

e511a05b4b3bb4d1dbca99b00af6d0dc0a65d295 drm-intel-nightly: 
2016y-02m-26d-13h-42m-46s UTC integration manifest
c072adf745e744b6d20d1fdcdc2979235430599e drm/i915/error: Capture WA ctx batch 
in error state
d187fe59fc41065bf02447604c2df9fbcc20a337 drm/i915/error: add GuC state error 
capture & decode
42341a5325b0b2dde27ecd09f4a536ecb1036c2b drm/i915/guc: Improve action error 
reporting
6dfb136e296a5906cde48fe578d7a9f5fc53cf3b drm/i915/error: enhanced error capture 
of requests
57b7c25ac7e9595d29cc4e7be4b5890069d249bb drm/i915/error: capture errored 
context based on request context-id
01bc355da54332af17ea674c606de5924f117189 drm/i915/error: improve CSB reporting
7c5e4382756f0fc89ca8b7209861ac73f2059eef drm/i915/error: report ctx id & desc 
for each request in the queue
64d800fceb8ddc6f1e431ea09c674077db359c9b drm/i915/error: capture ringbuffer 
pointed to by START
8398e7f4626cc0353d2d9d57c5fe2accf734612f drm/i915/error: capture execlist state 
on error

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Re: [Intel-gfx] [PATCH i-g-t] kms_atomic: drop unnecessary connector looping from plane_primary test

[Matt Roper]

On Fri, Feb 26, 2016 at 05:00:21PM +, Daniel Stone wrote:
> Hi,
> 
> On Fri, 2016-02-26 at 08:58 -0800, Matt Roper wrote:
> > Local variable num_connectors is never initialized before being
> > auto-incremented in the loop.  If we wind up with a non-zero garbage
> > value, it will lead us to try to write to an out-of-bounds array
> > index.
> > We should probably initialize it to zero before use.
> > 
> > However on closer inspection, the plane_primary test doesn't actually
> > wind up using the connector list or number of connectors, so just
> > remove
> > the whole block of code; it was probably brought in by accident as
> > part
> > of a copy-paste operation.
> 
> History rather than copy & paste; originally crtc_commit_*() was
> inlined. But the rest of your analysis is totally correct; thanks for
> finding this!
> 
> Reviewed-by: Daniel Stone 

Thanks for the speedy review!  Pushed to fdo.


Matt

-- 
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
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Re: [Intel-gfx] [PATCH v5 24/35] drm/i915: Added trace points to scheduler

[Jesse Barnes]

On 02/26/2016 07:55 AM, John Harrison wrote:
> On 23/02/2016 20:42, Jesse Barnes wrote:
>> On 02/18/2016 06:27 AM, john.c.harri...@intel.com wrote:
>>> From: John Harrison 
>>>
>>> Added trace points to the scheduler to track all the various events,
>>> node state transitions and other interesting things that occur.
>>>
>>> v2: Updated for new request completion tracking implementation.
>>>
>>> v3: Updated for changes to node kill code.
>>>
>>> v4: Wrapped some long lines to keep the style checker happy.
>>>
>>> For: VIZ-1587
>>> Signed-off-by: John Harrison 
>>> ---
>>>   drivers/gpu/drm/i915/i915_gem_execbuffer.c |   2 +
>>>   drivers/gpu/drm/i915/i915_scheduler.c  |  26 
>>>   drivers/gpu/drm/i915/i915_trace.h  | 196 
>>> +
>>>   drivers/gpu/drm/i915/intel_lrc.c   |   2 +
>>>   4 files changed, 226 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c 
>>> b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
>>> index b9ad0fd..d4de8c7 100644
>>> --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
>>> +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
>>> @@ -1272,6 +1272,8 @@ i915_gem_ringbuffer_submission(struct 
>>> i915_execbuffer_params *params,
>>> i915_gem_execbuffer_move_to_active(vmas, params->request);
>>>   +trace_i915_gem_ring_queue(ring, params);
>>> +
>>>   qe = container_of(params, typeof(*qe), params);
>>>   ret = i915_scheduler_queue_execbuffer(qe);
>>>   if (ret)
>>> diff --git a/drivers/gpu/drm/i915/i915_scheduler.c 
>>> b/drivers/gpu/drm/i915/i915_scheduler.c
>>> index 47d7de4..e56ce08 100644
>>> --- a/drivers/gpu/drm/i915/i915_scheduler.c
>>> +++ b/drivers/gpu/drm/i915/i915_scheduler.c
>>> @@ -88,6 +88,8 @@ static void i915_scheduler_node_requeue(struct 
>>> i915_scheduler_queue_entry *node)
>>>   /* Seqno will be reassigned on relaunch */
>>>   node->params.request->seqno = 0;
>>>   node->status = i915_sqs_queued;
>>> +trace_i915_scheduler_unfly(node->params.ring, node);
>>> +trace_i915_scheduler_node_state_change(node->params.ring, node);
>>>   }
>>> /*
>>> @@ -99,7 +101,11 @@ static void i915_scheduler_node_kill(struct 
>>> i915_scheduler_queue_entry *node)
>>>   WARN_ON(!node);
>>>   WARN_ON(I915_SQS_IS_COMPLETE(node));
>>>   +if (I915_SQS_IS_FLYING(node))
>>> +trace_i915_scheduler_unfly(node->params.ring, node);
>>> +
>>>   node->status = i915_sqs_dead;
>>> +trace_i915_scheduler_node_state_change(node->params.ring, node);
>>>   }
>>> /* Mark a node as in flight on the hardware. */
>>> @@ -124,6 +130,9 @@ static int i915_scheduler_node_fly(struct 
>>> i915_scheduler_queue_entry *node)
>>> node->status = i915_sqs_flying;
>>>   +trace_i915_scheduler_fly(ring, node);
>>> +trace_i915_scheduler_node_state_change(ring, node);
>>> +
>>>   if (!(scheduler->flags[ring->id] & i915_sf_interrupts_enabled)) {
>>>   bool success = true;
>>>   @@ -280,6 +289,8 @@ static int 
>>> i915_scheduler_pop_from_queue_locked(struct intel_engine_cs *ring,
>>>   INIT_LIST_HEAD(>link);
>>>   best->status  = i915_sqs_popped;
>>>   +trace_i915_scheduler_node_state_change(ring, best);
>>> +
>>>   ret = 0;
>>>   } else {
>>>   /* Can only get here if:
>>> @@ -297,6 +308,8 @@ static int i915_scheduler_pop_from_queue_locked(struct 
>>> intel_engine_cs *ring,
>>>   }
>>>   }
>>>   +trace_i915_scheduler_pop_from_queue(ring, best);
>>> +
>>>   *pop_node = best;
>>>   return ret;
>>>   }
>>> @@ -506,6 +519,8 @@ static int 
>>> i915_scheduler_queue_execbuffer_bypass(struct i915_scheduler_queue_en
>>>   struct i915_scheduler *scheduler = dev_priv->scheduler;
>>>   int ret;
>>>   +trace_i915_scheduler_queue(qe->params.ring, qe);
>>> +
>>>   intel_ring_reserved_space_cancel(qe->params.request->ringbuf);
>>> scheduler->flags[qe->params.ring->id] |= i915_sf_submitting;
>>> @@ -628,6 +643,9 @@ int i915_scheduler_queue_execbuffer(struct 
>>> i915_scheduler_queue_entry *qe)
>>>   not_flying = i915_scheduler_count_flying(scheduler, ring) <
>>>scheduler->min_flying;
>>>   +trace_i915_scheduler_queue(ring, node);
>>> +trace_i915_scheduler_node_state_change(ring, node);
>>> +
>>>   spin_unlock_irq(>lock);
>>> if (not_flying)
>>> @@ -657,6 +675,8 @@ bool i915_scheduler_notify_request(struct 
>>> drm_i915_gem_request *req)
>>>   struct i915_scheduler_queue_entry *node = req->scheduler_qe;
>>>   unsigned long flags;
>>>   +trace_i915_scheduler_landing(req);
>>> +
>>>   if (!node)
>>>   return false;
>>>   @@ -670,6 +690,8 @@ bool i915_scheduler_notify_request(struct 
>>> drm_i915_gem_request *req)
>>>   else
>>>   node->status = i915_sqs_complete;
>>>   +trace_i915_scheduler_node_state_change(req->ring, node);
>>> +
>>>   

[Intel-gfx] [PATCH 0/5] Pipe level color management V10

[Lionel Landwerlin]

This series introduces pipe level color management through a set of properties
attached to the CRTC. It also provides an implementation for some Intel
platforms.

This series is based of a previous set of patches by Shashank Sharma.

Cheers,

Lionel

v9: Rebase on nightly

v10: Mask GAMMA_MODE register value (Matt Roper)
 Cleanup legacy LUT helper (Emil Velikov)

Lionel Landwerlin (5):
  drm/i915: Extract out gamma table and CSC to their own file
  drm/i915: Do not read GAMMA_MODE register
  drm: introduce pipe color correction properties
  drm/i915: Implement color management on bdw/skl/bxt/kbl
  drm/i915: Implement color management on chv

 Documentation/DocBook/gpu.tmpl   |  65 +++-
 drivers/gpu/drm/drm_atomic.c |  88 +-
 drivers/gpu/drm/drm_atomic_helper.c  | 110 ++-
 drivers/gpu/drm/drm_crtc.c   |  35 +++
 drivers/gpu/drm/drm_crtc_helper.c|  33 +++
 drivers/gpu/drm/i915/Makefile|   1 +
 drivers/gpu/drm/i915/i915_drv.c  |  27 +-
 drivers/gpu/drm/i915/i915_drv.h  |   8 +
 drivers/gpu/drm/i915/i915_reg.h  |  53 
 drivers/gpu/drm/i915/intel_color.c   | 556 +++
 drivers/gpu/drm/i915/intel_display.c | 184 +++-
 drivers/gpu/drm/i915/intel_drv.h |  12 +
 drivers/gpu/drm/i915/intel_fbdev.c   |   8 +
 include/drm/drm_atomic_helper.h  |   3 +
 include/drm/drm_crtc.h   |  46 ++-
 include/drm/drm_crtc_helper.h|   3 +
 include/uapi/drm/drm_mode.h  |  15 +
 17 files changed, 1081 insertions(+), 166 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_color.c

--
2.7.0
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[Intel-gfx] [PATCH 5/5] drm/i915: Implement color management on chv

[Lionel Landwerlin]

Patch based on a previous series by Shashank Sharma.

v2: Update contributors

v3: Refactor degamma/gamma LUTs load into a single function

v4: Remove unused variable

Signed-off-by: Shashank Sharma 
Signed-off-by: Kumar, Kiran S 
Signed-off-by: Kausal Malladi 
Signed-off-by: Lionel Landwerlin 
Reviewed-by: Matt Roper 
---
 drivers/gpu/drm/i915/i915_drv.c|   3 +
 drivers/gpu/drm/i915/i915_reg.h|  31 +
 drivers/gpu/drm/i915/intel_color.c | 133 +++--
 3 files changed, 161 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 3807b73..8a2aaa7 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -68,6 +68,8 @@ static struct drm_driver driver;
 
 #define BDW_COLORS \
.color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
+#define CHV_COLORS \
+   .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
 
 static const struct intel_device_info intel_i830_info = {
.gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
@@ -325,6 +327,7 @@ static const struct intel_device_info intel_cherryview_info 
= {
.display_mmio_offset = VLV_DISPLAY_BASE,
GEN_CHV_PIPEOFFSETS,
CURSOR_OFFSETS,
+   CHV_COLORS,
 };
 
 static const struct intel_device_info intel_skylake_info = {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 76a9e49..ea599a9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7673,6 +7673,37 @@ enum skl_disp_power_wells {
 #define PREC_PAL_GC_MAX(pipe, i)   _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, 
_PAL_PREC_GC_MAX_B) + (i) * 4)
 #define PREC_PAL_EXT_GC_MAX(pipe, i)   _MMIO(_PIPE(pipe, 
_PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4)
 
+/* pipe CSC & degamma/gamma LUTs on CHV */
+#define _CGM_PIPE_A_CSC_COEFF01(VLV_DISPLAY_BASE + 0x67900)
+#define _CGM_PIPE_A_CSC_COEFF23(VLV_DISPLAY_BASE + 0x67904)
+#define _CGM_PIPE_A_CSC_COEFF45(VLV_DISPLAY_BASE + 0x67908)
+#define _CGM_PIPE_A_CSC_COEFF67(VLV_DISPLAY_BASE + 0x6790C)
+#define _CGM_PIPE_A_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x67910)
+#define _CGM_PIPE_A_DEGAMMA(VLV_DISPLAY_BASE + 0x66000)
+#define _CGM_PIPE_A_GAMMA  (VLV_DISPLAY_BASE + 0x67000)
+#define _CGM_PIPE_A_MODE   (VLV_DISPLAY_BASE + 0x67A00)
+#define   CGM_PIPE_MODE_GAMMA  (1 << 2)
+#define   CGM_PIPE_MODE_CSC(1 << 1)
+#define   CGM_PIPE_MODE_DEGAMMA(1 << 0)
+
+#define _CGM_PIPE_B_CSC_COEFF01(VLV_DISPLAY_BASE + 0x69900)
+#define _CGM_PIPE_B_CSC_COEFF23(VLV_DISPLAY_BASE + 0x69904)
+#define _CGM_PIPE_B_CSC_COEFF45(VLV_DISPLAY_BASE + 0x69908)
+#define _CGM_PIPE_B_CSC_COEFF67(VLV_DISPLAY_BASE + 0x6990C)
+#define _CGM_PIPE_B_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x69910)
+#define _CGM_PIPE_B_DEGAMMA(VLV_DISPLAY_BASE + 0x68000)
+#define _CGM_PIPE_B_GAMMA  (VLV_DISPLAY_BASE + 0x69000)
+#define _CGM_PIPE_B_MODE   (VLV_DISPLAY_BASE + 0x69A00)
+
+#define CGM_PIPE_CSC_COEFF01(pipe) _MMIO_PIPE(pipe, 
_CGM_PIPE_A_CSC_COEFF01, _CGM_PIPE_B_CSC_COEFF01)
+#define CGM_PIPE_CSC_COEFF23(pipe) _MMIO_PIPE(pipe, 
_CGM_PIPE_A_CSC_COEFF23, _CGM_PIPE_B_CSC_COEFF23)
+#define CGM_PIPE_CSC_COEFF45(pipe) _MMIO_PIPE(pipe, 
_CGM_PIPE_A_CSC_COEFF45, _CGM_PIPE_B_CSC_COEFF45)
+#define CGM_PIPE_CSC_COEFF67(pipe) _MMIO_PIPE(pipe, 
_CGM_PIPE_A_CSC_COEFF67, _CGM_PIPE_B_CSC_COEFF67)
+#define CGM_PIPE_CSC_COEFF8(pipe)  _MMIO_PIPE(pipe, 
_CGM_PIPE_A_CSC_COEFF8, _CGM_PIPE_B_CSC_COEFF8)
+#define CGM_PIPE_DEGAMMA(pipe, i, w)   _MMIO(_PIPE(pipe, _CGM_PIPE_A_DEGAMMA, 
_CGM_PIPE_B_DEGAMMA) + (i) * 8 + (w) * 4)
+#define CGM_PIPE_GAMMA(pipe, i, w) _MMIO(_PIPE(pipe, _CGM_PIPE_A_GAMMA, 
_CGM_PIPE_B_GAMMA) + (i) * 8 + (w) * 4)
+#define CGM_PIPE_MODE(pipe)_MMIO_PIPE(pipe, _CGM_PIPE_A_MODE, 
_CGM_PIPE_B_MODE)
+
 /* MIPI DSI registers */
 
 #define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c)   /* ports A and C only */
diff --git a/drivers/gpu/drm/i915/intel_color.c 
b/drivers/gpu/drm/i915/intel_color.c
index c6340d8..aa0b20d 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -29,6 +29,7 @@
 #define CTM_COEFF_1_0  (1ULL << 32)
 #define CTM_COEFF_2_0  (CTM_COEFF_1_0 << 1)
 #define CTM_COEFF_4_0  (CTM_COEFF_2_0 << 1)
+#define CTM_COEFF_8_0  (CTM_COEFF_4_0 << 1)
 #define CTM_COEFF_0_5  (CTM_COEFF_1_0 >> 1)
 #define CTM_COEFF_0_25 (CTM_COEFF_0_5 >> 1)
 #define CTM_COEFF_0_125(CTM_COEFF_0_25 >> 1)
@@ -199,6 +200,58 @@ static void i9xx_load_csc_matrix(struct drm_crtc *crtc)
}
 }
 
+/*
+ * Set up the pipe CSC unit on CherryView.
+ */
+static void cherryview_load_csc_matrix(struct drm_crtc *crtc)
+{
+   struct drm_device *dev = crtc->dev;
+   struct 

[Intel-gfx] [PATCH 4/5] drm/i915: Implement color management on bdw/skl/bxt/kbl

[Lionel Landwerlin]

Patch based on a previous series by Shashank Sharma.

v2: Do not read GAMMA_MODE register to figure what mode we're in

v3: Program PREC_PAL_GC_MAX to clamp pixel values > 1.0

Add documentation on how the Broadcast RGB property is affected by CTM

v4: Update contributors

v5: Refactor degamma/gamma LUTs load into a single function

v6: Fix missing intel_crtc variable (bisect issue)

v7: Fix & simplify limited range matrix multiplication (Matt Roper's
comment)

Signed-off-by: Shashank Sharma 
Signed-off-by: Kumar, Kiran S 
Signed-off-by: Kausal Malladi 
Signed-off-by: Lionel Landwerlin 
Acknowledged-by: Matt Roper 
---
 Documentation/DocBook/gpu.tmpl   |   6 +-
 drivers/gpu/drm/i915/i915_drv.c  |  24 ++-
 drivers/gpu/drm/i915/i915_drv.h  |   6 +
 drivers/gpu/drm/i915/i915_reg.h  |  22 +++
 drivers/gpu/drm/i915/intel_color.c   | 345 +--
 drivers/gpu/drm/i915/intel_display.c |  22 ++-
 drivers/gpu/drm/i915/intel_drv.h |   3 +-
 drivers/gpu/drm/i915/intel_fbdev.c   |   8 +
 8 files changed, 371 insertions(+), 65 deletions(-)

diff --git a/Documentation/DocBook/gpu.tmpl b/Documentation/DocBook/gpu.tmpl
index 1692c4d..430e99b 100644
--- a/Documentation/DocBook/gpu.tmpl
+++ b/Documentation/DocBook/gpu.tmpl
@@ -2153,7 +2153,11 @@ void intel_crt_init(struct drm_device *dev)
ENUM
{ "Automatic", "Full", "Limited 16:235" }
Connector
-   TBD
+   When this property is set to Limited 16:235
+   and CTM is set, the hardware will be programmed with the
+   result of the multiplication of CTM by the limited range
+   matrix to ensure the pixels normaly in the range 0..1.0 are
+   remapped to the range 16/255..235/255.


“audio”
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 20e8200..3807b73 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -66,6 +66,9 @@ static struct drm_driver driver;
 #define IVB_CURSOR_OFFSETS \
.cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, 
IVB_CURSOR_C_OFFSET }
 
+#define BDW_COLORS \
+   .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
+
 static const struct intel_device_info intel_i830_info = {
.gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
.has_overlay = 1, .overlay_needs_physical = 1,
@@ -288,24 +291,28 @@ static const struct intel_device_info 
intel_haswell_m_info = {
.is_mobile = 1,
 };
 
+#define BDW_FEATURES \
+   HSW_FEATURES, \
+   BDW_COLORS
+
 static const struct intel_device_info intel_broadwell_d_info = {
-   HSW_FEATURES,
+   BDW_FEATURES,
.gen = 8,
 };
 
 static const struct intel_device_info intel_broadwell_m_info = {
-   HSW_FEATURES,
+   BDW_FEATURES,
.gen = 8, .is_mobile = 1,
 };
 
 static const struct intel_device_info intel_broadwell_gt3d_info = {
-   HSW_FEATURES,
+   BDW_FEATURES,
.gen = 8,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
 
 static const struct intel_device_info intel_broadwell_gt3m_info = {
-   HSW_FEATURES,
+   BDW_FEATURES,
.gen = 8, .is_mobile = 1,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
@@ -321,13 +328,13 @@ static const struct intel_device_info 
intel_cherryview_info = {
 };
 
 static const struct intel_device_info intel_skylake_info = {
-   HSW_FEATURES,
+   BDW_FEATURES,
.is_skylake = 1,
.gen = 9,
 };
 
 static const struct intel_device_info intel_skylake_gt3_info = {
-   HSW_FEATURES,
+   BDW_FEATURES,
.is_skylake = 1,
.gen = 9,
.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
@@ -345,17 +352,18 @@ static const struct intel_device_info intel_broxton_info 
= {
.has_fbc = 1,
GEN_DEFAULT_PIPEOFFSETS,
IVB_CURSOR_OFFSETS,
+   BDW_COLORS,
 };
 
 static const struct intel_device_info intel_kabylake_info = {
-   HSW_FEATURES,
+   BDW_FEATURES,
.is_preliminary = 1,
.is_kabylake = 1,
.gen = 9,
 };
 
 static const struct intel_device_info intel_kabylake_gt3_info = {
-   HSW_FEATURES,
+   BDW_FEATURES,
.is_preliminary = 1,
.is_kabylake = 1,
.gen = 9,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d46d5e7..5d11d74 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -663,6 +663,7 @@ struct drm_i915_display_funcs {
/* display clock increase/decrease */
/* pll clock increase/decrease */
 
+   void (*load_csc_matrix)(struct drm_crtc *crtc);
void (*load_luts)(struct drm_crtc *crtc);
 };
 
@@ -812,6 

[Intel-gfx] [PATCH 2/5] drm/i915: Do not read GAMMA_MODE register

[Lionel Landwerlin]

Implement Daniel Stone's recommendation to not read registers to infer
the hardware's state.

v2: Read GAMMA_MODE register value at init (Matt Roper's comment)

v3: Read GAMMA_MODE register in intel_modeset_readout_hw_state along
with other registers (Matt Roper's comment).

v4: Mask GAMMA_MODE register with interesting bits when reading

Signed-off-by: Lionel Landwerlin 
Reviewed-by: Matt Roper 
---
 drivers/gpu/drm/i915/intel_color.c   | 7 +--
 drivers/gpu/drm/i915/intel_display.c | 3 +++
 drivers/gpu/drm/i915/intel_drv.h | 3 +++
 3 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_color.c 
b/drivers/gpu/drm/i915/intel_color.c
index 35b7f62..16657eb 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -121,6 +121,8 @@ static void haswell_load_luts(struct drm_crtc *crtc)
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+   struct intel_crtc_state *intel_crtc_state =
+   to_intel_crtc_state(crtc->state);
bool reenable_ips = false;
 
/*
@@ -128,11 +130,12 @@ static void haswell_load_luts(struct drm_crtc *crtc)
 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
 */
if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
-   ((I915_READ(GAMMA_MODE(intel_crtc->pipe)) & GAMMA_MODE_MODE_MASK) ==
-GAMMA_MODE_MODE_SPLIT)) {
+   (intel_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)) {
hsw_disable_ips(intel_crtc);
reenable_ips = true;
}
+
+   intel_crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
 
i9xx_load_luts(crtc);
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 66d6820..a5f57cd 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9870,6 +9870,9 @@ static bool haswell_get_pipe_config(struct intel_crtc 
*crtc,
 
intel_get_pipe_timings(crtc, pipe_config);
 
+   pipe_config->gamma_mode =
+   I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
+
if (INTEL_INFO(dev)->gen >= 9) {
skl_init_scalers(dev, crtc, pipe_config);
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index dc29816..d2855c7 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -518,6 +518,9 @@ struct intel_crtc_state {
struct skl_pipe_wm skl;
} optimal;
} wm;
+
+   /* Gamma mode programmed on the pipe */
+   uint32_t gamma_mode;
 };
 
 struct vlv_wm_state {
-- 
2.7.0

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[Intel-gfx] [PATCH 1/5] drm/i915: Extract out gamma table and CSC to their own file

[Lionel Landwerlin]

The moves a couple of functions programming the gamma LUT and CSC
units into their own file.

On generations prior to Haswell there is only a gamma LUT. From
haswell on there is also a new enhanced color correction unit that
isn't used yet. This is why we need to set the GAMMA_MODE register,
either we're using the legacy 8bits LUT or enhanced LUTs (of 10 or
12bits).

The CSC unit is only available from Haswell on.

We also need to make a special case for CherryView which is recognized
as a gen 8 but doesn't have the same enhanced color correction unit
from Haswell on.

v2: Fix access to GAMMA_MODE register on older generations than
Haswell (from Matt Roper's comments)

Signed-off-by: Lionel Landwerlin 
Reviewed-by: Matt Roper 
---
 drivers/gpu/drm/i915/Makefile|   1 +
 drivers/gpu/drm/i915/i915_drv.h  |   2 +
 drivers/gpu/drm/i915/intel_color.c   | 191 +++
 drivers/gpu/drm/i915/intel_display.c | 163 +++---
 drivers/gpu/drm/i915/intel_drv.h |  10 ++
 5 files changed, 216 insertions(+), 151 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_color.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 0851de07..0516300 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -55,6 +55,7 @@ i915-y += intel_audio.o \
  intel_atomic.o \
  intel_atomic_plane.o \
  intel_bios.o \
+ intel_color.o \
  intel_display.o \
  intel_fbc.o \
  intel_fifo_underrun.o \
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a4dcb74..d46d5e7 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -662,6 +662,8 @@ struct drm_i915_display_funcs {
/* render clock increase/decrease */
/* display clock increase/decrease */
/* pll clock increase/decrease */
+
+   void (*load_luts)(struct drm_crtc *crtc);
 };
 
 enum forcewake_domain_id {
diff --git a/drivers/gpu/drm/i915/intel_color.c 
b/drivers/gpu/drm/i915/intel_color.c
new file mode 100644
index 000..35b7f62
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -0,0 +1,191 @@
+/*
+ * Copyright © 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "intel_drv.h"
+
+/*
+ * Set up the pipe CSC unit.
+ *
+ * Currently only full range RGB to limited range RGB conversion
+ * is supported, but eventually this should handle various
+ * RGB<->YCbCr scenarios as well.
+ */
+static void i9xx_load_csc_matrix(struct drm_crtc *crtc)
+{
+   struct drm_device *dev = crtc->dev;
+   struct drm_i915_private *dev_priv = dev->dev_private;
+   struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+   int pipe = intel_crtc->pipe;
+   uint16_t coeff = 0x7800; /* 1.0 */
+
+   /*
+* TODO: Check what kind of values actually come out of the pipe
+* with these coeff/postoff values and adjust to get the best
+* accuracy. Perhaps we even need to take the bpc value into
+* consideration.
+*/
+
+   if (intel_crtc->config->limited_color_range)
+   coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
+
+   I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
+   I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
+
+   I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
+   I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
+
+   I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
+   I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
+
+   I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
+   I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
+   I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
+
+   if (INTEL_INFO(dev)->gen > 6) {
+   uint16_t postoff = 0;
+
+   if 

[Intel-gfx] [PATCH 3/5] drm: introduce pipe color correction properties

[Lionel Landwerlin]

Patch based on a previous series by Shashank Sharma.

This introduces optional properties to enable color correction at the
pipe level. It relies on 3 transformations applied to every pixels
displayed. First a lookup into a degamma table, then a multiplication
of the rgb components by a 3x3 matrix and finally another lookup into
a gamma table.

The following properties can be added to a pipe :
  - DEGAMMA_LUT : blob containing degamma LUT
  - DEGAMMA_LUT_SIZE : number of elements in DEGAMMA_LUT
  - CTM : transformation matrix applied after the degamma LUT
  - GAMMA_LUT : blob containing gamma LUT
  - GAMMA_LUT_SIZE : number of elements in GAMMA_LUT

DEGAMMA_LUT_SIZE and GAMMA_LUT_SIZE are read only properties, set by
the driver to tell userspace applications what sizes should be the
lookup tables in DEGAMMA_LUT and GAMMA_LUT.

A helper is also provided so legacy gamma correction is redirected
through these new properties.

v2: Register LUT size properties as range

v3: Fix round in drm_color_lut_get_value() helper
More docs on how degamma/gamma properties are used

v4: Update contributors

v5: Rename CTM_MATRIX property to CTM (Doh!)
Add legacy gamma_set atomic helper
Describe CTM/LUT acronyms in the kernel doc

v6: Fix missing blob unref in drm_atomic_helper_crtc_reset

Signed-off-by: Shashank Sharma 
Signed-off-by: Kumar, Kiran S 
Signed-off-by: Kausal Malladi 
Signed-off-by: Lionel Landwerlin 
Reviewed-by: Matt Roper 
---
 Documentation/DocBook/gpu.tmpl  |  59 ++-
 drivers/gpu/drm/drm_atomic.c|  88 -
 drivers/gpu/drm/drm_atomic_helper.c | 110 +++-
 drivers/gpu/drm/drm_crtc.c  |  35 
 drivers/gpu/drm/drm_crtc_helper.c   |  33 +++
 include/drm/drm_atomic_helper.h |   3 +
 include/drm/drm_crtc.h  |  46 ++-
 include/drm/drm_crtc_helper.h   |   3 +
 include/uapi/drm/drm_mode.h |  15 +
 9 files changed, 386 insertions(+), 6 deletions(-)

diff --git a/Documentation/DocBook/gpu.tmpl b/Documentation/DocBook/gpu.tmpl
index fe6b36a..1692c4d 100644
--- a/Documentation/DocBook/gpu.tmpl
+++ b/Documentation/DocBook/gpu.tmpl
@@ -1816,7 +1816,7 @@ void intel_crt_init(struct drm_device *dev)
Description/Restrictions


-   DRM
+   DRM
Generic
“rotation”
BITMASK
@@ -2068,7 +2068,7 @@ void intel_crt_init(struct drm_device *dev)
property to suggest an Y offset for a connector


-   Optional
+   Optional
“scaling mode”
ENUM
{ "None", "Full", "Center", "Full aspect" }
@@ -2092,6 +2092,61 @@ void intel_crt_init(struct drm_device *dev)
TBD


+   “DEGAMMA_LUT”
+   BLOB
+   0
+   CRTC
+   DRM property to set the degamma lookup table
+   (LUT) mapping pixel data from the framebuffer before it is
+   given to the transformation matrix. The data is an interpreted
+   as an array of struct drm_color_lut elements. Hardware might
+   choose not to use the full precision of the LUT elements nor
+   use all the elements of the LUT (for example the hardware
+   might choose to interpolate between LUT[0] and LUT[4]). 
+   
+   
+   “DEGAMMA_LUT_SIZE”
+   RANGE | IMMUTABLE
+   Min=0, Max=UINT_MAX
+   CRTC
+   DRM property to gives the size of the lookup
+   table to be set on the DEGAMMA_LUT property (the size depends
+   on the underlying hardware).
+   
+   
+   “CTM”
+   BLOB
+   0
+   CRTC
+   DRM property to set the current
+   transformation matrix (CTM) apply to pixel data after the
+   lookup through the degamma LUT and before the lookup through
+   the gamma LUT. The data is an interpreted as a struct
+   drm_color_ctm.
+   
+   
+   “GAMMA_LUT”
+   BLOB
+   0
+   CRTC
+   DRM property to set the gamma lookup table
+   (LUT) mapping pixel data after to the transformation matrix to
+   data sent to the connector. The data is an interpreted as an
+   array of struct drm_color_lut elements. Hardware might choose
+   not to use the full precision of the LUT elements nor use all
+   the elements of the LUT (for example the hardware might choose
+   to interpolate between LUT[0] and LUT[4]).
+   
+   
+   “GAMMA_LUT_SIZE”
+   RANGE | IMMUTABLE
+   Min=0, Max=UINT_MAX
+   CRTC
+   DRM property to gives the size of the lookup
+   table to be set on the GAMMA_LUT property (the size depends on
+   the underlying hardware).
+   
+   
  

Re: [Intel-gfx] [PATCH i-g-t] kms_atomic: drop unnecessary connector looping from plane_primary test

[Daniel Stone]

Hi,

On Fri, 2016-02-26 at 08:58 -0800, Matt Roper wrote:
> Local variable num_connectors is never initialized before being
> auto-incremented in the loop.  If we wind up with a non-zero garbage
> value, it will lead us to try to write to an out-of-bounds array
> index.
> We should probably initialize it to zero before use.
> 
> However on closer inspection, the plane_primary test doesn't actually
> wind up using the connector list or number of connectors, so just
> remove
> the whole block of code; it was probably brought in by accident as
> part
> of a copy-paste operation.

History rather than copy & paste; originally crtc_commit_*() was
inlined. But the rest of your analysis is totally correct; thanks for
finding this!

Reviewed-by: Daniel Stone 

Cheers,
Daniel
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[Intel-gfx] [PATCH v4] drm/i915: Execlists small cleanups and micro-optimisations

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Assorted changes in the areas of code cleanup, reduction of
invariant conditional in the interrupt handler and lock
contention and MMIO access optimisation.

 * Remove needless initialization.
 * Improve cache locality by reorganizing code and/or using
   branch hints to keep unexpected or error conditions out
   of line.
 * Favor busy submit path vs. empty queue.
 * Less branching in hot-paths.

v2:

 * Avoid mmio reads when possible. (Chris Wilson)
 * Use natural integer size for csb indices.
 * Remove useless return value from execlists_update_context.
 * Extract 32-bit ppgtt PDPs update so it is out of line and
   shared with two callers.
 * Grab forcewake across all mmio operations to ease the
   load on uncore lock and use chepear mmio ops.

v3:

 * Removed some more pointless u8 data types.
 * Removed unused return from execlists_context_queue.
 * Commit message updates.

v4:
 * Unclumsify the unqueue if statement. (Chris Wilson)
 * Hide forcewake from the queuing function. (Chris Wilson)

Version 3 now makes the irq handling code path ~20% smaller on
48-bit PPGTT hardware, and a little bit less elsewhere. Hot
paths are mostly in-line now and hammering on the uncore
spinlock is greatly reduced together with mmio traffic to an
extent.

Benchmarking with "gem_latency -n 100" (keep submitting
batches with 100 nop instruction) shows approximately 4% higher
throughput, 2% less CPU time and 22% smaller latencies. This was
on a big-core while small-cores could benefit even more.

Most likely reason for the improvements are the MMIO
optimization and uncore lock traffic reduction.

Signed-off-by: Tvrtko Ursulin 
Cc: Chris Wilson 
---
 drivers/gpu/drm/i915/intel_lrc.c| 214 +---
 drivers/gpu/drm/i915/intel_ringbuffer.h |   3 +-
 2 files changed, 114 insertions(+), 103 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index f0a57afc8dff..247daf80664b 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -269,6 +269,9 @@ logical_ring_init_platform_invariants(struct 
intel_engine_cs *ring)
 {
struct drm_device *dev = ring->dev;
 
+   if (IS_GEN8(dev) || IS_GEN9(dev))
+   ring->idle_lite_restore_wa = ~0;
+
ring->disable_lite_restore_wa = (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
IS_BXT_REVID(dev, 0, BXT_REVID_A1)) &&
(ring->id == VCS || ring->id == VCS2);
@@ -372,8 +375,6 @@ static void execlists_elsp_write(struct 
drm_i915_gem_request *rq0,
rq0->elsp_submitted++;
 
/* You must always write both descriptors in the order below. */
-   spin_lock(_priv->uncore.lock);
-   intel_uncore_forcewake_get__locked(dev_priv, FORCEWAKE_ALL);
I915_WRITE_FW(RING_ELSP(ring), upper_32_bits(desc[1]));
I915_WRITE_FW(RING_ELSP(ring), lower_32_bits(desc[1]));
 
@@ -383,11 +384,18 @@ static void execlists_elsp_write(struct 
drm_i915_gem_request *rq0,
 
/* ELSP is a wo register, use another nearby reg for posting */
POSTING_READ_FW(RING_EXECLIST_STATUS_LO(ring));
-   intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL);
-   spin_unlock(_priv->uncore.lock);
 }
 
-static int execlists_update_context(struct drm_i915_gem_request *rq)
+static void
+execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state)
+{
+   ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
+   ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
+   ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
+   ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
+}
+
+static void execlists_update_context(struct drm_i915_gem_request *rq)
 {
struct intel_engine_cs *ring = rq->ring;
struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt;
@@ -395,19 +403,13 @@ static int execlists_update_context(struct 
drm_i915_gem_request *rq)
 
reg_state[CTX_RING_TAIL+1] = rq->tail;
 
-   if (ppgtt && !USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
-   /* True 32b PPGTT with dynamic page allocation: update PDP
-* registers and point the unallocated PDPs to scratch page.
-* PML4 is allocated during ppgtt init, so this is not needed
-* in 48-bit mode.
-*/
-   ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
-   ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
-   ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
-   ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
-   }
-
-   return 0;
+   /* True 32b PPGTT with dynamic page allocation: update PDP
+* registers and point the unallocated PDPs to scratch page.
+* PML4 is allocated during ppgtt init, so this is not needed
+* in 48-bit mode.
+*/
+   if (ppgtt && !USES_FULL_48BIT_PPGTT(ppgtt->base.dev))
+   execlists_update_context_pdps(ppgtt, 

Re: [Intel-gfx] [PATCH] drm/i915/bxt: Additional MIPI clock divider form B0 stepping onwards

[Ramalingam C]

On Thursday 18 February 2016 02:00 AM, Jani Nikula wrote:

On Mon, 15 Feb 2016, Deepak M  wrote:

The MIPI clock calculations for the addtional clock
are revised from B0 stepping onwards, the bit definitions
have changed compared to old stepping.

v2: Fixing compilation warning.
v3: Retained the old Macros (Jani)

Signed-off-by: Deepak M 

Reviewed-by: Jani Nikula 

Tested-by: Ramalingam C 

Tested it on BXT-T with Tianma panel.




---
  drivers/gpu/drm/i915/i915_reg.h  | 96 +++-
  drivers/gpu/drm/i915/intel_dsi_pll.c | 56 ++---
  2 files changed, 89 insertions(+), 63 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 144586e..4e61b06 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7663,58 +7663,62 @@ enum skl_disp_power_wells {
  #define  BXT_MIPI_DIV_SHIFT(port) \
_MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \
BXT_MIPI2_DIV_SHIFT)
-/* Var clock divider to generate TX source. Result must be < 39.5 M */
-#define  BXT_MIPI1_ESCLK_VAR_DIV_MASK  (0x3F << 26)
-#define  BXT_MIPI2_ESCLK_VAR_DIV_MASK  (0x3F << 10)
-#define  BXT_MIPI_ESCLK_VAR_DIV_MASK(port) \
-   _MIPI_PORT(port, BXT_MIPI1_ESCLK_VAR_DIV_MASK, \
-   BXT_MIPI2_ESCLK_VAR_DIV_MASK)
-
-#define  BXT_MIPI_ESCLK_VAR_DIV(port, val) \
-   (val << BXT_MIPI_DIV_SHIFT(port))
+
  /* TX control divider to select actual TX clock output from (8x/var) */
-#define  BXT_MIPI1_TX_ESCLK_SHIFT  21
-#define  BXT_MIPI2_TX_ESCLK_SHIFT  5
+#define  BXT_MIPI1_TX_ESCLK_SHIFT  26
+#define  BXT_MIPI2_TX_ESCLK_SHIFT  10
  #define  BXT_MIPI_TX_ESCLK_SHIFT(port)\
_MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \
BXT_MIPI2_TX_ESCLK_SHIFT)
-#define  BXT_MIPI1_TX_ESCLK_FIXDIV_MASK(3 << 21)
-#define  BXT_MIPI2_TX_ESCLK_FIXDIV_MASK(3 << 5)
+#define  BXT_MIPI1_TX_ESCLK_FIXDIV_MASK(0x3F << 26)
+#define  BXT_MIPI2_TX_ESCLK_FIXDIV_MASK(0x3F << 10)
  #define  BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port)  \
_MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \
-   BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
-#define  BXT_MIPI_TX_ESCLK_8XDIV_BY2(port) \
-   (0x0 << BXT_MIPI_TX_ESCLK_SHIFT(port))
-#define  BXT_MIPI_TX_ESCLK_8XDIV_BY4(port) \
-   (0x1 << BXT_MIPI_TX_ESCLK_SHIFT(port))
-#define  BXT_MIPI_TX_ESCLK_8XDIV_BY8(port) \
-   (0x2 << BXT_MIPI_TX_ESCLK_SHIFT(port))
-/* RX control divider to select actual RX clock output from 8x*/
-#define  BXT_MIPI1_RX_ESCLK_SHIFT  19
-#define  BXT_MIPI2_RX_ESCLK_SHIFT  3
-#define  BXT_MIPI_RX_ESCLK_SHIFT(port) \
-   _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_SHIFT, \
-   BXT_MIPI2_RX_ESCLK_SHIFT)
-#define  BXT_MIPI1_RX_ESCLK_FIXDIV_MASK(3 << 19)
-#define  BXT_MIPI2_RX_ESCLK_FIXDIV_MASK(3 << 3)
-#define  BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port)   \
-   (3 << BXT_MIPI_RX_ESCLK_SHIFT(port))
-#define  BXT_MIPI_RX_ESCLK_8X_BY2(port)\
-   (1 << BXT_MIPI_RX_ESCLK_SHIFT(port))
-#define  BXT_MIPI_RX_ESCLK_8X_BY3(port)\
-   (2 << BXT_MIPI_RX_ESCLK_SHIFT(port))
-#define  BXT_MIPI_RX_ESCLK_8X_BY4(port)\
-   (3 << BXT_MIPI_RX_ESCLK_SHIFT(port))
-/* BXT-A WA: Always prog DPHY dividers to 00 */
-#define  BXT_MIPI1_DPHY_DIV_SHIFT  16
-#define  BXT_MIPI2_DPHY_DIV_SHIFT  0
-#define  BXT_MIPI_DPHY_DIV_SHIFT(port) \
-   _MIPI_PORT(port, BXT_MIPI1_DPHY_DIV_SHIFT, \
-   BXT_MIPI2_DPHY_DIV_SHIFT)
-#define  BXT_MIPI_1_DPHY_DIVIDER_MASK  (3 << 16)
-#define  BXT_MIPI_2_DPHY_DIVIDER_MASK  (3 << 0)
-#define  BXT_MIPI_DPHY_DIVIDER_MASK(port)  \
-   (3 << BXT_MIPI_DPHY_DIV_SHIFT(port))
+   BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
+#define  BXT_MIPI_TX_ESCLK_DIVIDER(port, val)  \
+   ((val & 0x3F) << BXT_MIPI_TX_ESCLK_SHIFT(port))
+/* RX upper control divider to select actual RX clock output from 8x*/
+#define  BXT_MIPI1_RX_ESCLK_UPPER_SHIFT21
+#define  BXT_MIPI2_RX_ESCLK_UPPER_SHIFT5
+#define  BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port)   \
+   _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_UPPER_SHIFT, \
+   BXT_MIPI2_RX_ESCLK_UPPER_SHIFT)
+#define  BXT_MIPI1_RX_ESCLK_UPPER_FIXDIV_MASK  (3 << 

[Intel-gfx] [PATCH i-g-t] kms_atomic: drop unnecessary connector looping from plane_primary test

[Matt Roper]

Local variable num_connectors is never initialized before being
auto-incremented in the loop.  If we wind up with a non-zero garbage
value, it will lead us to try to write to an out-of-bounds array index.
We should probably initialize it to zero before use.

However on closer inspection, the plane_primary test doesn't actually
wind up using the connector list or number of connectors, so just remove
the whole block of code; it was probably brought in by accident as part
of a copy-paste operation.

Cc: Daniel Stone 
Signed-off-by: Matt Roper 
---
 tests/kms_atomic.c | 12 
 1 file changed, 12 deletions(-)

diff --git a/tests/kms_atomic.c b/tests/kms_atomic.c
index c8b8b78..2f3080a 100644
--- a/tests/kms_atomic.c
+++ b/tests/kms_atomic.c
@@ -909,19 +909,7 @@ static void plane_primary(struct kms_atomic_crtc_state 
*crtc,
struct kms_atomic_plane_state plane = *plane_old;
uint32_t format = plane_get_igt_format();
drmModeAtomicReq *req = drmModeAtomicAlloc();
-   uint32_t *connectors;
-   int num_connectors;
struct igt_fb fb;
-   int i;
-
-   connectors = calloc(crtc->state->num_connectors, sizeof(*connectors));
-   igt_assert(connectors);
-
-   for (i = 0; i < crtc->state->num_connectors; i++) {
-   if (crtc->state->connectors[i].crtc_id == crtc->obj)
-   connectors[num_connectors++] =
-   crtc->state->connectors[i].obj;
-   }
 
igt_require(format != 0);
 
-- 
2.1.4

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[Intel-gfx] ✗ Fi.CI.BAT: warning for Capture more useful details in error state (rev3)

[Patchwork]

== Series Details ==

Series: Capture more useful details in error state (rev3)
URL   : https://patchwork.freedesktop.org/series/2906/
State : warning

== Summary ==

Series 2906v3 Capture more useful details in error state
http://patchwork.freedesktop.org/api/1.0/series/2906/revisions/3/mbox/

Test kms_flip:
Subgroup basic-flip-vs-dpms:
dmesg-warn -> PASS   (ilk-hp8440p) UNSTABLE
Subgroup basic-flip-vs-modeset:
incomplete -> PASS   (ilk-hp8440p) UNSTABLE
Test kms_force_connector_basic:
Subgroup force-load-detect:
fail   -> DMESG-FAIL (snb-x220t)
dmesg-fail -> FAIL   (ilk-hp8440p)
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass   -> DMESG-WARN (skl-i7k-2) UNSTABLE
pass   -> DMESG-WARN (ivb-t430s)
Subgroup suspend-read-crc-pipe-b:
incomplete -> PASS   (hsw-gt2)
Subgroup suspend-read-crc-pipe-c:
dmesg-warn -> PASS   (skl-i7k-2) UNSTABLE

bdw-nuci7total:166  pass:155  dwarn:0   dfail:0   fail:0   skip:11 
bdw-ultratotal:169  pass:155  dwarn:0   dfail:0   fail:0   skip:14 
byt-nuc  total:169  pass:144  dwarn:0   dfail:0   fail:0   skip:25 
hsw-brixbox  total:169  pass:155  dwarn:0   dfail:0   fail:0   skip:14 
hsw-gt2  total:169  pass:158  dwarn:0   dfail:1   fail:0   skip:10 
ilk-hp8440p  total:169  pass:119  dwarn:0   dfail:0   fail:1   skip:49 
ivb-t430stotal:169  pass:153  dwarn:1   dfail:0   fail:1   skip:14 
skl-i7k-2total:169  pass:152  dwarn:1   dfail:0   fail:0   skip:16 
snb-dellxps  total:169  pass:146  dwarn:0   dfail:0   fail:1   skip:22 
snb-x220ttotal:169  pass:146  dwarn:0   dfail:1   fail:1   skip:21 

Results at /archive/results/CI_IGT_test/Patchwork_1485/

e511a05b4b3bb4d1dbca99b00af6d0dc0a65d295 drm-intel-nightly: 
2016y-02m-26d-13h-42m-46s UTC integration manifest
c5b5716e7321f44ce2c0d9994e6d1ab9dc735e4a drm/i915/error: Capture WA ctx batch 
in error state
d0d6a51d514a16bd3bfa623e54878212b9b450f6 drm/i915/error: add GuC state error 
capture & decode
f81fa1909e5c88e4060de69a7475404464ccd5ef drm/i915/guc: Improve action error 
reporting
e0a249a8b775364dd7a15c397a0abcef3248ce54 drm/i915/error: enhanced error capture 
of requests
6d3ceff2dfcc5e61280e977d6513d474239e252a drm/i915/error: capture errored 
context based on request context-id
93faa0817f6256aabd62a002cce06eff78c4151b drm/i915/error: improve CSB reporting
68a66e19b0ebf2fd86322fa33630d907665f8dd0 drm/i915/error: report ctx id & desc 
for each request in the queue
ca600addec12762fed301a7edc87f52de2b21604 drm/i915/error: capture ringbuffer 
pointed to by START
1b4670325fee8d046050608ea70b88d2c98def3a drm/i915/error: capture execlist state 
on error

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Re: [Intel-gfx] [PATCH] drm/i915: Execlists small cleanups and micro-optimisations

[Chris Wilson]

On Fri, Feb 26, 2016 at 03:37:35PM +, Tvrtko Ursulin wrote:
> - if (ring->disable_lite_restore_wa) {
> - /* Prevent a ctx to preempt itself */
> - if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) &&
> - (submit_contexts != 0))
> - execlists_context_unqueue(ring);
> - } else if (submit_contexts != 0) {
> + if (submit_contexts && (!ring->disable_lite_restore_wa ||
> + (ring->disable_lite_restore_wa && (status &
> + GEN8_CTX_STATUS_ACTIVE_IDLE

A little clumsy.

if (submit_contexts) {
if (!ring->disable_lite_restore_wa == 0 ||
status & GEN8_CTX_STATUS_ACTIVE_IDLE)
execlists_context_unqueue__locked(ring);
}

i.e. checking for ring->disable_lite_restore_wa != 0 is redundant (as it
must be true along the false branch of !ring->disable_lite_restore)

And if we take a moment to clean up the logic there

>   list_add_tail(>execlist_link, >execlist_queue);
> - if (num_elements == 0)
> + if (num_elements == 0) {
> + spin_lock(_priv->uncore.lock);
> + intel_uncore_forcewake_get__locked(dev_priv, FORCEWAKE_ALL);
> +
>   execlists_context_unqueue(ring);
>  
> - spin_unlock_irq(>execlist_lock);
> + intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL);
> + spin_unlock(_priv->uncore.lock);
> + }

should we hide the locks here with
void execlists_context_unqueue()
{
spin_lock(_priv->uncore.lock);
intel_uncore_forcewake_get__locked(dev_priv, FORCEWAKE_ALL);

execlists_context_unqueue__locked(ring);

intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL);
spin_unlock(_priv->uncore.lock);

}
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Execlists small cleanups and micro-optimisations

[Patchwork]

== Series Details ==

Series: drm/i915: Execlists small cleanups and micro-optimisations
URL   : https://patchwork.freedesktop.org/series/3853/
State : failure

== Summary ==

Series 3853v1 drm/i915: Execlists small cleanups and micro-optimisations
http://patchwork.freedesktop.org/api/1.0/series/3853/revisions/1/mbox/

Test kms_flip:
Subgroup basic-flip-vs-modeset:
incomplete -> PASS   (ilk-hp8440p) UNSTABLE
Test kms_force_connector_basic:
Subgroup force-load-detect:
dmesg-fail -> FAIL   (hsw-gt2)
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass   -> DMESG-WARN (skl-i7k-2) UNSTABLE
Subgroup suspend-read-crc-pipe-b:
incomplete -> PASS   (hsw-gt2)
Subgroup suspend-read-crc-pipe-c:
dmesg-warn -> PASS   (skl-i7k-2) UNSTABLE
Test pm_rpm:
Subgroup basic-rte:
pass   -> FAIL   (hsw-brixbox)

bdw-nuci7total:166  pass:155  dwarn:0   dfail:0   fail:0   skip:11 
bdw-ultratotal:169  pass:155  dwarn:0   dfail:0   fail:0   skip:14 
bsw-nuc-2total:169  pass:138  dwarn:0   dfail:0   fail:1   skip:30 
hsw-brixbox  total:169  pass:154  dwarn:0   dfail:0   fail:1   skip:14 
hsw-gt2  total:169  pass:158  dwarn:0   dfail:0   fail:1   skip:10 
ilk-hp8440p  total:169  pass:118  dwarn:1   dfail:1   fail:0   skip:49 
ivb-t430stotal:169  pass:154  dwarn:0   dfail:0   fail:1   skip:14 
skl-i7k-2total:169  pass:152  dwarn:1   dfail:0   fail:0   skip:16 
snb-dellxps  total:169  pass:146  dwarn:0   dfail:0   fail:1   skip:22 

Results at /archive/results/CI_IGT_test/Patchwork_1484/

e511a05b4b3bb4d1dbca99b00af6d0dc0a65d295 drm-intel-nightly: 
2016y-02m-26d-13h-42m-46s UTC integration manifest
24c236658acc8d2be9cc1fef21fa2feefd92d506 drm/i915: Execlists small cleanups and 
micro-optimisations

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[Intel-gfx] [PATCH v3 9/9] drm/i915/error: Capture WA ctx batch in error state

[Arun Siluvery]

From Gen8 onwards we apply ctx workarounds using special batch buffers that
execute during save/restore, good to have them in error state.

v2: use wa_ctx->size and print only size values (Mika)

v3: simplify conditions when recording and freeing object (Chris)

Cc: Chris Wilson 
Cc: Mika Kuoppala 
Reviewed-by: Mika Kuoppala 
Signed-off-by: Arun Siluvery 
---

Applied r-b received for v2, this version just simplifies conditions so I
am assuming it still holds.

 drivers/gpu/drm/i915/i915_drv.h   |  2 +-
 drivers/gpu/drm/i915/i915_gpu_error.c | 27 +++
 2 files changed, 28 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e8a47af..b1ba039 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -568,7 +568,7 @@ struct drm_i915_error_state {
bool is_ppgtt;
int page_count;
u32 *pages[0];
-   } *req_ringbuffer, *hw_ringbuffer, *batchbuffer, 
*wa_batchbuffer, *ctx, *hws_page;
+   } *req_ringbuffer, *hw_ringbuffer, *batchbuffer, 
*wa_batchbuffer, *ctx, *hws_page, *wa_ctx;
 
struct drm_i915_error_request {
u64 ctx_desc;
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
b/drivers/gpu/drm/i915/i915_gpu_error.c
index f426538..f48788e 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -659,6 +659,27 @@ int i915_error_state_to_str(struct 
drm_i915_error_state_buf *m,
}
}
 
+   if ((obj = error->ring[i].wa_ctx)) {
+   u64 wa_ctx_offset = obj->gtt_offset;
+   u32 *wa_ctx_page = >pages[0][0];
+   struct intel_engine_cs *ring = _priv->ring[RCS];
+   u32 wa_ctx_size = (ring->wa_ctx.indirect_ctx.size +
+  ring->wa_ctx.per_ctx.size);
+
+   err_printf(m, "%s --- WA Ctx batch buffer = 0x%08llx\n",
+  dev_priv->ring[i].name, wa_ctx_offset);
+   offset = 0;
+   for (elt = 0; elt < wa_ctx_size; elt += 4) {
+   err_printf(m, "[%04x] %08x %08x %08x %08x\n",
+  offset,
+  wa_ctx_page[elt],
+  wa_ctx_page[elt+1],
+  wa_ctx_page[elt+2],
+  wa_ctx_page[elt+3]);
+   offset += 16;
+   }
+   }
+
if ((obj = error->ring[i].ctx)) {
err_printf(m, "%s --- HW Context = 0x%08x\n",
   dev_priv->ring[i].name,
@@ -752,6 +773,7 @@ static void i915_error_state_free(struct kref *error_ref)
i915_error_object_free(error->ring[i].hws_page);
i915_error_object_free(error->ring[i].ctx);
kfree(error->ring[i].requests);
+   i915_error_object_free(error->ring[i].wa_ctx);
}
 
i915_error_object_free(error->semaphore_obj);
@@ -1267,6 +1289,11 @@ static void i915_gem_record_rings(struct drm_device *dev,
error->ring[i].hws_page =
i915_error_ggtt_object_create(dev_priv, 
ring->status_page.obj);
 
+   if (ring->wa_ctx.obj) {
+   error->ring[i].wa_ctx =
+   i915_error_ggtt_object_create(dev_priv, 
ring->wa_ctx.obj);
+   }
+
i915_gem_record_active_context(ring, error, >ring[i]);
 
count = 0;
-- 
1.9.1

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Re: [Intel-gfx] [PATCH v5 24/35] drm/i915: Added trace points to scheduler

[John Harrison]

On 23/02/2016 20:42, Jesse Barnes wrote:

On 02/18/2016 06:27 AM, john.c.harri...@intel.com wrote:

From: John Harrison 

Added trace points to the scheduler to track all the various events,
node state transitions and other interesting things that occur.

v2: Updated for new request completion tracking implementation.

v3: Updated for changes to node kill code.

v4: Wrapped some long lines to keep the style checker happy.

For: VIZ-1587
Signed-off-by: John Harrison 
---
  drivers/gpu/drm/i915/i915_gem_execbuffer.c |   2 +
  drivers/gpu/drm/i915/i915_scheduler.c  |  26 
  drivers/gpu/drm/i915/i915_trace.h  | 196 +
  drivers/gpu/drm/i915/intel_lrc.c   |   2 +
  4 files changed, 226 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c 
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index b9ad0fd..d4de8c7 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1272,6 +1272,8 @@ i915_gem_ringbuffer_submission(struct 
i915_execbuffer_params *params,
  
  	i915_gem_execbuffer_move_to_active(vmas, params->request);
  
+	trace_i915_gem_ring_queue(ring, params);

+
qe = container_of(params, typeof(*qe), params);
ret = i915_scheduler_queue_execbuffer(qe);
if (ret)
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c 
b/drivers/gpu/drm/i915/i915_scheduler.c
index 47d7de4..e56ce08 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -88,6 +88,8 @@ static void i915_scheduler_node_requeue(struct 
i915_scheduler_queue_entry *node)
/* Seqno will be reassigned on relaunch */
node->params.request->seqno = 0;
node->status = i915_sqs_queued;
+   trace_i915_scheduler_unfly(node->params.ring, node);
+   trace_i915_scheduler_node_state_change(node->params.ring, node);
  }
  
  /*

@@ -99,7 +101,11 @@ static void i915_scheduler_node_kill(struct 
i915_scheduler_queue_entry *node)
WARN_ON(!node);
WARN_ON(I915_SQS_IS_COMPLETE(node));
  
+	if (I915_SQS_IS_FLYING(node))

+   trace_i915_scheduler_unfly(node->params.ring, node);
+
node->status = i915_sqs_dead;
+   trace_i915_scheduler_node_state_change(node->params.ring, node);
  }
  
  /* Mark a node as in flight on the hardware. */

@@ -124,6 +130,9 @@ static int i915_scheduler_node_fly(struct 
i915_scheduler_queue_entry *node)
  
  	node->status = i915_sqs_flying;
  
+	trace_i915_scheduler_fly(ring, node);

+   trace_i915_scheduler_node_state_change(ring, node);
+
if (!(scheduler->flags[ring->id] & i915_sf_interrupts_enabled)) {
bool success = true;
  
@@ -280,6 +289,8 @@ static int i915_scheduler_pop_from_queue_locked(struct intel_engine_cs *ring,

INIT_LIST_HEAD(>link);
best->status  = i915_sqs_popped;
  
+		trace_i915_scheduler_node_state_change(ring, best);

+
ret = 0;
} else {
/* Can only get here if:
@@ -297,6 +308,8 @@ static int i915_scheduler_pop_from_queue_locked(struct 
intel_engine_cs *ring,
}
}
  
+	trace_i915_scheduler_pop_from_queue(ring, best);

+
*pop_node = best;
return ret;
  }
@@ -506,6 +519,8 @@ static int i915_scheduler_queue_execbuffer_bypass(struct 
i915_scheduler_queue_en
struct i915_scheduler *scheduler = dev_priv->scheduler;
int ret;
  
+	trace_i915_scheduler_queue(qe->params.ring, qe);

+
intel_ring_reserved_space_cancel(qe->params.request->ringbuf);
  
  	scheduler->flags[qe->params.ring->id] |= i915_sf_submitting;

@@ -628,6 +643,9 @@ int i915_scheduler_queue_execbuffer(struct 
i915_scheduler_queue_entry *qe)
not_flying = i915_scheduler_count_flying(scheduler, ring) <
 scheduler->min_flying;
  
+	trace_i915_scheduler_queue(ring, node);

+   trace_i915_scheduler_node_state_change(ring, node);
+
spin_unlock_irq(>lock);
  
  	if (not_flying)

@@ -657,6 +675,8 @@ bool i915_scheduler_notify_request(struct 
drm_i915_gem_request *req)
struct i915_scheduler_queue_entry *node = req->scheduler_qe;
unsigned long flags;
  
+	trace_i915_scheduler_landing(req);

+
if (!node)
return false;
  
@@ -670,6 +690,8 @@ bool i915_scheduler_notify_request(struct drm_i915_gem_request *req)

else
node->status = i915_sqs_complete;
  
+	trace_i915_scheduler_node_state_change(req->ring, node);

+
spin_unlock_irqrestore(>lock, flags);
  
  	return true;

@@ -877,6 +899,8 @@ static bool i915_scheduler_remove(struct i915_scheduler 
*scheduler,
/* Launch more packets now? */
do_submit = (queued > 0) && (flying < scheduler->min_flying);
  
+	trace_i915_scheduler_remove(ring, min_seqno, do_submit);

+
spin_unlock_irq(>lock);
  
  	return do_submit;

@@ 

Re: [Intel-gfx] [PATCH 3/5] drm: introduce pipe color correction properties

[Lionel Landwerlin]

On 26/02/16 00:36, Emil Velikov wrote:

Hi Lionel,

A bunch of suggestions - feel free to take or ignore them :-)

On 25 February 2016 at 10:58, Lionel Landwerlin
 wrote:

Patch based on a previous series by Shashank Sharma.

This introduces optional properties to enable color correction at the
pipe level. It relies on 3 transformations applied to every pixels
displayed. First a lookup into a degamma table, then a multiplication
of the rgb components by a 3x3 matrix and finally another lookup into
a gamma table.

The following properties can be added to a pipe :
   - DEGAMMA_LUT : blob containing degamma LUT
   - DEGAMMA_LUT_SIZE : number of elements in DEGAMMA_LUT
   - CTM : transformation matrix applied after the degamma LUT
   - GAMMA_LUT : blob containing gamma LUT
   - GAMMA_LUT_SIZE : number of elements in GAMMA_LUT

DEGAMMA_LUT_SIZE and GAMMA_LUT_SIZE are read only properties, set by
the driver to tell userspace applications what sizes should be the
lookup tables in DEGAMMA_LUT and GAMMA_LUT.

A helper is also provided so legacy gamma correction is redirected
through these new properties.

v2: Register LUT size properties as range

v3: Fix round in drm_color_lut_get_value() helper
 More docs on how degamma/gamma properties are used

v4: Update contributors

v5: Rename CTM_MATRIX property to CTM (Doh!)
 Add legacy gamma_set atomic helper
 Describe CTM/LUT acronyms in the kernel doc

Signed-off-by: Shashank Sharma 
Signed-off-by: Lionel Landwerlin 
Signed-off-by: Kumar, Kiran S 
Signed-off-by: Kausal Malladi 

The above should be kept in the order of which people worked on them.


Reviewed-by: Matt Roper 
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -376,6 +377,57 @@ int drm_atomic_set_mode_prop_for_crtc(struct 
drm_crtc_state *state,
  EXPORT_SYMBOL(drm_atomic_set_mode_prop_for_crtc);

  /**
+ * drm_atomic_replace_property_blob - replace a blob property
+ * @blob: a pointer to the member blob to be replaced
+ * @new_blob: the new blob to replace with
+ * @expected_size: the expected size of the new blob
+ * @replaced: whether the blob has been replaced
+ *
+ * RETURNS:
+ * Zero on success, error code on failure
+ */
+static int
+drm_atomic_replace_property_blob(struct drm_property_blob **blob,
+struct drm_property_blob *new_blob,
+bool *replaced)

"Replaced" here and though the rest of the patch is used as "changed".
Worth naming it that way ?

I think the former describes the action, the later the state.




+{
+   struct drm_property_blob *old_blob = *blob;
+
+   if (old_blob == new_blob)
+   return 0;
+
+   if (old_blob)
+   drm_property_unreference_blob(old_blob);
+   if (new_blob)
+   drm_property_reference_blob(new_blob);
+   *blob = new_blob;
+   *replaced = true;
+
+   return 0;

The function always succeeds - drop the return value ?

Well spotted, dropping.


+}
+
+static int
+drm_atomic_replace_property_blob_from_id(struct drm_crtc *crtc,
+struct drm_property_blob **blob,
+uint64_t blob_id,
+ssize_t expected_size,
+bool *replaced)
+{
+   struct drm_device *dev = crtc->dev;
+   struct drm_property_blob *new_blob = NULL;
+
+   if (blob_id != 0) {
+   new_blob = drm_property_lookup_blob(dev, blob_id);
+   if (new_blob == NULL)
+   return -EINVAL;
+   if (expected_size > 0 && expected_size != new_blob->length)
+   return -EINVAL;
+   }
+

Having a look at drm_atomic_set_mode_prop_for_crtc() I think I can
spot a bug - it shouldn't drop/unref the old blob in case of an error.
A case you handle nicely here. Perhaps it's worth using the
drm_atomic_replace_property_blob() in there ?


I'm not sure it matters as the drm_crtc_state you're set properties on 
will be discarded if there is an error.
The current drm_crtc_state that has been applied onto the hardware 
should be untouched.





@@ -397,6 +449,7 @@ int drm_atomic_crtc_set_property(struct drm_crtc *crtc,
  {
 struct drm_device *dev = crtc->dev;
 struct drm_mode_config *config = >mode_config;
+   bool replaced = false;
 int ret;

 if (property == config->prop_active)
@@ -407,8 +460,31 @@ int drm_atomic_crtc_set_property(struct drm_crtc *crtc,
 ret = drm_atomic_set_mode_prop_for_crtc(state, mode);
 drm_property_unreference_blob(mode);
 return ret;
-   }
-   else if (crtc->funcs->atomic_set_property)
+   } else if (property == config->degamma_lut_property) {
+   

Re: [Intel-gfx] [RFC] drm/i915: Check if we hold a wakeref during ioread32/iowrite32

[Imre Deak]

On ti, 2016-02-23 at 16:54 +, Chris Wilson wrote:
> On Tue, Feb 23, 2016 at 05:09:29PM +0200, Imre Deak wrote:
> > On ti, 2016-02-23 at 14:55 +, Chris Wilson wrote:
> > > On Tue, Feb 23, 2016 at 04:47:17PM +0200, Imre Deak wrote:
> > [...]
> > > How's the separation of struct_mutex from rpm going so that we
> > > can
> > > forgo
> > > adding assertions and use explicit power management instead?
> > 
> > It's planned to be done, but no one is working on that yet. This is
> > something we could still have regardless, similarly to other
> > helpers
> > accessing the device.
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c
> b/drivers/gpu/drm/i915/i915_drv.c
> index 31b600d31158..b8687b6a6acb 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1430,24 +1430,6 @@ static int intel_runtime_suspend(struct device
> *device)
>  
> DRM_DEBUG_KMS("Suspending device\n");
>  
> -   /*
> -* We could deadlock here in case another thread holding
> struct_mutex
> -* calls RPM suspend concurrently, since the RPM suspend will
> wait
> -* first for this RPM suspend to finish. In this case the
> concurrent
> -* RPM resume will be followed by its RPM suspend
> counterpart. Still
> -* for consistency return -EAGAIN, which will reschedule this
> suspend.
> -*/
> -   if (!mutex_trylock(>struct_mutex)) {
> -   DRM_DEBUG_KMS("device lock contention, deffering
> suspend\n");
> -   /*
> -* Bump the expiration timestamp, otherwise the
> suspend won't
> -* be rescheduled.
> -*/
> -   pm_runtime_mark_last_busy(device);
> -
> -   return -EAGAIN;
> -   }
> -
> disable_rpm_wakeref_asserts(dev_priv);
>  
> /*
> @@ -1455,7 +1437,6 @@ static int intel_runtime_suspend(struct device
> *device)
>  * an RPM reference.
>  */
> i915_gem_release_all_mmaps(dev_priv);
> -   mutex_unlock(>struct_mutex);
>  
> intel_guc_suspend(dev);
>  
> diff --git a/drivers/gpu/drm/i915/i915_gem.c
> b/drivers/gpu/drm/i915/i915_gem.c
> index 79706621e6e4..4f6127466822 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -1670,9 +1670,13 @@ i915_gem_release_mmap(struct
> drm_i915_gem_object *obj)
> /* Serialisation between user GTT access and our code depends
> upon
>  * revoking the CPU's PTE whilst the mutex is held. The next
> user
>  * pagefault then has to wait until we release the mutex.
> +*
> +* Note that RPM complicates somewhat by adding an additional
> +* requirement that operations to the GGTT be made holding
> the RPM
> +* wakeref. This in turns allow us to release the mmap from
> within
> +* the RPM suspend code ignoring the struct_mutex
> serialisation in
> +* lieu of the RPM barriers.
>  */
> -   lockdep_assert_held(>base.dev->struct_mutex);
> -
> if (!obj->fault_mappable)
> return;
>  
> @@ -1685,11 +1689,21 @@ i915_gem_release_mmap(struct
> drm_i915_gem_object *obj)
> obj->fault_mappable = false;
>  }
>  
> +static void assert_rpm_release_all_mmaps(struct drm_i915_private
> *dev_priv)
> +{
> +   assert_rpm_wakelock_held(dev_priv);
> +}
> +
>  void
>  i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
>  {
> struct drm_i915_gem_object *obj;
>  
> +   /* This should only be called by RPM as we require the
> bound_list
> +* to be protected by the RPM barriers and not struct_mutex.
> +* We check that we are holding the wakeref whenever we
> manipulate
> +* the dev_priv->mm.bound_list (via
> assert_rpm_release_all_mmaps).
> +*/
> list_for_each_entry(obj, _priv->mm.bound_list,
> global_list)
> i915_gem_release_mmap(obj);
>  }
> @@ -2224,9 +2238,11 @@ i915_gem_object_retire__read(struct
> i915_gem_active *active,
>  * so that we don't steal from recently used but inactive
> objects
>  * (unless we are forced to ofc!)
>  */
> -   if (obj->bind_count)
> +   if (obj->bind_count) {
> +   assert_rpm_release_all_mmaps(request->i915);
> list_move_tail(>global_list,
>    >i915->mm.bound_list);
> +   }
>  
> if (i915_gem_object_has_active_reference(obj)) {
> i915_gem_object_unset_active_reference(obj);
> @@ -2751,9 +2767,11 @@ int i915_vma_unbind(struct i915_vma *vma)
>  
> /* Since the unbound list is global, only move to that list
> if
>  * no more VMAs exist. */
> -   if (--obj->bind_count == 0)
> +   if (--obj->bind_count == 0) {
> +   assert_rpm_release_all_mmaps(to_i915(obj->base.dev));
> list_move_tail(>global_list,
>    _i915(obj->base.dev)-
> >mm.unbound_list);
> +   }

[Intel-gfx] [PATCH] drm/i915: Execlists small cleanups and micro-optimisations

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Assorted changes in the areas of code cleanup, reduction of
invariant conditional in the interrupt handler and lock
contention and MMIO access optimisation.

 * Remove needless initialization.
 * Improve cache locality by reorganizing code and/or using
   branch hints to keep unexpected or error conditions out
   of line.
 * Favor busy submit path vs. empty queue.
 * Less branching in hot-paths.

v2:

 * Avoid mmio reads when possible. (Chris Wilson)
 * Use natural integer size for csb indices.
 * Remove useless return value from execlists_update_context.
 * Extract 32-bit ppgtt PDPs update so it is out of line and
   shared with two callers.
 * Grab forcewake across all mmio operations to ease the
   load on uncore lock and use chepear mmio ops.

v3:

 * Removed some more pointless u8 data types.
 * Removed unused return from execlists_context_queue.
 * Commit message updates.

Version 3 now makes the irq handling code path ~20% smaller on
48-bit PPGTT hardware, and a little bit less elsewhere. Hot
paths are mostly in-line now and hammering on the uncore
spinlock is greatly reduced together with mmio traffic to an
extent.

Benchmarking with "gem_latency -n 100" (keep submitting
batches with 100 nop instruction) shows approximately 4% higher
throughput, 2% less CPU time and 22% smaller latencies. This was
on a big-core while small-cores could benefit even more.

Most likely reason for the improvements are the MMIO
optimization and uncore lock traffic reduction.

Signed-off-by: Tvrtko Ursulin 
Cc: Chris Wilson 
---
 drivers/gpu/drm/i915/intel_lrc.c| 208 
 drivers/gpu/drm/i915/intel_ringbuffer.h |   3 +-
 2 files changed, 108 insertions(+), 103 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index f0a57afc8dff..0f4dae257fa6 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -269,6 +269,9 @@ logical_ring_init_platform_invariants(struct 
intel_engine_cs *ring)
 {
struct drm_device *dev = ring->dev;
 
+   if (IS_GEN8(dev) || IS_GEN9(dev))
+   ring->idle_lite_restore_wa = ~0;
+
ring->disable_lite_restore_wa = (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
IS_BXT_REVID(dev, 0, BXT_REVID_A1)) &&
(ring->id == VCS || ring->id == VCS2);
@@ -372,8 +375,6 @@ static void execlists_elsp_write(struct 
drm_i915_gem_request *rq0,
rq0->elsp_submitted++;
 
/* You must always write both descriptors in the order below. */
-   spin_lock(_priv->uncore.lock);
-   intel_uncore_forcewake_get__locked(dev_priv, FORCEWAKE_ALL);
I915_WRITE_FW(RING_ELSP(ring), upper_32_bits(desc[1]));
I915_WRITE_FW(RING_ELSP(ring), lower_32_bits(desc[1]));
 
@@ -383,11 +384,18 @@ static void execlists_elsp_write(struct 
drm_i915_gem_request *rq0,
 
/* ELSP is a wo register, use another nearby reg for posting */
POSTING_READ_FW(RING_EXECLIST_STATUS_LO(ring));
-   intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL);
-   spin_unlock(_priv->uncore.lock);
 }
 
-static int execlists_update_context(struct drm_i915_gem_request *rq)
+static void
+execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state)
+{
+   ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
+   ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
+   ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
+   ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
+}
+
+static void execlists_update_context(struct drm_i915_gem_request *rq)
 {
struct intel_engine_cs *ring = rq->ring;
struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt;
@@ -395,19 +403,13 @@ static int execlists_update_context(struct 
drm_i915_gem_request *rq)
 
reg_state[CTX_RING_TAIL+1] = rq->tail;
 
-   if (ppgtt && !USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
-   /* True 32b PPGTT with dynamic page allocation: update PDP
-* registers and point the unallocated PDPs to scratch page.
-* PML4 is allocated during ppgtt init, so this is not needed
-* in 48-bit mode.
-*/
-   ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
-   ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
-   ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
-   ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
-   }
-
-   return 0;
+   /* True 32b PPGTT with dynamic page allocation: update PDP
+* registers and point the unallocated PDPs to scratch page.
+* PML4 is allocated during ppgtt init, so this is not needed
+* in 48-bit mode.
+*/
+   if (ppgtt && !USES_FULL_48BIT_PPGTT(ppgtt->base.dev))
+   execlists_update_context_pdps(ppgtt, reg_state);
 }
 
 static void execlists_submit_requests(struct drm_i915_gem_request *rq0,
@@ -424,7 +426,7 @@ static 

Re: [Intel-gfx] [PATCH v2 9/9] drm/i915/error: Capture WA ctx batch in error state

[Chris Wilson]

On Fri, Feb 26, 2016 at 04:53:03PM +0200, Mika Kuoppala wrote:
> Arun Siluvery  writes:
> 
> > From Gen8 onwards we apply ctx workarounds using special batch buffers that
> > execute during save/restore, good to have them in error state.
> >
> > v2: use wa_ctx->size and print only size values (Mika)
> >
> > Signed-off-by: Arun Siluvery 
> 
> Reviewed-by: Mika Kuoppala 
> 
> > ---
> >  drivers/gpu/drm/i915/i915_drv.h   |  2 +-
> >  drivers/gpu/drm/i915/i915_gpu_error.c | 28 
> >  2 files changed, 29 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h 
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index f7808d3..7ad0b47 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -568,7 +568,7 @@ struct drm_i915_error_state {
> > bool is_ppgtt;
> > int page_count;
> > u32 *pages[0];
> > -   } *req_ringbuffer, *hw_ringbuffer, *batchbuffer, 
> > *wa_batchbuffer, *ctx, *hws_page;
> > +   } *req_ringbuffer, *hw_ringbuffer, *batchbuffer, 
> > *wa_batchbuffer, *ctx, *hws_page, *wa_ctx;
> >  
> > struct drm_i915_error_request {
> > u64 ctx_desc;
> > diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
> > b/drivers/gpu/drm/i915/i915_gpu_error.c
> > index f426538..b62edbb 100644
> > --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> > +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> > @@ -659,6 +659,27 @@ int i915_error_state_to_str(struct 
> > drm_i915_error_state_buf *m,
> > }
> > }
> >  
> > +   if ((obj = error->ring[i].wa_ctx)) {
> > +   u64 wa_ctx_offset = obj->gtt_offset;
> > +   u32 *wa_ctx_page = >pages[0][0];
> > +   struct intel_engine_cs *ring = _priv->ring[RCS];
> > +   u32 wa_ctx_size = (ring->wa_ctx.indirect_ctx.size +
> > +  ring->wa_ctx.per_ctx.size);
> > +
> > +   err_printf(m, "%s --- WA Ctx batch buffer = 0x%08llx\n",
> > +  dev_priv->ring[i].name, wa_ctx_offset);
> > +   offset = 0;
> > +   for (elt = 0; elt < wa_ctx_size; elt += 4) {
> > +   err_printf(m, "[%04x] %08x %08x %08x %08x\n",
> > +  offset,
> > +  wa_ctx_page[elt],
> > +  wa_ctx_page[elt+1],
> > +  wa_ctx_page[elt+2],
> > +  wa_ctx_page[elt+3]);
> > +   offset += 16;
> > +   }
> > +   }
> > +
> > if ((obj = error->ring[i].ctx)) {
> > err_printf(m, "%s --- HW Context = 0x%08x\n",
> >dev_priv->ring[i].name,
> > @@ -752,6 +773,8 @@ static void i915_error_state_free(struct kref 
> > *error_ref)
> > i915_error_object_free(error->ring[i].hws_page);
> > i915_error_object_free(error->ring[i].ctx);
> > kfree(error->ring[i].requests);
> > +   if (i == RCS)
> > +   i915_error_object_free(error->ring[i].wa_ctx);

Just always free it, it is a no-op if NULL.

> > +   if (INTEL_INFO(dev)->gen >= 8 && ring->id == RCS) {
> > +   error->ring[i].wa_ctx =
> > +   i915_error_ggtt_object_create(dev_priv, 
> > ring->wa_ctx.obj);

Just always record it if wa_ctx.obj exists.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
___
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Intel-gfx@lists.freedesktop.org
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Re: [Intel-gfx] [PATCH v2 9/9] drm/i915/error: Capture WA ctx batch in error state

[Mika Kuoppala]

Arun Siluvery  writes:

> From Gen8 onwards we apply ctx workarounds using special batch buffers that
> execute during save/restore, good to have them in error state.
>
> v2: use wa_ctx->size and print only size values (Mika)
>
> Signed-off-by: Arun Siluvery 

Reviewed-by: Mika Kuoppala 

> ---
>  drivers/gpu/drm/i915/i915_drv.h   |  2 +-
>  drivers/gpu/drm/i915/i915_gpu_error.c | 28 
>  2 files changed, 29 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index f7808d3..7ad0b47 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -568,7 +568,7 @@ struct drm_i915_error_state {
>   bool is_ppgtt;
>   int page_count;
>   u32 *pages[0];
> - } *req_ringbuffer, *hw_ringbuffer, *batchbuffer, 
> *wa_batchbuffer, *ctx, *hws_page;
> + } *req_ringbuffer, *hw_ringbuffer, *batchbuffer, 
> *wa_batchbuffer, *ctx, *hws_page, *wa_ctx;
>  
>   struct drm_i915_error_request {
>   u64 ctx_desc;
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
> b/drivers/gpu/drm/i915/i915_gpu_error.c
> index f426538..b62edbb 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -659,6 +659,27 @@ int i915_error_state_to_str(struct 
> drm_i915_error_state_buf *m,
>   }
>   }
>  
> + if ((obj = error->ring[i].wa_ctx)) {
> + u64 wa_ctx_offset = obj->gtt_offset;
> + u32 *wa_ctx_page = >pages[0][0];
> + struct intel_engine_cs *ring = _priv->ring[RCS];
> + u32 wa_ctx_size = (ring->wa_ctx.indirect_ctx.size +
> +ring->wa_ctx.per_ctx.size);
> +
> + err_printf(m, "%s --- WA Ctx batch buffer = 0x%08llx\n",
> +dev_priv->ring[i].name, wa_ctx_offset);
> + offset = 0;
> + for (elt = 0; elt < wa_ctx_size; elt += 4) {
> + err_printf(m, "[%04x] %08x %08x %08x %08x\n",
> +offset,
> +wa_ctx_page[elt],
> +wa_ctx_page[elt+1],
> +wa_ctx_page[elt+2],
> +wa_ctx_page[elt+3]);
> + offset += 16;
> + }
> + }
> +
>   if ((obj = error->ring[i].ctx)) {
>   err_printf(m, "%s --- HW Context = 0x%08x\n",
>  dev_priv->ring[i].name,
> @@ -752,6 +773,8 @@ static void i915_error_state_free(struct kref *error_ref)
>   i915_error_object_free(error->ring[i].hws_page);
>   i915_error_object_free(error->ring[i].ctx);
>   kfree(error->ring[i].requests);
> + if (i == RCS)
> + i915_error_object_free(error->ring[i].wa_ctx);
>   }
>  
>   i915_error_object_free(error->semaphore_obj);
> @@ -1267,6 +1290,11 @@ static void i915_gem_record_rings(struct drm_device 
> *dev,
>   error->ring[i].hws_page =
>   i915_error_ggtt_object_create(dev_priv, 
> ring->status_page.obj);
>  
> + if (INTEL_INFO(dev)->gen >= 8 && ring->id == RCS) {
> + error->ring[i].wa_ctx =
> + i915_error_ggtt_object_create(dev_priv, 
> ring->wa_ctx.obj);
> + }
> +
>   i915_gem_record_active_context(ring, error, >ring[i]);
>  
>   count = 0;
> -- 
> 1.9.1
>
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[Intel-gfx] ✗ Fi.CI.BAT: failure for Shared pll improvements

[Patchwork]

== Series Details ==

Series: Shared pll improvements
URL   : https://patchwork.freedesktop.org/series/3850/
State : failure

== Summary ==

Series 3850v1 Shared pll improvements
http://patchwork.freedesktop.org/api/1.0/series/3850/revisions/1/mbox/

Test kms_flip:
Subgroup basic-flip-vs-dpms:
pass   -> DMESG-WARN (bdw-ultra)
dmesg-warn -> PASS   (ilk-hp8440p) UNSTABLE
Subgroup basic-flip-vs-modeset:
incomplete -> PASS   (ilk-hp8440p) UNSTABLE
Subgroup basic-flip-vs-wf_vblank:
pass   -> FAIL   (snb-x220t)
Test kms_force_connector_basic:
Subgroup force-load-detect:
fail   -> DMESG-FAIL (snb-x220t)
dmesg-fail -> FAIL   (ilk-hp8440p)
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass   -> DMESG-WARN (bdw-ultra)
Subgroup suspend-read-crc-pipe-b:
incomplete -> PASS   (hsw-gt2)
pass   -> DMESG-WARN (bdw-ultra)
Subgroup suspend-read-crc-pipe-c:
pass   -> DMESG-WARN (bdw-ultra)
Test pm_rpm:
Subgroup basic-pci-d3-state:
pass   -> DMESG-WARN (bsw-nuc-2)

bdw-nuci7total:166  pass:155  dwarn:0   dfail:0   fail:0   skip:11 
bdw-ultratotal:169  pass:151  dwarn:4   dfail:0   fail:0   skip:14 
bsw-nuc-2total:169  pass:137  dwarn:1   dfail:0   fail:1   skip:30 
byt-nuc  total:169  pass:144  dwarn:0   dfail:0   fail:0   skip:25 
hsw-brixbox  total:169  pass:155  dwarn:0   dfail:0   fail:0   skip:14 
hsw-gt2  total:169  pass:158  dwarn:0   dfail:1   fail:0   skip:10 
ilk-hp8440p  total:169  pass:119  dwarn:0   dfail:0   fail:1   skip:49 
ivb-t430stotal:169  pass:154  dwarn:0   dfail:0   fail:1   skip:14 
skl-i7k-2total:169  pass:152  dwarn:1   dfail:0   fail:0   skip:16 
snb-dellxps  total:169  pass:146  dwarn:0   dfail:0   fail:1   skip:22 
snb-x220ttotal:169  pass:145  dwarn:0   dfail:1   fail:2   skip:21 

Results at /archive/results/CI_IGT_test/Patchwork_1483/

e511a05b4b3bb4d1dbca99b00af6d0dc0a65d295 drm-intel-nightly: 
2016y-02m-26d-13h-42m-46s UTC integration manifest
18253fa9f7d2984ec00687536e95777a19c10f15 drm/i915: Make SKL/KBL DPLL0 managed 
by the shared dpll code
b3041c989419f0d1d72282d697fc3452a66c7548 drm/i915: Manage HSW/BDW LCPLLs with 
the shared dpll interface
56b6dbd16b575c5f7c4715b03bcf47a3c649e1b4 drm/i915: Move BXT pll configuration 
logic to intel_dpll_mgr.c
9875c10e3933ada70175129384644dcfbebd539b drm/i915: Move SKL/KLB pll selection 
logic to intel_dpll_mgr.c
076dd92201a86cb74ca38bc592bf2f9c7c79ef82 drm/i915: Move HSW/BDW pll selection 
logic to intel_dpll_mgr.c
a48e2acab48bf343a929d3956c042d21e403dbdb drm/i915: Refactor platform specifics 
out of intel_get_shared_dpll()
ccea2d6bd0d09abc60fe5536bf8a5ad5885f341f drm/i915: Use a table to initilize 
shared dplls
c4671642db12a3adaf585d1c9d307e08c7606757 drm/i915: Move shared dpll function 
prototypes to intel_dpll_mgr.h
483a9a210246878470950dba9c1738b4403de6bc drm/i915: Move shared dpll struct 
definitions to separate header file
dc1a46803941180998188ec5fe431e4edc9ec7e5 drm/i915: Store a direct pointer to 
shared dpll in intel_crtc_state
5c6d7fd24a992bc44f6331487abc4f7893260976 drm/i915: Split 
intel_get_shared_dpll() into smaller functions
896bc10b27221cb3dd04dd207c877d13265757cf drm/i915: Move ddi shared dpll code to 
intel_dpll_mgr.c
b8058dc895423649ea6e561e70d89b325e709cd1 drm/i915: Move shared dpll code to a 
new file

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Re: [Intel-gfx] [PATCH v5 06/35] drm/i915: Start of GPU scheduler

[John Harrison]

On 26/02/2016 09:13, Joonas Lahtinen wrote:

Hi,

The below answers are reasonable. So v6 should be the version.


Are you planning on looking at the other patches first or are you going 
to wait until v6 is posted?


Thanks,
John.

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Re: [Intel-gfx] [PATCH] drm/i915: Balance assert_rpm_wakelock_held() for !IS_ENABLED(CONFIG_PM)

[Imre Deak]

On pe, 2016-02-26 at 00:20 +0200, Imre Deak wrote:
> On Thu, 2016-02-25 at 21:10 +, Chris Wilson wrote:
> > commit 09731280028ce03e6a27e1998137f1775a2839f3
> > Author: Imre Deak 
> > Date:   Wed Feb 17 14:17:42 2016 +0200
> > 
> > drm/i915: Add helper to get a display power ref if it was
> > already
> > enabled
> > 
> > left the rpm wakelock assertions unbalanced if CONFIG_PM was
> > disabled
> > as
> > intel_runtime_pm_get_if_in_use() would return true without
> > incrementing
> > the local bookkeeping required for the assertions.
> > 
> > Signed-off-by: Chris Wilson 
> > CC: Mika Kuoppala 
> > CC: Joonas Lahtinen 
> > CC: Ville Syrjälä 
> > Cc: Imre Deak 
> 
> Arg, I broke this in v3. Thanks for catching it:
> Reviewed-by: Imre Deak 

Thanks for the patch I pushed it to drm-intel-next-queued.

Dave, this fixes one patch in the following pull request:
https://lists.freedesktop.org/archives/intel-gfx/2016-February/088249.html

--Imre

> > ---
> >  drivers/gpu/drm/i915/intel_runtime_pm.c | 26 -
> > --
> > ---
> >  1 file changed, 12 insertions(+), 14 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index e2329768902c..4172e73212cd 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -2365,22 +2365,20 @@ bool intel_runtime_pm_get_if_in_use(struct
> > drm_i915_private *dev_priv)
> >  {
> >     struct drm_device *dev = dev_priv->dev;
> >     struct device *device = >pdev->dev;
> > -   int ret;
> >  
> > -   if (!IS_ENABLED(CONFIG_PM))
> > -   return true;
> > +   if (IS_ENABLED(CONFIG_PM)) {
> > +   int ret = pm_runtime_get_if_in_use(device);
> >  
> > -   ret = pm_runtime_get_if_in_use(device);
> > -
> > -   /*
> > -    * In cases runtime PM is disabled by the RPM core and we
> > get an
> > -    * -EINVAL return value we are not supposed to call this
> > function,
> > -    * since the power state is undefined. This applies atm to
> > the
> > -    * late/early system suspend/resume handlers.
> > -    */
> > -   WARN_ON_ONCE(ret < 0);
> > -   if (ret <= 0)
> > -   return false;
> > +   /*
> > +    * In cases runtime PM is disabled by the RPM core
> > and we get
> > +    * an -EINVAL return value we are not supposed to
> > call this
> > +    * function, since the power state is undefined.
> > This applies
> > +    * atm to the late/early system suspend/resume
> > handlers.
> > +    */
> > +   WARN_ON_ONCE(ret < 0);
> > +   if (ret <= 0)
> > +   return false;
> > +   }
> >  
> >     atomic_inc(_priv->pm.wakeref_count);
> >     assert_rpm_wakelock_held(dev_priv);
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[Intel-gfx] [PATCH 05/13] drm/i915: Move shared dpll struct definitions to separate header file

[Ander Conselvan de Oliveira]

Move the declarations related to shared dplls from i915_drv.h to their
own header file.

The code that became the shared dpll infrastructre was first introcude
in commit ee7b9f93fd96 ("drm/i915: manage PCH PLLs separately from
pipes"), hence the 2012-2016 copyright years in the new header file.

Signed-off-by: Ander Conselvan de Oliveira 

---
 drivers/gpu/drm/i915/i915_drv.h   |  76 +---
 drivers/gpu/drm/i915/intel_dpll_mgr.h | 106 ++
 2 files changed, 107 insertions(+), 75 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_dpll_mgr.h

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9e76bfc..6de93dc 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -53,6 +53,7 @@
 #include 
 #include 
 #include "intel_guc.h"
+#include "intel_dpll_mgr.h"
 
 /* General customization:
  */
@@ -340,81 +341,6 @@ struct drm_i915_file_private {
unsigned int bsd_ring;
 };
 
-enum intel_dpll_id {
-   DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
-   /* real shared dpll ids must be >= 0 */
-   DPLL_ID_PCH_PLL_A = 0,
-   DPLL_ID_PCH_PLL_B = 1,
-   /* hsw/bdw */
-   DPLL_ID_WRPLL1 = 0,
-   DPLL_ID_WRPLL2 = 1,
-   DPLL_ID_SPLL = 2,
-
-   /* skl */
-   DPLL_ID_SKL_DPLL1 = 0,
-   DPLL_ID_SKL_DPLL2 = 1,
-   DPLL_ID_SKL_DPLL3 = 2,
-};
-#define I915_NUM_PLLS 3
-
-struct intel_dpll_hw_state {
-   /* i9xx, pch plls */
-   uint32_t dpll;
-   uint32_t dpll_md;
-   uint32_t fp0;
-   uint32_t fp1;
-
-   /* hsw, bdw */
-   uint32_t wrpll;
-   uint32_t spll;
-
-   /* skl */
-   /*
-* DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
-* lower part of ctrl1 and they get shifted into position when writing
-* the register.  This allows us to easily compare the state to share
-* the DPLL.
-*/
-   uint32_t ctrl1;
-   /* HDMI only, 0 when used for DP */
-   uint32_t cfgcr1, cfgcr2;
-
-   /* bxt */
-   uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10,
-pcsdw12;
-};
-
-struct intel_shared_dpll_config {
-   unsigned crtc_mask; /* mask of CRTCs sharing this PLL */
-   struct intel_dpll_hw_state hw_state;
-};
-
-struct intel_shared_dpll {
-   struct intel_shared_dpll_config config;
-
-   int active; /* count of number of active CRTCs (i.e. DPMS on) */
-   bool on; /* is the PLL actually active? Disabled during modeset */
-   const char *name;
-   /* should match the index in the dev_priv->shared_dplls array */
-   enum intel_dpll_id id;
-   /* The mode_set hook is optional and should be used together with the
-* intel_prepare_shared_dpll function. */
-   void (*mode_set)(struct drm_i915_private *dev_priv,
-struct intel_shared_dpll *pll);
-   void (*enable)(struct drm_i915_private *dev_priv,
-  struct intel_shared_dpll *pll);
-   void (*disable)(struct drm_i915_private *dev_priv,
-   struct intel_shared_dpll *pll);
-   bool (*get_hw_state)(struct drm_i915_private *dev_priv,
-struct intel_shared_dpll *pll,
-struct intel_dpll_hw_state *hw_state);
-};
-
-#define SKL_DPLL0 0
-#define SKL_DPLL1 1
-#define SKL_DPLL2 2
-#define SKL_DPLL3 3
-
 /* Used by dp and fdi links */
 struct intel_link_m_n {
uint32_ttu;
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h 
b/drivers/gpu/drm/i915/intel_dpll_mgr.h
new file mode 100644
index 000..a62d1ba
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright © 2012-2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#ifndef 

[Intel-gfx] [PATCH 08/13] drm/i915: Refactor platform specifics out of intel_get_shared_dpll()

[Ander Conselvan de Oliveira]

The function intel_get_shared_dpll() had a more or less generic
implementation with some platform specific checks to handle smaller
differences between platforms. However, the minimalist approach forces
bigger differences between platforms to be implemented outside of the
shared dpll code (see the *_ddi_pll_select() functions in intel_ddi.c,
for instance).

This patch changes the implementation of intel_get_share_dpll() so that
a completely platform specific version can be used, providing helpers to
reduce code duplication. This should allow the code from the ddi pll
select functions to be moved, and also make room for making more dplls
managed by the shared dpll infrastructure.

Signed-off-by: Ander Conselvan de Oliveira 

---
 drivers/gpu/drm/i915/i915_drv.h   |   1 +
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 226 +-
 drivers/gpu/drm/i915/intel_dpll_mgr.h |   2 +
 3 files changed, 145 insertions(+), 84 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6de93dc..b858801 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1802,6 +1802,7 @@ struct drm_i915_private {
/* dpll and cdclk state is protected by connection_mutex */
int num_shared_dpll;
struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
+   const struct intel_dpll_mgr *dpll_mgr;
 
unsigned int active_crtcs;
unsigned int min_pixclk[I915_MAX_PIPES];
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c 
b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index e88dc46..3553324 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -174,66 +174,20 @@ void intel_disable_shared_dpll(struct intel_crtc *crtc)
intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
 }
 
-static enum intel_dpll_id
-ibx_get_fixed_dpll(struct intel_crtc *crtc,
-  struct intel_crtc_state *crtc_state)
-{
-   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-   struct intel_shared_dpll *pll;
-   enum intel_dpll_id i;
-
-   /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
-   i = (enum intel_dpll_id) crtc->pipe;
-   pll = _priv->shared_dplls[i];
-
-   DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
- crtc->base.base.id, pll->name);
-
-   return i;
-}
-
-static enum intel_dpll_id
-bxt_get_fixed_dpll(struct intel_crtc *crtc,
-  struct intel_crtc_state *crtc_state)
-{
-   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-   struct intel_encoder *encoder;
-   struct intel_digital_port *intel_dig_port;
-   struct intel_shared_dpll *pll;
-   enum intel_dpll_id i;
-
-   /* PLL is attached to port in bxt */
-   encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
-   if (WARN_ON(!encoder))
-   return DPLL_ID_PRIVATE;
-
-   intel_dig_port = enc_to_dig_port(>base);
-   /* 1:1 mapping between ports and PLLs */
-   i = (enum intel_dpll_id)intel_dig_port->port;
-   pll = _priv->shared_dplls[i];
-   DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
-   crtc->base.base.id, pll->name);
-
-   return i;
-}
-
-static enum intel_dpll_id
+static struct intel_shared_dpll *
 intel_find_shared_dpll(struct intel_crtc *crtc,
-  struct intel_crtc_state *crtc_state)
+  struct intel_crtc_state *crtc_state,
+  enum intel_dpll_id range_min,
+  enum intel_dpll_id range_max)
 {
struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
struct intel_shared_dpll *pll;
struct intel_shared_dpll_config *shared_dpll;
enum intel_dpll_id i;
-   int max = dev_priv->num_shared_dpll;
-
-   if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv))
-   /* Do not consider SPLL */
-   max = 2;
 
shared_dpll = 
intel_atomic_get_shared_dpll_state(crtc_state->base.state);
 
-   for (i = 0; i < max; i++) {
+   for (i = range_min; i <= range_max; i++) {
pll = _priv->shared_dplls[i];
 
/* Only want to check enabled timings first */
@@ -247,49 +201,33 @@ intel_find_shared_dpll(struct intel_crtc *crtc,
  crtc->base.base.id, pll->name,
  shared_dpll[i].crtc_mask,
  pll->active);
-   return i;
+   return pll;
}
}
 
/* Ok no matching timings, maybe there's a free one? */
-   for (i = 0; i < dev_priv->num_shared_dpll; i++) {
+   for (i = range_min; i <= range_max; i++) {
pll = _priv->shared_dplls[i];
if (shared_dpll[i].crtc_mask == 0) {
DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
  

[Intel-gfx] [PATCH 12/13] drm/i915: Manage HSW/BDW LCPLLs with the shared dpll interface

[Ander Conselvan de Oliveira]

Manage the LCPLLs used with DisplayPort, so that all the HSW/BDW DPLLs
are managed by the shared dpll code.

Signed-off-by: Ander Conselvan de Oliveira 

---
 drivers/gpu/drm/i915/intel_ddi.c  | 18 
 drivers/gpu/drm/i915/intel_display.c  | 35 
 drivers/gpu/drm/i915/intel_dp.c   | 23 +-
 drivers/gpu/drm/i915/intel_dp_mst.c   |  4 --
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 79 +++
 drivers/gpu/drm/i915/intel_dpll_mgr.h |  5 ++-
 drivers/gpu/drm/i915/intel_drv.h  |  1 -
 7 files changed, 110 insertions(+), 55 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index ad7888c..3cb9f36 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -992,17 +992,13 @@ hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
 {
struct intel_shared_dpll *pll;
 
-   if (intel_encoder->type == INTEL_OUTPUT_HDMI ||
-   intel_encoder->type == INTEL_OUTPUT_ANALOG) {
-   pll = intel_get_shared_dpll(intel_crtc, crtc_state,
-   intel_encoder);
-   if (!pll)
-   DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
-pipe_name(intel_crtc->pipe));
-   return pll;
-   } else {
-   return true;
-   }
+   pll = intel_get_shared_dpll(intel_crtc, crtc_state,
+   intel_encoder);
+   if (!pll)
+   DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
+pipe_name(intel_crtc->pipe));
+
+   return pll;
 }
 
 static bool
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 17f4f34..9ca31e2 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9660,13 +9660,19 @@ static void haswell_get_ddi_pll(struct drm_i915_private 
*dev_priv,
case PORT_CLK_SEL_SPLL:
id = DPLL_ID_SPLL;
break;
+   case PORT_CLK_SEL_LCPLL_810:
+   id = DPLL_ID_LCPLL_810;
+   break;
+   case PORT_CLK_SEL_LCPLL_1350:
+   id = DPLL_ID_LCPLL_1350;
+   break;
+   case PORT_CLK_SEL_LCPLL_2700:
+   id = DPLL_ID_LCPLL_2700;
+   break;
default:
MISSING_CASE(pipe_config->ddi_pll_sel);
/* fall through */
case PORT_CLK_SEL_NONE:
-   case PORT_CLK_SEL_LCPLL_810:
-   case PORT_CLK_SEL_LCPLL_1350:
-   case PORT_CLK_SEL_LCPLL_2700:
return;
}
 
@@ -9695,8 +9701,17 @@ static void haswell_get_ddi_port_state(struct intel_crtc 
*crtc,
 
pll = pipe_config->shared_dpll;
if (pll) {
-   WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
-_config->dpll_hw_state));
+   bool enabled =
+   pll->funcs.get_hw_state(dev_priv, pll,
+   _config->dpll_hw_state);
+
+   /*
+* We keep LCPLL always enabled but its ->get_hw_state() return
+* value relies on the crtc_mask to please the state checker.
+* That may not have been set yet, so just ignore the value for
+* those PLLs, since it shouldn't really matter.
+*/
+   WARN_ON(pll->id < DPLL_ID_LCPLL_810 && !enabled);
}
 
/*
@@ -15466,8 +15481,6 @@ static void intel_modeset_readout_hw_state(struct 
drm_device *dev)
for (i = 0; i < dev_priv->num_shared_dpll; i++) {
struct intel_shared_dpll *pll = _priv->shared_dplls[i];
 
-   pll->on = pll->funcs.get_hw_state(dev_priv, pll,
- >config.hw_state);
pll->active = 0;
pll->config.crtc_mask = 0;
for_each_intel_crtc(dev, crtc) {
@@ -15477,6 +15490,14 @@ static void intel_modeset_readout_hw_state(struct 
drm_device *dev)
}
}
 
+   /*
+*  Set this after updating crtc_mask because of LCPLL in HSW,
+*  since that's always kept enabled and the return value of
+*  get_hw_state() depends on that mask.
+*/
+   pll->on = pll->funcs.get_hw_state(dev_priv, pll,
+ >config.hw_state);
+
DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
  pll->name, pll->config.crtc_mask, pll->on);
 
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index cbc0659..5be6892 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1275,25 +1275,6 @@ 

[Intel-gfx] [PATCH 06/13] drm/i915: Move shared dpll function prototypes to intel_dpll_mgr.h

[Ander Conselvan de Oliveira]

Move shared dpll function prototype together with other shared dpll
definitions.

Signed-off-by: Ander Conselvan de Oliveira 

---
 drivers/gpu/drm/i915/intel_dpll_mgr.h | 30 ++
 drivers/gpu/drm/i915/intel_drv.h  | 28 
 2 files changed, 30 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h 
b/drivers/gpu/drm/i915/intel_dpll_mgr.h
index a62d1ba..a2ecf80 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h
@@ -26,6 +26,8 @@
 #define _INTEL_DPLL_MGR_H_
 
 struct drm_i915_private;
+struct intel_crtc;
+struct intel_crtc_state;
 
 enum intel_dpll_id {
DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
@@ -102,5 +104,33 @@ struct intel_shared_dpll {
 #define SKL_DPLL2 2
 #define SKL_DPLL3 3
 
+/* shared dpll functions */
+struct intel_shared_dpll *
+intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv,
+   enum intel_dpll_id id);
+enum intel_dpll_id
+intel_get_shared_dpll_id(struct drm_i915_private *dev_priv,
+struct intel_shared_dpll *pll);
+void
+intel_shared_dpll_config_get(struct intel_shared_dpll_config *config,
+struct intel_shared_dpll *pll,
+struct intel_crtc *crtc);
+void
+intel_shared_dpll_config_put(struct intel_shared_dpll_config *config,
+struct intel_shared_dpll *pll,
+struct intel_crtc *crtc);
+void assert_shared_dpll(struct drm_i915_private *dev_priv,
+   struct intel_shared_dpll *pll,
+   bool state);
+#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
+#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
+struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
+   struct intel_crtc_state *state);
+void intel_prepare_shared_dpll(struct intel_crtc *crtc);
+void intel_enable_shared_dpll(struct intel_crtc *crtc);
+void intel_disable_shared_dpll(struct intel_crtc *crtc);
+void intel_shared_dpll_commit(struct drm_atomic_state *state);
+void intel_shared_dpll_init(struct drm_device *dev);
+
 
 #endif /* _INTEL_DPLL_MGR_H_ */
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 0a929c1..c9e5030 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1146,34 +1146,6 @@ void intel_create_rotation_property(struct drm_device 
*dev,
 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
enum pipe pipe);
 
-/* shared dpll functions */
-struct intel_shared_dpll *
-intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv,
-   enum intel_dpll_id id);
-enum intel_dpll_id
-intel_get_shared_dpll_id(struct drm_i915_private *dev_priv,
-struct intel_shared_dpll *pll);
-void
-intel_shared_dpll_config_get(struct intel_shared_dpll_config *config,
-struct intel_shared_dpll *pll,
-struct intel_crtc *crtc);
-void
-intel_shared_dpll_config_put(struct intel_shared_dpll_config *config,
-struct intel_shared_dpll *pll,
-struct intel_crtc *crtc);
-void assert_shared_dpll(struct drm_i915_private *dev_priv,
-   struct intel_shared_dpll *pll,
-   bool state);
-#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
-#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
-struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
-   struct intel_crtc_state *state);
-void intel_prepare_shared_dpll(struct intel_crtc *crtc);
-void intel_enable_shared_dpll(struct intel_crtc *crtc);
-void intel_disable_shared_dpll(struct intel_crtc *crtc);
-void intel_shared_dpll_commit(struct drm_atomic_state *state);
-void intel_shared_dpll_init(struct drm_device *dev);
-
 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
 const struct dpll *dpll);
 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
-- 
2.4.3

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 13/13] drm/i915: Make SKL/KBL DPLL0 managed by the shared dpll code

[Ander Conselvan de Oliveira]

Include DPLL0 in the managed dplls for SKL/KBL. While it has to be kept
enabled because of it driving CDCLK, it is better to special case that
inside the DPLL code than in the higher level.

Signed-off-by: Ander Conselvan de Oliveira 


---
I wasn't able to test this patch. Would really appreciate a tested by
from someone.

---
 drivers/gpu/drm/i915/intel_ddi.c  |  21 --
 drivers/gpu/drm/i915/intel_dp.c   |  52 +-
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 126 +++---
 drivers/gpu/drm/i915/intel_dpll_mgr.h |   7 +-
 4 files changed, 107 insertions(+), 99 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 3cb9f36..8ef4d2e 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1008,9 +1008,6 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
 {
struct intel_shared_dpll *pll;
 
-   if (intel_encoder->type == INTEL_OUTPUT_EDP)
-   return true;
-
pll = intel_get_shared_dpll(intel_crtc, crtc_state, intel_encoder);
if (pll == NULL) {
DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
@@ -1570,24 +1567,6 @@ void intel_ddi_clk_select(struct intel_encoder *encoder,
uint32_t dpll = pipe_config->ddi_pll_sel;
uint32_t val;
 
-   /*
-* DPLL0 is used for eDP and is the only "private" DPLL (as
-* opposed to shared) on SKL
-*/
-   if (encoder->type == INTEL_OUTPUT_EDP) {
-   WARN_ON(dpll != SKL_DPLL0);
-
-   val = I915_READ(DPLL_CTRL1);
-
-   val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) |
-DPLL_CTRL1_SSC(dpll) |
-DPLL_CTRL1_LINK_RATE_MASK(dpll));
-   val |= pipe_config->dpll_hw_state.ctrl1 << (dpll * 6);
-
-   I915_WRITE(DPLL_CTRL1, val);
-   POSTING_READ(DPLL_CTRL1);
-   }
-
/* DDI -> PLL mapping  */
val = I915_READ(DPLL_CTRL2);
 
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 5be6892..9fef877 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1229,52 +1229,6 @@ intel_dp_connector_unregister(struct intel_connector 
*intel_connector)
intel_connector_unregister(intel_connector);
 }
 
-static void
-skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
-{
-   u32 ctrl1;
-
-   memset(_config->dpll_hw_state, 0,
-  sizeof(pipe_config->dpll_hw_state));
-
-   pipe_config->ddi_pll_sel = SKL_DPLL0;
-   pipe_config->dpll_hw_state.cfgcr1 = 0;
-   pipe_config->dpll_hw_state.cfgcr2 = 0;
-
-   ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
-   switch (pipe_config->port_clock / 2) {
-   case 81000:
-   ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
- SKL_DPLL0);
-   break;
-   case 135000:
-   ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350,
- SKL_DPLL0);
-   break;
-   case 27:
-   ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700,
- SKL_DPLL0);
-   break;
-   case 162000:
-   ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620,
- SKL_DPLL0);
-   break;
-   /* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which
-   results in CDCLK change. Need to handle the change of CDCLK by
-   disabling pipes and re-enabling them */
-   case 108000:
-   ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
- SKL_DPLL0);
-   break;
-   case 216000:
-   ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160,
- SKL_DPLL0);
-   break;
-
-   }
-   pipe_config->dpll_hw_state.ctrl1 = ctrl1;
-}
-
 static int
 intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
 {
@@ -1632,11 +1586,7 @@ found:
_config->dp_m2_n2);
}
 
-   if ((IS_SKYLAKE(dev)  || IS_KABYLAKE(dev)) && is_edp(intel_dp))
-   skl_edp_set_pll_config(pipe_config);
-   else if (IS_BROXTON(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev))
-   /* handled in ddi */;
-   else
+   if (!HAS_DDI(dev))
intel_dp_set_clock(encoder, pipe_config);
 
return true;
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c 
b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 78ce487..c695a28 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ 

[Intel-gfx] [PATCH 07/13] drm/i915: Use a table to initilize shared dplls

[Ander Conselvan de Oliveira]

Use a table to store the per-platform shared dpll information in one
place. This way, there is no need for platform specific init funtions.

Signed-off-by: Ander Conselvan de Oliveira 

---
 drivers/gpu/drm/i915/intel_display.c  |  16 +--
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 189 --
 drivers/gpu/drm/i915/intel_dpll_mgr.h |  22 ++--
 3 files changed, 108 insertions(+), 119 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index e723323..133b6b7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9148,8 +9148,8 @@ static bool ironlake_get_pipe_config(struct intel_crtc 
*crtc,
intel_get_shared_dpll_by_id(dev_priv, pll_id);
pll = pipe_config->shared_dpll;
 
-   WARN_ON(!pll->get_hw_state(dev_priv, pll,
-  _config->dpll_hw_state));
+   WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
+_config->dpll_hw_state));
 
tmp = pipe_config->dpll_hw_state.dpll;
pipe_config->pixel_multiplier =
@@ -9695,8 +9695,8 @@ static void haswell_get_ddi_port_state(struct intel_crtc 
*crtc,
 
pll = pipe_config->shared_dpll;
if (pll) {
-   WARN_ON(!pll->get_hw_state(dev_priv, pll,
-  _config->dpll_hw_state));
+   WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
+_config->dpll_hw_state));
}
 
/*
@@ -12728,7 +12728,7 @@ check_shared_dpll_state(struct drm_device *dev)
 
DRM_DEBUG_KMS("%s\n", pll->name);
 
-   active = pll->get_hw_state(dev_priv, pll, _hw_state);
+   active = pll->funcs.get_hw_state(dev_priv, pll, _hw_state);
 
I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
 "more active pll users than references: %i vs %i\n",
@@ -15466,8 +15466,8 @@ static void intel_modeset_readout_hw_state(struct 
drm_device *dev)
for (i = 0; i < dev_priv->num_shared_dpll; i++) {
struct intel_shared_dpll *pll = _priv->shared_dplls[i];
 
-   pll->on = pll->get_hw_state(dev_priv, pll,
-   >config.hw_state);
+   pll->on = pll->funcs.get_hw_state(dev_priv, pll,
+ >config.hw_state);
pll->active = 0;
pll->config.crtc_mask = 0;
for_each_intel_crtc(dev, crtc) {
@@ -15602,7 +15602,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev)
 
DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", 
pll->name);
 
-   pll->disable(dev_priv, pll);
+   pll->funcs.disable(dev_priv, pll);
pll->on = false;
}
 
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c 
b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 889ceed..e88dc46 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -74,7 +74,7 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv,
if (WARN(!pll, "asserting DPLL %s with no DPLL\n", onoff(state)))
return;
 
-   cur_state = pll->get_hw_state(dev_priv, pll, _state);
+   cur_state = pll->funcs.get_hw_state(dev_priv, pll, _state);
I915_STATE_WARN(cur_state != state,
 "%s assertion failure (expected %s, current %s)\n",
pll->name, onoff(state), onoff(cur_state));
@@ -95,7 +95,7 @@ void intel_prepare_shared_dpll(struct intel_crtc *crtc)
WARN_ON(pll->on);
assert_shared_dpll_disabled(dev_priv, pll);
 
-   pll->mode_set(dev_priv, pll);
+   pll->funcs.mode_set(dev_priv, pll);
}
 }
 
@@ -133,7 +133,7 @@ void intel_enable_shared_dpll(struct intel_crtc *crtc)
intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
 
DRM_DEBUG_KMS("enabling %s\n", pll->name);
-   pll->enable(dev_priv, pll);
+   pll->funcs.enable(dev_priv, pll);
pll->on = true;
 }
 
@@ -168,7 +168,7 @@ void intel_disable_shared_dpll(struct intel_crtc *crtc)
return;
 
DRM_DEBUG_KMS("disabling %s\n", pll->name);
-   pll->disable(dev_priv, pll);
+   pll->funcs.disable(dev_priv, pll);
pll->on = false;
 
intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
@@ -398,29 +398,13 @@ static void ibx_pch_dpll_disable(struct drm_i915_private 
*dev_priv,
udelay(200);
 }
 
-static char *ibx_pch_dpll_names[] = {
-   "PCH DPLL A",
-   "PCH DPLL B",
+static const struct intel_shared_dpll_funcs ibx_pch_dpll_funcs = {
+   .mode_set = ibx_pch_dpll_mode_set,
+   .enable = ibx_pch_dpll_enable,
+   .disable = 

[Intel-gfx] [PATCH 01/13] drm/i915: Move shared dpll code to a new file

[Ander Conselvan de Oliveira]

Create the new file intel_dpll_mgr.c and move the shared dpll code to
it. Follow up patches that reorganize pll handling will move more code
there and tweak the interface.

No functional changes.

Signed-off-by: Ander Conselvan de Oliveira 

---
 drivers/gpu/drm/i915/Makefile |   1 +
 drivers/gpu/drm/i915/intel_display.c  | 348 +---
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 368 ++
 drivers/gpu/drm/i915/intel_drv.h  |   8 +
 4 files changed, 379 insertions(+), 346 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_dpll_mgr.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 0851de07..5558a03 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -56,6 +56,7 @@ i915-y += intel_audio.o \
  intel_atomic_plane.o \
  intel_bios.o \
  intel_display.o \
+ intel_dpll_mgr.o \
  intel_fbc.o \
  intel_fifo_underrun.o \
  intel_frontbuffer.o \
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 8b7b8b6..df49324 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1182,34 +1182,6 @@ static void assert_dsi_pll(struct drm_i915_private 
*dev_priv, bool state)
 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
 
-struct intel_shared_dpll *
-intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
-{
-   struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
-
-   if (crtc->config->shared_dpll < 0)
-   return NULL;
-
-   return _priv->shared_dplls[crtc->config->shared_dpll];
-}
-
-/* For ILK+ */
-void assert_shared_dpll(struct drm_i915_private *dev_priv,
-   struct intel_shared_dpll *pll,
-   bool state)
-{
-   bool cur_state;
-   struct intel_dpll_hw_state hw_state;
-
-   if (WARN(!pll, "asserting DPLL %s with no DPLL\n", onoff(state)))
-   return;
-
-   cur_state = pll->get_hw_state(dev_priv, pll, _state);
-   I915_STATE_WARN(cur_state != state,
-"%s assertion failure (expected %s, current %s)\n",
-   pll->name, onoff(state), onoff(cur_state));
-}
-
 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
  enum pipe pipe, bool state)
 {
@@ -1446,21 +1418,8 @@ static void assert_vblank_disabled(struct drm_crtc *crtc)
drm_crtc_vblank_put(crtc);
 }
 
-static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
-{
-   u32 val;
-   bool enabled;
-
-   I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || 
HAS_PCH_CPT(dev_priv->dev)));
-
-   val = I915_READ(PCH_DREF_CONTROL);
-   enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
-   DREF_SUPERSPREAD_SOURCE_MASK));
-   I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be 
active but is disabled\n");
-}
-
-static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
-  enum pipe pipe)
+void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
+   enum pipe pipe)
 {
u32 val;
bool enabled;
@@ -1856,100 +1815,6 @@ void vlv_wait_port_ready(struct drm_i915_private 
*dev_priv,
 port_name(dport->port), I915_READ(dpll_reg) & port_mask, 
expected_mask);
 }
 
-static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
-{
-   struct drm_device *dev = crtc->base.dev;
-   struct drm_i915_private *dev_priv = dev->dev_private;
-   struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
-
-   if (WARN_ON(pll == NULL))
-   return;
-
-   WARN_ON(!pll->config.crtc_mask);
-   if (pll->active == 0) {
-   DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
-   WARN_ON(pll->on);
-   assert_shared_dpll_disabled(dev_priv, pll);
-
-   pll->mode_set(dev_priv, pll);
-   }
-}
-
-/**
- * intel_enable_shared_dpll - enable PCH PLL
- * @dev_priv: i915 private structure
- * @pipe: pipe PLL to enable
- *
- * The PCH PLL needs to be enabled before the PCH transcoder, since it
- * drives the transcoder clock.
- */
-static void intel_enable_shared_dpll(struct intel_crtc *crtc)
-{
-   struct drm_device *dev = crtc->base.dev;
-   struct drm_i915_private *dev_priv = dev->dev_private;
-   struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
-
-   if (WARN_ON(pll == NULL))
-   return;
-
-   if (WARN_ON(pll->config.crtc_mask == 0))
-   return;
-
-   DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
- pll->name, pll->active, pll->on,
-

[Intel-gfx] [PATCH 03/13] drm/i915: Split intel_get_shared_dpll() into smaller functions

[Ander Conselvan de Oliveira]

Make the code neater by splitting the code for platforms with fixed PLL
to their own functions and splitting the logic for finding a shareable
or unused pll from the logic for setting it up.

Signed-off-by: Ander Conselvan de Oliveira 

---
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 109 +++---
 1 file changed, 74 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c 
b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 6be0cd0..11effe3 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -145,52 +145,65 @@ void intel_disable_shared_dpll(struct intel_crtc *crtc)
intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
 }
 
-struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
-   struct intel_crtc_state 
*crtc_state)
+static enum intel_dpll_id
+ibx_get_fixed_dpll(struct intel_crtc *crtc,
+  struct intel_crtc_state *crtc_state)
 {
-   struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
+   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_shared_dpll *pll;
-   struct intel_shared_dpll_config *shared_dpll;
enum intel_dpll_id i;
-   int max = dev_priv->num_shared_dpll;
 
-   shared_dpll = 
intel_atomic_get_shared_dpll_state(crtc_state->base.state);
+   /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
+   i = (enum intel_dpll_id) crtc->pipe;
+   pll = _priv->shared_dplls[i];
 
-   if (HAS_PCH_IBX(dev_priv->dev)) {
-   /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
-   i = (enum intel_dpll_id) crtc->pipe;
-   pll = _priv->shared_dplls[i];
+   DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
+ crtc->base.base.id, pll->name);
 
-   DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
- crtc->base.base.id, pll->name);
+   return i;
+}
 
-   WARN_ON(shared_dpll[i].crtc_mask);
+static enum intel_dpll_id
+bxt_get_fixed_dpll(struct intel_crtc *crtc,
+  struct intel_crtc_state *crtc_state)
+{
+   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+   struct intel_encoder *encoder;
+   struct intel_digital_port *intel_dig_port;
+   struct intel_shared_dpll *pll;
+   enum intel_dpll_id i;
 
-   goto found;
-   }
+   /* PLL is attached to port in bxt */
+   encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
+   if (WARN_ON(!encoder))
+   return DPLL_ID_PRIVATE;
 
-   if (IS_BROXTON(dev_priv->dev)) {
-   /* PLL is attached to port in bxt */
-   struct intel_encoder *encoder;
-   struct intel_digital_port *intel_dig_port;
+   intel_dig_port = enc_to_dig_port(>base);
+   /* 1:1 mapping between ports and PLLs */
+   i = (enum intel_dpll_id)intel_dig_port->port;
+   pll = _priv->shared_dplls[i];
+   DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
+   crtc->base.base.id, pll->name);
 
-   encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
-   if (WARN_ON(!encoder))
-   return NULL;
+   return i;
+}
 
-   intel_dig_port = enc_to_dig_port(>base);
-   /* 1:1 mapping between ports and PLLs */
-   i = (enum intel_dpll_id)intel_dig_port->port;
-   pll = _priv->shared_dplls[i];
-   DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
-   crtc->base.base.id, pll->name);
-   WARN_ON(shared_dpll[i].crtc_mask);
+static enum intel_dpll_id
+intel_find_shared_dpll(struct intel_crtc *crtc,
+  struct intel_crtc_state *crtc_state)
+{
+   struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
+   struct intel_shared_dpll *pll;
+   struct intel_shared_dpll_config *shared_dpll;
+   enum intel_dpll_id i;
+   int max = dev_priv->num_shared_dpll;
 
-   goto found;
-   } else if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv))
+   if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv))
/* Do not consider SPLL */
max = 2;
 
+   shared_dpll = 
intel_atomic_get_shared_dpll_state(crtc_state->base.state);
+
for (i = 0; i < max; i++) {
pll = _priv->shared_dplls[i];
 
@@ -205,7 +218,7 @@ struct intel_shared_dpll *intel_get_shared_dpll(struct 
intel_crtc *crtc,
  crtc->base.base.id, pll->name,
  shared_dpll[i].crtc_mask,
  pll->active);
-   goto found;
+   return i;
}
}
 
@@ -215,13 +228,39 @@ struct intel_shared_dpll 

[Intel-gfx] [PATCH 00/13] Shared pll improvements

[Ander Conselvan de Oliveira]

Hi,

This patch series attempts to improve the shared pll interfaces. The
idea is to hide the details of which PLL to use behind the call to
intel_get_shared_dpll(), instead of having the weird mix currently
used with DDI platforms. I plan to keep working on the interfaces to
make it usuable by other platforms too, but that will come in a later
series.

With these patches, all DPLLS used with DDI are managed, including
LCPLL in HSW/BDW and DPLL0 in SKL/KBL (although I wasn't able to test
the latter).

The avid reviewer might notice that this series leaves all the
*_ddi_pll_select() function looking pretty much the same. I have
a clean up lined up for that, but it involves removing the
haswell_crtc_compute_clock() function and I haven't yet figured out
how/where to release the used dplls.

So this is still work in progress, but it is probably better to get
feedback now before there are even more patches.

Thanks,
Ander

Ander Conselvan de Oliveira (13):
  drm/i915: Move shared dpll code to a new file
  drm/i915: Move ddi shared dpll code to intel_dpll_mgr.c
  drm/i915: Split intel_get_shared_dpll() into smaller functions
  drm/i915: Store a direct pointer to shared dpll in intel_crtc_state
  drm/i915: Move shared dpll struct definitions to separate header file
  drm/i915: Move shared dpll function prototypes to intel_dpll_mgr.h
  drm/i915: Use a table to initilize shared dplls
  drm/i915: Refactor platform specifics out of intel_get_shared_dpll()
  drm/i915: Move HSW/BDW pll selection logic to intel_dpll_mgr.c
  drm/i915: Move SKL/KLB pll selection logic to intel_dpll_mgr.c
  drm/i915: Move BXT pll configuration logic to intel_dpll_mgr.c
  drm/i915: Manage HSW/BDW LCPLLs with the shared dpll interface
  drm/i915: Make SKL/KBL DPLL0 managed by the shared dpll code

 drivers/gpu/drm/i915/Makefile |1 +
 drivers/gpu/drm/i915/i915_drv.h   |   77 +-
 drivers/gpu/drm/i915/intel_crt.c  |8 +-
 drivers/gpu/drm/i915/intel_ddi.c  | 1200 +-
 drivers/gpu/drm/i915/intel_display.c  |  493 ++---
 drivers/gpu/drm/i915/intel_dp.c   |   73 +-
 drivers/gpu/drm/i915/intel_dp_mst.c   |4 -
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 1789 +
 drivers/gpu/drm/i915/intel_dpll_mgr.h |  157 +++
 drivers/gpu/drm/i915/intel_drv.h  |   17 +-
 drivers/gpu/drm/i915/intel_lvds.c |2 +-
 11 files changed, 2068 insertions(+), 1753 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_dpll_mgr.c
 create mode 100644 drivers/gpu/drm/i915/intel_dpll_mgr.h

-- 
2.4.3

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 02/13] drm/i915: Move ddi shared dpll code to intel_dpll_mgr.c

[Ander Conselvan de Oliveira]

No functional changes.

Signed-off-by: Ander Conselvan de Oliveira 

---
 drivers/gpu/drm/i915/intel_ddi.c  | 472 --
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 472 ++
 drivers/gpu/drm/i915/intel_drv.h  |   1 -
 3 files changed, 472 insertions(+), 473 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 21a9b83..eb6b55c 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2430,235 +2430,6 @@ static void intel_disable_ddi(struct intel_encoder 
*intel_encoder)
}
 }
 
-static void hsw_ddi_wrpll_enable(struct drm_i915_private *dev_priv,
-  struct intel_shared_dpll *pll)
-{
-   I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);
-   POSTING_READ(WRPLL_CTL(pll->id));
-   udelay(20);
-}
-
-static void hsw_ddi_spll_enable(struct drm_i915_private *dev_priv,
-   struct intel_shared_dpll *pll)
-{
-   I915_WRITE(SPLL_CTL, pll->config.hw_state.spll);
-   POSTING_READ(SPLL_CTL);
-   udelay(20);
-}
-
-static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv,
- struct intel_shared_dpll *pll)
-{
-   uint32_t val;
-
-   val = I915_READ(WRPLL_CTL(pll->id));
-   I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
-   POSTING_READ(WRPLL_CTL(pll->id));
-}
-
-static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv,
-struct intel_shared_dpll *pll)
-{
-   uint32_t val;
-
-   val = I915_READ(SPLL_CTL);
-   I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
-   POSTING_READ(SPLL_CTL);
-}
-
-static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv,
-  struct intel_shared_dpll *pll,
-  struct intel_dpll_hw_state *hw_state)
-{
-   uint32_t val;
-
-   if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
-   return false;
-
-   val = I915_READ(WRPLL_CTL(pll->id));
-   hw_state->wrpll = val;
-
-   intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
-
-   return val & WRPLL_PLL_ENABLE;
-}
-
-static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *dev_priv,
- struct intel_shared_dpll *pll,
- struct intel_dpll_hw_state *hw_state)
-{
-   uint32_t val;
-
-   if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
-   return false;
-
-   val = I915_READ(SPLL_CTL);
-   hw_state->spll = val;
-
-   intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
-
-   return val & SPLL_PLL_ENABLE;
-}
-
-
-static const char * const hsw_ddi_pll_names[] = {
-   "WRPLL 1",
-   "WRPLL 2",
-   "SPLL"
-};
-
-static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv)
-{
-   int i;
-
-   dev_priv->num_shared_dpll = 3;
-
-   for (i = 0; i < 2; i++) {
-   dev_priv->shared_dplls[i].id = i;
-   dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
-   dev_priv->shared_dplls[i].disable = hsw_ddi_wrpll_disable;
-   dev_priv->shared_dplls[i].enable = hsw_ddi_wrpll_enable;
-   dev_priv->shared_dplls[i].get_hw_state =
-   hsw_ddi_wrpll_get_hw_state;
-   }
-
-   /* SPLL is special, but needs to be initialized anyway.. */
-   dev_priv->shared_dplls[i].id = i;
-   dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
-   dev_priv->shared_dplls[i].disable = hsw_ddi_spll_disable;
-   dev_priv->shared_dplls[i].enable = hsw_ddi_spll_enable;
-   dev_priv->shared_dplls[i].get_hw_state = hsw_ddi_spll_get_hw_state;
-
-}
-
-static const char * const skl_ddi_pll_names[] = {
-   "DPLL 1",
-   "DPLL 2",
-   "DPLL 3",
-};
-
-struct skl_dpll_regs {
-   i915_reg_t ctl, cfgcr1, cfgcr2;
-};
-
-/* this array is indexed by the *shared* pll id */
-static const struct skl_dpll_regs skl_dpll_regs[3] = {
-   {
-   /* DPLL 1 */
-   .ctl = LCPLL2_CTL,
-   .cfgcr1 = DPLL_CFGCR1(SKL_DPLL1),
-   .cfgcr2 = DPLL_CFGCR2(SKL_DPLL1),
-   },
-   {
-   /* DPLL 2 */
-   .ctl = WRPLL_CTL(0),
-   .cfgcr1 = DPLL_CFGCR1(SKL_DPLL2),
-   .cfgcr2 = DPLL_CFGCR2(SKL_DPLL2),
-   },
-   {
-   /* DPLL 3 */
-   .ctl = WRPLL_CTL(1),
-   .cfgcr1 = DPLL_CFGCR1(SKL_DPLL3),
-   .cfgcr2 = DPLL_CFGCR2(SKL_DPLL3),
-   },
-};
-
-static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
-  struct intel_shared_dpll *pll)
-{
-   uint32_t val;
-   unsigned int dpll;
-   const struct skl_dpll_regs *regs = 

[Intel-gfx] [PATCH 10/13] drm/i915: Move SKL/KLB pll selection logic to intel_dpll_mgr.c

[Ander Conselvan de Oliveira]

Move the code for selecting plls for SKL/KLB into the shared dpll code,
so that the platform specific details are hidden behind that interface.

Signed-off-by: Ander Conselvan de Oliveira 

---
 drivers/gpu/drm/i915/intel_ddi.c  | 301 +
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 307 +-
 2 files changed, 306 insertions(+), 302 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index e1585a5..8258acd 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1005,311 +1005,15 @@ hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
}
 }
 
-struct skl_wrpll_context {
-   uint64_t min_deviation; /* current minimal deviation */
-   uint64_t central_freq;  /* chosen central freq */
-   uint64_t dco_freq;  /* chosen dco freq */
-   unsigned int p; /* chosen divider */
-};
-
-static void skl_wrpll_context_init(struct skl_wrpll_context *ctx)
-{
-   memset(ctx, 0, sizeof(*ctx));
-
-   ctx->min_deviation = U64_MAX;
-}
-
-/* DCO freq must be within +1%/-6%  of the DCO central freq */
-#define SKL_DCO_MAX_PDEVIATION 100
-#define SKL_DCO_MAX_NDEVIATION 600
-
-static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx,
- uint64_t central_freq,
- uint64_t dco_freq,
- unsigned int divider)
-{
-   uint64_t deviation;
-
-   deviation = div64_u64(1 * abs_diff(dco_freq, central_freq),
- central_freq);
-
-   /* positive deviation */
-   if (dco_freq >= central_freq) {
-   if (deviation < SKL_DCO_MAX_PDEVIATION &&
-   deviation < ctx->min_deviation) {
-   ctx->min_deviation = deviation;
-   ctx->central_freq = central_freq;
-   ctx->dco_freq = dco_freq;
-   ctx->p = divider;
-   }
-   /* negative deviation */
-   } else if (deviation < SKL_DCO_MAX_NDEVIATION &&
-  deviation < ctx->min_deviation) {
-   ctx->min_deviation = deviation;
-   ctx->central_freq = central_freq;
-   ctx->dco_freq = dco_freq;
-   ctx->p = divider;
-   }
-}
-
-static void skl_wrpll_get_multipliers(unsigned int p,
- unsigned int *p0 /* out */,
- unsigned int *p1 /* out */,
- unsigned int *p2 /* out */)
-{
-   /* even dividers */
-   if (p % 2 == 0) {
-   unsigned int half = p / 2;
-
-   if (half == 1 || half == 2 || half == 3 || half == 5) {
-   *p0 = 2;
-   *p1 = 1;
-   *p2 = half;
-   } else if (half % 2 == 0) {
-   *p0 = 2;
-   *p1 = half / 2;
-   *p2 = 2;
-   } else if (half % 3 == 0) {
-   *p0 = 3;
-   *p1 = half / 3;
-   *p2 = 2;
-   } else if (half % 7 == 0) {
-   *p0 = 7;
-   *p1 = half / 7;
-   *p2 = 2;
-   }
-   } else if (p == 3 || p == 9) {  /* 3, 5, 7, 9, 15, 21, 35 */
-   *p0 = 3;
-   *p1 = 1;
-   *p2 = p / 3;
-   } else if (p == 5 || p == 7) {
-   *p0 = p;
-   *p1 = 1;
-   *p2 = 1;
-   } else if (p == 15) {
-   *p0 = 3;
-   *p1 = 1;
-   *p2 = 5;
-   } else if (p == 21) {
-   *p0 = 7;
-   *p1 = 1;
-   *p2 = 3;
-   } else if (p == 35) {
-   *p0 = 7;
-   *p1 = 1;
-   *p2 = 5;
-   }
-}
-
-struct skl_wrpll_params {
-   uint32_tdco_fraction;
-   uint32_tdco_integer;
-   uint32_tqdiv_ratio;
-   uint32_tqdiv_mode;
-   uint32_tkdiv;
-   uint32_tpdiv;
-   uint32_tcentral_freq;
-};
-
-static void skl_wrpll_params_populate(struct skl_wrpll_params *params,
- uint64_t afe_clock,
- uint64_t central_freq,
- uint32_t p0, uint32_t p1, uint32_t p2)
-{
-   uint64_t dco_freq;
-
-   switch (central_freq) {
-   case 96ULL:
-   params->central_freq = 0;
-   break;
-   case 90ULL:
-   params->central_freq = 1;
-   break;
-   case 84ULL:
-   params->central_freq = 3;
-   }
-
-   switch (p0) {
-   case 1:
-   params->pdiv = 0;
-   break;

[Intel-gfx] [PATCH 09/13] drm/i915: Move HSW/BDW pll selection logic to intel_dpll_mgr.c

[Ander Conselvan de Oliveira]

Move the code for selecting and configuring HSW/BDW DDI PLLs into the
shared dpll infrastructure. With this most of the PLL selection logic
for those platforms is in one place. DisplayPort is handled separately,
but that should be fixed on a follow up patch. It also allows a small
clean up of the SPLL logic.

Signed-off-by: Ander Conselvan de Oliveira 

---
 drivers/gpu/drm/i915/intel_crt.c  |   8 +-
 drivers/gpu/drm/i915/intel_ddi.c  | 271 ++-
 drivers/gpu/drm/i915/intel_display.c  |   2 +-
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 295 --
 drivers/gpu/drm/i915/intel_dpll_mgr.h |  13 +-
 5 files changed, 307 insertions(+), 282 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 505fc5c..6353857 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -261,15 +261,9 @@ static bool intel_crt_compute_config(struct intel_encoder 
*encoder,
pipe_config->pipe_bpp = 24;
 
/* FDI must always be 2.7 GHz */
-   if (HAS_DDI(dev)) {
-   pipe_config->ddi_pll_sel = PORT_CLK_SEL_SPLL;
+   if (HAS_DDI(dev))
pipe_config->port_clock = 135000 * 2;
 
-   pipe_config->dpll_hw_state.wrpll = 0;
-   pipe_config->dpll_hw_state.spll =
-   SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC;
-   }
-
return true;
 }
 
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index a2b33d0..e1585a5 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -724,160 +724,6 @@ intel_ddi_get_crtc_new_encoder(struct intel_crtc_state 
*crtc_state)
 }
 
 #define LC_FREQ 2700
-#define LC_FREQ_2K U64_C(LC_FREQ * 2000)
-
-#define P_MIN 2
-#define P_MAX 64
-#define P_INC 2
-
-/* Constraints for PLL good behavior */
-#define REF_MIN 48
-#define REF_MAX 400
-#define VCO_MIN 2400
-#define VCO_MAX 4800
-
-#define abs_diff(a, b) ({  \
-   typeof(a) __a = (a);\
-   typeof(b) __b = (b);\
-   (void) (&__a == &__b);  \
-   __a > __b ? (__a - __b) : (__b - __a); })
-
-struct hsw_wrpll_rnp {
-   unsigned p, n2, r2;
-};
-
-static unsigned hsw_wrpll_get_budget_for_freq(int clock)
-{
-   unsigned budget;
-
-   switch (clock) {
-   case 25175000:
-   case 2520:
-   case 2700:
-   case 27027000:
-   case 37762500:
-   case 3780:
-   case 4050:
-   case 40541000:
-   case 5400:
-   case 54054000:
-   case 59341000:
-   case 5940:
-   case 7200:
-   case 74176000:
-   case 7425:
-   case 8100:
-   case 81081000:
-   case 89012000:
-   case 8910:
-   case 10800:
-   case 108108000:
-   case 111264000:
-   case 111375000:
-   case 148352000:
-   case 14850:
-   case 16200:
-   case 162162000:
-   case 222525000:
-   case 22275:
-   case 296703000:
-   case 29700:
-   budget = 0;
-   break;
-   case 23350:
-   case 24525:
-   case 24775:
-   case 25325:
-   case 29800:
-   budget = 1500;
-   break;
-   case 169128000:
-   case 16950:
-   case 17950:
-   case 20200:
-   budget = 2000;
-   break;
-   case 25625:
-   case 26250:
-   case 27000:
-   case 27250:
-   case 27375:
-   case 28075:
-   case 28125:
-   case 28600:
-   case 29175:
-   budget = 4000;
-   break;
-   case 26725:
-   case 26850:
-   budget = 5000;
-   break;
-   default:
-   budget = 1000;
-   break;
-   }
-
-   return budget;
-}
-
-static void hsw_wrpll_update_rnp(uint64_t freq2k, unsigned budget,
-unsigned r2, unsigned n2, unsigned p,
-struct hsw_wrpll_rnp *best)
-{
-   uint64_t a, b, c, d, diff, diff_best;
-
-   /* No best (r,n,p) yet */
-   if (best->p == 0) {
-   best->p = p;
-   best->n2 = n2;
-   best->r2 = r2;
-   return;
-   }
-
-   /*
-* Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
-* freq2k.
-*
-* delta = 1e6 *
-* abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
-* freq2k;
-*
-* and we would like delta <= budget.
-*
-* If the discrepancy is above the PPM-based budget, always prefer to
-* improve upon the previous solution.  However, if you're within the
-* budget, try to maximize Ref * VCO, 

[Intel-gfx] [PATCH 04/13] drm/i915: Store a direct pointer to shared dpll in intel_crtc_state

[Ander Conselvan de Oliveira]

Change the type of intel_crtc_state->shared_dpll to be a pointer to a
shared dpll. With this there is no need to first convert the id stored
in the crtc state to a pointer in order to use it. It does introduce a
bit of hassle on doing the opposite.

The long term objective is to hide details about dpll ids behind the
shared dpll interface.

Signed-off-by: Ander Conselvan de Oliveira 

---
 drivers/gpu/drm/i915/intel_ddi.c  |   4 +-
 drivers/gpu/drm/i915/intel_display.c  | 108 ++
 drivers/gpu/drm/i915/intel_dpll_mgr.c |  51 
 drivers/gpu/drm/i915/intel_drv.h  |  19 +-
 drivers/gpu/drm/i915/intel_lvds.c |   2 +-
 5 files changed, 132 insertions(+), 52 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index eb6b55c..a2b33d0 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1209,6 +1209,7 @@ hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
   struct intel_crtc_state *crtc_state,
   struct intel_encoder *intel_encoder)
 {
+   struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
int clock = crtc_state->port_clock;
 
if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
@@ -1244,7 +1245,8 @@ hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
WARN_ON(spll->hw_state.spll != 
crtc_state->dpll_hw_state.spll))
return false;
 
-   crtc_state->shared_dpll = DPLL_ID_SPLL;
+   crtc_state->shared_dpll =
+   intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_SPLL);
spll->hw_state.spll = crtc_state->dpll_hw_state.spll;
spll->crtc_mask |= 1 << intel_crtc->pipe;
}
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index df49324..e723323 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1828,8 +1828,7 @@ static void ironlake_enable_pch_transcoder(struct 
drm_i915_private *dev_priv,
BUG_ON(!HAS_PCH_SPLIT(dev));
 
/* Make sure PCH DPLL is enabled */
-   assert_shared_dpll_enabled(dev_priv,
-  intel_crtc_to_shared_dpll(intel_crtc));
+   assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
 
/* FDI must be feeding us bits for PCH ports */
assert_fdi_tx_enabled(dev_priv, pipe);
@@ -4024,7 +4023,8 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
temp = I915_READ(PCH_DPLL_SEL);
temp |= TRANS_DPLL_ENABLE(pipe);
sel = TRANS_DPLLB_SEL(pipe);
-   if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
+   if (intel_crtc->config->shared_dpll ==
+   intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
temp |= sel;
else
temp &= ~sel;
@@ -4724,7 +4724,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
  false);
 
-   if (intel_crtc_to_shared_dpll(intel_crtc))
+   if (intel_crtc->config->shared_dpll)
intel_enable_shared_dpll(intel_crtc);
 
if (intel_crtc->config->has_dp_encoder)
@@ -7891,7 +7891,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
return false;
 
pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
-   pipe_config->shared_dpll = DPLL_ID_PRIVATE;
+   pipe_config->shared_dpll = NULL;
 
ret = false;
 
@@ -9095,7 +9095,7 @@ static bool ironlake_get_pipe_config(struct intel_crtc 
*crtc,
return false;
 
pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
-   pipe_config->shared_dpll = DPLL_ID_PRIVATE;
+   pipe_config->shared_dpll = NULL;
 
ret = false;
tmp = I915_READ(PIPECONF(crtc->pipe));
@@ -9124,6 +9124,7 @@ static bool ironlake_get_pipe_config(struct intel_crtc 
*crtc,
 
if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
struct intel_shared_dpll *pll;
+   enum intel_dpll_id pll_id;
 
pipe_config->has_pch_encoder = true;
 
@@ -9134,17 +9135,18 @@ static bool ironlake_get_pipe_config(struct intel_crtc 
*crtc,
ironlake_get_fdi_m_n_config(crtc, pipe_config);
 
if (HAS_PCH_IBX(dev_priv->dev)) {
-   pipe_config->shared_dpll =
-   (enum intel_dpll_id) crtc->pipe;
+   pll_id = (enum intel_dpll_id) crtc->pipe;
} else {
tmp = I915_READ(PCH_DPLL_SEL);
if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
-   

[Intel-gfx] [PATCH 11/13] drm/i915: Move BXT pll configuration logic to intel_dpll_mgr.c

[Ander Conselvan de Oliveira]

Move the code for configurating BXT plls into the shared dpll code, so
that the platform specific details are hidden behind that interface.

Signed-off-by: Ander Conselvan de Oliveira 

---
 drivers/gpu/drm/i915/intel_ddi.c  | 141 +-
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 139 +++--
 2 files changed, 134 insertions(+), 146 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 8258acd..ad7888c 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1025,151 +1025,12 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
return true;
 }
 
-/* bxt clock parameters */
-struct bxt_clk_div {
-   int clock;
-   uint32_t p1;
-   uint32_t p2;
-   uint32_t m2_int;
-   uint32_t m2_frac;
-   bool m2_frac_en;
-   uint32_t n;
-};
-
-/* pre-calculated values for DP linkrates */
-static const struct bxt_clk_div bxt_dp_clk_val[] = {
-   {162000, 4, 2, 32, 1677722, 1, 1},
-   {27, 4, 1, 27,   0, 0, 1},
-   {54, 2, 1, 27,   0, 0, 1},
-   {216000, 3, 2, 32, 1677722, 1, 1},
-   {243000, 4, 1, 24, 1258291, 1, 1},
-   {324000, 4, 1, 32, 1677722, 1, 1},
-   {432000, 3, 1, 32, 1677722, 1, 1}
-};
-
 static bool
 bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
   struct intel_crtc_state *crtc_state,
   struct intel_encoder *intel_encoder)
 {
-   struct intel_shared_dpll *pll;
-   struct bxt_clk_div clk_div = {0};
-   int vco = 0;
-   uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
-   uint32_t lanestagger;
-   int clock = crtc_state->port_clock;
-
-   if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
-   intel_clock_t best_clock;
-
-   /* Calculate HDMI div */
-   /*
-* FIXME: tie the following calculation into
-* i9xx_crtc_compute_clock
-*/
-   if (!bxt_find_best_dpll(crtc_state, clock, _clock)) {
-   DRM_DEBUG_DRIVER("no PLL dividers found for clock %d 
pipe %c\n",
-clock, pipe_name(intel_crtc->pipe));
-   return false;
-   }
-
-   clk_div.p1 = best_clock.p1;
-   clk_div.p2 = best_clock.p2;
-   WARN_ON(best_clock.m1 != 2);
-   clk_div.n = best_clock.n;
-   clk_div.m2_int = best_clock.m2 >> 22;
-   clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1);
-   clk_div.m2_frac_en = clk_div.m2_frac != 0;
-
-   vco = best_clock.vco;
-   } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
-   intel_encoder->type == INTEL_OUTPUT_EDP) {
-   int i;
-
-   clk_div = bxt_dp_clk_val[0];
-   for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
-   if (bxt_dp_clk_val[i].clock == clock) {
-   clk_div = bxt_dp_clk_val[i];
-   break;
-   }
-   }
-   vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
-   }
-
-   if (vco >= 620 && vco <= 670) {
-   prop_coef = 4;
-   int_coef = 9;
-   gain_ctl = 3;
-   targ_cnt = 8;
-   } else if ((vco > 540 && vco < 620) ||
-   (vco >= 480 && vco < 540)) {
-   prop_coef = 5;
-   int_coef = 11;
-   gain_ctl = 3;
-   targ_cnt = 9;
-   } else if (vco == 540) {
-   prop_coef = 3;
-   int_coef = 8;
-   gain_ctl = 1;
-   targ_cnt = 9;
-   } else {
-   DRM_ERROR("Invalid VCO\n");
-   return false;
-   }
-
-   memset(_state->dpll_hw_state, 0,
-  sizeof(crtc_state->dpll_hw_state));
-
-   if (clock > 27)
-   lanestagger = 0x18;
-   else if (clock > 135000)
-   lanestagger = 0x0d;
-   else if (clock > 67000)
-   lanestagger = 0x07;
-   else if (clock > 33000)
-   lanestagger = 0x04;
-   else
-   lanestagger = 0x02;
-
-   crtc_state->dpll_hw_state.ebb0 =
-   PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2);
-   crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
-   crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n);
-   crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac;
-
-   if (clk_div.m2_frac_en)
-   crtc_state->dpll_hw_state.pll3 =
-   PORT_PLL_M2_FRAC_ENABLE;
-
-   crtc_state->dpll_hw_state.pll6 =
-   prop_coef | PORT_PLL_INT_COEFF(int_coef);
-   crtc_state->dpll_hw_state.pll6 |=
-   PORT_PLL_GAIN_CTL(gain_ctl);
-
-   

Re: [Intel-gfx] [RFCv2 03/14] drm/i915: Introduce host graphics memory/fence partition for GVT-g

[Joonas Lahtinen]

Hi,

On pe, 2016-02-26 at 13:21 +0800, Zhi Wang wrote:
> 
> On 02/24/16 15:42, Tian, Kevin wrote:
> > 
> > > 
> > > From: Wang, Zhi A
> > > Sent: Tuesday, February 23, 2016 9:23 PM
> > > > 
> > > > > 
> > > > > --- a/drivers/gpu/drm/i915/gvt/gvt.c
> > > > > +++ b/drivers/gpu/drm/i915/gvt/gvt.c
> > > > > @@ -348,6 +348,10 @@ void *gvt_create_pgt_device(struct 
> > > > > drm_i915_private
> > > *dev_priv)
> > > > 
> > > > > 
> > > > >       goto err;
> > > > >       }
> > > > > 
> > > > > + dev_priv->gvt.host_fence_sz = gvt.host_fence_sz;
> > > > > + dev_priv->gvt.host_low_gm_sz_in_mb = gvt.host_low_gm_sz;
> > > > > + dev_priv->gvt.host_high_gm_sz_in_mb = gvt.host_high_gm_sz;
> > > > I'm thinking, could we expose the pgt_device struct (at least
> > > > partially, and then have a PIMPL pattern), to avoid this kind of
> > > > duplication of declarations and unnecessary copies between i915 and
> > > > i915_gvt modules?
> > > > 
> > > > It's little rough that the gvt driver writes to i915_private struct.
> > > > I'd rather see that gvt.host_fence_sz and other variables get sanitized
> > > > and then written to pgt_device (maybe the public part would be
> > > > i915_pgt_device) and used by gvt and i915 code.
> > > > 
> > > > Was this ever considered?
> > > > 
> > > The previous version do something similar like that, both i915 and gvt
> > > reads GVT module kernel parameter but considered that GVT modules could
> > > be configured as "n" in kernel configuration, probably we should let
> > > i915 to store this information and GVT to configure it if GVT is active?
> > Agree with Joonas. We don't need another gvt wrap. Let's just expose
> > pgt_device directly. I believe all other information can be encapsulated
> > under pgt_device.
> > 
> How about this scheme:
> 
> 1. Move GVT kernel parameter into intel_gvt.{h, c}
> 2. Sanitize the partition configuration for host in intel_gvt.c
> 3. If CONFIG_DRM_I915_GVT = y, write the configuration into pgt_device 
> to inform GVT resource allocator ranges owned by host
> 

This sounds fine, if i915 driver wants to know about the gvt driver, it
will read its structure (if gvt was enabled), instead of gvt driver
pushing information to i915.

> > 
> > btw to match other description in the code, is it clear to rename pgt_device
> > to gvt_device?
> > 
> For the name of GVT physical device, if we use "gvt_device", it looks a 
> bit weird when both "gvt_device" and "vgt_device"(vGPU instance) 
> appeared in our code? :( And "pgpu" and "vgpu" also looks weird...
> 

The naming conventions are indeed very confusing, it would help if all
host related stuff was named gvt_* and client vgpu_*

Regards, Joonas

> > 
> > Another minor thing needs Joonas' feedback. Is it usual to capture
> > all module parameters belonging to one feature structurized together
> > (like 'gvt' in this patch), or just to leave them directly exposed?
> > 
> 
> > 
> > Thanks
> > Kevin
> > 
-- 
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Execlists cannot pin a context without the object

[Tvrtko Ursulin]

On 26/02/16 13:13, Tvrtko Ursulin wrote:



On 26/02/16 12:28, Patchwork wrote:

== Series Details ==

Series: drm/i915: Execlists cannot pin a context without the object
URL   : https://patchwork.freedesktop.org/series/3845/
State : failure

== Summary ==

Series 3845v1 drm/i915: Execlists cannot pin a context without the object
http://patchwork.freedesktop.org/api/1.0/series/3845/revisions/1/mbox/

Test drv_module_reload_basic:
 fail   -> PASS   (snb-dellxps)
Test gem_sync:
 Subgroup basic-bsd:
 pass   -> DMESG-FAIL (ilk-hp8440p)


New unrelated: https://bugs.freedesktop.org/show_bug.cgi?id=94307


Test kms_force_connector_basic:
 Subgroup force-load-detect:
 fail   -> DMESG-FAIL (ivb-t430s)


New unrelated: https://bugs.freedesktop.org/show_bug.cgi?id=94306


Test kms_pipe_crc_basic:
 Subgroup suspend-read-crc-pipe-b:
 pass   -> INCOMPLETE (hsw-gt2)


???


Test pm_rpm:
 Subgroup basic-rte:
 pass   -> FAIL   (bdw-nuci7)

bdw-nuci7total:165  pass:153  dwarn:0   dfail:0   fail:1
skip:11
bdw-ultratotal:168  pass:154  dwarn:0   dfail:0   fail:0
skip:14
bsw-nuc-2total:168  pass:137  dwarn:0   dfail:0   fail:1
skip:30
byt-nuc  total:168  pass:143  dwarn:0   dfail:0   fail:0
skip:25
hsw-brixbox  total:168  pass:154  dwarn:0   dfail:0   fail:0
skip:14
hsw-gt2  total:79   pass:75   dwarn:0   dfail:0   fail:0   skip:3
ilk-hp8440p  total:168  pass:117  dwarn:0   dfail:1   fail:1
skip:49
ivb-t430stotal:168  pass:153  dwarn:0   dfail:1   fail:0
skip:14
skl-i7k-2total:168  pass:151  dwarn:1   dfail:0   fail:0
skip:16
snb-dellxps  total:168  pass:145  dwarn:0   dfail:0   fail:1
skip:22
snb-x220ttotal:168  pass:145  dwarn:0   dfail:0   fail:2
skip:21

Results at /archive/results/CI_IGT_test/Patchwork_1482/

3401f93d4f525073bfea774c7d5bb927497effd9 drm-intel-nightly:
2016y-02m-26d-11h-30m-51s UTC integration manifest
0d643e82fdf6ddd553bf220d1319a560a00c5957 drm/i915: Execlists cannot
pin a context without the object


Merged, thanks for the patch!

Regards,

Tvrtko

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Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: Rename vma->*_list to *_link for consistency

[Tvrtko Ursulin]

On 26/02/16 12:10, Tvrtko Ursulin wrote:



On 26/02/16 11:27, Patchwork wrote:

== Series Details ==

Series: series starting with [1/2] drm/i915: Rename vma->*_list to
*_link for consistency
URL   : https://patchwork.freedesktop.org/series/3844/
State : failure

== Summary ==

Series 3844v1 Series without cover letter
http://patchwork.freedesktop.org/api/1.0/series/3844/revisions/1/mbox/

Test drv_hangman:
 Subgroup error-state-basic:
 pass   -> FAIL   (ilk-hp8440p)


Seen before but not filed until now?

https://bugs.freedesktop.org/show_bug.cgi?id=94305


Test kms_flip:
 Subgroup basic-flip-vs-dpms:
 pass   -> DMESG-WARN (ilk-hp8440p) UNSTABLE


Existing unrelated: https://bugs.freedesktop.org/show_bug.cgi?id=93787


 Subgroup basic-flip-vs-wf_vblank:
 pass   -> FAIL   (hsw-gt2)


Existing unrelated: https://bugs.freedesktop.org/show_bug.cgi?id=94294


Test kms_force_connector_basic:
 Subgroup force-edid:
 pass   -> SKIP   (ilk-hp8440p)
Test kms_pipe_crc_basic:
 Subgroup suspend-read-crc-pipe-a:
 pass   -> DMESG-WARN (skl-i7k-2) UNSTABLE


Existing unrelated:  https://bugs.freedesktop.org/show_bug.cgi?id=93294


 Subgroup suspend-read-crc-pipe-b:
 pass   -> SKIP   (hsw-gt2)
 Subgroup suspend-read-crc-pipe-c:
 dmesg-warn -> PASS   (skl-i7k-2) UNSTABLE
Test pm_rpm:
 Subgroup basic-pci-d3-state:
 dmesg-warn -> PASS   (byt-nuc)
 Subgroup basic-rte:
 fail   -> PASS   (bdw-nuci7)
 fail   -> PASS   (bdw-ultra)

bdw-nuci7total:165  pass:154  dwarn:0   dfail:0   fail:0
skip:11
bdw-ultratotal:168  pass:154  dwarn:0   dfail:0   fail:0
skip:14
bsw-nuc-2total:168  pass:137  dwarn:0   dfail:0   fail:1
skip:30
byt-nuc  total:168  pass:143  dwarn:0   dfail:0   fail:0
skip:25
hsw-brixbox  total:168  pass:154  dwarn:0   dfail:0   fail:0
skip:14
hsw-gt2  total:168  pass:155  dwarn:0   dfail:1   fail:1
skip:11
ilk-hp8440p  total:168  pass:115  dwarn:1   dfail:1   fail:1
skip:50
ivb-t430stotal:168  pass:153  dwarn:0   dfail:0   fail:1
skip:14
skl-i7k-2total:168  pass:151  dwarn:1   dfail:0   fail:0
skip:16
snb-dellxps  total:168  pass:145  dwarn:0   dfail:0   fail:1
skip:22
snb-x220ttotal:168  pass:145  dwarn:0   dfail:0   fail:2
skip:21

Results at /archive/results/CI_IGT_test/Patchwork_1481/

38f0cd5314ecb02d15d019631e388d3642275600 drm-intel-nightly:
2016y-02m-25d-15h-33m-53s UTC integration manifest
bd7970fbebc10e807e7d3d99fafec0729bf1907a drm/i915: Reduce the pointer
dance of i915_is_ggtt()
04b7dad1ec23e0bcfc77ce1970d8e6dc9260017a drm/i915: Rename vma->*_list
to *_link for consistency


Merged, thanks for the patches.

Regards,

Tvrtko

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Re: [Intel-gfx] [RFCv2 10/14] drm/i915: update PDPs by condition when submit the LRC context

[Joonas Lahtinen]

Hi,

On to, 2016-02-25 at 15:02 +, Wang, Zhi A wrote:
> 
> -Original Message-
> From: Tian, Kevin 
> Sent: Wednesday, February 24, 2016 4:50 PM
> To: Wang, Zhi A; intel-gfx@lists.freedesktop.org; igv...@lists.01.org
> Cc: Lv, Zhiyuan; Niu, Bing; Song, Jike; daniel.vet...@ffwll.ch; 
> Cowperthwaite, David J; ch...@chris-wilson.co.uk; 
> joonas.lahti...@linux.intel.com
> Subject: RE: [RFCv2 10/14] drm/i915: update PDPs by condition when submit the 
> LRC context
> 
> > 
> > From: Wang, Zhi A
> > Sent: Thursday, February 18, 2016 7:42 PM
> > 
> > Previously the PDPs inside the ring context are updated at:
> > 
> > - When populate a LRC context
> > - Before submitting a LRC context (only for 32 bit PPGTT, as the amount
> > of used PDPs may change)
> > 
> > This patch postpones the PDPs upgrade to submission time, and will update
> > it by condition if the PPGTT is 48b. Under GVT-g, one GVT context will be
> > used by different guest, the PPGTT instance related to the context might
> > be changed before the submission time. And this patch gives GVT context
> > a chance to load the new PPGTT instance into an initialized context.
> Could you elaborate why we share one GVT context across different guest?
> A natural thought is that we'll create one GVT context per every guest
> context...
> 
> [Zhi] We don't have context creation/destroy notification in guest i915 
> driver.
> Because in our implementation we need an unique context id to anchor the
> relationship between shadow context and guest context, while i915 uses GGTT
> address as context id. In each context pin/unpin, the context id may be 
> changes.

Does not this lead to plenty of unnecessary storing and restoring of
the context parameters?

I would imagine this to destroy performance.

Regards, Joonas

> 
> So it's not necessary to allocate multiple GVT context here. 
> 
> Thanks
> Kevin
-- 
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Execlists cannot pin a context without the object

[Tvrtko Ursulin]

On 26/02/16 12:28, Patchwork wrote:

== Series Details ==

Series: drm/i915: Execlists cannot pin a context without the object
URL   : https://patchwork.freedesktop.org/series/3845/
State : failure

== Summary ==

Series 3845v1 drm/i915: Execlists cannot pin a context without the object
http://patchwork.freedesktop.org/api/1.0/series/3845/revisions/1/mbox/

Test drv_module_reload_basic:
 fail   -> PASS   (snb-dellxps)
Test gem_sync:
 Subgroup basic-bsd:
 pass   -> DMESG-FAIL (ilk-hp8440p)


New unrelated: https://bugs.freedesktop.org/show_bug.cgi?id=94307


Test kms_force_connector_basic:
 Subgroup force-load-detect:
 fail   -> DMESG-FAIL (ivb-t430s)


New unrelated: https://bugs.freedesktop.org/show_bug.cgi?id=94306


Test kms_pipe_crc_basic:
 Subgroup suspend-read-crc-pipe-b:
 pass   -> INCOMPLETE (hsw-gt2)


???


Test pm_rpm:
 Subgroup basic-rte:
 pass   -> FAIL   (bdw-nuci7)

bdw-nuci7total:165  pass:153  dwarn:0   dfail:0   fail:1   skip:11
bdw-ultratotal:168  pass:154  dwarn:0   dfail:0   fail:0   skip:14
bsw-nuc-2total:168  pass:137  dwarn:0   dfail:0   fail:1   skip:30
byt-nuc  total:168  pass:143  dwarn:0   dfail:0   fail:0   skip:25
hsw-brixbox  total:168  pass:154  dwarn:0   dfail:0   fail:0   skip:14
hsw-gt2  total:79   pass:75   dwarn:0   dfail:0   fail:0   skip:3
ilk-hp8440p  total:168  pass:117  dwarn:0   dfail:1   fail:1   skip:49
ivb-t430stotal:168  pass:153  dwarn:0   dfail:1   fail:0   skip:14
skl-i7k-2total:168  pass:151  dwarn:1   dfail:0   fail:0   skip:16
snb-dellxps  total:168  pass:145  dwarn:0   dfail:0   fail:1   skip:22
snb-x220ttotal:168  pass:145  dwarn:0   dfail:0   fail:2   skip:21

Results at /archive/results/CI_IGT_test/Patchwork_1482/

3401f93d4f525073bfea774c7d5bb927497effd9 drm-intel-nightly: 
2016y-02m-26d-11h-30m-51s UTC integration manifest
0d643e82fdf6ddd553bf220d1319a560a00c5957 drm/i915: Execlists cannot pin a 
context without the object




Regards,

Tvrtko
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[Intel-gfx] [PATCH i-g-t v2 3/3] tests/kms_plane: Skip the test when configuration couldn't be applied

[Gabriel Feceoru]

This could happen when the selected pipe cannot be used with the connected
port due do HW constrains.

v2: Apply review comment (Marius)

bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86763
Signed-off-by: Gabriel Feceoru 
---
 tests/kms_plane.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/tests/kms_plane.c b/tests/kms_plane.c
index b7a42c6..4ce3289 100644
--- a/tests/kms_plane.c
+++ b/tests/kms_plane.c
@@ -68,6 +68,7 @@ test_grab_crc(data_t *data, igt_output_t *output, enum pipe 
pipe,
drmModeModeInfo *mode;
igt_plane_t *primary;
char *crc_str;
+   int ret;
 
igt_output_set_pipe(output, pipe);
 
@@ -81,7 +82,8 @@ test_grab_crc(data_t *data, igt_output_t *output, enum pipe 
pipe,
);
igt_plane_set_fb(primary, );
 
-   igt_display_commit(>display);
+   ret = igt_display_try_commit2(>display, COMMIT_LEGACY);
+   igt_skip_on(ret != 0);
 
igt_pipe_crc_collect_crc(data->pipe_crc, crc);
 
-- 
1.9.1

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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Execlists cannot pin a context without the object

[Patchwork]

== Series Details ==

Series: drm/i915: Execlists cannot pin a context without the object
URL   : https://patchwork.freedesktop.org/series/3845/
State : failure

== Summary ==

Series 3845v1 drm/i915: Execlists cannot pin a context without the object
http://patchwork.freedesktop.org/api/1.0/series/3845/revisions/1/mbox/

Test drv_module_reload_basic:
fail   -> PASS   (snb-dellxps)
Test gem_sync:
Subgroup basic-bsd:
pass   -> DMESG-FAIL (ilk-hp8440p)
Test kms_force_connector_basic:
Subgroup force-load-detect:
fail   -> DMESG-FAIL (ivb-t430s)
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass   -> INCOMPLETE (hsw-gt2)
Test pm_rpm:
Subgroup basic-rte:
pass   -> FAIL   (bdw-nuci7)

bdw-nuci7total:165  pass:153  dwarn:0   dfail:0   fail:1   skip:11 
bdw-ultratotal:168  pass:154  dwarn:0   dfail:0   fail:0   skip:14 
bsw-nuc-2total:168  pass:137  dwarn:0   dfail:0   fail:1   skip:30 
byt-nuc  total:168  pass:143  dwarn:0   dfail:0   fail:0   skip:25 
hsw-brixbox  total:168  pass:154  dwarn:0   dfail:0   fail:0   skip:14 
hsw-gt2  total:79   pass:75   dwarn:0   dfail:0   fail:0   skip:3  
ilk-hp8440p  total:168  pass:117  dwarn:0   dfail:1   fail:1   skip:49 
ivb-t430stotal:168  pass:153  dwarn:0   dfail:1   fail:0   skip:14 
skl-i7k-2total:168  pass:151  dwarn:1   dfail:0   fail:0   skip:16 
snb-dellxps  total:168  pass:145  dwarn:0   dfail:0   fail:1   skip:22 
snb-x220ttotal:168  pass:145  dwarn:0   dfail:0   fail:2   skip:21 

Results at /archive/results/CI_IGT_test/Patchwork_1482/

3401f93d4f525073bfea774c7d5bb927497effd9 drm-intel-nightly: 
2016y-02m-26d-11h-30m-51s UTC integration manifest
0d643e82fdf6ddd553bf220d1319a560a00c5957 drm/i915: Execlists cannot pin a 
context without the object

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Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: Rename vma->*_list to *_link for consistency

[Tvrtko Ursulin]

On 26/02/16 11:27, Patchwork wrote:

== Series Details ==

Series: series starting with [1/2] drm/i915: Rename vma->*_list to *_link for 
consistency
URL   : https://patchwork.freedesktop.org/series/3844/
State : failure

== Summary ==

Series 3844v1 Series without cover letter
http://patchwork.freedesktop.org/api/1.0/series/3844/revisions/1/mbox/

Test drv_hangman:
 Subgroup error-state-basic:
 pass   -> FAIL   (ilk-hp8440p)


Seen before but not filed until now?

https://bugs.freedesktop.org/show_bug.cgi?id=94305


Test kms_flip:
 Subgroup basic-flip-vs-dpms:
 pass   -> DMESG-WARN (ilk-hp8440p) UNSTABLE


Existing unrelated: https://bugs.freedesktop.org/show_bug.cgi?id=93787


 Subgroup basic-flip-vs-wf_vblank:
 pass   -> FAIL   (hsw-gt2)


Existing unrelated: https://bugs.freedesktop.org/show_bug.cgi?id=94294


Test kms_force_connector_basic:
 Subgroup force-edid:
 pass   -> SKIP   (ilk-hp8440p)
Test kms_pipe_crc_basic:
 Subgroup suspend-read-crc-pipe-a:
 pass   -> DMESG-WARN (skl-i7k-2) UNSTABLE


Existing unrelated:  https://bugs.freedesktop.org/show_bug.cgi?id=93294


 Subgroup suspend-read-crc-pipe-b:
 pass   -> SKIP   (hsw-gt2)
 Subgroup suspend-read-crc-pipe-c:
 dmesg-warn -> PASS   (skl-i7k-2) UNSTABLE
Test pm_rpm:
 Subgroup basic-pci-d3-state:
 dmesg-warn -> PASS   (byt-nuc)
 Subgroup basic-rte:
 fail   -> PASS   (bdw-nuci7)
 fail   -> PASS   (bdw-ultra)

bdw-nuci7total:165  pass:154  dwarn:0   dfail:0   fail:0   skip:11
bdw-ultratotal:168  pass:154  dwarn:0   dfail:0   fail:0   skip:14
bsw-nuc-2total:168  pass:137  dwarn:0   dfail:0   fail:1   skip:30
byt-nuc  total:168  pass:143  dwarn:0   dfail:0   fail:0   skip:25
hsw-brixbox  total:168  pass:154  dwarn:0   dfail:0   fail:0   skip:14
hsw-gt2  total:168  pass:155  dwarn:0   dfail:1   fail:1   skip:11
ilk-hp8440p  total:168  pass:115  dwarn:1   dfail:1   fail:1   skip:50
ivb-t430stotal:168  pass:153  dwarn:0   dfail:0   fail:1   skip:14
skl-i7k-2total:168  pass:151  dwarn:1   dfail:0   fail:0   skip:16
snb-dellxps  total:168  pass:145  dwarn:0   dfail:0   fail:1   skip:22
snb-x220ttotal:168  pass:145  dwarn:0   dfail:0   fail:2   skip:21

Results at /archive/results/CI_IGT_test/Patchwork_1481/

38f0cd5314ecb02d15d019631e388d3642275600 drm-intel-nightly: 
2016y-02m-25d-15h-33m-53s UTC integration manifest
bd7970fbebc10e807e7d3d99fafec0729bf1907a drm/i915: Reduce the pointer dance of 
i915_is_ggtt()
04b7dad1ec23e0bcfc77ce1970d8e6dc9260017a drm/i915: Rename vma->*_list to *_link 
for consistency




Regards,

Tvrtko
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: Rename vma->*_list to *_link for consistency

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915: Rename vma->*_list to *_link for 
consistency
URL   : https://patchwork.freedesktop.org/series/3844/
State : failure

== Summary ==

Series 3844v1 Series without cover letter
http://patchwork.freedesktop.org/api/1.0/series/3844/revisions/1/mbox/

Test drv_hangman:
Subgroup error-state-basic:
pass   -> FAIL   (ilk-hp8440p)
Test kms_flip:
Subgroup basic-flip-vs-dpms:
pass   -> DMESG-WARN (ilk-hp8440p) UNSTABLE
Subgroup basic-flip-vs-wf_vblank:
pass   -> FAIL   (hsw-gt2)
Test kms_force_connector_basic:
Subgroup force-edid:
pass   -> SKIP   (ilk-hp8440p)
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass   -> DMESG-WARN (skl-i7k-2) UNSTABLE
Subgroup suspend-read-crc-pipe-b:
pass   -> SKIP   (hsw-gt2)
Subgroup suspend-read-crc-pipe-c:
dmesg-warn -> PASS   (skl-i7k-2) UNSTABLE
Test pm_rpm:
Subgroup basic-pci-d3-state:
dmesg-warn -> PASS   (byt-nuc)
Subgroup basic-rte:
fail   -> PASS   (bdw-nuci7)
fail   -> PASS   (bdw-ultra)

bdw-nuci7total:165  pass:154  dwarn:0   dfail:0   fail:0   skip:11 
bdw-ultratotal:168  pass:154  dwarn:0   dfail:0   fail:0   skip:14 
bsw-nuc-2total:168  pass:137  dwarn:0   dfail:0   fail:1   skip:30 
byt-nuc  total:168  pass:143  dwarn:0   dfail:0   fail:0   skip:25 
hsw-brixbox  total:168  pass:154  dwarn:0   dfail:0   fail:0   skip:14 
hsw-gt2  total:168  pass:155  dwarn:0   dfail:1   fail:1   skip:11 
ilk-hp8440p  total:168  pass:115  dwarn:1   dfail:1   fail:1   skip:50 
ivb-t430stotal:168  pass:153  dwarn:0   dfail:0   fail:1   skip:14 
skl-i7k-2total:168  pass:151  dwarn:1   dfail:0   fail:0   skip:16 
snb-dellxps  total:168  pass:145  dwarn:0   dfail:0   fail:1   skip:22 
snb-x220ttotal:168  pass:145  dwarn:0   dfail:0   fail:2   skip:21 

Results at /archive/results/CI_IGT_test/Patchwork_1481/

38f0cd5314ecb02d15d019631e388d3642275600 drm-intel-nightly: 
2016y-02m-25d-15h-33m-53s UTC integration manifest
bd7970fbebc10e807e7d3d99fafec0729bf1907a drm/i915: Reduce the pointer dance of 
i915_is_ggtt()
04b7dad1ec23e0bcfc77ce1970d8e6dc9260017a drm/i915: Rename vma->*_list to *_link 
for consistency

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Re: [Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915/gen9: Set value of Indirect Context Offset based on gen version (rev4)

[Tvrtko Ursulin]

On 23/02/16 13:08, Michel Thierry wrote:

On Tue, Feb 23, 2016 at 11:21 AM, Patchwork
 wrote:

== Series Details ==

Series: drm/i915/gen9: Set value of Indirect Context Offset based on gen
version (rev4)
URL   : https://patchwork.freedesktop.org/series/3629/
State : warning

== Summary ==

Series 3629v4 drm/i915/gen9: Set value of Indirect Context Offset based
on gen version
http://patchwork.freedesktop.org/api/1.0/series/3629/revisions/4/mbox/

Test gem_cs_prefetch:
 Subgroup basic-default:
 incomplete -> PASS   (ilk-hp8440p)
Test kms_force_connector_basic:
 Subgroup force-edid:
 skip   -> PASS   (snb-x220t)
 Subgroup force-load-detect:
 dmesg-fail -> FAIL   (snb-x220t)
 dmesg-fail -> FAIL   (snb-dellxps)
 fail   -> DMESG-FAIL (ilk-hp8440p)


Unrelated to this patch, snd and ilk don't have execlists.

Looks like it has been like this for a while:
/archive/results/CI_IGT_test/igt@kms_force_connector_ba...@force-load-detect.html


Also, this subtest is quite recent,
https://cgit.freedesktop.org/xorg/app/intel-gpu-tools/commit/?id=7670e286f5043d04af0cd1e6df1f092b5bcaf09e



Test kms_pipe_crc_basic:
 Subgroup suspend-read-crc-pipe-b:
 dmesg-warn -> PASS   (skl-i5k-2) UNSTABLE
 pass   -> DMESG-WARN (ilk-hp8440p)


Got this warning in ilk,
[  591.239261] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR*
CPU pipe B FIFO underrun



 Subgroup suspend-read-crc-pipe-c:
 pass   -> DMESG-WARN (skl-i5k-2) UNSTABLE
 pass   -> DMESG-WARN (bsw-nuc-2)


Same as: https://bugs.freedesktop.org/show_bug.cgi?id=93294 (cpu_hotplug
lockdep fail).


Test pm_rpm:
 Subgroup basic-pci-d3-state:
 pass   -> DMESG-WARN (bsw-nuc-2)


Already reported in https://bugs.freedesktop.org/show_bug.cgi?id=94163



bdw-nuci7total:165  pass:154  dwarn:0   dfail:0   fail:0
skip:11
bdw-ultratotal:168  pass:154  dwarn:0   dfail:0   fail:0
skip:14
bsw-nuc-2total:168  pass:135  dwarn:2   dfail:0   fail:1
skip:30
byt-nuc  total:168  pass:142  dwarn:1   dfail:0   fail:0
skip:25
hsw-gt2  total:168  pass:157  dwarn:0   dfail:1   fail:0
skip:10
ilk-hp8440p  total:168  pass:117  dwarn:1   dfail:1   fail:0
skip:49
ivb-t430stotal:168  pass:153  dwarn:0   dfail:0   fail:1
skip:14
skl-i5k-2total:168  pass:151  dwarn:1   dfail:0   fail:0
skip:16
snb-dellxps  total:168  pass:145  dwarn:0   dfail:0   fail:1
skip:22
snb-x220ttotal:168  pass:145  dwarn:0   dfail:0   fail:2
skip:21

Results at /archive/results/CI_IGT_test/Patchwork_1460/

08fc1b101049694778bff7559e1d05250d2e7072 drm-intel-nightly:
2016y-02m-22d-17h-30m-27s UTC integration manifest
644bbd41dad8857b829a3c627d951873592a7f63 drm/i915/gen9: Set value of
Indirect Context Offset based on gen version



Merged, thanks for the patch! :)

Regards,

Tvrtko
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Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/lrc: Only set RS ctx enable in ctx control reg if there is a RS (rev2)

[Tvrtko Ursulin]

On 25/02/16 14:22, Michel Thierry wrote:

On Thu, Feb 25, 2016 at 11:10 AM, Patchwork
 wrote:

== Series Details ==

Series: drm/i915/lrc: Only set RS ctx enable in ctx control reg if there
is a RS (rev2)
URL   : https://patchwork.freedesktop.org/series/3725/
State : failure

== Summary ==

Series 3725v2 drm/i915/lrc: Only set RS ctx enable in ctx control reg if
there is a RS
http://patchwork.freedesktop.org/api/1.0/series/3725/revisions/2/mbox/

Test drv_hangman:
 Subgroup error-state-basic:
 pass   -> FAIL   (ilk-hp8440p)


(drv_hangman:6411) DEBUG: dfs entry i915_error_state read 'no error
state collected'

So hangman wasn't able to hang the ring?



Test gem_sync:
 Subgroup basic-default:
 pass   -> DMESG-FAIL (hsw-brixbox)


[  406.005039] [drm:i915_hangcheck_elapsed [i915]] *ERROR* Hangcheck
timer elapsed... render ring idle

This looks like a real regression (but unrelated to this patch, hsw
doesn't use execlists). I opened
https://bugs.freedesktop.org/show_bug.cgi?id=94289
Unfortunately I don't have a hsw to do a bisect.



Test kms_flip:
 Subgroup basic-flip-vs-modeset:
 pass   -> DMESG-WARN (ilk-hp8440p) UNSTABLE


The usual
[  196.712245] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR*
CPU pipe A FIFO underrun



Test kms_force_connector_basic:
 Subgroup force-load-detect:
 fail   -> DMESG-FAIL (ilk-hp8440p)

Again, unrelated to this patch, snd and ilk don't have execlists.

Looks like it has been like this for a while:
/archive/results/CI_IGT_test/igt@kms_force_connector_ba...@force-load-detect.html


Also, this subtest is quite recent,
https://cgit.freedesktop.org/xorg/app/intel-gpu-tools/commit/?id=7670e286f5043d04af0cd1e6df1f092b5bcaf09e



Test kms_pipe_crc_basic:
 Subgroup nonblocking-crc-pipe-a-frame-sequence:
 pass   -> DMESG-WARN (ilk-hp8440p)


Again,
[  682.562490] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR*
CPU pipe A FIFO underrun


 Subgroup suspend-read-crc-pipe-b:
 pass   -> DMESG-WARN (skl-i7k-2) UNSTABLE


Same as: https://bugs.freedesktop.org/show_bug.cgi?id=93294 (cpu_hotplug
lockdep fail).


 Subgroup suspend-read-crc-pipe-c:
 pass   -> SKIP   (bsw-nuc-2)
 pass   -> SKIP   (hsw-brixbox)
 dmesg-warn -> PASS   (skl-i7k-2) UNSTABLE
Test pm_rpm:
 Subgroup basic-pci-d3-state:
 dmesg-warn -> PASS   (bsw-nuc-2)

bdw-nuci7total:165  pass:154  dwarn:0   dfail:0   fail:0
skip:11
bdw-ultratotal:168  pass:154  dwarn:0   dfail:0   fail:0
skip:14
bsw-nuc-2total:168  pass:136  dwarn:0   dfail:0   fail:1
skip:31
byt-nuc  total:168  pass:143  dwarn:0   dfail:0   fail:0
skip:25
hsw-brixbox  total:168  pass:152  dwarn:0   dfail:1   fail:0
skip:15
hsw-gt2  total:168  pass:157  dwarn:0   dfail:1   fail:0
skip:10
ilk-hp8440p  total:168  pass:115  dwarn:2   dfail:1   fail:1
skip:49
ivb-t430stotal:168  pass:153  dwarn:0   dfail:0   fail:1
skip:14
skl-i7k-2total:168  pass:151  dwarn:1   dfail:0   fail:0
skip:16
snb-dellxps  total:168  pass:145  dwarn:0   dfail:0   fail:1
skip:22
snb-x220ttotal:168  pass:145  dwarn:0   dfail:0   fail:2
skip:21

Results at /archive/results/CI_IGT_test/Patchwork_1473/

eb8b161ee8760105238ce372afa47b4565590125 drm-intel-nightly:
2016y-02m-25d-08h-16m-19s UTC integration manifest
b593d5b2bb8f88797651fda8e988794699da8eba drm/i915/lrc: Only set RS ctx
enable in ctx control reg if there is a RS


Merged, thanks for the patch! :)

Regards,

Tvrtko
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[Intel-gfx] [PATCH] drm/i915: Execlists cannot pin a context without the object

[Tvrtko Ursulin]

From: Chris Wilson 

Given that the intel_lr_context_pin cannot succeed without the object,
we cannot reach intel_lr_context_unpin() without first allocating that
object - so we can remove the redundant test.

Signed-off-by: Chris Wilson 
Reviewed-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/intel_lrc.c | 4 
 1 file changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 3a03646e343d..f0a57afc8dff 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1144,10 +1144,6 @@ void intel_lr_context_unpin(struct intel_context *ctx,
struct drm_i915_gem_object *ctx_obj = ctx->engine[engine->id].state;
 
WARN_ON(!mutex_is_locked(>i915->dev->struct_mutex));
-
-   if (WARN_ON_ONCE(!ctx_obj))
-   return;
-
if (--ctx->engine[engine->id].pin_count == 0) {
kunmap(kmap_to_page(ctx->engine[engine->id].lrc_reg_state));
intel_unpin_ringbuffer_obj(ctx->engine[engine->id].ringbuf);
-- 
1.9.1

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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Adaptive backoff delay on link training

[Patchwork]

== Series Details ==

Series: drm/i915: Adaptive backoff delay on link training
URL   : https://patchwork.freedesktop.org/series/3843/
State : failure

== Summary ==

Series 3843v1 drm/i915: Adaptive backoff delay on link training
http://patchwork.freedesktop.org/api/1.0/series/3843/revisions/1/mbox/

Test kms_force_connector_basic:
Subgroup force-load-detect:
dmesg-fail -> FAIL   (hsw-gt2)
Test pm_rpm:
Subgroup basic-rte:
pass   -> FAIL   (hsw-gt2)
fail   -> PASS   (bdw-nuci7)
fail   -> PASS   (bdw-ultra)

bdw-nuci7total:165  pass:154  dwarn:0   dfail:0   fail:0   skip:11 
bdw-ultratotal:168  pass:154  dwarn:0   dfail:0   fail:0   skip:14 
bsw-nuc-2total:168  pass:137  dwarn:0   dfail:0   fail:1   skip:30 
hsw-brixbox  total:168  pass:154  dwarn:0   dfail:0   fail:0   skip:14 
hsw-gt2  total:168  pass:156  dwarn:0   dfail:0   fail:2   skip:10 
ilk-hp8440p  total:168  pass:118  dwarn:0   dfail:1   fail:0   skip:49 
ivb-t430stotal:168  pass:153  dwarn:0   dfail:0   fail:1   skip:14 
skl-i7k-2total:168  pass:151  dwarn:1   dfail:0   fail:0   skip:16 
snb-dellxps  total:168  pass:145  dwarn:0   dfail:0   fail:1   skip:22 
snb-x220ttotal:168  pass:145  dwarn:0   dfail:0   fail:2   skip:21 

Results at /archive/results/CI_IGT_test/Patchwork_1480/

38f0cd5314ecb02d15d019631e388d3642275600 drm-intel-nightly: 
2016y-02m-25d-15h-33m-53s UTC integration manifest
bfac725986e5c5f2982d943f0e7f43fa2ceab082 drm/i915: Adaptive backoff delay on 
link training

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[Intel-gfx] [PATCH i-g-t v2 2/3] lib/igt_kms: Add fail exit branch in do_display_commit()

[Gabriel Feceoru]

On Cherryview PIPE_C can only be connected to PORT_D (bspec).
The driver properly reports the crtc_mask for the encoder, however the
mismatch between pipe and port is not reported back to the test.

Add support for detecting this case so the test can be skipped.

v2: Apply review comments (Marius)

Signed-off-by: Gabriel Feceoru 
---
 lib/igt_kms.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index 90c8da7..6163a6d 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -1669,6 +1669,7 @@ static int do_display_commit(igt_display_t *display,
 bool fail_on_error)
 {
int i, ret;
+   int valid_outs = 0;
 
LOG_INDENT(display, "commit");
 
@@ -1680,12 +1681,16 @@ static int do_display_commit(igt_display_t *display,
if (!output->valid)
continue;
 
+   valid_outs++;
ret = igt_output_commit(output, s, fail_on_error);
CHECK_RETURN(ret, fail_on_error);
}
 
LOG_UNINDENT(display);
 
+   if (valid_outs == 0)
+   return -1;
+
igt_debug_wait_for_keypress("modeset");
 
return 0;
-- 
1.9.1

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[Intel-gfx] [PATCH 2/2] drm/i915: Reduce the pointer dance of i915_is_ggtt()

[Tvrtko Ursulin]

From: Chris Wilson 

The multiple levels of indirect do nothing but hinder the compiler and
the pointer chasing turns to be quite painful but painless to fix.

Signed-off-by: Chris Wilson 
Reviewed-by: Tvrtko Ursulin 
Reviewed-by: Dave Gordon 
---
 drivers/gpu/drm/i915/i915_debugfs.c| 13 ++---
 drivers/gpu/drm/i915/i915_drv.h|  7 ---
 drivers/gpu/drm/i915/i915_gem.c| 18 +++---
 drivers/gpu/drm/i915/i915_gem_execbuffer.c |  5 ++---
 drivers/gpu/drm/i915/i915_gem_gtt.c| 12 +---
 drivers/gpu/drm/i915/i915_gem_gtt.h|  5 +
 drivers/gpu/drm/i915/i915_trace.h  | 27 ---
 7 files changed, 33 insertions(+), 54 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index d7f03bceea57..a0f1bd711b53 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -118,7 +118,7 @@ static u64 i915_gem_obj_total_ggtt_size(struct 
drm_i915_gem_object *obj)
struct i915_vma *vma;
 
list_for_each_entry(vma, >vma_list, obj_link) {
-   if (i915_is_ggtt(vma->vm) && drm_mm_node_allocated(>node))
+   if (vma->is_ggtt && drm_mm_node_allocated(>node))
size += vma->node.size;
}
 
@@ -165,12 +165,11 @@ describe_obj(struct seq_file *m, struct 
drm_i915_gem_object *obj)
seq_printf(m, " (fence: %d)", obj->fence_reg);
list_for_each_entry(vma, >vma_list, obj_link) {
seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
-  i915_is_ggtt(vma->vm) ? "g" : "pp",
+  vma->is_ggtt ? "g" : "pp",
   vma->node.start, vma->node.size);
-   if (i915_is_ggtt(vma->vm))
-   seq_printf(m, ", type: %u)", vma->ggtt_view.type);
-   else
-   seq_puts(m, ")");
+   if (vma->is_ggtt)
+   seq_printf(m, ", type: %u", vma->ggtt_view.type);
+   seq_puts(m, ")");
}
if (obj->stolen)
seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
@@ -347,7 +346,7 @@ static int per_file_stats(int id, void *ptr, void *data)
if (!drm_mm_node_allocated(>node))
continue;
 
-   if (i915_is_ggtt(vma->vm)) {
+   if (vma->is_ggtt) {
stats->global += obj->base.size;
continue;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9e76bfc7d5ab..a4dcb744bfe8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3156,18 +3156,11 @@ bool i915_gem_obj_is_pinned(struct drm_i915_gem_object 
*obj);
 /* Some GGTT VM helpers */
 #define i915_obj_to_ggtt(obj) \
(&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
-static inline bool i915_is_ggtt(struct i915_address_space *vm)
-{
-   struct i915_address_space *ggtt =
-   &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
-   return vm == ggtt;
-}
 
 static inline struct i915_hw_ppgtt *
 i915_vm_to_ppgtt(struct i915_address_space *vm)
 {
WARN_ON(i915_is_ggtt(vm));
-
return container_of(vm, struct i915_hw_ppgtt, base);
 }
 
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index bcd2e481d014..3d31d3ac589e 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3336,8 +3336,7 @@ static int __i915_vma_unbind(struct i915_vma *vma, bool 
wait)
return ret;
}
 
-   if (i915_is_ggtt(vma->vm) &&
-   vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
+   if (vma->is_ggtt && vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
i915_gem_object_finish_gtt(obj);
 
/* release the fence reg _after_ flushing */
@@ -3352,7 +3351,7 @@ static int __i915_vma_unbind(struct i915_vma *vma, bool 
wait)
vma->bound = 0;
 
list_del_init(>vm_link);
-   if (i915_is_ggtt(vma->vm)) {
+   if (vma->is_ggtt) {
if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
obj->map_and_fenceable = false;
} else if (vma->ggtt_view.pages) {
@@ -4639,17 +4638,14 @@ struct i915_vma *i915_gem_obj_to_ggtt_view(struct 
drm_i915_gem_object *obj,
 
 void i915_gem_vma_destroy(struct i915_vma *vma)
 {
-   struct i915_address_space *vm = NULL;
WARN_ON(vma->node.allocated);
 
/* Keep the vma as a placeholder in the execbuffer reservation lists */
if (!list_empty(>exec_list))
return;
 
-   vm = vma->vm;
-
-   if 

[Intel-gfx] [PATCH 1/2] drm/i915: Rename vma->*_list to *_link for consistency

[Tvrtko Ursulin]

From: Chris Wilson 

Elsewhere we have adopted the convention of using '_link' to denote
elements in the list (and '_list' for the actual list_head itself), and
that the name should indicate which list the link belongs to (and
preferrably not just where the link is being stored).

s/vma_link/obj_link/ (we iterate over obj->vma_list)
s/mm_list/vm_link/ (we iterate over vm->[in]active_list)

Signed-off-by: Chris Wilson 
Reviewed-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_debugfs.c  | 17 +--
 drivers/gpu/drm/i915/i915_gem.c  | 50 
 drivers/gpu/drm/i915/i915_gem_context.c  |  2 +-
 drivers/gpu/drm/i915/i915_gem_evict.c|  6 ++--
 drivers/gpu/drm/i915/i915_gem_gtt.c  | 10 +++
 drivers/gpu/drm/i915/i915_gem_gtt.h  |  4 +--
 drivers/gpu/drm/i915/i915_gem_shrinker.c |  4 +--
 drivers/gpu/drm/i915/i915_gem_stolen.c   |  2 +-
 drivers/gpu/drm/i915/i915_gem_userptr.c  |  2 +-
 drivers/gpu/drm/i915/i915_gpu_error.c|  8 ++---
 10 files changed, 52 insertions(+), 53 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 9e19cf0e7075..d7f03bceea57 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -117,9 +117,8 @@ static u64 i915_gem_obj_total_ggtt_size(struct 
drm_i915_gem_object *obj)
u64 size = 0;
struct i915_vma *vma;
 
-   list_for_each_entry(vma, >vma_list, vma_link) {
-   if (i915_is_ggtt(vma->vm) &&
-   drm_mm_node_allocated(>node))
+   list_for_each_entry(vma, >vma_list, obj_link) {
+   if (i915_is_ggtt(vma->vm) && drm_mm_node_allocated(>node))
size += vma->node.size;
}
 
@@ -155,7 +154,7 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object 
*obj)
   obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
if (obj->base.name)
seq_printf(m, " (name: %d)", obj->base.name);
-   list_for_each_entry(vma, >vma_list, vma_link) {
+   list_for_each_entry(vma, >vma_list, obj_link) {
if (vma->pin_count > 0)
pin_count++;
}
@@ -164,7 +163,7 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object 
*obj)
seq_printf(m, " (display)");
if (obj->fence_reg != I915_FENCE_REG_NONE)
seq_printf(m, " (fence: %d)", obj->fence_reg);
-   list_for_each_entry(vma, >vma_list, vma_link) {
+   list_for_each_entry(vma, >vma_list, obj_link) {
seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
   i915_is_ggtt(vma->vm) ? "g" : "pp",
   vma->node.start, vma->node.size);
@@ -230,7 +229,7 @@ static int i915_gem_object_list_info(struct seq_file *m, 
void *data)
}
 
total_obj_size = total_gtt_size = count = 0;
-   list_for_each_entry(vma, head, mm_list) {
+   list_for_each_entry(vma, head, vm_link) {
seq_printf(m, "   ");
describe_obj(m, vma->obj);
seq_printf(m, "\n");
@@ -342,7 +341,7 @@ static int per_file_stats(int id, void *ptr, void *data)
stats->shared += obj->base.size;
 
if (USES_FULL_PPGTT(obj->base.dev)) {
-   list_for_each_entry(vma, >vma_list, vma_link) {
+   list_for_each_entry(vma, >vma_list, obj_link) {
struct i915_hw_ppgtt *ppgtt;
 
if (!drm_mm_node_allocated(>node))
@@ -454,12 +453,12 @@ static int i915_gem_object_info(struct seq_file *m, void* 
data)
   count, mappable_count, size, mappable_size);
 
size = count = mappable_size = mappable_count = 0;
-   count_vmas(>active_list, mm_list);
+   count_vmas(>active_list, vm_link);
seq_printf(m, "  %u [%u] active objects, %llu [%llu] bytes\n",
   count, mappable_count, size, mappable_size);
 
size = count = mappable_size = mappable_count = 0;
-   count_vmas(>inactive_list, mm_list);
+   count_vmas(>inactive_list, vm_link);
seq_printf(m, "  %u [%u] inactive objects, %llu [%llu] bytes\n",
   count, mappable_count, size, mappable_size);
 
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index f68f34606f2f..bcd2e481d014 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -138,10 +138,10 @@ i915_gem_get_aperture_ioctl(struct drm_device *dev, void 
*data,
 
pinned = 0;
mutex_lock(>struct_mutex);
-   list_for_each_entry(vma, >base.active_list, mm_list)
+   list_for_each_entry(vma, >base.active_list, vm_link)
if (vma->pin_count)
pinned += vma->node.size;
-   list_for_each_entry(vma, >base.inactive_list, mm_list)
+   list_for_each_entry(vma, 

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Balance assert_rpm_wakelock_held() for !IS_ENABLED(CONFIG_PM)

[Imre Deak]

On Fri, 2016-02-26 at 07:00 +, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915: Balance assert_rpm_wakelock_held() for
> !IS_ENABLED(CONFIG_PM)
> URL   : https://patchwork.freedesktop.org/series/3827/
> State : failure
> 
> == Summary ==
> 
> Series 3827v1 drm/i915: Balance assert_rpm_wakelock_held() for
> !IS_ENABLED(CONFIG_PM)
> http://patchwork.freedesktop.org/api/1.0/series/3827/revisions/1/mbox
> /
> 
> Test drv_hangman:
> Subgroup error-state-basic:
> pass   -> INCOMPLETE (snb-dellxps)
> Test gem_sync:
> Subgroup basic-bsd:
> pass   -> DMESG-FAIL (hsw-brixbox)
> pass   -> DMESG-FAIL (ilk-hp8440p)
> Test kms_flip:
> Subgroup basic-flip-vs-wf_vblank:
> pass   -> FAIL   (snb-x220t)
> Test pm_rpm:
> Subgroup basic-pci-d3-state:
> dmesg-warn -> PASS   (byt-nuc)
> Subgroup basic-rte:
> pass   -> DMESG-WARN (bsw-nuc-2)
> fail   -> PASS   (bdw-nuci7)
> fail   -> PASS   (bdw-ultra)

All tests are run with CONFIG_PM enabled, and the patch changes
behavior only with !CONFIG_PM. Even in case of !CONFIG_PM only the
generation of wakeref messages are affected and not any other
functionality. So I'm confident the above failures are unrelated.

> bdw-
> nuci7total:165  pass:154  dwarn:0   dfail:0   fail:0   skip:1
> 1 
> bdw-
> ultratotal:168  pass:154  dwarn:0   dfail:0   fail:0   skip:1
> 4 
> bsw-nuc-
> 2total:168  pass:136  dwarn:1   dfail:0   fail:1   skip:30 
> byt-
> nuc  total:168  pass:143  dwarn:0   dfail:0   fail:0   skip:2
> 5 
> hsw-
> brixbox  total:168  pass:153  dwarn:0   dfail:1   fail:0   skip:1
> 4 
> hsw-
> gt2  total:168  pass:157  dwarn:0   dfail:1   fail:0   skip:1
> 0 
> ilk-
> hp8440p  total:168  pass:117  dwarn:0   dfail:2   fail:0   skip:4
> 9 
> ivb-
> t430stotal:168  pass:153  dwarn:0   dfail:0   fail:1   skip:1
> 4 
> skl-i7k-
> 2total:168  pass:151  dwarn:1   dfail:0   fail:0   skip:16 
> snb-
> dellxps  total:154  pass:132  dwarn:0   dfail:0   fail:1   skip:2
> 0 
> snb-
> x220ttotal:168  pass:144  dwarn:0   dfail:0   fail:3   skip:2
> 1 
> 
> Results at /archive/results/CI_IGT_test/Patchwork_1479/
> 
> 38f0cd5314ecb02d15d019631e388d3642275600 drm-intel-nightly: 2016y-
> 02m-25d-15h-33m-53s UTC integration manifest
> f7a63002de7ec2829aeae48527217bc4d1d9b106 drm/i915: Balance
> assert_rpm_wakelock_held() for !IS_ENABLED(CONFIG_PM)
> 
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[Intel-gfx] [PATCH] drm/i915: Adaptive backoff delay on link training

[Mika Kuoppala]

If the panel don't give us the information how long to wait
before starting a new link training phase, it is not productive
to poke it at 100us or 400us intervals and then give up if it
fails to respond in time. Instead gradually increase the training
delay so that we reach the slower kind and get display up.

This was needed to reach panel:

: 12 14 c4 41 00 00 01 c0 02 00 00 00 1f 0b 00
0070: 01 00
0080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0100: 14 84 00 00 00 00 00 00 01 10 00
0200: 01 00 00 00 80 00 00 00
0600: 01
0700: 02
0701: b7 f6 00 00
0720: 00 04 02 00 0a 04 0a 00 1b 00 00 01 00 ff ff 03
0732: 04 10

on kbl (8086:591e)

Cc: Ander Conselvan de Oliveira 
Cc: Rodrigo Vivi 
Cc: Mika Kahola 
Signed-off-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/intel_dp_link_training.c | 21 ++---
 1 file changed, 18 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c 
b/drivers/gpu/drm/i915/intel_dp_link_training.c
index 0b8eefc2acc5..aec81e28e347 100644
--- a/drivers/gpu/drm/i915/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
@@ -104,6 +104,19 @@ intel_dp_update_link_train(struct intel_dp *intel_dp)
return ret == intel_dp->lane_count;
 }
 
+static void intel_dp_link_training_delay(struct intel_dp *intel_dp,
+int retry_count)
+{
+   if (intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL]) {
+   mdelay(intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
+   } else {
+   if (retry_count)
+   mdelay(retry_count * 4);
+   else
+   udelay(400);
+   }
+}
+
 /* Enable corresponding port and start training pattern 1 */
 static void
 intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
@@ -150,7 +163,8 @@ intel_dp_link_training_clock_recovery(struct intel_dp 
*intel_dp)
for (;;) {
uint8_t link_status[DP_LINK_STATUS_SIZE];
 
-   drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
+   intel_dp_link_training_delay(intel_dp, loop_tries);
+
if (!intel_dp_get_link_status(intel_dp, link_status)) {
DRM_ERROR("failed to get link status\n");
break;
@@ -184,7 +198,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp 
*intel_dp)
break;
if (i == intel_dp->lane_count) {
++loop_tries;
-   if (loop_tries == 5) {
+   if (loop_tries == 10) {
DRM_ERROR("too many full retries, give up\n");
break;
}
@@ -275,7 +289,8 @@ intel_dp_link_training_channel_equalization(struct intel_dp 
*intel_dp)
break;
}
 
-   drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
+   intel_dp_link_training_delay(intel_dp, cr_tries);
+
if (!intel_dp_get_link_status(intel_dp, link_status)) {
DRM_ERROR("failed to get link status\n");
break;
-- 
2.5.0

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Re: [Intel-gfx] System freeze apparently due to GPU memory exhaustion - why?

[Joonas Lahtinen]

On ti, 2016-02-23 at 20:58 +1000, Adam Nielsen wrote:
> > 
> > Can you attach a full dmesg from boot until the problem appears?
> Attached, thanks for your reply.
> 
> You can ignore the problem at T=1032000, that was a broken floppy disk
> in a USB floppy drive.  The first possibly-GPU-related problem starts
> at T=2121945 then the same problem happens immediately following in the
> log at T=2128002.
> 

That seems like a legit bug. If you can reproduce it with drm-intel-
nightly, could you please open a bug at freedesktop.org bugzilla?

Have you tried running the I-G-T testing suite on your hardware?

Regards, Joonas

> It may be of relevance to note that after a reboot it can take a while
> for the problem to surface, but if X crashes due to this issue and I
> restart X immediately, then it can be only a matter of minutes to
> hours until the problem happens again.
> 
> Many thanks,
> Adam.
> ___
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
-- 
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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Re: [Intel-gfx] [PATCH i-g-t v3] tests/drv_hangman: test for acthd increasing through invalid VM space

[Mika Kuoppala]

daniele.ceraolospu...@intel.com writes:

> From: Daniele Ceraolo Spurio 
>
> The hangcheck logic will not flag an hang if acthd keeps increasing.
> However, if a malformed batch jumps to an invalid offset in the ppgtt it
> can potentially continue executing through the whole address space
> without triggering the hangcheck mechanism.
>
> This patch adds a test to simulate the issue. I've kept the test running
> for more than 10 minutes before killing it on a BDW and no hang occurred.
> I've sampled i915_hangcheck_info a few times during the run and got the
> following:
>
> Hangcheck active, fires in 468ms
> render ring:
>   seqno = f55e [current f55e]
>   ACTHD = 0x47df685ecc [current 0x4926b81d90]
>   max ACTHD = 0x47df685ecc
>   score = 0
>   action = 2
>   instdone read = 0xffd7 0x 0x 0x
>   instdone accu = 0x 0x 0x 0x
>
> Hangcheck active, fires in 424ms
> render ring:
>   seqno = f55e [current f55e]
>   ACTHD = 0x6c953d3a34 [current 0x6de5e76fa4]
>   max ACTHD = 0x6c953d3a34
>   score = 0
>   action = 2
>   instdone read = 0xffd7 0x 0x 0x
>   instdone accu = 0x 0x 0x 0x
>
> Hangcheck active, fires in 1692ms
> render ring:
>   seqno = f55e [current f55e]
>   ACTHD = 0x1f49b0366dc [current 0x1f4dcbd88ec]
>   max ACTHD = 0x1f49b0366dc
>   score = 0
>   action = 2
>   instdone read = 0xffd7 0x 0x 0x
>   instdone accu = 0x 0x 0x 0x
>
> v2: use the new gem_wait() function (Chris)
>
> v3: switch to unterminated batch and rename test, remove redundant
> check, update test requirements (Chris), update top comment
>
> Cc: Mika Kuoppala 
> Cc: Arun Siluvery 
> Cc: Chris Wilson 
> Signed-off-by: Daniele Ceraolo Spurio 
> ---
>  tests/drv_hangman.c | 39 +++
>  1 file changed, 39 insertions(+)
>
> diff --git a/tests/drv_hangman.c b/tests/drv_hangman.c
> index 8a465cf..2360f26 100644
> --- a/tests/drv_hangman.c
> +++ b/tests/drv_hangman.c
> @@ -288,6 +288,42 @@ static void test_error_state_capture(unsigned ring_id,
>   check_error_state(gen, cmd_parser, ring_name, offset);
>  }
>  
> +/* This test covers the case where we end up in an uninitialised area of the
> + * ppgtt and keep executing through it. This is particularly relevant if 48b
> + * ppgtt is enabled because the ppgtt is massively bigger compared to the 32b
> + * case and it takes a lot more time to wrap, so the acthd can potentially 
> keep
> + * increasing for a long time
> + */
> +#define NSEC_PER_SEC 10L
> +static void hangcheck_unterminated(void)
> +{
> + int fd;
> + /* timeout needs to be greater than ~5*hangcheck */
> + int64_t timeout_ns = 100 * NSEC_PER_SEC; /* 100 seconds */
> + struct drm_i915_gem_execbuffer2 execbuf;
> + struct drm_i915_gem_exec_object2 gem_exec;
> + uint32_t handle;
> +
> + fd = drm_open_driver(DRIVER_INTEL);
> + igt_require(gem_uses_full_ppgtt(fd));
> + igt_require_hang_ring(fd, 0);
> +
> + handle = gem_create(fd, 4096);
> +
> + memset(_exec, 0, sizeof(gem_exec));
> + gem_exec.handle = handle;
> +
> + memset(, 0, sizeof(execbuf));
> + execbuf.buffers_ptr = (uintptr_t)_exec;
> + execbuf.buffer_count = 1;
> + execbuf.batch_len = 8;
> +
> + gem_execbuf(fd, );
> + igt_assert_eq(gem_wait(fd, handle, _ns), 0);

Chris pointed out in irc that if end up timeouting, that
means runaway head is there still progressing.

In order to make the gpu usable again, we need to forcereset
the gpu. Stop rings doesn't help at here anymore so
forcing 'echo 1 >i915_wedged_set should do the trick.

-Mika



> +
> + close(fd);
> +}
> +
>  igt_main
>  {
>   const struct intel_execution_engine *e;
> @@ -314,4 +350,7 @@ igt_main
>   test_error_state_capture(e->exec_id | e->flags,
>e->full_name);
>   }
> +
> + igt_subtest("hangcheck-unterminated")
> + hangcheck_unterminated();
>  }
> -- 
> 1.9.1
___
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Re: [Intel-gfx] [PATCH v5 06/35] drm/i915: Start of GPU scheduler

[Joonas Lahtinen]

Hi,

The below answers are reasonable. So v6 should be the version.

Regards, Joonas

On pe, 2016-02-19 at 17:03 +, John Harrison wrote:
> On 19/02/2016 13:03, Joonas Lahtinen wrote:
> > 
> > Hi,
> > 
> > Now the code is in reviewable chunks, excellent!
> > 
> > I've added my comments below. A few repeats from last round, but
> > now
> > with more questions about the logic itself.
> > 
> > On to, 2016-02-18 at 14:26 +, john.c.harri...@intel.com wrote:
> > > 
> > > From: John Harrison 
> > > 
> > > Initial creation of scheduler source files. Note that this patch
> > > implements most of the scheduler functionality but does not hook
> > > it in
> > > to the driver yet. It also leaves the scheduler code in 'pass
> > > through'
> > > mode so that even when it is hooked in, it will not actually do
> > > very
> > > much. This allows the hooks to be added one at a time in bite
> > > size
> > > chunks and only when the scheduler is finally enabled at the end
> > > does
> > > anything start happening.
> > > 
> > > The general theory of operation is that when batch buffers are
> > > submitted to the driver, the execbuffer() code packages up all
> > > the
> > > information required to execute the batch buffer at a later time.
> > > This
> > > package is given over to the scheduler which adds it to an
> > > internal
> > > node list. The scheduler also scans the list of objects
> > > associated
> > > with the batch buffer and compares them against the objects
> > > already in
> > > use by other buffers in the node list. If matches are found then
> > > the
> > > new batch buffer node is marked as being dependent upon the
> > > matching
> > > node. The same is done for the context object. The scheduler also
> > > bumps up the priority of such matching nodes on the grounds that
> > > the
> > > more dependencies a given batch buffer has the more important it
> > > is
> > > likely to be.
> > > 
> > > The scheduler aims to have a given (tuneable) number of batch
> > > buffers
> > > in flight on the hardware at any given time. If fewer than this
> > > are
> > > currently executing when a new node is queued, then the node is
> > > passed
> > > straight through to the submit function. Otherwise it is simply
> > > added
> > > to the queue and the driver returns back to user land.
> > > 
> > > The scheduler is notified when each batch buffer completes and
> > > updates
> > > its internal tracking accordingly. At the end of the completion
> > > interrupt processing, if any scheduler tracked batches were
> > > processed,
> > > the scheduler's deferred worker thread is woken up. This can do
> > > more
> > > involved processing such as actually removing completed nodes
> > > from the
> > > queue and freeing up the resources associated with them (internal
> > > memory allocations, DRM object references, context reference,
> > > etc.).
> > > The work handler also checks the in flight count and calls the
> > > submission code if a new slot has appeared.
> > > 
> > > When the scheduler's submit code is called, it scans the queued
> > > node
> > > list for the highest priority node that has no unmet
> > > dependencies.
> > > Note that the dependency calculation is complex as it must take
> > > inter-ring dependencies and potential preemptions into account.
> > > Note
> > > also that in the future this will be extended to include external
> > > dependencies such as the Android Native Sync file descriptors
> > > and/or
> > > the linux dma-buff synchronisation scheme.
> > > 
> > > If a suitable node is found then it is sent to execbuff_final()
> > > for
> > > submission to the hardware. The in flight count is then re-
> > > checked and
> > > a new node popped from the list if appropriate. All nodes that
> > > are not
> > > submitted have their priority bumped. This ensures that low
> > > priority
> > > tasks do not get starved out by busy higher priority ones -
> > > everything
> > > will eventually get its turn to run.
> > > 
> > > Note that this patch does not implement pre-emptive scheduling.
> > > Only
> > > basic scheduling by re-ordering batch buffer submission is
> > > currently
> > > implemented. Pre-emption of actively executing batch buffers
> > > comes in
> > > the next patch series.
> > > 
> > > v2: Changed priority levels to +/-1023 due to feedback from Chris
> > > Wilson.
> > > 
> > > Removed redundant index from scheduler node.
> > > 
> > > Changed time stamps to use jiffies instead of raw monotonic. This
> > > provides lower resolution but improved compatibility with other
> > > i915
> > > code.
> > > 
> > > Major re-write of completion tracking code due to struct fence
> > > conversion. The scheduler no longer has it's own private IRQ
> > > handler
> > > but just lets the existing request code handle completion events.
> > > Instead, the scheduler now hooks into the request notify code to
> > > be
> > > told when a request has completed.
> > > 
> > > Reduced driver mutex locking scope. 

[Intel-gfx] NULL pointer dereference in intel_fb_obj_invalidate

[Christian Hesse]

Hello everybody,

I am running a Lenovo Thinkpad X250 with this graphics controller:

00:02.0 VGA compatible controller: Intel Corporation Broadwell-U Integrated
Graphics (rev 09)

Everything works just fine when using the integrated display.

The notebook is connected to a docking station with two connected display
ports. With light-locker I can lock and unlock the screen once, system panics
with a kernel NULL pointer dereference in intel_fb_obj_invalidate the second
time.

Screen 0: minimum 8 x 8, current 3840 x 1080, maximum 32767 x 32767
eDP1 connected (normal left inverted right x axis y axis)
   1920x1080 60.04 +
   1400x1050 59.98  
   1600x900  60.00  
   1280x1024 60.02  
   1280x960  60.00  
   1368x768  60.00  
   1280x720  60.00  
   1024x768  60.00  
   1024x576  60.00  
   960x540   60.00  
   800x600   60.3256.25  
   864x486   60.00  
   640x480   59.94  
   720x405   60.00  
   640x360   60.00  
DP1 disconnected (normal left inverted right x axis y axis)
DP2 disconnected (normal left inverted right x axis y axis)
DP2-1 connected primary 1920x1080+0+0 (normal left inverted right x axis y 
axis) 521mm x 293mm
   1920x1080 60.00*+  50.0059.94  
   1680x1050 59.88  
   1600x900  60.00  
   1280x1024 75.0260.02  
   1440x900  59.90  
   1280x800  59.91  
   1152x864  75.00  
   1280x720  60.0050.0059.94  
   1024x768  75.0870.0760.00  
   832x624   74.55  
   800x600   72.1975.0060.3256.25  
   720x576   50.00  
   720x480   60.0059.94  
   640x480   75.0072.8166.6760.0059.94  
   720x400   70.08  
DP2-2 connected 1920x1080+1920+0 (normal left inverted right x axis y axis) 
521mm x 293mm
   1920x1080 60.00*+  50.0059.94  
   1680x1050 59.88  
   1600x900  60.00  
   1280x1024 75.0260.02  
   1440x900  59.90  
   1280x800  59.91  
   1152x864  75.00  
   1280x720  60.0050.0059.94  
   1024x768  75.0870.0760.00  
   832x624   74.55  
   800x600   72.1975.0060.3256.25  
   720x576   50.00  
   720x480   60.0059.94  
   640x480   75.0072.8166.6760.0059.94  
   720x400   70.08  
DP2-3 disconnected (normal left inverted right x axis y axis)
HDMI1 disconnected (normal left inverted right x axis y axis)
HDMI2 disconnected (normal left inverted right x axis y axis)
VIRTUAL1 disconnected (normal left inverted right x axis y axis)

kernel: BUG: unable to handle kernel NULL pointer dereference at 
0060
kernel: IP: [] intel_fb_obj_invalidate+0x1c/0xf0 [i915]
kernel: PGD c2f70067 PUD c2e8b067 PMD 0 
kernel: Oops:  [#1] PREEMPT SMP 
kernel: Modules linked in: fuse pci_stub vboxpci(O) bridge acpi_call(O) stp llc 
nf_log_ipv6 nf_log_ipv4 nf_log_common nft_redir_ipv4 nft_redir nf_nat_redirect 
nft_log nft_reject_inet nf_reject_ipv4 nf_reject_  ipv6 nft_reject 
nft_limit nft_meta nf_conntrack_ipv6 nf_defrag_ipv6 nft_ct nft_hash nft_rbtree 
nft_masq_ipv4 nf_nat_masquerade_ipv4 nft_masq nft_chain_nat_ipv4 
nf_conntrack_ipv4 nf_defrag_ipv4 nf_nat_ipv4 nf_nat nf_conntrack nf_tables_inet 
nf_tables_ipv6 nf_tables_ipv4 nf_tables nfnetlink sch_fq_codel zram 
lz4_compress vboxnetflt(O) vboxnetadp(O) snd_hda_codec_hdmi vboxdrv(O) iTCO_wdt 
iTCO_vendor_support nls_iso8859_1 usbserial udf crc_itu_t uas usb_storage tun 
nfs lockd grace sunrpc fscache loop iscsi_tcp libiscsi_tcp libiscsi 
scsi_transport_iscsi hfsplus hfs xfs libcrc32c intel_rapl crc32c_generic
kernel:  iosf_mbi nls_cp437 vfat x86_pkg_temp_thermal fat intel_powerclamp 
coretemp squashfs isofs kvm_intel btrfs kvm cdc_ether usbnet irqbypass r8152 
btusb btrtl btbcm xor btintel snd_hda_codec_realtek mii   mousedev 
joydev arc4 bluetooth snd_hda_codec_generic iwlmvm mac80211 pcspkr evdev 
input_leds mac_hid psmouse serio_raw iwlwifi intel_pch_thermal i2c_i801 
rtsx_pci_ms cfg80211 memstick thermal lpc_ich wmi i915 mei_me drm_kms_helper 
mei snd_hda_intel thinkpad_acpi battery snd_hda_codec nvram led_class ac rfkill 
snd_hda_core e1000e drm snd_hwdep ptp pps_core intel_gtt snd_pcm syscopyarea 
sysfillrect sysimgblt fb_sys_fops i2c_algo_bit fjes video snd_timer snd button 
shpchp soundcore tpm_tis tpm raid6_pq dummy dm_snapshot dm_bufio processor 
cdrom ip_tables x_tables ext4 crc16 mbcache jbd2 sha256_ssse3
kernel:  sha256_generic hmac drbg ansi_cprng dm_crypt algif_skcipher af_alg 
hid_generic usbhid hid dm_mod sd_mod rtsx_pci_sdmmc mmc_core atkbd libps2 
crct10dif_pclmul crc32_pclmul crc32c_intel aesni_intel aes  _x86_64 lrw 
gf128mul glue_helper ablk_helper cryptd ahci libahci libata scsi_mod ehci_pci 
xhci_pci ehci_hcd xhci_hcd rtsx_pci usbcore usb_common i8042 serio
kernel: CPU: 1 PID: 1417 Comm: Xorg Tainted: G U  W  O4.4.2-1-ARCH #1
kernel: Hardware name: LENOVO 20CLS06D00/20CLS06D00, BIOS N10ET41W (1.20 ) 
01/19/2016