[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/skl: Do not write the replay bit of the ring mode register for Gen 9

[Patchwork]

== Series Details ==

Series: drm/i915/skl: Do not write the replay bit of the ring mode register for 
Gen 9
URL   : https://patchwork.freedesktop.org/series/19875/
State : success

== Summary ==

Series 19875v1 drm/i915/skl: Do not write the replay bit of the ring mode 
register for Gen 9
https://patchwork.freedesktop.org/api/1.0/series/19875/revisions/1/mbox/

fi-bdw-5557u total:252  pass:241  dwarn:0   dfail:0   fail:0   skip:11 
fi-bsw-n3050 total:252  pass:213  dwarn:0   dfail:0   fail:0   skip:39 
fi-bxt-j4205 total:252  pass:233  dwarn:0   dfail:0   fail:0   skip:19 
fi-bxt-t5700 total:83   pass:70   dwarn:0   dfail:0   fail:0   skip:12 
fi-byt-j1900 total:252  pass:225  dwarn:0   dfail:0   fail:0   skip:27 
fi-byt-n2820 total:252  pass:221  dwarn:0   dfail:0   fail:0   skip:31 
fi-hsw-4770  total:252  pass:236  dwarn:0   dfail:0   fail:0   skip:16 
fi-hsw-4770r total:252  pass:236  dwarn:0   dfail:0   fail:0   skip:16 
fi-ilk-650   total:252  pass:202  dwarn:0   dfail:0   fail:0   skip:50 
fi-ivb-3520m total:252  pass:234  dwarn:0   dfail:0   fail:0   skip:18 
fi-ivb-3770  total:252  pass:234  dwarn:0   dfail:0   fail:0   skip:18 
fi-kbl-7500u total:252  pass:234  dwarn:0   dfail:0   fail:0   skip:18 
fi-skl-6260u total:252  pass:242  dwarn:0   dfail:0   fail:0   skip:10 
fi-skl-6700hqtotal:252  pass:235  dwarn:0   dfail:0   fail:0   skip:17 
fi-skl-6700k total:252  pass:230  dwarn:4   dfail:0   fail:0   skip:18 
fi-skl-6770hqtotal:252  pass:242  dwarn:0   dfail:0   fail:0   skip:10 
fi-snb-2520m total:252  pass:224  dwarn:0   dfail:0   fail:0   skip:28 
fi-snb-2600  total:252  pass:223  dwarn:0   dfail:0   fail:0   skip:29 

d13370a042e9d05329bcac34eb43c64e4f6704e0 drm-tip: 2017y-02m-17d-21h-23m-28s UTC 
integration manifest
8dcc17e drm/i915/skl: Do not write the replay bit of the ring mode register for 
Gen 9

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3892/
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[Intel-gfx] [PATCH] drm/i915/skl: Do not write the replay bit of the ring mode register for Gen 9

[Kelvin Gardiner]

The reply bit of the ring mode register is only valid on Gen 8.
Therefore do not write this for Gen 9.

Signed-off-by: Kelvin Gardiner 
---
 drivers/gpu/drm/i915/intel_lrc.c | 12 +---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index ee431d3..fa15377 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1259,9 +1259,15 @@ static int gen8_init_common_ring(struct intel_engine_cs 
*engine)
intel_engine_init_hangcheck(engine);
 
I915_WRITE(RING_HWSTAM(engine->mmio_base), 0x);
-   I915_WRITE(RING_MODE_GEN7(engine),
-  _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
-  _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
+
+   if (INTEL_GEN(dev_priv) >= 9)
+   I915_WRITE(RING_MODE_GEN7(engine),
+   _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
+   else
+   I915_WRITE(RING_MODE_GEN7(engine),
+   _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
+   _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
+
I915_WRITE(RING_HWS_PGA(engine->mmio_base),
   engine->status_page.ggtt_offset);
POSTING_READ(RING_HWS_PGA(engine->mmio_base));
-- 
1.9.1

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Re: [Intel-gfx] [PATCH] drm/i915/guc: Add onion teardown to the GuC setup

[Daniele Ceraolo Spurio]

On 16/02/17 06:18, Oscar Mateo wrote:

Starting with intel_guc_loader, down to intel_guc_submission
and finally to intel_guc_log.

Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_guc_submission.c |  94 +
 drivers/gpu/drm/i915/intel_guc_loader.c|  19 +-
 drivers/gpu/drm/i915/intel_guc_log.c   | 309 +++--
 drivers/gpu/drm/i915/intel_uc.h|   5 +-
 4 files changed, 229 insertions(+), 198 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
b/drivers/gpu/drm/i915/i915_guc_submission.c
index f7d9897..4147674 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -609,8 +609,14 @@ struct i915_vma *intel_guc_allocate_vma(struct intel_guc 
*guc, u32 size)
return vma;
 }

-static void guc_client_free(struct i915_guc_client *client)
+static void guc_client_free(struct i915_guc_client **p_client)
 {
+   struct i915_guc_client *client;
+
+   client = fetch_and_zero(p_client);
+   if (!client)
+   return;
+


This works now, but it might become risky if we have multiple clients in 
the future because we might do something like the following:


for_each_guc_client(client, guc->client_list, ...)
guc_client_free();


/*
 * XXX: wait for any outstanding submissions before freeing memory.
 * Be sure to drop any locks
@@ -818,7 +824,7 @@ static void guc_policies_init(struct guc_policies *policies)
policies->is_valid = 1;
 }

-static void guc_addon_create(struct intel_guc *guc)
+static int guc_addon_create(struct intel_guc *guc)
 {
struct drm_i915_private *dev_priv = guc_to_i915(guc);
struct i915_vma *vma;
@@ -835,14 +841,11 @@ static void guc_addon_create(struct intel_guc *guc)
sizeof(struct guc_mmio_reg_state) +
GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE;

-   vma = guc->ads_vma;
-   if (!vma) {


I believe the if was here to avoid re-allocating the vma if this 
function was called after a GPU reset. I agree that the check should be 
outside this function (and it already is), but we might want to still 
add here something like:


if (WARN_ON(guc->ads_vma))
return 0;


-   vma = intel_guc_allocate_vma(guc, PAGE_ALIGN(size));
-   if (IS_ERR(vma))
-   return;
+   vma = intel_guc_allocate_vma(guc, PAGE_ALIGN(size));
+   if (IS_ERR(vma))
+   return PTR_ERR(vma);

-   guc->ads_vma = vma;
-   }
+   guc->ads_vma = vma;

page = i915_vma_first_page(vma);
ads = kmap(page);
@@ -885,6 +888,13 @@ static void guc_addon_create(struct intel_guc *guc)
sizeof(struct guc_mmio_reg_state);

kunmap(page);
+
+   return 0;
+}
+
+static void guc_addon_destroy(struct intel_guc *guc)
+{
+   i915_vma_unpin_and_release(>ads_vma);
 }

 /*
@@ -899,6 +909,7 @@ int i915_guc_submission_init(struct drm_i915_private 
*dev_priv)
struct intel_guc *guc = _priv->guc;
struct i915_vma *vma;
void *vaddr;
+   int ret;

if (!HAS_GUC_SCHED(dev_priv))
return 0;
@@ -919,15 +930,23 @@ int i915_guc_submission_init(struct drm_i915_private 
*dev_priv)

guc->ctx_pool = vma;

-   vaddr = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
-   if (IS_ERR(vaddr))
-   goto err;
+   vaddr = i915_gem_object_pin_map(guc->ctx_pool->obj, I915_MAP_WB);
+   if (IS_ERR(vaddr)) {
+   ret = PTR_ERR(vaddr);
+   goto err_vma;
+   }

guc->ctx_pool_vaddr = vaddr;

+   ret = intel_guc_log_create(guc);
+   if (ret < 0)
+   goto err_vaddr;
+
+   ret = guc_addon_create(guc);
+   if (ret < 0)
+   goto err_log;
+
ida_init(>ctx_ids);
-   intel_guc_log_create(guc);
-   guc_addon_create(guc);

guc->execbuf_client = guc_client_alloc(dev_priv,
   INTEL_INFO(dev_priv)->ring_mask,
@@ -935,14 +954,33 @@ int i915_guc_submission_init(struct drm_i915_private 
*dev_priv)
   dev_priv->kernel_context);
if (IS_ERR(guc->execbuf_client)) {
DRM_ERROR("Failed to create GuC client for execbuf!\n");
-   goto err;
+   ret = PTR_ERR(guc->execbuf_client);
+   goto err_ads;
}

return 0;
+err_ads:
+   guc_addon_destroy(guc);
+err_log:
+   intel_guc_log_destroy(guc);
+err_vaddr:
+   i915_gem_object_unpin_map(guc->ctx_pool->obj);
+err_vma:
+   i915_vma_unpin_and_release(>ctx_pool);

-err:
-   i915_guc_submission_fini(dev_priv);
-   return -ENOMEM;
+   return ret;
+}
+
+void i915_guc_submission_fini(struct drm_i915_private *dev_priv)
+{
+   struct intel_guc *guc = _priv->guc;
+


if I'm 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Extract the in-fence from a dma-buf reservation object (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Extract the in-fence from a dma-buf reservation object (rev2)
URL   : https://patchwork.freedesktop.org/series/19874/
State : success

== Summary ==

Series 19874v2 drm/i915: Extract the in-fence from a dma-buf reservation object
https://patchwork.freedesktop.org/api/1.0/series/19874/revisions/2/mbox/

Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass   -> DMESG-WARN (fi-ivb-3520m) fdo#99847

fdo#99847 https://bugs.freedesktop.org/show_bug.cgi?id=99847

fi-bdw-5557u total:252  pass:241  dwarn:0   dfail:0   fail:0   skip:11 
fi-bsw-n3050 total:252  pass:213  dwarn:0   dfail:0   fail:0   skip:39 
fi-bxt-j4205 total:252  pass:233  dwarn:0   dfail:0   fail:0   skip:19 
fi-bxt-t5700 total:83   pass:70   dwarn:0   dfail:0   fail:0   skip:12 
fi-byt-j1900 total:252  pass:225  dwarn:0   dfail:0   fail:0   skip:27 
fi-byt-n2820 total:252  pass:221  dwarn:0   dfail:0   fail:0   skip:31 
fi-hsw-4770  total:252  pass:236  dwarn:0   dfail:0   fail:0   skip:16 
fi-hsw-4770r total:252  pass:236  dwarn:0   dfail:0   fail:0   skip:16 
fi-ilk-650   total:252  pass:202  dwarn:0   dfail:0   fail:0   skip:50 
fi-ivb-3520m total:252  pass:233  dwarn:1   dfail:0   fail:0   skip:18 
fi-ivb-3770  total:252  pass:234  dwarn:0   dfail:0   fail:0   skip:18 
fi-kbl-7500u total:252  pass:234  dwarn:0   dfail:0   fail:0   skip:18 
fi-skl-6260u total:252  pass:242  dwarn:0   dfail:0   fail:0   skip:10 
fi-skl-6700hqtotal:252  pass:235  dwarn:0   dfail:0   fail:0   skip:17 
fi-skl-6700k total:252  pass:230  dwarn:4   dfail:0   fail:0   skip:18 
fi-skl-6770hqtotal:252  pass:242  dwarn:0   dfail:0   fail:0   skip:10 
fi-snb-2520m total:252  pass:224  dwarn:0   dfail:0   fail:0   skip:28 
fi-snb-2600  total:252  pass:223  dwarn:0   dfail:0   fail:0   skip:29 

d13370a042e9d05329bcac34eb43c64e4f6704e0 drm-tip: 2017y-02m-17d-21h-23m-28s UTC 
integration manifest
3696557 drm/i915: Extract the in-fence from a dma-buf reservation object

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3891/
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Re: [Intel-gfx] [PATCH] drm/i915: Only start with the fake-irq timer if interrupts are dead

[Chris Wilson]

On Fri, Feb 17, 2017 at 02:59:44PM +, Tvrtko Ursulin wrote:
> 
> On 17/02/2017 11:55, Chris Wilson wrote:
> >As a backup to waiting on a user-interrupt from the GPU, we use a heavy
> >and frequent timer to wake up the waiting process should we detect an
> >inconsistency whilst waiting. After seeing a "missed interrupt", the
> >next time we wait, we restart the heavy timer. This patch is more
> >reluctant to restart the timer and will only do so if we have not see any
> >interrupts since when we started the fake irq timer. If we are seeing
> >interrupts, then the waiters are being woken normally and we had an
> >incoherency that caused to miss last time - that is unlikely to reoccur
> >and so taking the risk of stalling again seems pragmatic.
> >
> >Signed-off-by: Chris Wilson 
> >Cc: Tvrtko Ursulin 
> >Cc: Mika Kuoppala 

> Very soothing now that I have discovered the pre-existing behaviour. :)
> 
> Reviewed-by: Tvrtko Ursulin 

Thanks both of you for the review and suggestions, pushed to try and
soothe CI even more.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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[Intel-gfx] [RFCv2] drm/i915: Extract the in-fence from a dma-buf reservation object

[Chris Wilson]

The dma-buf holds an array of fences, which unlike the sync_file are not
sealed and may be modified at runtime. For the purpose of computing
dependencies, we can take a snapshot of the fences within the
dma-buf's reservation object (converting them into a fence-array) and
uses that as our input fence to this execbuf. It also provides a means
for us to pass in an array of fences and ask to only wait on the first
being signaled.

In short, it allows dma-buf to be used as a *reusable* container for
multiple signaling objects, and for scheduling execbuf between clients.

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
Cc: Mika Kuoppala 
Cc: Joonas Lahtinen 
Cc: Jason Ekstrand 
Cc: Gustavo Padovan 
---
 drivers/gpu/drm/i915/i915_drv.c|  1 +
 drivers/gpu/drm/i915/i915_gem_execbuffer.c | 62 --
 include/uapi/drm/i915_drm.h| 26 +++--
 3 files changed, 83 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 43da9cf65233..de8f40b0bd58 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -352,6 +352,7 @@ static int i915_getparam(struct drm_device *dev, void *data,
case I915_PARAM_HAS_EXEC_SOFTPIN:
case I915_PARAM_HAS_EXEC_ASYNC:
case I915_PARAM_HAS_EXEC_FENCE:
+   case I915_PARAM_HAS_EXEC_FENCE_DMABUF:
/* For the time being all of these are always true;
 * if some supported hardware does not have one of these
 * features this value needs to be provided from
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c 
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index da0846fe2ad6..eb9b9e333b9b 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -26,6 +26,7 @@
  *
  */
 
+#include 
 #include 
 #include 
 #include 
@@ -1576,6 +1577,49 @@ eb_select_engine(struct drm_i915_private *dev_priv,
return engine;
 }
 
+static struct dma_fence *
+dma_buf_get_fence(int fd, unsigned int flags)
+{
+   struct dma_buf *dmabuf;
+   struct dma_fence_array *array;
+   struct dma_fence **shared, *excl;
+   unsigned int count, i;
+
+   dmabuf = dma_buf_get(fd);
+   if (IS_ERR(dmabuf))
+   return ERR_CAST(dmabuf);
+
+   shared = NULL;
+   count = 0;
+   if (flags & I915_EXEC_FENCE_EXCL) {
+   excl = reservation_object_get_excl_rcu(dmabuf->resv);
+   } else {
+   int err;
+
+   err = reservation_object_get_fences_rcu(dmabuf->resv,
+   , , );
+   if (err) {
+   array = ERR_PTR(err);
+   goto out_put;
+   }
+   }
+
+   if (excl)
+   array = dma_fence_array_create(1, , 0, 0, false);
+   else if (shared)
+   array = dma_fence_array_create(count, shared, 0, 0,
+  flags & I915_EXEC_FENCE_ANY);
+   else
+   array = NULL;
+
+   for (i = 0 ; i < count; i++)
+   dma_fence_put(shared[i]);
+   kfree(shared);
+out_put:
+   dma_buf_put(dmabuf);
+   return >base;
+}
+
 static int
 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
   struct drm_file *file,
@@ -1640,9 +1684,21 @@ i915_gem_do_execbuffer(struct drm_device *dev, void 
*data,
}
 
if (args->flags & I915_EXEC_FENCE_IN) {
-   in_fence = sync_file_get_fence(lower_32_bits(args->rsvd2));
-   if (!in_fence)
-   return -EINVAL;
+   int fd = lower_32_bits(args->rsvd2);
+
+   in_fence = dma_buf_get_fence(fd, args->flags);
+   if (IS_ERR(in_fence)) {
+   if (in_fence != ERR_PTR(-EINVAL))
+   return PTR_ERR(in_fence);
+
+   if (args->flags &
+   (I915_EXEC_FENCE_ANY | I915_EXEC_FENCE_EXCL))
+   return -EINVAL;
+
+   in_fence = sync_file_get_fence(fd);
+   if (!in_fence)
+   return -EINVAL;
+   }
}
 
if (args->flags & I915_EXEC_FENCE_OUT) {
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 3554495bef13..ebc7641b5252 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -412,6 +412,12 @@ typedef struct drm_i915_irq_wait {
  */
 #define I915_PARAM_HAS_EXEC_FENCE   44
 
+/* Query whether DRM_I915_GEM_EXECBUFFER2 supports using a dma-buf fd as the
+ * in-fence for explicit fence support. See I915_EXEC_FENCE_IN and
+ * I915_EXEC_FENCE_ANY.
+ */

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] dma-fence: Flag when a fence-array is using signal-on-any

[Patchwork]

== Series Details ==

Series: series starting with [1/2] dma-fence: Flag when a fence-array is using 
signal-on-any
URL   : https://patchwork.freedesktop.org/series/19865/
State : success

== Summary ==

Series 19865v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/19865/revisions/1/mbox/

fi-bdw-5557u total:252  pass:241  dwarn:0   dfail:0   fail:0   skip:11 
fi-bsw-n3050 total:252  pass:213  dwarn:0   dfail:0   fail:0   skip:39 
fi-bxt-j4205 total:252  pass:233  dwarn:0   dfail:0   fail:0   skip:19 
fi-bxt-t5700 total:83   pass:70   dwarn:0   dfail:0   fail:0   skip:12 
fi-byt-j1900 total:252  pass:225  dwarn:0   dfail:0   fail:0   skip:27 
fi-byt-n2820 total:252  pass:221  dwarn:0   dfail:0   fail:0   skip:31 
fi-hsw-4770  total:252  pass:236  dwarn:0   dfail:0   fail:0   skip:16 
fi-hsw-4770r total:252  pass:236  dwarn:0   dfail:0   fail:0   skip:16 
fi-ilk-650   total:252  pass:202  dwarn:0   dfail:0   fail:0   skip:50 
fi-ivb-3520m total:252  pass:234  dwarn:0   dfail:0   fail:0   skip:18 
fi-ivb-3770  total:252  pass:234  dwarn:0   dfail:0   fail:0   skip:18 
fi-kbl-7500u total:252  pass:234  dwarn:0   dfail:0   fail:0   skip:18 
fi-skl-6260u total:252  pass:242  dwarn:0   dfail:0   fail:0   skip:10 
fi-skl-6700hqtotal:252  pass:235  dwarn:0   dfail:0   fail:0   skip:17 
fi-skl-6700k total:252  pass:230  dwarn:4   dfail:0   fail:0   skip:18 
fi-skl-6770hqtotal:252  pass:242  dwarn:0   dfail:0   fail:0   skip:10 
fi-snb-2520m total:252  pass:224  dwarn:0   dfail:0   fail:0   skip:28 
fi-snb-2600  total:252  pass:223  dwarn:0   dfail:0   fail:0   skip:29 

02022d17a5787709617b7897de3906970e2b0721 drm-tip: 2017y-02m-17d-15h-15m-45s UTC 
integration manifest
e97cc1a drm/i915: Avoid decomposing a signal-on-any fence-array
15dffc7 dma-fence: Flag when a fence-array is using signal-on-any

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3890/
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[Intel-gfx] [RFC] drm/i915: Extract the in-fence from a dma-buf reservation object

[Chris Wilson]

The dma-buf holds an array of fences, which unlike the sync_file are not
sealed and may be modified at runtime. For the purpose of computing
dependencies, we can take a snapshot of the fences within the
dma-buf's reservation object (converting them into a fence-array) and
uses that as our input fence to this execbuf. It also provides a means
for us to pass in an array of fences and ask to only wait on the first
being signaled.

In short, it allows dma-buf to be used as a *reusable* container for
multiple signaling objects, and for scheduling execbuf between clients.

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
Cc: Mika Kuoppala 
Cc: Joonas Lahtinen 
Cc: Jason Ekstrand 
Cc: Gustavo Padovan 
---
 drivers/gpu/drm/i915/i915_drv.c|  1 +
 drivers/gpu/drm/i915/i915_gem_execbuffer.c | 57 --
 include/uapi/drm/i915_drm.h| 26 --
 3 files changed, 78 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 43da9cf65233..de8f40b0bd58 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -352,6 +352,7 @@ static int i915_getparam(struct drm_device *dev, void *data,
case I915_PARAM_HAS_EXEC_SOFTPIN:
case I915_PARAM_HAS_EXEC_ASYNC:
case I915_PARAM_HAS_EXEC_FENCE:
+   case I915_PARAM_HAS_EXEC_FENCE_DMABUF:
/* For the time being all of these are always true;
 * if some supported hardware does not have one of these
 * features this value needs to be provided from
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c 
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index da0846fe2ad6..957d57524483 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -26,6 +26,7 @@
  *
  */
 
+#include 
 #include 
 #include 
 #include 
@@ -1576,6 +1577,44 @@ eb_select_engine(struct drm_i915_private *dev_priv,
return engine;
 }
 
+static struct dma_fence *
+dma_buf_get_fence(int fd, unsigned int flags)
+{
+   struct dma_buf *dmabuf;
+   struct dma_fence_array *array;
+   struct dma_fence **shared, *excl;
+   unsigned int count, i;
+
+   dmabuf = dma_buf_get(fd);
+   if (IS_ERR(dmabuf))
+   return ERR_CAST(dmabuf);
+
+   shared = NULL;
+   count = 0;
+   if (flags & I915_EXEC_FENCE_EXCL) {
+   excl = reservation_object_get_excl_rcu(obj->resv);
+   } else {
+   if (reservation_object_get_fences_rcu(dmabuf->resv,
+ , , ))
+   goto out_put;
+   }
+
+   if (excl)
+   array = dma_fence_array_create(1, , 0, 0, false);
+   else if (shared)
+   array = dma_fence_array_create(count, shared, 0, 0,
+  flags & I915_EXEC_FENCE_ANY);
+   else
+   array = NULL;
+
+   for (i = 0 ; i < count; i++)
+   dma_fence_put(shared[i]);
+   kfree(shared);
+out_put:
+   dma_buf_put(dmabuf);
+   return >base;
+}
+
 static int
 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
   struct drm_file *file,
@@ -1640,9 +1679,21 @@ i915_gem_do_execbuffer(struct drm_device *dev, void 
*data,
}
 
if (args->flags & I915_EXEC_FENCE_IN) {
-   in_fence = sync_file_get_fence(lower_32_bits(args->rsvd2));
-   if (!in_fence)
-   return -EINVAL;
+   int fd = lower_32_bits(args->rsvd2);
+
+   in_fence = dma_buf_get_fence(fd, args->flags);
+   if (IS_ERR(in_fence)) {
+   if (in_fence == ERR_PTR(-EINVAL)) {
+   if (args->flags & (I915_EXEC_FENCE_ANY | 
I915_EXEC_FENCE_EXCL))
+   return -EINVAL;
+
+   in_fence = sync_file_get_fence(fd);
+   if (!in_fence)
+   return -EINVAL;
+   } else {
+   return PTR_ERR(in_fance);
+   }
+   }
}
 
if (args->flags & I915_EXEC_FENCE_OUT) {
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 3554495bef13..ebc7641b5252 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -412,6 +412,12 @@ typedef struct drm_i915_irq_wait {
  */
 #define I915_PARAM_HAS_EXEC_FENCE   44
 
+/* Query whether DRM_I915_GEM_EXECBUFFER2 supports using a dma-buf fd as the
+ * in-fence for explicit fence support. See I915_EXEC_FENCE_IN and
+ * I915_EXEC_FENCE_ANY.
+ */
+#define I915_PARAM_HAS_EXEC_FENCE_DMABUF 45
+
 typedef 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Assert that the request->tail is always qword aligned

[Patchwork]

== Series Details ==

Series: drm/i915: Assert that the request->tail is always qword aligned
URL   : https://patchwork.freedesktop.org/series/19860/
State : success

== Summary ==

Series 19860v1 drm/i915: Assert that the request->tail is always qword aligned
https://patchwork.freedesktop.org/api/1.0/series/19860/revisions/1/mbox/

fi-bdw-5557u total:252  pass:241  dwarn:0   dfail:0   fail:0   skip:11 
fi-bsw-n3050 total:252  pass:213  dwarn:0   dfail:0   fail:0   skip:39 
fi-bxt-j4205 total:252  pass:233  dwarn:0   dfail:0   fail:0   skip:19 
fi-bxt-t5700 total:83   pass:70   dwarn:0   dfail:0   fail:0   skip:12 
fi-byt-j1900 total:252  pass:225  dwarn:0   dfail:0   fail:0   skip:27 
fi-byt-n2820 total:252  pass:221  dwarn:0   dfail:0   fail:0   skip:31 
fi-hsw-4770  total:252  pass:236  dwarn:0   dfail:0   fail:0   skip:16 
fi-hsw-4770r total:252  pass:236  dwarn:0   dfail:0   fail:0   skip:16 
fi-ilk-650   total:252  pass:202  dwarn:0   dfail:0   fail:0   skip:50 
fi-ivb-3520m total:252  pass:234  dwarn:0   dfail:0   fail:0   skip:18 
fi-ivb-3770  total:252  pass:234  dwarn:0   dfail:0   fail:0   skip:18 
fi-kbl-7500u total:252  pass:234  dwarn:0   dfail:0   fail:0   skip:18 
fi-skl-6260u total:252  pass:242  dwarn:0   dfail:0   fail:0   skip:10 
fi-skl-6700hqtotal:252  pass:235  dwarn:0   dfail:0   fail:0   skip:17 
fi-skl-6700k total:252  pass:230  dwarn:4   dfail:0   fail:0   skip:18 
fi-skl-6770hqtotal:252  pass:242  dwarn:0   dfail:0   fail:0   skip:10 
fi-snb-2520m total:252  pass:224  dwarn:0   dfail:0   fail:0   skip:28 
fi-snb-2600  total:252  pass:223  dwarn:0   dfail:0   fail:0   skip:29 

02022d17a5787709617b7897de3906970e2b0721 drm-tip: 2017y-02m-17d-15h-15m-45s UTC 
integration manifest
1a277bb drm/i915: Assert that the request->tail is always qword aligned

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3889/
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Re: [Intel-gfx] [PATCH 2/4] drm/i915: add intel_calc_cdclk()

[Ville Syrjälä]

On Fri, Feb 17, 2017 at 06:37:23PM -0200, Paulo Zanoni wrote:
> Em Sex, 2017-02-17 às 15:49 +0200, Ville Syrjälä escreveu:
> > On Fri, Feb 17, 2017 at 11:22:05AM -0200, Paulo Zanoni wrote:
> > > 
> > > Each x_modeset_calc_cdclk() has to do the same platform checks
> > > twice,
> > > so extract them to a single function. This way, the platform checks
> > > are all in the same place, and the platform-common code gets rid of
> > > all the platform-specific checks, which IMHO makes the code easier
> > > to
> > > read.
> > > 
> > > Signed-off-by: Paulo Zanoni 
> > > ---
> > >  drivers/gpu/drm/i915/intel_cdclk.c | 84 
> > > --
> > >  1 file changed, 45 insertions(+), 39 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
> > > b/drivers/gpu/drm/i915/intel_cdclk.c
> > > index d505ff1..6efc5f4 100644
> > > --- a/drivers/gpu/drm/i915/intel_cdclk.c
> > > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> > > @@ -1496,6 +1496,47 @@ static int intel_max_pixel_rate(struct
> > > drm_atomic_state *state)
> > >   return max_pixel_rate;
> > >  }
> > >  
> > > +static void intel_calc_cdclk(struct intel_atomic_state *state, int
> > > max_pixclk,
> > > +  int *cdclk, int *vco)
> > > +{
> > > + struct drm_i915_private *dev_priv = to_i915(state-
> > > >base.dev);
> > > +
> > > + switch (INTEL_INFO(dev_priv)->platform) {
> > > + case INTEL_VALLEYVIEW:
> > > + case INTEL_CHERRYVIEW:
> > > + *cdclk = vlv_calc_cdclk(dev_priv, max_pixclk);
> > > + break;
> > > + case INTEL_BROADWELL:
> > > + /*
> > > +  * FIXME: should also account for plane ratio once
> > > 64bpp pixel
> > > +  * formats are supported.
> > > +  */
> > > + *cdclk = bdw_calc_cdclk(max_pixclk);
> > > + break;
> > > + case INTEL_SKYLAKE:
> > > + case INTEL_KABYLAKE:
> > > + /*
> > > +  * FIXME: should also account for plane ratio once
> > > 64bpp pixel
> > > +  * formats are supported.
> > > +  */
> > > + *vco = state->cdclk.logical.vco;
> > > + if (!*vco)
> > > + *vco = dev_priv->skl_preferred_vco_freq;
> > > + *cdclk = skl_calc_cdclk(max_pixclk, *vco);
> > > + break;
> > > + case INTEL_BROXTON:
> > > + *cdclk = bxt_calc_cdclk(max_pixclk);
> > > + *vco = bxt_de_pll_vco(dev_priv, *cdclk);
> > > + break;
> > > + case INTEL_GEMINILAKE:
> > > + *cdclk = glk_calc_cdclk(max_pixclk);
> > > + *vco = glk_de_pll_vco(dev_priv, *cdclk);
> > > + break;
> > > + default:
> > > + MISSING_CASE(INTEL_INFO(dev_priv)->platform);
> > > + }
> > > +}
> > 
> > How about just replacing the .modeset_calc_cdclk() vfunc with a
> > slightly
> > lower level vfunc that just computes the cdclk/vco/whatever without
> > containing the active_crtcs logic?
> > 
> > Then we should have just
> > 
> > intel_modeset_calc_cdclk()
> > {
> > .calc_cdclk(logical, max_pixclk);
> > 
> > /*
> >  * maybe keep the max_cdclk check here, although it that
> >  * happens I think we have a bug somewhere, so perhaps
> >  * just convert it into a WARN, or drop entirely.
> >  */
> > 
> > if (!active_crtcs)
> > .calc_cdclk(actual, 0);
> > else
> > actual = logical;
> > }
> 
> Yeah, the code above is definitely a next step to the changes I did.
> 
> I'm just not a big fan of the .calc_cdclk vfunc since it will be just 2
> lines for each platform. Unless I inline them with the *real*
> x_calc_cdclk() funcs we have today, but then I'll have to check their
> other callers. So I'll take a look and try to submit a new patch.

At some point I had this idea of making the cdclk computation more data
driven. As in we'd store the various possible cdclk steps, required
guarbands etc. in some structure and thus avoid all the calc_cdclk()
functions which are mostly just if ladders with slightly different
numbers in them. But I never actually tried it, so not sure how
pretty/ugly it would turn out to be.

In the meantime, I think I'd prefer two line functions over the switch
statement. For one, it would allow us to keep the calculation part right
next to the other cdclk stuff for said platform. One thing that's a
slight concern is the future dvfs stuff we talked about. I've not yet
fully thought out where that needs to be done, but it might be that
some of it might nicely land in these two line function (making them
at least three lines ;).

-- 
Ville Syrjälä
Intel OTC
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Re: [Intel-gfx] [PATCH 2/4] drm/i915: add intel_calc_cdclk()

[Paulo Zanoni]

Em Sex, 2017-02-17 às 15:49 +0200, Ville Syrjälä escreveu:
> On Fri, Feb 17, 2017 at 11:22:05AM -0200, Paulo Zanoni wrote:
> > 
> > Each x_modeset_calc_cdclk() has to do the same platform checks
> > twice,
> > so extract them to a single function. This way, the platform checks
> > are all in the same place, and the platform-common code gets rid of
> > all the platform-specific checks, which IMHO makes the code easier
> > to
> > read.
> > 
> > Signed-off-by: Paulo Zanoni 
> > ---
> >  drivers/gpu/drm/i915/intel_cdclk.c | 84 
> > --
> >  1 file changed, 45 insertions(+), 39 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
> > b/drivers/gpu/drm/i915/intel_cdclk.c
> > index d505ff1..6efc5f4 100644
> > --- a/drivers/gpu/drm/i915/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> > @@ -1496,6 +1496,47 @@ static int intel_max_pixel_rate(struct
> > drm_atomic_state *state)
> >     return max_pixel_rate;
> >  }
> >  
> > +static void intel_calc_cdclk(struct intel_atomic_state *state, int
> > max_pixclk,
> > +    int *cdclk, int *vco)
> > +{
> > +   struct drm_i915_private *dev_priv = to_i915(state-
> > >base.dev);
> > +
> > +   switch (INTEL_INFO(dev_priv)->platform) {
> > +   case INTEL_VALLEYVIEW:
> > +   case INTEL_CHERRYVIEW:
> > +   *cdclk = vlv_calc_cdclk(dev_priv, max_pixclk);
> > +   break;
> > +   case INTEL_BROADWELL:
> > +   /*
> > +    * FIXME: should also account for plane ratio once
> > 64bpp pixel
> > +    * formats are supported.
> > +    */
> > +   *cdclk = bdw_calc_cdclk(max_pixclk);
> > +   break;
> > +   case INTEL_SKYLAKE:
> > +   case INTEL_KABYLAKE:
> > +   /*
> > +    * FIXME: should also account for plane ratio once
> > 64bpp pixel
> > +    * formats are supported.
> > +    */
> > +   *vco = state->cdclk.logical.vco;
> > +   if (!*vco)
> > +   *vco = dev_priv->skl_preferred_vco_freq;
> > +   *cdclk = skl_calc_cdclk(max_pixclk, *vco);
> > +   break;
> > +   case INTEL_BROXTON:
> > +   *cdclk = bxt_calc_cdclk(max_pixclk);
> > +   *vco = bxt_de_pll_vco(dev_priv, *cdclk);
> > +   break;
> > +   case INTEL_GEMINILAKE:
> > +   *cdclk = glk_calc_cdclk(max_pixclk);
> > +   *vco = glk_de_pll_vco(dev_priv, *cdclk);
> > +   break;
> > +   default:
> > +   MISSING_CASE(INTEL_INFO(dev_priv)->platform);
> > +   }
> > +}
> 
> How about just replacing the .modeset_calc_cdclk() vfunc with a
> slightly
> lower level vfunc that just computes the cdclk/vco/whatever without
> containing the active_crtcs logic?
> 
> Then we should have just
> 
> intel_modeset_calc_cdclk()
> {
>   .calc_cdclk(logical, max_pixclk);
> 
>   /*
>* maybe keep the max_cdclk check here, although it that
>* happens I think we have a bug somewhere, so perhaps
>* just convert it into a WARN, or drop entirely.
>*/
> 
>   if (!active_crtcs)
>   .calc_cdclk(actual, 0);
>   else
>   actual = logical;
> }

Yeah, the code above is definitely a next step to the changes I did.

I'm just not a big fan of the .calc_cdclk vfunc since it will be just 2
lines for each platform. Unless I inline them with the *real*
x_calc_cdclk() funcs we have today, but then I'll have to check their
other callers. So I'll take a look and try to submit a new patch.

> 
> 
> > 
> > +
> >  static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state)
> >  {
> >     struct drm_i915_private *dev_priv = to_i915(state->dev);
> > @@ -1503,14 +1544,7 @@ static int vlv_modeset_calc_cdclk(struct
> > drm_atomic_state *state)
> >     int max_pixclk = intel_max_pixel_rate(state);
> >     int cdclk;
> >  
> > -   /*
> > -    * FIXME: Broadwell should also account for plane ratio
> > once 64bpp pixel
> > -    * formats are supported.
> > -    */
> > -   if (IS_BROADWELL(dev_priv))
> > -   cdclk = bdw_calc_cdclk(max_pixclk);
> > -   else
> > -   cdclk = vlv_calc_cdclk(dev_priv, max_pixclk);
> > +   intel_calc_cdclk(intel_state, max_pixclk, , NULL);
> >  
> >     if (cdclk > dev_priv->max_cdclk_freq) {
> >     DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds
> > max (%d kHz)\n",
> > @@ -1521,11 +1555,7 @@ static int vlv_modeset_calc_cdclk(struct
> > drm_atomic_state *state)
> >     intel_state->cdclk.logical.cdclk = cdclk;
> >  
> >     if (!intel_state->active_crtcs) {
> > -   if (IS_BROADWELL(dev_priv))
> > -   cdclk = bdw_calc_cdclk(0);
> > -   else
> > -   cdclk = vlv_calc_cdclk(dev_priv, 0);
> > -
> > +   intel_calc_cdclk(intel_state, 0, , NULL);
> >     intel_state->cdclk.actual.cdclk = cdclk;
> >     } else {
> >     intel_state->cdclk.actual = intel_state-
> > >cdclk.logical;
> > @@ -1541,22 +1571,7 @@ 

Re: [Intel-gfx] [PATCH] drm/i915: Fix legacy cursor vs. watermarks for ILK-BDW

[Ville Syrjälä]

On Fri, Feb 17, 2017 at 09:04:44PM +0100, Uwe Kleine-König wrote:
> Hello Ville,
> 
> On Fri, Feb 17, 2017 at 05:01:59PM +0200, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä 
> > 
> > In order to make cursor updates actually safe wrt. watermark programming
> > we have to clear the legacy_cursor_update flag in the atomic state. That
> > will cause the regular atomic update path to do the necessary vblank
> > wait after the plane update if needed, otherwise the vblank wait would
> > be skipped and we'd feed the optimal watermarks to the hardware before
> > the plane update has actually happened.
> > 
> > [...]
> > 
> > Cc: Maarten Lankhorst 
> > Cc: Daniel Vetter 
> > Cc: Uwe Kleine-König 
> > Reported-by: Uwe Kleine-König 
> > Fixes: f79f26921ee1 ("drm/i915: Add a cursor hack to allow converting 
> > legacy page flip to atomic, v3.")
> > Signed-off-by: Ville Syrjälä 
> 
> Is this supposed to fix
> https://bugs.freedesktop.org/show_bug.cgi?id=98742 ? If so, the Fixes:
> line seems wrong because f79f26921ee1 isn't in 4.9 where I see the
> issue.
> 
> If I want to fix 4.9---my ultimate goal is to fix the kernel that will
> go into the next stable release---I have to cherry-pick f79f26921ee1
> first, I assume?

Argh. The fact is that it has actually been broken since forever,
but I suppose *something* must have been masking the problem for
you on earlier kernels, well, assuming you didn't actually hit the
problem before 4.9.

You can give backporting the custom legacy cursor path a try,
but I'm not sure how badly it depends on other things. So not
sure a backport is entirely trivial. Maarten, any thoughts?

-- 
Ville Syrjälä
Intel OTC
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Re: [Intel-gfx] [PATCH] drm/i915: Fix legacy cursor vs. watermarks for ILK-BDW

[Uwe Kleine-König]

Hello Ville,

On Fri, Feb 17, 2017 at 05:01:59PM +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä 
> 
> In order to make cursor updates actually safe wrt. watermark programming
> we have to clear the legacy_cursor_update flag in the atomic state. That
> will cause the regular atomic update path to do the necessary vblank
> wait after the plane update if needed, otherwise the vblank wait would
> be skipped and we'd feed the optimal watermarks to the hardware before
> the plane update has actually happened.
> 
> [...]
> 
> Cc: Maarten Lankhorst 
> Cc: Daniel Vetter 
> Cc: Uwe Kleine-König 
> Reported-by: Uwe Kleine-König 
> Fixes: f79f26921ee1 ("drm/i915: Add a cursor hack to allow converting legacy 
> page flip to atomic, v3.")
> Signed-off-by: Ville Syrjälä 

Is this supposed to fix
https://bugs.freedesktop.org/show_bug.cgi?id=98742 ? If so, the Fixes:
line seems wrong because f79f26921ee1 isn't in 4.9 where I see the
issue.

If I want to fix 4.9---my ultimate goal is to fix the kernel that will
go into the next stable release---I have to cherry-pick f79f26921ee1
first, I assume?

Best regards
Uwe


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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix clearing of BIOS power well requests (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Fix clearing of BIOS power well requests (rev2)
URL   : https://patchwork.freedesktop.org/series/19699/
State : success

== Summary ==

Series 19699v2 drm/i915: Fix clearing of BIOS power well requests
https://patchwork.freedesktop.org/api/1.0/series/19699/revisions/2/mbox/

fi-bdw-5557u total:252  pass:241  dwarn:0   dfail:0   fail:0   skip:11 
fi-bsw-n3050 total:252  pass:213  dwarn:0   dfail:0   fail:0   skip:39 
fi-bxt-j4205 total:252  pass:233  dwarn:0   dfail:0   fail:0   skip:19 
fi-bxt-t5700 total:83   pass:70   dwarn:0   dfail:0   fail:0   skip:12 
fi-byt-j1900 total:252  pass:225  dwarn:0   dfail:0   fail:0   skip:27 
fi-byt-n2820 total:252  pass:221  dwarn:0   dfail:0   fail:0   skip:31 
fi-hsw-4770  total:252  pass:236  dwarn:0   dfail:0   fail:0   skip:16 
fi-hsw-4770r total:252  pass:236  dwarn:0   dfail:0   fail:0   skip:16 
fi-ilk-650   total:252  pass:202  dwarn:0   dfail:0   fail:0   skip:50 
fi-ivb-3520m total:252  pass:234  dwarn:0   dfail:0   fail:0   skip:18 
fi-ivb-3770  total:252  pass:234  dwarn:0   dfail:0   fail:0   skip:18 
fi-kbl-7500u total:252  pass:234  dwarn:0   dfail:0   fail:0   skip:18 
fi-skl-6260u total:252  pass:242  dwarn:0   dfail:0   fail:0   skip:10 
fi-skl-6700hqtotal:252  pass:235  dwarn:0   dfail:0   fail:0   skip:17 
fi-skl-6700k total:252  pass:230  dwarn:4   dfail:0   fail:0   skip:18 
fi-skl-6770hqtotal:252  pass:242  dwarn:0   dfail:0   fail:0   skip:10 
fi-snb-2520m total:252  pass:224  dwarn:0   dfail:0   fail:0   skip:28 
fi-snb-2600  total:252  pass:223  dwarn:0   dfail:0   fail:0   skip:29 

02022d17a5787709617b7897de3906970e2b0721 drm-tip: 2017y-02m-17d-15h-15m-45s UTC 
integration manifest
0499ce8 drm/i915: Add power well SW/HW state verification
4cce996 drm/i915: Preserve the state of power wells not explicitly enabled
1c709db drm/i915/gen9: Fix clearing of the BIOS power well request register
28f7e95 drm/i915: Call the sync_hw hook for power wells without a domain
c059f6b drm/i915: Remove redundant toggling from the power well sync_hw hooks

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3887/
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm: handle override/firmware edid at the lowest level (rev2)

[Patchwork]

== Series Details ==

Series: drm: handle override/firmware edid at the lowest level (rev2)
URL   : https://patchwork.freedesktop.org/series/19764/
State : success

== Summary ==

Series 19764v2 drm: handle override/firmware edid at the lowest level
https://patchwork.freedesktop.org/api/1.0/series/19764/revisions/2/mbox/

fi-bdw-5557u total:252  pass:241  dwarn:0   dfail:0   fail:0   skip:11 
fi-bsw-n3050 total:252  pass:213  dwarn:0   dfail:0   fail:0   skip:39 
fi-bxt-j4205 total:252  pass:233  dwarn:0   dfail:0   fail:0   skip:19 
fi-bxt-t5700 total:83   pass:70   dwarn:0   dfail:0   fail:0   skip:12 
fi-byt-j1900 total:252  pass:225  dwarn:0   dfail:0   fail:0   skip:27 
fi-byt-n2820 total:252  pass:221  dwarn:0   dfail:0   fail:0   skip:31 
fi-hsw-4770  total:252  pass:236  dwarn:0   dfail:0   fail:0   skip:16 
fi-hsw-4770r total:252  pass:236  dwarn:0   dfail:0   fail:0   skip:16 
fi-ilk-650   total:252  pass:202  dwarn:0   dfail:0   fail:0   skip:50 
fi-ivb-3520m total:252  pass:234  dwarn:0   dfail:0   fail:0   skip:18 
fi-ivb-3770  total:252  pass:234  dwarn:0   dfail:0   fail:0   skip:18 
fi-kbl-7500u total:252  pass:234  dwarn:0   dfail:0   fail:0   skip:18 
fi-skl-6260u total:252  pass:242  dwarn:0   dfail:0   fail:0   skip:10 
fi-skl-6700hqtotal:252  pass:235  dwarn:0   dfail:0   fail:0   skip:17 
fi-skl-6700k total:252  pass:230  dwarn:4   dfail:0   fail:0   skip:18 
fi-skl-6770hqtotal:252  pass:242  dwarn:0   dfail:0   fail:0   skip:10 
fi-snb-2520m total:252  pass:224  dwarn:0   dfail:0   fail:0   skip:28 
fi-snb-2600  total:252  pass:223  dwarn:0   dfail:0   fail:0   skip:29 

02022d17a5787709617b7897de3906970e2b0721 drm-tip: 2017y-02m-17d-15h-15m-45s UTC 
integration manifest
5e3f195 drm: handle override edid and firmware EDID at drm_do_get_edid() level
2c81969 drm/edid: respect connector force for drm_get_edid ddc probe
bc9819b drm: do not debug log about missing CEA extensions on NULL edid
cf94d8b drm: move edid property update and add modes out of edid firmware loader

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3886/
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/6] drm/i915: Remove temporary allocation of dma addresses when rotating

[Patchwork]

== Series Details ==

Series: series starting with [CI,1/6] drm/i915: Remove temporary allocation of 
dma addresses when rotating
URL   : https://patchwork.freedesktop.org/series/19852/
State : success

== Summary ==

Series 19852v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/19852/revisions/1/mbox/

fi-bdw-5557u total:252  pass:241  dwarn:0   dfail:0   fail:0   skip:11 
fi-bsw-n3050 total:252  pass:213  dwarn:0   dfail:0   fail:0   skip:39 
fi-bxt-j4205 total:252  pass:233  dwarn:0   dfail:0   fail:0   skip:19 
fi-bxt-t5700 total:83   pass:70   dwarn:0   dfail:0   fail:0   skip:12 
fi-byt-j1900 total:252  pass:225  dwarn:0   dfail:0   fail:0   skip:27 
fi-byt-n2820 total:252  pass:221  dwarn:0   dfail:0   fail:0   skip:31 
fi-hsw-4770  total:252  pass:236  dwarn:0   dfail:0   fail:0   skip:16 
fi-hsw-4770r total:252  pass:236  dwarn:0   dfail:0   fail:0   skip:16 
fi-ilk-650   total:252  pass:202  dwarn:0   dfail:0   fail:0   skip:50 
fi-ivb-3520m total:252  pass:234  dwarn:0   dfail:0   fail:0   skip:18 
fi-ivb-3770  total:252  pass:234  dwarn:0   dfail:0   fail:0   skip:18 
fi-kbl-7500u total:252  pass:234  dwarn:0   dfail:0   fail:0   skip:18 
fi-skl-6260u total:252  pass:242  dwarn:0   dfail:0   fail:0   skip:10 
fi-skl-6700hqtotal:252  pass:235  dwarn:0   dfail:0   fail:0   skip:17 
fi-skl-6700k total:252  pass:230  dwarn:4   dfail:0   fail:0   skip:18 
fi-skl-6770hqtotal:252  pass:242  dwarn:0   dfail:0   fail:0   skip:10 
fi-snb-2520m total:252  pass:224  dwarn:0   dfail:0   fail:0   skip:28 
fi-snb-2600  total:252  pass:223  dwarn:0   dfail:0   fail:0   skip:29 

02022d17a5787709617b7897de3906970e2b0721 drm-tip: 2017y-02m-17d-15h-15m-45s UTC 
integration manifest
ceced16 drm/i915: Remove completed fences after a wait
91f2b88 drm/i915: Only start with the fake-irq timer if interrupts are dead
a143470 drm/i915: Defer declaration of missed-interrupt until the waiter is 
asleep
adb3285 drm/i915: Break i915_spin_request() if we see an interrupt
c38a802 drm/i915: Postpone fake breadcrumb interrupt until real interrupts cease
b948281 drm/i915: Remove temporary allocation of dma addresses when rotating

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3885/
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[Intel-gfx] [PATCH 2/2] drm/i915: Avoid decomposing a signal-on-any fence-array

[Chris Wilson]

The code currently assumes that all fence arrays it sees are the normal
signal-on-all variety, and decomposes the array into its individual
fences so that it can extract the native i915 fences. If the fence array
is using signal-on-any, we should not decompose as we must not wait on
them all, just the first in *that* set.

Signed-off-by: Chris Wilson 
Cc: Joonas Lahtinen 
Cc: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_gem_request.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_request.c 
b/drivers/gpu/drm/i915/i915_gem_request.c
index 2f6cfa47dc61..2ab96c35cc5e 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -696,7 +696,8 @@ i915_gem_request_await_dma_fence(struct 
drm_i915_gem_request *req,
if (dma_fence_is_i915(fence))
return i915_gem_request_await_request(req, to_request(fence));
 
-   if (!dma_fence_is_array(fence)) {
+   if (!dma_fence_is_array(fence) ||
+   test_bit(DMA_FENCE_ARRAY_SIGNAL_ANY, >flags)) {
ret = i915_sw_fence_await_dma_fence(>submit,
fence, I915_FENCE_TIMEOUT,
GFP_KERNEL);
-- 
2.11.0

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[Intel-gfx] [PATCH 1/2] dma-fence: Flag when a fence-array is using signal-on-any

[Chris Wilson]

Indicate that the fence array will be signaled on the first completion
(signal-on-any mode) as opposed to waiting for all to be signaled.

Signed-off-by: Chris Wilson 
Cc: Sumit Semwal 
Cc: Gustavo Padovan 
Cc: Daniel Vetter 
Cc: "Christian König" 
---
 drivers/dma-buf/dma-fence-array.c | 3 +++
 include/linux/dma-fence-array.h   | 4 
 2 files changed, 7 insertions(+)

diff --git a/drivers/dma-buf/dma-fence-array.c 
b/drivers/dma-buf/dma-fence-array.c
index 67eb7c8fb88c..8c48402a2daa 100644
--- a/drivers/dma-buf/dma-fence-array.c
+++ b/drivers/dma-buf/dma-fence-array.c
@@ -137,6 +137,9 @@ struct dma_fence_array *dma_fence_array_create(int 
num_fences,
dma_fence_init(>base, _fence_array_ops, >lock,
   context, seqno);
 
+   if (num_fences > 1 && signal_on_any)
+   __set_bit(DMA_FENCE_ARRAY_SIGNAL_ANY, >base.flags);
+
array->num_fences = num_fences;
atomic_set(>num_pending, signal_on_any ? 1 : num_fences);
array->fences = fences;
diff --git a/include/linux/dma-fence-array.h b/include/linux/dma-fence-array.h
index 5900945f962d..4270d33d05b3 100644
--- a/include/linux/dma-fence-array.h
+++ b/include/linux/dma-fence-array.h
@@ -49,6 +49,10 @@ struct dma_fence_array {
struct dma_fence **fences;
 };
 
+enum {
+   DMA_FENCE_ARRAY_SIGNAL_ANY = DMA_FENCE_FLAG_USER_BITS,
+};
+
 extern const struct dma_fence_ops dma_fence_array_ops;
 
 /**
-- 
2.11.0

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Remove temporary allocation of dma addresses when rotating (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Remove temporary allocation of dma addresses when rotating 
(rev2)
URL   : https://patchwork.freedesktop.org/series/19850/
State : success

== Summary ==

Series 19850v2 drm/i915: Remove temporary allocation of dma addresses when 
rotating
https://patchwork.freedesktop.org/api/1.0/series/19850/revisions/2/mbox/

fi-bdw-5557u total:252  pass:241  dwarn:0   dfail:0   fail:0   skip:11 
fi-bsw-n3050 total:252  pass:213  dwarn:0   dfail:0   fail:0   skip:39 
fi-bxt-j4205 total:252  pass:233  dwarn:0   dfail:0   fail:0   skip:19 
fi-bxt-t5700 total:83   pass:70   dwarn:0   dfail:0   fail:0   skip:12 
fi-byt-j1900 total:252  pass:225  dwarn:0   dfail:0   fail:0   skip:27 
fi-byt-n2820 total:252  pass:221  dwarn:0   dfail:0   fail:0   skip:31 
fi-hsw-4770  total:252  pass:236  dwarn:0   dfail:0   fail:0   skip:16 
fi-hsw-4770r total:252  pass:236  dwarn:0   dfail:0   fail:0   skip:16 
fi-ilk-650   total:252  pass:202  dwarn:0   dfail:0   fail:0   skip:50 
fi-ivb-3520m total:252  pass:234  dwarn:0   dfail:0   fail:0   skip:18 
fi-ivb-3770  total:252  pass:234  dwarn:0   dfail:0   fail:0   skip:18 
fi-kbl-7500u total:252  pass:234  dwarn:0   dfail:0   fail:0   skip:18 
fi-skl-6260u total:252  pass:242  dwarn:0   dfail:0   fail:0   skip:10 
fi-skl-6700hqtotal:252  pass:235  dwarn:0   dfail:0   fail:0   skip:17 
fi-skl-6700k total:252  pass:230  dwarn:4   dfail:0   fail:0   skip:18 
fi-skl-6770hqtotal:252  pass:242  dwarn:0   dfail:0   fail:0   skip:10 
fi-snb-2520m total:252  pass:224  dwarn:0   dfail:0   fail:0   skip:28 
fi-snb-2600  total:252  pass:223  dwarn:0   dfail:0   fail:0   skip:29 

02022d17a5787709617b7897de3906970e2b0721 drm-tip: 2017y-02m-17d-15h-15m-45s UTC 
integration manifest
1ecf305 drm/i915: Remove temporary allocation of dma addresses when rotating

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3884/
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Re: [Intel-gfx] linux-firmware pull request (bxt guc,huc; kbl guc,huc; skl huc)

[Kyle McMartin]

On Tue, Feb 07, 2017 at 10:12:38PM +, Srivatsa, Anusha wrote:
> Hi,
> 
> Please consider pulling i915 updates to linux-firmware.git.
> 
> The following changes since commit 6d3bc8886517d171068fd1263176b8b5c51df204:
> 
>   Fix permissions on ti-connectivity firmware from 05e9fe59 (2017-01-13 
> 10:14:07 -0500)
> 
> are available in the git repository at:
> 
>   https://github.com/anushasr/linux-firmware.git master
> 
> for you to fetch changes up to d7fe1272a38777a41ce9d1df80f58ace2d9e3d27:
> 
>   linux-firmware/i915: GuC firmware for Kabylake v9.14 (2017-02-07 11:48:05 
> -0800)
> 

Pulled, thanks.

regards, Kyle
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[Intel-gfx] [PATCH i-g-t 3/5] lib/igt_kms: Fix possible out-of-bounds access

[Brian Starkey]

If there's no primary plane, pipe->plane_primary == -1, and the assert
meant to check that it's valid will access pipe->planes[-1].

Fix that to check that pipe->plane_primary has been set instead.

Fixes: 36656239ef96 lib/igt_kms: Implement dynamic plane count support
Signed-off-by: Brian Starkey 
---
 lib/igt_kms.c |4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index 783c891aebf1..45c90c71f301 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -1820,9 +1820,9 @@ void igt_display_init(igt_display_t *display, int drm_fd)
 
/*
 * At the bare minimum, we should expect to have a primary
-* plane
+* plane, and it must be in slot 0.
 */
-   igt_assert(pipe->planes[pipe->plane_primary].drm_plane);
+   igt_assert_eq(pipe->plane_primary, 0);
 
if (display->has_cursor_plane) {
/*
-- 
1.7.9.5

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[Intel-gfx] [PATCH i-g-t 4/5] lib/igt_kms: Fix memory corruption when there's no cursor plane

[Brian Starkey]

The dynamic plane support means that if there's no cursor plane, then
there is no space in the pipe->planes array for it, and thus assigning
a "drm_plane-less" plane is out-of-bounds and leads to heap corruption
and later crashes.

The "drm_plane-less" cursor plane isn't included in n_planes anyway,
which means there's no way to ever access it/know that it's there - so
just remove it entirely.

Fixes: 36656239ef96 lib/igt_kms: Implement dynamic plane count support
Signed-off-by: Brian Starkey 
---
 lib/igt_kms.c |6 --
 1 file changed, 6 deletions(-)

diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index 45c90c71f301..ef7bfd1a8108 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -1837,12 +1837,6 @@ void igt_display_init(igt_display_t *display, int drm_fd)
memset(>planes[last_plane], 0,
   sizeof *plane);
}
-   } else {
-   /* Add drm_plane-less cursor */
-   plane = >planes[p];
-   plane->pipe = pipe;
-   plane->index = p;
-   plane->type = DRM_PLANE_TYPE_CURSOR;
}
 
pipe->n_planes = n_planes;
-- 
1.7.9.5

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[Intel-gfx] [PATCH i-g-t 5/5] lib/igt_kms: Remove redundant cursor code

[Brian Starkey]

The dynamic plane support means that there should never be gaps in the
pipe->planes array. This means we should never need to move the cursor
plane from the last slot to another.

Remove the unnecessary code, and add an assert that makes sure nothing
strange happened that broke the assignment logic.

Signed-off-by: Brian Starkey 
---
 lib/igt_kms.c |   19 +--
 1 file changed, 5 insertions(+), 14 deletions(-)

diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index ef7bfd1a8108..6fbe67139d98 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -1824,20 +1824,11 @@ void igt_display_init(igt_display_t *display, int 
drm_fd)
 */
igt_assert_eq(pipe->plane_primary, 0);
 
-   if (display->has_cursor_plane) {
-   /*
-* Cursor was put in the last slot.  If we have 0 or
-* only 1 sprite, that's the wrong slot and we need to
-* move it down.
-*/
-   if (p != last_plane) {
-   pipe->planes[p] =
-   pipe->planes[last_plane];
-   pipe->planes[p].index = p;
-   memset(>planes[last_plane], 0,
-  sizeof *plane);
-   }
-   }
+   /*
+* There should be no gaps. If there is, something happened
+* which we can't handle (e.g. all planes are cursors).
+*/
+   igt_assert_eq(p, last_plane);
 
pipe->n_planes = n_planes;
 
-- 
1.7.9.5

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[Intel-gfx] [PATCH i-g-t 1/5] lib/igt_kms: Fix drm_plane leak

[Brian Starkey]

In the loop looking for planes on a pipe, we always want to free up
the drm_plane afterwards.

Fixes: 36656239ef96 lib/igt_kms: Implement dynamic plane count support
Signed-off-by: Brian Starkey 
---

Hi,

This series cleans up igt_display_init a bit.

 - Fixes a memory leak.
 - Fixes out-of-bounds array access on cards with no primary plane.
 - Fixes memory corruption/crashes on cards with no cursor plane.
 - Cleans up some left-over stuff which wasn't really relevant after
   the dynamic planes change.

There's one detail (patch 4) I'm not really sure about - the dynamic
planes stuff means that the "drm_plane-less" cursor plane doesn't
work/make sense anymore, as it will never be found by
igt_pipe_get_plane_type(). I couldn't find any tests which seemed to
rely on having that cursor plane present, but I don't have any
hardware with a cursor to test on.

igt_display_init() could be simplified a bit further by not putting
the primary/cursor planes at the start/end respectively, but at least
kms_cursor_legacy appears to rely on a non-cursor plane being index 0,
so I've left it as-is for now.

I've given this a cursory test on Mali-DP, but if anyone is able to
test it more thoroughly on Intel HW that might be a good idea.

-Brian

 lib/igt_kms.c |8 +++-
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index f59af6e75348..4ca9145726e2 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -1759,12 +1759,10 @@ void igt_display_init(igt_display_t *display, int 
drm_fd)
plane_resources->planes[j]);
igt_assert(drm_plane);
 
-   if (!(drm_plane->possible_crtcs & (1 << i))) {
-   drmModeFreePlane(drm_plane);
-   continue;
-   }
+   if (drm_plane->possible_crtcs & (1 << i))
+   n_planes++;
 
-   n_planes++;
+   drmModeFreePlane(drm_plane);
}
 
igt_assert_lte(0, n_planes);
-- 
1.7.9.5

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[Intel-gfx] [PATCH i-g-t 2/5] lib/igt_kms: Neaten up pipe->planes[] assignment

[Brian Starkey]

Remove a bunch of branches, functionally equivalent.

Signed-off-by: Brian Starkey 
---
 lib/igt_kms.c |   34 ++
 1 file changed, 10 insertions(+), 24 deletions(-)

diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index 4ca9145726e2..783c891aebf1 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -1785,32 +1785,18 @@ void igt_display_init(igt_display_t *display, int 
drm_fd)
 
type = get_drm_plane_type(display->drm_fd,
  plane_resources->planes[j]);
-   switch (type) {
-   case DRM_PLANE_TYPE_PRIMARY:
-   if (pipe->plane_primary == -1) {
-   plane = >planes[0];
-   plane->index = 0;
-   pipe->plane_primary = 0;
-   } else {
-   plane = >planes[p];
-   plane->index = p++;
-   }
-   break;
-   case DRM_PLANE_TYPE_CURSOR:
-   if (pipe->plane_cursor == -1) {
-   plane = >planes[last_plane];
-   plane->index = last_plane;
-   pipe->plane_cursor = last_plane;
-   } else {
-   plane = >planes[p];
-   plane->index = p++;
-   }
-   display->has_cursor_plane = true;
-   break;
-   default:
+
+   if (type == DRM_PLANE_TYPE_PRIMARY && 
pipe->plane_primary == -1) {
+   plane = >planes[0];
+   plane->index = 0;
+   pipe->plane_primary = 0;
+   } else if (type == DRM_PLANE_TYPE_CURSOR && 
pipe->plane_cursor == -1) {
+   plane = >planes[last_plane];
+   plane->index = last_plane;
+   pipe->plane_cursor = last_plane;
+   } else {
plane = >planes[p];
plane->index = p++;
-   break;
}
 
igt_assert_f(plane->index < n_planes, "n_planes < 
plane->index failed\n");
-- 
1.7.9.5

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: reduce cursor size for GEN5 hardware (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915: reduce cursor size for GEN5 hardware (rev4)
URL   : https://patchwork.freedesktop.org/series/18822/
State : success

== Summary ==

Series 18822v4 drm/i915: reduce cursor size for GEN5 hardware
https://patchwork.freedesktop.org/api/1.0/series/18822/revisions/4/mbox/

fi-bdw-5557u total:252  pass:241  dwarn:0   dfail:0   fail:0   skip:11 
fi-bsw-n3050 total:252  pass:213  dwarn:0   dfail:0   fail:0   skip:39 
fi-bxt-j4205 total:252  pass:233  dwarn:0   dfail:0   fail:0   skip:19 
fi-bxt-t5700 total:83   pass:70   dwarn:0   dfail:0   fail:0   skip:12 
fi-byt-j1900 total:252  pass:225  dwarn:0   dfail:0   fail:0   skip:27 
fi-byt-n2820 total:252  pass:221  dwarn:0   dfail:0   fail:0   skip:31 
fi-hsw-4770  total:252  pass:236  dwarn:0   dfail:0   fail:0   skip:16 
fi-hsw-4770r total:252  pass:236  dwarn:0   dfail:0   fail:0   skip:16 
fi-ilk-650   total:252  pass:202  dwarn:0   dfail:0   fail:0   skip:50 
fi-ivb-3520m total:252  pass:234  dwarn:0   dfail:0   fail:0   skip:18 
fi-ivb-3770  total:252  pass:234  dwarn:0   dfail:0   fail:0   skip:18 
fi-kbl-7500u total:252  pass:234  dwarn:0   dfail:0   fail:0   skip:18 
fi-skl-6260u total:252  pass:242  dwarn:0   dfail:0   fail:0   skip:10 
fi-skl-6700hqtotal:252  pass:235  dwarn:0   dfail:0   fail:0   skip:17 
fi-skl-6700k total:252  pass:230  dwarn:4   dfail:0   fail:0   skip:18 
fi-skl-6770hqtotal:252  pass:242  dwarn:0   dfail:0   fail:0   skip:10 
fi-snb-2520m total:252  pass:224  dwarn:0   dfail:0   fail:0   skip:28 
fi-snb-2600  total:252  pass:223  dwarn:0   dfail:0   fail:0   skip:29 

02022d17a5787709617b7897de3906970e2b0721 drm-tip: 2017y-02m-17d-15h-15m-45s UTC 
integration manifest
1ad4f51 drm/i915: Fix legacy cursor vs. watermarks for ILK-BDW

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3883/
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Only apply legacy PDE overflow detection to 3lvl machines (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Only apply legacy PDE overflow detection to 3lvl machines 
(rev2)
URL   : https://patchwork.freedesktop.org/series/19845/
State : success

== Summary ==

Series 19845v2 drm/i915: Only apply legacy PDE overflow detection to 3lvl 
machines
https://patchwork.freedesktop.org/api/1.0/series/19845/revisions/2/mbox/

fi-bdw-5557u total:252  pass:241  dwarn:0   dfail:0   fail:0   skip:11 
fi-bsw-n3050 total:252  pass:213  dwarn:0   dfail:0   fail:0   skip:39 
fi-bxt-j4205 total:252  pass:233  dwarn:0   dfail:0   fail:0   skip:19 
fi-bxt-t5700 total:83   pass:70   dwarn:0   dfail:0   fail:0   skip:12 
fi-byt-j1900 total:252  pass:225  dwarn:0   dfail:0   fail:0   skip:27 
fi-byt-n2820 total:252  pass:221  dwarn:0   dfail:0   fail:0   skip:31 
fi-hsw-4770  total:252  pass:236  dwarn:0   dfail:0   fail:0   skip:16 
fi-hsw-4770r total:252  pass:236  dwarn:0   dfail:0   fail:0   skip:16 
fi-ilk-650   total:252  pass:202  dwarn:0   dfail:0   fail:0   skip:50 
fi-ivb-3520m total:252  pass:234  dwarn:0   dfail:0   fail:0   skip:18 
fi-ivb-3770  total:252  pass:234  dwarn:0   dfail:0   fail:0   skip:18 
fi-kbl-7500u total:252  pass:234  dwarn:0   dfail:0   fail:0   skip:18 
fi-skl-6260u total:252  pass:242  dwarn:0   dfail:0   fail:0   skip:10 
fi-skl-6700hqtotal:252  pass:235  dwarn:0   dfail:0   fail:0   skip:17 
fi-skl-6700k total:252  pass:230  dwarn:4   dfail:0   fail:0   skip:18 
fi-skl-6770hqtotal:252  pass:242  dwarn:0   dfail:0   fail:0   skip:10 
fi-snb-2520m total:252  pass:224  dwarn:0   dfail:0   fail:0   skip:28 
fi-snb-2600  total:252  pass:223  dwarn:0   dfail:0   fail:0   skip:29 

02022d17a5787709617b7897de3906970e2b0721 drm-tip: 2017y-02m-17d-15h-15m-45s UTC 
integration manifest
1c072c6 drm/i915: Only apply legacy PDE overflow detection to 3lvl machines

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3882/
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: Skip clflushes for all non-page backed objects

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915: Skip clflushes for all non-page 
backed objects
URL   : https://patchwork.freedesktop.org/series/19846/
State : failure

== Summary ==

Series 19846v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/19846/revisions/1/mbox/

Test core_auth:
Subgroup basic-auth:
pass   -> DMESG-FAIL (fi-ilk-650)
pass   -> DMESG-FAIL (fi-byt-n2820)
pass   -> DMESG-FAIL (fi-bxt-j4205)
pass   -> DMESG-FAIL (fi-bxt-t5700)
pass   -> DMESG-FAIL (fi-bsw-n3050)
pass   -> DMESG-FAIL (fi-byt-j1900)
Test core_prop_blob:
Subgroup basic:
pass   -> INCOMPLETE (fi-ilk-650)
pass   -> INCOMPLETE (fi-byt-n2820)
pass   -> INCOMPLETE (fi-bxt-j4205)
pass   -> INCOMPLETE (fi-bxt-t5700)
pass   -> INCOMPLETE (fi-bsw-n3050)
pass   -> INCOMPLETE (fi-byt-j1900)
Test kms_busy:
Subgroup basic-flip-default-a:
pass   -> INCOMPLETE (fi-ivb-3770)
pass   -> INCOMPLETE (fi-skl-6260u)
pass   -> INCOMPLETE (fi-kbl-7500u)
pass   -> INCOMPLETE (fi-bdw-5557u)
pass   -> INCOMPLETE (fi-skl-6700hq)
pass   -> INCOMPLETE (fi-ivb-3520m)
pass   -> INCOMPLETE (fi-hsw-4770)
pass   -> INCOMPLETE (fi-snb-2520m)
pass   -> INCOMPLETE (fi-hsw-4770r)
pass   -> INCOMPLETE (fi-snb-2600)

fi-bdw-5557u total:170  pass:165  dwarn:0   dfail:0   fail:0   skip:4  
fi-bsw-n3050 total:2pass:0dwarn:0   dfail:1   fail:0   skip:0  
fi-bxt-j4205 total:2pass:0dwarn:0   dfail:1   fail:0   skip:0  
fi-bxt-t5700 total:2pass:0dwarn:0   dfail:1   fail:0   skip:0  
fi-byt-j1900 total:2pass:0dwarn:0   dfail:1   fail:0   skip:0  
fi-byt-n2820 total:2pass:0dwarn:0   dfail:1   fail:0   skip:0  
fi-hsw-4770  total:170  pass:160  dwarn:0   dfail:0   fail:0   skip:9  
fi-hsw-4770r total:170  pass:160  dwarn:0   dfail:0   fail:0   skip:9  
fi-ilk-650   total:2pass:0dwarn:0   dfail:1   fail:0   skip:0  
fi-ivb-3520m total:170  pass:156  dwarn:0   dfail:0   fail:0   skip:13 
fi-ivb-3770  total:170  pass:156  dwarn:0   dfail:0   fail:0   skip:13 
fi-kbl-7500u total:170  pass:158  dwarn:0   dfail:0   fail:0   skip:11 
fi-skl-6260u total:170  pass:166  dwarn:0   dfail:0   fail:0   skip:3  
fi-skl-6700hqtotal:170  pass:158  dwarn:0   dfail:0   fail:0   skip:11 
fi-snb-2520m total:170  pass:152  dwarn:0   dfail:0   fail:0   skip:17 
fi-snb-2600  total:170  pass:152  dwarn:0   dfail:0   fail:0   skip:17 

02022d17a5787709617b7897de3906970e2b0721 drm-tip: 2017y-02m-17d-15h-15m-45s UTC 
integration manifest
1a36523 drm/i915: Perform object clflushing asynchronously
842d2a6 drm/i915: Skip clflushes for all non-page backed objects

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3881/
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[Intel-gfx] [PATCH] drm/i915: Assert that the request->tail is always qword aligned

[Chris Wilson]

The hardware requires that the tail pointer only advance in qword units,
so assert that the value we write is aligned to qwords, and similarly
enforce this restriction onto the request->tail.

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/intel_lrc.c| 4 
 drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index afcb1f189162..d6b67be4715d 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -325,6 +325,7 @@ static u64 execlists_update_context(struct 
drm_i915_gem_request *rq)
rq->ctx->ppgtt ?: rq->i915->mm.aliasing_ppgtt;
u32 *reg_state = ce->lrc_reg_state;
 
+   GEM_BUG_ON(!IS_ALIGNED(rq->tail, 8));
reg_state[CTX_RING_TAIL+1] = rq->tail;
 
/* True 32b PPGTT with dynamic page allocation: update PDP
@@ -1283,6 +1284,7 @@ static void reset_common_ring(struct intel_engine_cs 
*engine,
 
/* Reset WaIdleLiteRestore:bdw,skl as well */
request->tail = request->wa_tail - WA_TAIL_DWORDS * sizeof(u32);
+   GEM_BUG_ON(!IS_ALIGNED(request->tail, 8));
 }
 
 static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
@@ -1494,6 +1496,7 @@ static void gen8_emit_breadcrumb(struct 
drm_i915_gem_request *request, u32 *cs)
*cs++ = MI_USER_INTERRUPT;
*cs++ = MI_NOOP;
request->tail = intel_ring_offset(request, cs);
+   GEM_BUG_ON(!IS_ALIGNED(request->tail, 8));
 
gen8_emit_wa_tail(request, cs);
 }
@@ -1521,6 +1524,7 @@ static void gen8_emit_breadcrumb_render(struct 
drm_i915_gem_request *request,
*cs++ = MI_USER_INTERRUPT;
*cs++ = MI_NOOP;
request->tail = intel_ring_offset(request, cs);
+   GEM_BUG_ON(!IS_ALIGNED(request->tail, 8));
 
gen8_emit_wa_tail(request, cs);
 }
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index d56f384938f7..f62afffef682 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -784,6 +784,7 @@ static void i9xx_submit_request(struct drm_i915_gem_request 
*request)
 
i915_gem_request_submit(request);
 
+   GEM_BUG_ON(!IS_ALIGNED(request->tail, 8));
I915_WRITE_TAIL(request->engine, request->tail);
 }
 
@@ -795,6 +796,7 @@ static void i9xx_emit_breadcrumb(struct 
drm_i915_gem_request *req, u32 *cs)
*cs++ = MI_USER_INTERRUPT;
 
req->tail = intel_ring_offset(req, cs);
+   GEM_BUG_ON(!IS_ALIGNED(req->tail, 8));
 }
 
 static const int i9xx_emit_breadcrumb_sz = 4;
@@ -833,6 +835,7 @@ static void gen8_render_emit_breadcrumb(struct 
drm_i915_gem_request *req,
*cs++ = MI_NOOP;
 
req->tail = intel_ring_offset(req, cs);
+   GEM_BUG_ON(!IS_ALIGNED(req->tail, 8));
 }
 
 static const int gen8_render_emit_breadcrumb_sz = 8;
-- 
2.11.0

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Re: [Intel-gfx] [CI 1/6] drm/i915: Remove temporary allocation of dma addresses when rotating

[Chris Wilson]

On Fri, Feb 17, 2017 at 04:28:13PM +, Tvrtko Ursulin wrote:
> 
> On 17/02/2017 15:12, Chris Wilson wrote:
> >The object already stores (computed on the fly) the index to dma address
> >so use it instead of reallocating a large temporary array every time we
> >bind a rotated framebuffer.
> 
> On the other hand how big is the radix tree for a large framebuffer?
> I remember those nodes were quite chunky and will hang around for
> the lifetime of the object. While the above mentioned large
> temporary array needs to be allocated only if rotated VMAs have been
> discarded due GGTT pressure, no?
> 
> On the other other hand maybe the radix tree won't be so big in the
> typical case, due sg entry coalescing, but it will hang around for
> much longer.

Also don't forget that we use the radixtree for mmaps, partials, single
page lookups. In all likelihood it already exists, and it doesn't hang
around forever.

> >-DRM_DEBUG_KMS("Created rotated page mapping for object size %zu (%ux%u 
> >tiles, %u pages)\n",
> >-  obj->base.size, rot_info->plane[0].width, 
> >rot_info->plane[0].height, size);
> 
> Hm given how chatty KMS log level is this one wasn't that harmful
> but OK. Use to save me looking in debugfs/i915_gem_framebuffer and
> eyeball the VMA list. Granted that is much more manageable now after
> you added the human readable output there.

It's just the odd one out. If it is useful here, it presumably has some
use on the other branches - and do we want it at page allocation time or
vma creation. And I don't think we really want one at vma create, so I'd
prefer to improve the debugfs (or other) probe.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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Re: [Intel-gfx] [PATCH i-g-t] tools/intel_guc_logger: Fix the assert for the verbosity level

[Daniele Ceraolo Spurio]

Reviewed-by: Daniele Ceraolo Spurio 

On 16/02/17 06:31, Oscar Mateo wrote:

I guess no one has needed to change the verbosity level of the GuC logs.

Signed-off-by: Oscar Mateo 
---
 tools/intel_guc_logger.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/intel_guc_logger.c b/tools/intel_guc_logger.c
index 159a54e..c9ea60d 100644
--- a/tools/intel_guc_logger.c
+++ b/tools/intel_guc_logger.c
@@ -302,7 +302,7 @@ static int parse_options(int opt, int opt_index, void *data)
switch(opt) {
case 'v':
verbosity_level = atoi(optarg);
-   igt_assert_f(verbosity_level < 0 || verbosity_level > 3, "invalid 
input for -v option\n");
+   igt_assert_f(verbosity_level >= 0 && verbosity_level <= 3, "invalid 
input for -v option\n");
igt_debug("verbosity level to be used is %d\n", 
verbosity_level);
break;
case 'o':


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Re: [Intel-gfx] [CI 1/6] drm/i915: Remove temporary allocation of dma addresses when rotating

[Tvrtko Ursulin]

On 17/02/2017 15:12, Chris Wilson wrote:

The object already stores (computed on the fly) the index to dma address
so use it instead of reallocating a large temporary array every time we
bind a rotated framebuffer.


On the other hand how big is the radix tree for a large framebuffer? I 
remember those nodes were quite chunky and will hang around for the 
lifetime of the object. While the above mentioned large temporary array 
needs to be allocated only if rotated VMAs have been discarded due GGTT 
pressure, no?


On the other other hand maybe the radix tree won't be so big in the 
typical case, due sg entry coalescing, but it will hang around for much 
longer.



Signed-off-by: Chris Wilson 
Cc: Matthew Auld 
Cc: Joonas Lahtinen 
Cc: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 77 -
 1 file changed, 25 insertions(+), 52 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 47a38272f54c..848dbb926fd1 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3043,27 +3043,32 @@ void i915_gem_restore_gtt_mappings(struct 
drm_i915_private *dev_priv)
 }

 static struct scatterlist *
-rotate_pages(const dma_addr_t *in, unsigned int offset,
-unsigned int width, unsigned int height,
-unsigned int stride,
+rotate_pages(struct drm_i915_gem_object *obj,
+const struct intel_rotation_plane_info *p,
 struct sg_table *st, struct scatterlist *sg)
 {
unsigned int column, row;
-   unsigned int src_idx;

-   for (column = 0; column < width; column++) {
-   src_idx = stride * (height - 1) + column;
-   for (row = 0; row < height; row++) {
-   st->nents++;
+   for (column = 0; column < p->width; column++) {
+   unsigned long src_idx =
+   p->stride * (p->height - 1) + column + p->offset;
+   for (row = 0; row < p->height; row++) {
+   struct scatterlist *src;
+   unsigned int n;
+
+   src = i915_gem_object_get_sg(obj, src_idx, );
+   src_idx -= p->stride;
+
/* We don't need the pages, but need to initialize
 * the entries so the sg list can be happily traversed.
 * The only thing we need are DMA addresses.
 */
sg_set_page(sg, NULL, PAGE_SIZE, 0);
-   sg_dma_address(sg) = in[offset + src_idx];
+   sg_dma_address(sg) = sg_dma_address(src) + n*PAGE_SIZE;
sg_dma_len(sg) = PAGE_SIZE;
-   sg = sg_next(sg);
-   src_idx -= stride;
+   sg = __sg_next(sg);
+
+   st->nents++;
}
}

@@ -3074,62 +3079,30 @@ static noinline struct sg_table *
 intel_rotate_pages(struct intel_rotation_info *rot_info,
   struct drm_i915_gem_object *obj)
 {
-   const unsigned long n_pages = obj->base.size / PAGE_SIZE;
-   unsigned int size = intel_rotation_info_size(rot_info);
-   struct sgt_iter sgt_iter;
-   dma_addr_t dma_addr;
-   unsigned long i;
-   dma_addr_t *page_addr_list;
-   struct sg_table *st;
+   const unsigned int size = intel_rotation_info_size(rot_info);
struct scatterlist *sg;
+   struct sg_table *st;
+   unsigned long i;
int ret = -ENOMEM;

-   /* Allocate a temporary list of source pages for random access. */
-   page_addr_list = drm_malloc_gfp(n_pages,
-   sizeof(dma_addr_t),
-   GFP_TEMPORARY);
-   if (!page_addr_list)
-   return ERR_PTR(ret);
-
-   /* Allocate target SG list. */
st = kmalloc(sizeof(*st), GFP_KERNEL);
if (!st)
-   goto err_st_alloc;
+   goto err;

ret = sg_alloc_table(st, size, GFP_KERNEL);
if (ret)
-   goto err_sg_alloc;
-
-   /* Populate source page list from the object. */
-   i = 0;
-   for_each_sgt_dma(dma_addr, sgt_iter, obj->mm.pages)
-   page_addr_list[i++] = dma_addr;
+   goto err;

-   GEM_BUG_ON(i != n_pages);
st->nents = 0;
sg = st->sgl;
-
-   for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) {
-   sg = rotate_pages(page_addr_list, rot_info->plane[i].offset,
- rot_info->plane[i].width, 
rot_info->plane[i].height,
- rot_info->plane[i].stride, st, sg);
-   }
-
-   DRM_DEBUG_KMS("Created rotated page mapping for object size %zu (%ux%u 
tiles, %u pages)\n",
- 

[Intel-gfx] [PATCH 2/2] drm/i915: Delay disabling the user interrupt for breadcrumbs

[Chris Wilson]

A significant cost in setting up a wait is the overhead of enabling the
interrupt. As we disable the interrupt whenever the queue of waiters is
empty, if we are frequently waiting on alternating batches, we end up
re-enabling the interrupt on a frequent basis. We do want to disable the
interrupt during normal operations as under high load it may add several
thousand interrupts/s - we have been known in the past to occupy whole
cores with our interrupt handler after accidentally leaving user
interrupts enabled. As a compromise, leave the interrupt enabled until
the next IRQ, or the system is idle. This gives a small window for a
waiter to keep the interrupt active and not be delayed by having to
re-enable the interrupt.

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_gem.c  |  4 +-
 drivers/gpu/drm/i915/i915_irq.c  |  5 +-
 drivers/gpu/drm/i915/intel_breadcrumbs.c | 95 +++-
 drivers/gpu/drm/i915/intel_ringbuffer.h  |  4 +-
 4 files changed, 65 insertions(+), 43 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 6745dcbf3799..9c87aacce43b 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3003,8 +3003,10 @@ i915_gem_idle_work_handler(struct work_struct *work)
if (wait_for(intel_execlists_idle(dev_priv), 10))
DRM_ERROR("Timeout waiting for engines to idle\n");
 
-   for_each_engine(engine, dev_priv, id)
+   for_each_engine(engine, dev_priv, id) {
+   intel_engine_disarm_breadcrumbs(engine);
i915_gem_batch_pool_fini(>batch_pool);
+   }
 
GEM_BUG_ON(!dev_priv->gt.awake);
dev_priv->gt.awake = false;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 0c370c687c2a..fa597a29bc1d 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1036,9 +1036,6 @@ static void notify_ring(struct intel_engine_cs *engine)
struct drm_i915_gem_request *rq = NULL;
struct intel_wait *wait;
 
-   if (!intel_engine_has_waiter(engine))
-   return;
-
trace_i915_gem_request_notify(engine);
atomic_inc(>irq_count);
set_bit(ENGINE_IRQ_BREADCRUMB, >irq_posted);
@@ -1064,6 +1061,8 @@ static void notify_ring(struct intel_engine_cs *engine)
rq = wait->request;
 
wake_up_process(wait->tsk);
+   } else {
+   __intel_engine_disarm_breadcrumbs(engine);
}
spin_unlock(>breadcrumbs.lock);
 
diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c 
b/drivers/gpu/drm/i915/intel_breadcrumbs.c
index 860372653a59..94c6ce9c0a6f 100644
--- a/drivers/gpu/drm/i915/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c
@@ -35,8 +35,10 @@ static void intel_breadcrumbs_hangcheck(unsigned long data)
 {
struct intel_engine_cs *engine = (struct intel_engine_cs *)data;
struct intel_breadcrumbs *b = >breadcrumbs;
+   struct intel_wait *wait;
+   unsigned long flags;
 
-   if (!b->irq_enabled)
+   if (!intel_engine_has_waiter(engine))
return;
 
if (b->hangcheck_interrupts != atomic_read(>irq_count)) {
@@ -49,10 +51,15 @@ static void intel_breadcrumbs_hangcheck(unsigned long data)
 * to process the pending interupt (e.g, low priority task on a loaded
 * system) and wait until it sleeps before declaring a missed interrupt.
 */
-   if (!intel_engine_wakeup(engine)) {
+   spin_lock_irqsave(>lock, flags);
+   wait = b->first_wait;
+   if (wait && !wake_up_process(wait->tsk)) {
mod_timer(>hangcheck, wait_timeout());
-   return;
+   wait = NULL;
}
+   spin_unlock_irqrestore(>lock, flags);
+   if (!wait)
+   return;
 
DRM_DEBUG("Hangcheck timer elapsed... %s idle\n", engine->name);
set_bit(engine->id, >i915->gpu_error.missed_irq_rings);
@@ -107,6 +114,34 @@ static void irq_disable(struct intel_engine_cs *engine)
spin_unlock(>i915->irq_lock);
 }
 
+void __intel_engine_disarm_breadcrumbs(struct intel_engine_cs *engine)
+{
+   struct intel_breadcrumbs *b = >breadcrumbs;
+
+   assert_spin_locked(>lock);
+
+   if (b->irq_enabled) {
+   irq_disable(engine);
+   b->irq_enabled = false;
+   }
+
+   b->irq_armed = false;
+}
+
+void intel_engine_disarm_breadcrumbs(struct intel_engine_cs *engine)
+{
+   struct intel_breadcrumbs *b = >breadcrumbs;
+   unsigned long flags;
+
+   if (!b->irq_armed)
+   return;
+
+   spin_lock_irqsave(>lock, flags);
+   if (!intel_engine_has_waiter(engine))
+   __intel_engine_disarm_breadcrumbs(engine);
+   spin_unlock_irqrestore(>lock, flags);
+}
+
 

[Intel-gfx] [PATCH 1/2] drm/i915: signal first fence from irq handler if complete

[Chris Wilson]

As execlists and other non-semaphore multi-engine devices coordinate
between engines using interrupts, we can shave off a few 10s of
microsecond of scheduling latency by doing the fence signaling from the
interrupt as opposed to a RT kthread. (Realistically the delay adds
about 1% to an individual cross-engine workload.) We only signal the
first fence in order to limit the amount of work we move into the
interrupt handler. We also have to remember that our breadcrumbs may be
unordered with respect to the interrupt and so we still require the
waiter process to perform some heavyweight coherency fixups, as well as
traversing the tree of waiters.

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_drv.h  | 19 +---
 drivers/gpu/drm/i915/i915_gem_request.c  |  1 +
 drivers/gpu/drm/i915/i915_gem_request.h  |  2 ++
 drivers/gpu/drm/i915/i915_irq.c  | 38 ++--
 drivers/gpu/drm/i915/intel_breadcrumbs.c | 10 +
 drivers/gpu/drm/i915/intel_ringbuffer.h  | 30 +
 6 files changed, 62 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5005922f267b..2592a15d7727 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -4005,7 +4005,10 @@ static inline bool
 __i915_request_irq_complete(const struct drm_i915_gem_request *req)
 {
struct intel_engine_cs *engine = req->engine;
-   u32 seqno = i915_gem_request_global_seqno(req);
+   u32 seqno;
+
+   if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, >fence.flags))
+   return true;
 
/* The request was dequeued before we were awoken. We check after
 * inspecting the hw to confirm that this was the same request
@@ -4013,6 +4016,7 @@ __i915_request_irq_complete(const struct 
drm_i915_gem_request *req)
 * the request execution are sufficient to ensure that a check
 * after reading the value from hw matches this request.
 */
+   seqno = i915_gem_request_global_seqno(req);
if (!seqno)
return false;
 
@@ -4034,9 +4038,8 @@ __i915_request_irq_complete(const struct 
drm_i915_gem_request *req)
 * is woken.
 */
if (engine->irq_seqno_barrier &&
-   rcu_access_pointer(engine->breadcrumbs.irq_seqno_bh) == current &&
test_and_clear_bit(ENGINE_IRQ_BREADCRUMB, >irq_posted)) {
-   struct task_struct *tsk;
+   unsigned long flags;
 
/* The ordering of irq_posted versus applying the barrier
 * is crucial. The clearing of the current irq_posted must
@@ -4058,17 +4061,17 @@ __i915_request_irq_complete(const struct 
drm_i915_gem_request *req)
 * the seqno before we believe it coherent since they see
 * irq_posted == false but we are still running).
 */
-   rcu_read_lock();
-   tsk = rcu_dereference(engine->breadcrumbs.irq_seqno_bh);
-   if (tsk && tsk != current)
+   spin_lock_irqsave(>breadcrumbs.lock, flags);
+   if (engine->breadcrumbs.first_wait &&
+   engine->breadcrumbs.first_wait->tsk != current)
/* Note that if the bottom-half is changed as we
 * are sending the wake-up, the new bottom-half will
 * be woken by whomever made the change. We only have
 * to worry about when we steal the irq-posted for
 * ourself.
 */
-   wake_up_process(tsk);
-   rcu_read_unlock();
+   wake_up_process(engine->breadcrumbs.first_wait->tsk);
+   spin_unlock_irqrestore(>breadcrumbs.lock, flags);
 
if (__i915_gem_request_completed(req, seqno))
return true;
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c 
b/drivers/gpu/drm/i915/i915_gem_request.c
index e22eacec022d..2e7bdb0cf069 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -1083,6 +1083,7 @@ long i915_wait_request(struct drm_i915_gem_request *req,
}
 
wait.tsk = current;
+   wait.request = req;
 
 restart:
do {
diff --git a/drivers/gpu/drm/i915/i915_gem_request.h 
b/drivers/gpu/drm/i915/i915_gem_request.h
index 5f73d8c0a38a..0efee879df23 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.h
+++ b/drivers/gpu/drm/i915/i915_gem_request.h
@@ -32,10 +32,12 @@
 
 struct drm_file;
 struct drm_i915_gem_object;
+struct drm_i915_gem_request;
 
 struct intel_wait {
struct rb_node node;
struct task_struct *tsk;
+   struct drm_i915_gem_request *request;
u32 seqno;
 };
 
diff --git 

[Intel-gfx] [PATCH v2 3/5] drm/i915/gen9: Fix clearing of the BIOS power well request register

[Imre Deak]

Atm, in the power well sync_hw hook we are clearing all BIOS request
bits, not just the one corresponding to the given power well. This could
turn off an unrelated power well inadvertently if it didn't have a
request bit set in the driver request register.

This didn't cause a problem so far, since we enabled all power wells
explicitly before clearing the BIOS request register. A follow-up
patchset will add power wells that won't get enabled this way, so fix up
the inconsistency.

Note that this patch only makes the clearing of the BIOS req register
more logical. Power wells without a reference would still get disabled
by the end of power domain initialization, that is fixed by the next
patch.

v2:
- Clarify in the commit log that this patch doesn't address the case of
  power wells without a reference. (Ander)

Cc: Ander Conselvan de Oliveira 
Cc: David Weinehall 
Cc: Ville Syrjälä 
Signed-off-by: Imre Deak 
Reviewed-by: Ander Conselvan de Oliveira 
---
 drivers/gpu/drm/i915/intel_runtime_pm.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 9bbbdbc..62c99a9 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -862,8 +862,13 @@ static bool skl_power_well_enabled(struct drm_i915_private 
*dev_priv,
 static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
 {
+   uint32_t mask = SKL_POWER_WELL_REQ(power_well->id);
+   uint32_t bios_req = I915_READ(HSW_PWR_WELL_BIOS);
+
/* Clear any request made by BIOS as driver is taking over */
-   I915_WRITE(HSW_PWR_WELL_BIOS, 0);
+   if (bios_req & mask) {
+   I915_WRITE(HSW_PWR_WELL_BIOS, bios_req & ~mask);
+   }
 }
 
 static void skl_power_well_enable(struct drm_i915_private *dev_priv,
-- 
2.5.0

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[Intel-gfx] [PATCH v2 0/5] drm/i915: Fix clearing of BIOS power well requests

[Imre Deak]

This is v2 of [1], addressing Ander's comments.

[1]
https://lists.freedesktop.org/archives/intel-gfx/2017-February/120006.html

Cc: Ander Conselvan de Oliveira 
Cc: David Weinehall 
Cc: Ville Syrjälä 

Imre Deak (5):
  drm/i915: Remove redundant toggling from the power well sync_hw hooks
  drm/i915: Call the sync_hw hook for power wells without a domain
  drm/i915/gen9: Fix clearing of the BIOS power well request register
  drm/i915: Preserve the state of power wells not explicitly enabled
  drm/i915: Add power well SW/HW state verification

 drivers/gpu/drm/i915/i915_drv.h |  20 
 drivers/gpu/drm/i915/intel_display.c|   2 +
 drivers/gpu/drm/i915/intel_drv.h|   1 +
 drivers/gpu/drm/i915/intel_runtime_pm.c | 188 +++-
 4 files changed, 138 insertions(+), 73 deletions(-)

-- 
2.5.0
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[Intel-gfx] [PATCH v2 4/5] drm/i915: Preserve the state of power wells not explicitly enabled

[Imre Deak]

Atm, power wells that BIOS has enabled, but which we don't explicitly
enable during power domain initialization would get disabled as we clear
the BIOS request bit in the given power well sync_hw hook. To prevent
this copy over any set request bits in the BIOS request register to the
driver request register and clear the BIOS request bit only afterwards.

This doesn't make a difference now, since we enable all power wells
during power domain initialization. A follow-up patchset will add power
wells for which this isn't true, so fix up the inconsistency.

Cc: Ander Conselvan de Oliveira 
Cc: David Weinehall 
Cc: Ville Syrjälä 
Signed-off-by: Imre Deak 
---
 drivers/gpu/drm/i915/intel_runtime_pm.c | 18 --
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 62c99a9..44d4da3 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -830,12 +830,14 @@ static void skl_set_power_well(struct drm_i915_private 
*dev_priv,
 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
   struct i915_power_well *power_well)
 {
-   /*
-* We're taking over the BIOS, so clear any requests made by it since
-* the driver is in charge now.
-*/
-   if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
+   /* Take over the request bit if set by BIOS. */
+   if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST) {
+   if (!(I915_READ(HSW_PWR_WELL_DRIVER) &
+ HSW_PWR_WELL_ENABLE_REQUEST))
+   I915_WRITE(HSW_PWR_WELL_DRIVER,
+  HSW_PWR_WELL_ENABLE_REQUEST);
I915_WRITE(HSW_PWR_WELL_BIOS, 0);
+   }
 }
 
 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
@@ -865,8 +867,12 @@ static void skl_power_well_sync_hw(struct drm_i915_private 
*dev_priv,
uint32_t mask = SKL_POWER_WELL_REQ(power_well->id);
uint32_t bios_req = I915_READ(HSW_PWR_WELL_BIOS);
 
-   /* Clear any request made by BIOS as driver is taking over */
+   /* Take over the request bit if set by BIOS. */
if (bios_req & mask) {
+   uint32_t drv_req = I915_READ(HSW_PWR_WELL_DRIVER);
+
+   if (!(drv_req & mask))
+   I915_WRITE(HSW_PWR_WELL_DRIVER, drv_req | mask);
I915_WRITE(HSW_PWR_WELL_BIOS, bios_req & ~mask);
}
 }
-- 
2.5.0

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[Intel-gfx] [PATCH v2 2/5] drm/i915: Call the sync_hw hook for power wells without a domain

[Imre Deak]

So far the sync_hw hook wasn't called for power wells not belonging to
any power domain, that is the GEN9 PW1 and MISC_IO power wells. This
wasn't a problem so far since the goal of the sync_hw hook - to clear
the corresponding BIOS request bit - was guaranteed by clearing the
whole BIOS request register elsewhere. This will change with the next
patch, so fix up the inconsistency.

While at it clean up the power well iterator helpers and move them to
the rest of iterators.

v2:
- Clean up the power well iterator helpers. (Ander)
- Move the helpers to i915_drv.h.

Cc: Ander Conselvan de Oliveira 
Cc: David Weinehall 
Cc: Ville Syrjälä 
Signed-off-by: Imre Deak 
Reviewed-by: Ander Conselvan de Oliveira  (v1)
---
 drivers/gpu/drm/i915/i915_drv.h | 20 
 drivers/gpu/drm/i915/intel_runtime_pm.c | 28 
 2 files changed, 24 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b5f150b..d138508 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -500,6 +500,26 @@ struct i915_hotplug {
for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
for_each_if (BIT_ULL(domain) & (mask))
 
+#define for_each_power_well(__dev_priv, __power_well)  
\
+   for ((__power_well) = (__dev_priv)->power_domains.power_wells;  \
+(__power_well) - (__dev_priv)->power_domains.power_wells < \
+   (__dev_priv)->power_domains.power_well_count;   \
+(__power_well)++)
+
+#define for_each_power_well_rev(__dev_priv, __power_well)  
\
+   for ((__power_well) = (__dev_priv)->power_domains.power_wells + 
\
+ (__dev_priv)->power_domains.power_well_count - 1; 
\
+(__power_well) - (__dev_priv)->power_domains.power_wells >= 0; 
\
+(__power_well)--)
+
+#define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask)
\
+   for_each_power_well(__dev_priv, __power_well)   
\
+   for_each_if ((__power_well)->domains & (__domain_mask))
+
+#define for_each_power_domain_well_rev(__dev_priv, __power_well, 
__domain_mask) \
+   for_each_power_well_rev(__dev_priv, __power_well)   
\
+   for_each_if ((__power_well)->domains & (__domain_mask))
+
 struct drm_i915_private;
 struct i915_mm_struct;
 struct i915_mmu_object;
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 0f64bc1..9bbbdbc 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -49,19 +49,6 @@
  * present for a given platform.
  */
 
-#define for_each_power_well(i, power_well, domain_mask, power_domains) \
-   for (i = 0; \
-i < (power_domains)->power_well_count &&   \
-((power_well) = &(power_domains)->power_wells[i]); \
-i++)   \
-   for_each_if ((power_well)->domains & (domain_mask))
-
-#define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
-   for (i = (power_domains)->power_well_count - 1;  \
-i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
-i--)\
-   for_each_if ((power_well)->domains & (domain_mask))
-
 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
int power_well_id);
 
@@ -198,19 +185,15 @@ static bool hsw_power_well_enabled(struct 
drm_i915_private *dev_priv,
 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
  enum intel_display_power_domain domain)
 {
-   struct i915_power_domains *power_domains;
struct i915_power_well *power_well;
bool is_enabled;
-   int i;
 
if (dev_priv->pm.suspended)
return false;
 
-   power_domains = _priv->power_domains;
-
is_enabled = true;
 
-   for_each_power_well_rev(i, power_well, BIT_ULL(domain), power_domains) {
+   for_each_power_domain_well_rev(dev_priv, power_well, BIT_ULL(domain)) {
if (power_well->always_on)
continue;
 
@@ -1663,9 +1646,8 @@ __intel_display_power_get_domain(struct drm_i915_private 
*dev_priv,
 {
struct i915_power_domains *power_domains = _priv->power_domains;
struct i915_power_well *power_well;
-   int i;
 
-   for_each_power_well(i, power_well, BIT_ULL(domain), power_domains)
+   

[Intel-gfx] [PATCH v2 5/5] drm/i915: Add power well SW/HW state verification

[Imre Deak]

Verify that the refcount of all power wells match their HW enabled
state at the end of modeset HW state readout.

Also add documentation on how the reference count for each power well is
supposed to be acquired during initialization and HW state readout.

Suggested by Ander.

Cc: Ander Conselvan de Oliveira 
Cc: David Weinehall 
Cc: Ville Syrjälä 
Signed-off-by: Imre Deak 
---
 drivers/gpu/drm/i915/intel_display.c|  2 +
 drivers/gpu/drm/i915/intel_drv.h|  1 +
 drivers/gpu/drm/i915/intel_runtime_pm.c | 85 -
 3 files changed, 87 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 88b7d96..00c3fd8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15572,6 +15572,8 @@ intel_modeset_setup_hw_state(struct drm_device *dev)
}
intel_display_set_init_power(dev_priv, false);
 
+   intel_power_domains_verify_state(dev_priv);
+
intel_fbc_init_pipe_state(dev_priv);
 }
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 6e37fba..50c9329 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1695,6 +1695,7 @@ int intel_power_domains_init(struct drm_i915_private *);
 void intel_power_domains_fini(struct drm_i915_private *);
 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool 
resume);
 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
+void intel_power_domains_verify_state(struct drm_i915_private *dev_priv);
 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 44d4da3..6b52258 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2683,7 +2683,10 @@ static void vlv_cmnlane_wa(struct drm_i915_private 
*dev_priv)
  * @resume: Called from resume code paths or not
  *
  * This function initializes the hardware power domain state and enables all
- * power domains using intel_display_set_init_power().
+ * power wells belonging to the INIT power domain. Power wells in other
+ * domains (and not in the INIT domain) are referenced or disabled during the
+ * modeset state HW readout. After that the reference count of each power well
+ * must match its HW enabled state, see intel_power_domains_verify_state().
  */
 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool 
resume)
 {
@@ -2736,6 +2739,86 @@ void intel_power_domains_suspend(struct drm_i915_private 
*dev_priv)
bxt_display_core_uninit(dev_priv);
 }
 
+static void intel_power_domains_dump_info(struct drm_i915_private *dev_priv)
+{
+   struct i915_power_domains *power_domains = _priv->power_domains;
+   struct i915_power_well *power_well;
+
+   for_each_power_well(dev_priv, power_well) {
+   enum intel_display_power_domain domain;
+
+   DRM_DEBUG_DRIVER("%-25s %d\n",
+power_well->name, power_well->count);
+
+   for_each_power_domain(domain, power_well->domains)
+   DRM_DEBUG_DRIVER("  %-23s %d\n",
+intel_display_power_domain_str(domain),
+
power_domains->domain_use_count[domain]);
+   }
+}
+
+/**
+ * intel_power_domains_verify_state - verify the HW/SW state for all power 
wells
+ * @dev_priv: i915 device instance
+ *
+ * Verify if the reference count of each power well matches its HW enabled
+ * state and the total refcount of the domains it belongs to. This must be
+ * called after modeset HW state sanitization, which is responsible for
+ * acquiring reference counts for any power wells in use and disabling the
+ * ones left on by BIOS but not required by any active output.
+ */
+void intel_power_domains_verify_state(struct drm_i915_private *dev_priv)
+{
+   struct i915_power_domains *power_domains = _priv->power_domains;
+   struct i915_power_well *power_well;
+   bool dump_domain_info;
+
+   mutex_lock(_domains->lock);
+
+   dump_domain_info = false;
+   for_each_power_well(dev_priv, power_well) {
+   enum intel_display_power_domain domain;
+   int domains_count;
+   bool enabled;
+
+   /*
+* Power wells not belonging to any domain (like the MISC_IO
+* and PW1 power wells) are under FW control, so ignore them,
+* since their state can change asynchronously.
+*/
+   if (!power_well->domains)
+   

[Intel-gfx] [PATCH v2 1/5] drm/i915: Remove redundant toggling from the power well sync_hw hooks

[Imre Deak]

Doing an explicit enable/disable in the power well sync_hw hook based on
the power well's reference count is redundant, since by the time these
hooks are called all the power wells are enabled and have a reference.
So remove the redundant toggling.

This is needed by a follow-up patchset that adds power wells which we
can't enable/disable during power domain initialization and so want to
preserve their state until modeset init time.

Cc: Ander Conselvan de Oliveira 
Cc: David Weinehall 
Cc: Ville Syrjälä 
Signed-off-by: Imre Deak 
Reviewed-by: Ander Conselvan de Oliveira 
---
 drivers/gpu/drm/i915/intel_runtime_pm.c | 52 +++--
 1 file changed, 10 insertions(+), 42 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 8795679..0f64bc1 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -847,8 +847,6 @@ static void skl_set_power_well(struct drm_i915_private 
*dev_priv,
 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
   struct i915_power_well *power_well)
 {
-   hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
-
/*
 * We're taking over the BIOS, so clear any requests made by it since
 * the driver is in charge now.
@@ -881,8 +879,6 @@ static bool skl_power_well_enabled(struct drm_i915_private 
*dev_priv,
 static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
 {
-   skl_set_power_well(dev_priv, power_well, power_well->count > 0);
-
/* Clear any request made by BIOS as driver is taking over */
I915_WRITE(HSW_PWR_WELL_BIOS, 0);
 }
@@ -917,16 +913,6 @@ static bool bxt_dpio_cmn_power_well_enabled(struct 
drm_i915_private *dev_priv,
return bxt_ddi_phy_is_enabled(dev_priv, power_well->data);
 }
 
-static void bxt_dpio_cmn_power_well_sync_hw(struct drm_i915_private *dev_priv,
-   struct i915_power_well *power_well)
-{
-   if (power_well->count > 0)
-   bxt_dpio_cmn_power_well_enable(dev_priv, power_well);
-   else
-   bxt_dpio_cmn_power_well_disable(dev_priv, power_well);
-}
-
-
 static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv)
 {
struct i915_power_well *power_well;
@@ -989,13 +975,9 @@ static void gen9_dc_off_power_well_disable(struct 
drm_i915_private *dev_priv,
gen9_enable_dc5(dev_priv);
 }
 
-static void gen9_dc_off_power_well_sync_hw(struct drm_i915_private *dev_priv,
-  struct i915_power_well *power_well)
+static void i9xx_power_well_sync_hw_noop(struct drm_i915_private *dev_priv,
+struct i915_power_well *power_well)
 {
-   if (power_well->count > 0)
-   gen9_dc_off_power_well_enable(dev_priv, power_well);
-   else
-   gen9_dc_off_power_well_disable(dev_priv, power_well);
 }
 
 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
@@ -1045,12 +1027,6 @@ static void vlv_set_power_well(struct drm_i915_private 
*dev_priv,
mutex_unlock(_priv->rps.hw_lock);
 }
 
-static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
-  struct i915_power_well *power_well)
-{
-   vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
-}
-
 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
  struct i915_power_well *power_well)
 {
@@ -1661,14 +1637,6 @@ static void chv_set_pipe_power_well(struct 
drm_i915_private *dev_priv,
mutex_unlock(_priv->rps.hw_lock);
 }
 
-static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
-   struct i915_power_well *power_well)
-{
-   WARN_ON_ONCE(power_well->id != PIPE_A);
-
-   chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);
-}
-
 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
   struct i915_power_well *power_well)
 {
@@ -1914,21 +1882,21 @@ void intel_display_power_put(struct drm_i915_private 
*dev_priv,
BIT_ULL(POWER_DOMAIN_INIT))
 
 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
-   .sync_hw = i9xx_always_on_power_well_noop,
+   .sync_hw = i9xx_power_well_sync_hw_noop,
.enable = i9xx_always_on_power_well_noop,
.disable = i9xx_always_on_power_well_noop,
.is_enabled = i9xx_always_on_power_well_enabled,
 };
 
 static const struct i915_power_well_ops chv_pipe_power_well_ops = {
-   .sync_hw = chv_pipe_power_well_sync_hw,
+   .sync_hw 

Re: [Intel-gfx] Ubuntu 16.04.2 LTS with Intel Corporation Sky Lake Integrated Graphics (rev 06)

[Eric Johansson]

On 2/17/2017 at 2:30 PM, "Jani Nikula"  wrote:
>
>On Fri, 17 Feb 2017, Eric Johansson  
>wrote:
>> Hello,
>>
>> I have an HP EliteOne 800 G2 AiO which according to "lspci -v" 
>has a
>> Intel Corporation Sky Lake Integrated Graphics (rev 06). I have
>> previously installed Ubuntu 16.04.1 LTS with kernel 4.4 on the
>> computer and today also installed Ubuntu 16.04.2 LTS (clean 
>install
>> from a USB memory) which has kernel 4.8.0-36-generic. If I 
>understand
>> things right there should be new graphic hardware support in 
>16.04.2.
>>
>> Unfortunately, for both 16.04.2 and 16.04.1 I have the same 
>problem
>> which is that the screen is split in half so that the whole 
>desktop is
>> squeezed into the upper half of the screen. Do you have any idea 
>how
>> to get the graphics working? Thanks in advance!
>
>Try disabling legacy boot and switching to UEFI boot in the BIOS
>settings.
>
>Relevant bug report 
>https://bugs.freedesktop.org/show_bug.cgi?id=97822

Thanks, however, I probably did something stupid since it didn't work for me. I 
went into BIOS: F10 > BIOS Setup > Advanced > Secure Boot Configuration - here 
I changed "Legacy Support Enable and Secure Boot Disable" to "Legacy Support 
Disable and Secure Boot Disable". When I then try to boot the system I get 
"BootDevice Not Found. Please install an operating system on your hard disk. 
Hard Disk - (3F0)". If I try to boot the system from a USB memory to install 
Linux again I cannot do it since if I press F9 for boot menu it is just blank. 
It suggest a hard disk check and the quick test shows no errors. When I switch 
back to "Legacy Support Enable and Secure Boot Disable" the installed system 
boots Linux as before (with the same graphics problem as before of course). Any 
idea what I am doing wrong?

Best regards, Eric

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Re: [Intel-gfx] [PATCH v2 0/4] drm: handle override/firmware edid at the lowest level

[Ville Syrjälä]

On Fri, Feb 17, 2017 at 05:20:50PM +0200, Jani Nikula wrote:
> v2 of cover.1487241304.git.jani.nikula@intel.com">http://mid.mail-archive.com/cover.1487241304.git.jani.nikula@intel.com

lgtm. For the series
Reviewed-by: Ville Syrjälä 

-- 
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Intel OTC
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[Intel-gfx] [PATCH i-g-t] kms_atomic_transition: Initialize pipe_crcs to avoid segfault

[Brian Starkey]

igt_pipe_crc_new() is skipped for non-Intel devices, but the later calls
to collect_crcs_mask() will attempt to retrieve CRC values if the
pipe_crcs pointers are non-NULL.

Zero-initialise pipe_crcs to avoid accessing garbage pointers on
non-Intel devices.

Signed-off-by: Brian Starkey 
---
 tests/kms_atomic_transition.c |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tests/kms_atomic_transition.c b/tests/kms_atomic_transition.c
index ba8c8b5ca02b..1599f0b36c4e 100644
--- a/tests/kms_atomic_transition.c
+++ b/tests/kms_atomic_transition.c
@@ -608,7 +608,7 @@ static void run_modeset_tests(igt_display_t *display, int 
howmany, bool nonblock
struct igt_fb fbs[2];
int i, j;
unsigned iter_max = 1 << display->n_pipes;
-   igt_pipe_crc_t *pipe_crcs[I915_MAX_PIPES];
+   igt_pipe_crc_t *pipe_crcs[I915_MAX_PIPES] = { 0 };
igt_output_t *output;
unsigned width = 0, height = 0;
bool skip_test = false;
-- 
1.7.9.5

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Re: [Intel-gfx] [PATCH 4/4] drm/i915: reorganize the get_cdclk assignment

[Ville Syrjälä]

On Fri, Feb 17, 2017 at 01:17:22PM -0200, Paulo Zanoni wrote:
> Em Sex, 2017-02-17 às 16:05 +0200, Ville Syrjälä escreveu:
> > On Fri, Feb 17, 2017 at 11:22:07AM -0200, Paulo Zanoni wrote:
> > > 
> > > Possible problems of the current if-ladder:
> > >   - It's a huge if ladder with almost a different check for each of
> > > our platforms.
> > >   - It mixes 3 different types of checks: IS_GENX, IS_PLATFORM and
> > > IS_GROUP_OF_PLATFORMS.
> > >   - As demonstrated by the recent IS_G4X commit, it's not easy to
> > > be
> > > sure if a platform down on the list isn't also checked earlier.
> > >   - As demonstrated by the WARN at the end, it's not easy to be
> > > sure
> > > if we're actually checking for every single platform.
> > > 
> > > Possible advantages of the new switch statement:
> > >   - It may be easier for the compiler to optimize stuff (I didn't
> > > check this), especially since the values are labels of an enum.
> > >   - The compiler will tell us in case we miss some platform.
> > >   - All platforms are explicitly there instead of maybe hidden in
> > > some
> > > check for a certain group of platforms such as IS_GEN9_BC.
> > 
> > Performance is a bit of a moot point since this is run exaclty once,
> > but
> > the IS_GEN9_BC() stuff I tend to agree with. I don't really like
> > those
> > macros at all since they don't actully mean anything as far as the
> > hardware features go.
> 
> I think they make some sense when they're a single check. But when we
> have tons of checks for tons of platforms, I don't know.

The problem problem is that they basically mean different things in
different parts of the driver. So you anyway have to mentally expand
the list out to figure out what's really going on.

> 
> > 
> > > 
> > > 
> > > Possible disadvantages with the new code:
> > >   - A few lines bigger.
> > > 
> > > Signed-off-by: Paulo Zanoni 
> > > ---
> > >  drivers/gpu/drm/i915/intel_cdclk.c | 103 ++---
> > > 
> > >  1 file changed, 62 insertions(+), 41 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
> > > b/drivers/gpu/drm/i915/intel_cdclk.c
> > > index 7c92dc7..58a2f5c 100644
> > > --- a/drivers/gpu/drm/i915/intel_cdclk.c
> > > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> > > @@ -1789,49 +1789,70 @@ void intel_init_cdclk_hooks(struct
> > > drm_i915_private *dev_priv)
> > >   dev_priv->display.modeset_calc_cdclk =
> > > skl_modeset_calc_cdclk;
> > >   }
> > >  
> > > - if (IS_GEN9_BC(dev_priv))
> > > - dev_priv->display.get_cdclk = skl_get_cdclk;
> > > - else if (IS_GEN9_LP(dev_priv))
> > > - dev_priv->display.get_cdclk = bxt_get_cdclk;
> > > - else if (IS_BROADWELL(dev_priv))
> > > - dev_priv->display.get_cdclk = bdw_get_cdclk;
> > > - else if (IS_HASWELL(dev_priv))
> > > - dev_priv->display.get_cdclk = hsw_get_cdclk;
> > > - else if (IS_VALLEYVIEW(dev_priv) ||
> > > IS_CHERRYVIEW(dev_priv))
> > > - dev_priv->display.get_cdclk = vlv_get_cdclk;
> > > - else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
> > > + switch (INTEL_INFO(dev_priv)->platform) {
> > > + case INTEL_PLATFORM_UNINITIALIZED:
> > 
> > Just default: ?
> 
> If we add a default case the compiler will stop complaining in case we
> don't explicitly list every platform. It's a trade-off, I really think
> the current way is slightly better, but I won't oppose in case you
> still think it's better adding the default case.

Nah. Getting the compiler to do the work for us seems like
a decent idea. 

> 
> 
> > 
> > > 
> > > + MISSING_CASE(INTEL_INFO(dev_priv)->platform);
> > > + /* Fall through. */
> > > + case INTEL_I830:
> > > + dev_priv->display.get_cdclk =
> > > fixed_133mhz_get_cdclk;
> > > + break;
> > > + case INTEL_I845G:
> > > + dev_priv->display.get_cdclk =
> > > fixed_200mhz_get_cdclk;
> > > + break;
> > > + case INTEL_I85X:
> > > + dev_priv->display.get_cdclk = i85x_get_cdclk;
> > > + break;
> > > + case INTEL_I865G:
> > > + dev_priv->display.get_cdclk =
> > > fixed_266mhz_get_cdclk;
> > > + break;
> > > + case INTEL_I915G:
> > > + dev_priv->display.get_cdclk =
> > > fixed_333mhz_get_cdclk;
> > > + break;
> > > + case INTEL_I915GM:
> > > + dev_priv->display.get_cdclk = i915gm_get_cdclk;
> > > + break;
> > > + case INTEL_I945G:
> > > + case INTEL_I965G:
> > > + case INTEL_SANDYBRIDGE:
> > > + case INTEL_IVYBRIDGE:
> > 
> > I don't particularly like this disorder. I just managed to get the
> > list into some sort of sane order recently.
> 
> My original thought here was that since the compiler will actually
> complain in case we miss some platform, keeping a strict order is not
> as meaningful as it was before. But I was also wondering if this was
> actually better or not, so I can change this.

And unsorted list is quite hard to verify visually for correctness. We

[Intel-gfx] ✓ Fi.CI.BAT: success for Small clocking code refactor

[Patchwork]

== Series Details ==

Series: Small clocking code refactor
URL   : https://patchwork.freedesktop.org/series/19840/
State : success

== Summary ==

Series 19840v1 Small clocking code refactor
https://patchwork.freedesktop.org/api/1.0/series/19840/revisions/1/mbox/

fi-bdw-5557u total:252  pass:241  dwarn:0   dfail:0   fail:0   skip:11 
fi-bsw-n3050 total:252  pass:213  dwarn:0   dfail:0   fail:0   skip:39 
fi-bxt-j4205 total:252  pass:233  dwarn:0   dfail:0   fail:0   skip:19 
fi-bxt-t5700 total:83   pass:70   dwarn:0   dfail:0   fail:0   skip:12 
fi-byt-j1900 total:252  pass:225  dwarn:0   dfail:0   fail:0   skip:27 
fi-byt-n2820 total:252  pass:221  dwarn:0   dfail:0   fail:0   skip:31 
fi-hsw-4770  total:252  pass:236  dwarn:0   dfail:0   fail:0   skip:16 
fi-hsw-4770r total:252  pass:236  dwarn:0   dfail:0   fail:0   skip:16 
fi-ilk-650   total:252  pass:202  dwarn:0   dfail:0   fail:0   skip:50 
fi-ivb-3520m total:252  pass:234  dwarn:0   dfail:0   fail:0   skip:18 
fi-ivb-3770  total:252  pass:234  dwarn:0   dfail:0   fail:0   skip:18 
fi-kbl-7500u total:252  pass:234  dwarn:0   dfail:0   fail:0   skip:18 
fi-skl-6260u total:252  pass:242  dwarn:0   dfail:0   fail:0   skip:10 
fi-skl-6700hqtotal:252  pass:235  dwarn:0   dfail:0   fail:0   skip:17 
fi-skl-6700k total:252  pass:230  dwarn:4   dfail:0   fail:0   skip:18 
fi-skl-6770hqtotal:252  pass:242  dwarn:0   dfail:0   fail:0   skip:10 
fi-snb-2520m total:252  pass:224  dwarn:0   dfail:0   fail:0   skip:28 
fi-snb-2600  total:252  pass:223  dwarn:0   dfail:0   fail:0   skip:29 

2b7ce9512d9770350bc2a59652cc7bf469bc544a drm-tip: 2017y-02m-17d-12h-20m-31s UTC 
integration manifest
2d2db47 drm/i915: reorganize the get_cdclk assignment
e370ecb drm/i915: remove potentially confusing IS_G4X checks
78520fc drm/i915: add intel_calc_cdclk()
c82d3ef drm/i915: kill {bdw, bxt}_modeset_calc_cdclk

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3880/
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[Intel-gfx] [PATCH v2 3/4] drm/edid: respect connector force for drm_get_edid ddc probe

[Jani Nikula]

Skip DDC probe for forced connector status. Don't try to read the EDID
if the connector is forced off. Skipping probe for forced on connectors
will make more sense when drm_do_get_edid() will handle override and
firmware EDIDs.

Suggested-by: Ville Syrjälä 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/drm_edid.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 4bb50e0e7110..e1743ab276dc 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -1428,7 +1428,10 @@ struct edid *drm_get_edid(struct drm_connector 
*connector,
 {
struct edid *edid;
 
-   if (!drm_probe_ddc(adapter))
+   if (connector->force == DRM_FORCE_OFF)
+   return NULL;
+
+   if (connector->force == DRM_FORCE_UNSPECIFIED && 
!drm_probe_ddc(adapter))
return NULL;
 
edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
-- 
2.1.4

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[Intel-gfx] [PATCH v2 1/4] drm: move edid property update and add modes out of edid firmware loader

[Jani Nikula]

Make the firmware loader more generic and generally useful.

Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/drm_edid_load.c| 17 -
 drivers/gpu/drm/drm_probe_helper.c |  8 +++-
 include/drm/drm_edid.h |  7 ---
 3 files changed, 15 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/drm_edid_load.c b/drivers/gpu/drm/drm_edid_load.c
index 622f788bff46..1c0495acf341 100644
--- a/drivers/gpu/drm/drm_edid_load.c
+++ b/drivers/gpu/drm/drm_edid_load.c
@@ -256,15 +256,14 @@ static void *edid_load(struct drm_connector *connector, 
const char *name,
return edid;
 }
 
-int drm_load_edid_firmware(struct drm_connector *connector)
+struct edid *drm_load_edid_firmware(struct drm_connector *connector)
 {
const char *connector_name = connector->name;
char *edidname, *last, *colon, *fwstr, *edidstr, *fallback = NULL;
-   int ret;
struct edid *edid;
 
if (edid_firmware[0] == '\0')
-   return 0;
+   return ERR_PTR(-ENOENT);
 
/*
 * If there are multiple edid files specified and separated
@@ -293,7 +292,7 @@ int drm_load_edid_firmware(struct drm_connector *connector)
if (!edidname) {
if (!fallback) {
kfree(fwstr);
-   return 0;
+   return ERR_PTR(-ENOENT);
}
edidname = fallback;
}
@@ -305,13 +304,5 @@ int drm_load_edid_firmware(struct drm_connector *connector)
edid = edid_load(connector, edidname, connector_name);
kfree(fwstr);
 
-   if (IS_ERR_OR_NULL(edid))
-   return 0;
-
-   drm_mode_connector_update_edid_property(connector, edid);
-   ret = drm_add_edid_modes(connector, edid);
-   drm_edid_to_eld(connector, edid);
-   kfree(edid);
-
-   return ret;
+   return edid;
 }
diff --git a/drivers/gpu/drm/drm_probe_helper.c 
b/drivers/gpu/drm/drm_probe_helper.c
index 93381454bdf7..358957118ca9 100644
--- a/drivers/gpu/drm/drm_probe_helper.c
+++ b/drivers/gpu/drm/drm_probe_helper.c
@@ -311,7 +311,13 @@ int drm_helper_probe_single_connector_modes(struct 
drm_connector *connector,
count = drm_add_edid_modes(connector, edid);
drm_edid_to_eld(connector, edid);
} else {
-   count = drm_load_edid_firmware(connector);
+   struct edid *edid = drm_load_edid_firmware(connector);
+   if (!IS_ERR_OR_NULL(edid)) {
+   drm_mode_connector_update_edid_property(connector, 
edid);
+   count = drm_add_edid_modes(connector, edid);
+   drm_edid_to_eld(connector, edid);
+   kfree(edid);
+   }
if (count == 0)
count = (*connector_funcs->get_modes)(connector);
}
diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h
index 43fb0ac5eb9c..a55eea4afb61 100644
--- a/include/drm/drm_edid.h
+++ b/include/drm/drm_edid.h
@@ -331,11 +331,12 @@ int drm_av_sync_delay(struct drm_connector *connector,
  const struct drm_display_mode *mode);
 
 #ifdef CONFIG_DRM_LOAD_EDID_FIRMWARE
-int drm_load_edid_firmware(struct drm_connector *connector);
+struct edid *drm_load_edid_firmware(struct drm_connector *connector);
 #else
-static inline int drm_load_edid_firmware(struct drm_connector *connector)
+static inline struct edid *
+drm_load_edid_firmware(struct drm_connector *connector)
 {
-   return 0;
+   return ERR_PTR(-ENOENT);
 }
 #endif
 
-- 
2.1.4

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[Intel-gfx] [PATCH v2 4/4] drm: handle override edid and firmware EDID at drm_do_get_edid() level

[Jani Nikula]

Handle debugfs override edid and firmware edid at the low level to
transparently and completely replace the real edid. Previously, we
practically only used the modes from the override EDID, and none of the
other data. This also prevents actual EDID reads when the EDID is to be
overridden, but retains the DDC probe.

Move firmware EDID loading from helper to core, as the functionality
moves to lower level as well. This will result in a change of module
parameter from drm_kms_helper.edid_firmware to drm.edid_firmware, which
arguably makes more sense anyway.

FIXME: validate override edid, deduplicate firmware edid validation.

v2: move firmware loading to core

Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/Kconfig|  2 +-
 drivers/gpu/drm/Makefile   |  2 +-
 drivers/gpu/drm/drm_edid.c | 15 +++
 drivers/gpu/drm/drm_probe_helper.c | 19 +--
 4 files changed, 18 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 90bc65d07a35..f983ef60299c 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -101,7 +101,7 @@ config DRM_FBDEV_EMULATION
 
 config DRM_LOAD_EDID_FIRMWARE
bool "Allow to specify an EDID data set instead of probing for it"
-   depends on DRM_KMS_HELPER
+   depends on DRM
help
  Say Y here, if you want to use EDID data to be loaded from the
  /lib/firmware directory or one of the provided built-in
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 92de3991fa56..a10ac095608f 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -27,13 +27,13 @@ drm-$(CONFIG_DRM_PANEL) += drm_panel.o
 drm-$(CONFIG_OF) += drm_of.o
 drm-$(CONFIG_AGP) += drm_agpsupport.o
 drm-$(CONFIG_DEBUG_FS) += drm_debugfs.o drm_debugfs_crc.o
+drm-$(CONFIG_DRM_LOAD_EDID_FIRMWARE) += drm_edid_load.o
 
 drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o drm_probe_helper.o \
drm_plane_helper.o drm_dp_mst_topology.o drm_atomic_helper.o \
drm_kms_helper_common.o drm_dp_dual_mode_helper.o \
drm_simple_kms_helper.o drm_modeset_helper.o
 
-drm_kms_helper-$(CONFIG_DRM_LOAD_EDID_FIRMWARE) += drm_edid_load.o
 drm_kms_helper-$(CONFIG_DRM_FBDEV_EMULATION) += drm_fb_helper.o
 drm_kms_helper-$(CONFIG_DRM_KMS_CMA_HELPER) += drm_fb_cma_helper.o
 drm_kms_helper-$(CONFIG_DRM_DP_AUX_CHARDEV) += drm_dp_aux_dev.o
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index e1743ab276dc..4007998d5ce3 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -1309,6 +1309,10 @@ static void connector_bad_edid(struct drm_connector 
*connector,
  * level, drivers must make all reasonable efforts to expose it as an I2C
  * adapter and use drm_get_edid() instead of abusing this function.
  *
+ * The EDID may be overridden using debugfs override_edid or firmare EDID
+ * (drm_load_edid_firmware()), in this priority order. Having either of them
+ * bypasses actual EDID reads.
+ *
  * Return: Pointer to valid EDID or NULL if we couldn't find any.
  */
 struct edid *drm_do_get_edid(struct drm_connector *connector,
@@ -1318,6 +1322,17 @@ struct edid *drm_do_get_edid(struct drm_connector 
*connector,
 {
int i, j = 0, valid_extensions = 0;
u8 *edid, *new;
+   struct edid *override = NULL;
+
+   if (connector->override_edid)
+   override = drm_edid_duplicate((const struct edid *)
+ connector->edid_blob_ptr->data);
+
+   if (!override)
+   override = drm_load_edid_firmware(connector);
+
+   if (!IS_ERR_OR_NULL(override))
+   return override;
 
if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
return NULL;
diff --git a/drivers/gpu/drm/drm_probe_helper.c 
b/drivers/gpu/drm/drm_probe_helper.c
index 358957118ca9..871326cbc465 100644
--- a/drivers/gpu/drm/drm_probe_helper.c
+++ b/drivers/gpu/drm/drm_probe_helper.c
@@ -199,8 +199,6 @@ drm_connector_detect(struct drm_connector *connector, bool 
force)
  *drm_mode_probed_add(). New modes start their life with status as OK.
  *Modes are added from a single source using the following priority order.
  *
- *- debugfs 'override_edid' (used for testing only)
- *- firmware EDID (drm_load_edid_firmware())
  *- _connector_helper_funcs.get_modes vfunc
  *- if the connector status is connector_status_connected, standard
  *  VESA DMT modes up to 1024x768 are automatically added
@@ -305,22 +303,7 @@ int drm_helper_probe_single_connector_modes(struct 
drm_connector *connector,
goto prune;
}
 
-   if (connector->override_edid) {
-   struct edid *edid = (struct edid *) 
connector->edid_blob_ptr->data;
-
-   count = drm_add_edid_modes(connector, edid);
-   drm_edid_to_eld(connector, edid);
-   } else {
-   

[Intel-gfx] [PATCH v2 2/4] drm: do not debug log about missing CEA extensions on NULL edid

[Jani Nikula]

Make the drm_edid_to_eld() function useful for resetting, not just
setting, the ELD and HDMI VSDB data, without debug warnings about
missing CEA extensions.

Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/drm_edid.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 24e7b282f16c..4bb50e0e7110 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -3437,6 +3437,9 @@ void drm_edid_to_eld(struct drm_connector *connector, 
struct edid *edid)
connector->video_latency[1] = 0;
connector->audio_latency[1] = 0;
 
+   if (!edid)
+   return;
+
cea = drm_find_cea_extension(edid);
if (!cea) {
DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
-- 
2.1.4

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[Intel-gfx] [PATCH v2 0/4] drm: handle override/firmware edid at the lowest level

[Jani Nikula]

v2 of cover.1487241304.git.jani.nikula@intel.com">http://mid.mail-archive.com/cover.1487241304.git.jani.nikula@intel.com

BR,
Jani.


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Re: [Intel-gfx] [PATCH 4/4] drm/i915: reorganize the get_cdclk assignment

[Paulo Zanoni]

Em Sex, 2017-02-17 às 16:05 +0200, Ville Syrjälä escreveu:
> On Fri, Feb 17, 2017 at 11:22:07AM -0200, Paulo Zanoni wrote:
> > 
> > Possible problems of the current if-ladder:
> >   - It's a huge if ladder with almost a different check for each of
> > our platforms.
> >   - It mixes 3 different types of checks: IS_GENX, IS_PLATFORM and
> > IS_GROUP_OF_PLATFORMS.
> >   - As demonstrated by the recent IS_G4X commit, it's not easy to
> > be
> > sure if a platform down on the list isn't also checked earlier.
> >   - As demonstrated by the WARN at the end, it's not easy to be
> > sure
> > if we're actually checking for every single platform.
> > 
> > Possible advantages of the new switch statement:
> >   - It may be easier for the compiler to optimize stuff (I didn't
> > check this), especially since the values are labels of an enum.
> >   - The compiler will tell us in case we miss some platform.
> >   - All platforms are explicitly there instead of maybe hidden in
> > some
> > check for a certain group of platforms such as IS_GEN9_BC.
> 
> Performance is a bit of a moot point since this is run exaclty once,
> but
> the IS_GEN9_BC() stuff I tend to agree with. I don't really like
> those
> macros at all since they don't actully mean anything as far as the
> hardware features go.

I think they make some sense when they're a single check. But when we
have tons of checks for tons of platforms, I don't know.

> 
> > 
> > 
> > Possible disadvantages with the new code:
> >   - A few lines bigger.
> > 
> > Signed-off-by: Paulo Zanoni 
> > ---
> >  drivers/gpu/drm/i915/intel_cdclk.c | 103 ++---
> > 
> >  1 file changed, 62 insertions(+), 41 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
> > b/drivers/gpu/drm/i915/intel_cdclk.c
> > index 7c92dc7..58a2f5c 100644
> > --- a/drivers/gpu/drm/i915/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> > @@ -1789,49 +1789,70 @@ void intel_init_cdclk_hooks(struct
> > drm_i915_private *dev_priv)
> >     dev_priv->display.modeset_calc_cdclk =
> > skl_modeset_calc_cdclk;
> >     }
> >  
> > -   if (IS_GEN9_BC(dev_priv))
> > -   dev_priv->display.get_cdclk = skl_get_cdclk;
> > -   else if (IS_GEN9_LP(dev_priv))
> > -   dev_priv->display.get_cdclk = bxt_get_cdclk;
> > -   else if (IS_BROADWELL(dev_priv))
> > -   dev_priv->display.get_cdclk = bdw_get_cdclk;
> > -   else if (IS_HASWELL(dev_priv))
> > -   dev_priv->display.get_cdclk = hsw_get_cdclk;
> > -   else if (IS_VALLEYVIEW(dev_priv) ||
> > IS_CHERRYVIEW(dev_priv))
> > -   dev_priv->display.get_cdclk = vlv_get_cdclk;
> > -   else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
> > +   switch (INTEL_INFO(dev_priv)->platform) {
> > +   case INTEL_PLATFORM_UNINITIALIZED:
> 
> Just default: ?

If we add a default case the compiler will stop complaining in case we
don't explicitly list every platform. It's a trade-off, I really think
the current way is slightly better, but I won't oppose in case you
still think it's better adding the default case.


> 
> > 
> > +   MISSING_CASE(INTEL_INFO(dev_priv)->platform);
> > +   /* Fall through. */
> > +   case INTEL_I830:
> > +   dev_priv->display.get_cdclk =
> > fixed_133mhz_get_cdclk;
> > +   break;
> > +   case INTEL_I845G:
> > +   dev_priv->display.get_cdclk =
> > fixed_200mhz_get_cdclk;
> > +   break;
> > +   case INTEL_I85X:
> > +   dev_priv->display.get_cdclk = i85x_get_cdclk;
> > +   break;
> > +   case INTEL_I865G:
> > +   dev_priv->display.get_cdclk =
> > fixed_266mhz_get_cdclk;
> > +   break;
> > +   case INTEL_I915G:
> > +   dev_priv->display.get_cdclk =
> > fixed_333mhz_get_cdclk;
> > +   break;
> > +   case INTEL_I915GM:
> > +   dev_priv->display.get_cdclk = i915gm_get_cdclk;
> > +   break;
> > +   case INTEL_I945G:
> > +   case INTEL_I965G:
> > +   case INTEL_SANDYBRIDGE:
> > +   case INTEL_IVYBRIDGE:
> 
> I don't particularly like this disorder. I just managed to get the
> list into some sort of sane order recently.

My original thought here was that since the compiler will actually
complain in case we miss some platform, keeping a strict order is not
as meaningful as it was before. But I was also wondering if this was
actually better or not, so I can change this.

But I did notice you sorted the list. In fact, I originally wrote this
commit against a tree without your improvements, so one of the reasons
I cited in the commit message was the mess of an ordering we had at
that time :).

> 
> > 
> >     dev_priv->display.get_cdclk =
> > fixed_400mhz_get_cdclk;
> > -   else if (IS_GEN5(dev_priv))
> > -   dev_priv->display.get_cdclk =
> > fixed_450mhz_get_cdclk;
> > -   else if (IS_GM45(dev_priv))
> > -   dev_priv->display.get_cdclk = gm45_get_cdclk;
> > -   else if (IS_G45(dev_priv))
> > + 

Re: [Intel-gfx] [PATCH 2/3] drm/i915/glk: Enable pipe CSC

[Ander Conselvan De Oliveira]

On Fri, 2017-02-17 at 14:06 +0200, Ander Conselvan de Oliveira wrote:
> Now that the pre-csc degamma table is set up correctly in Geminilake,
> pipe CSC can be enabled without causing a black screen.
> 
> v2: Rebase.
> Signed-off-by: Ander Conselvan de Oliveira 
> 
> Reviewed-by: Ville Syrjälä 

Pushed up to here. Thanks for the reviews.

Ander

> ---
>  drivers/gpu/drm/i915/intel_display.c | 1 +
>  drivers/gpu/drm/i915/intel_sprite.c  | 1 +
>  2 files changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index b05d9c8..730aee7 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3327,6 +3327,7 @@ static void skylake_update_primary_plane(struct 
> drm_plane *plane,
>   if (IS_GEMINILAKE(dev_priv)) {
>   I915_WRITE(PLANE_COLOR_CTL(pipe, plane_id),
>  PLANE_COLOR_PIPE_GAMMA_ENABLE |
> +PLANE_COLOR_PIPE_CSC_ENABLE |
>  PLANE_COLOR_PLANE_GAMMA_DISABLE);
>   } else {
>   plane_ctl |=
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c 
> b/drivers/gpu/drm/i915/intel_sprite.c
> index b16a295..27e0752 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -224,6 +224,7 @@ skl_update_plane(struct drm_plane *drm_plane,
>   if (IS_GEMINILAKE(dev_priv)) {
>   I915_WRITE(PLANE_COLOR_CTL(pipe, plane_id),
>  PLANE_COLOR_PIPE_GAMMA_ENABLE |
> +PLANE_COLOR_PIPE_CSC_ENABLE |
>  PLANE_COLOR_PLANE_GAMMA_DISABLE);
>   } else {
>   plane_ctl |=
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[Intel-gfx] [CI 2/6] drm/i915: Postpone fake breadcrumb interrupt until real interrupts cease

[Chris Wilson]

When the timer expires for checking on interrupt processing, check to
see if any interrupts arrived within the last time period. If real
interrupts are still being delivered, we can be reassured that we
haven't missed the final interrupt as the waiter will still be woken.
Only once all activity ceases, do we have to worry about the waiter
never being woken and so need to install a timer to kick the waiter for
a slow arrival of a seqno.

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
Reviewed-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_irq.c  |  1 +
 drivers/gpu/drm/i915/intel_breadcrumbs.c | 23 ++-
 drivers/gpu/drm/i915/intel_ringbuffer.h  |  3 ++-
 3 files changed, 13 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 91be31617e78..57fa1bf78a85 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1033,6 +1033,7 @@ static void ironlake_rps_change_irq_handler(struct 
drm_i915_private *dev_priv)
 
 static void notify_ring(struct intel_engine_cs *engine)
 {
+   atomic_inc(>irq_count);
set_bit(ENGINE_IRQ_BREADCRUMB, >irq_posted);
if (intel_engine_wakeup(engine))
trace_i915_gem_request_notify(engine);
diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c 
b/drivers/gpu/drm/i915/intel_breadcrumbs.c
index 74cb7b91b5db..d229a555db25 100644
--- a/drivers/gpu/drm/i915/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c
@@ -26,6 +26,11 @@
 
 #include "i915_drv.h"
 
+static unsigned long wait_timeout(void)
+{
+   return round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES);
+}
+
 static void intel_breadcrumbs_hangcheck(unsigned long data)
 {
struct intel_engine_cs *engine = (struct intel_engine_cs *)data;
@@ -34,8 +39,9 @@ static void intel_breadcrumbs_hangcheck(unsigned long data)
if (!b->irq_enabled)
return;
 
-   if (time_before(jiffies, b->timeout)) {
-   mod_timer(>hangcheck, b->timeout);
+   if (b->hangcheck_interrupts != atomic_read(>irq_count)) {
+   b->hangcheck_interrupts = atomic_read(>irq_count);
+   mod_timer(>hangcheck, wait_timeout());
return;
}
 
@@ -55,11 +61,6 @@ static void intel_breadcrumbs_hangcheck(unsigned long data)
i915_queue_hangcheck(engine->i915);
 }
 
-static unsigned long wait_timeout(void)
-{
-   return round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES);
-}
-
 static void intel_breadcrumbs_fake_irq(unsigned long data)
 {
struct intel_engine_cs *engine = (struct intel_engine_cs *)data;
@@ -129,6 +130,7 @@ static void __intel_breadcrumbs_enable_irq(struct 
intel_breadcrumbs *b)
 
/* No interrupts? Kick the waiter every jiffie! */
if (intel_irqs_enabled(i915)) {
+   b->hangcheck_interrupts = 0;
if (!test_bit(engine->id, >gpu_error.test_irq_rings))
irq_enable(engine);
b->irq_enabled = true;
@@ -140,8 +142,7 @@ static void __intel_breadcrumbs_enable_irq(struct 
intel_breadcrumbs *b)
i915_queue_hangcheck(i915);
} else {
/* Ensure we never sleep indefinitely */
-   GEM_BUG_ON(!time_after(b->timeout, jiffies));
-   mod_timer(>hangcheck, b->timeout);
+   mod_timer(>hangcheck, wait_timeout());
}
 }
 
@@ -258,7 +259,6 @@ static bool __intel_engine_add_wait(struct intel_engine_cs 
*engine,
GEM_BUG_ON(!next && !first);
if (next && next != >node) {
GEM_BUG_ON(first);
-   b->timeout = wait_timeout();
b->first_wait = to_wait(next);
rcu_assign_pointer(b->irq_seqno_bh, b->first_wait->tsk);
/* As there is a delay between reading the current
@@ -286,7 +286,6 @@ static bool __intel_engine_add_wait(struct intel_engine_cs 
*engine,
 
if (first) {
GEM_BUG_ON(rb_first(>waiters) != >node);
-   b->timeout = wait_timeout();
b->first_wait = wait;
rcu_assign_pointer(b->irq_seqno_bh, wait->tsk);
/* After assigning ourselves as the new bottom-half, we must
@@ -396,7 +395,6 @@ void intel_engine_remove_wait(struct intel_engine_cs 
*engine,
 * the interrupt, or if we have to handle an
 * exception rather than a seqno completion.
 */
-   b->timeout = wait_timeout();
b->first_wait = to_wait(next);
rcu_assign_pointer(b->irq_seqno_bh, b->first_wait->tsk);
if (b->first_wait->seqno != wait->seqno)
@@ -627,7 +625,6 @@ void intel_engine_reset_breadcrumbs(struct intel_engine_cs 
*engine)
 

[Intel-gfx] [CI 1/6] drm/i915: Remove temporary allocation of dma addresses when rotating

[Chris Wilson]

The object already stores (computed on the fly) the index to dma address
so use it instead of reallocating a large temporary array every time we
bind a rotated framebuffer.

Signed-off-by: Chris Wilson 
Cc: Matthew Auld 
Cc: Joonas Lahtinen 
Cc: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 77 -
 1 file changed, 25 insertions(+), 52 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 47a38272f54c..848dbb926fd1 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3043,27 +3043,32 @@ void i915_gem_restore_gtt_mappings(struct 
drm_i915_private *dev_priv)
 }
 
 static struct scatterlist *
-rotate_pages(const dma_addr_t *in, unsigned int offset,
-unsigned int width, unsigned int height,
-unsigned int stride,
+rotate_pages(struct drm_i915_gem_object *obj,
+const struct intel_rotation_plane_info *p,
 struct sg_table *st, struct scatterlist *sg)
 {
unsigned int column, row;
-   unsigned int src_idx;
 
-   for (column = 0; column < width; column++) {
-   src_idx = stride * (height - 1) + column;
-   for (row = 0; row < height; row++) {
-   st->nents++;
+   for (column = 0; column < p->width; column++) {
+   unsigned long src_idx =
+   p->stride * (p->height - 1) + column + p->offset;
+   for (row = 0; row < p->height; row++) {
+   struct scatterlist *src;
+   unsigned int n;
+
+   src = i915_gem_object_get_sg(obj, src_idx, );
+   src_idx -= p->stride;
+
/* We don't need the pages, but need to initialize
 * the entries so the sg list can be happily traversed.
 * The only thing we need are DMA addresses.
 */
sg_set_page(sg, NULL, PAGE_SIZE, 0);
-   sg_dma_address(sg) = in[offset + src_idx];
+   sg_dma_address(sg) = sg_dma_address(src) + n*PAGE_SIZE;
sg_dma_len(sg) = PAGE_SIZE;
-   sg = sg_next(sg);
-   src_idx -= stride;
+   sg = __sg_next(sg);
+
+   st->nents++;
}
}
 
@@ -3074,62 +3079,30 @@ static noinline struct sg_table *
 intel_rotate_pages(struct intel_rotation_info *rot_info,
   struct drm_i915_gem_object *obj)
 {
-   const unsigned long n_pages = obj->base.size / PAGE_SIZE;
-   unsigned int size = intel_rotation_info_size(rot_info);
-   struct sgt_iter sgt_iter;
-   dma_addr_t dma_addr;
-   unsigned long i;
-   dma_addr_t *page_addr_list;
-   struct sg_table *st;
+   const unsigned int size = intel_rotation_info_size(rot_info);
struct scatterlist *sg;
+   struct sg_table *st;
+   unsigned long i;
int ret = -ENOMEM;
 
-   /* Allocate a temporary list of source pages for random access. */
-   page_addr_list = drm_malloc_gfp(n_pages,
-   sizeof(dma_addr_t),
-   GFP_TEMPORARY);
-   if (!page_addr_list)
-   return ERR_PTR(ret);
-
-   /* Allocate target SG list. */
st = kmalloc(sizeof(*st), GFP_KERNEL);
if (!st)
-   goto err_st_alloc;
+   goto err;
 
ret = sg_alloc_table(st, size, GFP_KERNEL);
if (ret)
-   goto err_sg_alloc;
-
-   /* Populate source page list from the object. */
-   i = 0;
-   for_each_sgt_dma(dma_addr, sgt_iter, obj->mm.pages)
-   page_addr_list[i++] = dma_addr;
+   goto err;
 
-   GEM_BUG_ON(i != n_pages);
st->nents = 0;
sg = st->sgl;
-
-   for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) {
-   sg = rotate_pages(page_addr_list, rot_info->plane[i].offset,
- rot_info->plane[i].width, 
rot_info->plane[i].height,
- rot_info->plane[i].stride, st, sg);
-   }
-
-   DRM_DEBUG_KMS("Created rotated page mapping for object size %zu (%ux%u 
tiles, %u pages)\n",
- obj->base.size, rot_info->plane[0].width, 
rot_info->plane[0].height, size);
-
-   drm_free_large(page_addr_list);
+   for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
+   sg = rotate_pages(obj, _info->plane[i], st, sg);
+   GEM_BUG_ON(st->nents != size);
 
return st;
 
-err_sg_alloc:
+err:
kfree(st);
-err_st_alloc:
-   drm_free_large(page_addr_list);
-
-   DRM_DEBUG_KMS("Failed to create rotated mapping for object size %zu! 

[Intel-gfx] [CI 3/6] drm/i915: Break i915_spin_request() if we see an interrupt

[Chris Wilson]

If an interrupt has been posted, and we were spinning on the active
seqno waiting for it to advance but it did not, then we can expect that
it will not see its advance in the immediate future and should call into
the irq-seqno barrier. We can stop spinning at this point, and leave the
difficulty of handling the coherency to the caller.

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
Cc: Mika Kuoppala 
Reviewed-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_gem_request.c | 12 +++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_request.c 
b/drivers/gpu/drm/i915/i915_gem_request.c
index 2f6cfa47dc61..a5fac40d2a4f 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -963,7 +963,8 @@ static bool busywait_stop(unsigned long timeout, unsigned 
int cpu)
 bool __i915_spin_request(const struct drm_i915_gem_request *req,
 int state, unsigned long timeout_us)
 {
-   unsigned int cpu;
+   struct intel_engine_cs *engine = req->engine;
+   unsigned int irq, cpu;
 
/* When waiting for high frequency requests, e.g. during synchronous
 * rendering split between the CPU and GPU, the finite amount of time
@@ -975,11 +976,20 @@ bool __i915_spin_request(const struct 
drm_i915_gem_request *req,
 * takes to sleep on a request, on the order of a microsecond.
 */
 
+   irq = atomic_read(>irq_count);
timeout_us += local_clock_us();
do {
if (__i915_gem_request_completed(req))
return true;
 
+   /* Seqno are meant to be ordered *before* the interrupt. If
+* we see an interrupt without a corresponding seqno advance,
+* assume we won't see one in the near future but require
+* the engine->seqno_barrier() to fixup coherency.
+*/
+   if (atomic_read(>irq_count) != irq)
+   break;
+
if (signal_pending_state(state, current))
break;
 
-- 
2.11.0

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[Intel-gfx] [CI 6/6] drm/i915: Remove completed fences after a wait

[Chris Wilson]

If we wait upon the full (i.e. all shared fences, or upon an exclusive fence)
reservation object successfully, we know that all fences beneath it have
been signaled, so long as no new fences were added whilst we slept. If the
reservation_object remains the same, as detected by its seqcount, we can
then reap all the fences upon completion.

Signed-off-by: Chris Wilson 
Cc: Joonas Lahtinen 
Reviewed-by: Matthew Auld 
---
 drivers/gpu/drm/i915/i915_gem.c | 15 ++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 5f7b8c88eb7e..d93032875f28 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -427,7 +427,9 @@ i915_gem_object_wait_reservation(struct reservation_object 
*resv,
 long timeout,
 struct intel_rps_client *rps)
 {
+   unsigned int seq = __read_seqcount_begin(>seq);
struct dma_fence *excl;
+   bool prune_fences = false;
 
if (flags & I915_WAIT_ALL) {
struct dma_fence **shared;
@@ -452,15 +454,26 @@ i915_gem_object_wait_reservation(struct 
reservation_object *resv,
for (; i < count; i++)
dma_fence_put(shared[i]);
kfree(shared);
+
+   prune_fences = count && timeout >= 0;
} else {
excl = reservation_object_get_excl_rcu(resv);
}
 
-   if (excl && timeout >= 0)
+   if (excl && timeout >= 0) {
timeout = i915_gem_object_wait_fence(excl, flags, timeout, rps);
+   prune_fences = timeout >= 0;
+   }
 
dma_fence_put(excl);
 
+   if (prune_fences && !__read_seqcount_retry(>seq, seq)) {
+   reservation_object_lock(resv, NULL);
+   if (!__read_seqcount_retry(>seq, seq))
+   reservation_object_add_excl_fence(resv, NULL);
+   reservation_object_unlock(resv);
+   }
+
return timeout;
 }
 
-- 
2.11.0

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[Intel-gfx] [CI 5/6] drm/i915: Only start with the fake-irq timer if interrupts are dead

[Chris Wilson]

As a backup to waiting on a user-interrupt from the GPU, we use a heavy
and frequent timer to wake up the waiting process should we detect an
inconsistency whilst waiting. After seeing a "missed interrupt", the
next time we wait, we restart the heavy timer. This patch is more
reluctant to restart the timer and will only do so if we have not see any
interrupts since when we started the fake irq timer. If we are seeing
interrupts, then the waiters are being woken normally and we had an
incoherency that caused to miss last time - that is unlikely to reoccur
and so taking the risk of stalling again seems pragmatic.

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
Cc: Mika Kuoppala 
Reviewed-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/intel_breadcrumbs.c | 20 ++--
 1 file changed, 18 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c 
b/drivers/gpu/drm/i915/intel_breadcrumbs.c
index 83a8b67d6427..1719f9da13b8 100644
--- a/drivers/gpu/drm/i915/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c
@@ -107,6 +107,23 @@ static void irq_disable(struct intel_engine_cs *engine)
spin_unlock(>i915->irq_lock);
 }
 
+static bool use_fake_irq(const struct intel_breadcrumbs *b)
+{
+   const struct intel_engine_cs *engine =
+   container_of(b, struct intel_engine_cs, breadcrumbs);
+
+   if (!test_bit(engine->id, >i915->gpu_error.missed_irq_rings))
+   return false;
+
+   /* Only start with the heavy weight fake irq timer if we have not
+* seen any interrupts since enabling it the first time. If the
+* interrupts are still arriving, it means we made a mistake in our
+* engine->seqno_barrier(), a timing error that should be transient
+* and unlikely to reoccur.
+*/
+   return atomic_read(>irq_count) == b->hangcheck_interrupts;
+}
+
 static void __intel_breadcrumbs_enable_irq(struct intel_breadcrumbs *b)
 {
struct intel_engine_cs *engine =
@@ -145,8 +162,7 @@ static void __intel_breadcrumbs_enable_irq(struct 
intel_breadcrumbs *b)
b->irq_enabled = true;
}
 
-   if (!b->irq_enabled ||
-   test_bit(engine->id, >gpu_error.missed_irq_rings)) {
+   if (!b->irq_enabled || use_fake_irq(b)) {
mod_timer(>fake_irq, jiffies + 1);
i915_queue_hangcheck(i915);
} else {
-- 
2.11.0

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[Intel-gfx] [CI 4/6] drm/i915: Defer declaration of missed-interrupt until the waiter is asleep

[Chris Wilson]

If the waiter was currently running, assume it hasn't had a chance
to process the pending interupt (e.g, low priority task on a loaded
system) and wait until it sleeps before declaring a missed interrupt.

References: https://bugs.freedesktop.org/show_bug.cgi?id=99816
Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
Cc: Mika Kuoppala 
Reviewed-by: Tvrtko Ursulin 
Reviewed-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/intel_breadcrumbs.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c 
b/drivers/gpu/drm/i915/intel_breadcrumbs.c
index d229a555db25..83a8b67d6427 100644
--- a/drivers/gpu/drm/i915/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c
@@ -45,6 +45,15 @@ static void intel_breadcrumbs_hangcheck(unsigned long data)
return;
}
 
+   /* If the waiter was currently running, assume it hasn't had a chance
+* to process the pending interupt (e.g, low priority task on a loaded
+* system) and wait until it sleeps before declaring a missed interrupt.
+*/
+   if (!intel_engine_wakeup(engine)) {
+   mod_timer(>hangcheck, wait_timeout());
+   return;
+   }
+
DRM_DEBUG("Hangcheck timer elapsed... %s idle\n", engine->name);
set_bit(engine->id, >i915->gpu_error.missed_irq_rings);
mod_timer(>breadcrumbs.fake_irq, jiffies + 1);
-- 
2.11.0

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[Intel-gfx] [PATCH] drm/i915: Remove temporary allocation of dma addresses when rotating

[Chris Wilson]

The object already stores (computed on the fly) the index to dma address
so use it instead of reallocating a large temporary array every time we
bind a rotated framebuffer.

Signed-off-by: Chris Wilson 
Cc: Matthew Auld 
Cc: Joonas Lahtinen 
Cc: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 77 -
 1 file changed, 25 insertions(+), 52 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 47a38272f54c..848dbb926fd1 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3043,27 +3043,32 @@ void i915_gem_restore_gtt_mappings(struct 
drm_i915_private *dev_priv)
 }
 
 static struct scatterlist *
-rotate_pages(const dma_addr_t *in, unsigned int offset,
-unsigned int width, unsigned int height,
-unsigned int stride,
+rotate_pages(struct drm_i915_gem_object *obj,
+const struct intel_rotation_plane_info *p,
 struct sg_table *st, struct scatterlist *sg)
 {
unsigned int column, row;
-   unsigned int src_idx;
 
-   for (column = 0; column < width; column++) {
-   src_idx = stride * (height - 1) + column;
-   for (row = 0; row < height; row++) {
-   st->nents++;
+   for (column = 0; column < p->width; column++) {
+   unsigned long src_idx =
+   p->stride * (p->height - 1) + column + p->offset;
+   for (row = 0; row < p->height; row++) {
+   struct scatterlist *src;
+   unsigned int n;
+
+   src = i915_gem_object_get_sg(obj, src_idx, );
+   src_idx -= p->stride;
+
/* We don't need the pages, but need to initialize
 * the entries so the sg list can be happily traversed.
 * The only thing we need are DMA addresses.
 */
sg_set_page(sg, NULL, PAGE_SIZE, 0);
-   sg_dma_address(sg) = in[offset + src_idx];
+   sg_dma_address(sg) = sg_dma_address(src) + n*PAGE_SIZE;
sg_dma_len(sg) = PAGE_SIZE;
-   sg = sg_next(sg);
-   src_idx -= stride;
+   sg = __sg_next(sg);
+
+   st->nents++;
}
}
 
@@ -3074,62 +3079,30 @@ static noinline struct sg_table *
 intel_rotate_pages(struct intel_rotation_info *rot_info,
   struct drm_i915_gem_object *obj)
 {
-   const unsigned long n_pages = obj->base.size / PAGE_SIZE;
-   unsigned int size = intel_rotation_info_size(rot_info);
-   struct sgt_iter sgt_iter;
-   dma_addr_t dma_addr;
-   unsigned long i;
-   dma_addr_t *page_addr_list;
-   struct sg_table *st;
+   const unsigned int size = intel_rotation_info_size(rot_info);
struct scatterlist *sg;
+   struct sg_table *st;
+   unsigned long i;
int ret = -ENOMEM;
 
-   /* Allocate a temporary list of source pages for random access. */
-   page_addr_list = drm_malloc_gfp(n_pages,
-   sizeof(dma_addr_t),
-   GFP_TEMPORARY);
-   if (!page_addr_list)
-   return ERR_PTR(ret);
-
-   /* Allocate target SG list. */
st = kmalloc(sizeof(*st), GFP_KERNEL);
if (!st)
-   goto err_st_alloc;
+   goto err;
 
ret = sg_alloc_table(st, size, GFP_KERNEL);
if (ret)
-   goto err_sg_alloc;
-
-   /* Populate source page list from the object. */
-   i = 0;
-   for_each_sgt_dma(dma_addr, sgt_iter, obj->mm.pages)
-   page_addr_list[i++] = dma_addr;
+   goto err;
 
-   GEM_BUG_ON(i != n_pages);
st->nents = 0;
sg = st->sgl;
-
-   for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) {
-   sg = rotate_pages(page_addr_list, rot_info->plane[i].offset,
- rot_info->plane[i].width, 
rot_info->plane[i].height,
- rot_info->plane[i].stride, st, sg);
-   }
-
-   DRM_DEBUG_KMS("Created rotated page mapping for object size %zu (%ux%u 
tiles, %u pages)\n",
- obj->base.size, rot_info->plane[0].width, 
rot_info->plane[0].height, size);
-
-   drm_free_large(page_addr_list);
+   for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
+   sg = rotate_pages(obj, _info->plane[i], st, sg);
+   GEM_BUG_ON(st->nents != size);
 
return st;
 
-err_sg_alloc:
+err:
kfree(st);
-err_st_alloc:
-   drm_free_large(page_addr_list);
-
-   DRM_DEBUG_KMS("Failed to create rotated mapping for object size %zu! 

[Intel-gfx] [PATCH] drm/i915: Remove temporary allocation of dma addresses when rotating

[Chris Wilson]

The object already stores (computed on the fly) the index to dma address
so use it instead of reallocating a large temporary array every time we
bind a rotated framebuffer.

Signed-off-by: Chris Wilson 
Cc: Matthew Auld 
Cc: Joonas Lahtinen 
Cc: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 77 -
 1 file changed, 25 insertions(+), 52 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 47a38272f54c..848dbb926fd1 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3043,27 +3043,32 @@ void i915_gem_restore_gtt_mappings(struct 
drm_i915_private *dev_priv)
 }
 
 static struct scatterlist *
-rotate_pages(const dma_addr_t *in, unsigned int offset,
-unsigned int width, unsigned int height,
-unsigned int stride,
+rotate_pages(struct drm_i915_gem_object *obj,
+const struct intel_rotation_plane_info *p,
 struct sg_table *st, struct scatterlist *sg)
 {
unsigned int column, row;
-   unsigned int src_idx;
 
-   for (column = 0; column < width; column++) {
-   src_idx = stride * (height - 1) + column;
-   for (row = 0; row < height; row++) {
-   st->nents++;
+   for (column = 0; column < p->width; column++) {
+   unsigned long src_idx =
+   p->stride * (p->height - 1) + column + p->offset;
+   for (row = 0; row < p->height; row++) {
+   struct scatterlist *src;
+   unsigned int n;
+
+   src = i915_gem_object_get_sg(obj, src_idx, );
+   src_idx -= p->stride;
+
/* We don't need the pages, but need to initialize
 * the entries so the sg list can be happily traversed.
 * The only thing we need are DMA addresses.
 */
sg_set_page(sg, NULL, PAGE_SIZE, 0);
-   sg_dma_address(sg) = in[offset + src_idx];
+   sg_dma_address(sg) = sg_dma_address(src) + n*PAGE_SIZE;
sg_dma_len(sg) = PAGE_SIZE;
-   sg = sg_next(sg);
-   src_idx -= stride;
+   sg = __sg_next(sg);
+
+   st->nents++;
}
}
 
@@ -3074,62 +3079,30 @@ static noinline struct sg_table *
 intel_rotate_pages(struct intel_rotation_info *rot_info,
   struct drm_i915_gem_object *obj)
 {
-   const unsigned long n_pages = obj->base.size / PAGE_SIZE;
-   unsigned int size = intel_rotation_info_size(rot_info);
-   struct sgt_iter sgt_iter;
-   dma_addr_t dma_addr;
-   unsigned long i;
-   dma_addr_t *page_addr_list;
-   struct sg_table *st;
+   const unsigned int size = intel_rotation_info_size(rot_info);
struct scatterlist *sg;
+   struct sg_table *st;
+   unsigned long i;
int ret = -ENOMEM;
 
-   /* Allocate a temporary list of source pages for random access. */
-   page_addr_list = drm_malloc_gfp(n_pages,
-   sizeof(dma_addr_t),
-   GFP_TEMPORARY);
-   if (!page_addr_list)
-   return ERR_PTR(ret);
-
-   /* Allocate target SG list. */
st = kmalloc(sizeof(*st), GFP_KERNEL);
if (!st)
-   goto err_st_alloc;
+   goto err;
 
ret = sg_alloc_table(st, size, GFP_KERNEL);
if (ret)
-   goto err_sg_alloc;
-
-   /* Populate source page list from the object. */
-   i = 0;
-   for_each_sgt_dma(dma_addr, sgt_iter, obj->mm.pages)
-   page_addr_list[i++] = dma_addr;
+   goto err;
 
-   GEM_BUG_ON(i != n_pages);
st->nents = 0;
sg = st->sgl;
-
-   for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) {
-   sg = rotate_pages(page_addr_list, rot_info->plane[i].offset,
- rot_info->plane[i].width, 
rot_info->plane[i].height,
- rot_info->plane[i].stride, st, sg);
-   }
-
-   DRM_DEBUG_KMS("Created rotated page mapping for object size %zu (%ux%u 
tiles, %u pages)\n",
- obj->base.size, rot_info->plane[0].width, 
rot_info->plane[0].height, size);
-
-   drm_free_large(page_addr_list);
+   for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
+   sg = rotate_pages(obj, _info->plane[i], st, sg);
+   GEM_BUG_ON(st->nents != size);
 
return st;
 
-err_sg_alloc:
+err:
kfree(st);
-err_st_alloc:
-   drm_free_large(page_addr_list);
-
-   DRM_DEBUG_KMS("Failed to create rotated mapping for object size %zu! 

Re: [Intel-gfx] [PATCH] drm/i915: Only start with the fake-irq timer if interrupts are dead

[Tvrtko Ursulin]

On 17/02/2017 11:55, Chris Wilson wrote:

As a backup to waiting on a user-interrupt from the GPU, we use a heavy
and frequent timer to wake up the waiting process should we detect an
inconsistency whilst waiting. After seeing a "missed interrupt", the
next time we wait, we restart the heavy timer. This patch is more
reluctant to restart the timer and will only do so if we have not see any
interrupts since when we started the fake irq timer. If we are seeing
interrupts, then the waiters are being woken normally and we had an
incoherency that caused to miss last time - that is unlikely to reoccur
and so taking the risk of stalling again seems pragmatic.

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/intel_breadcrumbs.c | 20 ++--
 1 file changed, 18 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c 
b/drivers/gpu/drm/i915/intel_breadcrumbs.c
index 83a8b67d6427..1719f9da13b8 100644
--- a/drivers/gpu/drm/i915/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c
@@ -107,6 +107,23 @@ static void irq_disable(struct intel_engine_cs *engine)
spin_unlock(>i915->irq_lock);
 }

+static bool use_fake_irq(const struct intel_breadcrumbs *b)
+{
+   const struct intel_engine_cs *engine =
+   container_of(b, struct intel_engine_cs, breadcrumbs);
+
+   if (!test_bit(engine->id, >i915->gpu_error.missed_irq_rings))
+   return false;
+
+   /* Only start with the heavy weight fake irq timer if we have not
+* seen any interrupts since enabling it the first time. If the
+* interrupts are still arriving, it means we made a mistake in our
+* engine->seqno_barrier(), a timing error that should be transient
+* and unlikely to reoccur.
+*/
+   return atomic_read(>irq_count) == b->hangcheck_interrupts;
+}
+
 static void __intel_breadcrumbs_enable_irq(struct intel_breadcrumbs *b)
 {
struct intel_engine_cs *engine =
@@ -145,8 +162,7 @@ static void __intel_breadcrumbs_enable_irq(struct 
intel_breadcrumbs *b)
b->irq_enabled = true;
}

-   if (!b->irq_enabled ||
-   test_bit(engine->id, >gpu_error.missed_irq_rings)) {
+   if (!b->irq_enabled || use_fake_irq(b)) {
mod_timer(>fake_irq, jiffies + 1);
i915_queue_hangcheck(i915);
} else {



Very soothing now that I have discovered the pre-existing behaviour. :)

Reviewed-by: Tvrtko Ursulin 

Regards,

Tvrtko
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[Intel-gfx] [PATCH] drm/i915: Fix legacy cursor vs. watermarks for ILK-BDW

[ville . syrjala]

From: Ville Syrjälä 

In order to make cursor updates actually safe wrt. watermark programming
we have to clear the legacy_cursor_update flag in the atomic state. That
will cause the regular atomic update path to do the necessary vblank
wait after the plane update if needed, otherwise the vblank wait would
be skipped and we'd feed the optimal watermarks to the hardware before
the plane update has actually happened.

To make the slow vs. fast path determination in
intel_legacy_cursor_update() a little simpler we can ignore the actual
visibility of the plane (which can only get computed once we've already
chosen out path) and instead we simply check whether the fb is being
set or cleared by the user. This means a fully clipped but logically
visible cursor will be considered visible as far as watermark
programming is concerned. We can do that for the cursor since it's a
fixed size plane and the clipped size doesn't play a role in the
watermark computation.

This should fix underruns that can occur when the cursor gets
enable/disabled or the size gets changed. Hopefully it's good enough
that only pure cursor movement and flips go through unthrottled.

Cc: Maarten Lankhorst 
Cc: Daniel Vetter 
Cc: Uwe Kleine-König 
Reported-by: Uwe Kleine-König 
Fixes: f79f26921ee1 ("drm/i915: Add a cursor hack to allow converting legacy 
page flip to atomic, v3.")
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_display.c | 29 ++---
 drivers/gpu/drm/i915/intel_pm.c  | 20 
 2 files changed, 30 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index b05d9c85384b..356ac04093e8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13031,6 +13031,17 @@ static int intel_atomic_commit(struct drm_device *dev,
struct drm_i915_private *dev_priv = to_i915(dev);
int ret = 0;
 
+   /*
+* The intel_legacy_cursor_update() fast path takes care
+* of avoiding the vblank waits for simple cursor
+* movement and flips. For cursor on/off and size changes,
+* we want to perform the vblank waits so that watermark
+* updates happen during the correct frames. Gen9+ have
+* double buffered watermarks and so shouldn't need this.
+*/
+   if (INTEL_GEN(dev_priv) < 9)
+   state->legacy_cursor_update = false;
+
ret = drm_atomic_helper_setup_commit(state, nonblock);
if (ret)
return ret;
@@ -13455,8 +13466,7 @@ intel_legacy_cursor_update(struct drm_plane *plane,
old_plane_state->src_h != src_h ||
old_plane_state->crtc_w != crtc_w ||
old_plane_state->crtc_h != crtc_h ||
-   !old_plane_state->visible ||
-   old_plane_state->fb->modifier != fb->modifier)
+   !old_plane_state->fb != !fb)
goto slow;
 
new_plane_state = intel_plane_duplicate_state(plane);
@@ -13479,10 +13489,6 @@ intel_legacy_cursor_update(struct drm_plane *plane,
if (ret)
goto out_free;
 
-   /* Visibility changed, must take slowpath. */
-   if (!new_plane_state->visible)
-   goto slow_free;
-
ret = mutex_lock_interruptible(_priv->drm.struct_mutex);
if (ret)
goto out_free;
@@ -13522,9 +13528,12 @@ intel_legacy_cursor_update(struct drm_plane *plane,
new_plane_state->fb = old_fb;
to_intel_plane_state(new_plane_state)->vma = old_vma;
 
-   intel_plane->update_plane(plane,
- to_intel_crtc_state(crtc->state),
- to_intel_plane_state(plane->state));
+   if (plane->state->visible)
+   intel_plane->update_plane(plane,
+ to_intel_crtc_state(crtc->state),
+ to_intel_plane_state(plane->state));
+   else
+   intel_plane->disable_plane(plane, crtc);
 
intel_cleanup_plane_fb(plane, new_plane_state);
 
@@ -13534,8 +13543,6 @@ intel_legacy_cursor_update(struct drm_plane *plane,
intel_plane_destroy_state(plane, new_plane_state);
return ret;
 
-slow_free:
-   intel_plane_destroy_state(plane, new_plane_state);
 slow:
return drm_atomic_helper_update_plane(plane, crtc, fb,
  crtc_x, crtc_y, crtc_w, crtc_h,
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index fe243c65de1a..4de8c40acc7e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1831,20 +1831,24 @@ static uint32_t ilk_compute_cur_wm(const struct 
intel_crtc_state *cstate,
   

Re: [Intel-gfx] [PATCH v2 05/14] drm/i915: Deconstruct execute fence

[Tvrtko Ursulin]

On 17/02/2017 14:41, Chris Wilson wrote:

On Fri, Feb 17, 2017 at 02:26:04PM +, Tvrtko Ursulin wrote:


On 14/02/2017 09:54, Chris Wilson wrote:

@@ -1036,12 +1011,11 @@ long i915_wait_request(struct drm_i915_gem_request *req,
if (flags & I915_WAIT_LOCKED)
add_wait_queue(errq, );

-   if (!i915_sw_fence_done(>execute)) {
-   DEFINE_WAIT(exec);
-
+   reset_wait_queue(>execute, );
+   if (!req->global_seqno) {
do {
-   prepare_to_wait(>execute.wait, , state);


Somehow I missed the moment when reset_wait_queue was introduced.
But why you can't just use prepare_to_wait here?


In a few patches, we starting looping around at this point, so reset is
required then (and choosing to do reset now just avoid a few lines
later on). Then in a few more patches, the reset_wait_queue is eliminated
entirely.


Fair enough;

Reviewed-by: Tvrtko Ursulin 

Regards,

Tvrtko

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[Intel-gfx] ✓ Fi.CI.BAT: success for GuC Scrub vol. 1 (rev3)

[Patchwork]

== Series Details ==

Series: GuC Scrub vol. 1 (rev3)
URL   : https://patchwork.freedesktop.org/series/16856/
State : success

== Summary ==

Series 16856v3 GuC Scrub vol. 1
https://patchwork.freedesktop.org/api/1.0/series/16856/revisions/3/mbox/

fi-bdw-5557u total:252  pass:241  dwarn:0   dfail:0   fail:0   skip:11 
fi-bsw-n3050 total:252  pass:213  dwarn:0   dfail:0   fail:0   skip:39 
fi-bxt-j4205 total:252  pass:233  dwarn:0   dfail:0   fail:0   skip:19 
fi-bxt-t5700 total:83   pass:70   dwarn:0   dfail:0   fail:0   skip:12 
fi-byt-j1900 total:252  pass:225  dwarn:0   dfail:0   fail:0   skip:27 
fi-byt-n2820 total:252  pass:221  dwarn:0   dfail:0   fail:0   skip:31 
fi-hsw-4770  total:252  pass:236  dwarn:0   dfail:0   fail:0   skip:16 
fi-hsw-4770r total:252  pass:236  dwarn:0   dfail:0   fail:0   skip:16 
fi-ilk-650   total:252  pass:202  dwarn:0   dfail:0   fail:0   skip:50 
fi-ivb-3520m total:252  pass:234  dwarn:0   dfail:0   fail:0   skip:18 
fi-ivb-3770  total:252  pass:234  dwarn:0   dfail:0   fail:0   skip:18 
fi-kbl-7500u total:252  pass:234  dwarn:0   dfail:0   fail:0   skip:18 
fi-skl-6260u total:252  pass:242  dwarn:0   dfail:0   fail:0   skip:10 
fi-skl-6700hqtotal:252  pass:235  dwarn:0   dfail:0   fail:0   skip:17 
fi-skl-6700k total:252  pass:230  dwarn:4   dfail:0   fail:0   skip:18 
fi-skl-6770hqtotal:252  pass:242  dwarn:0   dfail:0   fail:0   skip:10 
fi-snb-2520m total:252  pass:224  dwarn:0   dfail:0   fail:0   skip:28 
fi-snb-2600  total:252  pass:223  dwarn:0   dfail:0   fail:0   skip:29 

2b7ce9512d9770350bc2a59652cc7bf469bc544a drm-tip: 2017y-02m-17d-12h-20m-31s UTC 
integration manifest
24f57ae drm/i915/uc: Simplify firwmare path handling
592aa50c drm/i915/guc: Simplify intel_guc_init_hw()
f8dd825 drm/i915/guc: Extract param logic form guc_init
ed62ebf drm/i915/uc: Make intel_uc_fw_fetch() static
a29ea96 drm/i915/uc: Rename intel_?uc_init() to intel_?uc_fetch_fw()
4433687 drm/i915/huc: Add huc_to_i915
6d6c305 drm/i915/uc: Drop superfluous externs in intel_uc.h
2d116de drm/i915/uc: Rename intel_?uc_{setup, load}() to _init_hw()

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3879/
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Re: [Intel-gfx] [PATCH v2 06/14] drm/i915: Protect the request->global_seqno with the engine->timeline lock

[Tvrtko Ursulin]

On 14/02/2017 09:54, Chris Wilson wrote:

A request is assigned a global seqno only when it is on the hardware
execution queue. The global seqno can be used to maintain a list of
requests on the same engine in retirement order, for example for
constructing a priority queue for waiting. Prior to its execution, or
if it is subsequently removed in the event of preemption, its global
seqno is zero. As both insertion and removal from the execution queue
may operate in IRQ context, it is not guarded by the usual struct_mutex
BKL. Instead those relying on the global seqno must be prepared for its
value to change between reads. Only when the request is complete can
the global seqno be stable (due to the memory barriers on submitting
the commands to the hardware to write the breadcrumb, if the HWS shows
that it has passed the global seqno and the global seqno is unchanged
after the read, it is indeed complete).

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_drv.h  | 16 ++--
 drivers/gpu/drm/i915/i915_gem.c  | 16 +---
 drivers/gpu/drm/i915/i915_gem_request.c  | 46 ++
 drivers/gpu/drm/i915/i915_gem_request.h  | 66 +---
 drivers/gpu/drm/i915/intel_breadcrumbs.c | 11 --
 5 files changed, 114 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 251b2d66407e..cb66fc33cab6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -4005,14 +4005,24 @@ wait_remaining_ms_from_jiffies(unsigned long 
timestamp_jiffies, int to_wait_ms)
 }

 static inline bool
-__i915_request_irq_complete(struct drm_i915_gem_request *req)
+__i915_request_irq_complete(const struct drm_i915_gem_request *req)
 {
struct intel_engine_cs *engine = req->engine;
+   u32 seqno = i915_gem_request_global_seqno(req);
+
+   /* The request was dequeued before we were awoken. We check after
+* inspecting the hw to confirm that this was the same request
+* that generated the HWS update. The memory barriers within
+* the request execution are sufficient to ensure that a check
+* after reading the value from hw matches this request.
+*/
+   if (!seqno)
+   return false;

/* Before we do the heavier coherent read of the seqno,
 * check the value (hopefully) in the CPU cacheline.
 */
-   if (__i915_gem_request_completed(req))
+   if (__i915_gem_request_completed(req, seqno))
return true;

/* Ensure our read of the seqno is coherent so that we
@@ -4063,7 +4073,7 @@ __i915_request_irq_complete(struct drm_i915_gem_request 
*req)
wake_up_process(tsk);
rcu_read_unlock();

-   if (__i915_gem_request_completed(req))
+   if (__i915_gem_request_completed(req, seqno))
return true;
}

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 766820ae9985..a7eea5ff44ca 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -400,7 +400,7 @@ i915_gem_object_wait_fence(struct dma_fence *fence,
if (flags & I915_WAIT_LOCKED && i915_gem_request_completed(rq))
i915_gem_request_retire_upto(rq);

-   if (rps && rq->global_seqno == intel_engine_last_submit(rq->engine)) {
+   if (rps && i915_gem_request_global_seqno(rq) == 
intel_engine_last_submit(rq->engine)) {
/* The GPU is now idle and this client has stalled.
 * Since no other client has submitted a request in the
 * meantime, assume that this client is the only one
@@ -2612,7 +2612,8 @@ static void i915_gem_context_mark_innocent(struct 
i915_gem_context *ctx)
 struct drm_i915_gem_request *
 i915_gem_find_active_request(struct intel_engine_cs *engine)
 {
-   struct drm_i915_gem_request *request;
+   struct drm_i915_gem_request *request, *active = NULL;
+   unsigned long flags;

/* We are called by the error capture and reset at a random
 * point in time. In particular, note that neither is crucially
@@ -2622,17 +2623,22 @@ i915_gem_find_active_request(struct intel_engine_cs 
*engine)
 * extra delay for a recent interrupt is pointless. Hence, we do
 * not need an engine->irq_seqno_barrier() before the seqno reads.
 */
+   spin_lock_irqsave(>timeline->lock, flags);
list_for_each_entry(request, >timeline->requests, link) {
-   if (__i915_gem_request_completed(request))
+   if (__i915_gem_request_completed(request,
+request->global_seqno))
continue;

GEM_BUG_ON(request->engine != engine);
GEM_BUG_ON(test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,

Re: [Intel-gfx] [PATCH v2 05/14] drm/i915: Deconstruct execute fence

[Chris Wilson]

On Fri, Feb 17, 2017 at 02:26:04PM +, Tvrtko Ursulin wrote:
> 
> On 14/02/2017 09:54, Chris Wilson wrote:
> >@@ -1036,12 +1011,11 @@ long i915_wait_request(struct drm_i915_gem_request 
> >*req,
> > if (flags & I915_WAIT_LOCKED)
> > add_wait_queue(errq, );
> >
> >-if (!i915_sw_fence_done(>execute)) {
> >-DEFINE_WAIT(exec);
> >-
> >+reset_wait_queue(>execute, );
> >+if (!req->global_seqno) {
> > do {
> >-prepare_to_wait(>execute.wait, , state);
> 
> Somehow I missed the moment when reset_wait_queue was introduced.
> But why you can't just use prepare_to_wait here?

In a few patches, we starting looping around at this point, so reset is
required then (and choosing to do reset now just avoid a few lines
later on). Then in a few more patches, the reset_wait_queue is eliminated
entirely.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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Re: [Intel-gfx] [PATCH 8/8] drm/i915/uc: Simplify firwmare path handling

[Michal Wajdeczko]

On Fri, Feb 17, 2017 at 02:05:57PM +0100, Arkadiusz Hiler wrote:

Typo in subject s/firwmare/firmware


> Currently fw->path values can represent one of three possible states:
> 
>  1) NULL - device without the uC
>  2) '\0' - device with the uC but have no firmware
>  3) else - device with the uC and we have firmware
> 
> Second case is used only to WARN at a later stage.
> 
> We can WARN right away and merge cases 1 and 2.
> 
> Code can be even further simplified and common (HuC/GuC logic) happening
> right before the fetch can be offloaded to the common function.
> 
> v2: fewer temporary variables, more straightforward flow (M. Wajdeczko)
> 
> Cc: Anusha Srivatsa 
> Cc: Tvrtko Ursulin 
> Cc: Michal Winiarski 
> Cc: Michal Wajdeczko 
> Signed-off-by: Arkadiusz Hiler 
> ---
>  drivers/gpu/drm/i915/intel_guc_loader.c | 39 
> +++--
>  drivers/gpu/drm/i915/intel_huc.c| 20 +
>  drivers/gpu/drm/i915/intel_uc.c |  5 +++--
>  3 files changed, 22 insertions(+), 42 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c 
> b/drivers/gpu/drm/i915/intel_guc_loader.c
> index 549a254..aade185 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -433,12 +433,8 @@ int intel_guc_init_hw(struct drm_i915_private *dev_priv)
>   intel_uc_fw_status_repr(guc_fw->load_status));
>  
>   if (fw_path == NULL) {
> - /* Device is known to have no uCode (e.g. no GuC) */
> + /* We do not have uCode for the device */
>   return -ENXIO;
> - } else if (*fw_path == '\0') {
> - /* Device has a GuC but we don't know what f/w to load? */
> - WARN(1, "No GuC firmware known for this platform!\n");
> - return -ENODEV;
>   }
>  
>   /* Fetch failed, or already fetched but failed to load? */
> @@ -474,7 +470,6 @@ int intel_guc_init_hw(struct drm_i915_private *dev_priv)
>   return 0;
>  }
>  
> -
>  /**
>   * intel_guc_fetch_fw() - determine and fetch firmware
>   * @guc: intel_guc struct
> @@ -487,39 +482,31 @@ int intel_guc_init_hw(struct drm_i915_private *dev_priv)
>  void intel_guc_fetch_fw(struct intel_guc *guc)
>  {
>   struct drm_i915_private *dev_priv = guc_to_i915(guc);
> - const char *fw_path;
>  
> - if (!HAS_GUC_UCODE(dev_priv)) {
> - fw_path = NULL;
> - } else if (IS_SKYLAKE(dev_priv)) {
> - fw_path = I915_SKL_GUC_UCODE;
> + guc->fw.path = NULL;
> + guc->fw.fetch_status = INTEL_UC_FIRMWARE_NONE;
> + guc->fw.load_status = INTEL_UC_FIRMWARE_NONE;
> + guc->fw.fw = INTEL_UC_FW_TYPE_GUC;

Maybe for above code we can add new function:

void intel_uc_fw_init_early(struct intel_uc_fw *fw,
enum intel_uc_fw_type type);

and use it for both guc and huc:

intel_uc_fw_init_early(>fw, INTEL_UC_FW_TYPE_GUC);
intel_uc_fw_init_early(>fw, INTEL_UC_FW_TYPE_HUC);

> +
> + if (IS_SKYLAKE(dev_priv)) {
> + guc->fw.path = I915_SKL_GUC_UCODE;
>   guc->fw.major_ver_wanted = SKL_FW_MAJOR;
>   guc->fw.minor_ver_wanted = SKL_FW_MINOR;
>   } else if (IS_BROXTON(dev_priv)) {
> - fw_path = I915_BXT_GUC_UCODE;
> + guc->fw.path = I915_BXT_GUC_UCODE;
>   guc->fw.major_ver_wanted = BXT_FW_MAJOR;
>   guc->fw.minor_ver_wanted = BXT_FW_MINOR;
>   } else if (IS_KABYLAKE(dev_priv)) {
> - fw_path = I915_KBL_GUC_UCODE;
> + guc->fw.path = I915_KBL_GUC_UCODE;
>   guc->fw.major_ver_wanted = KBL_FW_MAJOR;
>   guc->fw.minor_ver_wanted = KBL_FW_MINOR;
>   } else {
> - fw_path = "";   /* unknown device */
> + WARN(1, "No GuC firmware known for platform with GuC!\n");

Maybe simpler DRM_ERROR will be sufficient? We don't need callstack.


> + i915.enable_guc_loading = 0;

What about making this firmware path guess work part of the early init or
sanitize options function? Note that actual fetch is already done by in 
different function, so mostly we just need to pick nice name for the
new function. Maybe

int intel_guc_init_fw() ?

Note that changing i915.enable_guc param here has implication on other
actions (like Huc loading) and thus forcing redundant checks elsewhere

> + return;
>   }
>  
> - guc->fw.path = fw_path;
> - guc->fw.fetch_status = INTEL_UC_FIRMWARE_NONE;
> - guc->fw.load_status = INTEL_UC_FIRMWARE_NONE;
> -
> - if (fw_path == NULL)
> - return;
> - if (*fw_path == '\0')
> - return;
> -
> - guc->fw.fetch_status = INTEL_UC_FIRMWARE_PENDING;
> - DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path);
>   

Re: [Intel-gfx] [PATCH v2 05/14] drm/i915: Deconstruct execute fence

[Tvrtko Ursulin]

On 14/02/2017 09:54, Chris Wilson wrote:

On reflection, we are only using the execute fence as a waitqueue on the
global_seqno and not using it for dependency tracking between fences
(unlike the submit and dma fences). By only treating it as a waitqueue,
we can then treat it similar to the other waitqueues durin submit,


during


making the code simpler.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_gem_request.c | 47 +++--
 drivers/gpu/drm/i915/i915_gem_request.h | 10 +--
 2 files changed, 11 insertions(+), 46 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_request.c 
b/drivers/gpu/drm/i915/i915_gem_request.c
index 001fc9fedf49..bb59acaa8a34 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -69,7 +69,6 @@ static void i915_fence_release(struct dma_fence *fence)
 * caught trying to reuse dead objects.
 */
i915_sw_fence_fini(>submit);
-   i915_sw_fence_fini(>execute);

kmem_cache_free(req->i915->requests, req);
 }
@@ -211,7 +210,6 @@ static void i915_gem_request_retire(struct 
drm_i915_gem_request *request)

lockdep_assert_held(>i915->drm.struct_mutex);
GEM_BUG_ON(!i915_sw_fence_signaled(>submit));
-   GEM_BUG_ON(!i915_sw_fence_signaled(>execute));
GEM_BUG_ON(!i915_gem_request_completed(request));

GEM_BUG_ON(!request->i915->gt.active_requests);
@@ -422,7 +420,7 @@ void __i915_gem_request_submit(struct drm_i915_gem_request 
*request)
list_move_tail(>link, >requests);
spin_unlock(>timeline->lock);

-   i915_sw_fence_commit(>execute);
+   wake_up_all(>execute);
 }

 void i915_gem_request_submit(struct drm_i915_gem_request *request)
@@ -457,24 +455,6 @@ submit_notify(struct i915_sw_fence *fence, enum 
i915_sw_fence_notify state)
return NOTIFY_DONE;
 }

-static int __i915_sw_fence_call
-execute_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
-{
-   struct drm_i915_gem_request *request =
-   container_of(fence, typeof(*request), execute);
-
-   switch (state) {
-   case FENCE_COMPLETE:
-   break;
-
-   case FENCE_FREE:
-   i915_gem_request_put(request);
-   break;
-   }
-
-   return NOTIFY_DONE;
-}
-
 /**
  * i915_gem_request_alloc - allocate a request structure
  *
@@ -567,13 +547,7 @@ i915_gem_request_alloc(struct intel_engine_cs *engine,

/* We bump the ref for the fence chain */
i915_sw_fence_init(_gem_request_get(req)->submit, submit_notify);
-   i915_sw_fence_init(_gem_request_get(req)->execute, execute_notify);
-
-   /* Ensure that the execute fence completes after the submit fence -
-* as we complete the execute fence from within the submit fence
-* callback, its completion would otherwise be visible first.
-*/
-   i915_sw_fence_await_sw_fence(>execute, >submit, >execq);
+   init_waitqueue_head(>execute);

i915_priotree_init(>priotree);

@@ -1015,6 +989,7 @@ long i915_wait_request(struct drm_i915_gem_request *req,
TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
wait_queue_head_t *errq = >i915->gpu_error.wait_queue;
DEFINE_WAIT(reset);
+   DEFINE_WAIT(exec);
struct intel_wait wait;

might_sleep();
@@ -1036,12 +1011,11 @@ long i915_wait_request(struct drm_i915_gem_request *req,
if (flags & I915_WAIT_LOCKED)
add_wait_queue(errq, );

-   if (!i915_sw_fence_done(>execute)) {
-   DEFINE_WAIT(exec);
-
+   reset_wait_queue(>execute, );
+   if (!req->global_seqno) {
do {
-   prepare_to_wait(>execute.wait, , state);


Somehow I missed the moment when reset_wait_queue was introduced. But 
why you can't just use prepare_to_wait here?


Otherwise looks OK.

Regards,

Tvrtko


-   if (i915_sw_fence_done(>execute))
+   set_current_state(state);
+   if (req->global_seqno)
break;

if (flags & I915_WAIT_LOCKED &&
@@ -1064,15 +1038,14 @@ long i915_wait_request(struct drm_i915_gem_request *req,

timeout = io_schedule_timeout(timeout);
} while (1);
-   finish_wait(>execute.wait, );
+   finish_wait(>execute, );

if (timeout < 0)
goto complete;

-   GEM_BUG_ON(!i915_sw_fence_done(>execute));
+   GEM_BUG_ON(!req->global_seqno);
}
-   GEM_BUG_ON(!i915_sw_fence_done(>submit));
-   GEM_BUG_ON(!req->global_seqno);
+   GEM_BUG_ON(!i915_sw_fence_signaled(>submit));

/* Optimistic short spin before touching IRQs */
if (i915_spin_request(req, state, 5))
diff --git a/drivers/gpu/drm/i915/i915_gem_request.h 

[Intel-gfx] ✗ Fi.CI.BAT: failure for GLK MIPI DSI VIDEO MODE PATCHES (rev6)

[Patchwork]

== Series Details ==

Series: GLK MIPI DSI VIDEO MODE PATCHES (rev6)
URL   : https://patchwork.freedesktop.org/series/16542/
State : failure

== Summary ==

Series 16542v6 GLK MIPI DSI VIDEO MODE PATCHES
https://patchwork.freedesktop.org/api/1.0/series/16542/revisions/6/mbox/

Test gem_exec_basic:
Subgroup readonly-bsd2:
skip   -> INCOMPLETE (fi-byt-j1900)

fi-bdw-5557u total:252  pass:241  dwarn:0   dfail:0   fail:0   skip:11 
fi-bsw-n3050 total:252  pass:213  dwarn:0   dfail:0   fail:0   skip:39 
fi-bxt-j4205 total:252  pass:233  dwarn:0   dfail:0   fail:0   skip:19 
fi-bxt-t5700 total:83   pass:70   dwarn:0   dfail:0   fail:0   skip:12 
fi-byt-j1900 total:40   pass:32   dwarn:0   dfail:0   fail:0   skip:7  
fi-byt-n2820 total:252  pass:221  dwarn:0   dfail:0   fail:0   skip:31 
fi-hsw-4770  total:252  pass:236  dwarn:0   dfail:0   fail:0   skip:16 
fi-hsw-4770r total:252  pass:236  dwarn:0   dfail:0   fail:0   skip:16 
fi-ilk-650   total:252  pass:202  dwarn:0   dfail:0   fail:0   skip:50 
fi-ivb-3520m total:252  pass:234  dwarn:0   dfail:0   fail:0   skip:18 
fi-ivb-3770  total:252  pass:234  dwarn:0   dfail:0   fail:0   skip:18 
fi-kbl-7500u total:252  pass:234  dwarn:0   dfail:0   fail:0   skip:18 
fi-skl-6260u total:252  pass:242  dwarn:0   dfail:0   fail:0   skip:10 
fi-skl-6700hqtotal:252  pass:235  dwarn:0   dfail:0   fail:0   skip:17 
fi-skl-6700k total:252  pass:230  dwarn:4   dfail:0   fail:0   skip:18 
fi-skl-6770hqtotal:252  pass:242  dwarn:0   dfail:0   fail:0   skip:10 
fi-snb-2520m total:252  pass:224  dwarn:0   dfail:0   fail:0   skip:28 
fi-snb-2600  total:252  pass:223  dwarn:0   dfail:0   fail:0   skip:29 

2b7ce9512d9770350bc2a59652cc7bf469bc544a drm-tip: 2017y-02m-17d-12h-20m-31s UTC 
integration manifest
c05c8bb drm/i915/glk: Validate only DSI PORT A PLL divider
c1ced3d drm/i915/glk: Program txesc clock divider for GLK
f848bd1 drm/i915i/glk: Program MIPI_CLOCK_CTRL only for BXT
1efa662 drm/i915/glk: Add DSI PLL divider range for glk
4403589 drm/i915/glk: Add MIPIIO Enable/disable sequence
cf7ac11 drm/i915/glk: Program new MIPI DSI PHY registers for GLK
c109f5e drm/i915/glk: Program dphy param reg for GLK

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3878/
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[Intel-gfx] [PATCH v2] drm/i915: Only apply legacy PDE overflow detection to 3lvl machines

[Chris Wilson]

Prevent the overflow check from firing on machines with the full 4lvl
page tables, that are not restricted to GEN8_LEGACY_PDES.

v2: Also fix the off-by-one in the compare

Fixes: 894ccebee2b0 ("drm/i915: Micro-optimise gen8_ppgtt_insert_entries()")
Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 1f281554e4c9..b0ccc9b6c1c5 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -854,7 +854,8 @@ gen8_ppgtt_insert_pte_entries(struct i915_hw_ppgtt *ppgtt,
break;
}
 
-   GEM_BUG_ON(pdpe > GEN8_LEGACY_PDPES);
+   GEM_BUG_ON(!i915_vm_is_48bit(>base) &&
+  pdpe >= GEN8_LEGACY_PDPES);
pd = pdp->page_directory[pdpe];
pde = 0;
}
-- 
2.11.0

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Re: [Intel-gfx] [PATCH] drm/i915: Only apply legacy PDE overflow detection to 3lvl machines

[Chris Wilson]

On Fri, Feb 17, 2017 at 04:07:50PM +0200, Ville Syrjälä wrote:
> On Fri, Feb 17, 2017 at 01:59:09PM +, Chris Wilson wrote:
> > Prevent the overflow check from firing on machines with the full 4lvl
> > page tables, that are not restricted to GEN8_LEGACY_PDES.
> > 
> > Fixes: 894ccebee2b0 ("drm/i915: Micro-optimise gen8_ppgtt_insert_entries()")
> > Signed-off-by: Chris Wilson 
> > Cc: Mika Kuoppala 
> > ---
> >  drivers/gpu/drm/i915/i915_gem_gtt.c | 3 ++-
> >  1 file changed, 2 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
> > b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > index 1f281554e4c9..65cadc09b56e 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > @@ -854,7 +854,8 @@ gen8_ppgtt_insert_pte_entries(struct i915_hw_ppgtt 
> > *ppgtt,
> > break;
> > }
> >  
> > -   GEM_BUG_ON(pdpe > GEN8_LEGACY_PDPES);
> > +   GEM_BUG_ON(!i915_vm_is_48bit(>base) &&
> > +  pdpe > GEN8_LEGACY_PDPES);
> 
> Should that be >= ?

Yes, next you'll be fixing the name ;)
-Chris

-- 
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Re: [Intel-gfx] [PATCH] drm/i915: Only apply legacy PDE overflow detection to 3lvl machines

[Ville Syrjälä]

On Fri, Feb 17, 2017 at 01:59:09PM +, Chris Wilson wrote:
> Prevent the overflow check from firing on machines with the full 4lvl
> page tables, that are not restricted to GEN8_LEGACY_PDES.
> 
> Fixes: 894ccebee2b0 ("drm/i915: Micro-optimise gen8_ppgtt_insert_entries()")
> Signed-off-by: Chris Wilson 
> Cc: Mika Kuoppala 
> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 1f281554e4c9..65cadc09b56e 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -854,7 +854,8 @@ gen8_ppgtt_insert_pte_entries(struct i915_hw_ppgtt *ppgtt,
>   break;
>   }
>  
> - GEM_BUG_ON(pdpe > GEN8_LEGACY_PDPES);
> + GEM_BUG_ON(!i915_vm_is_48bit(>base) &&
> +pdpe > GEN8_LEGACY_PDPES);

Should that be >= ?

>   pd = pdp->page_directory[pdpe];
>   pde = 0;
>   }
> -- 
> 2.11.0
> 
> ___
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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[Intel-gfx] [PATCH 1/2] drm/i915: Skip clflushes for all non-page backed objects

[Chris Wilson]

Generalise the skip for physical and stolen objects by skipping anything
we do not have a valid address inside the sg.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_gem.c | 9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 6745dcbf3799..96098a7e0bc3 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3162,14 +3162,19 @@ void i915_gem_clflush_object(struct drm_i915_gem_object 
*obj,
 * to GPU, and we can ignore the cache flush because it'll happen
 * again at bind time.
 */
-   if (!obj->mm.pages)
+   if (!obj->mm.pages) {
+   GEM_BUG_ON(obj->base.write_domain != I915_GEM_DOMAIN_CPU);
return;
+   }
 
/*
 * Stolen memory is always coherent with the GPU as it is explicitly
 * marked as wc by the system, or the system is cache-coherent.
+* Similarly, we only access struct pages through the CPU cache, so
+* anything not backed by physical memory we consider to be always
+* coherent and not need clflushing.
 */
-   if (obj->stolen || obj->phys_handle)
+   if (!i915_gem_object_has_struct_page(obj))
return;
 
/* If the GPU is snooping the contents of the CPU cache,
-- 
2.11.0

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[Intel-gfx] [PATCH 2/2] drm/i915: Perform object clflushing asynchronously

[Chris Wilson]

Flushing the cachelines for an object is slow, can be as much as 100ms
for a large framebuffer. We currently do this under the struct_mutex BKL
on execution or on pageflip. But now with the ability to add fences to
obj->resv for both flips and execbuf (and we naturally wait on the fence
before CPU access), we can move the clflush operation to a workqueue and
signal a fence for completion, thereby doing the work asynchronously and
not blocking the driver or its clients.

Suggested-by: Akash Goel 
Signed-off-by: Chris Wilson 
Cc: Joonas Lahtinen 
Cc: Matthew Auld 
---
 drivers/gpu/drm/i915/Makefile  |   1 +
 drivers/gpu/drm/i915/i915_drv.h|   8 +-
 drivers/gpu/drm/i915/i915_gem.c|  66 ++
 drivers/gpu/drm/i915/i915_gem_clflush.c| 194 +
 drivers/gpu/drm/i915/i915_gem_execbuffer.c |   8 +-
 drivers/gpu/drm/i915/intel_display.c   |  49 
 6 files changed, 240 insertions(+), 86 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/i915_gem_clflush.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 1490d8622234..b1b580337c7a 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -29,6 +29,7 @@ i915-$(CONFIG_DEBUG_FS) += i915_debugfs.o intel_pipe_crc.o
 # GEM code
 i915-y += i915_cmd_parser.o \
  i915_gem_batch_pool.o \
+ i915_gem_clflush.o \
  i915_gem_context.o \
  i915_gem_dmabuf.o \
  i915_gem_evict.o \
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5005922f267b..97d3ecbcf8d4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3369,7 +3369,13 @@ int i915_gem_reset_prepare(struct drm_i915_private 
*dev_priv);
 void i915_gem_reset(struct drm_i915_private *dev_priv);
 void i915_gem_reset_finish(struct drm_i915_private *dev_priv);
 void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
-void i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
+
+void i915_gem_clflush_init(struct drm_i915_private *i915);
+void i915_gem_clflush_object(struct drm_i915_gem_object *obj,
+unsigned int flags);
+#define I915_CLFLUSH_FORCE BIT(0)
+#define I915_CLFLUSH_SYNC BIT(1)
+
 void i915_gem_init_mmio(struct drm_i915_private *i915);
 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
 int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 96098a7e0bc3..fc11f5205e00 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1621,23 +1621,17 @@ i915_gem_sw_finish_ioctl(struct drm_device *dev, void 
*data,
 {
struct drm_i915_gem_sw_finish *args = data;
struct drm_i915_gem_object *obj;
-   int err = 0;
 
obj = i915_gem_object_lookup(file, args->handle);
if (!obj)
return -ENOENT;
 
/* Pinned buffers may be scanout, so flush the cache */
-   if (READ_ONCE(obj->pin_display)) {
-   err = i915_mutex_lock_interruptible(dev);
-   if (!err) {
-   i915_gem_object_flush_cpu_write_domain(obj);
-   mutex_unlock(>struct_mutex);
-   }
-   }
+   if (READ_ONCE(obj->pin_display))
+   i915_gem_clflush_object(obj, I915_CLFLUSH_FORCE);
 
i915_gem_object_put(obj);
-   return err;
+   return 0;
 }
 
 /**
@@ -3155,46 +3149,6 @@ int i915_gem_wait_for_idle(struct drm_i915_private 
*i915, unsigned int flags)
return 0;
 }
 
-void i915_gem_clflush_object(struct drm_i915_gem_object *obj,
-bool force)
-{
-   /* If we don't have a page list set up, then we're not pinned
-* to GPU, and we can ignore the cache flush because it'll happen
-* again at bind time.
-*/
-   if (!obj->mm.pages) {
-   GEM_BUG_ON(obj->base.write_domain != I915_GEM_DOMAIN_CPU);
-   return;
-   }
-
-   /*
-* Stolen memory is always coherent with the GPU as it is explicitly
-* marked as wc by the system, or the system is cache-coherent.
-* Similarly, we only access struct pages through the CPU cache, so
-* anything not backed by physical memory we consider to be always
-* coherent and not need clflushing.
-*/
-   if (!i915_gem_object_has_struct_page(obj))
-   return;
-
-   /* If the GPU is snooping the contents of the CPU cache,
-* we do not need to manually clear the CPU cache lines.  However,
-* the caches are only snooped when the render cache is
-* flushed/invalidated.  As we always have to emit invalidations
-* and flushes when moving into and out of the RENDER domain, correct

Re: [Intel-gfx] [PATCH 2/3] drm: reset ELD if NULL edid is passed to drm_edid_to_eld

[Ville Syrjälä]

On Fri, Feb 17, 2017 at 04:02:02PM +0200, Jani Nikula wrote:
> On Thu, 16 Feb 2017, Ville Syrjälä  wrote:
> > On Thu, Feb 16, 2017 at 12:36:43PM +0200, Jani Nikula wrote:
> >> Make the function useful for resetting, not just setting, the ELD.
> >> 
> >> Signed-off-by: Jani Nikula 
> >> ---
> >>  drivers/gpu/drm/drm_edid.c | 3 +++
> >>  1 file changed, 3 insertions(+)
> >> 
> >> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> >> index 24e7b282f16c..362036360724 100644
> >> --- a/drivers/gpu/drm/drm_edid.c
> >> +++ b/drivers/gpu/drm/drm_edid.c
> >> @@ -3430,6 +3430,9 @@ void drm_edid_to_eld(struct drm_connector 
> >> *connector, struct edid *edid)
> >>  
> >>memset(eld, 0, sizeof(connector->eld));
> >>  
> >> +  if (!edid)
> >> +  return;
> >> +
> >>connector->latency_present[0] = false;
> >>connector->latency_present[1] = false;
> >>connector->video_latency[0] = 0;
> >
> > /me thinks the check should be after all these.
> 
> D'oh!
> 
> > Hmm. Actually the cea ext block check below should be safe wrt.
> > edid==NULL, so not sure we need this at all.
> 
> I'd just like to be explicit and avoid the debug message on missing CEA
> extensions if the whole EDID is missing.

Fair enough.

-- 
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Intel OTC
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Re: [Intel-gfx] [PATCH 4/4] drm/i915: reorganize the get_cdclk assignment

[Ville Syrjälä]

On Fri, Feb 17, 2017 at 11:22:07AM -0200, Paulo Zanoni wrote:
> Possible problems of the current if-ladder:
>   - It's a huge if ladder with almost a different check for each of
> our platforms.
>   - It mixes 3 different types of checks: IS_GENX, IS_PLATFORM and
> IS_GROUP_OF_PLATFORMS.
>   - As demonstrated by the recent IS_G4X commit, it's not easy to be
> sure if a platform down on the list isn't also checked earlier.
>   - As demonstrated by the WARN at the end, it's not easy to be sure
> if we're actually checking for every single platform.
> 
> Possible advantages of the new switch statement:
>   - It may be easier for the compiler to optimize stuff (I didn't
> check this), especially since the values are labels of an enum.
>   - The compiler will tell us in case we miss some platform.
>   - All platforms are explicitly there instead of maybe hidden in some
> check for a certain group of platforms such as IS_GEN9_BC.

Performance is a bit of a moot point since this is run exaclty once, but
the IS_GEN9_BC() stuff I tend to agree with. I don't really like those
macros at all since they don't actully mean anything as far as the
hardware features go.

> 
> Possible disadvantages with the new code:
>   - A few lines bigger.
> 
> Signed-off-by: Paulo Zanoni 
> ---
>  drivers/gpu/drm/i915/intel_cdclk.c | 103 
> ++---
>  1 file changed, 62 insertions(+), 41 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c 
> b/drivers/gpu/drm/i915/intel_cdclk.c
> index 7c92dc7..58a2f5c 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -1789,49 +1789,70 @@ void intel_init_cdclk_hooks(struct drm_i915_private 
> *dev_priv)
>   dev_priv->display.modeset_calc_cdclk = skl_modeset_calc_cdclk;
>   }
>  
> - if (IS_GEN9_BC(dev_priv))
> - dev_priv->display.get_cdclk = skl_get_cdclk;
> - else if (IS_GEN9_LP(dev_priv))
> - dev_priv->display.get_cdclk = bxt_get_cdclk;
> - else if (IS_BROADWELL(dev_priv))
> - dev_priv->display.get_cdclk = bdw_get_cdclk;
> - else if (IS_HASWELL(dev_priv))
> - dev_priv->display.get_cdclk = hsw_get_cdclk;
> - else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> - dev_priv->display.get_cdclk = vlv_get_cdclk;
> - else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
> + switch (INTEL_INFO(dev_priv)->platform) {
> + case INTEL_PLATFORM_UNINITIALIZED:

Just default: ?

> + MISSING_CASE(INTEL_INFO(dev_priv)->platform);
> + /* Fall through. */
> + case INTEL_I830:
> + dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk;
> + break;
> + case INTEL_I845G:
> + dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk;
> + break;
> + case INTEL_I85X:
> + dev_priv->display.get_cdclk = i85x_get_cdclk;
> + break;
> + case INTEL_I865G:
> + dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk;
> + break;
> + case INTEL_I915G:
> + dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk;
> + break;
> + case INTEL_I915GM:
> + dev_priv->display.get_cdclk = i915gm_get_cdclk;
> + break;
> + case INTEL_I945G:
> + case INTEL_I965G:
> + case INTEL_SANDYBRIDGE:
> + case INTEL_IVYBRIDGE:

I don't particularly like this disorder. I just managed to get the
list into some sort of sane order recently.

>   dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
> - else if (IS_GEN5(dev_priv))
> - dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk;
> - else if (IS_GM45(dev_priv))
> - dev_priv->display.get_cdclk = gm45_get_cdclk;
> - else if (IS_G45(dev_priv))
> + break;
> + case INTEL_I945GM:
> + dev_priv->display.get_cdclk = i945gm_get_cdclk;
> + break;
> + case INTEL_G33:
> + case INTEL_G45:

More disorder.

>   dev_priv->display.get_cdclk = g33_get_cdclk;
> - else if (IS_I965GM(dev_priv))
> - dev_priv->display.get_cdclk = i965gm_get_cdclk;
> - else if (IS_I965G(dev_priv))
> - dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
> - else if (IS_PINEVIEW(dev_priv))
> + break;
> + case INTEL_PINEVIEW:
>   dev_priv->display.get_cdclk = pnv_get_cdclk;
> - else if (IS_G33(dev_priv))
> - dev_priv->display.get_cdclk = g33_get_cdclk;
> - else if (IS_I945GM(dev_priv))
> - dev_priv->display.get_cdclk = i945gm_get_cdclk;
> - else if (IS_I945G(dev_priv))
> - dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
> - else if (IS_I915GM(dev_priv))
> - dev_priv->display.get_cdclk = i915gm_get_cdclk;
> - else if (IS_I915G(dev_priv))
> - 

Re: [Intel-gfx] [PATCH v2 04/14] drm/i915: Inline __i915_gem_request_wait_for_execute()

[Tvrtko Ursulin]

On 14/02/2017 09:54, Chris Wilson wrote:

It had only one callsite and existed to keep the code clearer. Now
having shared the wait-on-error between phases and with plans to change
the wait-for-execute in the next few patches, remove the out of line
wait loop and move it into the main body of i915_wait_request.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_gem_request.c | 78 -
 1 file changed, 29 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_request.c 
b/drivers/gpu/drm/i915/i915_gem_request.c
index dcc0a7ab95dc..001fc9fedf49 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -988,54 +988,6 @@ bool __i915_spin_request(const struct drm_i915_gem_request 
*req,
return false;
 }

-static long
-__i915_request_wait_for_execute(struct drm_i915_gem_request *request,
-   unsigned int flags,
-   long timeout)
-{
-   const int state = flags & I915_WAIT_INTERRUPTIBLE ?
-   TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
-   wait_queue_head_t *q = >i915->gpu_error.wait_queue;
-   DEFINE_WAIT(reset);
-   DEFINE_WAIT(wait);
-
-   if (flags & I915_WAIT_LOCKED)
-   add_wait_queue(q, );
-
-   do {
-   prepare_to_wait(>execute.wait, , state);
-
-   if (i915_sw_fence_done(>execute))
-   break;
-
-   if (flags & I915_WAIT_LOCKED &&
-   i915_reset_in_progress(>i915->gpu_error)) {
-   __set_current_state(TASK_RUNNING);
-   i915_reset(request->i915);
-   reset_wait_queue(q, );
-   continue;
-   }
-
-   if (signal_pending_state(state, current)) {
-   timeout = -ERESTARTSYS;
-   break;
-   }
-
-   if (!timeout) {
-   timeout = -ETIME;
-   break;
-   }
-
-   timeout = io_schedule_timeout(timeout);
-   } while (1);
-   finish_wait(>execute.wait, );
-
-   if (flags & I915_WAIT_LOCKED)
-   remove_wait_queue(q, );
-
-   return timeout;
-}
-
 /**
  * i915_wait_request - wait until execution of request has finished
  * @req: the request to wait upon
@@ -1085,7 +1037,35 @@ long i915_wait_request(struct drm_i915_gem_request *req,
add_wait_queue(errq, );

if (!i915_sw_fence_done(>execute)) {
-   timeout = __i915_request_wait_for_execute(req, flags, timeout);
+   DEFINE_WAIT(exec);
+
+   do {
+   prepare_to_wait(>execute.wait, , state);
+   if (i915_sw_fence_done(>execute))
+   break;
+
+   if (flags & I915_WAIT_LOCKED &&
+   i915_reset_in_progress(>i915->gpu_error)) {
+   __set_current_state(TASK_RUNNING);
+   i915_reset(req->i915);
+   reset_wait_queue(errq, );
+   continue;
+   }
+
+   if (signal_pending_state(state, current)) {
+   timeout = -ERESTARTSYS;
+   break;
+   }
+
+   if (!timeout) {
+   timeout = -ETIME;
+   break;
+   }
+
+   timeout = io_schedule_timeout(timeout);
+   } while (1);
+   finish_wait(>execute.wait, );
+
if (timeout < 0)
goto complete;




Reviewed-by: Tvrtko Ursulin 

Regards,

Tvrtko
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Re: [Intel-gfx] [PATCH 7/8] drm/i915/guc: Simplify intel_guc_init_hw()

[Michal Wajdeczko]

On Fri, Feb 17, 2017 at 02:05:56PM +0100, Arkadiusz Hiler wrote:
> Current version of intel_guc_init_hw() does a lot:
>  - cares about submission
>  - loads huc
>  - implement WA
> 
> This change offloads some of the logic to intel_uc_load(), which now
> cares about the above.
> 
> v2: rename guc_hw_reset and fix typo in define name (M. Wajdeczko)
> 
> Cc: Anusha Srivatsa 
> Cc: Michal Winiarski 
> Cc: Michal Wajdeczko 
> Cc: Daniele Ceraolo Spurio 
> Signed-off-by: Arkadiusz Hiler 
> ---



> diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
> index ef9dc72..2bb49b7 100644
> --- a/drivers/gpu/drm/i915/intel_uc.c
> +++ b/drivers/gpu/drm/i915/intel_uc.c
> @@ -29,6 +29,25 @@
>  static void uc_fetch_fw(struct drm_i915_private *dev_priv,
> struct intel_uc_fw *uc_fw);
>  
> +static int guc_hw_reset(struct drm_i915_private *dev_priv)

This function looks like and is guc specific.
Maybe we should revisit the idea of having separate intel_guc.c file
that will hold only guc specific functions. And use intel_uc.c file
only for functions that are common across Guc, Huc...

-Michal

> +{
> + int ret;
> + u32 guc_status;
> +
> + ret = intel_guc_reset(dev_priv);
> + if (ret) {
> + DRM_ERROR("GuC reset failed, ret = %d\n", ret);
> + return ret;
> + }
> +
> + guc_status = I915_READ(GUC_STATUS);
> + WARN(!(guc_status & GS_MIA_IN_RESET),
> +  "GuC status: 0x%x, MIA core expected to be in reset\n",
> +  guc_status);
> +
> + return ret;
> +}
> +
>  void intel_uc_sanitize_params(struct drm_i915_private *dev_priv)
>  {
>   if (!HAS_GUC(dev_priv)) {
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Re: [Intel-gfx] [PATCH 2/3] drm: reset ELD if NULL edid is passed to drm_edid_to_eld

[Jani Nikula]

On Thu, 16 Feb 2017, Ville Syrjälä  wrote:
> On Thu, Feb 16, 2017 at 12:36:43PM +0200, Jani Nikula wrote:
>> Make the function useful for resetting, not just setting, the ELD.
>> 
>> Signed-off-by: Jani Nikula 
>> ---
>>  drivers/gpu/drm/drm_edid.c | 3 +++
>>  1 file changed, 3 insertions(+)
>> 
>> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
>> index 24e7b282f16c..362036360724 100644
>> --- a/drivers/gpu/drm/drm_edid.c
>> +++ b/drivers/gpu/drm/drm_edid.c
>> @@ -3430,6 +3430,9 @@ void drm_edid_to_eld(struct drm_connector *connector, 
>> struct edid *edid)
>>  
>>  memset(eld, 0, sizeof(connector->eld));
>>  
>> +if (!edid)
>> +return;
>> +
>>  connector->latency_present[0] = false;
>>  connector->latency_present[1] = false;
>>  connector->video_latency[0] = 0;
>
> /me thinks the check should be after all these.

D'oh!

> Hmm. Actually the cea ext block check below should be safe wrt.
> edid==NULL, so not sure we need this at all.

I'd just like to be explicit and avoid the debug message on missing CEA
extensions if the whole EDID is missing.

BR,
Jani.



-- 
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[Intel-gfx] [PATCH] drm/i915: Only apply legacy PDE overflow detection to 3lvl machines

[Chris Wilson]

Prevent the overflow check from firing on machines with the full 4lvl
page tables, that are not restricted to GEN8_LEGACY_PDES.

Fixes: 894ccebee2b0 ("drm/i915: Micro-optimise gen8_ppgtt_insert_entries()")
Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 1f281554e4c9..65cadc09b56e 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -854,7 +854,8 @@ gen8_ppgtt_insert_pte_entries(struct i915_hw_ppgtt *ppgtt,
break;
}
 
-   GEM_BUG_ON(pdpe > GEN8_LEGACY_PDPES);
+   GEM_BUG_ON(!i915_vm_is_48bit(>base) &&
+  pdpe > GEN8_LEGACY_PDPES);
pd = pdp->page_directory[pdpe];
pde = 0;
}
-- 
2.11.0

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Re: [Intel-gfx] [PATCH 6/8] drm/i915/guc: Extract param logic form guc_init

[Michal Wajdeczko]

On Fri, Feb 17, 2017 at 02:05:55PM +0100, Arkadiusz Hiler wrote:
> Let intel_guc_fetch_fw() focus on determining and fetching the correct
> firmware.
> 
> This patch introduces intel_sanitize_uc_params() that is called from
> intel_sanitize_options().

Function name mentioned here does not match function in the patch.
Also, can we use "options" to match parent function name?


> 
> Then, if we have GuC, we can call intel_guc_fetch_fw() conditionally and
> we do not have to do the internal checks.
> 
> v2: fix comment, notify when nuking GuC explicitly enabled (M. Wajdeczko)
> 
> Cc: Michal Winiarski 
> Cc: Michal Wajdeczko 
> Cc: Daniele Ceraolo Spurio 
> Signed-off-by: Arkadiusz Hiler 
> ---
>  drivers/gpu/drm/i915/i915_drv.c |  2 ++
>  drivers/gpu/drm/i915/intel_guc_loader.c | 16 +---
>  drivers/gpu/drm/i915/intel_uc.c | 27 ++-
>  drivers/gpu/drm/i915/intel_uc.h |  1 +
>  4 files changed, 30 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 45fae97..687f7c0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -993,6 +993,8 @@ static void intel_sanitize_options(struct 
> drm_i915_private *dev_priv)
>  
>   i915.semaphores = intel_sanitize_semaphores(dev_priv, i915.semaphores);
>   DRM_DEBUG_DRIVER("use GPU sempahores? %s\n", yesno(i915.semaphores));
> +
> + intel_uc_sanitize_params(dev_priv);
>  }
>  
>  /**
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c 
> b/drivers/gpu/drm/i915/intel_guc_loader.c
> index 110dfd1..e74c127 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -588,7 +588,7 @@ int intel_guc_init_hw(struct drm_i915_private *dev_priv)
>  
>  
>  /**
> - * intel_guc_fetch_fw() - define parameters and fetch firmware
> + * intel_guc_fetch_fw() - determine and fetch firmware
>   * @guc: intel_guc struct
>   *
>   * Called early during driver load, but after GEM is initialised.
> @@ -601,17 +601,6 @@ void intel_guc_fetch_fw(struct intel_guc *guc)
>   struct drm_i915_private *dev_priv = guc_to_i915(guc);
>   const char *fw_path;
>  
> - if (!HAS_GUC(dev_priv)) {
> - i915.enable_guc_loading = 0;
> - i915.enable_guc_submission = 0;
> - } else {
> - /* A negative value means "use platform default" */
> - if (i915.enable_guc_loading < 0)
> - i915.enable_guc_loading = HAS_GUC_UCODE(dev_priv);
> - if (i915.enable_guc_submission < 0)
> - i915.enable_guc_submission = HAS_GUC_SCHED(dev_priv);
> - }
> -
>   if (!HAS_GUC_UCODE(dev_priv)) {
>   fw_path = NULL;
>   } else if (IS_SKYLAKE(dev_priv)) {
> @@ -634,9 +623,6 @@ void intel_guc_fetch_fw(struct intel_guc *guc)
>   guc->fw.fetch_status = INTEL_UC_FIRMWARE_NONE;
>   guc->fw.load_status = INTEL_UC_FIRMWARE_NONE;
>  
> - /* Early (and silent) return if GuC loading is disabled */
> - if (!i915.enable_guc_loading)
> - return;
>   if (fw_path == NULL)
>   return;
>   if (*fw_path == '\0')
> diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
> index d2d2b6c..ef9dc72 100644
> --- a/drivers/gpu/drm/i915/intel_uc.c
> +++ b/drivers/gpu/drm/i915/intel_uc.c
> @@ -29,6 +29,27 @@
>  static void uc_fetch_fw(struct drm_i915_private *dev_priv,
> struct intel_uc_fw *uc_fw);
>  
> +void intel_uc_sanitize_params(struct drm_i915_private *dev_priv)
> +{
> + if (!HAS_GUC(dev_priv)) {
> + if (i915.enable_guc_loading > 0)
> + DRM_INFO("Disabling GuC, no hardware");

Hmm, I'm not sure you can disable something that does not exist...
Maybe message should be like this "Ignoring GuC options (no hardware)"


> +
> + i915.enable_guc_loading = 0;
> + i915.enable_guc_submission = 0;
> + } else {
> + /* A negative value means "use platform default" */
> + if (i915.enable_guc_loading < 0)
> + i915.enable_guc_loading = HAS_GUC_UCODE(dev_priv);
> + if (i915.enable_guc_submission < 0)
> + i915.enable_guc_submission = HAS_GUC_SCHED(dev_priv);
> + }
> +
> + /* can't enable guc submission without guc loaded */
> + if (!i915.enable_guc_loading)
> + i915.enable_guc_submission = 0;

This extra condition should be moved into "else" above.

> +}
> +
>  void intel_uc_init_early(struct drm_i915_private *dev_priv)
>  {
>   mutex_init(_priv->guc.send_mutex);
> @@ -36,8 +57,12 @@ void intel_uc_init_early(struct drm_i915_private *dev_priv)
>  
>  void intel_fetch_uc_fw(struct drm_i915_private *dev_priv)
>  {
> + if (!i915.enable_guc_loading)

[Intel-gfx] ✓ Fi.CI.BAT: success for Geminilake pipe CSC (rev4)

[Patchwork]

== Series Details ==

Series: Geminilake pipe CSC (rev4)
URL   : https://patchwork.freedesktop.org/series/18596/
State : success

== Summary ==

Series 18596v4 Geminilake pipe CSC
https://patchwork.freedesktop.org/api/1.0/series/18596/revisions/4/mbox/

fi-bdw-5557u total:252  pass:241  dwarn:0   dfail:0   fail:0   skip:11 
fi-bsw-n3050 total:252  pass:213  dwarn:0   dfail:0   fail:0   skip:39 
fi-bxt-j4205 total:252  pass:233  dwarn:0   dfail:0   fail:0   skip:19 
fi-bxt-t5700 total:83   pass:70   dwarn:0   dfail:0   fail:0   skip:12 
fi-byt-j1900 total:252  pass:225  dwarn:0   dfail:0   fail:0   skip:27 
fi-byt-n2820 total:252  pass:221  dwarn:0   dfail:0   fail:0   skip:31 
fi-hsw-4770  total:252  pass:236  dwarn:0   dfail:0   fail:0   skip:16 
fi-hsw-4770r total:252  pass:236  dwarn:0   dfail:0   fail:0   skip:16 
fi-ilk-650   total:252  pass:202  dwarn:0   dfail:0   fail:0   skip:50 
fi-ivb-3520m total:252  pass:234  dwarn:0   dfail:0   fail:0   skip:18 
fi-ivb-3770  total:252  pass:234  dwarn:0   dfail:0   fail:0   skip:18 
fi-kbl-7500u total:252  pass:234  dwarn:0   dfail:0   fail:0   skip:18 
fi-skl-6260u total:252  pass:242  dwarn:0   dfail:0   fail:0   skip:10 
fi-skl-6700hqtotal:252  pass:235  dwarn:0   dfail:0   fail:0   skip:17 
fi-skl-6700k total:252  pass:230  dwarn:4   dfail:0   fail:0   skip:18 
fi-skl-6770hqtotal:252  pass:242  dwarn:0   dfail:0   fail:0   skip:10 
fi-snb-2520m total:252  pass:224  dwarn:0   dfail:0   fail:0   skip:28 
fi-snb-2600  total:252  pass:223  dwarn:0   dfail:0   fail:0   skip:29 

2b7ce9512d9770350bc2a59652cc7bf469bc544a drm-tip: 2017y-02m-17d-12h-20m-31s UTC 
integration manifest
b780a42 drm/i915: Merge BDW pipe gamma and degamma table code
03a10bc drm/i915/glk: Enable pipe CSC
0a5d181 drm/i915/glk: Load the degamma LUT even in legacy gamma mode

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3877/
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Re: [Intel-gfx] [PATCH 1/4] drm/i915: kill {bdw, bxt}_modeset_calc_cdclk

[Ville Syrjälä]

On Fri, Feb 17, 2017 at 11:22:04AM -0200, Paulo Zanoni wrote:
> The functions are pretty much the same, except for the CDCLK and VCO
> calculations. Add BDW support to vlv_modeset_calc_cdclk() and add
> BXT/GLK support to skl_modeset_calc_cdclk(). The two reamining
> functions are still very similar, except for the fact that the vlv
> version doesn't touch the VCO. Further patches could unify them even
> more if that's desired.
> 
> While at it, merge some lines that can fit 80 columns in those
> functions.
> 
> Signed-off-by: Paulo Zanoni 
> ---
>  drivers/gpu/drm/i915/intel_cdclk.c | 120 
> ++---
>  1 file changed, 30 insertions(+), 90 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c 
> b/drivers/gpu/drm/i915/intel_cdclk.c
> index d643c0c..d505ff1 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -1499,45 +1499,18 @@ static int intel_max_pixel_rate(struct 
> drm_atomic_state *state)
>  static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state)
>  {
>   struct drm_i915_private *dev_priv = to_i915(state->dev);
> - int max_pixclk = intel_max_pixel_rate(state);
> - struct intel_atomic_state *intel_state =
> - to_intel_atomic_state(state);
> - int cdclk;
> -
> - cdclk = vlv_calc_cdclk(dev_priv, max_pixclk);
> -
> - if (cdclk > dev_priv->max_cdclk_freq) {
> - DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
> -   cdclk, dev_priv->max_cdclk_freq);
> - return -EINVAL;
> - }
> -
> - intel_state->cdclk.logical.cdclk = cdclk;
> -
> - if (!intel_state->active_crtcs) {
> - cdclk = vlv_calc_cdclk(dev_priv, 0);
> -
> - intel_state->cdclk.actual.cdclk = cdclk;
> - } else {
> - intel_state->cdclk.actual =
> - intel_state->cdclk.logical;
> - }
> -
> - return 0;
> -}
> -
> -static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state)
> -{
> - struct drm_i915_private *dev_priv = to_i915(state->dev);
>   struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
>   int max_pixclk = intel_max_pixel_rate(state);
>   int cdclk;
>  
>   /*
> -  * FIXME should also account for plane ratio
> -  * once 64bpp pixel formats are supported.
> +  * FIXME: Broadwell should also account for plane ratio once 64bpp pixel
> +  * formats are supported.

BTW these restrictions affect pretty much all platforms, so specifying the
platforms in the comment is rather redundant.

>*/
> - cdclk = bdw_calc_cdclk(max_pixclk);
> + if (IS_BROADWELL(dev_priv))
> + cdclk = bdw_calc_cdclk(max_pixclk);
> + else
> + cdclk = vlv_calc_cdclk(dev_priv, max_pixclk);
>  
>   if (cdclk > dev_priv->max_cdclk_freq) {
>   DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
> @@ -1548,12 +1521,14 @@ static int bdw_modeset_calc_cdclk(struct 
> drm_atomic_state *state)
>   intel_state->cdclk.logical.cdclk = cdclk;
>  
>   if (!intel_state->active_crtcs) {
> - cdclk = bdw_calc_cdclk(0);
> + if (IS_BROADWELL(dev_priv))
> + cdclk = bdw_calc_cdclk(0);
> + else
> + cdclk = vlv_calc_cdclk(dev_priv, 0);
>  
>   intel_state->cdclk.actual.cdclk = cdclk;
>   } else {
> - intel_state->cdclk.actual =
> - intel_state->cdclk.logical;
> + intel_state->cdclk.actual = intel_state->cdclk.logical;
>   }
>  
>   return 0;
> @@ -1561,57 +1536,26 @@ static int bdw_modeset_calc_cdclk(struct 
> drm_atomic_state *state)
>  
>  static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
>  {
> - struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
>   struct drm_i915_private *dev_priv = to_i915(state->dev);
> - const int max_pixclk = intel_max_pixel_rate(state);
> + struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
> + int max_pixclk = intel_max_pixel_rate(state);
>   int cdclk, vco;
>  
> - vco = intel_state->cdclk.logical.vco;
> - if (!vco)
> - vco = dev_priv->skl_preferred_vco_freq;
> -
>   /*
> -  * FIXME should also account for plane ratio
> -  * once 64bpp pixel formats are supported.
> +  * FIXME: Skylake/Kabylake should also account for plane ratio once
> +  * 64bpp pixel formats are supported.
>*/
> - cdclk = skl_calc_cdclk(max_pixclk, vco);
> -
> - if (cdclk > dev_priv->max_cdclk_freq) {
> - DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
> -   cdclk, dev_priv->max_cdclk_freq);
> - return -EINVAL;
> - }
> -
> - intel_state->cdclk.logical.vco = vco;
> - intel_state->cdclk.logical.cdclk = cdclk;
> -
> - if 

Re: [Intel-gfx] [PATCH 2/4] drm/i915: add intel_calc_cdclk()

[Ville Syrjälä]

On Fri, Feb 17, 2017 at 11:22:05AM -0200, Paulo Zanoni wrote:
> Each x_modeset_calc_cdclk() has to do the same platform checks twice,
> so extract them to a single function. This way, the platform checks
> are all in the same place, and the platform-common code gets rid of
> all the platform-specific checks, which IMHO makes the code easier to
> read.
> 
> Signed-off-by: Paulo Zanoni 
> ---
>  drivers/gpu/drm/i915/intel_cdclk.c | 84 
> --
>  1 file changed, 45 insertions(+), 39 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c 
> b/drivers/gpu/drm/i915/intel_cdclk.c
> index d505ff1..6efc5f4 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -1496,6 +1496,47 @@ static int intel_max_pixel_rate(struct 
> drm_atomic_state *state)
>   return max_pixel_rate;
>  }
>  
> +static void intel_calc_cdclk(struct intel_atomic_state *state, int 
> max_pixclk,
> +  int *cdclk, int *vco)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> +
> + switch (INTEL_INFO(dev_priv)->platform) {
> + case INTEL_VALLEYVIEW:
> + case INTEL_CHERRYVIEW:
> + *cdclk = vlv_calc_cdclk(dev_priv, max_pixclk);
> + break;
> + case INTEL_BROADWELL:
> + /*
> +  * FIXME: should also account for plane ratio once 64bpp pixel
> +  * formats are supported.
> +  */
> + *cdclk = bdw_calc_cdclk(max_pixclk);
> + break;
> + case INTEL_SKYLAKE:
> + case INTEL_KABYLAKE:
> + /*
> +  * FIXME: should also account for plane ratio once 64bpp pixel
> +  * formats are supported.
> +  */
> + *vco = state->cdclk.logical.vco;
> + if (!*vco)
> + *vco = dev_priv->skl_preferred_vco_freq;
> + *cdclk = skl_calc_cdclk(max_pixclk, *vco);
> + break;
> + case INTEL_BROXTON:
> + *cdclk = bxt_calc_cdclk(max_pixclk);
> + *vco = bxt_de_pll_vco(dev_priv, *cdclk);
> + break;
> + case INTEL_GEMINILAKE:
> + *cdclk = glk_calc_cdclk(max_pixclk);
> + *vco = glk_de_pll_vco(dev_priv, *cdclk);
> + break;
> + default:
> + MISSING_CASE(INTEL_INFO(dev_priv)->platform);
> + }
> +}

How about just replacing the .modeset_calc_cdclk() vfunc with a slightly
lower level vfunc that just computes the cdclk/vco/whatever without
containing the active_crtcs logic?

Then we should have just

intel_modeset_calc_cdclk()
{
.calc_cdclk(logical, max_pixclk);

/*
 * maybe keep the max_cdclk check here, although it that
 * happens I think we have a bug somewhere, so perhaps
 * just convert it into a WARN, or drop entirely.
 */

if (!active_crtcs)
.calc_cdclk(actual, 0);
else
actual = logical;
}


> +
>  static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state)
>  {
>   struct drm_i915_private *dev_priv = to_i915(state->dev);
> @@ -1503,14 +1544,7 @@ static int vlv_modeset_calc_cdclk(struct 
> drm_atomic_state *state)
>   int max_pixclk = intel_max_pixel_rate(state);
>   int cdclk;
>  
> - /*
> -  * FIXME: Broadwell should also account for plane ratio once 64bpp pixel
> -  * formats are supported.
> -  */
> - if (IS_BROADWELL(dev_priv))
> - cdclk = bdw_calc_cdclk(max_pixclk);
> - else
> - cdclk = vlv_calc_cdclk(dev_priv, max_pixclk);
> + intel_calc_cdclk(intel_state, max_pixclk, , NULL);
>  
>   if (cdclk > dev_priv->max_cdclk_freq) {
>   DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
> @@ -1521,11 +1555,7 @@ static int vlv_modeset_calc_cdclk(struct 
> drm_atomic_state *state)
>   intel_state->cdclk.logical.cdclk = cdclk;
>  
>   if (!intel_state->active_crtcs) {
> - if (IS_BROADWELL(dev_priv))
> - cdclk = bdw_calc_cdclk(0);
> - else
> - cdclk = vlv_calc_cdclk(dev_priv, 0);
> -
> + intel_calc_cdclk(intel_state, 0, , NULL);
>   intel_state->cdclk.actual.cdclk = cdclk;
>   } else {
>   intel_state->cdclk.actual = intel_state->cdclk.logical;
> @@ -1541,22 +1571,7 @@ static int skl_modeset_calc_cdclk(struct 
> drm_atomic_state *state)
>   int max_pixclk = intel_max_pixel_rate(state);
>   int cdclk, vco;
>  
> - /*
> -  * FIXME: Skylake/Kabylake should also account for plane ratio once
> -  * 64bpp pixel formats are supported.
> -  */
> - if (IS_GEMINILAKE(dev_priv)) {
> - cdclk = glk_calc_cdclk(max_pixclk);
> - vco = glk_de_pll_vco(dev_priv, cdclk);
> - } else if (IS_BROXTON(dev_priv)) {
> - cdclk = bxt_calc_cdclk(max_pixclk);
> - 

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Remove completed fences after a wait

[Matthew Auld]

On 12 February 2017 at 21:53, Chris Wilson  wrote:
> If we wait up on the full (i.e. all shared fences, or upon an exclusive fence)
s/up on/upon

> reservation object successfully, we know that all fences beneath it have
> been signaled, so long as no new fences were added whilst we slept. If the
> reservation_object remains the same, as detected by its seqcount, we can
> then reap all the fences upon completion.
>
> Signed-off-by: Chris Wilson 
> Cc: Joonas Lahtinen 
Reviewed-by: Matthew Auld 
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Re: [Intel-gfx] [PATCH 5/8] drm/i915/uc: Make intel_uc_fw_fetch() static

[Michal Wajdeczko]

On Fri, Feb 17, 2017 at 02:05:54PM +0100, Arkadiusz Hiler wrote:
> intel_uc_fw_fetch() is confusingly named in the light of recent changes.
> 
> It's also in the worng place - 'guc_loader.h' - it's used for both guc

Typo s/worng/wrong

> and huc, which was reflected in name, but not it's location, so let's
> move it to 'intel_uc.c'.
> 
> We can make a intel_uc_fw callback out of it, to avoid leaking it
> outside `intel_uc.c`

Hmm, why do you think it is a problem to expose this function outside of 
intel_uc.c?
I can't see any real gain, rather unnecessary code complexity

-Michal

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[Intel-gfx] [PATCH i-g-t] tests/kms_atomic: test that TEST_ONLY does not clobber state

[Mika Kahola]

We need to make sure that TEST_ONLY really only touches the free-standing
state objects and nothing else. Test approach here is the following:

- Create a config and submit it with TEST_ONLY.
- do dpms off/on cycle with the current config to reconfigure hw
- read back all legacy state to make sure none of that is clobbered

Signed-off-by: Mika Kahola 
---
 tests/kms_atomic.c | 79 ++
 1 file changed, 79 insertions(+)

diff --git a/tests/kms_atomic.c b/tests/kms_atomic.c
index d6273f4..3531fa4 100644
--- a/tests/kms_atomic.c
+++ b/tests/kms_atomic.c
@@ -831,6 +831,25 @@ static uint32_t plane_get_igt_format(struct 
kms_atomic_plane_state *plane)
return ret;
 }
 
+static void
+set_dpms(int fd, int mode)
+{
+   int i;
+   drmModeConnector *connector;
+   uint32_t id;
+   drmModeRes *resources = drmModeGetResources(fd);
+
+   for (i = 0; i < resources->count_connectors; i++) {
+   id = resources->connectors[i];
+
+   connector = drmModeGetConnectorCurrent(fd, id);
+
+   kmstest_set_connector_dpms(fd, connector, mode);
+
+   drmModeFreeConnector(connector);
+   }
+}
+
 static void plane_overlay(struct kms_atomic_crtc_state *crtc,
  struct kms_atomic_plane_state *plane_old)
 {
@@ -930,6 +949,54 @@ static void plane_primary(struct kms_atomic_crtc_state 
*crtc,
drmModeAtomicFree(req);
 }
 
+static void plane_primary_state_check(struct kms_atomic_crtc_state *crtc,
+ struct kms_atomic_plane_state *plane_old)
+{
+   struct drm_mode_modeinfo *mode = crtc->mode.data;
+   struct kms_atomic_plane_state plane = *plane_old;
+   uint32_t format = plane_get_igt_format();
+   drmModeAtomicReq *req = drmModeAtomicAlloc();
+   struct igt_fb fb;
+   int ret;
+
+   igt_require(format != 0);
+
+   plane.src_x = 0;
+   plane.src_y = 0;
+   plane.src_w = mode->hdisplay << 16;
+   plane.src_h = mode->vdisplay << 16;
+   plane.crtc_x = 0;
+   plane.crtc_y = 0;
+   plane.crtc_w = mode->hdisplay;
+   plane.crtc_h = mode->vdisplay;
+   plane.crtc_id = crtc->obj;
+   plane.fb_id = igt_create_pattern_fb(plane.state->desc->fd,
+   plane.crtc_w, plane.crtc_h,
+   format, I915_TILING_NONE, );
+
+   drmModeAtomicSetCursor(req, 0);
+   crtc_populate_req(crtc, req);
+   plane_populate_req(, req);
+   ret = drmModeAtomicCommit(crtc->state->desc->fd, req,
+ DRM_MODE_ATOMIC_TEST_ONLY, NULL);
+
+   igt_assert_eq(ret, 0);
+
+   /* go through dpms off/on cycle */
+   set_dpms(crtc->state->desc->fd, DRM_MODE_DPMS_OFF);
+   set_dpms(crtc->state->desc->fd, DRM_MODE_DPMS_ON);
+
+   /* check the state */
+   crtc_check_current_state(crtc, plane_old, CRTC_RELAX_MODE);
+   plane_check_current_state(plane_old, CRTC_RELAX_MODE);
+
+   /* Re-enable the plane through the legacy CRTC/primary-plane API, and
+* verify through atomic. */
+   crtc_commit_legacy(crtc, plane_old, CRTC_RELAX_MODE);
+
+   drmModeAtomicFree(req);
+}
+
 static void plane_cursor(struct kms_atomic_crtc_state *crtc,
 struct kms_atomic_plane_state *plane_old)
 {
@@ -1427,6 +1494,18 @@ igt_main
atomic_state_free(scratch);
}
 
+   igt_subtest("plane_primary_state_check") {
+   struct kms_atomic_state *scratch = atomic_state_dup(current);
+   struct kms_atomic_crtc_state *crtc = find_crtc(scratch, true);
+   struct kms_atomic_plane_state *plane =
+   find_plane(scratch, PLANE_TYPE_PRIMARY, crtc);
+
+   igt_require(crtc);
+   igt_require(plane);
+   plane_primary_state_check(crtc, plane);
+   atomic_state_free(scratch);
+   }
+
igt_subtest("plane_cursor_legacy") {
struct kms_atomic_state *scratch = atomic_state_dup(current);
struct kms_atomic_crtc_state *crtc = find_crtc(scratch, true);
-- 
2.7.4

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Re: [Intel-gfx] [PATCH 4/8] drm/i915/uc: Rename intel_?uc_init() to intel_?uc_fetch_fw()

[Michal Wajdeczko]

On Fri, Feb 17, 2017 at 02:05:53PM +0100, Arkadiusz Hiler wrote:
> Trying to have subject_verb_object ordering and more descriptive names,
> the intel_huc_init() and intel_guc_init() functions are renamed:
> 
>  * `intel_guc` is the subject, so those functions now take intel_guc
>structure, instead of the dev_priv
>  * fetch is the verb
>  * fw is the object which better describes the function's role
> 
> Same change is done for the huc counterpart.
> 
> Also we bulk call both functions from higher-level intel_fetch_uc_fw:
>  * intel being the subject (taking the dev_priv as param)
>  * fetch being the verb
>  * uc_fw being the subject
> 
> Cc: Joonas Lahtinen 
> Cc: Michal Wajdeczko 
> Cc: Michal Winiarski 
> Signed-off-by: Arkadiusz Hiler 
> ---



> diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
> index 41b7351..19b8966 100644
> --- a/drivers/gpu/drm/i915/intel_uc.h
> +++ b/drivers/gpu/drm/i915/intel_uc.h
> @@ -185,11 +185,12 @@ struct intel_huc {
>  
>  /* intel_uc.c */
>  void intel_uc_init_early(struct drm_i915_private *dev_priv);
> +void intel_fetch_uc_fw(struct drm_i915_private *dev_priv);

Hmm, names of these two functions above are inconsistent now.
Maybe they both should start with i915 as they take dev_priv:

void i915_uc_init_early(struct drm_i915_private *dev_priv);
void i915_uc_fetch_fw(struct drm_i915_private *dev_priv);

or treat intel_uc as a subject:

void intel_uc_init_early(struct drm_i915_private *dev_priv);
void intel_uc_fetch_fw(struct drm_i915_private *dev_priv);


-Michal 

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Re: [Intel-gfx] Ubuntu 16.04.2 LTS with Intel Corporation Sky Lake Integrated Graphics (rev 06)

[Jani Nikula]

On Fri, 17 Feb 2017, Eric Johansson  wrote:
> Hello,
>
> I have an HP EliteOne 800 G2 AiO which according to "lspci -v" has a
> Intel Corporation Sky Lake Integrated Graphics (rev 06). I have
> previously installed Ubuntu 16.04.1 LTS with kernel 4.4 on the
> computer and today also installed Ubuntu 16.04.2 LTS (clean install
> from a USB memory) which has kernel 4.8.0-36-generic. If I understand
> things right there should be new graphic hardware support in 16.04.2.
>
> Unfortunately, for both 16.04.2 and 16.04.1 I have the same problem
> which is that the screen is split in half so that the whole desktop is
> squeezed into the upper half of the screen. Do you have any idea how
> to get the graphics working? Thanks in advance!

Try disabling legacy boot and switching to UEFI boot in the BIOS
settings.

Relevant bug report https://bugs.freedesktop.org/show_bug.cgi?id=97822

BR,
Jani.

-- 
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[Intel-gfx] [PATCH 0/4] Small clocking code refactor

[Paulo Zanoni]

Hi

I've been trying to understand the clocking code and spotted some
possible improvements. None of these changes are actually necessary
for anything, but IMHO they make the code a little easier to read and
later extend. Feel free to bikeshed or even NAK my proposals.

Thanks,
Paulo

Paulo Zanoni (4):
  drm/i915: kill {bdw,bxt}_modeset_calc_cdclk
  drm/i915: add intel_calc_cdclk()
  drm/i915: remove potentially confusing IS_G4X checks
  drm/i915: reorganize the get_cdclk assignment

 drivers/gpu/drm/i915/intel_cdclk.c | 257 -
 1 file changed, 112 insertions(+), 145 deletions(-)

-- 
2.7.4

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[Intel-gfx] [PATCH 2/4] drm/i915: add intel_calc_cdclk()

[Paulo Zanoni]

Each x_modeset_calc_cdclk() has to do the same platform checks twice,
so extract them to a single function. This way, the platform checks
are all in the same place, and the platform-common code gets rid of
all the platform-specific checks, which IMHO makes the code easier to
read.

Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/intel_cdclk.c | 84 --
 1 file changed, 45 insertions(+), 39 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_cdclk.c 
b/drivers/gpu/drm/i915/intel_cdclk.c
index d505ff1..6efc5f4 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1496,6 +1496,47 @@ static int intel_max_pixel_rate(struct drm_atomic_state 
*state)
return max_pixel_rate;
 }
 
+static void intel_calc_cdclk(struct intel_atomic_state *state, int max_pixclk,
+int *cdclk, int *vco)
+{
+   struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+
+   switch (INTEL_INFO(dev_priv)->platform) {
+   case INTEL_VALLEYVIEW:
+   case INTEL_CHERRYVIEW:
+   *cdclk = vlv_calc_cdclk(dev_priv, max_pixclk);
+   break;
+   case INTEL_BROADWELL:
+   /*
+* FIXME: should also account for plane ratio once 64bpp pixel
+* formats are supported.
+*/
+   *cdclk = bdw_calc_cdclk(max_pixclk);
+   break;
+   case INTEL_SKYLAKE:
+   case INTEL_KABYLAKE:
+   /*
+* FIXME: should also account for plane ratio once 64bpp pixel
+* formats are supported.
+*/
+   *vco = state->cdclk.logical.vco;
+   if (!*vco)
+   *vco = dev_priv->skl_preferred_vco_freq;
+   *cdclk = skl_calc_cdclk(max_pixclk, *vco);
+   break;
+   case INTEL_BROXTON:
+   *cdclk = bxt_calc_cdclk(max_pixclk);
+   *vco = bxt_de_pll_vco(dev_priv, *cdclk);
+   break;
+   case INTEL_GEMINILAKE:
+   *cdclk = glk_calc_cdclk(max_pixclk);
+   *vco = glk_de_pll_vco(dev_priv, *cdclk);
+   break;
+   default:
+   MISSING_CASE(INTEL_INFO(dev_priv)->platform);
+   }
+}
+
 static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state)
 {
struct drm_i915_private *dev_priv = to_i915(state->dev);
@@ -1503,14 +1544,7 @@ static int vlv_modeset_calc_cdclk(struct 
drm_atomic_state *state)
int max_pixclk = intel_max_pixel_rate(state);
int cdclk;
 
-   /*
-* FIXME: Broadwell should also account for plane ratio once 64bpp pixel
-* formats are supported.
-*/
-   if (IS_BROADWELL(dev_priv))
-   cdclk = bdw_calc_cdclk(max_pixclk);
-   else
-   cdclk = vlv_calc_cdclk(dev_priv, max_pixclk);
+   intel_calc_cdclk(intel_state, max_pixclk, , NULL);
 
if (cdclk > dev_priv->max_cdclk_freq) {
DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
@@ -1521,11 +1555,7 @@ static int vlv_modeset_calc_cdclk(struct 
drm_atomic_state *state)
intel_state->cdclk.logical.cdclk = cdclk;
 
if (!intel_state->active_crtcs) {
-   if (IS_BROADWELL(dev_priv))
-   cdclk = bdw_calc_cdclk(0);
-   else
-   cdclk = vlv_calc_cdclk(dev_priv, 0);
-
+   intel_calc_cdclk(intel_state, 0, , NULL);
intel_state->cdclk.actual.cdclk = cdclk;
} else {
intel_state->cdclk.actual = intel_state->cdclk.logical;
@@ -1541,22 +1571,7 @@ static int skl_modeset_calc_cdclk(struct 
drm_atomic_state *state)
int max_pixclk = intel_max_pixel_rate(state);
int cdclk, vco;
 
-   /*
-* FIXME: Skylake/Kabylake should also account for plane ratio once
-* 64bpp pixel formats are supported.
-*/
-   if (IS_GEMINILAKE(dev_priv)) {
-   cdclk = glk_calc_cdclk(max_pixclk);
-   vco = glk_de_pll_vco(dev_priv, cdclk);
-   } else if (IS_BROXTON(dev_priv)) {
-   cdclk = bxt_calc_cdclk(max_pixclk);
-   vco = bxt_de_pll_vco(dev_priv, cdclk);
-   } else {
-   vco = intel_state->cdclk.logical.vco;
-   if (!vco)
-   vco = dev_priv->skl_preferred_vco_freq;
-   cdclk = skl_calc_cdclk(max_pixclk, vco);
-   }
+   intel_calc_cdclk(intel_state, max_pixclk, , );
 
if (cdclk > dev_priv->max_cdclk_freq) {
DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
@@ -1568,16 +1583,7 @@ static int skl_modeset_calc_cdclk(struct 
drm_atomic_state *state)
intel_state->cdclk.logical.cdclk = cdclk;
 
if (!intel_state->active_crtcs) {
-   if (IS_GEMINILAKE(dev_priv)) {
-   cdclk = glk_calc_cdclk(0);
-

[Intel-gfx] [PATCH 3/4] drm/i915: remove potentially confusing IS_G4X checks

[Paulo Zanoni]

The IS_G4X macro is defined as IS_G45 || IS_GM45. We have two points
in our code where we have an if statement checking for GM45 followed
by an else if statement checking for IS_G4X. This can be confusing
since the IS_G4X check won't be catching the previously-checked GM45.
Someone quickly trying to check which functions run on each platform
may end up getting confused while reading the code.

Fix the potential confusion by limiting the else if statements to only
check for the platform that was not already checked earlier in the if
ladder.

Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/intel_cdclk.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_cdclk.c 
b/drivers/gpu/drm/i915/intel_cdclk.c
index 6efc5f4..7c92dc7 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -223,7 +223,7 @@ static unsigned int intel_hpll_vco(struct drm_i915_private 
*dev_priv)
/* FIXME other chipsets? */
if (IS_GM45(dev_priv))
vco_table = ctg_vco;
-   else if (IS_G4X(dev_priv))
+   else if (IS_G45(dev_priv))
vco_table = elk_vco;
else if (IS_I965GM(dev_priv))
vco_table = cl_vco;
@@ -1805,7 +1805,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private 
*dev_priv)
dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk;
else if (IS_GM45(dev_priv))
dev_priv->display.get_cdclk = gm45_get_cdclk;
-   else if (IS_G4X(dev_priv))
+   else if (IS_G45(dev_priv))
dev_priv->display.get_cdclk = g33_get_cdclk;
else if (IS_I965GM(dev_priv))
dev_priv->display.get_cdclk = i965gm_get_cdclk;
-- 
2.7.4

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[Intel-gfx] [PATCH 4/4] drm/i915: reorganize the get_cdclk assignment

[Paulo Zanoni]

Possible problems of the current if-ladder:
  - It's a huge if ladder with almost a different check for each of
our platforms.
  - It mixes 3 different types of checks: IS_GENX, IS_PLATFORM and
IS_GROUP_OF_PLATFORMS.
  - As demonstrated by the recent IS_G4X commit, it's not easy to be
sure if a platform down on the list isn't also checked earlier.
  - As demonstrated by the WARN at the end, it's not easy to be sure
if we're actually checking for every single platform.

Possible advantages of the new switch statement:
  - It may be easier for the compiler to optimize stuff (I didn't
check this), especially since the values are labels of an enum.
  - The compiler will tell us in case we miss some platform.
  - All platforms are explicitly there instead of maybe hidden in some
check for a certain group of platforms such as IS_GEN9_BC.

Possible disadvantages with the new code:
  - A few lines bigger.

Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/intel_cdclk.c | 103 ++---
 1 file changed, 62 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_cdclk.c 
b/drivers/gpu/drm/i915/intel_cdclk.c
index 7c92dc7..58a2f5c 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1789,49 +1789,70 @@ void intel_init_cdclk_hooks(struct drm_i915_private 
*dev_priv)
dev_priv->display.modeset_calc_cdclk = skl_modeset_calc_cdclk;
}
 
-   if (IS_GEN9_BC(dev_priv))
-   dev_priv->display.get_cdclk = skl_get_cdclk;
-   else if (IS_GEN9_LP(dev_priv))
-   dev_priv->display.get_cdclk = bxt_get_cdclk;
-   else if (IS_BROADWELL(dev_priv))
-   dev_priv->display.get_cdclk = bdw_get_cdclk;
-   else if (IS_HASWELL(dev_priv))
-   dev_priv->display.get_cdclk = hsw_get_cdclk;
-   else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
-   dev_priv->display.get_cdclk = vlv_get_cdclk;
-   else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
+   switch (INTEL_INFO(dev_priv)->platform) {
+   case INTEL_PLATFORM_UNINITIALIZED:
+   MISSING_CASE(INTEL_INFO(dev_priv)->platform);
+   /* Fall through. */
+   case INTEL_I830:
+   dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk;
+   break;
+   case INTEL_I845G:
+   dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk;
+   break;
+   case INTEL_I85X:
+   dev_priv->display.get_cdclk = i85x_get_cdclk;
+   break;
+   case INTEL_I865G:
+   dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk;
+   break;
+   case INTEL_I915G:
+   dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk;
+   break;
+   case INTEL_I915GM:
+   dev_priv->display.get_cdclk = i915gm_get_cdclk;
+   break;
+   case INTEL_I945G:
+   case INTEL_I965G:
+   case INTEL_SANDYBRIDGE:
+   case INTEL_IVYBRIDGE:
dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
-   else if (IS_GEN5(dev_priv))
-   dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk;
-   else if (IS_GM45(dev_priv))
-   dev_priv->display.get_cdclk = gm45_get_cdclk;
-   else if (IS_G45(dev_priv))
+   break;
+   case INTEL_I945GM:
+   dev_priv->display.get_cdclk = i945gm_get_cdclk;
+   break;
+   case INTEL_G33:
+   case INTEL_G45:
dev_priv->display.get_cdclk = g33_get_cdclk;
-   else if (IS_I965GM(dev_priv))
-   dev_priv->display.get_cdclk = i965gm_get_cdclk;
-   else if (IS_I965G(dev_priv))
-   dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
-   else if (IS_PINEVIEW(dev_priv))
+   break;
+   case INTEL_PINEVIEW:
dev_priv->display.get_cdclk = pnv_get_cdclk;
-   else if (IS_G33(dev_priv))
-   dev_priv->display.get_cdclk = g33_get_cdclk;
-   else if (IS_I945GM(dev_priv))
-   dev_priv->display.get_cdclk = i945gm_get_cdclk;
-   else if (IS_I945G(dev_priv))
-   dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
-   else if (IS_I915GM(dev_priv))
-   dev_priv->display.get_cdclk = i915gm_get_cdclk;
-   else if (IS_I915G(dev_priv))
-   dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk;
-   else if (IS_I865G(dev_priv))
-   dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk;
-   else if (IS_I85X(dev_priv))
-   dev_priv->display.get_cdclk = i85x_get_cdclk;
-   else if (IS_I845G(dev_priv))
-   dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk;
-   else { /* 830 */
-   WARN(!IS_I830(dev_priv),
-"Unknown platform. Assuming 133 MHz CDCLK\n");
-   

[Intel-gfx] [PATCH 1/4] drm/i915: kill {bdw, bxt}_modeset_calc_cdclk

[Paulo Zanoni]

The functions are pretty much the same, except for the CDCLK and VCO
calculations. Add BDW support to vlv_modeset_calc_cdclk() and add
BXT/GLK support to skl_modeset_calc_cdclk(). The two reamining
functions are still very similar, except for the fact that the vlv
version doesn't touch the VCO. Further patches could unify them even
more if that's desired.

While at it, merge some lines that can fit 80 columns in those
functions.

Signed-off-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/intel_cdclk.c | 120 ++---
 1 file changed, 30 insertions(+), 90 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_cdclk.c 
b/drivers/gpu/drm/i915/intel_cdclk.c
index d643c0c..d505ff1 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1499,45 +1499,18 @@ static int intel_max_pixel_rate(struct drm_atomic_state 
*state)
 static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state)
 {
struct drm_i915_private *dev_priv = to_i915(state->dev);
-   int max_pixclk = intel_max_pixel_rate(state);
-   struct intel_atomic_state *intel_state =
-   to_intel_atomic_state(state);
-   int cdclk;
-
-   cdclk = vlv_calc_cdclk(dev_priv, max_pixclk);
-
-   if (cdclk > dev_priv->max_cdclk_freq) {
-   DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
- cdclk, dev_priv->max_cdclk_freq);
-   return -EINVAL;
-   }
-
-   intel_state->cdclk.logical.cdclk = cdclk;
-
-   if (!intel_state->active_crtcs) {
-   cdclk = vlv_calc_cdclk(dev_priv, 0);
-
-   intel_state->cdclk.actual.cdclk = cdclk;
-   } else {
-   intel_state->cdclk.actual =
-   intel_state->cdclk.logical;
-   }
-
-   return 0;
-}
-
-static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state)
-{
-   struct drm_i915_private *dev_priv = to_i915(state->dev);
struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
int max_pixclk = intel_max_pixel_rate(state);
int cdclk;
 
/*
-* FIXME should also account for plane ratio
-* once 64bpp pixel formats are supported.
+* FIXME: Broadwell should also account for plane ratio once 64bpp pixel
+* formats are supported.
 */
-   cdclk = bdw_calc_cdclk(max_pixclk);
+   if (IS_BROADWELL(dev_priv))
+   cdclk = bdw_calc_cdclk(max_pixclk);
+   else
+   cdclk = vlv_calc_cdclk(dev_priv, max_pixclk);
 
if (cdclk > dev_priv->max_cdclk_freq) {
DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
@@ -1548,12 +1521,14 @@ static int bdw_modeset_calc_cdclk(struct 
drm_atomic_state *state)
intel_state->cdclk.logical.cdclk = cdclk;
 
if (!intel_state->active_crtcs) {
-   cdclk = bdw_calc_cdclk(0);
+   if (IS_BROADWELL(dev_priv))
+   cdclk = bdw_calc_cdclk(0);
+   else
+   cdclk = vlv_calc_cdclk(dev_priv, 0);
 
intel_state->cdclk.actual.cdclk = cdclk;
} else {
-   intel_state->cdclk.actual =
-   intel_state->cdclk.logical;
+   intel_state->cdclk.actual = intel_state->cdclk.logical;
}
 
return 0;
@@ -1561,57 +1536,26 @@ static int bdw_modeset_calc_cdclk(struct 
drm_atomic_state *state)
 
 static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
 {
-   struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
struct drm_i915_private *dev_priv = to_i915(state->dev);
-   const int max_pixclk = intel_max_pixel_rate(state);
+   struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
+   int max_pixclk = intel_max_pixel_rate(state);
int cdclk, vco;
 
-   vco = intel_state->cdclk.logical.vco;
-   if (!vco)
-   vco = dev_priv->skl_preferred_vco_freq;
-
/*
-* FIXME should also account for plane ratio
-* once 64bpp pixel formats are supported.
+* FIXME: Skylake/Kabylake should also account for plane ratio once
+* 64bpp pixel formats are supported.
 */
-   cdclk = skl_calc_cdclk(max_pixclk, vco);
-
-   if (cdclk > dev_priv->max_cdclk_freq) {
-   DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
- cdclk, dev_priv->max_cdclk_freq);
-   return -EINVAL;
-   }
-
-   intel_state->cdclk.logical.vco = vco;
-   intel_state->cdclk.logical.cdclk = cdclk;
-
-   if (!intel_state->active_crtcs) {
-   cdclk = skl_calc_cdclk(0, vco);
-
-   intel_state->cdclk.actual.vco = vco;
-   intel_state->cdclk.actual.cdclk = cdclk;
-   } else {
-   intel_state->cdclk.actual =
-   

Re: [Intel-gfx] [PATCH 3/8] drm/i915/huc: Add huc_to_i915

[Michal Wajdeczko]

On Fri, Feb 17, 2017 at 02:05:52PM +0100, Arkadiusz Hiler wrote:
> Used to obtain "dev_priv" from huc struct pointer.
> We already have similar thing for guc.
> 
> Cc: Michal Wajdeczko 
> Signed-off-by: Arkadiusz Hiler 

Reviewed-by: Michal Wajdeczko 

-Michal

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Re: [Intel-gfx] [PATCH 2/8] drm/i915/uc: Drop superfluous externs in intel_uc.h

[Michal Wajdeczko]

On Fri, Feb 17, 2017 at 02:05:51PM +0100, Arkadiusz Hiler wrote:

I think one line with description will not kill us ;)

Reviewed-by: Michal Wajdeczko 

> Cc: Michal Wajdeczko 
> Signed-off-by: Arkadiusz Hiler 
> ---
>  drivers/gpu/drm/i915/intel_uc.h | 12 ++--
>  1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
> index dd34a1b..41b7351 100644
> --- a/drivers/gpu/drm/i915/intel_uc.h
> +++ b/drivers/gpu/drm/i915/intel_uc.h
> @@ -189,12 +189,12 @@ int intel_guc_send(struct intel_guc *guc, const u32 
> *action, u32 len);
>  int intel_guc_sample_forcewake(struct intel_guc *guc);
>  
>  /* intel_guc_loader.c */
> -extern void intel_guc_init(struct drm_i915_private *dev_priv);
> -extern int intel_guc_init_hw(struct drm_i915_private *dev_priv);
> -extern void intel_guc_fini(struct drm_i915_private *dev_priv);
> -extern const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status);
> -extern int intel_guc_suspend(struct drm_i915_private *dev_priv);
> -extern int intel_guc_resume(struct drm_i915_private *dev_priv);
> +void intel_guc_init(struct drm_i915_private *dev_priv);
> +int intel_guc_init_hw(struct drm_i915_private *dev_priv);
> +void intel_guc_fini(struct drm_i915_private *dev_priv);
> +const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status);
> +int intel_guc_suspend(struct drm_i915_private *dev_priv);
> +int intel_guc_resume(struct drm_i915_private *dev_priv);
>  void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
>   struct intel_uc_fw *uc_fw);
>  u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv);
> -- 
> 2.9.3
> 
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Re: [Intel-gfx] [PATCH 1/8] drm/i915/uc: Rename intel_?uc_{setup, load}() to _init_hw()

[Michal Wajdeczko]

On Fri, Feb 17, 2017 at 02:05:50PM +0100, Arkadiusz Hiler wrote:
> GuC historically has two "startup" functions called _init() and _setup()
> 
> Then HuC came with it's _init() and _load().
> 
> This commit renames intel_guc_setup() and intel_huc_load() to
> *uc_init_hw() as they called from the i915_gem_init_hw().
> 
> The aim is to be consistent in that entry points called during
> particular driver init phases (e.g. init_hw) are all suffixed by that
> phase. When reading the leaf functions, it should be clear at what stage
> during the driver load it is called and therefore what operations are
> legal at that point.
> 
> v2: commit message update (Chris Wilson)
> 
> Cc: Chris Wilson 
> Cc: Michal Winiarski 
> Cc: Michal Wajdeczko 
> Signed-off-by: Arkadiusz Hiler 
> Reviewed-by: Joonas Lahtinen 

Reviewed-by: Michal Wajdeczko 

-Michal
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[Intel-gfx] [PATCH 7/8] drm/i915/guc: Simplify intel_guc_init_hw()

[Arkadiusz Hiler]

Current version of intel_guc_init_hw() does a lot:
 - cares about submission
 - loads huc
 - implement WA

This change offloads some of the logic to intel_uc_load(), which now
cares about the above.

v2: rename guc_hw_reset and fix typo in define name (M. Wajdeczko)

Cc: Anusha Srivatsa 
Cc: Michal Winiarski 
Cc: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
Signed-off-by: Arkadiusz Hiler 
---
 drivers/gpu/drm/i915/i915_gem.c |   2 +-
 drivers/gpu/drm/i915/intel_guc_loader.c | 136 +++-
 drivers/gpu/drm/i915/intel_uc.c | 105 
 drivers/gpu/drm/i915/intel_uc.h |   5 ++
 4 files changed, 123 insertions(+), 125 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index fa2ca05..c3147f5 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4499,7 +4499,7 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
intel_mocs_init_l3cc_table(dev_priv);
 
/* We can't enable contexts until all firmware is loaded */
-   ret = intel_guc_init_hw(dev_priv);
+   ret = intel_uc_init_hw(dev_priv);
if (ret)
goto out;
 
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c 
b/drivers/gpu/drm/i915/intel_guc_loader.c
index e74c127..549a254 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -90,7 +90,7 @@ const char *intel_uc_fw_status_repr(enum intel_uc_fw_status 
status)
}
 };
 
-static void guc_interrupts_release(struct drm_i915_private *dev_priv)
+void intel_guc_interrupts_release(struct drm_i915_private *dev_priv)
 {
struct intel_engine_cs *engine;
enum intel_engine_id id;
@@ -108,7 +108,7 @@ static void guc_interrupts_release(struct drm_i915_private 
*dev_priv)
I915_WRITE(GUC_WD_VECS_IER, 0);
 }
 
-static void guc_interrupts_capture(struct drm_i915_private *dev_priv)
+void intel_guc_interrupts_capture(struct drm_i915_private *dev_priv)
 {
struct intel_engine_cs *engine;
enum intel_engine_id id;
@@ -408,24 +408,6 @@ static int guc_ucode_xfer(struct drm_i915_private 
*dev_priv)
return ret;
 }
 
-static int guc_hw_reset(struct drm_i915_private *dev_priv)
-{
-   int ret;
-   u32 guc_status;
-
-   ret = intel_guc_reset(dev_priv);
-   if (ret) {
-   DRM_ERROR("GuC reset failed, ret = %d\n", ret);
-   return ret;
-   }
-
-   guc_status = I915_READ(GUC_STATUS);
-   WARN(!(guc_status & GS_MIA_IN_RESET),
-"GuC status: 0x%x, MIA core expected to be in reset\n", 
guc_status);
-
-   return ret;
-}
-
 /**
  * intel_guc_init_hw() - finish preparing the GuC for activity
  * @dev_priv:  i915 device private
@@ -443,147 +425,53 @@ int intel_guc_init_hw(struct drm_i915_private *dev_priv)
 {
struct intel_uc_fw *guc_fw = _priv->guc.fw;
const char *fw_path = guc_fw->path;
-   int retries, ret, err;
+   int ret;
 
DRM_DEBUG_DRIVER("GuC fw status: path %s, fetch %s, load %s\n",
fw_path,
intel_uc_fw_status_repr(guc_fw->fetch_status),
intel_uc_fw_status_repr(guc_fw->load_status));
 
-   /* Loading forbidden, or no firmware to load? */
-   if (!i915.enable_guc_loading) {
-   err = 0;
-   goto fail;
-   } else if (fw_path == NULL) {
+   if (fw_path == NULL) {
/* Device is known to have no uCode (e.g. no GuC) */
-   err = -ENXIO;
-   goto fail;
+   return -ENXIO;
} else if (*fw_path == '\0') {
/* Device has a GuC but we don't know what f/w to load? */
WARN(1, "No GuC firmware known for this platform!\n");
-   err = -ENODEV;
-   goto fail;
+   return -ENODEV;
}
 
/* Fetch failed, or already fetched but failed to load? */
if (guc_fw->fetch_status != INTEL_UC_FIRMWARE_SUCCESS) {
-   err = -EIO;
-   goto fail;
+   return -EIO;
} else if (guc_fw->load_status == INTEL_UC_FIRMWARE_FAIL) {
-   err = -ENOEXEC;
-   goto fail;
+   return -ENOEXEC;
}
 
-   guc_interrupts_release(dev_priv);
-   gen9_reset_guc_interrupts(dev_priv);
-
-   /* We need to notify the guc whenever we change the GGTT */
-   i915_ggtt_enable_guc(dev_priv);
-
guc_fw->load_status = INTEL_UC_FIRMWARE_PENDING;
 
DRM_DEBUG_DRIVER("GuC fw status: fetch %s, load %s\n",
intel_uc_fw_status_repr(guc_fw->fetch_status),
intel_uc_fw_status_repr(guc_fw->load_status));
 
-   err = i915_guc_submission_init(dev_priv);
-   if (err)
-   goto fail;
-
/*
 

[Intel-gfx] [PATCH 8/8] drm/i915/uc: Simplify firwmare path handling

[Arkadiusz Hiler]

Currently fw->path values can represent one of three possible states:

 1) NULL - device without the uC
 2) '\0' - device with the uC but have no firmware
 3) else - device with the uC and we have firmware

Second case is used only to WARN at a later stage.

We can WARN right away and merge cases 1 and 2.

Code can be even further simplified and common (HuC/GuC logic) happening
right before the fetch can be offloaded to the common function.

v2: fewer temporary variables, more straightforward flow (M. Wajdeczko)

Cc: Anusha Srivatsa 
Cc: Tvrtko Ursulin 
Cc: Michal Winiarski 
Cc: Michal Wajdeczko 
Signed-off-by: Arkadiusz Hiler 
---
 drivers/gpu/drm/i915/intel_guc_loader.c | 39 +++--
 drivers/gpu/drm/i915/intel_huc.c| 20 +
 drivers/gpu/drm/i915/intel_uc.c |  5 +++--
 3 files changed, 22 insertions(+), 42 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c 
b/drivers/gpu/drm/i915/intel_guc_loader.c
index 549a254..aade185 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -433,12 +433,8 @@ int intel_guc_init_hw(struct drm_i915_private *dev_priv)
intel_uc_fw_status_repr(guc_fw->load_status));
 
if (fw_path == NULL) {
-   /* Device is known to have no uCode (e.g. no GuC) */
+   /* We do not have uCode for the device */
return -ENXIO;
-   } else if (*fw_path == '\0') {
-   /* Device has a GuC but we don't know what f/w to load? */
-   WARN(1, "No GuC firmware known for this platform!\n");
-   return -ENODEV;
}
 
/* Fetch failed, or already fetched but failed to load? */
@@ -474,7 +470,6 @@ int intel_guc_init_hw(struct drm_i915_private *dev_priv)
return 0;
 }
 
-
 /**
  * intel_guc_fetch_fw() - determine and fetch firmware
  * @guc:   intel_guc struct
@@ -487,39 +482,31 @@ int intel_guc_init_hw(struct drm_i915_private *dev_priv)
 void intel_guc_fetch_fw(struct intel_guc *guc)
 {
struct drm_i915_private *dev_priv = guc_to_i915(guc);
-   const char *fw_path;
 
-   if (!HAS_GUC_UCODE(dev_priv)) {
-   fw_path = NULL;
-   } else if (IS_SKYLAKE(dev_priv)) {
-   fw_path = I915_SKL_GUC_UCODE;
+   guc->fw.path = NULL;
+   guc->fw.fetch_status = INTEL_UC_FIRMWARE_NONE;
+   guc->fw.load_status = INTEL_UC_FIRMWARE_NONE;
+   guc->fw.fw = INTEL_UC_FW_TYPE_GUC;
+
+   if (IS_SKYLAKE(dev_priv)) {
+   guc->fw.path = I915_SKL_GUC_UCODE;
guc->fw.major_ver_wanted = SKL_FW_MAJOR;
guc->fw.minor_ver_wanted = SKL_FW_MINOR;
} else if (IS_BROXTON(dev_priv)) {
-   fw_path = I915_BXT_GUC_UCODE;
+   guc->fw.path = I915_BXT_GUC_UCODE;
guc->fw.major_ver_wanted = BXT_FW_MAJOR;
guc->fw.minor_ver_wanted = BXT_FW_MINOR;
} else if (IS_KABYLAKE(dev_priv)) {
-   fw_path = I915_KBL_GUC_UCODE;
+   guc->fw.path = I915_KBL_GUC_UCODE;
guc->fw.major_ver_wanted = KBL_FW_MAJOR;
guc->fw.minor_ver_wanted = KBL_FW_MINOR;
} else {
-   fw_path = "";   /* unknown device */
+   WARN(1, "No GuC firmware known for platform with GuC!\n");
+   i915.enable_guc_loading = 0;
+   return;
}
 
-   guc->fw.path = fw_path;
-   guc->fw.fetch_status = INTEL_UC_FIRMWARE_NONE;
-   guc->fw.load_status = INTEL_UC_FIRMWARE_NONE;
-
-   if (fw_path == NULL)
-   return;
-   if (*fw_path == '\0')
-   return;
-
-   guc->fw.fetch_status = INTEL_UC_FIRMWARE_PENDING;
-   DRM_DEBUG_DRIVER("GuC firmware pending, path %s\n", fw_path);
guc->fw.fetch(dev_priv, >fw);
-   /* status must now be FAIL or SUCCESS */
 }
 
 /**
diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
index 7527988..c94e22f 100644
--- a/drivers/gpu/drm/i915/intel_huc.c
+++ b/drivers/gpu/drm/i915/intel_huc.c
@@ -155,37 +155,29 @@ static int huc_ucode_xfer(struct drm_i915_private 
*dev_priv)
 void intel_huc_fetch_fw(struct intel_huc *huc)
 {
struct drm_i915_private *dev_priv = huc_to_i915(huc);
-   const char *fw_path = NULL;
 
huc->fw.path = NULL;
huc->fw.fetch_status = INTEL_UC_FIRMWARE_NONE;
huc->fw.load_status = INTEL_UC_FIRMWARE_NONE;
huc->fw.fw = INTEL_UC_FW_TYPE_HUC;
 
-   if (!HAS_HUC_UCODE(dev_priv))
-   return;
-
if (IS_SKYLAKE(dev_priv)) {
-   fw_path = I915_SKL_HUC_UCODE;
+   huc->fw.path = I915_SKL_HUC_UCODE;
huc->fw.major_ver_wanted = SKL_HUC_FW_MAJOR;
huc->fw.minor_ver_wanted = SKL_HUC_FW_MINOR;
} else if 

[Intel-gfx] [PATCH 5/8] drm/i915/uc: Make intel_uc_fw_fetch() static

[Arkadiusz Hiler]

intel_uc_fw_fetch() is confusingly named in the light of recent changes.

It's also in the worng place - 'guc_loader.h' - it's used for both guc
and huc, which was reflected in name, but not it's location, so let's
move it to 'intel_uc.c'.

We can make a intel_uc_fw callback out of it, to avoid leaking it
outside `intel_uc.c`

Cc: Joonas Lahtinen 
Cc: Michal Wajdeczko 
Cc: Michal Winiarski 
Signed-off-by: Arkadiusz Hiler 
---
 drivers/gpu/drm/i915/intel_guc_loader.c | 137 +--
 drivers/gpu/drm/i915/intel_huc.c|   2 +-
 drivers/gpu/drm/i915/intel_uc.c | 141 
 drivers/gpu/drm/i915/intel_uc.h |   4 +-
 4 files changed, 145 insertions(+), 139 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c 
b/drivers/gpu/drm/i915/intel_guc_loader.c
index 753aeef..110dfd1 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -26,7 +26,6 @@
  *Dave Gordon 
  *Alex Dai 
  */
-#include 
 #include "i915_drv.h"
 #include "intel_uc.h"
 
@@ -587,140 +586,6 @@ int intel_guc_init_hw(struct drm_i915_private *dev_priv)
return ret;
 }
 
-void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
-struct intel_uc_fw *uc_fw)
-{
-   struct pci_dev *pdev = dev_priv->drm.pdev;
-   struct drm_i915_gem_object *obj;
-   const struct firmware *fw = NULL;
-   struct uc_css_header *css;
-   size_t size;
-   int err;
-
-   DRM_DEBUG_DRIVER("before requesting firmware: uC fw fetch status %s\n",
-   intel_uc_fw_status_repr(uc_fw->fetch_status));
-
-   err = request_firmware(, uc_fw->path, >dev);
-   if (err)
-   goto fail;
-   if (!fw)
-   goto fail;
-
-   DRM_DEBUG_DRIVER("fetch uC fw from %s succeeded, fw %p\n",
-   uc_fw->path, fw);
-
-   /* Check the size of the blob before examining buffer contents */
-   if (fw->size < sizeof(struct uc_css_header)) {
-   DRM_NOTE("Firmware header is missing\n");
-   goto fail;
-   }
-
-   css = (struct uc_css_header *)fw->data;
-
-   /* Firmware bits always start from header */
-   uc_fw->header_offset = 0;
-   uc_fw->header_size = (css->header_size_dw - css->modulus_size_dw -
-   css->key_size_dw - css->exponent_size_dw) * sizeof(u32);
-
-   if (uc_fw->header_size != sizeof(struct uc_css_header)) {
-   DRM_NOTE("CSS header definition mismatch\n");
-   goto fail;
-   }
-
-   /* then, uCode */
-   uc_fw->ucode_offset = uc_fw->header_offset + uc_fw->header_size;
-   uc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32);
-
-   /* now RSA */
-   if (css->key_size_dw != UOS_RSA_SCRATCH_MAX_COUNT) {
-   DRM_NOTE("RSA key size is bad\n");
-   goto fail;
-   }
-   uc_fw->rsa_offset = uc_fw->ucode_offset + uc_fw->ucode_size;
-   uc_fw->rsa_size = css->key_size_dw * sizeof(u32);
-
-   /* At least, it should have header, uCode and RSA. Size of all three. */
-   size = uc_fw->header_size + uc_fw->ucode_size + uc_fw->rsa_size;
-   if (fw->size < size) {
-   DRM_NOTE("Missing firmware components\n");
-   goto fail;
-   }
-
-   /*
-* The GuC firmware image has the version number embedded at a 
well-known
-* offset within the firmware blob; note that major / minor version are
-* TWO bytes each (i.e. u16), although all pointers and offsets are 
defined
-* in terms of bytes (u8).
-*/
-   switch (uc_fw->fw) {
-   case INTEL_UC_FW_TYPE_GUC:
-   /* Header and uCode will be loaded to WOPCM. Size of the two. */
-   size = uc_fw->header_size + uc_fw->ucode_size;
-
-   /* Top 32k of WOPCM is reserved (8K stack + 24k RC6 context). */
-   if (size > intel_guc_wopcm_size(dev_priv)) {
-   DRM_ERROR("Firmware is too large to fit in WOPCM\n");
-   goto fail;
-   }
-   uc_fw->major_ver_found = css->guc.sw_version >> 16;
-   uc_fw->minor_ver_found = css->guc.sw_version & 0x;
-   break;
-
-   case INTEL_UC_FW_TYPE_HUC:
-   uc_fw->major_ver_found = css->huc.sw_version >> 16;
-   uc_fw->minor_ver_found = css->huc.sw_version & 0x;
-   break;
-
-   default:
-   DRM_ERROR("Unknown firmware type %d\n", uc_fw->fw);
-   err = -ENOEXEC;
-   goto fail;
-   }
-
-   if (uc_fw->major_ver_found != uc_fw->major_ver_wanted ||
-   uc_fw->minor_ver_found < uc_fw->minor_ver_wanted) {
-   DRM_NOTE("uC firmware version %d.%d,