[Intel-gfx] ✗ Fi.CI.BAT: failure for Gen8+ engine-reset

[Patchwork]

== Series Details ==

Series: Gen8+ engine-reset
URL   : https://patchwork.freedesktop.org/series/21868/
State : failure

== Summary ==

Series 21868v1 Gen8+ engine-reset
https://patchwork.freedesktop.org/api/1.0/series/21868/revisions/1/mbox/

Test pm_rpm:
Subgroup basic-rte:
pass   -> DMESG-WARN (fi-skl-6770hq)
Test pm_rps:
Subgroup basic-api:
pass   -> INCOMPLETE (fi-skl-6770hq)

fi-bdw-5557u total:278  pass:267  dwarn:0   dfail:0   fail:0   skip:11  
time: 471s
fi-bdw-gvtdvmtotal:278  pass:256  dwarn:8   dfail:0   fail:0   skip:14  
time: 469s
fi-bsw-n3050 total:278  pass:239  dwarn:0   dfail:0   fail:0   skip:39  
time: 585s
fi-bxt-j4205 total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19  
time: 537s
fi-bxt-t5700 total:278  pass:258  dwarn:0   dfail:0   fail:0   skip:20  
time: 574s
fi-byt-j1900 total:278  pass:251  dwarn:0   dfail:0   fail:0   skip:27  
time: 505s
fi-hsw-4770  total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time: 439s
fi-hsw-4770r total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time: 437s
fi-ilk-650   total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50  
time: 444s
fi-ivb-3520m total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time: 513s
fi-ivb-3770  total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time: 491s
fi-kbl-7500u total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time: 481s
fi-skl-6260u total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time: 486s
fi-skl-6700hqtotal:278  pass:261  dwarn:0   dfail:0   fail:0   skip:17  
time: 600s
fi-skl-6700k total:278  pass:256  dwarn:4   dfail:0   fail:0   skip:18  
time: 494s
fi-skl-6770hqtotal:243  pass:232  dwarn:1   dfail:0   fail:0   skip:9   
time: 0s
fi-skl-gvtdvmtotal:278  pass:265  dwarn:0   dfail:0   fail:0   skip:13  
time: 469s
fi-snb-2520m total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  
time: 554s
fi-snb-2600  total:278  pass:249  dwarn:0   dfail:0   fail:0   skip:29  
time: 424s
fi-byt-n2820 failed to collect. IGT log at Patchwork_4300/fi-byt-n2820/igt.log

102397b5dbb1f68504739adefde2c28a5aba95b9 drm-tip: 2017y-03m-25d-00h-24m-58s UTC 
integration manifest
6dda863 drm/i915: Watchdog timeout: Export media reset count from GuC to debugfs
a71c802 drm/i915: Watchdog timeout: DRM kernel interface to set the timeout
8e10876 drm/i915: Watchdog timeout: Ringbuffer command emission for gen8+
a2167c8 drm/i915: Watchdog timeout: IRQ handler for gen8+
96e2ee6 drm/i915: Watchdog timeout: Pass GuC shared data structure during param 
load
5a60c42 drm/i915/guc: Add support for reset engine using GuC commands
6ed1757 drm/i915/guc: Provide register list to be saved/restored during engine 
reset
af217a8 drm/i915/selftests: reset engine self tests
d43b3eb drm/i915: Add engine reset count in get-reset-stats ioctl
dea8dca drm/i915/tdr: Enable Engine reset and recovery support
f872bd8 drm/i915/tdr: Export per-engine reset count info to debugfs
4d66882b1 drm/i915/tdr: Add engine reset count to error state
a3d1a331 drm/i915: Skip reset request if there is one already
42fdfd1 drm/i915/tdr: Add support for per engine reset recovery
1ce9821 drm/i915/tdr: Modify error handler for per engine hang recovery
15808ca drm/i915: Update i915.reset to handle engine resets
95bad53 drm/i915: Rename gen8_(un)request_engine_reset to 
gen8_(un)request_reset_engine
56350ec drm/i915: Fix stale comment about I915_RESET_IN_PROGRESS flag

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4300/
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[Intel-gfx] [PATCH v5 13/18] drm/i915/guc: Add support for reset engine using GuC commands

[Michel Thierry]

This patch adds per engine reset and recovery (TDR) support when GuC is
used to submit workloads to GPU.

In the case of i915 directly submission to ELSP, driver manages hang
detection, recovery and resubmission. With GuC submission these tasks
are shared between driver and GuC. i915 is still responsible for detecting
a hang, and when it does it only requests GuC to reset that Engine. GuC
internally manages acquiring forcewake and idling the engine before actually
resetting it.

Once the reset is successful, i915 takes over again and handles resubmission.
The scheduler in i915 knows which requests are pending so after resetting
a engine, pending workloads/requests are resubmitted again.

Signed-off-by: Arun Siluvery 
Signed-off-by: Jeff McGee 
Signed-off-by: Michel Thierry 
---
 drivers/gpu/drm/i915/i915_drv.c| 43 +-
 drivers/gpu/drm/i915/i915_drv.h|  1 +
 drivers/gpu/drm/i915/i915_guc_submission.c | 48 ++
 drivers/gpu/drm/i915/intel_guc_fwif.h  |  6 
 drivers/gpu/drm/i915/intel_lrc.c   |  5 ++--
 drivers/gpu/drm/i915/intel_uc.h|  1 +
 drivers/gpu/drm/i915/intel_uncore.c|  5 
 7 files changed, 88 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index a111b39bbc12..3da0e7146ff8 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1940,23 +1940,34 @@ int i915_reset_engine(struct intel_engine_cs *engine)
 */
i915_gem_reset_engine(engine);
 
-   /* forcing engine to idle */
-   ret = intel_request_reset_engine(engine);
-   if (ret) {
-   DRM_ERROR("Failed to disable %s\n", engine->name);
-   goto error;
-   }
+   if (!dev_priv->guc.execbuf_client) {
+   /* forcing engine to idle */
+   ret = intel_request_reset_engine(engine);
+   if (ret) {
+   DRM_ERROR("Failed to disable %s\n", engine->name);
+   goto error;
+   }
 
-   /* finally, reset engine */
-   ret = intel_gpu_reset(dev_priv, intel_engine_flag(engine));
-   if (ret) {
-   DRM_ERROR("Failed to reset %s, ret=%d\n", engine->name, ret);
+   /* finally, reset engine */
+   ret = intel_gpu_reset(dev_priv, intel_engine_flag(engine));
+   if (ret) {
+   DRM_ERROR("Failed to reset %s, ret=%d\n",
+ engine->name, ret);
+   intel_unrequest_reset_engine(engine);
+   goto error;
+   }
+
+   /* be sure the request reset bit gets cleared */
intel_unrequest_reset_engine(engine);
-   goto error;
-   }
 
-   /* be sure the request reset bit gets cleared */
-   intel_unrequest_reset_engine(engine);
+   } else {
+   ret = i915_guc_request_engine_reset(engine);
+   if (ret) {
+   DRM_ERROR("GuC failed to reset %s, ret=%d\n",
+ engine->name, ret);
+   goto error;
+   }
+   }
 
/* i915_gem_reset_prepare revoked the fences */
i915_gem_restore_fences(dev_priv);
@@ -1967,6 +1978,10 @@ int i915_reset_engine(struct intel_engine_cs *engine)
if (ret)
goto error;
 
+   /* for guc too */
+   if (dev_priv->guc.execbuf_client)
+   i915_guc_submission_reenable_engine(engine);
+
error->reset_engine_count[engine->id]++;
 
 wakeup:
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fbb4f200756a..d5c12ddd35b3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3048,6 +3048,7 @@ extern void i915_reset(struct drm_i915_private *dev_priv, 
u32 engine_mask);
 extern bool intel_has_reset_engine(struct drm_i915_private *dev_priv);
 extern int intel_request_reset_engine(struct intel_engine_cs *engine);
 extern void intel_unrequest_reset_engine(struct intel_engine_cs *engine);
+extern int i915_guc_request_engine_reset(struct intel_engine_cs *engine);
 extern int intel_guc_reset(struct drm_i915_private *dev_priv);
 extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
 extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 2445af96aa71..fc21ec733f93 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -1335,6 +1335,25 @@ void i915_guc_submission_disable(struct drm_i915_private 
*dev_priv)
guc->execbuf_client = NULL;
 }
 
+void i915_guc_submission_reenable_engine(struct intel_engine_cs *engine)
+{
+   

[Intel-gfx] [PATCH v5 07/18] drm/i915/tdr: Add engine reset count to error state

[Michel Thierry]

From: Arun Siluvery 

Driver maintains count of how many times a given engine is reset, useful to
capture this in error state also. It gives an idea of how engine is coping
up with the workloads it is executing before this error state.

A follow-up patch will provide this information in debugfs.

v2: s/engine_reset/reset_engine/ (Chris)
Define count as unsigned int (Tvrtko)

Cc: Chris Wilson 
Cc: Mika Kuoppala 
Signed-off-by: Arun Siluvery 
Signed-off-by: Michel Thierry 
---
 drivers/gpu/drm/i915/i915_drv.c   | 2 ++
 drivers/gpu/drm/i915/i915_drv.h   | 8 
 drivers/gpu/drm/i915/i915_gpu_error.c | 3 +++
 3 files changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9c7bdcf03c13..a111b39bbc12 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1967,6 +1967,8 @@ int i915_reset_engine(struct intel_engine_cs *engine)
if (ret)
goto error;
 
+   error->reset_engine_count[engine->id]++;
+
 wakeup:
enable_irq(dev_priv->drm.irq);
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 67201ecd98e5..fbb4f200756a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -999,6 +999,7 @@ struct i915_gpu_state {
enum intel_engine_hangcheck_action hangcheck_action;
struct i915_address_space *vm;
int num_requests;
+   u32 reset_count;
 
/* position of active request inside the ring */
u32 rq_head, rq_post, rq_tail;
@@ -1639,6 +1640,7 @@ struct i915_gpu_error {
 
/* if available, engine-specific reset is tried before full gpu reset */
u32 reset_engine_mask;
+   u32 reset_engine_count[I915_NUM_ENGINES];
 
/**
 * Waitqueue to signal when a hang is detected. Used to for waiters
@@ -3450,6 +3452,12 @@ static inline u32 i915_reset_count(struct i915_gpu_error 
*error)
return READ_ONCE(error->reset_count);
 }
 
+static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
+ struct intel_engine_cs *engine)
+{
+   return READ_ONCE(error->reset_engine_count[engine->id]);
+}
+
 int i915_gem_reset_prepare(struct drm_i915_private *dev_priv,
   unsigned int engine_mask);
 void i915_gem_reset(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 5099b3599c34..5d015bcc7484 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -463,6 +463,7 @@ static void error_print_engine(struct 
drm_i915_error_state_buf *m,
err_printf(m, "  hangcheck action timestamp: %lu, %u ms ago\n",
   ee->hangcheck_timestamp,
   jiffies_to_msecs(jiffies - ee->hangcheck_timestamp));
+   err_printf(m, "  engine reset count: %u\n", ee->reset_count);
 
error_print_request(m, "  ELSP[0]: ", >execlist[0]);
error_print_request(m, "  ELSP[1]: ", >execlist[1]);
@@ -1236,6 +1237,8 @@ static void error_record_engine_registers(struct 
i915_gpu_state *error,
ee->hangcheck_timestamp = engine->hangcheck.action_timestamp;
ee->hangcheck_action = engine->hangcheck.action;
ee->hangcheck_stalled = engine->hangcheck.stalled;
+   ee->reset_count = i915_reset_engine_count(_priv->gpu_error,
+ engine);
 
if (USES_PPGTT(dev_priv)) {
int i;
-- 
2.11.0

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[Intel-gfx] [PATCH v5 11/18] drm/i915/selftests: reset engine self tests

[Michel Thierry]

Check that we can reset specific engines, also check the fallback to
full reset if something didn't work.

Signed-off-by: Michel Thierry 
---
 drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 144 +++
 1 file changed, 144 insertions(+)

diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c 
b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
index 76d5f78c1724..91b78e638494 100644
--- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
@@ -323,6 +323,56 @@ static int igt_global_reset(void *arg)
return err;
 }
 
+static int igt_reset_engine(void *arg)
+{
+   struct drm_i915_private *i915 = arg;
+   struct intel_engine_cs *engine;
+   enum intel_engine_id id;
+   unsigned int reset_count, reset_engine_count;
+   int err = 0;
+
+   /* Check that we can issue a global GPU and engine reset */
+
+   if (!intel_has_gpu_reset(i915))
+   return 0;
+
+   if (!intel_has_reset_engine(i915))
+   return 0;
+
+   set_bit(I915_RESET_BACKOFF, >gpu_error.flags);
+   mutex_lock(>drm.struct_mutex);
+
+   for_each_engine(engine, i915, id) {
+   reset_count = i915_reset_count(>gpu_error);
+   reset_engine_count = i915_reset_engine_count(>gpu_error,
+engine);
+
+   set_bit(I915_RESET_HANDOFF, >gpu_error.flags);
+   i915_reset(i915, intel_engine_flag(engine));
+   GEM_BUG_ON(test_bit(I915_RESET_HANDOFF, 
>gpu_error.flags));
+
+   if (i915_reset_count(>gpu_error) != reset_count) {
+   pr_err("Full GPU reset recorded! (engine reset 
expected)\n");
+   err = -EINVAL;
+   break;
+   }
+
+   if (i915_reset_engine_count(>gpu_error, engine) ==
+   reset_engine_count) {
+   pr_err("No %s engine reset recorded!\n", engine->name);
+   err = -EINVAL;
+   break;
+   }
+   }
+   mutex_unlock(>drm.struct_mutex);
+
+   clear_bit(I915_RESET_BACKOFF, >gpu_error.flags);
+   if (i915_terminally_wedged(>gpu_error))
+   err = -EIO;
+
+   return err;
+}
+
 static u32 fake_hangcheck(struct drm_i915_gem_request *rq)
 {
u32 reset_count;
@@ -527,13 +577,107 @@ static int igt_reset_queue(void *arg)
return err;
 }
 
+static int igt_render_engine_reset_fallback(void *arg)
+{
+   struct drm_i915_private *i915 = arg;
+   struct intel_engine_cs *engine = i915->engine[RCS];
+   struct hang h;
+   struct drm_i915_gem_request *rq;
+   unsigned int reset_count, reset_engine_count;
+   int err = 0;
+
+   /* Check that we can issue a global GPU and engine reset */
+
+   if (!intel_has_gpu_reset(i915))
+   return 0;
+
+   if (!intel_has_reset_engine(i915))
+   return 0;
+
+   set_bit(I915_RESET_BACKOFF, >gpu_error.flags);
+   mutex_lock(>drm.struct_mutex);
+
+   err = hang_init(, i915);
+   if (err)
+   goto unlock;
+
+   rq = hang_create_request(, engine, i915->kernel_context);
+   if (IS_ERR(rq)) {
+   err = PTR_ERR(rq);
+   goto fini;
+   }
+
+   i915_gem_request_get(rq);
+   __i915_add_request(rq, true);
+
+   /* make reset engine fail */
+   rq->fence.error = -EIO;
+
+   if (!wait_for_hang(, rq)) {
+   pr_err("Failed to start request %x\n", rq->fence.seqno);
+   err = -EIO;
+   goto fini;
+   }
+
+   reset_engine_count = i915_reset_engine_count(>gpu_error, engine);
+   reset_count = fake_hangcheck(rq);
+
+   i915_reset(i915, intel_engine_flag(engine));
+   GEM_BUG_ON(test_bit(I915_RESET_HANDOFF, >gpu_error.flags));
+
+   if (i915_reset_engine_count(>gpu_error, engine) !=
+   reset_engine_count) {
+   pr_err("render engine reset recorded! (full reset expected)\n");
+   err = -EINVAL;
+   goto fini;
+   }
+
+   if (i915_reset_count(>gpu_error) == reset_count) {
+   pr_err("No full GPU reset recorded!\n");
+   err = -EINVAL;
+   goto fini;
+   }
+
+   /*
+* by using fence.error = -EIO, full reset sets the wedged flag, do one
+* more full reset to re-enable the hw.
+*/
+   if (i915_terminally_wedged(>gpu_error)) {
+   rq->fence.error = 0;
+
+   set_bit(I915_RESET_HANDOFF, >gpu_error.flags);
+   i915_reset(i915, ALL_ENGINES);
+   GEM_BUG_ON(test_bit(I915_RESET_HANDOFF,
+   >gpu_error.flags));
+
+   if (i915_reset_count(>gpu_error) == reset_count) {
+   pr_err("No full GPU reset recorded!\n");
+ 

[Intel-gfx] [PATCH v5 00/18] Gen8+ engine-reset

[Michel Thierry]

These patches add the reset-engine feature from Gen8. This is also
referred to as Timeout detection and recovery (TDR). This complements to
the full gpu reset feature available in i915 but it only allows to reset a
particular engine instead of all engines thus providing a light weight
engine reset and recovery mechanism.

Thanks to recent changes merged, this implementation is now not only for
execlists, but for GuC based submission too; it is still limited from
Gen8 onwards. I have also included the changes for watchdog timeout
detection. The GuC related patches can be seen as RFC.

Timeout detection relies on the existing hangcheck, which remains the same;
main changes are to the recovery mechanism. Once we detect a hang on a
particular engine we identify the request that caused the hang, skip the
request and adjust head pointers to allow the execution to proceed
normally. After some cleanup, submissions are restarted to process
remaining work queued to that engine.

If engine reset fails to recover engine correctly then we fallback to full
gpu reset.

We can argue about the effectiveness of reset-engine vs full reset when
more than one ring is hung, but the benefits of just resetting one engine
are reduced when the driver has to do it multiple times.

Note - with guc submission enabled, Fi.CI.BAT is reporting a regression
in gem_ringfill@basic-default-hang. But local testing show it can only be
reproducible while running IGT v1.7; IGT v1.8 or newer don't show the
problem.

v2: ELSP queue request tracking and reset path changes to handle incomplete
requests during reset. Thanks to Chris Wilson for providing these patches.

v3: Let the waiter keep handling the full gpu reset if it already has the
lock; point out that GuC submission needs a different method to restart
workloads after the engine reset completes.

v4: Handle reset as 2 level resets, by first going to engine only and fall
backing to full/chip reset as needed, i.e. reset_engine will need the
struct_mutex.

v5: Rebased after reset flag split in 2, add GuC support, include watchdog
detection patches, addressing comments from prev RFC.

Cc: Chris Wilson 
Cc: Mika Kuoppala 

Arun Siluvery (7):
  drm/i915: Update i915.reset to handle engine resets
  drm/i915/tdr: Modify error handler for per engine hang recovery
  drm/i915/tdr: Add support for per engine reset recovery
  drm/i915/tdr: Add engine reset count to error state
  drm/i915/tdr: Export per-engine reset count info to debugfs
  drm/i915/tdr: Enable Engine reset and recovery support
  drm/i915/guc: Provide register list to be saved/restored during engine
reset

Michel Thierry (10):
  drm/i915: Fix stale comment about I915_RESET_IN_PROGRESS flag
  drm/i915: Rename gen8_(un)request_engine_reset to
gen8_(un)request_reset_engine
  drm/i915: Add engine reset count in get-reset-stats ioctl
  drm/i915/selftests: reset engine self tests
  drm/i915/guc: Add support for reset engine using GuC commands
  drm/i915: Watchdog timeout: Pass GuC shared data structure during
param load
  drm/i915: Watchdog timeout: IRQ handler for gen8+
  drm/i915: Watchdog timeout: Ringbuffer command emission for gen8+
  drm/i915: Watchdog timeout: DRM kernel interface to set the timeout
  drm/i915: Watchdog timeout: Export media reset count from GuC to
debugfs

Mika Kuoppala (1):
  drm/i915: Skip reset request if there is one already

 drivers/gpu/drm/i915/i915_debugfs.c  |  49 +++
 drivers/gpu/drm/i915/i915_drv.c  | 150 +-
 drivers/gpu/drm/i915/i915_drv.h  |  34 -
 drivers/gpu/drm/i915/i915_gem.c  |  16 ++-
 drivers/gpu/drm/i915/i915_gem_context.c  |  92 +-
 drivers/gpu/drm/i915/i915_gem_context.h  |  24 
 drivers/gpu/drm/i915/i915_gem_request.c  |   5 +-
 drivers/gpu/drm/i915/i915_gpu_error.c|  14 +-
 drivers/gpu/drm/i915/i915_guc_submission.c   |  98 +-
 drivers/gpu/drm/i915/i915_irq.c  |  32 -
 drivers/gpu/drm/i915/i915_params.c   |   6 +-
 drivers/gpu/drm/i915/i915_params.h   |   2 +-
 drivers/gpu/drm/i915/i915_pci.c  |   5 +-
 drivers/gpu/drm/i915/i915_reg.h  |   6 +
 drivers/gpu/drm/i915/intel_guc_fwif.h|  26 +++-
 drivers/gpu/drm/i915/intel_guc_loader.c  |   8 ++
 drivers/gpu/drm/i915/intel_hangcheck.c   |  13 +-
 drivers/gpu/drm/i915/intel_lrc.c | 155 ++-
 drivers/gpu/drm/i915/intel_ringbuffer.h  |  24 
 drivers/gpu/drm/i915/intel_uc.h  |   1 +
 drivers/gpu/drm/i915/intel_uncore.c  |  43 ++-
 drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 148 +-
 include/uapi/drm/i915_drm.h  |   7 +-
 23 files changed, 906 insertions(+), 52 deletions(-)

-- 
2.11.0

[Intel-gfx] [PATCH v5 01/18] drm/i915: Fix stale comment about I915_RESET_IN_PROGRESS flag

[Michel Thierry]

It has been replaced by I915_RESET_BACKOFF / I915_RESET_HANDOFF.

Signed-off-by: Michel Thierry 
---
 drivers/gpu/drm/i915/i915_drv.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e8250bb79d12..6f19f5467f74 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1588,7 +1588,7 @@ struct i915_gpu_error {
 *
 * This is a counter which gets incremented when reset is triggered,
 *
-* Before the reset commences, the I915_RESET_IN_PROGRESS bit is set
+* Before the reset commences, the I915_RESET_BACKOFF bit is set
 * meaning that any waiters holding onto the struct_mutex should
 * relinquish the lock immediately in order for the reset to start.
 *
-- 
2.11.0

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[Intel-gfx] [PATCH v5 03/18] drm/i915: Update i915.reset to handle engine resets

[Michel Thierry]

From: Arun Siluvery 

In preparation for engine reset work update this parameter to handle more
than one type of reset. Default at the moment is still full gpu reset.

Cc: Chris Wilson 
Cc: Mika Kuoppala 
Signed-off-by: Arun Siluvery 
Signed-off-by: Michel Thierry 
---
 drivers/gpu/drm/i915/i915_params.c | 6 +++---
 drivers/gpu/drm/i915/i915_params.h | 2 +-
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index b6a7e363d076..045cadb77285 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -46,7 +46,7 @@ struct i915_params i915 __read_mostly = {
.prefault_disable = 0,
.load_detect_test = 0,
.force_reset_modeset_test = 0,
-   .reset = true,
+   .reset = 1,
.error_capture = true,
.invert_brightness = 0,
.disable_display = 0,
@@ -115,8 +115,8 @@ MODULE_PARM_DESC(vbt_sdvo_panel_type,
"Override/Ignore selection of SDVO panel mode in the VBT "
"(-2=ignore, -1=auto [default], index in VBT BIOS table)");
 
-module_param_named_unsafe(reset, i915.reset, bool, 0600);
-MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
+module_param_named_unsafe(reset, i915.reset, int, 0600);
+MODULE_PARM_DESC(reset, "Attempt GPU resets (0=disabled, 1=full gpu reset 
[default], 2=engine reset)");
 
 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
 module_param_named(error_capture, i915.error_capture, bool, 0600);
diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index 34148cc8637c..febbfdbd30bd 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -51,6 +51,7 @@
func(int, use_mmio_flip); \
func(int, mmio_debug); \
func(int, edp_vswing); \
+   func(int, reset); \
func(unsigned int, inject_load_failure); \
/* leave bools at the end to not create holes */ \
func(bool, alpha_support); \
@@ -60,7 +61,6 @@
func(bool, prefault_disable); \
func(bool, load_detect_test); \
func(bool, force_reset_modeset_test); \
-   func(bool, reset); \
func(bool, error_capture); \
func(bool, disable_display); \
func(bool, verbose_state_checks); \
-- 
2.11.0

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[Intel-gfx] [PATCH v5 16/18] drm/i915: Watchdog timeout: Ringbuffer command emission for gen8+

[Michel Thierry]

Emit the required commands into the ring buffer for starting and
stopping the watchdog timer before/after batch buffer start during
batch buffer submission.

v2: Support watchdog threshold per context engine, merge lri commands,
and move watchdog commands emission to emit_bb_start. Request space of
combined start_watchdog, bb_start and stop_watchdog to avoid any error
after emitting bb_start.

Signed-off-by: Tomas Elf 
Signed-off-by: Ian Lister 
Signed-off-by: Arun Siluvery 
Signed-off-by: Michel Thierry 
---
 drivers/gpu/drm/i915/i915_gem_context.h |  4 ++
 drivers/gpu/drm/i915/intel_lrc.c| 86 -
 drivers/gpu/drm/i915/intel_ringbuffer.h |  4 ++
 3 files changed, 92 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.h 
b/drivers/gpu/drm/i915/i915_gem_context.h
index 4af2ab94558b..88700bdbb4e1 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/i915_gem_context.h
@@ -150,6 +150,10 @@ struct i915_gem_context {
u32 *lrc_reg_state;
u64 lrc_desc;
int pin_count;
+   /** watchdog_threshold: hw watchdog threshold value,
+* in clock counts
+*/
+   u32 watchdog_threshold;
bool initialised;
} engine[I915_NUM_ENGINES];
 
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 73f8fbdcf1fb..2736f642dc76 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1319,6 +1319,8 @@ static int gen8_emit_bb_start(struct drm_i915_gem_request 
*req,
  const unsigned int flags)
 {
u32 *cs;
+   u32 num_dwords;
+   bool watchdog_running = false;
int ret;
 
/* Don't rely in hw updating PDPs, specially in lite-restore.
@@ -1338,10 +1340,29 @@ static int gen8_emit_bb_start(struct 
drm_i915_gem_request *req,
req->ctx->ppgtt->pd_dirty_rings &= 
~intel_engine_flag(req->engine);
}
 
-   cs = intel_ring_begin(req, 4);
+   /* bb_start only */
+   num_dwords = 4;
+
+   /* check if watchdog will be required */
+   if (req->ctx->engine[req->engine->id].watchdog_threshold != 0) {
+   if (!req->engine->emit_start_watchdog ||
+   !req->engine->emit_stop_watchdog)
+   return -EINVAL;
+
+   /* start_watchdog (6) + bb_start (4) + stop_watchdog (4) */
+   num_dwords += 10;
+   watchdog_running = true;
+   }
+
+   cs = intel_ring_begin(req, num_dwords);
if (IS_ERR(cs))
return PTR_ERR(cs);
 
+   if (watchdog_running) {
+   /* Start watchdog timer */
+   cs = req->engine->emit_start_watchdog(req, cs);
+   }
+
/* FIXME(BDW): Address space and security selectors. */
*cs++ = MI_BATCH_BUFFER_START_GEN8 |
(flags & I915_DISPATCH_SECURE ? 0 : BIT(8)) |
@@ -1349,8 +1370,13 @@ static int gen8_emit_bb_start(struct 
drm_i915_gem_request *req,
*cs++ = lower_32_bits(offset);
*cs++ = upper_32_bits(offset);
*cs++ = MI_NOOP;
-   intel_ring_advance(req, cs);
 
+   if (watchdog_running) {
+   /* Cancel watchdog timer */
+   cs = req->engine->emit_stop_watchdog(req, cs);
+   }
+
+   intel_ring_advance(req, cs);
return 0;
 }
 
@@ -1512,6 +1538,54 @@ static void gen8_watchdog_irq_handler(unsigned long data)
intel_uncore_forcewake_put(dev_priv, engine->fw_domains);
 }
 
+static u32 *gen8_emit_start_watchdog(struct drm_i915_gem_request *req, u32 *cs)
+{
+   struct intel_engine_cs *engine = req->engine;
+   struct i915_gem_context *ctx = req->ctx;
+   struct intel_context *ce = >engine[engine->id];
+
+   /* XXX: no watchdog support in BCS engine */
+   GEM_BUG_ON(engine->id == BCS);
+
+   /*
+* watchdog register must never be programmed to zero. This would
+* cause the watchdog counter to exceed and not allow the engine to
+* go into IDLE state
+*/
+   GEM_BUG_ON(ce->watchdog_threshold == 0);
+
+   /* Set counter period */
+   *cs++ = MI_LOAD_REGISTER_IMM(2);
+   *cs++ = i915_mmio_reg_offset(RING_THRESH(engine->mmio_base));
+   *cs++ = ce->watchdog_threshold;
+   /* Start counter */
+   *cs++ = i915_mmio_reg_offset(RING_CNTR(engine->mmio_base));
+   *cs++ = GEN8_WATCHDOG_ENABLE;
+   *cs++ = MI_NOOP;
+
+   return cs;
+}
+
+static u32 *gen8_emit_stop_watchdog(struct drm_i915_gem_request *req, u32 *cs)
+{
+   struct intel_engine_cs *engine = req->engine;
+
+   /* XXX: no watchdog support in BCS engine */
+   GEM_BUG_ON(engine->id == BCS);
+
+   *cs++ = MI_LOAD_REGISTER_IMM(2);
+   *cs++ = 

[Intel-gfx] [PATCH v5 17/18] drm/i915: Watchdog timeout: DRM kernel interface to set the timeout

[Michel Thierry]

Final enablement patch for GPU hang detection using watchdog timeout.
Using the gem_context_setparam ioctl, users can specify the desired
timeout value in microseconds, and the driver will do the conversion to
'timestamps'.

The recommended default watchdog threshold for video engines is 6 us,
since this has been _empirically determined_ to be a good compromise for
low-latency requirements and low rate of false positives. The default
register value is ~106000us and the theoretical max value (all 1s) is
353 seconds.

v2: Fixed get api to return values in microseconds. Threshold updated to
be per context engine. Check for u32 overflow. Capture ctx threshold
value in error state.

Signed-off-by: Tomas Elf 
Signed-off-by: Arun Siluvery 
Signed-off-by: Michel Thierry 
---
 drivers/gpu/drm/i915/i915_drv.h |  1 +
 drivers/gpu/drm/i915/i915_gem_context.c | 78 +
 drivers/gpu/drm/i915/i915_gem_context.h | 20 +
 drivers/gpu/drm/i915/i915_gpu_error.c   | 11 +++--
 drivers/gpu/drm/i915/intel_lrc.c|  2 +-
 include/uapi/drm/i915_drm.h |  1 +
 6 files changed, 108 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b43c37a911bb..1741584d858f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1039,6 +1039,7 @@ struct i915_gpu_state {
int ban_score;
int active;
int guilty;
+   int watchdog_threshold;
} context;
 
struct drm_i915_error_object {
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index edbed85a1c88..f5c126c0c681 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -422,6 +422,78 @@ i915_gem_context_create_gvt(struct drm_device *dev)
return ctx;
 }
 
+/* Return the timer count threshold in microseconds. */
+int i915_gem_context_get_watchdog(struct i915_gem_context *ctx,
+ struct drm_i915_gem_context_param *args)
+{
+   struct drm_i915_private *dev_priv = ctx->i915;
+   struct intel_engine_cs *engine;
+   enum intel_engine_id id;
+   u32 threshold_in_us[I915_NUM_ENGINES];
+
+   if (!dev_priv->engine[VCS]->emit_start_watchdog)
+   return -ENODEV;
+
+   for_each_engine(engine, dev_priv, id) {
+   struct intel_context *ce = >engine[id];
+
+   threshold_in_us[id] = watchdog_to_us(ce->watchdog_threshold);
+   }
+
+   mutex_unlock(_priv->drm.struct_mutex);
+   if (__copy_to_user(u64_to_user_ptr(args->value),
+  _in_us,
+  sizeof(threshold_in_us))) {
+   mutex_lock(_priv->drm.struct_mutex);
+   return -EFAULT;
+   }
+   mutex_lock(_priv->drm.struct_mutex);
+   args->size = sizeof(threshold_in_us);
+
+   return 0;
+}
+
+/*
+ * Based on time out value in microseconds (us) calculate
+ * timer count thresholds needed based on core frequency.
+ * Watchdog can be disabled by setting it to 0.
+ */
+int i915_gem_context_set_watchdog(struct i915_gem_context *ctx,
+ struct drm_i915_gem_context_param *args)
+{
+   struct drm_i915_private *dev_priv = ctx->i915;
+   struct intel_engine_cs *engine;
+   enum intel_engine_id id;
+   u32 threshold_in_us[I915_NUM_ENGINES];
+
+   if (!dev_priv->engine[VCS]->emit_start_watchdog)
+   return -ENODEV;
+   else if (args->size < sizeof(threshold_in_us))
+   return -EINVAL;
+
+   mutex_unlock(_priv->drm.struct_mutex);
+   if (copy_from_user(_in_us,
+  u64_to_user_ptr(args->value),
+  sizeof(threshold_in_us))) {
+   mutex_lock(_priv->drm.struct_mutex);
+   return -EFAULT;
+   }
+   mutex_lock(_priv->drm.struct_mutex);
+
+   /* not supported in blitter engine */
+   if (threshold_in_us[BCS] != 0)
+   return -EINVAL;
+
+   for_each_engine(engine, dev_priv, id) {
+   struct intel_context *ce = >engine[id];
+
+   ce->watchdog_threshold =
+   watchdog_to_clock_counts((u64)threshold_in_us[id]);
+   }
+
+   return 0;
+}
+
 int i915_gem_context_init(struct drm_i915_private *dev_priv)
 {
struct i915_gem_context *ctx;
@@ -1061,6 +1133,9 @@ int i915_gem_context_getparam_ioctl(struct drm_device 
*dev, void *data,
case I915_CONTEXT_PARAM_BANNABLE:
args->value = i915_gem_context_is_bannable(ctx);
break;
+   case I915_CONTEXT_PARAM_WATCHDOG:
+   ret = i915_gem_context_get_watchdog(ctx, args);
+   break;
default:
ret 

[Intel-gfx] [PATCH v5 05/18] drm/i915/tdr: Add support for per engine reset recovery

[Michel Thierry]

From: Arun Siluvery 

This change implements support for per-engine reset as an initial, less
intrusive hang recovery option to be attempted before falling back to the
legacy full GPU reset recovery mode if necessary. This is only supported
from Gen8 onwards.

Hangchecker determines which engines are hung and invokes error handler to
recover from it. Error handler schedules recovery for each of those engines
that are hung. The recovery procedure is as follows,
 - identifies the request that caused the hang and it is dropped
 - force engine to idle: this is done by issuing a reset request
 - reset and re-init engine
 - restart submissions to the engine

If engine reset fails then we fall back to heavy weight full gpu reset
which resets all engines and reinitiazes complete state of HW and SW.

v2: Rebase.
v3: s/*engine_reset*/*reset_engine*/; freeze engine and irqs before
calling i915_gem_reset_engine (Chris).
v4: Rebase, modify i915_gem_reset_prepare to use a ring mask and
reuse the function for reset_engine.

Cc: Chris Wilson 
Cc: Mika Kuoppala 
Signed-off-by: Tomas Elf 
Signed-off-by: Arun Siluvery 
Signed-off-by: Michel Thierry 
---
 drivers/gpu/drm/i915/i915_drv.c | 88 +++--
 drivers/gpu/drm/i915/i915_drv.h | 11 +++--
 drivers/gpu/drm/i915/i915_gem.c | 16 +++---
 drivers/gpu/drm/i915/i915_gem_request.c |  2 +-
 drivers/gpu/drm/i915/intel_uncore.c | 20 
 5 files changed, 122 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index c7eb43deb33e..9c7bdcf03c13 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1831,7 +1831,7 @@ void i915_reset_chip(struct drm_i915_private *dev_priv)
 
pr_notice("drm/i915: Resetting chip after gpu hang\n");
disable_irq(dev_priv->drm.irq);
-   ret = i915_gem_reset_prepare(dev_priv);
+   ret = i915_gem_reset_prepare(dev_priv, ALL_ENGINES);
if (ret) {
DRM_ERROR("GPU recovery failed\n");
intel_gpu_reset(dev_priv, ALL_ENGINES);
@@ -1873,7 +1873,7 @@ void i915_reset_chip(struct drm_i915_private *dev_priv)
i915_queue_hangcheck(dev_priv);
 
 finish:
-   i915_gem_reset_finish(dev_priv);
+   i915_gem_reset_finish(dev_priv, ALL_ENGINES);
enable_irq(dev_priv->drm.irq);
 
 wakeup:
@@ -1892,11 +1892,91 @@ void i915_reset_chip(struct drm_i915_private *dev_priv)
  *
  * Reset a specific GPU engine. Useful if a hang is detected.
  * Returns zero on successful reset or otherwise an error code.
+ *
+ * Caller must hold the struct_mutex.
+ *
+ * Procedure is:
+ *  - identifies the request that caused the hang and it is dropped
+ *  - force engine to idle: this is done by issuing a reset request
+ *  - reset engine
+ *  - restart submissions to the engine
  */
 int i915_reset_engine(struct intel_engine_cs *engine)
 {
-   /* FIXME: replace me with engine reset sequence */
-   return -ENODEV;
+   int ret;
+   struct drm_i915_private *dev_priv = engine->i915;
+   struct i915_gpu_error *error = _priv->gpu_error;
+
+   lockdep_assert_held(_priv->drm.struct_mutex);
+   GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, >flags));
+
+   if (!test_and_clear_bit(I915_RESET_HANDOFF, >flags))
+   return 0;
+
+   DRM_DEBUG_DRIVER("resetting %s\n", engine->name);
+
+   /*
+* We need to first idle the engine by issuing a reset request,
+* then perform soft reset and re-initialize hw state, for all of
+* this GT power need to be awake so ensure it does throughout the
+* process
+*/
+   intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+
+   disable_irq(dev_priv->drm.irq);
+   ret = i915_gem_reset_prepare(dev_priv, intel_engine_flag(engine));
+   if (ret) {
+   DRM_ERROR("Previous reset failed - promote to full reset\n");
+   goto error;
+   }
+
+   if (dev_priv->gt.active_requests)
+   engine_retire_requests(engine);
+
+   /*
+* the request that caused the hang is stuck on elsp, identify the
+* active request and drop it, adjust head to skip the offending
+* request to resume executing remaining requests in the queue.
+*/
+   i915_gem_reset_engine(engine);
+
+   /* forcing engine to idle */
+   ret = intel_request_reset_engine(engine);
+   if (ret) {
+   DRM_ERROR("Failed to disable %s\n", engine->name);
+   goto error;
+   }
+
+   /* finally, reset engine */
+   ret = intel_gpu_reset(dev_priv, intel_engine_flag(engine));
+   if (ret) {
+   DRM_ERROR("Failed to reset %s, ret=%d\n", engine->name, ret);
+   intel_unrequest_reset_engine(engine);
+ 

[Intel-gfx] [PATCH v5 10/18] drm/i915: Add engine reset count in get-reset-stats ioctl

[Michel Thierry]

Users/tests relying on the total reset count will start seeing a smaller
number since most of the hangs can be handled by engine reset.
Note that if reset engine x, context a running on engine y will be unaware
and unaffected.

To start the discussion, include just a total engine reset count. If it
is deemed useful, it can be extended to report each engine separately.

v2: s/engine_reset/reset_engine/, use union in uapi to not break compatibility.

Cc: Chris Wilson 
Cc: Mika Kuoppala 
Cc: mesa-...@lists.freedesktop.org
Signed-off-by: Michel Thierry 
---
 drivers/gpu/drm/i915/i915_gem_context.c | 14 +++---
 include/uapi/drm/i915_drm.h |  6 +-
 2 files changed, 16 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index 8bd0c4966913..edbed85a1c88 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -1133,9 +1133,11 @@ int i915_gem_context_reset_stats_ioctl(struct drm_device 
*dev,
struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_i915_reset_stats *args = data;
struct i915_gem_context *ctx;
+   struct intel_engine_cs *engine;
+   enum intel_engine_id id;
int ret;
 
-   if (args->flags || args->pad)
+   if (args->flags)
return -EINVAL;
 
if (args->ctx_id == DEFAULT_CONTEXT_HANDLE && !capable(CAP_SYS_ADMIN))
@@ -1151,10 +1153,16 @@ int i915_gem_context_reset_stats_ioctl(struct 
drm_device *dev,
return PTR_ERR(ctx);
}
 
-   if (capable(CAP_SYS_ADMIN))
+   if (capable(CAP_SYS_ADMIN)) {
args->reset_count = i915_reset_count(_priv->gpu_error);
-   else
+   for_each_engine(engine, dev_priv, id)
+   args->reset_engine_count +=
+   i915_reset_engine_count(_priv->gpu_error,
+   engine);
+   } else {
args->reset_count = 0;
+   args->reset_engine_count = 0;
+   }
 
args->batch_active = ctx->guilty_count;
args->batch_pending = ctx->active_count;
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 3554495bef13..f083931a7809 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1263,7 +1263,11 @@ struct drm_i915_reset_stats {
/* Number of batches lost pending for execution, for this context */
__u32 batch_pending;
 
-   __u32 pad;
+   union {
+   __u32 pad;
+   /* Engine resets since boot/module reload, for all contexts */
+   __u32 reset_engine_count;
+   };
 };
 
 struct drm_i915_gem_userptr {
-- 
2.11.0

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[Intel-gfx] [PATCH v5 08/18] drm/i915/tdr: Export per-engine reset count info to debugfs

[Michel Thierry]

From: Arun Siluvery 

A new variable is added to export the reset counts to debugfs, this
includes full gpu reset and engine reset count. This is useful for tests
where they are expected to trigger reset; these counts are checked before
and after the test to ensure the same.

v2: Include reset engine count in i915_engine_info too (Chris).

Cc: Chris Wilson 
Cc: Mika Kuoppala 
Signed-off-by: Arun Siluvery 
Signed-off-by: Michel Thierry 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 21 +
 1 file changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 3ebdbc798f33..8db850541e03 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1400,6 +1400,23 @@ static int i915_hangcheck_info(struct seq_file *m, void 
*unused)
return 0;
 }
 
+static int i915_reset_info(struct seq_file *m, void *unused)
+{
+   struct drm_i915_private *dev_priv = node_to_i915(m->private);
+   struct i915_gpu_error *error = _priv->gpu_error;
+   struct intel_engine_cs *engine;
+   enum intel_engine_id id;
+
+   seq_printf(m, "full gpu reset = %u\n", i915_reset_count(error));
+
+   for_each_engine(engine, dev_priv, id) {
+   seq_printf(m, "%s = %u\n", engine->name,
+  i915_reset_engine_count(error, engine));
+   }
+
+   return 0;
+}
+
 static int ironlake_drpc_info(struct seq_file *m)
 {
struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -3241,6 +3258,7 @@ static int i915_display_info(struct seq_file *m, void 
*unused)
 static int i915_engine_info(struct seq_file *m, void *unused)
 {
struct drm_i915_private *dev_priv = node_to_i915(m->private);
+   struct i915_gpu_error *error = _priv->gpu_error;
struct intel_engine_cs *engine;
enum intel_engine_id id;
 
@@ -3264,6 +3282,8 @@ static int i915_engine_info(struct seq_file *m, void 
*unused)
   engine->hangcheck.seqno,
   jiffies_to_msecs(jiffies - 
engine->hangcheck.action_timestamp),
   engine->timeline->inflight_seqnos);
+   seq_printf(m, "\tReset count: %d\n",
+  i915_reset_engine_count(error, engine));
 
rcu_read_lock();
 
@@ -4774,6 +4794,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
{"i915_huc_load_status", i915_huc_load_status_info, 0},
{"i915_frequency_info", i915_frequency_info, 0},
{"i915_hangcheck_info", i915_hangcheck_info, 0},
+   {"i915_reset_info", i915_reset_info, 0},
{"i915_drpc_info", i915_drpc_info, 0},
{"i915_emon_status", i915_emon_status, 0},
{"i915_ring_freq_table", i915_ring_freq_table, 0},
-- 
2.11.0

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[Intel-gfx] [PATCH v5 09/18] drm/i915/tdr: Enable Engine reset and recovery support

[Michel Thierry]

From: Arun Siluvery 

This feature is made available only from Gen8, for previous gen devices
driver uses legacy full gpu reset.

Cc: Chris Wilson 
Cc: Mika Kuoppala 
Signed-off-by: Tomas Elf 
Signed-off-by: Arun Siluvery 
Signed-off-by: Michel Thierry 
---
 drivers/gpu/drm/i915/i915_params.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index 045cadb77285..14e2c2e57f96 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -46,7 +46,7 @@ struct i915_params i915 __read_mostly = {
.prefault_disable = 0,
.load_detect_test = 0,
.force_reset_modeset_test = 0,
-   .reset = 1,
+   .reset = 2,
.error_capture = true,
.invert_brightness = 0,
.disable_display = 0,
@@ -116,7 +116,7 @@ MODULE_PARM_DESC(vbt_sdvo_panel_type,
"(-2=ignore, -1=auto [default], index in VBT BIOS table)");
 
 module_param_named_unsafe(reset, i915.reset, int, 0600);
-MODULE_PARM_DESC(reset, "Attempt GPU resets (0=disabled, 1=full gpu reset 
[default], 2=engine reset)");
+MODULE_PARM_DESC(reset, "Attempt GPU resets (0=disabled, 1=full gpu reset, 
2=engine reset [default])");
 
 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
 module_param_named(error_capture, i915.error_capture, bool, 0600);
-- 
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[Intel-gfx] [PATCH v5 02/18] drm/i915: Rename gen8_(un)request_engine_reset to gen8_(un)request_reset_engine

[Michel Thierry]

As all other functions related to resetting engines are using reset_engine.

Signed-off-by: Michel Thierry 
---
 drivers/gpu/drm/i915/intel_uncore.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
b/drivers/gpu/drm/i915/intel_uncore.c
index 6d1ea26b2493..5f815a100a8d 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1658,7 +1658,7 @@ int intel_wait_for_register(struct drm_i915_private 
*dev_priv,
return ret;
 }
 
-static int gen8_request_engine_reset(struct intel_engine_cs *engine)
+static int gen8_request_reset_engine(struct intel_engine_cs *engine)
 {
struct drm_i915_private *dev_priv = engine->i915;
int ret;
@@ -1677,7 +1677,7 @@ static int gen8_request_engine_reset(struct 
intel_engine_cs *engine)
return ret;
 }
 
-static void gen8_unrequest_engine_reset(struct intel_engine_cs *engine)
+static void gen8_unrequest_reset_engine(struct intel_engine_cs *engine)
 {
struct drm_i915_private *dev_priv = engine->i915;
 
@@ -1692,14 +1692,14 @@ static int gen8_reset_engines(struct drm_i915_private 
*dev_priv,
unsigned int tmp;
 
for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
-   if (gen8_request_engine_reset(engine))
+   if (gen8_request_reset_engine(engine))
goto not_ready;
 
return gen6_reset_engines(dev_priv, engine_mask);
 
 not_ready:
for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
-   gen8_unrequest_engine_reset(engine);
+   gen8_unrequest_reset_engine(engine);
 
return -EIO;
 }
-- 
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[Intel-gfx] [PATCH v5 12/18] drm/i915/guc: Provide register list to be saved/restored during engine reset

[Michel Thierry]

From: Arun Siluvery 

GuC expects a list of registers from the driver which are saved/restored
during engine reset. The type of value to be saved is controlled by
flags. We provide a minimal set of registers that we want GuC to save and
restore. This is not an issue in case of engine reset as driver initializes
most of them following an engine reset, but in case of media reset (aka
watchdog reset) which is completely internal to GuC (including resubmission
of hung workload), it is necessary to provide this list, otherwise GuC won't
be able to schedule further workloads after a reset. This is the minimal
set of registers identified for things to work as expected but if we see
any new issues, this register list can be expanded.

Signed-off-by: Arun Siluvery 
Signed-off-by: Jeff McGee 
Signed-off-by: Michel Thierry 
---
 drivers/gpu/drm/i915/i915_guc_submission.c | 50 +-
 1 file changed, 49 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 991e76e10f82..2445af96aa71 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -1015,6 +1015,22 @@ static void guc_policies_init(struct guc_policies 
*policies)
policies->is_valid = 1;
 }
 
+/*
+ * In this macro it is highly unlikely to exceed max value but even if we did
+ * it is not an error so just throw a warning and continue. Only side effect
+ * in continuing further means some registers won't be added to save/restore
+ * list.
+ */
+#define GUC_ADD_MMIO_REG_ADS(node, reg_addr, _flags)   \
+   do {\
+   u32 __count = node->number_of_registers;\
+   if (WARN_ON(__count >= GUC_REGSET_MAX_REGISTERS))   \
+   continue;   \
+   node->registers[__count].offset = reg_addr.reg; \
+   node->registers[__count].flags = (_flags);  \
+   node->number_of_registers++;\
+   } while (0)
+
 static int guc_ads_create(struct intel_guc *guc)
 {
struct drm_i915_private *dev_priv = guc_to_i915(guc);
@@ -1047,10 +1063,42 @@ static int guc_ads_create(struct intel_guc *guc)
 
/* MMIO reg state */
for_each_engine(engine, dev_priv, id) {
+   u32 flags;
+   struct guc_mmio_regset *eng_reg =
+   >reg_state.engine_reg[engine->guc_id];
+
+   /*
+* Provide a list of registers to be saved/restored during gpu
+* reset. This is mainly required for Media reset (aka watchdog
+* timeout) which is completely under the control of GuC
+* (resubmission of hung workload is handled inside GuC).
+*/
+   flags = GUC_REGSET_POWERCYCLE |
+   GUC_REGSET_ENGINERESET |
+   GUC_REGSET_SAVE_CURRENT_VALUE;
+
+   GUC_ADD_MMIO_REG_ADS(eng_reg, RING_HEAD(engine->mmio_base),
+flags);
+
+   GUC_ADD_MMIO_REG_ADS(eng_reg, RING_TAIL(engine->mmio_base),
+flags);
+
+   GUC_ADD_MMIO_REG_ADS(eng_reg, RING_HWS_PGA(engine->mmio_base),
+flags);
+
+   GUC_ADD_MMIO_REG_ADS(eng_reg, RING_MODE_GEN7(engine),
+(flags | GUC_REGSET_MASKED));
+
+   GUC_ADD_MMIO_REG_ADS(eng_reg, RING_IMR(engine->mmio_base),
+flags);
+
+   DRM_DEBUG_DRIVER("%s register save/restore count: %u\n",
+engine->name, eng_reg->number_of_registers);
+
+/* Nothing to be white listed for now. */
blob->reg_state.white_list[engine->guc_id].mmio_start =
engine->mmio_base + GUC_MMIO_WHITE_LIST_START;
 
-   /* Nothing to be saved or restored for now. */
blob->reg_state.white_list[engine->guc_id].count = 0;
}
 
-- 
2.11.0

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[Intel-gfx] [PATCH v5 06/18] drm/i915: Skip reset request if there is one already

[Michel Thierry]

From: Mika Kuoppala 

To perform engine reset we first disable engine to capture its state. This
is done by issuing a reset request. Because we are reusing existing
infrastructure, again when we actually reset an engine, reset function
checks engine mask and issues reset request again which is unnecessary. To
avoid this we check if the engine is already prepared, if so we just exit
from that point.

Cc: Chris Wilson 
Signed-off-by: Mika Kuoppala 
Signed-off-by: Arun Siluvery 
Signed-off-by: Michel Thierry 
---
 drivers/gpu/drm/i915/intel_uncore.c | 9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
b/drivers/gpu/drm/i915/intel_uncore.c
index 596b99dbbff8..9886d7bd11ba 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1661,10 +1661,15 @@ int intel_wait_for_register(struct drm_i915_private 
*dev_priv,
 static int gen8_request_reset_engine(struct intel_engine_cs *engine)
 {
struct drm_i915_private *dev_priv = engine->i915;
+   const i915_reg_t reset_ctrl = RING_RESET_CTL(engine->mmio_base);
+   const u32 ready = RESET_CTL_REQUEST_RESET | RESET_CTL_READY_TO_RESET;
int ret;
 
-   I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base),
- _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET));
+   /* If engine has been already prepared, we can shortcut here */
+   if ((I915_READ_FW(reset_ctrl) & ready) == ready)
+   return 0;
+
+   I915_WRITE_FW(reset_ctrl, _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET));
 
ret = intel_wait_for_register_fw(dev_priv,
 RING_RESET_CTL(engine->mmio_base),
-- 
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[Intel-gfx] [PATCH v5 18/18] drm/i915: Watchdog timeout: Export media reset count from GuC to debugfs

[Michel Thierry]

From firmware v8.8, GuC provides the count of media engine resets
(watchdog timeout). This information is available in the GuC shared
context data struct, which resides in the first page of the default
(kernel) lrc context.

Since GuC handled engine resets are transparent for kernel and user,
provide a simple debugfs entry to see the number of times media reset
has happened.

Signed-off-by: Michel Thierry 
---
 drivers/gpu/drm/i915/i915_debugfs.c   | 28 
 drivers/gpu/drm/i915/intel_guc_fwif.h | 18 ++
 2 files changed, 46 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 8db850541e03..f40a2c84b423 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1400,6 +1400,32 @@ static int i915_hangcheck_info(struct seq_file *m, void 
*unused)
return 0;
 }
 
+static u32 i915_watchdog_reset_count(struct drm_i915_private *dev_priv)
+{
+   struct drm_device *dev = _priv->drm;
+   struct i915_gem_context *ctx;
+   struct page *page;
+   struct guc_shared_ctx_data *guc_shared_data;
+   u32 guc_media_reset_count;
+
+   if (!i915.enable_guc_submission)
+   return 0;
+
+   if (mutex_lock_interruptible(>struct_mutex))
+   return 0;
+
+   ctx = dev_priv->kernel_context;
+   page = i915_gem_object_get_dirty_page(ctx->engine[RCS].state->obj,
+ LRC_GUCSHR_PN);
+   guc_shared_data = kmap_atomic(page);
+   guc_media_reset_count = guc_shared_data->media_reset_count;
+   kunmap_atomic(guc_shared_data);
+
+   mutex_unlock(>struct_mutex);
+
+   return guc_media_reset_count;
+}
+
 static int i915_reset_info(struct seq_file *m, void *unused)
 {
struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -1408,6 +1434,8 @@ static int i915_reset_info(struct seq_file *m, void 
*unused)
enum intel_engine_id id;
 
seq_printf(m, "full gpu reset = %u\n", i915_reset_count(error));
+   seq_printf(m, "GuC watchdog/media reset = %u\n",
+  i915_watchdog_reset_count(dev_priv));
 
for_each_engine(engine, dev_priv, id) {
seq_printf(m, "%s = %u\n", engine->name,
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h 
b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 5db3def5f74e..d9dc844fcce0 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -503,6 +503,24 @@ union guc_log_control {
u32 value;
 } __packed;
 
+/* GuC Shared Context Data Struct */
+struct guc_shared_ctx_data {
+   u32 addr_of_last_preempted_data_low;
+   u32 addr_of_last_preempted_data_high;
+   u32 addr_of_last_preempted_data_high_tmp;
+   u32 padding;
+   u32 is_mapped_to_proxy;
+   u32 proxy_ctx_id;
+   u32 engine_reset_ctx_id;
+   u32 media_reset_count;
+   u32 reserved[8];
+   u32 uk_last_ctx_switch_reason;
+   u32 was_reset;
+   u32 lrca_gpu_addr;
+   u32 execlist_ctx;
+   u32 reserved1[32];
+} __packed;
+
 /* This Action will be programmed in C180 - SOFT_SCRATCH_O_REG */
 enum intel_guc_action {
INTEL_GUC_ACTION_DEFAULT = 0x0,
-- 
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[Intel-gfx] [PATCH v5 15/18] drm/i915: Watchdog timeout: IRQ handler for gen8+

[Michel Thierry]

*** General ***

Watchdog timeout (or "media engine reset") is a feature that allows
userland applications to enable hang detection on individual batch buffers.
The detection mechanism itself is mostly bound to the hardware and the only
thing that the driver needs to do to support this form of hang detection
is to implement the interrupt handling support as well as watchdog command
emission before and after the emitted batch buffer start instruction in the
ring buffer.

The principle of the hang detection mechanism is as follows:

1. Once the decision has been made to enable watchdog timeout for a
particular batch buffer and the driver is in the process of emitting the
batch buffer start instruction into the ring buffer it also emits a
watchdog timer start instruction before and a watchdog timer cancellation
instruction after the batch buffer start instruction in the ring buffer.

2. Once the GPU execution reaches the watchdog timer start instruction
the hardware watchdog counter is started by the hardware. The counter
keeps counting until either reaching a previously configured threshold
value or the timer cancellation instruction is executed.

2a. If the counter reaches the threshold value the hardware fires a
watchdog interrupt that is picked up by the watchdog interrupt handler.
This means that a hang has been detected and the driver needs to deal with
it the same way it would deal with a engine hang detected by the periodic
hang checker. The only difference between the two is that we already blamed
the active request (to ensure an engine reset).

2b. If the batch buffer completes and the execution reaches the watchdog
cancellation instruction before the watchdog counter reaches its
threshold value the watchdog is cancelled and nothing more comes of it.
No hang is detected.

Note about future interaction with preemption: Preemption could happen
in a command sequence prior to watchdog counter getting disabled,
resulting in watchdog being triggered following preemption. The driver will
need to explicitly disable the watchdog counter as part of the
preemption sequence.

*** This patch introduces: ***

1. IRQ handler code for watchdog timeout allowing direct hang recovery
based on hardware-driven hang detection, which then integrates directly
with the hang recovery path. This is independent of having per-engine reset
or just full gpu reset.

2. Watchdog specific register information.

Currently the render engine and all available media engines support
watchdog timeout (VECS is only supported in GEN9). The specifications elude
to the BCS engine being supported but that is currently not supported by
this commit.

Note that the value to stop the counter is different between render and
non-render engines.

v2: Move irq handler to tasklet, arm watchdog for a 2nd time to check
against false-positives.

Signed-off-by: Tomas Elf 
Signed-off-by: Ian Lister 
Signed-off-by: Arun Siluvery 
Signed-off-by: Michel Thierry 
---
 drivers/gpu/drm/i915/i915_drv.h |  4 +++
 drivers/gpu/drm/i915/i915_irq.c | 13 ++-
 drivers/gpu/drm/i915/i915_reg.h |  6 
 drivers/gpu/drm/i915/intel_hangcheck.c  | 13 ---
 drivers/gpu/drm/i915/intel_lrc.c| 64 +
 drivers/gpu/drm/i915/intel_ringbuffer.h |  4 +++
 6 files changed, 99 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d5c12ddd35b3..b43c37a911bb 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1628,6 +1628,9 @@ struct i915_gpu_error {
 * inspect the bit and do the reset directly, otherwise the worker
 * waits for the struct_mutex.
 *
+* #I915_RESET_WATCHDOG - When hw detects a hang before us, we can use
+* I915_RESET_WATCHDOG to report the hang detection cause accurately.
+*
 * #I915_WEDGED - If reset fails and we can no longer use the GPU,
 * we set the #I915_WEDGED bit. Prior to command submission, e.g.
 * i915_gem_request_alloc(), this bit is checked and the sequence
@@ -1636,6 +1639,7 @@ struct i915_gpu_error {
unsigned long flags;
 #define I915_RESET_BACKOFF 0
 #define I915_RESET_HANDOFF 1
+#define I915_RESET_WATCHDOG2
 #define I915_WEDGED(BITS_PER_LONG - 1)
 
/* if available, engine-specific reset is tried before full gpu reset */
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 87e76ef589b1..d484cbc561eb 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1369,6 +1369,10 @@ gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 
iir, int test_shift)
 
if (tasklet)
tasklet_hi_schedule(>irq_tasklet);
+
+   if (iir & (GT_GEN8_WATCHDOG_INTERRUPT << test_shift)) {
+   

[Intel-gfx] [PATCH v5 14/18] drm/i915: Watchdog timeout: Pass GuC shared data structure during param load

[Michel Thierry]

For watchdog / media reset, the firmware must know the address of the shared
data page (the first page of the default context).

This information should be in DWORD 9 of the GUC_CTL structure.

Signed-off-by: Michel Thierry 
---
 drivers/gpu/drm/i915/intel_guc_fwif.h   | 2 +-
 drivers/gpu/drm/i915/intel_guc_loader.c | 8 
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h 
b/drivers/gpu/drm/i915/intel_guc_fwif.h
index b627206b8f56..5db3def5f74e 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -135,7 +135,7 @@
 #define   GUC_ADS_ADDR_SHIFT   11
 #define   GUC_ADS_ADDR_MASK0xf800
 
-#define GUC_CTL_RSRVD  9
+#define GUC_CTL_SHARED_DATA9
 
 #define GUC_CTL_MAX_DWORDS (SOFT_SCRATCH_COUNT - 2) /* [1..14] */
 
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c 
b/drivers/gpu/drm/i915/intel_guc_loader.c
index 7d92321f8731..afa584864cb5 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -119,6 +119,7 @@ static void guc_params_init(struct drm_i915_private 
*dev_priv)
 {
struct intel_guc *guc = _priv->guc;
u32 params[GUC_CTL_MAX_DWORDS];
+   struct i915_gem_context *ctx;
int i;
 
memset(, 0, sizeof(params));
@@ -167,6 +168,13 @@ static void guc_params_init(struct drm_i915_private 
*dev_priv)
params[GUC_CTL_FEATURE] &= ~GUC_CTL_DISABLE_SCHEDULER;
}
 
+   /*
+* For watchdog / media reset, GuC must know the address of the shared
+* data page, which is the first page of the default context.
+*/
+   ctx = dev_priv->kernel_context;
+   params[GUC_CTL_SHARED_DATA] = i915_ggtt_offset(ctx->engine[RCS].state);
+
I915_WRITE(SOFT_SCRATCH(0), 0);
 
for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
-- 
2.11.0

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[Intel-gfx] [PATCH v5 04/18] drm/i915/tdr: Modify error handler for per engine hang recovery

[Michel Thierry]

From: Arun Siluvery 

This is a preparatory patch which modifies error handler to do per engine
hang recovery. The actual patch which implements this sequence follows
later in the series. The aim is to prepare existing recovery function to
adapt to this new function where applicable (which fails at this point
because core implementation is lacking) and continue recovery using legacy
full gpu reset.

A helper function is also added to query the availability of engine
reset.

The error events behaviour that are used to notify user of reset are
adapted to engine reset such that it doesn't break users listening to these
events. In legacy we report an error event, a reset event before resetting
the gpu and a reset done event marking the completion of reset. The same
behaviour is adapted but reset event is only dispatched once even when
multiple engines are hung. Finally once reset is complete we send reset
done event as usual.

Note that this implementation of engine reset is for i915 directly
submitting to the ELSP, where the driver manages the hang detection,
recovery and resubmission. With GuC submission these tasks are shared
between driver and firmware; i915 will still responsible for detecting a
hang, and when it does it will have to request GuC to reset that Engine and
remind the firmware about the outstanding submissions. This will be
added in different patch.

v2: rebase, advertise engine reset availability in platform definition,
add note about GuC submission.
v3: s/*engine_reset*/*reset_engine*/. (Chris)
Handle reset as 2 level resets, by first going to engine only and fall
backing to full/chip reset as needed, i.e. reset_engine will need the
struct_mutex.
v4: Pass the engine mask to i915_reset. (Chris)
v5: Rebase, update selftests.

Cc: Chris Wilson 
Cc: Mika Kuoppala 
Signed-off-by: Ian Lister 
Signed-off-by: Tomas Elf 
Signed-off-by: Arun Siluvery 
Signed-off-by: Michel Thierry 
---
 drivers/gpu/drm/i915/i915_drv.c  | 49 +++-
 drivers/gpu/drm/i915/i915_drv.h  |  7 +++-
 drivers/gpu/drm/i915/i915_gem_request.c  |  3 +-
 drivers/gpu/drm/i915/i915_irq.c  | 19 -
 drivers/gpu/drm/i915/i915_pci.c  |  5 ++-
 drivers/gpu/drm/i915/intel_ringbuffer.h  | 16 
 drivers/gpu/drm/i915/intel_uncore.c  | 11 ++
 drivers/gpu/drm/i915/selftests/intel_hangcheck.c |  4 +-
 8 files changed, 105 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 6d9944a00b7d..c7eb43deb33e 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1794,7 +1794,7 @@ static int i915_resume_switcheroo(struct drm_device *dev)
 }
 
 /**
- * i915_reset - reset chip after a hang
+ * i915_reset_chip - reset chip after a hang
  * @dev_priv: device private to reset
  *
  * Reset the chip.  Useful if a hang is detected. Marks the device as wedged
@@ -1810,7 +1810,7 @@ static int i915_resume_switcheroo(struct drm_device *dev)
  *   - re-init interrupt state
  *   - re-init display
  */
-void i915_reset(struct drm_i915_private *dev_priv)
+void i915_reset_chip(struct drm_i915_private *dev_priv)
 {
struct i915_gpu_error *error = _priv->gpu_error;
int ret;
@@ -1821,6 +1821,8 @@ void i915_reset(struct drm_i915_private *dev_priv)
if (!test_bit(I915_RESET_HANDOFF, >flags))
return;
 
+   DRM_DEBUG_DRIVER("resetting chip\n");
+
/* Clear any previous failed attempts at recovery. Time to try again. */
if (!i915_gem_unset_wedged(dev_priv))
goto wakeup;
@@ -1884,6 +1886,49 @@ void i915_reset(struct drm_i915_private *dev_priv)
goto finish;
 }
 
+/**
+ * i915_reset_engine - reset GPU engine to recover from a hang
+ * @engine: engine to reset
+ *
+ * Reset a specific GPU engine. Useful if a hang is detected.
+ * Returns zero on successful reset or otherwise an error code.
+ */
+int i915_reset_engine(struct intel_engine_cs *engine)
+{
+   /* FIXME: replace me with engine reset sequence */
+   return -ENODEV;
+}
+
+/**
+ * i915_reset - start either engine or full GPU reset to recover from a hang
+ * @dev_priv: device private
+ * @engine_mask: mask representing engines that are hung
+ *
+ * Wrapper function to initiate a GPU reset. When platform supports it, attempt
+ * to reset the hung engine only. If engine reset fails (or is not supported),
+ * reset the full GPU. If more than one engine is hung, the speed gains of
+ * reset_engine are negligible, thus promote to full reset.
+ *
+ * Caller must hold the struct_mutex.
+ */
+void i915_reset(struct drm_i915_private *dev_priv, u32 engine_mask)
+{
+   /* try engine reset first */
+   if 

[Intel-gfx] [Regression report] Weekly regression report WW12

[Jairo Miramontes]

Link to FDO regression list: 
https://bugs.freedesktop.org/buglist.cgi?bug_status=NEW_status=ASSIGNED_status=REOPENED_status=NEEDINFO=DRM%2FIntel=OP=OP=short_desc=keywords=CP=CP=OR_name=i915%20regressions_id=600614=anywordssubstr=anywordssubstr_sys=All_sys=Linux%20%28All%29_sys=other=bug_id%20DESC=DRI_based_on=i915%20regressions_format=advanced_platform=All_platform=x86%20%28IA32%29_platform=x86-64%20%28AMD64%29_platform=IA64%20%28Itanium%29_platform=Other=regression%20bisect=regression%20bisected%20pending_bisect

Total regressions: 26

This week regressions:0
+---+-+++
| BugId | Summary | Created on | Bisect |
+---+-+++

Previous regressions:26
++--+++
| BugId  | Summary | Created on | Bisect |
++--+++
| 99929  | [i915] Black/gray screen with kernel 
4.9.3   | 2017-02-23 | Yes |
| 99766  | [v4.9 PATCH] DisplayPort Monitor Doesn't Come Back From 
Sleep| 2017-02-10 | Yes|
| 99578  | [SKL][bisected] Screen regularly returns from power save 
mode| 2017-01-28 | Yes|
| 99575  | [ilk bisected] "drm/i915: Type safe register read/write" -> 
poor/nonexistent IPS | 2017-01-28 | Yes|
| 99362  | no resolutions >=1080p with Acer P7500 and Thinkpad 
X1   | 2017-01-11 | No |
| 99093  | [PNV][regression] N450 and D510 machines get stuck in 
igt@gem_ringfill@basic-def | 2016-12-15 | Yes|
| 98690  | [SKL bisected] System freeze when starting X using kernel 
4.9-rc1 or later   | 2016-11-11 | Yes|
| 98517  | Skylake gen6 suspend/resume video regression 
4.9 | 2016-10-31 | No |
| 97918  | [bdw regression 4.8] Severe graphics regression, rainbow 
glitching and flickerin | 2016-09-25 | No |
| 96781  | [skl dp-mst] oops in atomic 
commit   | 2016-07-02 | Yes|
| 96428  | [IVB bisected] [drm:intel_dp_aux_ch] *ERROR* dp aux hw did 
not signal timeout (h | 2016-06-07 | Yes|
| 95736  | [IVB bisected] *ERROR* uncleared fifo underrun on pipe 
A | 2016-05-24 | Yes|
| 94590  | [KBL] igt/kms_fbcon_fbt/psr-suspend 
regression   | 2016-03-17 | No |
| 93782  | [i9xx TV][BISECT] vblank wait timeout on 
crtc| 2016-01-19 | Yes|
| 93486  | [HP Compaq dc7800 Small Form Factor PC][REGRESSION] 
suspend/resume failure   | 2015-12-23 | No |
| 93361  | 12bpc hdmi causes wrong real refresh rate (swapbuffers return 
time)  | 2015-12-12 | Yes|
| 93263  | 945GM regression since 
4.3   | 2015-12-05 | 
No |
| 92050  | [regression]/bug introduced by commit 
[0e572fe7383a376992364914694c39aa7fe44c1d] | 2015-09-19 | Yes|
| 91974  | [bisected] unrecoverable black screen after killing 
X| 2015-09-11 | Yes|
| 90112  | [BSW bisected] OglGSCloth/Lightsmark/CS/ Portal/ Half Life 2 
games performance d | 2015-04-20 | Yes|
| 89632  | [i965 
regression]igt/kms_universal_plane/universal-plane-pipe-A-functional 
cause | 2015-03-18 | No |
| 88124  | i915: regression: after DP connected (via docking station) 
monitor is turned off | 2015-01-06 | No |
| 87726  | [BDW Bisected] OglDrvCtx performance reduced by ~30% after 
use true PPGTT in Gen | 2014-12-26 | Yes|
| 87725  | [BDW Bisected] OglBatch7 performance reduced by ~7% after 
enable execlists   | 2014-12-26 | Yes|
| 87131  | [PNV regression] igt/gem_exec_lut_handle takes more than 10 
minutes  | 2014-12-09 | No |
| 100221 | [SKL] Resume from suspend to disk fails - 
bisected   | 2017-03-15 | Yes|
++--+++ 


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[Intel-gfx] [PATCH] aubdump: Don't bail if a GEM handle of 0 is passed into execbuf

[Jason Ekstrand]

A gem handle of 0 can be used to check for whether or not 48-bit
addressing is available.  This keeps aubdump from failing on you if
you try to do the check.
---
 tools/aubdump.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/tools/aubdump.c b/tools/aubdump.c
index 8a89b8c..3aca7eb 100644
--- a/tools/aubdump.c
+++ b/tools/aubdump.c
@@ -131,7 +131,6 @@ get_bo(uint32_t handle)
 
fail_if(handle >= MAX_BO_COUNT, "bo handle too large\n");
bo = [handle];
-   fail_if(bo->size == 0, "invalid bo handle (%d) in execbuf\n", handle);
 
return bo;
 }
@@ -442,7 +441,7 @@ dump_execbuffer2(int fd, struct drm_i915_gem_execbuffer2 
*execbuffer2)
offset = align_u32(offset + bo->size + 4095, 4096);
}
 
-   if (bo->map == NULL)
+   if (bo->map == NULL && bo->size > 0)
bo->map = gem_mmap(fd, obj->handle, 0, bo->size);
fail_if(bo->map == MAP_FAILED, "intel_aubdump: bo mmap 
failed\n");
}
@@ -583,7 +582,7 @@ maybe_init(void)
}
fclose(config);
 
-   bos = malloc(MAX_BO_COUNT * sizeof(bos[0]));
+   bos = calloc(MAX_BO_COUNT, sizeof(bos[0]));
fail_if(bos == NULL, "intel_aubdump: out of memory\n");
 }
 
-- 
2.5.0.400.gff86faf

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Re: [Intel-gfx] [PATCH 08/16] drm: document drm_ioctl.[hc]

[kbuild test robot]

Hi Daniel,

[auto build test WARNING on drm/drm-next]
[cannot apply to v4.11-rc3 next-20170324]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Daniel-Vetter/more-drmP-h-cleanup/20170325-030940
base:   git://people.freedesktop.org/~airlied/linux.git drm-next
reproduce: make htmldocs

All warnings (new ones prefixed by >>):

   WARNING: convert(1) not found, for SVG to PDF conversion install ImageMagick 
(https://www.imagemagick.org)
   include/linux/init.h:1: warning: no structured comments found
   kernel/sched/core.c:2085: warning: No description found for parameter 'rf'
   kernel/sched/core.c:2085: warning: Excess function parameter 'cookie' 
description in 'try_to_wake_up_local'
   include/linux/kthread.h:26: warning: Excess function parameter '...' 
description in 'kthread_create'
   kernel/sys.c:1: warning: no structured comments found
   include/linux/device.h:969: warning: No description found for parameter 
'dma_ops'
   drivers/dma-buf/seqno-fence.c:1: warning: no structured comments found
   include/linux/iio/iio.h:597: warning: No description found for parameter 
'trig_readonly'
   include/linux/iio/trigger.h:151: warning: No description found for parameter 
'indio_dev'
   include/linux/iio/trigger.h:151: warning: No description found for parameter 
'trig'
   include/linux/device.h:970: warning: No description found for parameter 
'dma_ops'
   drivers/regulator/core.c:1467: warning: Excess function parameter 'ret' 
description in 'regulator_dev_lookup'
   include/drm/drm_drv.h:524: warning: No description found for parameter 
'set_busid'
   include/drm/drm_drv.h:524: warning: No description found for parameter 
'irq_handler'
   include/drm/drm_drv.h:524: warning: No description found for parameter 
'irq_preinstall'
   include/drm/drm_drv.h:524: warning: No description found for parameter 
'irq_postinstall'
   include/drm/drm_drv.h:524: warning: No description found for parameter 
'irq_uninstall'
   include/drm/drm_drv.h:524: warning: No description found for parameter 
'debugfs_init'
   include/drm/drm_drv.h:524: warning: No description found for parameter 
'gem_open_object'
   include/drm/drm_drv.h:524: warning: No description found for parameter 
'gem_close_object'
   include/drm/drm_drv.h:524: warning: No description found for parameter 
'prime_handle_to_fd'
   include/drm/drm_drv.h:524: warning: No description found for parameter 
'prime_fd_to_handle'
   include/drm/drm_drv.h:524: warning: No description found for parameter 
'gem_prime_export'
   include/drm/drm_drv.h:524: warning: No description found for parameter 
'gem_prime_import'
   include/drm/drm_drv.h:524: warning: No description found for parameter 
'gem_prime_pin'
   include/drm/drm_drv.h:524: warning: No description found for parameter 
'gem_prime_unpin'
   include/drm/drm_drv.h:524: warning: No description found for parameter 
'gem_prime_res_obj'
   include/drm/drm_drv.h:524: warning: No description found for parameter 
'gem_prime_get_sg_table'
   include/drm/drm_drv.h:524: warning: No description found for parameter 
'gem_prime_import_sg_table'
   include/drm/drm_drv.h:524: warning: No description found for parameter 
'gem_prime_vmap'
   include/drm/drm_drv.h:524: warning: No description found for parameter 
'gem_prime_vunmap'
   include/drm/drm_drv.h:524: warning: No description found for parameter 
'gem_prime_mmap'
   include/drm/drm_drv.h:524: warning: No description found for parameter 
'gem_vm_ops'
   include/drm/drm_drv.h:524: warning: No description found for parameter 
'major'
   include/drm/drm_drv.h:524: warning: No description found for parameter 
'minor'
   include/drm/drm_drv.h:524: warning: No description found for parameter 
'patchlevel'
   include/drm/drm_drv.h:524: warning: No description found for parameter 'name'
   include/drm/drm_drv.h:524: warning: No description found for parameter 'desc'
   include/drm/drm_drv.h:524: warning: No description found for parameter 'date'
   include/drm/drm_drv.h:524: warning: No description found for parameter 
'driver_features'
   include/drm/drm_drv.h:524: warning: No description found for parameter 
'ioctls'
   include/drm/drm_drv.h:524: warning: No description found for parameter 
'num_ioctls'
   include/drm/drm_drv.h:524: warning: No description found for parameter 'fops'
   include/drm/drm_connector.h:138: warning: No description found for parameter 
'scdc'
   include/drm/drm_color_mgmt.h:1: warning: no structured comments found
   drivers/gpu/drm/drm_ioc32.c:3: warning: Cannot understand  * \file 
drm_ioc32.c
on line 3 - I thought it was a doc line
>> drivers/gpu/drm/drm_ioc32.c:1124: warning: No description found for 
>> parameter 'filp'
>> drivers/gpu/drm/drm_ioc32.c:1124: warning: No description found for 
>> parameter 'cmd'
>> drivers/gpu/drm/drm_ioc32.c:1124: warning: No description found for 
>> parameter 'arg'
   

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Use LINEAR modifier instead of NONE

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915: Use LINEAR modifier instead of NONE
URL   : https://patchwork.freedesktop.org/series/21854/
State : success

== Summary ==

Series 21854v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/21854/revisions/1/mbox/

Test gem_exec_flush:
Subgroup basic-batch-kernel-default-uc:
fail   -> PASS   (fi-snb-2600) fdo#17

fdo#17 https://bugs.freedesktop.org/show_bug.cgi?id=17

fi-bdw-5557u total:278  pass:262  dwarn:0   dfail:0   fail:5   skip:11  
time: 466s
fi-bdw-gvtdvmtotal:278  pass:251  dwarn:8   dfail:0   fail:5   skip:14  
time: 453s
fi-bsw-n3050 total:278  pass:234  dwarn:0   dfail:0   fail:5   skip:39  
time: 592s
fi-bxt-j4205 total:278  pass:254  dwarn:0   dfail:0   fail:5   skip:19  
time: 539s
fi-bxt-t5700 total:278  pass:253  dwarn:0   dfail:0   fail:5   skip:20  
time: 564s
fi-byt-j1900 total:278  pass:246  dwarn:0   dfail:0   fail:5   skip:27  
time: 510s
fi-byt-n2820 total:278  pass:242  dwarn:0   dfail:0   fail:5   skip:31  
time: 504s
fi-hsw-4770  total:278  pass:257  dwarn:0   dfail:0   fail:5   skip:16  
time: 438s
fi-hsw-4770r total:278  pass:257  dwarn:0   dfail:0   fail:5   skip:16  
time: 432s
fi-ilk-650   total:278  pass:223  dwarn:0   dfail:0   fail:5   skip:50  
time: 447s
fi-ivb-3520m total:278  pass:255  dwarn:0   dfail:0   fail:5   skip:18  
time: 516s
fi-ivb-3770  total:278  pass:255  dwarn:0   dfail:0   fail:5   skip:18  
time: 503s
fi-kbl-7500u total:278  pass:255  dwarn:0   dfail:0   fail:5   skip:18  
time: 481s
fi-skl-6260u total:278  pass:263  dwarn:0   dfail:0   fail:5   skip:10  
time: 486s
fi-skl-6700hqtotal:278  pass:255  dwarn:0   dfail:0   fail:5   skip:18  
time: 608s
fi-skl-6700k total:278  pass:251  dwarn:4   dfail:0   fail:5   skip:18  
time: 480s
fi-skl-6770hqtotal:278  pass:263  dwarn:0   dfail:0   fail:5   skip:10  
time: 517s
fi-skl-gvtdvmtotal:278  pass:260  dwarn:0   dfail:0   fail:5   skip:13  
time: 461s
fi-snb-2520m total:278  pass:245  dwarn:0   dfail:0   fail:5   skip:28  
time: 552s
fi-snb-2600  total:278  pass:244  dwarn:0   dfail:0   fail:5   skip:29  
time: 424s

36ae70c6a67b894a97ba4098a32e091334ef51bc drm-tip: 2017y-03m-24d-19h-36m-19s UTC 
integration manifest
816a758 drm/i915: Add format modifiers for Intel
e906273 drm: Add new DRM_IOCTL_MODE_GETPLANE2
45b6fd7 drm/i915: Use LINEAR modifier instead of NONE

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4299/
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[Intel-gfx] [PATCH 1/3] drm/i915: Use LINEAR modifier instead of NONE

[Ben Widawsky]

They're the same, so use the one which makes more sense.

Signed-off-by: Ben Widawsky 
---
 drivers/gpu/drm/i915/intel_display.c | 28 ++--
 1 file changed, 14 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 9a28a8917dc1..696d106461f8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1997,7 +1997,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, 
int plane)
unsigned int cpp = fb->format->cpp[plane];
 
switch (fb->modifier) {
-   case DRM_FORMAT_MOD_NONE:
+   case DRM_FORMAT_MOD_LINEAR:
return cpp;
case I915_FORMAT_MOD_X_TILED:
if (IS_GEN2(dev_priv))
@@ -2033,7 +2033,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, 
int plane)
 static unsigned int
 intel_tile_height(const struct drm_framebuffer *fb, int plane)
 {
-   if (fb->modifier == DRM_FORMAT_MOD_NONE)
+   if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
return 1;
else
return intel_tile_size(to_i915(fb->dev)) /
@@ -2107,7 +2107,7 @@ static unsigned int intel_surf_alignment(const struct 
drm_framebuffer *fb,
return 4096;
 
switch (fb->modifier) {
-   case DRM_FORMAT_MOD_NONE:
+   case DRM_FORMAT_MOD_LINEAR:
return intel_linear_alignment(dev_priv);
case I915_FORMAT_MOD_X_TILED:
if (INTEL_GEN(dev_priv) >= 9)
@@ -2290,7 +2290,7 @@ static u32 intel_adjust_tile_offset(int *x, int *y,
 
WARN_ON(new_offset > old_offset);
 
-   if (fb->modifier != DRM_FORMAT_MOD_NONE) {
+   if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
unsigned int tile_size, tile_width, tile_height;
unsigned int pitch_tiles;
 
@@ -2345,7 +2345,7 @@ static u32 _intel_compute_tile_offset(const struct 
drm_i915_private *dev_priv,
if (alignment)
alignment--;
 
-   if (fb_modifier != DRM_FORMAT_MOD_NONE) {
+   if (fb_modifier != DRM_FORMAT_MOD_LINEAR) {
unsigned int tile_size, tile_width, tile_height;
unsigned int tile_rows, tiles, pitch_tiles;
 
@@ -2471,7 +2471,7 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
DRM_ROTATE_0, tile_size);
offset /= tile_size;
 
-   if (fb->modifier != DRM_FORMAT_MOD_NONE) {
+   if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
unsigned int tile_width, tile_height;
unsigned int pitch_tiles;
struct drm_rect r;
@@ -2803,7 +2803,7 @@ static int skl_max_plane_width(const struct 
drm_framebuffer *fb, int plane,
int cpp = fb->format->cpp[plane];
 
switch (fb->modifier) {
-   case DRM_FORMAT_MOD_NONE:
+   case DRM_FORMAT_MOD_LINEAR:
case I915_FORMAT_MOD_X_TILED:
switch (cpp) {
case 8:
@@ -3199,7 +3199,7 @@ static void ironlake_update_primary_plane(struct 
drm_plane *primary,
 static u32
 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane)
 {
-   if (fb->modifier == DRM_FORMAT_MOD_NONE)
+   if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
return 64;
else
return intel_tile_width_bytes(fb, plane);
@@ -3298,7 +3298,7 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
 static u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
 {
switch (fb_modifier) {
-   case DRM_FORMAT_MOD_NONE:
+   case DRM_FORMAT_MOD_LINEAR:
break;
case I915_FORMAT_MOD_X_TILED:
return PLANE_CTL_TILED_X;
@@ -8426,7 +8426,7 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
tiling = val & PLANE_CTL_TILED_MASK;
switch (tiling) {
case PLANE_CTL_TILED_LINEAR:
-   fb->modifier = DRM_FORMAT_MOD_NONE;
+   fb->modifier = DRM_FORMAT_MOD_LINEAR;
break;
case PLANE_CTL_TILED_X:
plane_config->tiling = I915_TILING_X;
@@ -10399,7 +10399,7 @@ static void skl_do_mmio_flip(struct intel_crtc 
*intel_crtc,
ctl = I915_READ(PLANE_CTL(pipe, 0));
ctl &= ~PLANE_CTL_TILED_MASK;
switch (fb->modifier) {
-   case DRM_FORMAT_MOD_NONE:
+   case DRM_FORMAT_MOD_LINEAR:
break;
case I915_FORMAT_MOD_X_TILED:
ctl |= PLANE_CTL_TILED_X;
@@ -13756,7 +13756,7 @@ intel_check_cursor_plane(struct drm_plane *plane,
return -ENOMEM;
}
 
-   if (fb->modifier != DRM_FORMAT_MOD_NONE) {
+   if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
DRM_DEBUG_KMS("cursor cannot be tiled\n");
return -EINVAL;
}
@@ -14412,7 +14412,7 @@ static int intel_framebuffer_init(struct 
intel_framebuffer *intel_fb,
   

[Intel-gfx] [PATCH 2/3] drm: Add new DRM_IOCTL_MODE_GETPLANE2

[Ben Widawsky]

Originally based off of a patch by Kristian.

This new ioctl extends DRM_IOCTL_MODE_GETPLANE, by returning information
about the modifiers that will work with each format.

It's modified from Kristian's patch in that the modifiers and formats
are setup by the driver, and then a callback is used to create the
format list. The LOC was enough difference that I don't think it made
sense to leave his authorship, but the new UABI was primarily his idea.

Additionally, I hit a couple of drivers which Kristian missed updating.

It also contains a change requested by Daniel to make the modifiers
array a sentinel based structure instead of a sized one. Upon discussion
on IRC, it was determined that having an invalid modifier might make
sense in general as well.

v2:
  - Make formats uint32_t, and use an offset, see the comment in the
  patch. Add a WARN_ON and early bail for when there are more than 32
  formats. (Rob)
  - Remove DRM_DEBUG_KMS (Ville)
  - make flags come before count in struct (Ville)

v3:
  - Make formats 64b again to defer the pain, and add a pad
  - Make init fail if > 64 instead of at get_plane. This could be made
  more optimal by doing it in get_plane because 0 masked modifiers don't
  need to be reported back to userspace. As a result, the first driver
  to go back 64 formats has to deal with this.
  - Fix the comment to be more clear.

v4:
  - Add drivers/gpu/drm/qxl/

Cc: Rob Clark 
Cc: Ville Syrjälä 
Cc: Daniel Stone 
Cc: "Kristian H. Kristensen" 
References: https://patchwork.kernel.org/patch/9482393/
Signed-off-by: Ben Widawsky 
---
 drivers/gpu/drm/arc/arcpgu_crtc.c   |  1 +
 drivers/gpu/drm/arm/hdlcd_crtc.c|  1 +
 drivers/gpu/drm/arm/malidp_planes.c |  2 +-
 drivers/gpu/drm/armada/armada_crtc.c|  1 +
 drivers/gpu/drm/armada/armada_overlay.c |  1 +
 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c |  4 +-
 drivers/gpu/drm/drm_ioctl.c |  2 +-
 drivers/gpu/drm/drm_modeset_helper.c|  1 +
 drivers/gpu/drm/drm_plane.c | 67 -
 drivers/gpu/drm/drm_simple_kms_helper.c |  3 ++
 drivers/gpu/drm/exynos/exynos_drm_plane.c   |  2 +-
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c |  2 +-
 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c  |  1 +
 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c |  2 +-
 drivers/gpu/drm/i915/intel_display.c|  7 ++-
 drivers/gpu/drm/i915/intel_sprite.c |  4 +-
 drivers/gpu/drm/imx/ipuv3-plane.c   |  4 +-
 drivers/gpu/drm/mediatek/mtk_drm_plane.c|  2 +-
 drivers/gpu/drm/meson/meson_plane.c |  1 +
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c   |  2 +-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c   |  4 +-
 drivers/gpu/drm/mxsfb/mxsfb_drv.c   |  2 +-
 drivers/gpu/drm/nouveau/nv50_display.c  |  5 +-
 drivers/gpu/drm/omapdrm/omap_plane.c|  3 +-
 drivers/gpu/drm/qxl/qxl_display.c   |  2 +-
 drivers/gpu/drm/rcar-du/rcar_du_plane.c |  4 +-
 drivers/gpu/drm/rcar-du/rcar_du_vsp.c   |  4 +-
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c |  4 +-
 drivers/gpu/drm/sti/sti_cursor.c|  2 +-
 drivers/gpu/drm/sti/sti_gdp.c   |  2 +-
 drivers/gpu/drm/sti/sti_hqvdp.c |  2 +-
 drivers/gpu/drm/sun4i/sun4i_layer.c |  2 +-
 drivers/gpu/drm/tegra/dc.c  | 12 ++---
 drivers/gpu/drm/vc4/vc4_plane.c |  2 +-
 drivers/gpu/drm/virtio/virtgpu_plane.c  |  2 +-
 drivers/gpu/drm/zte/zx_plane.c  |  2 +-
 include/drm/drm_plane.h | 21 +++-
 include/drm/drm_simple_kms_helper.h |  1 +
 include/uapi/drm/drm.h  |  1 +
 include/uapi/drm/drm_fourcc.h   | 11 
 include/uapi/drm/drm_mode.h | 44 
 41 files changed, 200 insertions(+), 42 deletions(-)

diff --git a/drivers/gpu/drm/arc/arcpgu_crtc.c 
b/drivers/gpu/drm/arc/arcpgu_crtc.c
index ad9a95916f1f..cd8a24c7c67d 100644
--- a/drivers/gpu/drm/arc/arcpgu_crtc.c
+++ b/drivers/gpu/drm/arc/arcpgu_crtc.c
@@ -218,6 +218,7 @@ static struct drm_plane *arc_pgu_plane_init(struct 
drm_device *drm)
 
ret = drm_universal_plane_init(drm, plane, 0xff, _pgu_plane_funcs,
   formats, ARRAY_SIZE(formats),
+  NULL,
   DRM_PLANE_TYPE_PRIMARY, NULL);
if (ret)
return ERR_PTR(ret);
diff --git a/drivers/gpu/drm/arm/hdlcd_crtc.c b/drivers/gpu/drm/arm/hdlcd_crtc.c
index 798a3cc480a2..0caa03ae8708 100644
--- a/drivers/gpu/drm/arm/hdlcd_crtc.c
+++ b/drivers/gpu/drm/arm/hdlcd_crtc.c
@@ -303,6 +303,7 @@ static struct drm_plane 

[Intel-gfx] [PATCH 3/3] drm/i915: Add format modifiers for Intel

[Ben Widawsky]

This was based on a patch originally by Kristian. It has been modified
pretty heavily to use the new callbacks from the previous patch.

v2:
  - Add LINEAR and Yf modifiers to list (Ville)
  - Combine i8xx and i965 into one list of formats (Ville)
  - Allow 1010102 formats for Y/Yf tiled (Ville)

v3:
  - Handle cursor formats (Ville)
  - Put handling for LINEAR in the mod_support functions (Ville)

Cc: Ville Syrjälä 
Cc: Kristian H. Kristensen 
Signed-off-by: Ben Widawsky 
---
 drivers/gpu/drm/i915/intel_display.c | 112 +--
 drivers/gpu/drm/i915/intel_sprite.c  |  25 +++-
 2 files changed, 131 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 802a8449c5d3..bb559a116fda 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -72,6 +72,12 @@ static const uint32_t i965_primary_formats[] = {
DRM_FORMAT_XBGR2101010,
 };
 
+static const uint64_t i9xx_format_modifiers[] = {
+   I915_FORMAT_MOD_X_TILED,
+   DRM_FORMAT_MOD_LINEAR,
+   DRM_FORMAT_MOD_INVALID
+};
+
 static const uint32_t skl_primary_formats[] = {
DRM_FORMAT_C8,
DRM_FORMAT_RGB565,
@@ -87,6 +93,14 @@ static const uint32_t skl_primary_formats[] = {
DRM_FORMAT_VYUY,
 };
 
+static const uint64_t skl_format_modifiers[] = {
+   I915_FORMAT_MOD_Yf_TILED,
+   I915_FORMAT_MOD_Y_TILED,
+   I915_FORMAT_MOD_X_TILED,
+   DRM_FORMAT_MOD_LINEAR,
+   DRM_FORMAT_MOD_INVALID
+};
+
 /* Cursor formats */
 static const uint32_t intel_cursor_formats[] = {
DRM_FORMAT_ARGB,
@@ -13453,6 +13467,83 @@ void intel_plane_destroy(struct drm_plane *plane)
kfree(to_intel_plane(plane));
 }
 
+static bool i8xx_mod_supported(uint32_t format, uint64_t modifier)
+{
+   switch (format) {
+   case DRM_FORMAT_C8:
+   case DRM_FORMAT_RGB565:
+   case DRM_FORMAT_XRGB1555:
+   case DRM_FORMAT_XRGB:
+   return modifier == DRM_FORMAT_MOD_LINEAR ||
+   modifier == I915_FORMAT_MOD_X_TILED;
+   default:
+   return false;
+   }
+}
+
+static bool i965_mod_supported(uint32_t format, uint64_t modifier)
+{
+   switch (format) {
+   case DRM_FORMAT_C8:
+   case DRM_FORMAT_RGB565:
+   case DRM_FORMAT_XRGB:
+   case DRM_FORMAT_XBGR:
+   case DRM_FORMAT_XRGB2101010:
+   case DRM_FORMAT_XBGR2101010:
+   return modifier == DRM_FORMAT_MOD_LINEAR ||
+   modifier == I915_FORMAT_MOD_X_TILED;
+   default:
+   return false;
+   }
+}
+
+static bool skl_mod_supported(uint32_t format, uint64_t modifier)
+{
+   switch (format) {
+   case DRM_FORMAT_C8:
+   return modifier == DRM_FORMAT_MOD_LINEAR ||
+   (modifier >= I915_FORMAT_MOD_X_TILED &&
+modifier < I915_FORMAT_MOD_Yf_TILED);
+   case DRM_FORMAT_RGB565:
+   case DRM_FORMAT_XRGB:
+   case DRM_FORMAT_XBGR:
+   case DRM_FORMAT_ARGB:
+   case DRM_FORMAT_ABGR:
+   case DRM_FORMAT_XRGB2101010:
+   case DRM_FORMAT_XBGR2101010:
+   return modifier == DRM_FORMAT_MOD_LINEAR ||
+   (modifier >= I915_FORMAT_MOD_X_TILED &&
+   modifier <= I915_FORMAT_MOD_Yf_TILED);
+   case DRM_FORMAT_YUYV:
+   case DRM_FORMAT_YVYU:
+   case DRM_FORMAT_UYVY:
+   case DRM_FORMAT_VYUY:
+   return modifier == DRM_FORMAT_MOD_LINEAR;
+   default:
+   return false;
+   }
+
+}
+
+static bool intel_plane_format_mod_supported(struct drm_plane *plane,
+uint32_t format,
+uint64_t modifier)
+{
+   struct drm_i915_private *dev_priv = to_i915(plane->dev);
+
+   if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID))
+   return false;
+
+   if (INTEL_GEN(dev_priv) >= 9)
+   return skl_mod_supported(format, modifier);
+   else if (INTEL_GEN(dev_priv) >= 4)
+   return i965_mod_supported(format, modifier);
+   else
+   return i8xx_mod_supported(format, modifier);
+
+   return false;
+}
+
 const struct drm_plane_funcs intel_plane_funcs = {
.update_plane = drm_atomic_helper_update_plane,
.disable_plane = drm_atomic_helper_disable_plane,
@@ -13462,6 +13553,7 @@ const struct drm_plane_funcs intel_plane_funcs = {
.atomic_set_property = intel_plane_atomic_set_property,
.atomic_duplicate_state = intel_plane_duplicate_state,
.atomic_destroy_state = intel_plane_destroy_state,
+   .format_mod_supported = intel_plane_format_mod_supported,
 };
 
 static int
@@ -13598,6 +13690,7 @@ static const struct drm_plane_funcs 
intel_cursor_plane_funcs = {

Re: [Intel-gfx] [PATCH 15/16] drm/vblank: Simplify the get_scanout_position helper hook

[kbuild test robot]

Hi Daniel,

[auto build test WARNING on drm/drm-next]
[cannot apply to v4.11-rc3 next-20170324]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Daniel-Vetter/more-drmP-h-cleanup/20170325-030940
base:   git://people.freedesktop.org/~airlied/linux.git drm-next


coccinelle warnings: (new ones prefixed by >>)

>> drivers/gpu/drm/nouveau/nouveau_display.c:154:8-9: WARNING: return of 0/1 in 
>> function 'nouveau_display_scanoutpos' with return type bool

Please review and possibly fold the followup patch.

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation
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[Intel-gfx] [PATCH] drm/vblank: fix boolreturn.cocci warnings

[kbuild test robot]

drivers/gpu/drm/nouveau/nouveau_display.c:154:8-9: WARNING: return of 0/1 in 
function 'nouveau_display_scanoutpos' with return type bool

 Return statements in functions returning bool should use
 true/false instead of 1/0.
Generated by: scripts/coccinelle/misc/boolreturn.cocci

CC: Daniel Vetter 
Signed-off-by: Fengguang Wu 
---

 nouveau_display.c |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

--- a/drivers/gpu/drm/nouveau/nouveau_display.c
+++ b/drivers/gpu/drm/nouveau/nouveau_display.c
@@ -151,7 +151,7 @@ nouveau_display_scanoutpos(struct drm_de
}
}
 
-   return 0;
+   return false;
 }
 
 static void
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Re: [Intel-gfx] [PATCH 1/3] drm/i915: Fixup intel_write_status_page() for old CPUs without clflush

[Ville Syrjälä]

On Fri, Mar 24, 2017 at 09:04:45PM +, Chris Wilson wrote:
> On Fri, Mar 24, 2017 at 10:53:18PM +0200, Ville Syrjälä wrote:
> > On Fri, Mar 24, 2017 at 09:05:13PM +0200, Ville Syrjälä wrote:
> > > Unfortunately the GPU still dies as soon as I fire up glxgears. 4.9
> > > seems to be working just fine, so looks like a kernel regression.
> > 
> > And bisected down to
> > 
> > commit 944397f04f24eaf05125896dcb601c0e1c917879
> > Author: Chris Wilson 
> > Date:   Mon Jan 9 16:16:11 2017 +
> > 
> > drm/i915: Store required fence size/alignment for GGTT vma
> 
> That was a surprise. The last kernel I glanced at my i845 was an
> v4.11-rc2, so it had a chance of hitting the same.
> 
> Can you send me the error state?

Attached.

-- 
Ville Syrjälä
Intel OTC
GPU HANG: ecode 2:0:0x02b11081, in X [2769], reason: Hang on render ring, 
action: reset
Kernel: 4.10.0-rc2-alm-bisect-7-g944397f04f24
Time: 1490388786 s 205105 us
Boottime: 130 s 798388 us
Uptime: 25 s 70614 us
is_mobile: yes
is_lp: no
is_alpha_support: no
has_64bit_reloc: no
has_aliasing_ppgtt: no
has_csr: no
has_ddi: no
has_decoupled_mmio: no
has_dp_mst: no
has_fbc: no
has_fpga_dbg: no
has_full_ppgtt: no
has_full_48bit_ppgtt: no
has_gmbus_irq: no
has_gmch_display: yes
has_guc: no
has_hotplug: no
has_hw_contexts: no
has_l3_dpf: no
has_llc: no
has_logical_ring_contexts: no
has_overlay: yes
has_pipe_cxsr: no
has_pooled_eu: no
has_psr: no
has_rc6: no
has_rc6p: no
has_resource_streamer: no
has_runtime_pm: no
has_snoop: yes
cursor_needs_physical: yes
hws_needs_physical: yes
overlay_needs_physical: yes
supports_tv: no
Active process (on ring render): X [2769], context bans 0
Reset count: 0
Suspend count: 0
Platform: I830
PCI ID: 0x3577
PCI Revision: 0x04
PCI Subsystem: 10cf:113c
IOMMU enabled?: -1
EIR: 0x
IER: 0x0052
PGTBL_ER: 0x
FORCEWAKE: 0x
DERRMR: 0x
CCID: 0x
Missed interrupts: 0x
  fence[0] = 00400241
  fence[1] = 00800351
  fence[2] = 
  fence[3] = 
  fence[4] = 
  fence[5] = 
  fence[6] = 
  fence[7] = 
render command stream:
  START: 0x3000
  HEAD:  0x040c [0x03c0]
  TAIL:  0x0420 [0x0410, 0x0420]
  CTL:   0x0001f001
  MODE:  0x
  HWS:   0x
  ACTHD: 0x 040c
  IPEIR: 0x
  IPEHR: 0x0200
  INSTDONE: 0x00b11081
  batch: [0x_003ff000, 0x_0040]
  INSTPM: 0x
  FADDR: 0x 
  seqno: 0x000a
  last_seqno: 0x000b
  waiting: yes
  ring->head: 0x
  ring->tail: 0x0420
  hangcheck stall: yes
  hangcheck action: dead
  hangcheck action timestamp: 4294914624, 930090 ms ago
Active (render ring) [3]:
_003ff000 4096 7e 00 [ 0b 00 00 00 00 ] 00 dirty uncached
_07cbf000  3145728 02 00 [ 0b 00 00 00 00 ] 00 X uncached (name: 3)
_0040  1572864 36 00 [ 0b 00 00 00 00 ] 00 X dirty uncached 
(fence: 0)
Pinned (global) [5]:
_07cbf000  3145728 02 00 [ 0b 00 00 00 00 ] 00 X uncached (name: 3)
_0040  1572864 36 00 [ 0b 00 00 00 00 ] 00 X dirty uncached 
(fence: 0)
_3000   131072 40 40 [ 00 00 00 00 00 ] 00 dirty uncached
_07fbf000   262144 41 00 [ 00 00 00 00 00 ] 00 uncached
_00023000  3145728 77 00 [ 00 00 00 00 00 ] 00 dirty uncached 
(name: 1)
render ring (submitted by X [2769], bans 0) --- gtt_offset = 0x 003ff000

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Fixup intel_write_status_page() for old CPUs without clflush

[Chris Wilson]

On Fri, Mar 24, 2017 at 10:53:18PM +0200, Ville Syrjälä wrote:
> On Fri, Mar 24, 2017 at 09:05:13PM +0200, Ville Syrjälä wrote:
> > Unfortunately the GPU still dies as soon as I fire up glxgears. 4.9
> > seems to be working just fine, so looks like a kernel regression.
> 
> And bisected down to
> 
> commit 944397f04f24eaf05125896dcb601c0e1c917879
> Author: Chris Wilson 
> Date:   Mon Jan 9 16:16:11 2017 +
> 
> drm/i915: Store required fence size/alignment for GGTT vma

That was a surprise. The last kernel I glanced at my i845 was an
v4.11-rc2, so it had a chance of hitting the same.

Can you send me the error state?
-Chris

-- 
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Re: [Intel-gfx] [PATCH 1/3] drm/i915: Fixup intel_write_status_page() for old CPUs without clflush

[Ville Syrjälä]

On Fri, Mar 24, 2017 at 09:05:13PM +0200, Ville Syrjälä wrote:
> On Fri, Mar 24, 2017 at 04:35:38PM +, Chris Wilson wrote:
> > Note all of our target platforms have clflush. For those without, just
> > assume the status page is sufficiently coherent that we do not need our
> > paranoia.
> > 
> > Reported-by: Ville Syrjälä 
> > Fixes: 14a6bbf9e535 ("drm/i915: Replace irq_seqno_barrier on hws write with 
> > a clflush")
> > Signed-off-by: Chris Wilson 
> > Cc: Mika Kuoppala 
> > Cc: Ville Syrjälä 
> > ---
> >  drivers/gpu/drm/i915/intel_ringbuffer.h | 22 +++---
> >  1 file changed, 15 insertions(+), 7 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h 
> > b/drivers/gpu/drm/i915/intel_ringbuffer.h
> > index 2ecb41788fb6..b5ce6692ed8a 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> > @@ -454,14 +454,22 @@ intel_read_status_page(struct intel_engine_cs 
> > *engine, int reg)
> >  }
> >  
> >  static inline void
> > -intel_write_status_page(struct intel_engine_cs *engine,
> > -   int reg, u32 value)
> > +intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value)
> >  {
> > -   mb();
> > -   clflush(>status_page.page_addr[reg]);
> > -   engine->status_page.page_addr[reg] = value;
> > -   clflush(>status_page.page_addr[reg]);
> > -   mb();
> > +   /* Writing into the status page should be done sparingly. Since
> > +* we do when we are uncertain of the device state, we take a bit
> > +* if extra paranoia to try and ensure that the HWS takes the value
> > +* we give and that it doesn't end up trapped inside the CPU!
> > +*/
> > +   if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
> > +   mb();
> > +   clflush(>status_page.page_addr[reg]);
> > +   engine->status_page.page_addr[reg] = value;
> > +   clflush(>status_page.page_addr[reg]);
> > +   mb();
> > +   } else {
> > +   WRITE_ONCE(engine->status_page.page_addr[reg], value);
> > +   }
> 
> Fixes the illegal opcode explosion.
> Tested-by: Ville Syrjälä 
> 
> Unfortunately the GPU still dies as soon as I fire up glxgears. 4.9
> seems to be working just fine, so looks like a kernel regression.

And bisected down to

commit 944397f04f24eaf05125896dcb601c0e1c917879
Author: Chris Wilson 
Date:   Mon Jan 9 16:16:11 2017 +

drm/i915: Store required fence size/alignment for GGTT vma


Doesn't revert cleanly so can't tell whether there are other
issues piled on top or not.

-- 
Ville Syrjälä
Intel OTC
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Re: [Intel-gfx] [PATCH v10 3/6] drm/edid: detect SCDC support in HF-VSDB

[Daniel Vetter]

On Mon, Mar 13, 2017 at 12:24 PM, Shashank Sharma
 wrote:
> +/**
> + * struct drm_hdmi_info - runtime information about the connected HDMI sink
> + *
> + * Describes if a given display supports advanced HDMI 2.0 features.
> + * This information is available in CEA-861-F extension blocks (like 
> HF-VSDB).
> + */
> +struct drm_hdmi_info {
> +   struct drm_scdc scdc;

This creates a new warning when building docs. Please fix.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH 1/3] drm/i915: Fixup intel_write_status_page() for old CPUs without clflush

[Ville Syrjälä]

On Fri, Mar 24, 2017 at 04:35:38PM +, Chris Wilson wrote:
> Note all of our target platforms have clflush. For those without, just
> assume the status page is sufficiently coherent that we do not need our
> paranoia.
> 
> Reported-by: Ville Syrjälä 
> Fixes: 14a6bbf9e535 ("drm/i915: Replace irq_seqno_barrier on hws write with a 
> clflush")
> Signed-off-by: Chris Wilson 
> Cc: Mika Kuoppala 
> Cc: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/intel_ringbuffer.h | 22 +++---
>  1 file changed, 15 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h 
> b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index 2ecb41788fb6..b5ce6692ed8a 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -454,14 +454,22 @@ intel_read_status_page(struct intel_engine_cs *engine, 
> int reg)
>  }
>  
>  static inline void
> -intel_write_status_page(struct intel_engine_cs *engine,
> - int reg, u32 value)
> +intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value)
>  {
> - mb();
> - clflush(>status_page.page_addr[reg]);
> - engine->status_page.page_addr[reg] = value;
> - clflush(>status_page.page_addr[reg]);
> - mb();
> + /* Writing into the status page should be done sparingly. Since
> +  * we do when we are uncertain of the device state, we take a bit
> +  * if extra paranoia to try and ensure that the HWS takes the value
> +  * we give and that it doesn't end up trapped inside the CPU!
> +  */
> + if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
> + mb();
> + clflush(>status_page.page_addr[reg]);
> + engine->status_page.page_addr[reg] = value;
> + clflush(>status_page.page_addr[reg]);
> + mb();
> + } else {
> + WRITE_ONCE(engine->status_page.page_addr[reg], value);
> + }

Fixes the illegal opcode explosion.
Tested-by: Ville Syrjälä 

Unfortunately the GPU still dies as soon as I fire up glxgears. 4.9
seems to be working just fine, so looks like a kernel regression.

>  }
>  
>  /*
> -- 
> 2.11.0

-- 
Ville Syrjälä
Intel OTC
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Re: [Intel-gfx] [PATCH] drm/i915: Reduce Data Link N value for 1 lane DP->hdmi converters

[Clint Taylor]

On 03/24/2017 04:25 AM, Jani Nikula wrote:

On Thu, 23 Mar 2017, Clint Taylor  wrote:

I would prefer a solution for B (rules for M/N), but the code doesn't
appear to be broken and I don't believe we should "Fix" something that
is working. The device also works by changing the roundup_pow_of_two()
to rounddown_pow_of_two() however that would apply the change to every
device connected.


Looking at this again, the problem must be in the (external) link M/N,
not (internal) data M/N. Thus it's only about the pixel clock / link
clock ratio. Right?



Correct, Pixel/Link clock ratio only.


With current code link N exceeds 0x8 only when link clock >= 54
kHz. Except for the eDP intermediate link clocks, at least the four
least significant bits are always zero. But just one bit shift right
would be enough to bring even the DP 1.4 81 kHz link clock under
0x8 link N. The pixel clock for modes that require a link clock >=
54 kHz would also have several least significant bits zero.

Unless the user provides a mode with an odd pixel clock value, we can
reduce the numbers to reach the goal, with no loss in precision, and it
doesn't even feel like a hack. The DP spec even mentions sources making
choices that "allow for static and relatively small Mvid and Nvid
values".


As long as the precision is maintained a lower value should be fine.


Of course, all of this hinges on the problem being specific to the link
M/N, and independent of data M/N.

BR,
Jani.


diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 9a28a8917dc1..55bb6cf2a2d3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6337,6 +6337,15 @@ intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
 static void compute_m_n(unsigned int m, unsigned int n,
uint32_t *ret_m, uint32_t *ret_n)
 {
+   /*
+* Reduce M/N as much as possible without loss in precision. Several DP
+* dongles in particular seem to be fussy about too large M/N values.
+*/
+   while ((m & 1) == 0 && (n & 1) == 0) {
+   m >>= 1;
+   n >>= 1;
+   }
+
*ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
*ret_m = div_u64((uint64_t) m * *ret_n, n);
intel_reduce_m_n_ratio(ret_m, ret_n);
---

And the hack on top that ensures we're below 0x8 link N independent
of the pixel clock. Note that the only loss in precision here is the one
bit in pixel clock; the other values passed in will always be even.

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 55bb6cf2a2d3..b51b836b9538 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6341,6 +6341,8 @@ static void compute_m_n(unsigned int m, unsigned int n,
 * Reduce M/N as much as possible without loss in precision. Several DP
 * dongles in particular seem to be fussy about too large M/N values.
 */
+   m >>= 1;
+   n >>= 1;
while ((m & 1) == 0 && (n & 1) == 0) {
m >>= 1;
n >>= 1;





The above code at 1 lane @ 5.4 Ghz 1080P@60 (148.400Mhz pixel clock) 
makes GMCH Data N,M = 0x4, 0x34CCC and Link N,M = 0x4, 0x11999. 
The offending dongle appears to work fine with the new values as 
expected. I saw Nvid values of 0x1 at 2048x1152 and the dongle still 
worked.


-Clint


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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2] drm: Make the decision to keep vblank irq enabled earlier (rev3)

[Patchwork]

== Series Details ==

Series: series starting with [v2] drm: Make the decision to keep vblank irq 
enabled earlier (rev3)
URL   : https://patchwork.freedesktop.org/series/21318/
State : success

== Summary ==

Series 21318v3 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/21318/revisions/3/mbox/

fi-bdw-5557u total:278  pass:267  dwarn:0   dfail:0   fail:0   skip:11  
time: 463s
fi-bdw-gvtdvmtotal:278  pass:256  dwarn:8   dfail:0   fail:0   skip:14  
time: 461s
fi-bsw-n3050 total:278  pass:239  dwarn:0   dfail:0   fail:0   skip:39  
time: 592s
fi-bxt-j4205 total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19  
time: 542s
fi-bxt-t5700 total:278  pass:258  dwarn:0   dfail:0   fail:0   skip:20  
time: 564s
fi-byt-j1900 total:278  pass:251  dwarn:0   dfail:0   fail:0   skip:27  
time: 505s
fi-byt-n2820 total:278  pass:247  dwarn:0   dfail:0   fail:0   skip:31  
time: 508s
fi-hsw-4770  total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time: 436s
fi-hsw-4770r total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time: 427s
fi-ilk-650   total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50  
time: 442s
fi-ivb-3520m total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time: 513s
fi-ivb-3770  total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time: 514s
fi-kbl-7500u total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time: 488s
fi-skl-6260u total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time: 495s
fi-skl-6700hqtotal:278  pass:261  dwarn:0   dfail:0   fail:0   skip:17  
time: 599s
fi-skl-6700k total:278  pass:256  dwarn:4   dfail:0   fail:0   skip:18  
time: 481s
fi-skl-6770hqtotal:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time: 526s
fi-skl-gvtdvmtotal:278  pass:265  dwarn:0   dfail:0   fail:0   skip:13  
time: 462s
fi-snb-2520m total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  
time: 552s
fi-snb-2600  total:278  pass:249  dwarn:0   dfail:0   fail:0   skip:29  
time: 416s

81750750fbd26d08f5744e5fd12cb3e8e7425805 drm-tip: 2017y-03m-24d-17h-11m-46s UTC 
integration manifest
d267c1a drm: Peek at the current counter/timestamp for vblank queries
a02877e drm: Make the decision to keep vblank irq enabled earlier

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4298/
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[Intel-gfx] [PATCH v2] drm: Make the decision to keep vblank irq enabled earlier

[Chris Wilson]

We want to provide the vblank irq shadow for pageflip events as well as
vblank queries. Such events are completed within the vblank interrupt
handler, and so the current check for disabling the irq will disable it
from with the same interrupt as the last pageflip event. If we move the
decision on whether to disable the irq (based on there no being no
remaining vblank events, i.e. vblank->refcount == 0) to before we signal
the events, we will only disable the irq on the interrupt after the last
event was signaled. In the normal course of events, this will keep the
vblank irq enabled for the entire flip sequence whereas before it would
flip-flop around every interrupt.

v2: Move the disable_fn() call outside of the vblank_event_lock.

Signed-off-by: Chris Wilson 
Cc: Ville Syrjälä 
Cc: Daniel Vetter 
Cc: Michel Dänzer 
Cc: Laurent Pinchart 
Cc: Dave Airlie ,
Cc: Mario Kleiner 
Reviewed-by: Ville Syrjälä  #v1
Reviewed-by: Mario Kleiner  #v1
---
 drivers/gpu/drm/drm_irq.c | 20 
 1 file changed, 12 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/drm_irq.c b/drivers/gpu/drm/drm_irq.c
index 5b77057e91ca..a511597580d8 100644
--- a/drivers/gpu/drm/drm_irq.c
+++ b/drivers/gpu/drm/drm_irq.c
@@ -1741,6 +1741,7 @@ bool drm_handle_vblank(struct drm_device *dev, unsigned 
int pipe)
 {
struct drm_vblank_crtc *vblank = >vblank[pipe];
unsigned long irqflags;
+   bool disable_irq;
 
if (WARN_ON_ONCE(!dev->num_crtcs))
return false;
@@ -1768,20 +1769,23 @@ bool drm_handle_vblank(struct drm_device *dev, unsigned 
int pipe)
spin_unlock(>vblank_time_lock);
 
wake_up(>queue);
-   drm_handle_vblank_events(dev, pipe);
 
/* With instant-off, we defer disabling the interrupt until after
-* we finish processing the following vblank. The disable has to
-* be last (after drm_handle_vblank_events) so that the timestamp
-* is always accurate.
+* we finish processing the following vblank after all events have
+* been signaled. The disable has to be last (after
+* drm_handle_vblank_events) so that the timestamp is always accurate.
 */
-   if (dev->vblank_disable_immediate &&
-   drm_vblank_offdelay > 0 &&
-   !atomic_read(>refcount))
-   vblank_disable_fn((unsigned long)vblank);
+   disable_irq = (dev->vblank_disable_immediate &&
+  drm_vblank_offdelay > 0 &&
+  !atomic_read(>refcount));
+
+   drm_handle_vblank_events(dev, pipe);
 
spin_unlock_irqrestore(>event_lock, irqflags);
 
+   if (disable_irq)
+   vblank_disable_fn((unsigned long)vblank);
+
return true;
 }
 EXPORT_SYMBOL(drm_handle_vblank);
-- 
2.11.0

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Re: [Intel-gfx] [PATCH] drm: Make the decision to keep vblank irq enabled earlier

[Chris Wilson]

On Fri, Mar 24, 2017 at 04:16:28AM +0100, Mario Kleiner wrote:
> Looks good to me. As a further optimization, i think we could move
> the vblank_disable_fn() call outside/below the
> spin_unlock_irqrestore for event_lock, as vblank_disable_fn()
> doesn't need any locks held at call time, so slightly reduce
> event_lock hold time. Don't know if it is worth it.

Hmm, I was cautious since I don't trust myself around the vbl spinlocks.
But yes, the vblank->refcount is controlled by vbl_lock and that is
checked inside the disable callback, so we can move it out from the
vblank_event_lock.
-Chris

-- 
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Limit number of reads to stabilize rc6 counter reads

[Patchwork]

== Series Details ==

Series: drm/i915: Limit number of reads to stabilize rc6 counter reads
URL   : https://patchwork.freedesktop.org/series/21843/
State : success

== Summary ==

Series 21843v1 drm/i915: Limit number of reads to stabilize rc6 counter reads
https://patchwork.freedesktop.org/api/1.0/series/21843/revisions/1/mbox/

fi-bdw-5557u total:278  pass:267  dwarn:0   dfail:0   fail:0   skip:11  
time: 459s
fi-bdw-gvtdvmtotal:278  pass:256  dwarn:8   dfail:0   fail:0   skip:14  
time: 457s
fi-bsw-n3050 total:278  pass:239  dwarn:0   dfail:0   fail:0   skip:39  
time: 582s
fi-bxt-j4205 total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19  
time: 539s
fi-bxt-t5700 total:278  pass:258  dwarn:0   dfail:0   fail:0   skip:20  
time: 577s
fi-byt-j1900 total:278  pass:251  dwarn:0   dfail:0   fail:0   skip:27  
time: 515s
fi-hsw-4770  total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time: 437s
fi-hsw-4770r total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time: 431s
fi-ilk-650   total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50  
time: 438s
fi-ivb-3520m total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time: 511s
fi-ivb-3770  total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time: 513s
fi-kbl-7500u total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time: 484s
fi-skl-6260u total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time: 483s
fi-skl-6700hqtotal:278  pass:261  dwarn:0   dfail:0   fail:0   skip:17  
time: 598s
fi-skl-6700k total:278  pass:256  dwarn:4   dfail:0   fail:0   skip:18  
time: 496s
fi-skl-6770hqtotal:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time: 515s
fi-skl-gvtdvmtotal:278  pass:265  dwarn:0   dfail:0   fail:0   skip:13  
time: 457s
fi-snb-2520m total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  
time: 545s
fi-snb-2600  total:278  pass:249  dwarn:0   dfail:0   fail:0   skip:29  
time: 429s
fi-byt-n2820 failed to collect. IGT log at Patchwork_4297/fi-byt-n2820/igt.log

286b64375ffcd1fdae8427f6fdae7af6e043a641 drm-tip: 2017y-03m-24d-15h-59m-46s UTC 
integration manifest
42dcfbb drm/i915: Limit number of reads to stabilize rc6 counter reads

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4297/
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Re: [Intel-gfx] [PATCH 1/2] drm/i915: Disable MI_SET_CONTEXT psmi w/a for bdw

[Chris Wilson]

On Fri, Mar 24, 2017 at 05:01:56PM +0100, Michał Winiarski wrote:
> On Fri, Mar 24, 2017 at 03:17:23PM +, Chris Wilson wrote:
> > The current w/a for the gen7 psmi related hangs doesn't apply to bdw, so
> > disable it if using bdw ringbuffer submission.
> > 
> > Signed-off-by: Chris Wilson 
> > ---
> >  drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
> > b/drivers/gpu/drm/i915/i915_gem_context.c
> > index e8dc3e74c093..68dc81aee2f1 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_context.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> > @@ -660,7 +660,7 @@ mi_set_context(struct drm_i915_gem_request *req, u32 
> > flags)
> > enum intel_engine_id id;
> > const int num_rings =
> > /* Use an extended w/a on ivb+ if signalling from other rings */
> 
> The comment also needs updating, we're only using extended w/a (not just
> disabling arbitration) for gen7.
> 
> With that:
> 
> Reviewed-by: Michał Winiarski 

Tweaked and applied. Now I can delete working code in good conscience!
-Chris

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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Fixup intel_write_status_page() for old CPUs without clflush

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915: Fixup intel_write_status_page() 
for old CPUs without clflush
URL   : https://patchwork.freedesktop.org/series/21842/
State : success

== Summary ==

Series 21842v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/21842/revisions/1/mbox/

fi-bdw-5557u total:278  pass:267  dwarn:0   dfail:0   fail:0   skip:11  
time: 460s
fi-bdw-gvtdvmtotal:278  pass:256  dwarn:8   dfail:0   fail:0   skip:14  
time: 459s
fi-bsw-n3050 total:278  pass:239  dwarn:0   dfail:0   fail:0   skip:39  
time: 584s
fi-bxt-j4205 total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19  
time: 543s
fi-bxt-t5700 total:278  pass:258  dwarn:0   dfail:0   fail:0   skip:20  
time: 574s
fi-byt-j1900 total:278  pass:251  dwarn:0   dfail:0   fail:0   skip:27  
time: 512s
fi-byt-n2820 total:278  pass:247  dwarn:0   dfail:0   fail:0   skip:31  
time: 502s
fi-hsw-4770  total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time: 431s
fi-hsw-4770r total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time: 433s
fi-ilk-650   total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50  
time: 439s
fi-ivb-3520m total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time: 509s
fi-ivb-3770  total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time: 487s
fi-kbl-7500u total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time: 484s
fi-skl-6260u total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time: 489s
fi-skl-6700hqtotal:278  pass:261  dwarn:0   dfail:0   fail:0   skip:17  
time: 598s
fi-skl-6700k total:278  pass:256  dwarn:4   dfail:0   fail:0   skip:18  
time: 489s
fi-skl-6770hqtotal:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time: 518s
fi-skl-gvtdvmtotal:278  pass:265  dwarn:0   dfail:0   fail:0   skip:13  
time: 461s
fi-snb-2520m total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  
time: 550s
fi-snb-2600  total:278  pass:249  dwarn:0   dfail:0   fail:0   skip:29  
time: 416s

286b64375ffcd1fdae8427f6fdae7af6e043a641 drm-tip: 2017y-03m-24d-15h-59m-46s UTC 
integration manifest
ab76e0b drm/i915: Use BIT() for computing the engine's flag
703fd59 drm/i915: Remove unused intel_flush_status_page()
517b5e8f drm/i915: Fixup intel_write_status_page() for old CPUs without clflush

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4296/
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Re: [Intel-gfx] [PATCH 1/3] drm/i915: Fixup intel_write_status_page() for old CPUs without clflush

[Chris Wilson]

On Fri, Mar 24, 2017 at 04:35:38PM +, Chris Wilson wrote:
> Note all of our target platforms have clflush. For those without, just
s/Note/Not/

> assume the status page is sufficiently coherent that we do not need our
> paranoia.
-Chris

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[Intel-gfx] [PATCH] drm/i915: Limit number of reads to stabilize rc6 counter reads

[Chris Wilson]

We have only 8bits of precise timestamps in which to complete our
upper/load reads, along with the switch between precision. This is not
always enough time to read the upper counter twice within the same time
slice, leading to hard lockups. Limit the number of times to prevent
an inifite loop (my fault for assuming we would have no trouble doing
the write + reads fast enough).

Fixes: 47c21d9a1a7b ("drm/i915: Extend vlv/chv residency resolution")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100377
Signed-off-by: Chris Wilson 
Cc: Ville Syrjälä 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/intel_pm.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index aece0ff88a5d..63ce70329e6e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8355,6 +8355,7 @@ static u64 vlv_residency_raw(struct drm_i915_private 
*dev_priv,
 const i915_reg_t reg)
 {
u32 lower, upper, tmp;
+   int loop = 2;
 
/* The register accessed do not need forcewake. We borrow
 * uncore lock to prevent concurrent access to range reg.
@@ -8383,7 +8384,7 @@ static u64 vlv_residency_raw(struct drm_i915_private 
*dev_priv,
I915_WRITE_FW(VLV_COUNTER_CONTROL,
  _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
upper = I915_READ_FW(reg);
-   } while (upper != tmp);
+   } while (upper != tmp && --loop);
 
/* Everywhere else we always use VLV_COUNTER_CONTROL with the
 * VLV_COUNT_RANGE_HIGH bit set - so it is safe to leave it set
-- 
2.11.0

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[Intel-gfx] [PATCH 1/3] drm/i915: Fixup intel_write_status_page() for old CPUs without clflush

[Chris Wilson]

Note all of our target platforms have clflush. For those without, just
assume the status page is sufficiently coherent that we do not need our
paranoia.

Reported-by: Ville Syrjälä 
Fixes: 14a6bbf9e535 ("drm/i915: Replace irq_seqno_barrier on hws write with a 
clflush")
Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_ringbuffer.h | 22 +++---
 1 file changed, 15 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h 
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 2ecb41788fb6..b5ce6692ed8a 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -454,14 +454,22 @@ intel_read_status_page(struct intel_engine_cs *engine, 
int reg)
 }
 
 static inline void
-intel_write_status_page(struct intel_engine_cs *engine,
-   int reg, u32 value)
+intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value)
 {
-   mb();
-   clflush(>status_page.page_addr[reg]);
-   engine->status_page.page_addr[reg] = value;
-   clflush(>status_page.page_addr[reg]);
-   mb();
+   /* Writing into the status page should be done sparingly. Since
+* we do when we are uncertain of the device state, we take a bit
+* if extra paranoia to try and ensure that the HWS takes the value
+* we give and that it doesn't end up trapped inside the CPU!
+*/
+   if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
+   mb();
+   clflush(>status_page.page_addr[reg]);
+   engine->status_page.page_addr[reg] = value;
+   clflush(>status_page.page_addr[reg]);
+   mb();
+   } else {
+   WRITE_ONCE(engine->status_page.page_addr[reg], value);
+   }
 }
 
 /*
-- 
2.11.0

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Re: [Intel-gfx] [PATCH] drm/i915/guc: Refactor the retrieval of guc_process_desc

[Chris Wilson]

On Fri, Mar 24, 2017 at 01:11:20PM +0100, Michał Winiarski wrote:
> On Thu, Mar 23, 2017 at 11:00:00PM +, Chris Wilson wrote:
> > Move the common "client->vaddr + client->proc_desc_offset" to its own
> > function, __get_process_desc() to match the newly established pattern.
> > 
> > Signed-off-by: Chris Wilson 
> 
> Reviewed-by: Michał Winiarski 
Applied, thanks.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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[Intel-gfx] [PATCH 2/3] drm/i915: Remove unused intel_flush_status_page()

[Chris Wilson]

intel_flush_status_page() is defunct since commit f8dd2934c4ec
("drm/i915: Remove BXT incoherent seqno write workaround"), time to
remove it.

Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Joonas Lahtinen 
Cc: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_ringbuffer.h | 8 
 1 file changed, 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h 
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index b5ce6692ed8a..93be3bd99a38 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -438,14 +438,6 @@ intel_engine_flag(const struct intel_engine_cs *engine)
return 1 << engine->id;
 }
 
-static inline void
-intel_flush_status_page(struct intel_engine_cs *engine, int reg)
-{
-   mb();
-   clflush(>status_page.page_addr[reg]);
-   mb();
-}
-
 static inline u32
 intel_read_status_page(struct intel_engine_cs *engine, int reg)
 {
-- 
2.11.0

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[Intel-gfx] [PATCH 3/3] drm/i915: Use BIT() for computing the engine's flag

[Chris Wilson]

Since the engine's flag is just the bit of its id, use BIT().

Signed-off-by: Chris Wilson 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/intel_ringbuffer.h | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h 
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 93be3bd99a38..3aae2c4f9ca3 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -432,10 +432,9 @@ struct intel_engine_cs {
u32 (*get_cmd_length_mask)(u32 cmd_header);
 };
 
-static inline unsigned
-intel_engine_flag(const struct intel_engine_cs *engine)
+static inline unsigned intel_engine_flag(const struct intel_engine_cs *engine)
 {
-   return 1 << engine->id;
+   return BIT(engine->id);
 }
 
 static inline u32
-- 
2.11.0

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[Intel-gfx] [dim PATCH 5/7] dim: remove apply-igt subcommand

[Jani Nikula]

Out of scope for dim, and relies on hard coded paths. People can add the
function to their .dimrc if needed.

Signed-off-by: Jani Nikula 
---
 dim | 7 ---
 dim.rst | 4 
 2 files changed, 11 deletions(-)

diff --git a/dim b/dim
index fc72cd619dbd..b7d6b2aafff6 100755
--- a/dim
+++ b/dim
@@ -915,13 +915,6 @@ function dim_magic_rebase_resolve
git rebase --continue
 }
 
-dim_alias_ai=apply-igt
-function dim_apply_igt
-{
-   cd ~/xorg/intel-gpu-tools/
-   git am --whitespace=fix -3 -s
-}
-
 dim_alias_mp=magic-patch
 function dim_magic_patch
 {
diff --git a/dim.rst b/dim.rst
index aa1c5d62606e..1fc64e4799a4 100644
--- a/dim.rst
+++ b/dim.rst
@@ -240,10 +240,6 @@ apply-resolved
 Compile-test the current tree and if successfully resolve a
 confilicted git am. Also runs the patch checker afterwards.
 
-apply-igt
--
-Apply a patch to the i-g-t repository.
-
 tc *commit-ish*
 ---
 Print the oldest Linux kernel release or -rc tag that contains the supplied
-- 
2.1.4

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[Intel-gfx] [dim PATCH 3/7] dim: add 'make mancheck' target to check all subcommands have been documented

[Jani Nikula]

Just a simple grep.

Signed-off-by: Jani Nikula 
---
 Makefile | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/Makefile b/Makefile
index c1fe02c1b565..ce283114c4aa 100644
--- a/Makefile
+++ b/Makefile
@@ -32,6 +32,13 @@ SC_EXCLUDE := \
 shellcheck:
shellcheck $(SC_EXCLUDE) dim bash_completion
 
+mancheck:
+   @for cmd in $$(dim list-commands); do \
+   if ! grep -q "^$$cmd" dim.rst; then \
+   echo "$$cmd not documented"; \
+   fi \
+   done
+
 clean:
rm -f drm-intel.html drm-intel-flow.svg dim.html drm-misc.html
 
-- 
2.1.4

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[Intel-gfx] [dim PATCH 6/7] dim: document drm-intel specific shorthands separately from the generic ones

[Jani Nikula]

Hopefully increases clarity for people not working on drm-intel.

Signed-off-by: Jani Nikula 
---
 dim.rst | 57 +
 1 file changed, 29 insertions(+), 28 deletions(-)

diff --git a/dim.rst b/dim.rst
index 1fc64e4799a4..f595f10ab0e7 100644
--- a/dim.rst
+++ b/dim.rst
@@ -139,6 +139,9 @@ Pipes stdin into the fixup patch file for the current 
drm-tip merge.
 
 push-branch branch [*git push arguments*]
 -
+Updates the named branch. Complains if that's not the current branch, assuming
+that patches got merged to the wrong branch. After pushing also updates
+linux-next and drm-tip branches.
 
 push-fixes [*git push arguments*]
 -
@@ -148,31 +151,27 @@ push-next-fixes [*git push arguments*]
 
 push-queued [*git push arguments*]
 --
-
-Updates the named branch, or drm-intel-fixes, drm-intel-next-fixes or the
-drm-intel-next-queued branch respectively. Complains if that's not the current
-branch, assuming that patches got merged to the wrong branch. After pushing 
also
-updates linux-next and drm-tip branches.
+**push-branch** shorthands for *drm-intel-fixes*, *drm-intel-next-fixes*, and
+*drm-intel-next-queued* branches respectively.
 
 checkout *branch*
 -
 Checks out the named branch.
 
-conq
-
-
 cof
 ---
 
 conf
 
-Checks out the drm-intel-fixes branch, dinf or dinq respectively for merging
-patches.
+
+conq
+
+**checkout** shorthands for *drm-intel-fixes*, *drm-intel-next-fixes*, and
+*drm-intel-next-queued* branches respectively.
 
 apply-branch branch [*git am arguments*]
 
-Applys a patch to the given branch, complaining if it is not
-checked out yet.
+Applys a patch to the given branch, complaining if it is not checked out yet.
 
 apply-fixes [*git am arguments*]
 
@@ -182,14 +181,14 @@ apply-next-fixes [*git am arguments*]
 
 apply-queued [*git am arguments*]
 -
-Applies a patch to -fixes, -next-fixes or -next-queued respectively, complains
-if it's not the right branch. Additional arguments are passed to git am.
+**apply-branch** shorthands for *drm-intel-fixes*, *drm-intel-next-fixes*, and
+*drm-intel-next-queued* branches respectively.
 
 extract-tags *branch* [*git-rangeish*]
 --
-
-extract-queued [*git-rangeish*]

+This extracts various tags (eg. Reviwed-by:) from emails and applies them to 
the
+top commit on the given branch. You can give the command a rangeish to add the
+tags from the same email to multiple already applied patches.
 
 extract-fixes [*git-rangeish*]
 --
@@ -197,9 +196,10 @@ extract-fixes [*git-rangeish*]
 extract-next-fixes [*git-rangeish*]
 ---
 
-This extracts various tags (eg. Reviwed-by:) from emails and applies them to 
the
-top commit on the given branch. You can give the comamnd a rangeish to add the
-tags from the same email to multiple already applied patches.
+extract-queued [*git-rangeish*]
+---
+**extract-tags** shorthands for *drm-intel-fixes*, *drm-intel-next-fixes*, and
+*drm-intel-next-queued* branches respectively.
 
 magic-patch [-a]
 
@@ -210,9 +210,7 @@ per-branch workdir model.
 
 add-link *branch*
 -
-
-add-link-queued

+This command adds the Link: tag (for patches that failed to apply directly).
 
 add-link-fixes
 --
@@ -220,7 +218,10 @@ add-link-fixes
 add-link-next-fixes
 ---
 
-This command adds the Link: tag (for patches that failed to apply directly).
+add-link-queued
+---
+**add-link** shorthands for *drm-intel-fixes*, *drm-intel-next-fixes*, and
+*drm-intel-next-queued* branches respectively.
 
 magic-rebase-resolve
 
@@ -282,13 +283,13 @@ regenerated with the same commands if something goes 
wrong.
 
 pull-request-fixes [*upstream*]
 ---
-This is a special case of **pull-request**, with *drm-intel-fixes* as the
-branch and *origin/master* as the default upstream.
+**pull-request** shorthand for *drm-intel-fixes* as the branch and
+*origin/master* as the default upstream.
 
 pull-request-next-fixes [*upstream*]
 
-This is a special case of **pull-request**, with *drm-intel-next-fixes* as
-the branch and *\$DRM_UPSTREAM/drm-next* as the default upstream.
+**pull-request** shorthand for *drm-intel-next-fixes* as the branch and
+*\$DRM_UPSTREAM/drm-next* as the default upstream.
 
 pull-request-next [*upstream*]
 --
-- 
2.1.4

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[Intel-gfx] [dim PATCH 7/7] dim: group command documentation in the man page by target audiences

[Jani Nikula]

Group the man page by:

- commands for developers
- commands for committers and maintainers
- advanced commands for committers and maintainers
- commands for maintainers
- dim help commands.

We have so many commands by now that it should be helpful to group them
a little.

Signed-off-by: Jani Nikula 
---
 dim.rst | 225 
 1 file changed, 113 insertions(+), 112 deletions(-)

diff --git a/dim.rst b/dim.rst
index f595f10ab0e7..22b2e1487d1b 100644
--- a/dim.rst
+++ b/dim.rst
@@ -101,58 +101,72 @@ OPTIONS
 COMMANDS
 
 
-Many of the commands have default aliases. See **dim list-aliases** for the 
list
-of aliases.
+The commands are grouped by target audiences and functionality below. Many of
+the commands have default aliases. See **dim list-aliases** for the list of
+aliases.
 
-setup *prefix*
---
-Setup git maintainer branches in the given prefix.
+COMMANDS FOR DEVELOPERS
+===
 
-update-branches
+tc *commit-ish*
 ---
-Updates all maintainer branches. Useful to synchronize all branches when other
-maintainers and committers pushed patches meanwhile.
+Print the oldest Linux kernel release or -rc tag that contains the supplied
+*commit-ish*, or, if none do, print the upstream branches that contain it.
 
-status
---
+cite *commit-ish*
+-
+Cite the supplied *commit-ish* in format 'sha1 ("commit subject")'.
 
-Lists all branches with unmerged patches, and how many patches are unmerged.
+fixes *commit-ish*
+--
+Print the Fixes: and Cc: lines for the supplied *commit-ish* in the linux 
kernel
+CodingStyle approved format.
 
-rebuild-tip

-Rebuild and push the integration tree.
+checkpatch [*commit-ish* [.. *commit-ish*]]
+---
+Runs the given commit range commit-ish..commit-ish through the check tools.
 
-revert-rerere *rerere-cache-commit-ish*
+If no commit-ish is passed, defaults to HEAD^..HEAD. If one commit-ish is 
passed
+instead of a range, the range commit-ish..HEAD is used.
+
+sparse [*commit-ish* [.. *commit-ish*]]
 ---
+Run sparse on the files changed by the given commit range.
 
-When a stored conflict resolution in the integration tree is wrong, this 
command
-can be used to fix up the mess. First figure out which commit in the
-*rerere-cache* branch contains the bogus conflict resolution, then revert it
-using this command. This ensures the resolution is also purged from any local
-caches, to make sure it doesn't get resurrected. Then run *rebuild-tip* to
-redo the merges, correctly.
+If no commit-ish is passed, defaults to HEAD^..HEAD. If one commit-ish is 
passed
+instead of a range, the range commit-ish..HEAD is used.
 
-cat-to-fixup
-
+checker
+---
+Run sparse on drm/i915.
 
-Pipes stdin into the fixup patch file for the current drm-tip merge.
+retip [*branch*] [*git-rebase option* ...]
+--
+Rebase the given local branch, current branch by default, onto drm-tip. Options
+after the branch will be passed to **git-rebase**.
 
-push-branch branch [*git push arguments*]
--
-Updates the named branch. Complains if that's not the current branch, assuming
-that patches got merged to the wrong branch. After pushing also updates
-linux-next and drm-tip branches.
+COMMANDS FOR COMMITTERS AND MAINTAINERS
+===
 
-push-fixes [*git push arguments*]
--
+setup *prefix*
+--
+Setup git maintainer branches in the given prefix.
 
-push-next-fixes [*git push arguments*]
---
+update-branches
+---
+Updates all maintainer branches. Useful to synchronize all branches when other
+maintainers and committers pushed patches meanwhile.
 
-push-queued [*git push arguments*]
---
-**push-branch** shorthands for *drm-intel-fixes*, *drm-intel-next-fixes*, and
-*drm-intel-next-queued* branches respectively.
+status
+--
+Lists all branches with unmerged patches, and how many patches are unmerged.
+
+cd
+--
+Changes the working directory into the git repository used by the last previous
+branch-specific command. This is implemented as a bash-function to make it
+useful in interactive shells and scripts. Only available when the bash
+completion is sourced.
 
 checkout *branch*
 -
@@ -201,6 +215,43 @@ extract-queued [*git-rangeish*]
 **extract-tags** shorthands for *drm-intel-fixes*, *drm-intel-next-fixes*, and
 *drm-intel-next-queued* branches respectively.
 
+push-branch branch [*git push arguments*]
+-
+Updates the named branch. Complains if that's not the current branch, assuming
+that patches got merged to the wrong branch. After pushing also updates
+linux-next and 

[Intel-gfx] [dim PATCH 4/7] dim: remove aliases from the man page

[Jani Nikula]

Increase clarity. People can list the aliases using 'dim list-aliases'
and add their own.

Signed-off-by: Jani Nikula 
---
 dim.rst | 55 +--
 1 file changed, 29 insertions(+), 26 deletions(-)

diff --git a/dim.rst b/dim.rst
index 1bec3838bace..aa1c5d62606e 100644
--- a/dim.rst
+++ b/dim.rst
@@ -101,6 +101,9 @@ OPTIONS
 COMMANDS
 
 
+Many of the commands have default aliases. See **dim list-aliases** for the 
list
+of aliases.
+
 setup *prefix*
 --
 Setup git maintainer branches in the given prefix.
@@ -137,22 +140,22 @@ Pipes stdin into the fixup patch file for the current 
drm-tip merge.
 push-branch branch [*git push arguments*]
 -
 
-push-fixes|pf [*git push arguments*]
-
+push-fixes [*git push arguments*]
+-
 
-push-next-fixes|pnf [*git push arguments*]
---
+push-next-fixes [*git push arguments*]
+--
 
-push-queued|pq [*git push arguments*]
--
+push-queued [*git push arguments*]
+--
 
 Updates the named branch, or drm-intel-fixes, drm-intel-next-fixes or the
 drm-intel-next-queued branch respectively. Complains if that's not the current
 branch, assuming that patches got merged to the wrong branch. After pushing 
also
 updates linux-next and drm-tip branches.
 
-checkout|co *branch*
-
+checkout *branch*
+-
 Checks out the named branch.
 
 conq
@@ -166,19 +169,19 @@ conf
 Checks out the drm-intel-fixes branch, dinf or dinq respectively for merging
 patches.
 
-apply-branch|ab|sob branch [*git am arguments*]

+apply-branch branch [*git am arguments*]
+
 Applys a patch to the given branch, complaining if it is not
 checked out yet.
 
-apply-fixes|af [*git am arguments*]

+apply-fixes [*git am arguments*]
+
 
-apply-next-fixes|anf [*git am arguments*]
--
+apply-next-fixes [*git am arguments*]
+-
 
-apply-queued|aq [*git am arguments*]
-
+apply-queued [*git am arguments*]
+-
 Applies a patch to -fixes, -next-fixes or -next-queued respectively, complains
 if it's not the right branch. Additional arguments are passed to git am.
 
@@ -198,8 +201,8 @@ This extracts various tags (eg. Reviwed-by:) from emails 
and applies them to the
 top commit on the given branch. You can give the comamnd a rangeish to add the
 tags from the same email to multiple already applied patches.
 
-magic-patch|mp [-a]

+magic-patch [-a]
+
 Apply a patch using patch and then wiggle in any conflicts. When passing the
 option -a automatically changes the working directory into the git repository
 used by the last previous branch-specific command. This is useful with the
@@ -219,8 +222,8 @@ add-link-next-fixes
 
 This command adds the Link: tag (for patches that failed to apply directly).
 
-magic-rebase-resolve|mrr
-
+magic-rebase-resolve
+
 Tries to resolve a rebase conflict by first resetting the tree
 and the using the magic patch tool. Then builds the tree, adds
 any changes with git add -u and continues the rebase.
@@ -232,13 +235,13 @@ branch-specific command. This is implemented as a 
bash-function to make it
 useful in interactive shells and scripts. Only available when the bash
 completion is sourced.
 
-apply-resolved|ar
--
+apply-resolved
+--
 Compile-test the current tree and if successfully resolve a
 confilicted git am. Also runs the patch checker afterwards.
 
-apply-igt|ai
-
+apply-igt
+-
 Apply a patch to the i-g-t repository.
 
 tc *commit-ish*
@@ -320,8 +323,8 @@ remote is up-to-date. Useful if drm-intel-next has been 
changed since the last
 run of the update-next command (e.g. to apply a hotfix before sending out the
 pull request).
 
-checkpatch|check-patch|cp [*commit-ish* [.. *commit-ish*]]
---
+checkpatch [*commit-ish* [.. *commit-ish*]]
+---
 Runs the given commit range commit-ish..commit-ish through the check tools.
 
 If no commit-ish is passed, defaults to HEAD^..HEAD. If one commit-ish is 
passed
-- 
2.1.4

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[Intel-gfx] [dim PATCH 1/7] completion: shellcheck bash completion and fix issues

[Jani Nikula]

Add bash_completion to 'make shellcheck' target, and fix the failures.

Signed-off-by: Jani Nikula 
---
 Makefile|  2 +-
 bash_completion | 13 +++--
 2 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/Makefile b/Makefile
index 30fc3dd3bff8..c1fe02c1b565 100644
--- a/Makefile
+++ b/Makefile
@@ -30,7 +30,7 @@ SC_EXCLUDE := \
-e SC2143
 
 shellcheck:
-   shellcheck $(SC_EXCLUDE) dim
+   shellcheck $(SC_EXCLUDE) dim bash_completion
 
 clean:
rm -f drm-intel.html drm-intel-flow.svg dim.html drm-misc.html
diff --git a/bash_completion b/bash_completion
index 9f659b4ebcce..7dfc4b86cb13 100644
--- a/bash_completion
+++ b/bash_completion
@@ -3,7 +3,7 @@
 dim ()
 {
if [[ "x$1" = "xcd" ]]; then
-   cd `cat ~/.dim-last-path`
+   cd $(cat ~/.dim-last-path) || exit
else
command dim "$@"
fi
@@ -12,6 +12,7 @@ dim ()
 _dim ()
 {
local args arg cur prev words cword split
+   local nightly_branches upstream_branches opts cmds aliasref
 
# require bash-completion with _init_completion
type -t _init_completion >/dev/null 2>&1 || return
@@ -26,18 +27,18 @@ _dim ()
# args = number of arguments
_count_args
 
-   local nightly_branches="$(dim list-branches)"
-   local upstream_branches="$(dim list-upstreams)"
+   nightly_branches="$(dim list-branches)"
+   upstream_branches="$(dim list-upstreams)"
 
if [ -z "${arg}" ]; then
# top level completion
case "${cur}" in
-*)
-   local opts="-d -f -i"
+   opts="-d -f -i"
COMPREPLY=( $(compgen -W "${opts}" -- ${cur}) )
;;
*)
-   local cmds="$(dim list-commands) $(dim 
list-aliases | sed 's/\t.*//')"
+   cmds="$(dim list-commands) $(dim list-aliases | 
sed 's/\t.*//')"
COMPREPLY=( $(compgen -W "${cmds}" -- ${cur}) )
;;
esac
@@ -45,7 +46,7 @@ _dim ()
fi
 
# complete aliases like the actual command
-   local aliasref=$(dim list-aliases | sed -n "s/^${arg}\t\(.*\)/\1/p")
+   aliasref=$(dim list-aliases | sed -n "s/^${arg}\t\(.*\)/\1/p")
if [[ -n "$aliasref" ]]; then
arg="$aliasref"
fi
-- 
2.1.4

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[Intel-gfx] [dim PATCH 2/7] dim: return error exit status on unknown subcommands

[Jani Nikula]

Signed-off-by: Jani Nikula 
---
 dim | 9 +
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/dim b/dim
index 989674ab7a91..fc72cd619dbd 100755
--- a/dim
+++ b/dim
@@ -1840,11 +1840,12 @@ if ! declare -n subcmd=dim_alias_${subcommand//-/_} &> 
/dev/null || \
subcmd="$subcommand"
 fi
 
-# if there's a function by the subcommand name, call it
+# look up the function by the subcommand name
 subcmd_func=dim_${subcmd//-/_}
-if declare -f $subcmd_func >/dev/null; then
-   $subcmd_func "$@"
-else
+if ! declare -f $subcmd_func >/dev/null; then
echoerr "'$subcommand' is not a dim command."
dim_usage
+   exit 1
 fi
+
+$subcmd_func "$@"
-- 
2.1.4

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Re: [Intel-gfx] [PATCH 1/2] drm/i915: Disable MI_SET_CONTEXT psmi w/a for bdw

[Michał Winiarski]

On Fri, Mar 24, 2017 at 03:17:23PM +, Chris Wilson wrote:
> The current w/a for the gen7 psmi related hangs doesn't apply to bdw, so
> disable it if using bdw ringbuffer submission.
> 
> Signed-off-by: Chris Wilson 
> ---
>  drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
> b/drivers/gpu/drm/i915/i915_gem_context.c
> index e8dc3e74c093..68dc81aee2f1 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -660,7 +660,7 @@ mi_set_context(struct drm_i915_gem_request *req, u32 
> flags)
>   enum intel_engine_id id;
>   const int num_rings =
>   /* Use an extended w/a on ivb+ if signalling from other rings */

The comment also needs updating, we're only using extended w/a (not just
disabling arbitration) for gen7.

With that:

Reviewed-by: Michał Winiarski 

-Michał

> - i915.semaphores ?
> + (i915.semaphores && INTEL_GEN(dev_priv) == 7) ?
>   INTEL_INFO(dev_priv)->num_rings - 1 :
>   0;
>   int len;
> -- 
> 2.11.0
> 
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Re: [Intel-gfx] [PATCH] drm/i915/guc: limit forcewake to blitter domain in guc_send

[Chris Wilson]

On Fri, Mar 24, 2017 at 09:12:13PM +0530, Kamble, Sagar A wrote:
>Reviewed-by: Sagar Arun Kamble [1]

and pushed.

Sagar, you might want to turn off sending html email for intel-gfx@.
-Chris

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Re: [Intel-gfx] [PATCH] drm/i915/guc: limit forcewake to blitter domain in guc_send

[Kamble, Sagar A]

Reviewed-by: Sagar Arun Kamble 

On 3/24/2017 8:18 PM, Daniele Ceraolo Spurio wrote:

The forcewake_get call in the guc_send_mmio function was added to
avoid getting and releasing forcewake on each register access.
While this makes sense, all GuC registers are in the blitter range
so no need to wake all the wells.

Signed-off-by: Daniele Ceraolo Spurio 
---
  drivers/gpu/drm/i915/intel_uc.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 4a872cd..e016227 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -245,7 +245,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 
*action, u32 len)
return -EINVAL;
  
  	mutex_lock(>send_mutex);

-   intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+   intel_uncore_forcewake_get(dev_priv, FORCEWAKE_BLITTER);
  
  	dev_priv->guc.action_count += 1;

dev_priv->guc.action_cmd = action[0];
@@ -283,7 +283,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 
*action, u32 len)
}
dev_priv->guc.action_status = status;
  
-	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);

+   intel_uncore_forcewake_put(dev_priv, FORCEWAKE_BLITTER);
mutex_unlock(>send_mutex);
  
  	return ret;


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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: Disable MI_SET_CONTEXT psmi w/a for bdw

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915: Disable MI_SET_CONTEXT psmi w/a 
for bdw
URL   : https://patchwork.freedesktop.org/series/21837/
State : failure

== Summary ==

Series 21837v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/21837/revisions/1/mbox/

Test gem_exec_flush:
Subgroup basic-batch-kernel-default-uc:
pass   -> FAIL   (fi-snb-2600) fdo#17
Test gem_exec_reloc:
Subgroup basic-write-read-noreloc:
pass   -> INCOMPLETE (fi-byt-j1900)
Test gem_exec_suspend:
Subgroup basic-s4-devices:
pass   -> DMESG-WARN (fi-bxt-t5700) fdo#100125

fdo#17 https://bugs.freedesktop.org/show_bug.cgi?id=17
fdo#100125 https://bugs.freedesktop.org/show_bug.cgi?id=100125

fi-bdw-5557u total:278  pass:267  dwarn:0   dfail:0   fail:0   skip:11  
time: 463s
fi-bdw-gvtdvmtotal:278  pass:256  dwarn:8   dfail:0   fail:0   skip:14  
time: 459s
fi-bsw-n3050 total:278  pass:239  dwarn:0   dfail:0   fail:0   skip:39  
time: 582s
fi-bxt-j4205 total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19  
time: 550s
fi-bxt-t5700 total:278  pass:257  dwarn:1   dfail:0   fail:0   skip:20  
time: 568s
fi-byt-j1900 total:88   pass:78   dwarn:0   dfail:0   fail:0   skip:9   
time: 0s
fi-byt-n2820 total:278  pass:247  dwarn:0   dfail:0   fail:0   skip:31  
time: 501s
fi-hsw-4770  total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time: 437s
fi-hsw-4770r total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time: 429s
fi-ilk-650   total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50  
time: 440s
fi-ivb-3520m total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time: 509s
fi-ivb-3770  total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time: 492s
fi-kbl-7500u total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time: 495s
fi-skl-6260u total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time: 494s
fi-skl-6700hqtotal:278  pass:261  dwarn:0   dfail:0   fail:0   skip:17  
time: 594s
fi-skl-6700k total:278  pass:256  dwarn:4   dfail:0   fail:0   skip:18  
time: 489s
fi-skl-6770hqtotal:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time: 521s
fi-skl-gvtdvmtotal:278  pass:265  dwarn:0   dfail:0   fail:0   skip:13  
time: 461s
fi-snb-2520m total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  
time: 549s
fi-snb-2600  total:278  pass:248  dwarn:0   dfail:0   fail:1   skip:29  
time: 432s

fd27e1e4c9b5dc11966b4953432bd6e0510da308 drm-tip: 2017y-03m-24d-08h-39m-20s UTC 
integration manifest
70941c2 drm/i915: Fix semaphore emission for BDW+ RCS ringbuffer emission
613347c drm/i915: Disable MI_SET_CONTEXT psmi w/a for bdw

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4295/
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Re: [Intel-gfx] [PATCH 2/2] drm/i915: Remove obsolete ringbuffer emission for gen8+

[Chris Wilson]

On Fri, Mar 24, 2017 at 09:42:40AM +, Chris Wilson wrote:
> Since removing the module parameter to force selection of ringbuffer
> emission for gen8, the code is defunct. Remove it.

To put the difference into perspective, a couple of microbenchmarks (bdw 
i7-5557u):
ring  execlists
exec continuous nops on all rings:   1.491us2.223us
exec sequential nops on each ring:  12.508us   53.682us
single nop + sync:   9.272us   30.291us

vblank_mode=0 glxgears:~11000fps   ~9000fps
-Chris

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Re: [Intel-gfx] [PATCH 2/2] drm/i915: Fix semaphore emission for BDW+ RCS ringbuffer emission

[Michał Winiarski]

On Fri, Mar 24, 2017 at 03:17:24PM +, Chris Wilson wrote:
> The required number of dwords for semaphore emission on BDW RCS is 8,
> not 6 - leading to ring buffer corruption and immediate GPU hangs when
> using ringbuffer submission.
> 
> Signed-off-by: Chris Wilson 

Reviewed-by: Michał Winiarski 

-Michał

> ---
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
> b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 62756eb2bd4a..4729ac7ac122 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -2117,7 +2117,7 @@ int intel_init_render_ring_buffer(struct 
> intel_engine_cs *engine)
>  
>   num_rings =
>   hweight32(INTEL_INFO(dev_priv)->ring_mask) - 1;
> - engine->emit_breadcrumb_sz += num_rings * 6;
> + engine->emit_breadcrumb_sz += num_rings * 8;
>   }
>   } else if (INTEL_GEN(dev_priv) >= 6) {
>   engine->init_context = intel_rcs_ctx_init;
> -- 
> 2.11.0
> 
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[Intel-gfx] [PATCH 2/2] drm/i915: Fix semaphore emission for BDW+ RCS ringbuffer emission

[Chris Wilson]

The required number of dwords for semaphore emission on BDW RCS is 8,
not 6 - leading to ring buffer corruption and immediate GPU hangs when
using ringbuffer submission.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 62756eb2bd4a..4729ac7ac122 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2117,7 +2117,7 @@ int intel_init_render_ring_buffer(struct intel_engine_cs 
*engine)
 
num_rings =
hweight32(INTEL_INFO(dev_priv)->ring_mask) - 1;
-   engine->emit_breadcrumb_sz += num_rings * 6;
+   engine->emit_breadcrumb_sz += num_rings * 8;
}
} else if (INTEL_GEN(dev_priv) >= 6) {
engine->init_context = intel_rcs_ctx_init;
-- 
2.11.0

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[Intel-gfx] [PATCH 1/2] drm/i915: Disable MI_SET_CONTEXT psmi w/a for bdw

[Chris Wilson]

The current w/a for the gen7 psmi related hangs doesn't apply to bdw, so
disable it if using bdw ringbuffer submission.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index e8dc3e74c093..68dc81aee2f1 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -660,7 +660,7 @@ mi_set_context(struct drm_i915_gem_request *req, u32 flags)
enum intel_engine_id id;
const int num_rings =
/* Use an extended w/a on ivb+ if signalling from other rings */
-   i915.semaphores ?
+   (i915.semaphores && INTEL_GEN(dev_priv) == 7) ?
INTEL_INFO(dev_priv)->num_rings - 1 :
0;
int len;
-- 
2.11.0

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: limit forcewake to blitter domain in guc_send

[Patchwork]

== Series Details ==

Series: drm/i915/guc: limit forcewake to blitter domain in guc_send
URL   : https://patchwork.freedesktop.org/series/21834/
State : success

== Summary ==

Series 21834v1 drm/i915/guc: limit forcewake to blitter domain in guc_send
https://patchwork.freedesktop.org/api/1.0/series/21834/revisions/1/mbox/

fi-bdw-5557u total:278  pass:267  dwarn:0   dfail:0   fail:0   skip:11  
time: 455s
fi-bdw-gvtdvmtotal:278  pass:256  dwarn:8   dfail:0   fail:0   skip:14  
time: 453s
fi-bsw-n3050 total:278  pass:239  dwarn:0   dfail:0   fail:0   skip:39  
time: 541s
fi-bxt-j4205 total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19  
time: 544s
fi-bxt-t5700 total:278  pass:258  dwarn:0   dfail:0   fail:0   skip:20  
time: 565s
fi-byt-j1900 total:278  pass:251  dwarn:0   dfail:0   fail:0   skip:27  
time: 507s
fi-byt-n2820 total:278  pass:247  dwarn:0   dfail:0   fail:0   skip:31  
time: 500s
fi-hsw-4770  total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time: 434s
fi-hsw-4770r total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time: 431s
fi-ilk-650   total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50  
time: 448s
fi-ivb-3520m total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time: 519s
fi-ivb-3770  total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time: 500s
fi-kbl-7500u total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time: 484s
fi-skl-6260u total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time: 489s
fi-skl-6700hqtotal:278  pass:261  dwarn:0   dfail:0   fail:0   skip:17  
time: 613s
fi-skl-6700k total:278  pass:256  dwarn:4   dfail:0   fail:0   skip:18  
time: 486s
fi-skl-6770hqtotal:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time: 512s
fi-skl-gvtdvmtotal:278  pass:265  dwarn:0   dfail:0   fail:0   skip:13  
time: 462s
fi-snb-2520m total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  
time: 551s
fi-snb-2600  total:278  pass:249  dwarn:0   dfail:0   fail:0   skip:29  
time: 414s

fd27e1e4c9b5dc11966b4953432bd6e0510da308 drm-tip: 2017y-03m-24d-08h-39m-20s UTC 
integration manifest
429dcea drm/i915/guc: limit forcewake to blitter domain in guc_send

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4294/
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[Intel-gfx] [PATCH] drm/i915/guc: limit forcewake to blitter domain in guc_send

[Daniele Ceraolo Spurio]

The forcewake_get call in the guc_send_mmio function was added to
avoid getting and releasing forcewake on each register access.
While this makes sense, all GuC registers are in the blitter range
so no need to wake all the wells.

Signed-off-by: Daniele Ceraolo Spurio 
---
 drivers/gpu/drm/i915/intel_uc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 4a872cd..e016227 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -245,7 +245,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 
*action, u32 len)
return -EINVAL;
 
mutex_lock(>send_mutex);
-   intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+   intel_uncore_forcewake_get(dev_priv, FORCEWAKE_BLITTER);
 
dev_priv->guc.action_count += 1;
dev_priv->guc.action_cmd = action[0];
@@ -283,7 +283,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 
*action, u32 len)
}
dev_priv->guc.action_status = status;
 
-   intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+   intel_uncore_forcewake_put(dev_priv, FORCEWAKE_BLITTER);
mutex_unlock(>send_mutex);
 
return ret;
-- 
1.9.1

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Re: [Intel-gfx] [PATCH dim 2/2] dim: Curate and insert tags into patch(es)

[Sean Paul]

On Fri, Mar 24, 2017 at 11:07:17AM +0200, Ville Syrjälä wrote:
> On Thu, Mar 23, 2017 at 05:07:28PM -0400, Sean Paul wrote:
> > Launch $EDITOR when extracting tags to curate the tags immediately. Once the
> > tags are proper, automatically add them before the first Signed-off-by line
> > to all patches in the range.
> 
> Not sure adding them before the first sob is the right thing. If we want
> the tags to reflect the history somehow, then I suppose they should go
> just before *your* sob, which may or may not be the first sob in the
> commit message. Personally I've just started slapping them to the end
> which also maintains the history, but granted it doesn't really show who
> signed off on those tags. Or is there some "official" rule how tags
> should be sorted in commit messages?

Hi Ville,
Thanks for your review.

I usually sort them based on my perceived strength of the tag and put them
before the first SoB.

Cc:
Reviewed-by:
Tested-by:
Acked-by:
Signed-off-by:

I'm fine with putting them above the first SoB of the committer, that makes 
sense to
me. I'm not sure this is something we'll get consensus on, so that seems like a
sensible approach.

Sean

> 
> And I don't like the $EDITOR idea either, so at least make it
> optional.
> 
> > 
> > Signed-off-by: Sean Paul 
> > ---
> >  dim | 13 ++---
> >  1 file changed, 10 insertions(+), 3 deletions(-)
> > 
> > diff --git a/dim b/dim
> > index 43ea794..6a5580a 100755
> > --- a/dim
> > +++ b/dim
> > @@ -1145,6 +1145,12 @@ function rangeish()
> > fi
> >  }
> >  
> > +function insert_extracted_tags
> > +{
> > +   new_tabs=`cat $1 | awk '{ORS="n"} {print $0}' | head -c-3`
> > +   awk "/Signed-off-by/{p++} p==1{print \"$new_tabs\"; p++} p!=1{print}"
> > +}
> > +
> >  function dim_extract_tags
> >  {
> > local branch range file tags
> > @@ -1167,9 +1173,10 @@ function dim_extract_tags
> > return 0
> > fi
> >  
> > -   tags=$(printf -- "# *** extracted tags ***\n%s" "$tags")
> > -
> > -   git filter-branch -f --msg-filter "cat ; echo \"$tags\"" $range
> > +   echo "$tags" > $file
> > +   $EDITOR $file
> > +   export -f insert_extracted_tags
> > +   git filter-branch -f --msg-filter "insert_extracted_tags $file" $range
> >  }
> >  
> >  function dim_extract_queued
> > -- 
> > 2.12.1.500.gab5fba24ee-goog
> 
> -- 
> Ville Syrjälä
> Intel OTC

-- 
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Re: [Intel-gfx] [PATCH dim 2/2] dim: Curate and insert tags into patch(es)

[Sean Paul]

On Fri, Mar 24, 2017 at 09:54:15AM +0200, Jani Nikula wrote:
> On Thu, 23 Mar 2017, Sean Paul  wrote:
> > Launch $EDITOR when extracting tags to curate the tags immediately. Once the
> > tags are proper, automatically add them before the first Signed-off-by line
> > to all patches in the range.
> 
> Two problems I have with this. First, I like to edit the final commit
> message, not an intermediate file. 

Hi Jani,
Thanks for your review.

The intermediate file includes just the extracted tags, not the entire commit
message. This allows you to reorder them as appropriate, or remove any false
positives before it hits the log.


> Second, I pipe messages to dim
> extract-tags *from* my $EDITOR, so I'd rather not have it launch $EDITOR
> again.
> 

The idea is that you approve the tags as soon as you extract them and saves you
having to commit --amend later to remove the "*** extracted tags ***" lines.
This can be meaningful if you've extracted tags to a large set, since you'd need
to go through each commit to make any necessary changes.

As Ville suggested, I can make the editor step optional (and restore the
"*** extracted tags ***" for the disabled case).

Sean



> BR,
> Jani.
> 
> >
> > Signed-off-by: Sean Paul 
> > ---
> >  dim | 13 ++---
> >  1 file changed, 10 insertions(+), 3 deletions(-)
> >
> > diff --git a/dim b/dim
> > index 43ea794..6a5580a 100755
> > --- a/dim
> > +++ b/dim
> > @@ -1145,6 +1145,12 @@ function rangeish()
> > fi
> >  }
> >  
> > +function insert_extracted_tags
> > +{
> > +   new_tabs=`cat $1 | awk '{ORS="n"} {print $0}' | head -c-3`
> > +   awk "/Signed-off-by/{p++} p==1{print \"$new_tabs\"; p++} p!=1{print}"
> > +}
> > +
> >  function dim_extract_tags
> >  {
> > local branch range file tags
> > @@ -1167,9 +1173,10 @@ function dim_extract_tags
> > return 0
> > fi
> >  
> > -   tags=$(printf -- "# *** extracted tags ***\n%s" "$tags")
> > -
> > -   git filter-branch -f --msg-filter "cat ; echo \"$tags\"" $range
> > +   echo "$tags" > $file
> > +   $EDITOR $file
> > +   export -f insert_extracted_tags
> > +   git filter-branch -f --msg-filter "insert_extracted_tags $file" $range
> >  }
> >  
> >  function dim_extract_queued
> 
> -- 
> Jani Nikula, Intel Open Source Technology Center

-- 
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Re: [Intel-gfx] [PATCH 1/2] drm/i915: Sanitize display INIT power domain enabling

[Imre Deak]

On Fri, Mar 24, 2017 at 02:36:54PM +0200, Imre Deak wrote:
> For consistency move the INIT power domain enabling to happen at the
> same call-stack level everywhere. So far we didn't do this enabling
> during:
> - on GEN9 big-core when resuming from system freeze
> - on VLV on the i915_drm_suspend_late() error path
> 
> Fortunately neither of these depended on display power wells being
> enabled until proper references are taken by the modeset code. (This
> also means the we can probably remove the INIT power domain get/put
> from these places as a follow-up, after some more auditing.)
> 
> The current unpaired enable/disable was noticed by Ville during some
> earlier review.
> 
> Cc: Ville Syrjälä 
> Signed-off-by: Imre Deak 
> ---
>  drivers/gpu/drm/i915/i915_drv.c | 6 ++
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 2 --
>  2 files changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 6d9944a..6b10e37 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -592,6 +592,8 @@ static int i915_load_modeset_init(struct drm_device *dev)
>   intel_update_rawclk(dev_priv);
>  
>   intel_power_domains_init_hw(dev_priv, false);
> + /* Enable the INIT power domain wells for HW initialization. */
> + intel_display_set_init_power(dev_priv, true);

Arr, this will result in HPD IRQs inited too early on VLV. Need to
rethink this.

>  
>   intel_csr_ucode_init(dev_priv);
>  
> @@ -1559,6 +1561,8 @@ static int i915_drm_suspend_late(struct drm_device 
> *dev, bool hibernation)
>   if (!fw_csr)
>   intel_power_domains_init_hw(dev_priv, true);
>  
> + intel_display_set_init_power(dev_priv, true);
> +
>   goto out;
>   }
>  
> @@ -1768,6 +1772,8 @@ static int i915_drm_resume_early(struct drm_device *dev)
>   if (IS_GEN9_LP(dev_priv) ||
>   !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
>   intel_power_domains_init_hw(dev_priv, true);
> + /* Enable the INIT power domain wells for HW initialization. */
> + intel_display_set_init_power(dev_priv, true);
>  
>   i915_gem_sanitize(dev_priv);
>  
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 012bc35..ecc43c6 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -2715,8 +2715,6 @@ void intel_power_domains_init_hw(struct 
> drm_i915_private *dev_priv, bool resume)
>   mutex_unlock(_domains->lock);
>   }
>  
> - /* For now, we need the power well to be always enabled. */
> - intel_display_set_init_power(dev_priv, true);
>   /* Disable power support if the user asked so. */
>   if (!i915.disable_power_well)
>   intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
> -- 
> 2.5.0
> 
> ___
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: Sanitize display INIT power domain enabling

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915: Sanitize display INIT power domain 
enabling
URL   : https://patchwork.freedesktop.org/series/21827/
State : failure

== Summary ==

Series 21827v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/21827/revisions/1/mbox/

Test core_auth:
Subgroup basic-auth:
pass   -> SKIP   (fi-byt-j1900)
pass   -> SKIP   (fi-byt-n2820)
Test core_prop_blob:
Subgroup basic:
pass   -> SKIP   (fi-byt-j1900)
pass   -> SKIP   (fi-byt-n2820)
Test drv_getparams_basic:
Subgroup basic-eu-total:
pass   -> SKIP   (fi-byt-j1900)
pass   -> SKIP   (fi-byt-n2820)
Subgroup basic-subslice-total:
pass   -> SKIP   (fi-byt-j1900)
pass   -> SKIP   (fi-byt-n2820)
Test drv_hangman:
Subgroup error-state-basic:
pass   -> SKIP   (fi-byt-j1900)
pass   -> SKIP   (fi-byt-n2820)
Test drv_module_reload:
Subgroup basic-reload:
pass   -> INCOMPLETE (fi-byt-j1900)
pass   -> INCOMPLETE (fi-byt-n2820)
Test gem_basic:
Subgroup bad-close:
pass   -> SKIP   (fi-byt-j1900)
pass   -> SKIP   (fi-byt-n2820)
Subgroup create-close:
pass   -> SKIP   (fi-byt-j1900)
pass   -> SKIP   (fi-byt-n2820)
Subgroup create-fd-close:
pass   -> SKIP   (fi-byt-j1900)
pass   -> SKIP   (fi-byt-n2820)
Test gem_busy:
Subgroup basic-busy-default:
pass   -> SKIP   (fi-byt-j1900)
pass   -> SKIP   (fi-byt-n2820)
Subgroup basic-hang-default:
pass   -> SKIP   (fi-byt-j1900)
pass   -> SKIP   (fi-byt-n2820)
Test gem_close_race:
Subgroup basic-process:
pass   -> SKIP   (fi-byt-j1900)
pass   -> SKIP   (fi-byt-n2820)
Subgroup basic-threads:
pass   -> SKIP   (fi-byt-j1900)
pass   -> SKIP   (fi-byt-n2820)
Test gem_cpu_reloc:
Subgroup basic:
pass   -> SKIP   (fi-byt-j1900)
pass   -> SKIP   (fi-byt-n2820)
Test gem_cs_tlb:
Subgroup basic-default:
pass   -> SKIP   (fi-byt-j1900)
pass   -> SKIP   (fi-byt-n2820)
Test gem_ctx_basic:
pass   -> SKIP   (fi-byt-j1900)
pass   -> SKIP   (fi-byt-n2820)
Test gem_ctx_create:
Subgroup basic:
pass   -> SKIP   (fi-byt-j1900)
pass   -> SKIP   (fi-byt-n2820)
Subgroup basic-files:
pass   -> SKIP   (fi-byt-j1900)
pass   -> SKIP   (fi-byt-n2820)
Test gem_ctx_exec:
Subgroup basic:
pass   -> SKIP   (fi-byt-j1900)
pass   -> SKIP   (fi-byt-n2820)
Test gem_ctx_param:
Subgroup basic:
pass   -> SKIP   (fi-byt-j1900)
pass   -> SKIP   (fi-byt-n2820)
Subgroup basic-default:
pass   -> SKIP   (fi-byt-j1900)
pass   -> SKIP   (fi-byt-n2820)
Test gem_ctx_switch:
Subgroup basic-default:
pass   -> SKIP   (fi-byt-j1900)
pass   -> SKIP   (fi-byt-n2820)
Subgroup basic-default-heavy:
pass   -> SKIP   (fi-byt-j1900)
pass   -> SKIP   (fi-byt-n2820)
Test gem_exec_basic:
Subgroup basic-blt:
pass   -> SKIP   (fi-byt-j1900)
pass   -> SKIP   (fi-byt-n2820)
Subgroup basic-bsd:
pass   -> SKIP   (fi-byt-j1900)
pass   -> SKIP   (fi-byt-n2820)
Subgroup basic-default:
pass   -> SKIP   (fi-byt-j1900)
pass   -> SKIP   (fi-byt-n2820)
Subgroup basic-render:
pass   -> SKIP   (fi-byt-j1900)
pass   -> SKIP   (fi-byt-n2820)
Subgroup gtt-blt:
WARNING: Long output truncated
fi-bdw-gvtdvm failed to collect. IGT log at Patchwork_4293/fi-bdw-gvtdvm/igt.log

fd27e1e4c9b5dc11966b4953432bd6e0510da308 drm-tip: 2017y-03m-24d-08h-39m-20s UTC 
integration manifest
eff2a71 drm/i915: Sanitize display INIT power domain disabling
f6f4eaa drm/i915: Sanitize display INIT power domain enabling

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4293/
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[Intel-gfx] [PATCH 2/2] drm/i915: Sanitize display INIT power domain disabling

[Imre Deak]

For consistency move the INIT power domain disabling to the same
call-stack level with the corresponding enabling.

This change will remove the disable call via intel_finish_reset() and
intel_lid_notify(), but this is fine: we didn't enable the INIT power
domain on these paths to begin with, so the disable call was just a NOP.
(Enabling the INIT power domain on these paths is not needed either
 since we access the HW directly only for old HW without RPM support, or
 do a full modeset restore, which knows how to enable any required power
 domain.)

Signed-off-by: Imre Deak 
---
 drivers/gpu/drm/i915/i915_drv.c | 4 
 drivers/gpu/drm/i915/intel_display.c| 3 ---
 drivers/gpu/drm/i915/intel_runtime_pm.c | 7 +++
 3 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 6b10e37..13fa585 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -609,6 +609,8 @@ static int i915_load_modeset_init(struct drm_device *dev)
if (ret)
goto cleanup_irq;
 
+   intel_display_set_init_power(dev_priv, false);
+
intel_uc_init_fw(dev_priv);
 
ret = i915_gem_init(dev_priv);
@@ -1670,6 +1672,8 @@ static int i915_drm_resume(struct drm_device *dev)
 
intel_display_resume(dev);
 
+   intel_display_set_init_power(dev_priv, false);
+
drm_kms_helper_poll_enable(dev);
 
/*
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 9a28a89..0920291 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15610,9 +15610,6 @@ intel_modeset_setup_hw_state(struct drm_device *dev)
if (WARN_ON(put_domains))
modeset_put_power_domains(dev_priv, put_domains);
}
-   intel_display_set_init_power(dev_priv, false);
-
-   intel_power_domains_verify_state(dev_priv);
 
intel_fbc_init_pipe_state(dev_priv);
 }
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index ecc43c6..0fb5bfb 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -270,6 +270,13 @@ void intel_display_set_init_power(struct drm_i915_private 
*dev_priv,
intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 
dev_priv->power_domains.init_power_on = enable;
+
+   if (!enable)
+   /*
+* By this point all enabled power wells must have a reference
+* and all unneeded power wells must be disabled; verify this.
+*/
+   intel_power_domains_verify_state(dev_priv);
 }
 
 /*
-- 
2.5.0

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[Intel-gfx] [PATCH 1/2] drm/i915: Sanitize display INIT power domain enabling

[Imre Deak]

For consistency move the INIT power domain enabling to happen at the
same call-stack level everywhere. So far we didn't do this enabling
during:
- on GEN9 big-core when resuming from system freeze
- on VLV on the i915_drm_suspend_late() error path

Fortunately neither of these depended on display power wells being
enabled until proper references are taken by the modeset code. (This
also means the we can probably remove the INIT power domain get/put
from these places as a follow-up, after some more auditing.)

The current unpaired enable/disable was noticed by Ville during some
earlier review.

Cc: Ville Syrjälä 
Signed-off-by: Imre Deak 
---
 drivers/gpu/drm/i915/i915_drv.c | 6 ++
 drivers/gpu/drm/i915/intel_runtime_pm.c | 2 --
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 6d9944a..6b10e37 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -592,6 +592,8 @@ static int i915_load_modeset_init(struct drm_device *dev)
intel_update_rawclk(dev_priv);
 
intel_power_domains_init_hw(dev_priv, false);
+   /* Enable the INIT power domain wells for HW initialization. */
+   intel_display_set_init_power(dev_priv, true);
 
intel_csr_ucode_init(dev_priv);
 
@@ -1559,6 +1561,8 @@ static int i915_drm_suspend_late(struct drm_device *dev, 
bool hibernation)
if (!fw_csr)
intel_power_domains_init_hw(dev_priv, true);
 
+   intel_display_set_init_power(dev_priv, true);
+
goto out;
}
 
@@ -1768,6 +1772,8 @@ static int i915_drm_resume_early(struct drm_device *dev)
if (IS_GEN9_LP(dev_priv) ||
!(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
intel_power_domains_init_hw(dev_priv, true);
+   /* Enable the INIT power domain wells for HW initialization. */
+   intel_display_set_init_power(dev_priv, true);
 
i915_gem_sanitize(dev_priv);
 
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 012bc35..ecc43c6 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -2715,8 +2715,6 @@ void intel_power_domains_init_hw(struct drm_i915_private 
*dev_priv, bool resume)
mutex_unlock(_domains->lock);
}
 
-   /* For now, we need the power well to be always enabled. */
-   intel_display_set_init_power(dev_priv, true);
/* Disable power support if the user asked so. */
if (!i915.disable_power_well)
intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
-- 
2.5.0

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Re: [Intel-gfx] [i-g-t PATCH 2/2] igt/kms_flip: Fix set_dpms called with an idle bo

[Chris Wilson]

On Fri, Mar 24, 2017 at 01:55:00PM +0200, Ander Conselvan De Oliveira wrote:
> On Thu, 2016-12-01 at 11:23 +, Chris Wilson wrote:
> > On Thu, Dec 01, 2016 at 12:58:46PM +0200, Abdiel Janulgue wrote:
> > > Signed-off-by: Abdiel Janulgue 
> 
> How is the bug that this commit fixes triggered? Reverting this change seems 
> to
> fix [1] which, if I understand correctly, is caused by the atomic commit of
> set_dpms() to be waiting for the dummy write to the frontbuffer complete, 
> while 
> the spin batch never ends since the test is blocked and so doesn't handle the
> timer signal. 

That is actually a kernel regression (that I'm responsible for). However
it raises a good point that we don't actually want to interrupt the
modeset to handle the signal in this case, otherwise the interrupt
modeset and when it restarts, it will find it doesn't have to wait -
invalidating our test that it can wait for completion. Hmm, that affects
all users.  We want to delegate that task to a thread/child to avoid
interrupting the syscall and perturbing the actual code under test.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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Re: [Intel-gfx] [PATCH] drm/i915/guc: Refactor the retrieval of guc_process_desc

[Michał Winiarski]

On Thu, Mar 23, 2017 at 11:00:00PM +, Chris Wilson wrote:
> Move the common "client->vaddr + client->proc_desc_offset" to its own
> function, __get_process_desc() to match the newly established pattern.
> 
> Signed-off-by: Chris Wilson 

Reviewed-by: Michał Winiarski 

-Michał

> ---
>  drivers/gpu/drm/i915/i915_guc_submission.c | 24 +++-
>  1 file changed, 11 insertions(+), 13 deletions(-)
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Enable FBC for non X-tiled FBs (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915: Enable FBC for non X-tiled FBs (rev4)
URL   : https://patchwork.freedesktop.org/series/21264/
State : success

== Summary ==

Series 21264v4 drm/i915: Enable FBC for non X-tiled FBs
https://patchwork.freedesktop.org/api/1.0/series/21264/revisions/4/mbox/

fi-bdw-5557u total:278  pass:267  dwarn:0   dfail:0   fail:0   skip:11  
time: 460s
fi-bdw-gvtdvmtotal:278  pass:256  dwarn:8   dfail:0   fail:0   skip:14  
time: 466s
fi-bsw-n3050 total:278  pass:239  dwarn:0   dfail:0   fail:0   skip:39  
time: 590s
fi-bxt-j4205 total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19  
time: 540s
fi-bxt-t5700 total:278  pass:258  dwarn:0   dfail:0   fail:0   skip:20  
time: 559s
fi-byt-j1900 total:278  pass:251  dwarn:0   dfail:0   fail:0   skip:27  
time: 506s
fi-byt-n2820 total:278  pass:247  dwarn:0   dfail:0   fail:0   skip:31  
time: 509s
fi-hsw-4770  total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time: 437s
fi-hsw-4770r total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time: 431s
fi-ilk-650   total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50  
time: 438s
fi-ivb-3520m total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time: 516s
fi-ivb-3770  total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time: 491s
fi-kbl-7500u total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time: 485s
fi-skl-6260u total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time: 476s
fi-skl-6700hqtotal:278  pass:261  dwarn:0   dfail:0   fail:0   skip:17  
time: 600s
fi-skl-6700k total:278  pass:256  dwarn:4   dfail:0   fail:0   skip:18  
time: 493s
fi-skl-6770hqtotal:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time: 520s
fi-skl-gvtdvmtotal:278  pass:265  dwarn:0   dfail:0   fail:0   skip:13  
time: 456s
fi-snb-2520m total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  
time: 550s
fi-snb-2600  total:278  pass:249  dwarn:0   dfail:0   fail:0   skip:29  
time: 414s

fd27e1e4c9b5dc11966b4953432bd6e0510da308 drm-tip: 2017y-03m-24d-08h-39m-20s UTC 
integration manifest
e61d48d drm/i915: Fix FBC cfb stride programming for non X-tiled FB

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4292/
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Re: [Intel-gfx] [i-g-t PATCH 2/2] igt/kms_flip: Fix set_dpms called with an idle bo

[Ander Conselvan De Oliveira]

On Thu, 2016-12-01 at 11:23 +, Chris Wilson wrote:
> On Thu, Dec 01, 2016 at 12:58:46PM +0200, Abdiel Janulgue wrote:
> > Signed-off-by: Abdiel Janulgue 

How is the bug that this commit fixes triggered? Reverting this change seems to
fix [1] which, if I understand correctly, is caused by the atomic commit of
set_dpms() to be waiting for the dummy write to the frontbuffer complete, while 
the spin batch never ends since the test is blocked and so doesn't handle the
timer signal. 


[1] https://bugs.freedesktop.org/show_bug.cgi?id=100261

Thanks,
Ander

> > ---
> >  tests/kms_flip.c | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> > 
> > diff --git a/tests/kms_flip.c b/tests/kms_flip.c
> > index 289335a..f744b3d 100644
> > --- a/tests/kms_flip.c
> > +++ b/tests/kms_flip.c
> > @@ -757,9 +757,9 @@ static unsigned int run_test_step(struct test_output *o)
> >  
> > if (o->flags & TEST_DPMS) {
> > if (spin_rcs)
> > -   igt_spin_batch_end(spin_rcs);
> > +   igt_spin_batch_set_timeout(spin_rcs, NSEC_PER_SEC);
> > if (spin_bcs)
> > -   igt_spin_batch_end(spin_bcs);
> > +   igt_spin_batch_set_timeout(spin_bcs, NSEC_PER_SEC);
> > set_dpms(o, DRM_MODE_DPMS_ON);
> > }
> 
> Reviewed-by: Chris Wilson 
> -Chris
> 
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Enhanced disable access to stolen memory as a guest (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Enhanced disable access to stolen memory as a guest (rev2)
URL   : https://patchwork.freedesktop.org/series/21818/
State : success

== Summary ==

Series 21818v2 drm/i915: Enhanced disable access to stolen memory as a guest
https://patchwork.freedesktop.org/api/1.0/series/21818/revisions/2/mbox/

fi-bdw-5557u total:278  pass:267  dwarn:0   dfail:0   fail:0   skip:11  
time: 458s
fi-bdw-gvtdvmtotal:278  pass:256  dwarn:8   dfail:0   fail:0   skip:14  
time: 454s
fi-bsw-n3050 total:278  pass:239  dwarn:0   dfail:0   fail:0   skip:39  
time: 578s
fi-bxt-j4205 total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19  
time: 542s
fi-bxt-t5700 total:278  pass:258  dwarn:0   dfail:0   fail:0   skip:20  
time: 583s
fi-byt-j1900 total:278  pass:251  dwarn:0   dfail:0   fail:0   skip:27  
time: 506s
fi-byt-n2820 total:278  pass:247  dwarn:0   dfail:0   fail:0   skip:31  
time: 507s
fi-hsw-4770  total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time: 438s
fi-hsw-4770r total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time: 431s
fi-ilk-650   total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50  
time: 433s
fi-ivb-3520m total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time: 522s
fi-ivb-3770  total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time: 497s
fi-kbl-7500u total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time: 485s
fi-skl-6260u total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time: 488s
fi-skl-6700hqtotal:278  pass:261  dwarn:0   dfail:0   fail:0   skip:17  
time: 601s
fi-skl-6700k total:278  pass:256  dwarn:4   dfail:0   fail:0   skip:18  
time: 490s
fi-skl-6770hqtotal:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time: 525s
fi-skl-gvtdvmtotal:278  pass:265  dwarn:0   dfail:0   fail:0   skip:13  
time: 464s
fi-snb-2520m total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  
time: 547s
fi-snb-2600  total:278  pass:249  dwarn:0   dfail:0   fail:0   skip:29  
time: 429s

fd27e1e4c9b5dc11966b4953432bd6e0510da308 drm-tip: 2017y-03m-24d-08h-39m-20s UTC 
integration manifest
f072895 drm/i915: Enhanced disable access to stolen memory as a guest

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4290/
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[Intel-gfx] [PATCH v4] drm/i915: Fix FBC cfb stride programming for non X-tiled FB

[Praveen Paneri]

When FBC is enabled for linear, legacy Y-tiled and Yf-tiled
surfaces on gen9, the cfb stride must be programmed by SW as

cfb_stride = ceiling[(at least plane width in pixels)/
 (32 * compression limit factor)] * 8

v2: Minor fix for a build error

v3: Fixed subject, register name and platform check (Ville)

v4: Added WA details in comment (Paulo)

Cc: Paulo Zanoni 
Cc: Ville Syrj??l?? 
Signed-off-by: Praveen Paneri 
---
 drivers/gpu/drm/i915/i915_reg.h  | 3 +++
 drivers/gpu/drm/i915/intel_fbc.c | 9 +
 2 files changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 04c8f69..4adf2e6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6504,6 +6504,9 @@ enum {
 #define  GLK_CL1_PWR_DOWN  (1 << 11)
 #define  GLK_CL2_PWR_DOWN  (1 << 12)
 
+#define CHICKEN_MISC_4 _MMIO(0x4208c)
+#define   FBC_STRIDE_OVERRIDE  (1<<13)
+
 #define _CHICKEN_PIPESL_1_A0x420b0
 #define _CHICKEN_PIPESL_1_B0x420b4
 #define  HSW_FBCQ_DIS  (1 << 22)
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index ded2add..1183633 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -298,9 +298,18 @@ static bool ilk_fbc_is_active(struct drm_i915_private 
*dev_priv)
 static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
 {
struct intel_fbc_reg_params *params = _priv->fbc.params;
+   struct intel_fbc_state_cache *cache = _priv->fbc.state_cache;
u32 dpfc_ctl;
int threshold = dev_priv->fbc.threshold;
 
+   /* Display WA #0529: skl, kbl, bxt, glk */
+   if (IS_GEN9(dev_priv) &&
+   i915_gem_object_get_tiling(cache->vma->obj) != I915_TILING_X) {
+   int cfb_stride = DIV_ROUND_UP(cache->plane.src_w,
+ (32 * threshold)) * 8;
+   I915_WRITE(CHICKEN_MISC_4, FBC_STRIDE_OVERRIDE | cfb_stride);
+   }
+
dpfc_ctl = 0;
if (IS_IVYBRIDGE(dev_priv))
dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.plane);
-- 
1.9.1

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[Intel-gfx] ✗ Fi.CI.BAT: failure for Enable OA unit for Gen 8 and 9 in i915 perf (rev3)

[Patchwork]

== Series Details ==

Series: Enable OA unit for Gen 8 and 9 in i915 perf (rev3)
URL   : https://patchwork.freedesktop.org/series/20084/
State : failure

== Summary ==

Series 20084v3 Enable OA unit for Gen 8 and 9 in i915 perf
https://patchwork.freedesktop.org/api/1.0/series/20084/revisions/3/mbox/

Test gem_exec_fence:
Subgroup await-hang-default:
pass   -> INCOMPLETE (fi-hsw-4770)

fi-bdw-5557u total:278  pass:267  dwarn:0   dfail:0   fail:0   skip:11  
time: 470s
fi-bdw-gvtdvmtotal:278  pass:256  dwarn:8   dfail:0   fail:0   skip:14  
time: 467s
fi-bsw-n3050 total:278  pass:239  dwarn:0   dfail:0   fail:0   skip:39  
time: 584s
fi-bxt-j4205 total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19  
time: 534s
fi-bxt-t5700 total:278  pass:258  dwarn:0   dfail:0   fail:0   skip:20  
time: 568s
fi-byt-j1900 total:278  pass:251  dwarn:0   dfail:0   fail:0   skip:27  
time: 509s
fi-hsw-4770  total:48   pass:41   dwarn:0   dfail:0   fail:0   skip:6   
time: 0s
fi-hsw-4770r total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time: 432s
fi-ilk-650   total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50  
time: 442s
fi-ivb-3520m total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time: 510s
fi-ivb-3770  total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time: 495s
fi-kbl-7500u total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time: 488s
fi-skl-6260u total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time: 481s
fi-skl-6700hqtotal:278  pass:261  dwarn:0   dfail:0   fail:0   skip:17  
time: 606s
fi-skl-6700k total:278  pass:256  dwarn:4   dfail:0   fail:0   skip:18  
time: 492s
fi-skl-6770hqtotal:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time: 516s
fi-skl-gvtdvmtotal:278  pass:265  dwarn:0   dfail:0   fail:0   skip:13  
time: 461s
fi-snb-2520m total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  
time: 546s
fi-snb-2600  total:278  pass:249  dwarn:0   dfail:0   fail:0   skip:29  
time: 426s
fi-byt-n2820 failed to collect. IGT log at Patchwork_4288/fi-byt-n2820/igt.log

fd27e1e4c9b5dc11966b4953432bd6e0510da308 drm-tip: 2017y-03m-24d-08h-39m-20s UTC 
integration manifest
913d37d drm/i915: Add 'render basic' Gen8+ OA unit configs
9500fa8 drm/i915: expose _SUBSLICE_MASK GETPARM
fd8966b drm/i915: expose _SLICE_MASK GETPARM

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4288/
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Re: [Intel-gfx] [PATCH] drm/i915: Reduce Data Link N value for 1 lane DP->hdmi converters

[Jani Nikula]

On Thu, 23 Mar 2017, Clint Taylor  wrote:
> I would prefer a solution for B (rules for M/N), but the code doesn't 
> appear to be broken and I don't believe we should "Fix" something that 
> is working. The device also works by changing the roundup_pow_of_two() 
> to rounddown_pow_of_two() however that would apply the change to every 
> device connected.

Looking at this again, the problem must be in the (external) link M/N,
not (internal) data M/N. Thus it's only about the pixel clock / link
clock ratio. Right?

With current code link N exceeds 0x8 only when link clock >= 54
kHz. Except for the eDP intermediate link clocks, at least the four
least significant bits are always zero. But just one bit shift right
would be enough to bring even the DP 1.4 81 kHz link clock under
0x8 link N. The pixel clock for modes that require a link clock >=
54 kHz would also have several least significant bits zero.

Unless the user provides a mode with an odd pixel clock value, we can
reduce the numbers to reach the goal, with no loss in precision, and it
doesn't even feel like a hack. The DP spec even mentions sources making
choices that "allow for static and relatively small Mvid and Nvid
values".

Of course, all of this hinges on the problem being specific to the link
M/N, and independent of data M/N.

BR,
Jani.


diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 9a28a8917dc1..55bb6cf2a2d3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6337,6 +6337,15 @@ intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
 static void compute_m_n(unsigned int m, unsigned int n,
uint32_t *ret_m, uint32_t *ret_n)
 {
+   /*
+* Reduce M/N as much as possible without loss in precision. Several DP
+* dongles in particular seem to be fussy about too large M/N values.
+*/
+   while ((m & 1) == 0 && (n & 1) == 0) {
+   m >>= 1;
+   n >>= 1;
+   }
+
*ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
*ret_m = div_u64((uint64_t) m * *ret_n, n);
intel_reduce_m_n_ratio(ret_m, ret_n);
---

And the hack on top that ensures we're below 0x8 link N independent
of the pixel clock. Note that the only loss in precision here is the one
bit in pixel clock; the other values passed in will always be even.

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 55bb6cf2a2d3..b51b836b9538 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6341,6 +6341,8 @@ static void compute_m_n(unsigned int m, unsigned int n,
 * Reduce M/N as much as possible without loss in precision. Several DP
 * dongles in particular seem to be fussy about too large M/N values.
 */
+   m >>= 1;
+   n >>= 1;
while ((m & 1) == 0 && (n & 1) == 0) {
m >>= 1;
n >>= 1;



-- 
Jani Nikula, Intel Open Source Technology Center
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Reduce Data Link N value for 1 lane DP->hdmi converters (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Reduce Data Link N value for 1 lane DP->hdmi converters (rev2)
URL   : https://patchwork.freedesktop.org/series/21724/
State : success

== Summary ==

Series 21724v2 drm/i915: Reduce Data Link N value for 1 lane DP->hdmi converters
https://patchwork.freedesktop.org/api/1.0/series/21724/revisions/2/mbox/

Test gem_exec_flush:
Subgroup basic-batch-kernel-default-uc:
pass   -> FAIL   (fi-snb-2600) fdo#17

fdo#17 https://bugs.freedesktop.org/show_bug.cgi?id=17

fi-bdw-5557u total:278  pass:267  dwarn:0   dfail:0   fail:0   skip:11  
time: 471s
fi-bdw-gvtdvmtotal:278  pass:256  dwarn:8   dfail:0   fail:0   skip:14  
time: 456s
fi-bxt-j4205 total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19  
time: 536s
fi-bxt-t5700 total:278  pass:258  dwarn:0   dfail:0   fail:0   skip:20  
time: 583s
fi-byt-j1900 total:278  pass:251  dwarn:0   dfail:0   fail:0   skip:27  
time: 506s
fi-byt-n2820 total:278  pass:247  dwarn:0   dfail:0   fail:0   skip:31  
time: 506s
fi-hsw-4770  total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time: 439s
fi-hsw-4770r total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time: 437s
fi-ilk-650   total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50  
time: 433s
fi-ivb-3520m total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time: 518s
fi-ivb-3770  total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time: 493s
fi-kbl-7500u total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time: 483s
fi-skl-6260u total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time: 488s
fi-skl-6700hqtotal:278  pass:261  dwarn:0   dfail:0   fail:0   skip:17  
time: 633s
fi-skl-6700k total:278  pass:256  dwarn:4   dfail:0   fail:0   skip:18  
time: 492s
fi-skl-6770hqtotal:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time: 530s
fi-skl-gvtdvmtotal:278  pass:265  dwarn:0   dfail:0   fail:0   skip:13  
time: 467s
fi-snb-2520m total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  
time: 547s
fi-snb-2600  total:278  pass:248  dwarn:0   dfail:0   fail:1   skip:29  
time: 419s
fi-bsw-n3050 failed to collect. IGT log at Patchwork_4287/fi-bsw-n3050/igt.log

fd27e1e4c9b5dc11966b4953432bd6e0510da308 drm-tip: 2017y-03m-24d-08h-39m-20s UTC 
integration manifest
fd3c6c1 drm/i915: Reduce Data Link N value for 1 lane DP->hdmi converters

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4287/
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dp: Validate cached link rate and lane count before retraining

[Patchwork]

== Series Details ==

Series: drm/i915/dp: Validate cached link rate and lane count before retraining
URL   : https://patchwork.freedesktop.org/series/21797/
State : success

== Summary ==

Series 21797v1 drm/i915/dp: Validate cached link rate and lane count before 
retraining
https://patchwork.freedesktop.org/api/1.0/series/21797/revisions/1/mbox/

Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-c:
pass   -> INCOMPLETE (fi-bsw-n3050) fdo#100113

fdo#100113 https://bugs.freedesktop.org/show_bug.cgi?id=100113

fi-bdw-5557u total:278  pass:267  dwarn:0   dfail:0   fail:0   skip:11  
time: 467s
fi-bdw-gvtdvmtotal:278  pass:256  dwarn:8   dfail:0   fail:0   skip:14  
time: 454s
fi-bsw-n3050 total:237  pass:201  dwarn:0   dfail:0   fail:0   skip:35  
time: 0s
fi-bxt-j4205 total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19  
time: 545s
fi-bxt-t5700 total:278  pass:258  dwarn:0   dfail:0   fail:0   skip:20  
time: 562s
fi-byt-j1900 total:278  pass:251  dwarn:0   dfail:0   fail:0   skip:27  
time: 508s
fi-byt-n2820 total:278  pass:247  dwarn:0   dfail:0   fail:0   skip:31  
time: 503s
fi-hsw-4770  total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time: 433s
fi-hsw-4770r total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time: 437s
fi-ilk-650   total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50  
time: 440s
fi-ivb-3520m total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time: 511s
fi-ivb-3770  total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time: 496s
fi-kbl-7500u total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time: 476s
fi-skl-6260u total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time: 486s
fi-skl-6700hqtotal:278  pass:261  dwarn:0   dfail:0   fail:0   skip:17  
time: 601s
fi-skl-6700k total:278  pass:256  dwarn:4   dfail:0   fail:0   skip:18  
time: 490s
fi-skl-6770hqtotal:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time: 526s
fi-skl-gvtdvmtotal:278  pass:265  dwarn:0   dfail:0   fail:0   skip:13  
time: 464s
fi-snb-2520m total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  
time: 549s
fi-snb-2600  total:278  pass:249  dwarn:0   dfail:0   fail:0   skip:29  
time: 416s

fd27e1e4c9b5dc11966b4953432bd6e0510da308 drm-tip: 2017y-03m-24d-08h-39m-20s UTC 
integration manifest
44ec18c drm/i915/dp: Validate cached link rate and lane count before retraining

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4286/
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Re: [Intel-gfx] [PATCH 6/6] drm/i915: Use i9xx_check_plane_surface() for sprite planes as well

[Chris Wilson]

On Thu, Mar 23, 2017 at 09:27:12PM +0200, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä 
> 
> All the pre-SKL sprite planes compute the x/y/tile offsets in a
> similar way. There are a couple of minor differences but the primary
> planes have those as well. Thus i9xx_check_plane_surface()
> already does what we need, so let's use it.
> 
> Signed-off-by: Ville Syrjälä 

Looks right to me, but I'd recommend a second opinion here.
Reviewed-by: Chris Wilson 
-Chris

-- 
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[Intel-gfx] [PATCH] drm/i915: Reorganise intel_engine_cleanup

[Chris Wilson]

Merge the two vfuncs into one and so eliminate one more case of
execlists/ringbuffer specialisation outside of the intel_engine_cs.c

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_drv.c |  2 +-
 drivers/gpu/drm/i915/i915_drv.h |  2 --
 drivers/gpu/drm/i915/i915_gem.c | 17 ++---
 drivers/gpu/drm/i915/intel_engine_cs.c  | 11 +-
 drivers/gpu/drm/i915/intel_lrc.c| 21 ---
 drivers/gpu/drm/i915/intel_lrc.h|  1 -
 drivers/gpu/drm/i915/intel_ringbuffer.c | 63 -
 drivers/gpu/drm/i915/intel_ringbuffer.h |  1 +
 8 files changed, 50 insertions(+), 68 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 547d7d198271..6020ef8bd3b2 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -554,7 +554,7 @@ static void i915_gem_fini(struct drm_i915_private *dev_priv)
mutex_lock(_priv->drm.struct_mutex);
if (i915.enable_guc_loading)
intel_uc_fini_hw(dev_priv);
-   i915_gem_cleanup_engines(dev_priv);
+   intel_engines_cleanup(dev_priv);
i915_gem_context_fini(dev_priv);
i915_gem_cleanup_userptr(dev_priv);
mutex_unlock(_priv->drm.struct_mutex);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e20a21c7ecdf..5274acfe5df9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2519,7 +2519,6 @@ struct drm_i915_private {
/* Abstract the submission mechanism (legacy ringbuffer or execlists) 
away */
struct {
void (*resume)(struct drm_i915_private *);
-   void (*cleanup_engine)(struct intel_engine_cs *engine);
 
struct list_head timelines;
struct i915_gem_timeline global_timeline;
@@ -3369,7 +3368,6 @@ void i915_gem_init_mmio(struct drm_i915_private *i915);
 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
 int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
 void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
-void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
 int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
   unsigned int flags);
 int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 5704dbfe5653..ab77e38ec264 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4602,13 +4602,10 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
i915_vma_init(dev_priv);
i915_gem_clflush_init(dev_priv);
 
-   if (USE_EXECLISTS(dev_priv)) {
+   if (USE_EXECLISTS(dev_priv))
dev_priv->gt.resume = intel_lr_context_resume;
-   dev_priv->gt.cleanup_engine = intel_logical_ring_cleanup;
-   } else {
+   else
dev_priv->gt.resume = intel_legacy_submission_resume;
-   dev_priv->gt.cleanup_engine = intel_engine_cleanup;
-   }
 
/* This is just a security blanket to placate dragons.
 * On some systems, we very sporadically observe that the first TLBs
@@ -4658,16 +4655,6 @@ void i915_gem_init_mmio(struct drm_i915_private *i915)
 }
 
 void
-i915_gem_cleanup_engines(struct drm_i915_private *dev_priv)
-{
-   struct intel_engine_cs *engine;
-   enum intel_engine_id id;
-
-   for_each_engine(engine, dev_priv, id)
-   dev_priv->gt.cleanup_engine(engine);
-}
-
-void
 i915_gem_load_init_fences(struct drm_i915_private *dev_priv)
 {
int i;
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 4045b971a0ff..bd91aa1f0deb 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -214,7 +214,7 @@ int intel_engines_init(struct drm_i915_private *dev_priv)
if (id >= err_id)
kfree(engine);
else
-   dev_priv->gt.cleanup_engine(engine);
+   engine->cleanup(engine);
}
return err;
 }
@@ -1116,6 +1116,15 @@ void intel_engines_reset_default_submission(struct 
drm_i915_private *i915)
engine->set_default_submission(engine);
 }
 
+void intel_engines_cleanup(struct drm_i915_private *i915)
+{
+   struct intel_engine_cs *engine;
+   enum intel_engine_id id;
+
+   for_each_engine(engine, i915, id)
+   engine->cleanup(engine);
+}
+
 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
 #include "selftests/mock_engine.c"
 #endif
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 3bab62c2d800..d45e6d13545a 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1518,13 +1518,9 @@ static int gen8_init_rcs_context(struct 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Refactor the retrieval of guc_process_desc

[Patchwork]

== Series Details ==

Series: drm/i915/guc: Refactor the retrieval of guc_process_desc
URL   : https://patchwork.freedesktop.org/series/21795/
State : success

== Summary ==

Series 21795v1 drm/i915/guc: Refactor the retrieval of guc_process_desc
https://patchwork.freedesktop.org/api/1.0/series/21795/revisions/1/mbox/

Test gem_exec_flush:
Subgroup basic-batch-kernel-default-uc:
pass   -> FAIL   (fi-snb-2600) fdo#17

fdo#17 https://bugs.freedesktop.org/show_bug.cgi?id=17

fi-bdw-5557u total:278  pass:267  dwarn:0   dfail:0   fail:0   skip:11  
time: 455s
fi-bdw-gvtdvmtotal:278  pass:256  dwarn:8   dfail:0   fail:0   skip:14  
time: 454s
fi-bsw-n3050 total:278  pass:239  dwarn:0   dfail:0   fail:0   skip:39  
time: 584s
fi-bxt-j4205 total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19  
time: 538s
fi-bxt-t5700 total:278  pass:258  dwarn:0   dfail:0   fail:0   skip:20  
time: 579s
fi-byt-j1900 total:278  pass:251  dwarn:0   dfail:0   fail:0   skip:27  
time: 506s
fi-byt-n2820 total:278  pass:247  dwarn:0   dfail:0   fail:0   skip:31  
time: 505s
fi-hsw-4770  total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time: 437s
fi-hsw-4770r total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time: 436s
fi-ilk-650   total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50  
time: 444s
fi-ivb-3520m total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time: 512s
fi-ivb-3770  total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time: 494s
fi-kbl-7500u total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time: 484s
fi-skl-6260u total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time: 494s
fi-skl-6700hqtotal:278  pass:261  dwarn:0   dfail:0   fail:0   skip:17  
time: 596s
fi-skl-6700k total:278  pass:256  dwarn:4   dfail:0   fail:0   skip:18  
time: 487s
fi-skl-6770hqtotal:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time: 516s
fi-skl-gvtdvmtotal:278  pass:265  dwarn:0   dfail:0   fail:0   skip:13  
time: 462s
fi-snb-2520m total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  
time: 543s
fi-snb-2600  total:278  pass:248  dwarn:0   dfail:0   fail:1   skip:29  
time: 422s

fd27e1e4c9b5dc11966b4953432bd6e0510da308 drm-tip: 2017y-03m-24d-08h-39m-20s UTC 
integration manifest
5a2e711 drm/i915/guc: Refactor the retrieval of guc_process_desc

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4285/
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Moar plane update optimizations (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915: Moar plane update optimizations (rev4)
URL   : https://patchwork.freedesktop.org/series/21475/
State : success

== Summary ==

Series 21475v4 drm/i915: Moar plane update optimizations
https://patchwork.freedesktop.org/api/1.0/series/21475/revisions/4/mbox/

Test gem_exec_flush:
Subgroup basic-batch-kernel-default-uc:
pass   -> FAIL   (fi-snb-2600) fdo#17
Test gem_exec_suspend:
Subgroup basic-s4-devices:
pass   -> DMESG-WARN (fi-bxt-t5700) fdo#100125

fdo#17 https://bugs.freedesktop.org/show_bug.cgi?id=17
fdo#100125 https://bugs.freedesktop.org/show_bug.cgi?id=100125

fi-bdw-5557u total:278  pass:267  dwarn:0   dfail:0   fail:0   skip:11  
time: 464s
fi-bdw-gvtdvmtotal:278  pass:256  dwarn:8   dfail:0   fail:0   skip:14  
time: 462s
fi-bsw-n3050 total:278  pass:239  dwarn:0   dfail:0   fail:0   skip:39  
time: 576s
fi-bxt-j4205 total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19  
time: 539s
fi-bxt-t5700 total:278  pass:257  dwarn:1   dfail:0   fail:0   skip:20  
time: 576s
fi-byt-j1900 total:278  pass:251  dwarn:0   dfail:0   fail:0   skip:27  
time: 509s
fi-byt-n2820 total:278  pass:247  dwarn:0   dfail:0   fail:0   skip:31  
time: 502s
fi-hsw-4770  total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time: 436s
fi-hsw-4770r total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time: 430s
fi-ilk-650   total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50  
time: 441s
fi-ivb-3520m total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time: 526s
fi-ivb-3770  total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time: 495s
fi-kbl-7500u total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time: 487s
fi-skl-6260u total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time: 480s
fi-skl-6700hqtotal:278  pass:261  dwarn:0   dfail:0   fail:0   skip:17  
time: 597s
fi-skl-6700k total:278  pass:256  dwarn:4   dfail:0   fail:0   skip:18  
time: 484s
fi-skl-6770hqtotal:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time: 527s
fi-skl-gvtdvmtotal:278  pass:265  dwarn:0   dfail:0   fail:0   skip:13  
time: 464s
fi-snb-2520m total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  
time: 548s
fi-snb-2600  total:278  pass:248  dwarn:0   dfail:0   fail:1   skip:29  
time: 424s

fd27e1e4c9b5dc11966b4953432bd6e0510da308 drm-tip: 2017y-03m-24d-08h-39m-20s UTC 
integration manifest
f0802c0 drm/i915: Use i9xx_check_plane_surface() for sprite planes as well
faabda6 drm/i915: Eliminate ironlake_update_primary_plane()
8c56d06 drm/i915: Introduce i9xx_check_plane_surface()
0e8a06b drm/i915: Pre-compute plane control register value
3d6d2c0 drm/i915: Nuke ironlake_plane_ctl()
bc357e8 drm/i915: Extract i9xx_plane_ctl() and ironlake_plane_ctl()

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4284/
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[Intel-gfx] [PATCHi v2] drm/i915: Enhanced disable access to stolen memory as a guest

[Xiong Zhang]

commit "04a68a3 drm/i915/gvt: Disable access to stolen memory as a guest"
isn't enough in GVT-d which will pass through IGD to guest and don't run
vgt code. While intel_vgpu_active() is true only when vgt code run on
host and guest in GVT-g.

v2:GVT-g may run in non qemu (Zhenyu)

Signed-off-by: Xiong Zhang 
---
 drivers/gpu/drm/i915/i915_drv.c| 1 +
 drivers/gpu/drm/i915/i915_drv.h| 1 +
 drivers/gpu/drm/i915/i915_gem_stolen.c | 4 ++--
 3 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 03d9e45..8b807a9 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -223,6 +223,7 @@ static void intel_detect_pch(struct drm_i915_private 
*dev_priv)
PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
pch->subsystem_device ==
PCI_SUBDEVICE_ID_QEMU)) {
+   dev_priv->run_on_qemu = true;
dev_priv->pch_type =
intel_virt_detect_pch(dev_priv);
} else
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a5947a4..ad95c87 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2145,6 +2145,7 @@ struct drm_i915_private {
struct intel_uncore uncore;
 
struct i915_virtual_gpu vgpu;
+   bool run_on_qemu;
 
struct intel_gvt *gvt;
 
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c 
b/drivers/gpu/drm/i915/i915_gem_stolen.c
index f3abdc2..6a011b0 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -409,8 +409,8 @@ int i915_gem_init_stolen(struct drm_i915_private *dev_priv)
 
mutex_init(_priv->mm.stolen_lock);
 
-   if (intel_vgpu_active(dev_priv)) {
-   DRM_INFO("iGVT-g active, disabling use of stolen memory\n");
+   if (dev_priv->run_on_qemu || intel_vgpu_active(dev_priv)) {
+   DRM_INFO("Running in guest, disabling use of stolen memory\n");
return 0;
}
 
-- 
1.9.1

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Re: [Intel-gfx] [PATCH 08/19] drm/tilcdc: Drop calls to modeset_lock_crtc

[Tomi Valkeinen]

On 22/03/17 23:50, Daniel Vetter wrote:
> Again this is an internal helper, not the official way to lock a crtc.
> 
> Cc: Jyri Sarha 
> Cc: Tomi Valkeinen 
> Signed-off-by: Daniel Vetter 
> ---
>  drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 12 ++--
>  1 file changed, 6 insertions(+), 6 deletions(-)

Reviewed-by: Tomi Valkeinen 

 Tomi



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[Intel-gfx] ✗ Fi.CI.BAT: failure for Some minor i915-perf prep changes (rev2)

[Patchwork]

== Series Details ==

Series: Some minor i915-perf prep changes (rev2)
URL   : https://patchwork.freedesktop.org/series/20073/
State : failure

== Summary ==

Series 20073v2 Some minor i915-perf prep changes
https://patchwork.freedesktop.org/api/1.0/series/20073/revisions/2/mbox/

Test drv_getparams_basic:
Subgroup basic-eu-total:
pass   -> INCOMPLETE (fi-byt-j1900)
Test gem_exec_suspend:
Subgroup basic-s4-devices:
pass   -> DMESG-WARN (fi-snb-2600)

fi-bdw-5557u total:278  pass:267  dwarn:0   dfail:0   fail:0   skip:11  
time: 461s
fi-bdw-gvtdvmtotal:278  pass:256  dwarn:8   dfail:0   fail:0   skip:14  
time: 461s
fi-bsw-n3050 total:278  pass:239  dwarn:0   dfail:0   fail:0   skip:39  
time: 586s
fi-bxt-j4205 total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19  
time: 531s
fi-bxt-t5700 total:278  pass:258  dwarn:0   dfail:0   fail:0   skip:20  
time: 583s
fi-byt-j1900 total:3pass:2dwarn:0   dfail:0   fail:0   skip:0   
time: 0s
fi-byt-n2820 total:278  pass:247  dwarn:0   dfail:0   fail:0   skip:31  
time: 501s
fi-hsw-4770  total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time: 446s
fi-hsw-4770r total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time: 430s
fi-ilk-650   total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50  
time: 444s
fi-ivb-3520m total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time: 516s
fi-ivb-3770  total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time: 496s
fi-kbl-7500u total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time: 488s
fi-skl-6260u total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time: 487s
fi-skl-6700hqtotal:278  pass:261  dwarn:0   dfail:0   fail:0   skip:17  
time: 610s
fi-skl-6700k total:278  pass:256  dwarn:4   dfail:0   fail:0   skip:18  
time: 491s
fi-skl-6770hqtotal:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time: 533s
fi-skl-gvtdvmtotal:278  pass:265  dwarn:0   dfail:0   fail:0   skip:13  
time: 461s
fi-snb-2520m total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  
time: 547s
fi-snb-2600  total:278  pass:248  dwarn:1   dfail:0   fail:0   skip:29  
time: 421s

fd27e1e4c9b5dc11966b4953432bd6e0510da308 drm-tip: 2017y-03m-24d-08h-39m-20s UTC 
integration manifest
7eb53856 drm/i915/perf: improve invalid OA format debug message

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4283/
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[Intel-gfx] [PATCH 2/2] drm/i915: Remove obsolete ringbuffer emission for gen8+

[Chris Wilson]

Since removing the module parameter to force selection of ringbuffer
emission for gen8, the code is defunct. Remove it.

References: https://bugs.freedesktop.org/show_bug.cgi?id=87725
Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_debugfs.c |  44 +---
 drivers/gpu/drm/i915/i915_drv.h |   2 -
 drivers/gpu/drm/i915/i915_gem.c |   4 +-
 drivers/gpu/drm/i915/i915_gpu_error.c   |  41 +---
 drivers/gpu/drm/i915/intel_engine_cs.c  |  12 -
 drivers/gpu/drm/i915/intel_hangcheck.c  |  44 +---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 407 +---
 drivers/gpu/drm/i915/intel_ringbuffer.h |  25 +-
 8 files changed, 87 insertions(+), 492 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 67289dec657a..dbd97fd52b00 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3346,44 +3346,12 @@ static int i915_semaphore_status(struct seq_file *m, 
void *unused)
return ret;
intel_runtime_pm_get(dev_priv);
 
-   if (IS_BROADWELL(dev_priv)) {
-   struct page *page;
-   uint64_t *seqno;
-
-   page = i915_gem_object_get_page(dev_priv->semaphore->obj, 0);
-
-   seqno = (uint64_t *)kmap_atomic(page);
-   for_each_engine(engine, dev_priv, id) {
-   uint64_t offset;
-
-   seq_printf(m, "%s\n", engine->name);
-
-   seq_puts(m, "  Last signal:");
-   for (j = 0; j < num_rings; j++) {
-   offset = id * I915_NUM_ENGINES + j;
-   seq_printf(m, "0x%08llx (0x%02llx) ",
-  seqno[offset], offset * 8);
-   }
-   seq_putc(m, '\n');
-
-   seq_puts(m, "  Last wait:  ");
-   for (j = 0; j < num_rings; j++) {
-   offset = id + (j * I915_NUM_ENGINES);
-   seq_printf(m, "0x%08llx (0x%02llx) ",
-  seqno[offset], offset * 8);
-   }
-   seq_putc(m, '\n');
-
-   }
-   kunmap_atomic(seqno);
-   } else {
-   seq_puts(m, "  Last signal:");
-   for_each_engine(engine, dev_priv, id)
-   for (j = 0; j < num_rings; j++)
-   seq_printf(m, "0x%08x\n",
-  
I915_READ(engine->semaphore.mbox.signal[j]));
-   seq_putc(m, '\n');
-   }
+   seq_puts(m, "  Last signal:");
+   for_each_engine(engine, dev_priv, id)
+   for (j = 0; j < num_rings; j++)
+   seq_printf(m, "0x%08x\n",
+  I915_READ(engine->semaphore.mbox.signal[j]));
+   seq_putc(m, '\n');
 
intel_runtime_pm_put(dev_priv);
mutex_unlock(>struct_mutex);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c767b50c14ff..e20a21c7ecdf 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -981,7 +981,6 @@ struct i915_gpu_state {
u64 fence[I915_MAX_NUM_FENCES];
struct intel_overlay_error_state *overlay;
struct intel_display_error_state *display;
-   struct drm_i915_error_object *semaphore;
struct drm_i915_error_object *guc_log;
 
struct drm_i915_error_engine {
@@ -2202,7 +2201,6 @@ struct drm_i915_private {
struct pci_dev *bridge_dev;
struct i915_gem_context *kernel_context;
struct intel_engine_cs *engine[I915_NUM_ENGINES];
-   struct i915_vma *semaphore;
 
struct drm_dma_handle *status_page_dmah;
struct resource mch_res;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 1b5b2be33e80..5704dbfe5653 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4574,7 +4574,7 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
 
 bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value)
 {
-   if (INTEL_INFO(dev_priv)->gen < 6)
+   if (INTEL_GEN(dev_priv) < 6)
return false;
 
/* TODO: make semaphores and Execlists play nicely together */
@@ -4586,7 +4586,7 @@ bool intel_sanitize_semaphores(struct drm_i915_private 
*dev_priv, int value)
 
 #ifdef CONFIG_INTEL_IOMMU
/* Enable semaphores on SNB when IO remapping is off */
-   if (INTEL_INFO(dev_priv)->gen == 6 && intel_iommu_gfx_mapped)
+   if (INTEL_GEN(dev_priv) == 6 && intel_iommu_gfx_mapped)
return false;
 #endif
 
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 4b247b050dcd..b08cf6e2a510 100644
--- 

[Intel-gfx] [PATCH 1/2] drm/i915: Remove i915.enable_execlists module parameter

[Chris Wilson]

Execlists and legacy ringbuffer submission are no longer feature
comparable (execlists now offer greater functionality that should
overcome their performance hit) and obsoletes the unsafe module
parameter, i.e. comparing the two modes of execution is no longer
useful, so remove the debug tool.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/gvt/render.c   |  3 +-
 drivers/gpu/drm/i915/i915_debugfs.c | 72 +
 drivers/gpu/drm/i915/i915_drv.c |  4 --
 drivers/gpu/drm/i915/i915_drv.h |  1 +
 drivers/gpu/drm/i915/i915_gem.c | 12 +++---
 drivers/gpu/drm/i915/i915_gem_context.c | 22 --
 drivers/gpu/drm/i915/i915_gem_gtt.c |  4 +-
 drivers/gpu/drm/i915/i915_params.c  |  6 ---
 drivers/gpu/drm/i915/i915_params.h  |  1 -
 drivers/gpu/drm/i915/intel_display.c|  5 ++-
 drivers/gpu/drm/i915/intel_engine_cs.c  |  2 +-
 drivers/gpu/drm/i915/intel_gvt.c|  9 ++---
 drivers/gpu/drm/i915/intel_lrc.c| 32 ---
 drivers/gpu/drm/i915/intel_lrc.h|  4 --
 drivers/gpu/drm/i915/intel_pm.c |  2 +-
 15 files changed, 28 insertions(+), 151 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/render.c 
b/drivers/gpu/drm/i915/gvt/render.c
index 95ee091ce085..c762a44e61ff 100644
--- a/drivers/gpu/drm/i915/gvt/render.c
+++ b/drivers/gpu/drm/i915/gvt/render.c
@@ -286,8 +286,7 @@ void intel_gvt_load_render_mmio(struct intel_vgpu *vgpu, 
int ring_id)
 * write.
 */
if (mmio->in_context &&
-   ((ctx_ctrl & inhibit_mask) != inhibit_mask) &&
-   i915.enable_execlists)
+   (ctx_ctrl & inhibit_mask) != inhibit_mask)
continue;
 
if (mmio->mask)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 5e7175abee76..67289dec657a 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1999,75 +1999,6 @@ static int i915_context_status(struct seq_file *m, void 
*unused)
return 0;
 }
 
-static void i915_dump_lrc_obj(struct seq_file *m,
- struct i915_gem_context *ctx,
- struct intel_engine_cs *engine)
-{
-   struct i915_vma *vma = ctx->engine[engine->id].state;
-   struct page *page;
-   int j;
-
-   seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id);
-
-   if (!vma) {
-   seq_puts(m, "\tFake context\n");
-   return;
-   }
-
-   if (vma->flags & I915_VMA_GLOBAL_BIND)
-   seq_printf(m, "\tBound in GGTT at 0x%08x\n",
-  i915_ggtt_offset(vma));
-
-   if (i915_gem_object_pin_pages(vma->obj)) {
-   seq_puts(m, "\tFailed to get pages for context object\n\n");
-   return;
-   }
-
-   page = i915_gem_object_get_page(vma->obj, LRC_STATE_PN);
-   if (page) {
-   u32 *reg_state = kmap_atomic(page);
-
-   for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
-   seq_printf(m,
-  "\t[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n",
-  j * 4,
-  reg_state[j], reg_state[j + 1],
-  reg_state[j + 2], reg_state[j + 3]);
-   }
-   kunmap_atomic(reg_state);
-   }
-
-   i915_gem_object_unpin_pages(vma->obj);
-   seq_putc(m, '\n');
-}
-
-static int i915_dump_lrc(struct seq_file *m, void *unused)
-{
-   struct drm_i915_private *dev_priv = node_to_i915(m->private);
-   struct drm_device *dev = _priv->drm;
-   struct intel_engine_cs *engine;
-   struct i915_gem_context *ctx;
-   enum intel_engine_id id;
-   int ret;
-
-   if (!i915.enable_execlists) {
-   seq_printf(m, "Logical Ring Contexts are disabled\n");
-   return 0;
-   }
-
-   ret = mutex_lock_interruptible(>struct_mutex);
-   if (ret)
-   return ret;
-
-   list_for_each_entry(ctx, _priv->context_list, link)
-   for_each_engine(engine, dev_priv, id)
-   i915_dump_lrc_obj(m, ctx, engine);
-
-   mutex_unlock(>struct_mutex);
-
-   return 0;
-}
-
 static const char *swizzle_string(unsigned swizzle)
 {
switch (swizzle) {
@@ -3317,7 +3248,7 @@ static int i915_engine_info(struct seq_file *m, void 
*unused)
seq_printf(m, "\tBBADDR: 0x%08x_%08x\n",
   upper_32_bits(addr), lower_32_bits(addr));
 
-   if (i915.enable_execlists) {
+   if (USE_EXECLISTS(dev_priv)) {
u32 ptr, read, write;
struct rb_node *rb;
 
@@ -4791,7 +4722,6 @@ static const struct drm_info_list i915_debugfs_list[] = {
{"i915_vbt", i915_vbt, 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Replace literal tabs in ns2501 debug messages with spaces

[Patchwork]

== Series Details ==

Series: drm/i915: Replace literal tabs in ns2501 debug messages with spaces
URL   : https://patchwork.freedesktop.org/series/21787/
State : success

== Summary ==

Series 21787v1 drm/i915: Replace literal tabs in ns2501 debug messages with 
spaces
https://patchwork.freedesktop.org/api/1.0/series/21787/revisions/1/mbox/

fi-bdw-5557u total:278  pass:267  dwarn:0   dfail:0   fail:0   skip:11  
time: 469s
fi-bdw-gvtdvmtotal:278  pass:256  dwarn:8   dfail:0   fail:0   skip:14  
time: 455s
fi-bsw-n3050 total:278  pass:239  dwarn:0   dfail:0   fail:0   skip:39  
time: 581s
fi-bxt-j4205 total:278  pass:259  dwarn:0   dfail:0   fail:0   skip:19  
time: 538s
fi-bxt-t5700 total:278  pass:258  dwarn:0   dfail:0   fail:0   skip:20  
time: 569s
fi-byt-j1900 total:278  pass:251  dwarn:0   dfail:0   fail:0   skip:27  
time: 510s
fi-byt-n2820 total:278  pass:247  dwarn:0   dfail:0   fail:0   skip:31  
time: 499s
fi-hsw-4770  total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time: 433s
fi-hsw-4770r total:278  pass:262  dwarn:0   dfail:0   fail:0   skip:16  
time: 434s
fi-ilk-650   total:278  pass:228  dwarn:0   dfail:0   fail:0   skip:50  
time: 436s
fi-ivb-3520m total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time: 520s
fi-ivb-3770  total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time: 514s
fi-kbl-7500u total:278  pass:260  dwarn:0   dfail:0   fail:0   skip:18  
time: 482s
fi-skl-6260u total:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time: 478s
fi-skl-6700hqtotal:278  pass:261  dwarn:0   dfail:0   fail:0   skip:17  
time: 602s
fi-skl-6700k total:278  pass:256  dwarn:4   dfail:0   fail:0   skip:18  
time: 492s
fi-skl-6770hqtotal:278  pass:268  dwarn:0   dfail:0   fail:0   skip:10  
time: 520s
fi-skl-gvtdvmtotal:278  pass:265  dwarn:0   dfail:0   fail:0   skip:13  
time: 462s
fi-snb-2520m total:278  pass:250  dwarn:0   dfail:0   fail:0   skip:28  
time: 545s
fi-snb-2600  total:278  pass:249  dwarn:0   dfail:0   fail:0   skip:29  
time: 429s

fd27e1e4c9b5dc11966b4953432bd6e0510da308 drm-tip: 2017y-03m-24d-08h-39m-20s UTC 
integration manifest
a78c7ed drm/i915: Replace literal tabs in ns2501 debug messages with spaces

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_4282/
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Re: [Intel-gfx] [PATCH dim 2/2] dim: Curate and insert tags into patch(es)

[Ville Syrjälä]

On Thu, Mar 23, 2017 at 05:07:28PM -0400, Sean Paul wrote:
> Launch $EDITOR when extracting tags to curate the tags immediately. Once the
> tags are proper, automatically add them before the first Signed-off-by line
> to all patches in the range.

Not sure adding them before the first sob is the right thing. If we want
the tags to reflect the history somehow, then I suppose they should go
just before *your* sob, which may or may not be the first sob in the
commit message. Personally I've just started slapping them to the end
which also maintains the history, but granted it doesn't really show who
signed off on those tags. Or is there some "official" rule how tags
should be sorted in commit messages?

And I don't like the $EDITOR idea either, so at least make it
optional.

> 
> Signed-off-by: Sean Paul 
> ---
>  dim | 13 ++---
>  1 file changed, 10 insertions(+), 3 deletions(-)
> 
> diff --git a/dim b/dim
> index 43ea794..6a5580a 100755
> --- a/dim
> +++ b/dim
> @@ -1145,6 +1145,12 @@ function rangeish()
>   fi
>  }
>  
> +function insert_extracted_tags
> +{
> + new_tabs=`cat $1 | awk '{ORS="n"} {print $0}' | head -c-3`
> + awk "/Signed-off-by/{p++} p==1{print \"$new_tabs\"; p++} p!=1{print}"
> +}
> +
>  function dim_extract_tags
>  {
>   local branch range file tags
> @@ -1167,9 +1173,10 @@ function dim_extract_tags
>   return 0
>   fi
>  
> - tags=$(printf -- "# *** extracted tags ***\n%s" "$tags")
> -
> - git filter-branch -f --msg-filter "cat ; echo \"$tags\"" $range
> + echo "$tags" > $file
> + $EDITOR $file
> + export -f insert_extracted_tags
> + git filter-branch -f --msg-filter "insert_extracted_tags $file" $range
>  }
>  
>  function dim_extract_queued
> -- 
> 2.12.1.500.gab5fba24ee-goog

-- 
Ville Syrjälä
Intel OTC
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Re: [Intel-gfx] [PATCH v4 03/13] drm/i915/guc: Add onion teardown to the GuC setup

[Chris Wilson]

On Thu, Mar 23, 2017 at 09:36:10AM -0700, Oscar Mateo wrote:
> On 03/23/2017 03:57 PM, Chris Wilson wrote:
> >I'm not happy with moving subfeature detection logic into the core GEM
> >code. if (i915.enable_guc_loading) firstly should never be a module
> >parameter (it's derived state!) and secondly it should reside next to
> >the dependent logic and not be interrupting the central control flow.
> What do you mean it's derived state? from what?

The set of features, whether to use guc submission, huc, or whether
there is a platform requirement to load the firmware, define whether or
not we need to request and upload a particular firmware. Every module
option should be a quirk to alter driver behaviour (i.e. a debugging
crutch), few and strongly justified (we have too many) and necessarily
global in scope. Device specific options should ideally use a more
specific interface (most clear examples are the panel specific quirks).
-Chris

-- 
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Re: [Intel-gfx] [PATCH] drm/debugfs: Add kerneldoc

[Daniel Vetter]

On Wed, Mar 22, 2017 at 09:54:01PM +0100, Daniel Vetter wrote:
> I've decided to not document drm_debugfs_remove_files, it's on the way
> out.
> 
> The biggest part is a huge todo.rst entry with what all should be
> improved.
> 
> v2: Nits from Gabriel.
> 
> Cc: Gabriel Krisman Bertazi 
> Reviewed-by: Gabriel Krisman Bertazi 
> Signed-off-by: Daniel Vetter 

Merged up to this patch to drm-misc-next.

I will trade reviews for more reviews to help get the remaining in!

Thanks, Daniel
> ---
>  Documentation/gpu/drm-uapi.rst |  9 
>  Documentation/gpu/todo.rst | 26 +
>  drivers/gpu/drm/drm_debugfs.c  | 51 
> ++
>  drivers/gpu/drm/drm_internal.h |  2 +-
>  include/drm/drm_debugfs.h  | 38 +--
>  5 files changed, 74 insertions(+), 52 deletions(-)
> 
> diff --git a/Documentation/gpu/drm-uapi.rst b/Documentation/gpu/drm-uapi.rst
> index 369e8ca12b8e..76356c86e358 100644
> --- a/Documentation/gpu/drm-uapi.rst
> +++ b/Documentation/gpu/drm-uapi.rst
> @@ -210,6 +210,15 @@ Display CRC Support
>  .. kernel-doc:: drivers/gpu/drm/drm_debugfs_crc.c
> :export:
>  
> +Debugfs Support
> +---
> +
> +.. kernel-doc:: include/drm/drm_debugfs.h
> +   :internal:
> +
> +.. kernel-doc:: drivers/gpu/drm/drm_debugfs.c
> +   :export:
> +
>  VBlank event handling
>  =
>  
> diff --git a/Documentation/gpu/todo.rst b/Documentation/gpu/todo.rst
> index 64e9d16170ce..0cdaddad2b9b 100644
> --- a/Documentation/gpu/todo.rst
> +++ b/Documentation/gpu/todo.rst
> @@ -272,6 +272,32 @@ This is a really varied tasks with lots of little bits 
> and pieces:
>  
>  Contact: Daniel Vetter
>  
> +Clean up the debugfs support
> +
> +
> +There's a bunch of issues with it:
> +
> +- The drm_info_list ->show() function doesn't even bother to cast to the drm
> +  structure for you. This is lazy.
> +
> +- We probably want to have some support for debugfs files on crtc/connectors 
> and
> +  maybe other kms objects directly in core. There's even drm_print support in
> +  the funcs for these objects to dump kms state, so it's all there. And then 
> the
> +  ->show() functions should obviously give you a pointer to the right object.
> +
> +- The drm_info_list stuff is centered on drm_minor instead of drm_device. For
> +  anything we want to print drm_device (or maybe drm_file) is the right 
> thing.
> +
> +- The drm_driver->debugfs_init hooks we have is just an artifact of the old
> +  midlayered load sequence. DRM debugfs should work more like sysfs, where 
> you
> +  can create properties/files for an object anytime you want, and the core
> +  takes care of publishing/unpuplishing all the files at register/unregister
> +  time. Drivers shouldn't need to worry about these technicalities, and 
> fixing
> +  this (together with the drm_minor->drm_device move) would allow us to 
> remove
> +  debugfs_init.
> +
> +Contact: Daniel Vetter
> +
>  Better Testing
>  ==
>  
> diff --git a/drivers/gpu/drm/drm_debugfs.c b/drivers/gpu/drm/drm_debugfs.c
> index 4b02f4230562..c1807d5754b2 100644
> --- a/drivers/gpu/drm/drm_debugfs.c
> +++ b/drivers/gpu/drm/drm_debugfs.c
> @@ -1,10 +1,3 @@
> -/**
> - * \file drm_debugfs.c
> - * debugfs support for DRM
> - *
> - * \author Ben Gamari 
> - */
> -
>  /*
>   * Created: Sun Dec 21 13:08:50 2008 by bgam...@gmail.com
>   *
> @@ -75,16 +68,15 @@ static const struct file_operations drm_debugfs_fops = {
>  
>  
>  /**
> - * Initialize a given set of debugfs files for a device
> - *
> - * \param files The array of files to create
> - * \param count The number of files given
> - * \param root DRI debugfs dir entry.
> - * \param minor device minor number
> - * \return Zero on success, non-zero on failure
> + * drm_debugfs_create_files - Initialize a given set of debugfs files for DRM
> + *   minor
> + * @files: The array of files to create
> + * @count: The number of files given
> + * @root: DRI debugfs dir entry.
> + * @minor: device minor number
>   *
>   * Create a given set of debugfs files represented by an array of
> - * _info_list in the given root directory. These files will be removed
> + *  drm_info_list in the given root directory. These files will be 
> removed
>   * automatically on drm_debugfs_cleanup().
>   */
>  int drm_debugfs_create_files(const struct drm_info_list *files, int count,
> @@ -133,17 +125,6 @@ int drm_debugfs_create_files(const struct drm_info_list 
> *files, int count,
>  }
>  EXPORT_SYMBOL(drm_debugfs_create_files);
>  
> -/**
> - * Initialize the DRI debugfs filesystem for a device
> - *
> - * \param dev DRM device
> - * \param minor device minor number
> - * \param root DRI debugfs dir entry.
> - *
> - * Create the DRI debugfs root entry "/sys/kernel/debug/dri", the device 
> debugfs root entry
> - * 

Re: [Intel-gfx] [PATCH dim 2/2] dim: Curate and insert tags into patch(es)

[Jani Nikula]

On Thu, 23 Mar 2017, Sean Paul  wrote:
> Launch $EDITOR when extracting tags to curate the tags immediately. Once the
> tags are proper, automatically add them before the first Signed-off-by line
> to all patches in the range.

Two problems I have with this. First, I like to edit the final commit
message, not an intermediate file. Second, I pipe messages to dim
extract-tags *from* my $EDITOR, so I'd rather not have it launch $EDITOR
again.

BR,
Jani.

>
> Signed-off-by: Sean Paul 
> ---
>  dim | 13 ++---
>  1 file changed, 10 insertions(+), 3 deletions(-)
>
> diff --git a/dim b/dim
> index 43ea794..6a5580a 100755
> --- a/dim
> +++ b/dim
> @@ -1145,6 +1145,12 @@ function rangeish()
>   fi
>  }
>  
> +function insert_extracted_tags
> +{
> + new_tabs=`cat $1 | awk '{ORS="n"} {print $0}' | head -c-3`
> + awk "/Signed-off-by/{p++} p==1{print \"$new_tabs\"; p++} p!=1{print}"
> +}
> +
>  function dim_extract_tags
>  {
>   local branch range file tags
> @@ -1167,9 +1173,10 @@ function dim_extract_tags
>   return 0
>   fi
>  
> - tags=$(printf -- "# *** extracted tags ***\n%s" "$tags")
> -
> - git filter-branch -f --msg-filter "cat ; echo \"$tags\"" $range
> + echo "$tags" > $file
> + $EDITOR $file
> + export -f insert_extracted_tags
> + git filter-branch -f --msg-filter "insert_extracted_tags $file" $range
>  }
>  
>  function dim_extract_queued

-- 
Jani Nikula, Intel Open Source Technology Center
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Re: [Intel-gfx] [PATCH] drm/i915: Enhanced disable access to stolen memory as a guest

[Zhenyu Wang]

On 2017.03.24 15:23:24 +0800, Xiong Zhang wrote:
> commit "04a68a3 drm/i915/gvt: Disable access to stolen memory as a guest"
> isn't enough in GVT-d which will pass through IGD to guest and don't run
> vgt code. While intel_vgpu_active() is true only when vgt code run on
> host and guest in GVT-g.
> 
> Signed-off-by: Xiong Zhang 
> ---
>  drivers/gpu/drm/i915/i915_drv.c| 1 +
>  drivers/gpu/drm/i915/i915_drv.h| 1 +
>  drivers/gpu/drm/i915/i915_gem_stolen.c | 4 ++--
>  3 files changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 03d9e45..8b807a9 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -223,6 +223,7 @@ static void intel_detect_pch(struct drm_i915_private 
> *dev_priv)
>   PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
>   pch->subsystem_device ==
>   PCI_SUBDEVICE_ID_QEMU)) {
> + dev_priv->run_on_qemu = true;
>   dev_priv->pch_type =
>   intel_virt_detect_pch(dev_priv);
>   } else
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index a5947a4..ad95c87 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2145,6 +2145,7 @@ struct drm_i915_private {
>   struct intel_uncore uncore;
>  
>   struct i915_virtual_gpu vgpu;
> + bool run_on_qemu;
>  
>   struct intel_gvt *gvt;
>  
> diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c 
> b/drivers/gpu/drm/i915/i915_gem_stolen.c
> index f3abdc2..07e1721 100644
> --- a/drivers/gpu/drm/i915/i915_gem_stolen.c
> +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
> @@ -409,8 +409,8 @@ int i915_gem_init_stolen(struct drm_i915_private 
> *dev_priv)
>  
>   mutex_init(_priv->mm.stolen_lock);
>  
> - if (intel_vgpu_active(dev_priv)) {
> - DRM_INFO("iGVT-g active, disabling use of stolen memory\n");
> + if (dev_priv->run_on_qemu) {
> + DRM_INFO("Run on qemu, disabling use of stolen memory\n");
>   return 0;

Shouldn't remove vgpu active check which is based on pvinfo, we don't want to
depend on some qemu machine config but pvinfo interface is officially defined.

-- 
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Re: [Intel-gfx] [PATCH v2] drm/i915: Reduce Data Link N value for 1 lane DP->hdmi converters

[Daniel Vetter]

On Thu, Mar 23, 2017 at 04:38:58PM -0700, clinton.a.tay...@intel.com wrote:
> From: Clint Taylor 
> 
> Several major vendor USB-C->HDMI converters fail to recover a 5.4 GHz 1 lane
> signal if the Data Link N is greater than 0x8.
> Patch detects when 1 lane 5.4 GHz signal is being used and makes the maximum
> value 20 bit instead of the maximum specification supported 24 bit value.
> 
> v2: Detect specific device that exhibits the issue.

Since this is a sink quirk, shouldn't we have this in the dp helpers to be
able to share it with all other drivers. There will be more quirks like
this, starting with a sink quirk table imo makes sense (like we already
have an edid quirk table).
-Daniel


> 
> Cc: Dhinakaran Pandiyan 
> Cc: Jani Nikula 
> Cc: Anusha Srivatsa 
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93578
> 
> Signed-off-by: Clint Taylor 
> ---
>  drivers/gpu/drm/i915/i915_drv.h  |3 ++-
>  drivers/gpu/drm/i915/i915_reg.h  |2 ++
>  drivers/gpu/drm/i915/intel_display.c |   20 ++--
>  drivers/gpu/drm/i915/intel_dp.c  |   14 --
>  drivers/gpu/drm/i915/intel_dp_mst.c  |3 ++-
>  5 files changed, 32 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index a5947a4..6869df9 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -580,7 +580,8 @@ struct intel_link_m_n {
>  
>  void intel_link_compute_m_n(int bpp, int nlanes,
>   int pixel_clock, int link_clock,
> - struct intel_link_m_n *m_n);
> + struct intel_link_m_n *m_n,
> + bool reduced_n);
>  
>  /* Interface history:
>   *
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 04c8f69..838d8d5 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4869,6 +4869,8 @@ enum {
>  
>  #define  DATA_LINK_M_N_MASK  (0xff)
>  #define  DATA_LINK_N_MAX (0x80)
> +/* Maximum N value useable on some DP->HDMI converters */
> +#define  DATA_LINK_REDUCED_N_MAX (0x8)
>  
>  #define _PIPEA_DATA_N_G4X0x70054
>  #define _PIPEB_DATA_N_G4X0x71054
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index 010e5dd..143c7ac 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6139,7 +6139,7 @@ static int ironlake_fdi_compute_config(struct 
> intel_crtc *intel_crtc,
>   pipe_config->fdi_lanes = lane;
>  
>   intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
> -link_bw, _config->fdi_m_n);
> +link_bw, _config->fdi_m_n, false);
>  
>   ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
>   if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
> @@ -6315,9 +6315,10 @@ static int intel_crtc_compute_config(struct intel_crtc 
> *crtc,
>  }
>  
>  static void compute_m_n(unsigned int m, unsigned int n,
> - uint32_t *ret_m, uint32_t *ret_n)
> + uint32_t *ret_m, uint32_t *ret_n,
> + uint32_t max_link_n)
>  {
> - *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
> + *ret_n = min_t(unsigned int, roundup_pow_of_two(n), max_link_n);
>   *ret_m = div_u64((uint64_t) m * *ret_n, n);
>   intel_reduce_m_n_ratio(ret_m, ret_n);
>  }
> @@ -6325,16 +6326,23 @@ static void compute_m_n(unsigned int m, unsigned int 
> n,
>  void
>  intel_link_compute_m_n(int bits_per_pixel, int nlanes,
>  int pixel_clock, int link_clock,
> -struct intel_link_m_n *m_n)
> +struct intel_link_m_n *m_n,
> +bool reduced_n)
>  {
> + uint32_t max_link_n = DATA_LINK_N_MAX;
>   m_n->tu = 64;
>  
> + if ((reduced_n) && (nlanes == 1) && (link_clock >= 54))
> + max_link_n = DATA_LINK_REDUCED_N_MAX;
> +
>   compute_m_n(bits_per_pixel * pixel_clock,
>   link_clock * nlanes * 8,
> - _n->gmch_m, _n->gmch_n);
> + _n->gmch_m, _n->gmch_n,
> + max_link_n);
>  
>   compute_m_n(pixel_clock, link_clock,
> - _n->link_m, _n->link_n);
> + _n->link_m, _n->link_n,
> + max_link_n);
>  }
>  
>  static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index fd96a6c..9c96f5f 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1624,6 +1624,8 @@ static int intel_dp_compute_bpp(struct intel_dp 
> *intel_dp,
>   

[Intel-gfx] [PATCH] drm/i915: Enhanced disable access to stolen memory as a guest

[Xiong Zhang]

commit "04a68a3 drm/i915/gvt: Disable access to stolen memory as a guest"
isn't enough in GVT-d which will pass through IGD to guest and don't run
vgt code. While intel_vgpu_active() is true only when vgt code run on
host and guest in GVT-g.

Signed-off-by: Xiong Zhang 
---
 drivers/gpu/drm/i915/i915_drv.c| 1 +
 drivers/gpu/drm/i915/i915_drv.h| 1 +
 drivers/gpu/drm/i915/i915_gem_stolen.c | 4 ++--
 3 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 03d9e45..8b807a9 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -223,6 +223,7 @@ static void intel_detect_pch(struct drm_i915_private 
*dev_priv)
PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
pch->subsystem_device ==
PCI_SUBDEVICE_ID_QEMU)) {
+   dev_priv->run_on_qemu = true;
dev_priv->pch_type =
intel_virt_detect_pch(dev_priv);
} else
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a5947a4..ad95c87 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2145,6 +2145,7 @@ struct drm_i915_private {
struct intel_uncore uncore;
 
struct i915_virtual_gpu vgpu;
+   bool run_on_qemu;
 
struct intel_gvt *gvt;
 
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c 
b/drivers/gpu/drm/i915/i915_gem_stolen.c
index f3abdc2..07e1721 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -409,8 +409,8 @@ int i915_gem_init_stolen(struct drm_i915_private *dev_priv)
 
mutex_init(_priv->mm.stolen_lock);
 
-   if (intel_vgpu_active(dev_priv)) {
-   DRM_INFO("iGVT-g active, disabling use of stolen memory\n");
+   if (dev_priv->run_on_qemu) {
+   DRM_INFO("Run on qemu, disabling use of stolen memory\n");
return 0;
}
 
-- 
1.9.1

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Re: [Intel-gfx] [PATCH 02/19] drm: Add acquire ctx parameter to ->update_plane

[Daniel Vetter]

On Wed, Mar 22, 2017 at 11:03:41PM +, Russell King - ARM Linux wrote:
> On Wed, Mar 22, 2017 at 10:50:41PM +0100, Daniel Vetter wrote:
> > diff --git a/drivers/gpu/drm/armada/armada_overlay.c 
> > b/drivers/gpu/drm/armada/armada_overlay.c
> > index 34cb73d0db77..b54fd8cbd3a6 100644
> > --- a/drivers/gpu/drm/armada/armada_overlay.c
> > +++ b/drivers/gpu/drm/armada/armada_overlay.c
> > @@ -94,7 +94,8 @@ static int
> >  armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
> > struct drm_framebuffer *fb,
> > int crtc_x, int crtc_y, unsigned crtc_w, unsigned crtc_h,
> > -   uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h)
> > +   uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h,
> > +   struct drm_modeset_acquire_ctx *ctx)
> 
> I'm rather unhappy that we're ending up with a function taking soo many
> arguments.
> 
> Most of these have to be stacked on ARM, and I'm guessing most
> architectures end up doing something similar.  Is there a reason why we
> don't pass pointers to drm_rect's or maybe even consider passing the
> drm_plane_state structure in?
> 
> I've found that, when cleaning up these code paths in armada, that
> storing all the parameters into a drm_plane_state and then validating
> it with drm_plane_helper_check_state() is by way the simplest solution,
> and of course, it's forward-compatible with atomic modeset.

Yeah, we could do that, there's not many plane_update implementations
left. But it wouldn't help for this case here, because acquire context is
in drm_atomic_state, not in the individual per-object state structs.

There's no reason this isn't the case except organically grown and no one
bothered to improve it. I'll be happy to review such patches, but probably
won't ever get around to typing them.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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