Re: [Intel-gfx] [PULL] drm-intel-fixes

[Dave Airlie]

On 20 September 2017 at 15:43, Dave Airlie  wrote:
> On 20 September 2017 at 09:03, Rodrigo Vivi  wrote:
>> Hi Dave,
>
> Hi Rodrigo,
>
> This pull request is generated wrongly, it contains some commits from
> drm-next in it.

Sorry contains some commits from drm-fixes in it.
>
> Please regenerate it, I'm assuming you generated against 4.14-rc1 and
> not against drm-next.

not against drm-fixes :-)

Dave.
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Re: [Intel-gfx] [PULL] drm-intel-fixes

[Dave Airlie]

On 20 September 2017 at 09:03, Rodrigo Vivi  wrote:
> Hi Dave,

Hi Rodrigo,

This pull request is generated wrongly, it contains some commits from
drm-next in it.

Please regenerate it, I'm assuming you generated against 4.14-rc1 and
not against drm-next.

Dave.
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[Intel-gfx] ✗ Fi.CI.IGT: failure for tests/psr: Don't strcmp CRCs that are not NULL terminated. (rev2)

[Patchwork]

== Series Details ==

Series: tests/psr: Don't strcmp CRCs that are not NULL terminated. (rev2)
URL   : https://patchwork.freedesktop.org/series/30564/
State : failure

== Summary ==

Test gem_eio:
Subgroup in-flight-external:
dmesg-warn -> PASS   (shard-hsw)
Subgroup in-flight-contexts:
dmesg-warn -> PASS   (shard-hsw)
Test kms_setmode:
Subgroup basic:
fail   -> PASS   (shard-hsw) fdo#99912
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-primscrn-shrfb-pgflip-blt:
pass   -> FAIL   (shard-hsw)
Test kms_busy:
Subgroup extended-modeset-hang-newfb-with-reset-render-C:
pass   -> DMESG-WARN (shard-hsw) fdo#102249

fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102249 https://bugs.freedesktop.org/show_bug.cgi?id=102249

shard-hswtotal:2271 pass:1217 dwarn:2   dfail:0   fail:14  skip:1038 
time:9615s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_231/shards.html
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Re: [Intel-gfx] [igt] igt/kms_psr_sink_crc: Add psr_drrs subtest

[Vivi, Rodrigo]

> On Sep 19, 2017, at 6:26 PM, Pandiyan, Dhinakaran 
>  wrote:
> 
> 
>> On Fri, 2017-09-15 at 17:00 -0700, Radhakrishna Sripada wrote:
>> Platforms do not support psr and drrs simultaneously.
>> Adding a subtest to make the check.
>> 
>> Cc: Rodrigo Vivi 
>> Cc: Daniel Vetter 
>> Signed-off-by: Radhakrishna Sripada 
>> ---
>> tests/kms_psr_sink_crc.c | 14 ++
>> 1 file changed, 14 insertions(+)
>> 
>> diff --git a/tests/kms_psr_sink_crc.c b/tests/kms_psr_sink_crc.c
>> index bd3fa5e94d85..1c25f2c81a34 100644
>> --- a/tests/kms_psr_sink_crc.c
>> +++ b/tests/kms_psr_sink_crc.c
>> @@ -284,6 +284,15 @@ static void assert_or_manual(bool condition, const char 
>> *expected)
>>igt_assert(igt_interactive_debug || condition);
>> }
>> 
>> +static bool drrs_disabled(data_t *data)
>> +{
>> +char buf[512];
>> +
>> +igt_debugfs_read(data->drm_fd, "i915_drrs_status", buf);
>> +
>> +return strstr(buf, "DRRS Support: No\n");
>^ 
> This is causing the PSR sink crc test to fail. The string I see in the
> kernel is. 
> 
>seq_puts(m, "\tDRRS Supported : No");
> 
> Also, how does this work when there is more than one enabled crtc? For
> e.g., my machine has 
> 
> cat /sys/kernel/debug/dri/0/i915_drrs_status
> 
> CRTC 1:  eDP-1:
>VBT: DRRS_type: Static
> 
>DRRS Supported : No
> 
> CRTC 2:  DP-4:
>VBT: DRRS_type: Static
> 
>DRRS Supported : No
> 
> If the eDP supported DRRS( and PSR was enabled) and the external display
> did not, won't this result in a false positive?

Yes... we need a quick fix on test case or to revert the test case while it 
cannot handle proper parse for edp's drrs...

> 
> 
>> +}
>> +
>> static void run_test(data_t *data)
>> {
>>uint32_t handle = data->fb_white.gem_handle;
>> @@ -524,6 +533,11 @@ int main(int argc, char *argv[])
>>igt_assert(wait_psr_entry());
>>}
>> 
>> +igt_subtest("psr_drrs") {
>> +setup_test_plane();
>> +igt_assert(drrs_disabled());
>> +}
>> +
>>for (op = PAGE_FLIP; op <= RENDER; op++) {
>>igt_subtest_f("primary_%s", op_str(op)) {
>>data.test_plane = DRM_PLANE_TYPE_PRIMARY;
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Re: [Intel-gfx] [PATCH][drm-next] drm/i915/gvt: ensure -ve return value is handled correctly

[Joe Perches]

On Wed, 2017-09-20 at 05:46 +0800, Zhenyu Wang wrote:
> On 2017.09.19 16:55:34 +0100, Colin King wrote:
> > From: Colin Ian King 
> > 
> > An earlier fix changed the return type from find_bb_size however the
> > integer return is being assigned to a unsigned int so the -ve error
> > check will never be detected. Make bb_size an int to fix this.
> > 
> > Detected by CoverityScan CID#1456886 ("Unsigned compared against 0")
> > 
> > Fixes: 1e3197d6ad73 ("drm/i915/gvt: Refine error handling for 
> > perform_bb_shadow")
> > Signed-off-by: Colin Ian King 
> > ---
> >  drivers/gpu/drm/i915/gvt/cmd_parser.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c 
> > b/drivers/gpu/drm/i915/gvt/cmd_parser.c
> > index 2c0ccbb817dc..f41cbf664b69 100644
> > --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
> > +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
> > @@ -1628,7 +1628,7 @@ static int perform_bb_shadow(struct parser_exec_state 
> > *s)
> > struct intel_shadow_bb_entry *entry_obj;
> > struct intel_vgpu *vgpu = s->vgpu;
> > unsigned long gma = 0;
> > -   uint32_t bb_size;
> > +   int bb_size;
> > void *dst = NULL;
> > int ret = 0;
> >  
> 
> Applied this, thanks!

Is it possible for bb_size to be both >= 2g and valid?

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[Intel-gfx] ✗ Fi.CI.IGT: failure for tools_test: Clean up and fix sysfs_l3_parity

[Patchwork]

== Series Details ==

Series: tools_test: Clean up and fix sysfs_l3_parity
URL   : https://patchwork.freedesktop.org/series/30583/
State : failure

== Summary ==

Test drv_hangman:
Subgroup error-state-capture-render:
pass   -> SKIP   (shard-hsw)
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-mmap-wc:
pass   -> FAIL   (shard-hsw)
Subgroup fbc-1p-offscren-pri-shrfb-draw-blt:
pass   -> FAIL   (shard-hsw)
Test kms_setmode:
Subgroup basic:
pass   -> FAIL   (shard-hsw) fdo#99912
Test perf:
Subgroup polling:
fail   -> PASS   (shard-hsw) fdo#102252
Test kms_flip:
Subgroup rcs-wf_vblank-vs-dpms:
dmesg-warn -> PASS   (shard-hsw)

fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-hswtotal:2317 pass:1242 dwarn:3   dfail:0   fail:14  skip:1058 
time:10548s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_229/shards.html
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Re: [Intel-gfx] [PATCH v4 1/3] drm/i915/gvt: Add gvt_debug in i915_params for GVT-g log classification

[Shuo Liu]

On Wed 20.Sep'17 at  4:45:31 +0800, Zhenyu Wang wrote:

On 2017.09.19 18:17:04 +0800, Shuo Liu wrote:

On Tue 19.Sep'17 at 10:22:16 +0100, Chris Wilson wrote:
> Quoting Shuo Liu (2017-09-19 08:54:43)
> > Signed-off-by: Shuo Liu 
> > ---
> >  drivers/gpu/drm/i915/i915_params.c | 13 +
> >  drivers/gpu/drm/i915/i915_params.h |  1 +
> >  2 files changed, 14 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
> > index 8ab003d..ceeae1d 100644
> > --- a/drivers/gpu/drm/i915/i915_params.c
> > +++ b/drivers/gpu/drm/i915/i915_params.c
> > @@ -65,6 +65,7 @@ struct i915_params i915 __read_mostly = {
> > .inject_load_failure = 0,
> > .enable_dpcd_backlight = false,
> > .enable_gvt = false,
> > +   .debug_gvt = 0,
> >  };
> >
> >  module_param_named(modeset, i915.modeset, int, 0400);
> > @@ -257,3 +258,15 @@ struct i915_params i915 __read_mostly = {
> >  module_param_named(enable_gvt, i915.enable_gvt, bool, 0400);
> >  MODULE_PARM_DESC(enable_gvt,
> > "Enable support for Intel GVT-g graphics virtualization host 
support(default:false)");
> > +
> > +module_param_named(debug_gvt, i915.debug_gvt, int, 0600);
> > +MODULE_PARM_DESC(debug_gvt, "Enable GVT-g debug output, where each bit enables 
a category.\n"
> > +   "Bit 0 (0x01) will enable CORE messages (GVT-g core 
message)\n"
> > +   "Bit 1 (0x02) will enable IRQ messages (GVT-g interrupt 
message)\n"
> > +   "Bit 2 (0x04) will enable MM messages (GVT-g memory 
management message)\n"
> > +   "Bit 3 (0x08) will enable MMIO messages (GVT-g MMIO 
message)\n"
> > +   "Bit 4 (0x10) will enable DPY messages (GVT-g display 
message)\n"
> > +   "Bit 5 (0x20) will enable EL messages (GVT-g execlist 
message)\n"
> > +   "Bit 6 (0x40) will enable SCHED messages (GVT-g schedule 
message)\n"
> > +   "Bit 7 (0x80) will enable RENDER messages (GVT-g render 
message)\n"
> > +   "Bit 8 (0x100) will enable CMD messages (GVT-g command 
message)");
> > diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
> > index ac84470..cd29c78 100644
> > --- a/drivers/gpu/drm/i915/i915_params.h
> > +++ b/drivers/gpu/drm/i915/i915_params.h
> > @@ -54,6 +54,7 @@
> > func(int, edp_vswing); \
> > func(int, reset); \
> > func(unsigned int, inject_load_failure); \
> > +   func(int, debug_gvt); \
> > /* leave bools at the end to not create holes */ \
> > func(bool, alpha_support); \
> > func(bool, enable_cmd_parser); \
>
> Note that you are not forced to use i915_params. If you have gvt only
> module options that you don't want exposed outside of gvt, just create
> them within gvt.
Have talked this with Zhenyu, his suggestion is put params together as
gvt is in i915 module.


As gvt is in i915 module now, so I think better to put all the params
in one place instead of any surprise.


>
> Having said that, I would strongly advise against having module options,
> and I would advise you to go the dyndebug route instead of copying a
> rectangular wheel.
Thanks Chris. dyndebug might be an option. The disadvantage of dyndebug
is complicated to use, expecially in bootup debugging (add a long
cmdline to enable interesting messages). Module option is
straightforward. Zhenyu, any comments on this?



yeah, I think moving to dyndebug is better than module option and boot debug
shouldn't be that hard right? as we're mostly with file seperation for different
function unit.


OK. I will try to move to dyndebug approach.

Thanks
Shuo
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[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915/cnp: Display Wa #1179: WaHardHangonHotPlug

[Patchwork]

== Series Details ==

Series: drm/i915/cnp: Display Wa #1179: WaHardHangonHotPlug
URL   : https://patchwork.freedesktop.org/series/30626/
State : warning

== Summary ==

Test kms_flip:
Subgroup rcs-wf_vblank-vs-dpms:
dmesg-warn -> PASS   (shard-hsw)
Test perf:
Subgroup polling:
fail   -> PASS   (shard-hsw) fdo#102252 +1
Test kms_atomic:
Subgroup plane_primary_legacy:
pass   -> SKIP   (shard-hsw)

fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-hswtotal:2317 pass:1244 dwarn:3   dfail:0   fail:12  skip:1058 
time:9504s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5759/shards.html
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Re: [Intel-gfx] [igt] igt/kms_psr_sink_crc: Add psr_drrs subtest

[Pandiyan, Dhinakaran]

On Fri, 2017-09-15 at 17:00 -0700, Radhakrishna Sripada wrote:
> Platforms do not support psr and drrs simultaneously.
> Adding a subtest to make the check.
> 
> Cc: Rodrigo Vivi 
> Cc: Daniel Vetter 
> Signed-off-by: Radhakrishna Sripada 
> ---
>  tests/kms_psr_sink_crc.c | 14 ++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/tests/kms_psr_sink_crc.c b/tests/kms_psr_sink_crc.c
> index bd3fa5e94d85..1c25f2c81a34 100644
> --- a/tests/kms_psr_sink_crc.c
> +++ b/tests/kms_psr_sink_crc.c
> @@ -284,6 +284,15 @@ static void assert_or_manual(bool condition, const char 
> *expected)
>   igt_assert(igt_interactive_debug || condition);
>  }
>  
> +static bool drrs_disabled(data_t *data)
> +{
> + char buf[512];
> +
> + igt_debugfs_read(data->drm_fd, "i915_drrs_status", buf);
> +
> + return strstr(buf, "DRRS Support: No\n");
^ 
This is causing the PSR sink crc test to fail. The string I see in the
kernel is. 

seq_puts(m, "\tDRRS Supported : No");

Also, how does this work when there is more than one enabled crtc? For
e.g., my machine has 

 cat /sys/kernel/debug/dri/0/i915_drrs_status

CRTC 1:  eDP-1:
VBT: DRRS_type: Static

DRRS Supported : No

CRTC 2:  DP-4:
VBT: DRRS_type: Static

DRRS Supported : No

If the eDP supported DRRS( and PSR was enabled) and the external display
did not, won't this result in a false positive?


> +}
> +
>  static void run_test(data_t *data)
>  {
>   uint32_t handle = data->fb_white.gem_handle;
> @@ -524,6 +533,11 @@ int main(int argc, char *argv[])
>   igt_assert(wait_psr_entry());
>   }
>  
> + igt_subtest("psr_drrs") {
> + setup_test_plane();
> + igt_assert(drrs_disabled());
> + }
> +
>   for (op = PAGE_FLIP; op <= RENDER; op++) {
>   igt_subtest_f("primary_%s", op_str(op)) {
>   data.test_plane = DRM_PLANE_TYPE_PRIMARY;
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Skylake plane update/disable unifications [v5]

[Patchwork]

== Series Details ==

Series: drm/i915: Skylake plane update/disable unifications [v5]
URL   : https://patchwork.freedesktop.org/series/30622/
State : success

== Summary ==

Test perf:
Subgroup blocking:
pass   -> FAIL   (shard-hsw) fdo#102252
Test kms_flip:
Subgroup rcs-wf_vblank-vs-dpms:
dmesg-warn -> PASS   (shard-hsw)
Subgroup wf_vblank-ts-check-interruptible:
pass   -> FAIL   (shard-hsw) fdo#100368

fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368

shard-hswtotal:2317 pass:1243 dwarn:3   dfail:0   fail:14  skip:1057 
time:9560s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5756/shards.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for tests/psr: Don't strcmp CRCs that are not NULL terminated. (rev2)

[Patchwork]

== Series Details ==

Series: tests/psr: Don't strcmp CRCs that are not NULL terminated. (rev2)
URL   : https://patchwork.freedesktop.org/series/30564/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
da197b5f3cb516aaaea72d0d60b0f5c1c81081dd igt/gem_eio: Add another variant of 
in-flight to avoid request coalescing

with latest DRM-Tip kernel build CI_DRM_3111
85e28edde5bf drm-tip: 2017y-09m-19d-23h-07m-57s UTC integration manifest

Test chamelium:
Subgroup hdmi-hpd-fast:
fail   -> SKIP   (fi-kbl-7500u)
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-legacy:
fail   -> PASS   (fi-snb-2600) fdo#100215
Test drv_module_reload:
Subgroup basic-reload:
dmesg-warn -> PASS   (fi-glk-1) fdo#102777

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#102777 https://bugs.freedesktop.org/show_bug.cgi?id=102777

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:438s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:473s
fi-blb-e6850 total:289  pass:224  dwarn:1   dfail:0   fail:0   skip:64  
time:422s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:519s
fi-bwr-2160  total:289  pass:184  dwarn:0   dfail:0   fail:0   skip:105 
time:277s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:514s
fi-byt-j1900 total:289  pass:254  dwarn:1   dfail:0   fail:0   skip:34  
time:504s
fi-byt-n2820 total:289  pass:250  dwarn:1   dfail:0   fail:0   skip:38  
time:497s
fi-cfl-s total:289  pass:223  dwarn:34  dfail:0   fail:0   skip:32  
time:550s
fi-elk-e7500 total:289  pass:230  dwarn:0   dfail:0   fail:0   skip:59  
time:414s
fi-glk-1 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:565s
fi-hsw-4770  total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:435s
fi-hsw-4770r total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:408s
fi-ilk-650   total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:433s
fi-ivb-3520m total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:486s
fi-ivb-3770  total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:469s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:472s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:575s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:591s
fi-pnv-d510  total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:545s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:454s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:752s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:493s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:480s
fi-snb-2520m total:289  pass:251  dwarn:0   dfail:0   fail:0   skip:38  
time:571s
fi-snb-2600  total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:423s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_231/
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[Intel-gfx] ✗ Fi.CI.BAT: failure for igt/kms_rotation_crc : Remove flip tests for sprite plane

[Patchwork]

== Series Details ==

Series: igt/kms_rotation_crc : Remove flip tests for sprite plane
URL   : https://patchwork.freedesktop.org/series/30588/
State : failure

== Summary ==

IGT patchset tested on top of latest successful build
da197b5f3cb516aaaea72d0d60b0f5c1c81081dd igt/gem_eio: Add another variant of 
in-flight to avoid request coalescing

with latest DRM-Tip kernel build CI_DRM_3111
85e28edde5bf drm-tip: 2017y-09m-19d-23h-07m-57s UTC integration manifest

Test chamelium:
Subgroup dp-edid-read:
pass   -> FAIL   (fi-kbl-7500u) fdo#102672
Subgroup hdmi-hpd-fast:
fail   -> SKIP   (fi-kbl-7500u)
Test gem_mmap_gtt:
Subgroup basic-wc:
pass   -> DMESG-WARN (fi-kbl-7500u)
Subgroup basic-write-read:
pass   -> DMESG-WARN (fi-kbl-7500u)
Test gem_pwrite:
Subgroup basic:
pass   -> DMESG-WARN (fi-kbl-7500u)
Test kms_addfb_basic:
Subgroup bad-pitch-0:
pass   -> DMESG-WARN (fi-kbl-7500u)
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-legacy:
fail   -> PASS   (fi-snb-2600) fdo#100215
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass   -> INCOMPLETE (fi-kbl-7500u)
Test drv_module_reload:
Subgroup basic-reload:
dmesg-warn -> PASS   (fi-glk-1) fdo#102777 +1

fdo#102672 https://bugs.freedesktop.org/show_bug.cgi?id=102672
fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#102777 https://bugs.freedesktop.org/show_bug.cgi?id=102777

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:450s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:468s
fi-blb-e6850 total:289  pass:224  dwarn:1   dfail:0   fail:0   skip:64  
time:420s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:527s
fi-bwr-2160  total:289  pass:184  dwarn:0   dfail:0   fail:0   skip:105 
time:276s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:509s
fi-byt-j1900 total:289  pass:254  dwarn:1   dfail:0   fail:0   skip:34  
time:508s
fi-byt-n2820 total:289  pass:250  dwarn:1   dfail:0   fail:0   skip:38  
time:500s
fi-cfl-s total:289  pass:223  dwarn:34  dfail:0   fail:0   skip:32  
time:547s
fi-elk-e7500 total:289  pass:230  dwarn:0   dfail:0   fail:0   skip:59  
time:419s
fi-glk-1 total:289  pass:259  dwarn:1   dfail:0   fail:0   skip:29  
time:571s
fi-hsw-4770  total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:427s
fi-hsw-4770r total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:406s
fi-ilk-650   total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:432s
fi-ivb-3520m total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:484s
fi-ivb-3770  total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:464s
fi-kbl-7500u total:245  pass:218  dwarn:5   dfail:0   fail:1   skip:20 
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:579s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:589s
fi-pnv-d510  total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:543s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:452s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:754s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:492s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:472s
fi-snb-2520m total:289  pass:251  dwarn:0   dfail:0   fail:0   skip:38  
time:576s
fi-snb-2600  total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:415s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_230/
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[Intel-gfx] ✗ Fi.CI.IGT: warning for GuC code restructuring and fixes (rev3)

[Patchwork]

== Series Details ==

Series: GuC code restructuring and fixes (rev3)
URL   : https://patchwork.freedesktop.org/series/30351/
State : warning

== Summary ==

Test perf:
Subgroup blocking:
pass   -> FAIL   (shard-hsw) fdo#102252 +1
Test kms_flip:
Subgroup rcs-wf_vblank-vs-dpms:
dmesg-warn -> PASS   (shard-hsw)
Test kms_atomic:
Subgroup plane_primary_legacy:
pass   -> SKIP   (shard-hsw)

fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-hswtotal:2317 pass:1244 dwarn:3   dfail:0   fail:12  skip:1058 
time:9654s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5753/shards.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for tools_test: Clean up and fix sysfs_l3_parity

[Patchwork]

== Series Details ==

Series: tools_test: Clean up and fix sysfs_l3_parity
URL   : https://patchwork.freedesktop.org/series/30583/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
da197b5f3cb516aaaea72d0d60b0f5c1c81081dd igt/gem_eio: Add another variant of 
in-flight to avoid request coalescing

with latest DRM-Tip kernel build CI_DRM_3110
bf6ecf6d25c1 drm-tip: 2017y-09m-19d-17h-23m-04s UTC integration manifest

Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
pass   -> FAIL   (fi-snb-2600) fdo#100215 +1
Test kms_frontbuffer_tracking:
Subgroup basic:
dmesg-warn -> PASS   (fi-kbl-7500u)
Test kms_pipe_crc_basic:
Subgroup hang-read-crc-pipe-b:
incomplete -> DMESG-WARN (fi-cfl-s) fdo#102294
Subgroup suspend-read-crc-pipe-a:
incomplete -> PASS   (fi-kbl-7500u)

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#102294 https://bugs.freedesktop.org/show_bug.cgi?id=102294

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:451s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:472s
fi-blb-e6850 total:289  pass:224  dwarn:1   dfail:0   fail:0   skip:64  
time:423s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:524s
fi-bwr-2160  total:289  pass:184  dwarn:0   dfail:0   fail:0   skip:105 
time:278s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:508s
fi-byt-j1900 total:289  pass:254  dwarn:1   dfail:0   fail:0   skip:34  
time:500s
fi-byt-n2820 total:289  pass:250  dwarn:1   dfail:0   fail:0   skip:38  
time:491s
fi-cfl-s total:289  pass:222  dwarn:35  dfail:0   fail:0   skip:32  
time:548s
fi-elk-e7500 total:289  pass:230  dwarn:0   dfail:0   fail:0   skip:59  
time:424s
fi-glk-1 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:574s
fi-hsw-4770  total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:431s
fi-hsw-4770r total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:406s
fi-ilk-650   total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:437s
fi-ivb-3520m total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:483s
fi-ivb-3770  total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:474s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:474s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:582s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:590s
fi-pnv-d510  total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:542s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:458s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:761s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:497s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:486s
fi-snb-2520m total:289  pass:251  dwarn:0   dfail:0   fail:0   skip:38  
time:571s
fi-snb-2600  total:289  pass:248  dwarn:0   dfail:0   fail:2   skip:39  
time:420s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_229/
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gvt: ensure -ve return value is handled correctly

[Patchwork]

== Series Details ==

Series: drm/i915/gvt: ensure -ve return value is handled correctly
URL   : https://patchwork.freedesktop.org/series/30604/
State : success

== Summary ==

Test perf:
Subgroup polling:
fail   -> PASS   (shard-hsw) fdo#102252 +1
Test kms_flip:
Subgroup rcs-wf_vblank-vs-dpms:
dmesg-warn -> PASS   (shard-hsw)

fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-hswtotal:2317 pass:1245 dwarn:3   dfail:0   fail:12  skip:1057 
time:9651s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5752/shards.html
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Re: [Intel-gfx] [igt] igt/kms_psr_sink_crc: Add psr_drrs subtest

[Rodrigo Vivi]

On Tue, Sep 19, 2017 at 09:41:36AM +, Petri Latvala wrote:
> On Mon, Sep 18, 2017 at 12:51:07PM -0700, Rodrigo Vivi wrote:
> > > Reviewed-by: Rodrigo Vivi 
> > 
> > merged to master. thanks for the patch,.
> 
> 
> Obligatory scolding: You forgot to add your R-b to the commit message.

Duh! o>

I get I got used to dim tool and patchwork adding that for me...
I assume that I also forgot to sign-off...

Sorry about that...

> 
> 
> -- 
> Petri Latvala
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Re: [Intel-gfx] [PATCH] drm/i915/cfl: Remove alpha support protection.

[Rodrigo Vivi]

On Fri, Sep 08, 2017 at 01:45:59AM +, Pandiyan, Dhinakaran wrote:
> On Thu, 2017-09-07 at 16:06 -0700, Rodrigo Vivi wrote:
> > We now have Coffee Lake on our CI systems.
> > 
> > Coffee Lake is at this point in same stage as Kaby Lake.
> > 
> > And it seems that we don't have any risk of bad blank
> > screens or anything like that. So let's remove the protection.
> > 
> 
> Reviewed-by: Dhinakaran Pandiyan 

merged to dinq. thanks for the review.

> 
> > Cc: Daniel Vetter 
> > Cc: Dhinakaran Pandiyan 
> > Signed-off-by: Rodrigo Vivi 
> > ---
> >  drivers/gpu/drm/i915/i915_pci.c | 1 -
> >  1 file changed, 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_pci.c 
> > b/drivers/gpu/drm/i915/i915_pci.c
> > index 129877b94c20..93c6e899929b 100644
> > --- a/drivers/gpu/drm/i915/i915_pci.c
> > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > @@ -526,7 +526,6 @@ static const struct intel_device_info 
> > intel_kabylake_gt3_info __initconst = {
> >  };
> >  
> >  #define CFL_PLATFORM \
> > -   .is_alpha_support = 1, \
> > BDW_FEATURES, \
> > .gen = 9, \
> > .platform = INTEL_COFFEELAKE, \
> ___
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Re: [Intel-gfx] [PATCH] drm/i915/cnp: Display Wa #1179: WaHardHangonHotPlug

[Rodrigo Vivi]

On Tue, Sep 19, 2017 at 09:57:03PM +, Rodrigo Vivi wrote:
> "CNL PCH chance of hang when software accesses south display
> registers after hotplug is enabled.
> Workaround: Program 0xC2000 bits 11:8 = 0xF before enabling
> south display hotplug detection."
> 
> "Workaround only needs to be applied to pre-production steppings
> used in graphics capable SKUs, but it is easier to apply to
> everything, and does not hurt."
> 
> v2: Moving from clock gating to right before enabling
> SHOTPLUG_CTL as it should be.
> v3: Align with SOUTH_CHICKEN1 (DK) and consequently use proper
> spaces on bits definition since other bits around already use
> new style. And now that checkpatch is not noise anymore I also
> fixed the reg read mask to avoid going over 80 chars.
> 
> Suggested-by: Ben Widawsky 
> Cc: Ben Widawsky 
> Cc: Dhinakaran Pandiyan 
> Signed-off-by: Rodrigo Vivi 
> Reviewed-by: Dhinakaran Pandiyan 

merged to dinq. thanks for the review

> ---
>  drivers/gpu/drm/i915/i915_irq.c | 10 +-
>  drivers/gpu/drm/i915/i915_reg.h |  2 ++
>  2 files changed, 11 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 4d0e8f76ed1a..c23efc4394ce 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3218,7 +3218,15 @@ static void ibx_hpd_irq_setup(struct drm_i915_private 
> *dev_priv)
>  
>  static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
>  {
> - u32 hotplug;
> + u32 val, hotplug;
> +
> + /* Display WA #1179 WaHardHangonHotPlug: cnp */
> + if (HAS_PCH_CNP(dev_priv)) {
> + val = I915_READ(SOUTH_CHICKEN1);
> + val &= ~CHASSIS_CLK_REQ_DURATION_MASK;
> + val |= CHASSIS_CLK_REQ_DURATION(0xf);
> + I915_WRITE(SOUTH_CHICKEN1, val);
> + }
>  
>   /* Enable digital hotplug on the PCH */
>   hotplug = I915_READ(PCH_PORT_HOTPLUG);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 94b40a469afd..82f36dd0cd94 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7471,6 +7471,8 @@ enum {
>  #define  FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 
> 2)))
>  #define  FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 
> 2)))
>  #define  FDI_BC_BIFURCATION_SELECT   (1 << 12)
> +#define  CHASSIS_CLK_REQ_DURATION_MASK   (0xf << 8)
> +#define  CHASSIS_CLK_REQ_DURATION(x) ((x) << 8)
>  #define  SPT_PWM_GRANULARITY (1<<0)
>  #define SOUTH_CHICKEN2   _MMIO(0xc2004)
>  #define  FDI_MPHY_IOSFSB_RESET_STATUS(1<<13)
> -- 
> 2.13.5
> 
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[Intel-gfx] ✗ Fi.CI.BAT: failure for tests/kms_cursor_legacy: Do not start collecting CRC after making FB busy

[Patchwork]

== Series Details ==

Series: tests/kms_cursor_legacy: Do not start collecting CRC after making FB 
busy
URL   : https://patchwork.freedesktop.org/series/30582/
State : failure

== Summary ==

IGT patchset tested on top of latest successful build
da197b5f3cb516aaaea72d0d60b0f5c1c81081dd igt/gem_eio: Add another variant of 
in-flight to avoid request coalescing

with latest DRM-Tip kernel build CI_DRM_3110
bf6ecf6d25c1 drm-tip: 2017y-09m-19d-17h-23m-04s UTC integration manifest

Test chamelium:
Subgroup dp-crc-fast:
pass   -> FAIL   (fi-kbl-7500u) fdo#102514
Test gem_exec_suspend:
Subgroup basic-s3:
pass   -> INCOMPLETE (fi-cfl-s)
Test kms_frontbuffer_tracking:
Subgroup basic:
dmesg-warn -> PASS   (fi-kbl-7500u)
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
incomplete -> PASS   (fi-kbl-7500u)

fdo#102514 https://bugs.freedesktop.org/show_bug.cgi?id=102514

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:445s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:470s
fi-blb-e6850 total:289  pass:224  dwarn:1   dfail:0   fail:0   skip:64  
time:419s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:524s
fi-bwr-2160  total:289  pass:184  dwarn:0   dfail:0   fail:0   skip:105 
time:278s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:516s
fi-byt-j1900 total:289  pass:254  dwarn:1   dfail:0   fail:0   skip:34  
time:505s
fi-byt-n2820 total:289  pass:250  dwarn:1   dfail:0   fail:0   skip:38  
time:503s
fi-cfl-s total:118  pass:97   dwarn:0   dfail:0   fail:0   skip:20 
fi-elk-e7500 total:289  pass:230  dwarn:0   dfail:0   fail:0   skip:59  
time:427s
fi-glk-1 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:567s
fi-hsw-4770  total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:425s
fi-hsw-4770r total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:408s
fi-ilk-650   total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:437s
fi-ivb-3520m total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:490s
fi-ivb-3770  total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:464s
fi-kbl-7500u total:289  pass:263  dwarn:1   dfail:0   fail:1   skip:24  
time:462s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:586s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:588s
fi-pnv-d510  total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:545s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:451s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:746s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:490s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:478s
fi-snb-2520m total:289  pass:251  dwarn:0   dfail:0   fail:0   skip:38  
time:568s
fi-snb-2600  total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:418s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_228/
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[Intel-gfx] [PULL] drm-intel-fixes

[Rodrigo Vivi]

Hi Dave,

Here are drm/i915 the fixes for 4.14-rc1.

Couple fixes for stable:

- Fix MIPI panels on BXT.
- Fix PCI BARs information on GVT.

Plus other fixes:

- Fix minimal brightness for BXT, GLK, CFL and CNL.
- Fix compilation warning: unused in_vbl
- Fix error handling in intel_framebuffer_init

Thanks,
Rodrigo.

The following changes since commit 2bd6bf03f4c1c59381d62c61d03f6cc3fe71f66e:

  Linux 4.14-rc1 (2017-09-16 15:47:51 -0700)

are available in the git repository at:

  git://anongit.freedesktop.org/git/drm-intel tags/drm-intel-fixes-2017-09-19

for you to fetch changes up to 99df13b6ea811a63eeacb278d05a5b914ce28073:

  drm/i915: Remove unused 'in_vbl' from i915_get_crtc_scanoutpos() (2017-09-18 
15:22:37 -0700)


drm/i915 fixes for 4.14-rc1

Couple fixes for stable:

- Fix MIPI panels on BXT.
- Fix PCI BARs information on GVT.

Plus other fixes:

- Fix minimal brightness for BXT, GLK, CFL and CNL.
- Fix compilation warning: unused in_vbl
- Fix error handling in intel_framebuffer_init


Changbin Du (1):
  drm/i915/gvt: Fix incorrect PCI BARs reporting

Chris Wilson (1):
  drm/i915: Remove unused 'in_vbl' from i915_get_crtc_scanoutpos()

Christophe JAILLET (1):
  drm/i915: Fix an error handling in 'intel_framebuffer_init()'

Dave Airlie (1):
  Merge tag 'drm-amdkfd-next-2017-09-02' of 
git://people.freedesktop.org/~gabbayo/linux into drm-fixes

Himanshu Jha (1):
  drm/amdkfd: remove memset before memcpy

Lee, Shawn C (2):
  drm/i915/bxt: set min brightness from VBT
  drm/i915/cnp: set min brightness from VBT

Mikko Rapeli (1):
  uapi linux/kfd_ioctl.h: only use __u32 and __u64

Oded Gabbay (1):
  drm/amdkfd: pass queue's mqd when destroying mqd

Uma Shankar (1):
  Revert "drm/i915/bxt: Disable device ready before shutdown command"

 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c  |   2 +-
 .../gpu/drm/amd/amdkfd/kfd_process_queue_manager.c |   1 -
 drivers/gpu/drm/i915/gvt/cfg_space.c   | 113 ++
 drivers/gpu/drm/i915/i915_irq.c|   3 -
 drivers/gpu/drm/i915/intel_display.c   |   2 +-
 drivers/gpu/drm/i915/intel_dsi.c   |  11 --
 drivers/gpu/drm/i915/intel_panel.c |   4 +
 include/uapi/linux/kfd_ioctl.h | 172 ++---
 8 files changed, 140 insertions(+), 168 deletions(-)
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[Intel-gfx] [PATCH i-g-t v2] tests/psr: Don't strcmp CRCs that are not NULL terminated.

[Dhinakaran Pandiyan]

Switched to strncmp.
v2: increased buffer size to account for NULL character.

Cc: Rodrigo Vivi 
Signed-off-by: Dhinakaran Pandiyan 
---
 tests/kms_psr_sink_crc.c | 13 +++--
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/tests/kms_psr_sink_crc.c b/tests/kms_psr_sink_crc.c
index 1c25f2c8..ff257698 100644
--- a/tests/kms_psr_sink_crc.c
+++ b/tests/kms_psr_sink_crc.c
@@ -34,6 +34,7 @@
 bool running_with_psr_disabled;
 
 #define CRC_BLACK ""
+#define CRC_LEN 12
 
 enum operations {
PAGE_FLIP,
@@ -243,7 +244,7 @@ static void get_sink_crc(data_t *data, char *crc) {
usleep(30);
 
/* Black screen is always invalid */
-   igt_assert(strcmp(crc, CRC_BLACK) != 0);
+   igt_assert(strncmp(crc, CRC_BLACK, CRC_LEN + 1) != 0);
 }
 
 static bool is_green(char *crc)
@@ -298,8 +299,8 @@ static void run_test(data_t *data)
uint32_t handle = data->fb_white.gem_handle;
igt_plane_t *test_plane;
void *ptr;
-   char ref_crc[12];
-   char crc[12];
+   char ref_crc[CRC_LEN + 1] = {0};
+   char crc[CRC_LEN + 1] = {0};
const char *expected = "";
 
/* Confirm that screen became Green */
@@ -356,9 +357,9 @@ static void run_test(data_t *data)
memset(ptr, 0xff, data->mod_size);
get_sink_crc(data, crc);
if (data->test_plane == DRM_PLANE_TYPE_PRIMARY)
-   assert_or_manual(strcmp(ref_crc, crc) == 0, "screen 
WHITE");
+   assert_or_manual(strncmp(ref_crc, crc, CRC_LEN + 1) == 
0, "screen WHITE");
else
-   assert_or_manual(strcmp(ref_crc, crc) == 0,
+   assert_or_manual(strncmp(ref_crc, crc, CRC_LEN + 1) == 
0,
   "GREEN background with WHITE box");
 
igt_info("Waiting 10s...\n");
@@ -401,7 +402,7 @@ static void run_test(data_t *data)
break;
}
get_sink_crc(data, crc);
-   assert_or_manual(strcmp(ref_crc, crc) != 0, expected);
+   assert_or_manual(strncmp(ref_crc, crc, CRC_LEN + 1) != 0, expected);
 }
 
 static void test_cleanup(data_t *data) {
-- 
2.11.0

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[Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [1/2] drm/i915/cnl: Add support slice/subslice/eu configs

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/cnl: Add support slice/subslice/eu 
configs
URL   : https://patchwork.freedesktop.org/series/30629/
State : warning

== Summary ==

Series 30629v1 series starting with [1/2] drm/i915/cnl: Add support 
slice/subslice/eu configs
https://patchwork.freedesktop.org/api/1.0/series/30629/revisions/1/mbox/

Test gem_exec_reloc:
Subgroup basic-write-read-noreloc:
pass   -> DMESG-WARN (fi-kbl-7500u)
Test gem_exec_store:
Subgroup basic-vebox:
pass   -> DMESG-WARN (fi-kbl-7500u)
Test gem_exec_suspend:
Subgroup basic-s3:
pass   -> INCOMPLETE (fi-kbl-7500u) fdo#102850
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-legacy:
pass   -> FAIL   (fi-snb-2600) fdo#100215
Test kms_pipe_crc_basic:
Subgroup hang-read-crc-pipe-b:
incomplete -> DMESG-WARN (fi-cfl-s) fdo#102294
Test drv_module_reload:
Subgroup basic-reload:
pass   -> DMESG-WARN (fi-glk-1) fdo#102777

fdo#102850 https://bugs.freedesktop.org/show_bug.cgi?id=102850
fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#102294 https://bugs.freedesktop.org/show_bug.cgi?id=102294
fdo#102777 https://bugs.freedesktop.org/show_bug.cgi?id=102777

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:444s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:463s
fi-blb-e6850 total:289  pass:224  dwarn:1   dfail:0   fail:0   skip:64  
time:418s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:509s
fi-bwr-2160  total:289  pass:184  dwarn:0   dfail:0   fail:0   skip:105 
time:278s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:498s
fi-byt-j1900 total:289  pass:254  dwarn:1   dfail:0   fail:0   skip:34  
time:489s
fi-byt-n2820 total:289  pass:250  dwarn:1   dfail:0   fail:0   skip:38  
time:501s
fi-cfl-s total:289  pass:222  dwarn:35  dfail:0   fail:0   skip:32  
time:548s
fi-elk-e7500 total:289  pass:230  dwarn:0   dfail:0   fail:0   skip:59  
time:413s
fi-glk-1 total:289  pass:259  dwarn:1   dfail:0   fail:0   skip:29  
time:563s
fi-hsw-4770  total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:423s
fi-hsw-4770r total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:408s
fi-ilk-650   total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:426s
fi-ivb-3520m total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:480s
fi-ivb-3770  total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:459s
fi-kbl-7500u total:118  pass:98   dwarn:3   dfail:0   fail:0   skip:16 
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:575s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:588s
fi-pnv-d510  total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:549s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:450s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:751s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:488s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:466s
fi-snb-2520m total:289  pass:251  dwarn:0   dfail:0   fail:0   skip:38  
time:564s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:1   skip:39  
time:417s

bf6ecf6d25c1c45e576643b7d7a65e8b1e6b4f01 drm-tip: 2017y-09m-19d-17h-23m-04s UTC 
integration manifest
9818047933cf drm/i915/cnl: Fix SSEU Device Status.
2927b87c3d3d drm/i915/cnl: Add support slice/subslice/eu configs

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5760/
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Stop engines before reset (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Stop engines before reset (rev2)
URL   : https://patchwork.freedesktop.org/series/30357/
State : success

== Summary ==

Test perf:
Subgroup blocking:
pass   -> FAIL   (shard-hsw) fdo#102252 +1
Test kms_flip:
Subgroup rcs-wf_vblank-vs-dpms:
dmesg-warn -> PASS   (shard-hsw)

fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-hswtotal:2317 pass:1245 dwarn:3   dfail:0   fail:12  skip:1057 
time:9589s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5749/shards.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/cnp: Display Wa #1179: WaHardHangonHotPlug

[Patchwork]

== Series Details ==

Series: drm/i915/cnp: Display Wa #1179: WaHardHangonHotPlug
URL   : https://patchwork.freedesktop.org/series/30626/
State : success

== Summary ==

Series 30626v1 drm/i915/cnp: Display Wa #1179: WaHardHangonHotPlug
https://patchwork.freedesktop.org/api/1.0/series/30626/revisions/1/mbox/

Test chamelium:
Subgroup dp-crc-fast:
pass   -> FAIL   (fi-kbl-7500u) fdo#102514
Test kms_frontbuffer_tracking:
Subgroup basic:
dmesg-warn -> PASS   (fi-kbl-7500u)
Test kms_pipe_crc_basic:
Subgroup hang-read-crc-pipe-b:
incomplete -> DMESG-WARN (fi-cfl-s) fdo#102294
Subgroup suspend-read-crc-pipe-a:
incomplete -> PASS   (fi-kbl-7500u)
Test drv_module_reload:
Subgroup basic-reload:
pass   -> DMESG-WARN (fi-glk-1) fdo#102777

fdo#102514 https://bugs.freedesktop.org/show_bug.cgi?id=102514
fdo#102294 https://bugs.freedesktop.org/show_bug.cgi?id=102294
fdo#102777 https://bugs.freedesktop.org/show_bug.cgi?id=102777

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:440s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:469s
fi-blb-e6850 total:289  pass:224  dwarn:1   dfail:0   fail:0   skip:64  
time:419s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:510s
fi-bwr-2160  total:289  pass:184  dwarn:0   dfail:0   fail:0   skip:105 
time:277s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:496s
fi-byt-j1900 total:289  pass:254  dwarn:1   dfail:0   fail:0   skip:34  
time:496s
fi-byt-n2820 total:289  pass:250  dwarn:1   dfail:0   fail:0   skip:38  
time:494s
fi-cfl-s total:289  pass:222  dwarn:35  dfail:0   fail:0   skip:32  
time:539s
fi-elk-e7500 total:289  pass:230  dwarn:0   dfail:0   fail:0   skip:59  
time:421s
fi-glk-1 total:289  pass:259  dwarn:1   dfail:0   fail:0   skip:29  
time:561s
fi-hsw-4770  total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:423s
fi-hsw-4770r total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:407s
fi-ilk-650   total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:431s
fi-ivb-3520m total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:493s
fi-ivb-3770  total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:464s
fi-kbl-7500u total:289  pass:263  dwarn:1   dfail:0   fail:1   skip:24  
time:467s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:574s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:586s
fi-pnv-d510  total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:542s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:448s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:747s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:487s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:474s
fi-snb-2520m total:289  pass:251  dwarn:0   dfail:0   fail:0   skip:38  
time:567s
fi-snb-2600  total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:418s

bf6ecf6d25c1c45e576643b7d7a65e8b1e6b4f01 drm-tip: 2017y-09m-19d-17h-23m-04s UTC 
integration manifest
a7e5944e9f01 drm/i915/cnp: Display Wa #1179: WaHardHangonHotPlug

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5759/
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[Intel-gfx] [PATCH 2/2] drm/i915/cnl: Fix SSEU Device Status.

[Rodrigo Vivi]

CNL adds an extra register for slice/subslice information.
Although no SKU is planed with an extra slice let's already
handle this extra piece of information so we don't have the
risk in future of getting a part that might have chosen this
part of the die instead of other slices or anything like that.

Also if subslice is disabled the information of eu ack for that
is garbage, so let's skip checks for eu if subslice is disabled
as we skip the subslice if slice is disabled.

The rest is pretty much like gen9.

v2: Remove IS_CANNONLAKE from gen9 status function.

Cc: Oscar Mateo 
Signed-off-by: Rodrigo Vivi 
Reviewed-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 54 +++--
 drivers/gpu/drm/i915/i915_reg.h |  6 +
 2 files changed, 58 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index ca6fa6d122c6..e86d2be4b815 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4575,6 +4575,54 @@ static void cherryview_sseu_device_status(struct 
drm_i915_private *dev_priv,
}
 }
 
+static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
+struct sseu_dev_info *sseu)
+{
+   const struct intel_device_info *info = INTEL_INFO(dev_priv);
+   int s_max = 4, ss_max = 3;
+   int s, ss;
+   u32 s_reg[s_max], eu_reg[2 * s_max], eu_mask[2];
+
+   for (s = 0; s < s_max; s++) {
+   s_reg[s] = I915_READ(GEN10_SLICE_PGCTL_ACK(s));
+   eu_reg[2 * s] = I915_READ(GEN10_SS01_EU_PGCTL_ACK(s));
+   eu_reg[2 * s + 1] = I915_READ(GEN10_SS23_EU_PGCTL_ACK(s));
+   }
+
+   eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
+GEN9_PGCTL_SSA_EU19_ACK |
+GEN9_PGCTL_SSA_EU210_ACK |
+GEN9_PGCTL_SSA_EU311_ACK;
+   eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
+GEN9_PGCTL_SSB_EU19_ACK |
+GEN9_PGCTL_SSB_EU210_ACK |
+GEN9_PGCTL_SSB_EU311_ACK;
+
+   for (s = 0; s < s_max; s++) {
+   if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
+   /* skip disabled slice */
+   continue;
+
+   sseu->slice_mask |= BIT(s);
+   sseu->subslice_mask = info->sseu.subslice_mask;
+
+   for (ss = 0; ss < ss_max; ss++) {
+   unsigned int eu_cnt;
+
+   if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss
+   /* skip disabled subslice */
+   continue;
+
+   eu_cnt = 2 * hweight32(eu_reg[2 * s + ss / 2] &
+  eu_mask[ss % 2]);
+   sseu->eu_total += eu_cnt;
+   sseu->eu_per_subslice = max_t(unsigned int,
+ sseu->eu_per_subslice,
+ eu_cnt);
+   }
+   }
+}
+
 static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
struct sseu_dev_info *sseu)
 {
@@ -4610,7 +4658,7 @@ static void gen9_sseu_device_status(struct 
drm_i915_private *dev_priv,
 
sseu->slice_mask |= BIT(s);
 
-   if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
+   if (IS_GEN9_BC(dev_priv))
sseu->subslice_mask =
INTEL_INFO(dev_priv)->sseu.subslice_mask;
 
@@ -4716,8 +4764,10 @@ static int i915_sseu_status(struct seq_file *m, void 
*unused)
cherryview_sseu_device_status(dev_priv, );
} else if (IS_BROADWELL(dev_priv)) {
broadwell_sseu_device_status(dev_priv, );
-   } else if (INTEL_GEN(dev_priv) >= 9) {
+   } else if (IS_GEN9(dev_priv)) {
gen9_sseu_device_status(dev_priv, );
+   } else if (INTEL_GEN(dev_priv) >= 10) {
+   gen10_sseu_device_status(dev_priv, );
}
 
intel_runtime_pm_put(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9f4b8faf2982..93b688666419 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8018,11 +8018,17 @@ enum {
 #define   CHV_EU311_PG_ENABLE  (1<<1)
 
 #define GEN9_SLICE_PGCTL_ACK(slice)_MMIO(0x804c + (slice)*0x4)
+#define GEN10_SLICE_PGCTL_ACK(slice)   ((slice) == 3 ? _MMIO(0x8080) : \
+GEN9_SLICE_PGCTL_ACK((slice)))
 #define   GEN9_PGCTL_SLICE_ACK (1 << 0)
 #define   GEN9_PGCTL_SS_ACK(subslice)  (1 << (2 + (subslice)*2))
 
 #define GEN9_SS01_EU_PGCTL_ACK(slice)  _MMIO(0x805c + (slice)*0x8)
+#define GEN10_SS01_EU_PGCTL_ACK(slice) ((slice) == 3 ? _MMIO(0x808c) : \
+  

[Intel-gfx] [PATCH 1/2] drm/i915/cnl: Add support slice/subslice/eu configs

[Rodrigo Vivi]

From: Ben Widawsky 

Cannonlake Slice and Subslice information has changed.

This patch initially provided by Ben adds the proper sseu
initialization.

v2: This v2 done by Rodrigo includes:
- Fix on Total slices count by avoiding [1][2] and [2][2].
- Inclusion of EU Per Subslice.
- Commit message.
v3: This v3 done by Rodrigo includes:
- Handle all possible bits and extra fuse register.
- Use INTEL_GEN macro.
- Fully assume uniform distribution so remove union
  with eu_per_subslice and add proper the comment.
v4: This v4 done by Rodrigo includes:
- Consider all bits available: 6 bits for slices [27:22]
  and 4 for subslices [21:18].
v5: This v5 done by Rodrigo includes:
- sseu->subslice_mask = (1 << 4) - 1 - missed on previous
versions and noticed by Oscar.

Cc: Oscar Mateo 
Signed-off-by: Ben Widawsky 
Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/i915_reg.h  |  8 +++
 drivers/gpu/drm/i915/intel_device_info.c | 37 +++-
 2 files changed, 44 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 94b40a469afd..9f4b8faf2982 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2730,6 +2730,11 @@ enum i915_power_well_id {
 #define   GEN9_F2_SS_DIS_SHIFT 20
 #define   GEN9_F2_SS_DIS_MASK  (0xf << GEN9_F2_SS_DIS_SHIFT)
 
+#define   GEN10_F2_S_ENA_SHIFT 22
+#define   GEN10_F2_S_ENA_MASK  (0x3f << GEN10_F2_S_ENA_SHIFT)
+#define   GEN10_F2_SS_DIS_SHIFT18
+#define   GEN10_F2_SS_DIS_MASK (0xf << GEN10_F2_SS_DIS_SHIFT)
+
 #define GEN8_EU_DISABLE0   _MMIO(0x9134)
 #define   GEN8_EU_DIS0_S0_MASK 0xff
 #define   GEN8_EU_DIS0_S1_SHIFT24
@@ -2745,6 +2750,9 @@ enum i915_power_well_id {
 
 #define GEN9_EU_DISABLE(slice) _MMIO(0x9134 + (slice)*0x4)
 
+#define GEN10_EU_DISABLE3  _MMIO(0x9140)
+#define   GEN10_EU_DIS_SS_MASK 0xff
+
 #define GEN6_BSD_SLEEP_PSMI_CONTROL_MMIO(0x12050)
 #define   GEN6_BSD_SLEEP_MSG_DISABLE   (1 << 0)
 #define   GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c 
b/drivers/gpu/drm/i915/intel_device_info.c
index 43831b09b47a..d2e7ae61775d 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -82,6 +82,39 @@ void intel_device_info_dump(struct drm_i915_private 
*dev_priv)
 #undef PRINT_FLAG
 }
 
+static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
+{
+   struct sseu_dev_info *sseu = _device_info(dev_priv)->sseu;
+   const u32 fuse2 = I915_READ(GEN8_FUSE2);
+
+   sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>
+   GEN10_F2_S_ENA_SHIFT;
+   sseu->subslice_mask = (1 << 4) - 1;
+   sseu->subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
+GEN10_F2_SS_DIS_SHIFT);
+
+   sseu->eu_total = hweight32(~I915_READ(GEN8_EU_DISABLE0));
+   sseu->eu_total += hweight32(~I915_READ(GEN8_EU_DISABLE1));
+   sseu->eu_total += hweight32(~I915_READ(GEN8_EU_DISABLE2));
+   sseu->eu_total += hweight8(~(I915_READ(GEN10_EU_DISABLE3) &
+GEN10_EU_DIS_SS_MASK));
+
+   /*
+* CNL is expected to always have a uniform distribution
+* of EU across subslices with the exception that any one
+* EU in any one subslice may be fused off for die
+* recovery.
+*/
+   sseu->eu_per_subslice = sseu_subslice_total(sseu) ?
+   DIV_ROUND_UP(sseu->eu_total,
+sseu_subslice_total(sseu)) : 0;
+
+   /* No restrictions on Power Gating */
+   sseu->has_slice_pg = 1;
+   sseu->has_subslice_pg = 1;
+   sseu->has_eu_pg = 1;
+}
+
 static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
 {
struct sseu_dev_info *sseu = _device_info(dev_priv)->sseu;
@@ -409,8 +442,10 @@ void intel_device_info_runtime_init(struct 
drm_i915_private *dev_priv)
cherryview_sseu_info_init(dev_priv);
else if (IS_BROADWELL(dev_priv))
broadwell_sseu_info_init(dev_priv);
-   else if (INTEL_INFO(dev_priv)->gen >= 9)
+   else if (INTEL_GEN(dev_priv) == 9)
gen9_sseu_info_init(dev_priv);
+   else if (INTEL_GEN(dev_priv) >= 10)
+   gen10_sseu_info_init(dev_priv);
 
DRM_DEBUG_DRIVER("slice mask: %04x\n", info->sseu.slice_mask);
DRM_DEBUG_DRIVER("slice total: %u\n", hweight8(info->sseu.slice_mask));
-- 
2.13.5

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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/edp: Be less aggressive about changing link config on eDP (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915/edp: Be less aggressive about changing link config on eDP 
(rev4)
URL   : https://patchwork.freedesktop.org/series/28588/
State : failure

== Summary ==

Series 28588v4 drm/i915/edp: Be less aggressive about changing link config on 
eDP
https://patchwork.freedesktop.org/api/1.0/series/28588/revisions/4/mbox/

Test gem_exec_reloc:
Subgroup basic-gtt-cpu-active:
pass   -> INCOMPLETE (fi-byt-j1900)
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
pass   -> FAIL   (fi-snb-2600) fdo#100215
Test kms_frontbuffer_tracking:
Subgroup basic:
dmesg-warn -> PASS   (fi-kbl-7500u)
Test kms_pipe_crc_basic:
Subgroup hang-read-crc-pipe-b:
incomplete -> DMESG-WARN (fi-cfl-s) fdo#102294
Subgroup suspend-read-crc-pipe-a:
incomplete -> PASS   (fi-kbl-7500u)
Test drv_module_reload:
Subgroup basic-reload:
pass   -> DMESG-WARN (fi-glk-1) fdo#102777

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#102294 https://bugs.freedesktop.org/show_bug.cgi?id=102294
fdo#102777 https://bugs.freedesktop.org/show_bug.cgi?id=102777

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:439s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:470s
fi-blb-e6850 total:289  pass:224  dwarn:1   dfail:0   fail:0   skip:64  
time:415s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:514s
fi-bwr-2160  total:289  pass:184  dwarn:0   dfail:0   fail:0   skip:105 
time:278s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:514s
fi-byt-j1900 total:102  pass:83   dwarn:0   dfail:0   fail:0   skip:18 
fi-byt-n2820 total:289  pass:250  dwarn:1   dfail:0   fail:0   skip:38  
time:479s
fi-cfl-s total:289  pass:222  dwarn:35  dfail:0   fail:0   skip:32  
time:542s
fi-elk-e7500 total:289  pass:230  dwarn:0   dfail:0   fail:0   skip:59  
time:416s
fi-glk-1 total:289  pass:259  dwarn:1   dfail:0   fail:0   skip:29  
time:564s
fi-hsw-4770  total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:426s
fi-hsw-4770r total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:403s
fi-ilk-650   total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:427s
fi-ivb-3520m total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:484s
fi-ivb-3770  total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:458s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:472s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:573s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:586s
fi-pnv-d510  total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:542s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:448s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:750s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:487s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:476s
fi-snb-2520m total:289  pass:251  dwarn:0   dfail:0   fail:0   skip:38  
time:568s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:1   skip:39  
time:414s

bf6ecf6d25c1c45e576643b7d7a65e8b1e6b4f01 drm-tip: 2017y-09m-19d-17h-23m-04s UTC 
integration manifest
d200ddf98baa drm/i915/edp: Be less aggressive about changing link config on eDP

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5758/
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[Intel-gfx] [PATCH] drm/i915/cnp: Display Wa #1179: WaHardHangonHotPlug

[Rodrigo Vivi]

"CNL PCH chance of hang when software accesses south display
registers after hotplug is enabled.
Workaround: Program 0xC2000 bits 11:8 = 0xF before enabling
south display hotplug detection."

"Workaround only needs to be applied to pre-production steppings
used in graphics capable SKUs, but it is easier to apply to
everything, and does not hurt."

v2: Moving from clock gating to right before enabling
SHOTPLUG_CTL as it should be.
v3: Align with SOUTH_CHICKEN1 (DK) and consequently use proper
spaces on bits definition since other bits around already use
new style. And now that checkpatch is not noise anymore I also
fixed the reg read mask to avoid going over 80 chars.

Suggested-by: Ben Widawsky 
Cc: Ben Widawsky 
Cc: Dhinakaran Pandiyan 
Signed-off-by: Rodrigo Vivi 
Reviewed-by: Dhinakaran Pandiyan 
---
 drivers/gpu/drm/i915/i915_irq.c | 10 +-
 drivers/gpu/drm/i915/i915_reg.h |  2 ++
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 4d0e8f76ed1a..c23efc4394ce 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3218,7 +3218,15 @@ static void ibx_hpd_irq_setup(struct drm_i915_private 
*dev_priv)
 
 static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
 {
-   u32 hotplug;
+   u32 val, hotplug;
+
+   /* Display WA #1179 WaHardHangonHotPlug: cnp */
+   if (HAS_PCH_CNP(dev_priv)) {
+   val = I915_READ(SOUTH_CHICKEN1);
+   val &= ~CHASSIS_CLK_REQ_DURATION_MASK;
+   val |= CHASSIS_CLK_REQ_DURATION(0xf);
+   I915_WRITE(SOUTH_CHICKEN1, val);
+   }
 
/* Enable digital hotplug on the PCH */
hotplug = I915_READ(PCH_PORT_HOTPLUG);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 94b40a469afd..82f36dd0cd94 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7471,6 +7471,8 @@ enum {
 #define  FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 
2)))
 #define  FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
 #define  FDI_BC_BIFURCATION_SELECT (1 << 12)
+#define  CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8)
+#define  CHASSIS_CLK_REQ_DURATION(x)   ((x) << 8)
 #define  SPT_PWM_GRANULARITY   (1<<0)
 #define SOUTH_CHICKEN2 _MMIO(0xc2004)
 #define  FDI_MPHY_IOSFSB_RESET_STATUS  (1<<13)
-- 
2.13.5

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Re: [Intel-gfx] [PATCH 0/6] Adding NV12 support

[Kristian Høgsberg]

On Mon, Aug 28, 2017 at 3:17 PM, Daniel Vetter  wrote:
> On Mon, Aug 28, 2017 at 04:22:16PM +0530, Vidya Srinivas wrote:
>> This patch series is adding NV12 support for Broxton display after
>> rebasing on latest drm-intel-nightly. Initial series of the patches
>> can be found here:
>> https://lists.freedesktop.org/archives/intel-gfx/2015-May/066786.html
>>
>> Previous revision history:
>> Patches were initial reviewed last when floated but
>> currently there was a design change with respect to
>> - the way fb offset is handled
>> - the way rotation is handled
>> Rebase of the current NV12 patch series has been done as per the
>> current changes on drm-intel-nightly.
>> Review comments from Ville (12th June 2017) have been addressed
>> Review comments from Clinton A Taylor (7th July 2017) have been
>> addressed
>> Review comments from Clinton A Taylor (10th July 2017) have been
>> addressed. Had missed out tested-by/reviewed-by in the patches.
>> Fixed that error in this series.
>> Review comments from Ville (11th July 2017) addressed.
>> Review comments from Paauwe, Bob (29th July 2017) addressed.
>>
>> Update from last rev:
>> Rebased the series as Ville's patches are merged. Previously,
>> this series included those floating patches.
>>
>> Chandra Konduru (6):
>>   drm/i915: Set scaler mode for NV12
>>   drm/i915: Update format_is_yuv() to include NV12
>>   drm/i915: Upscale scaler max scale for NV12
>>   drm/i915: Add NV12 as supported format for primary plane
>>   drm/i915: Add NV12 as supported format for sprite plane
>>   drm/i915: Add NV12 support to intel_framebuffer_init
>
> Needs serious work on the plane scaling igt (it's atm all broken, and
> doesn't test any atomic interactions).
>
> Then this needs serious work on the nv12 plane igts (which don't yet
> exist).
>
> Then this probably needs pile more igts to test interactions between
> everything (e.g. rotation, ...).
>
> In short: This needs itgs. Lots of them :-)
>
> Before those exist, and before we've tracked down the bug in the existing
> code you're building on it imo makes no sense to start reviewing these
> here.

Also, this series need to advertise which modifiers work with the new
NV12 format by adding a case to
skl_sprite_plane_format_mod_supported() and skl_mod_supported().

Kristian

> Thanks, Daniel
>
>>
>>  drivers/gpu/drm/i915/i915_reg.h  |  1 +
>>  drivers/gpu/drm/i915/intel_atomic.c  |  8 -
>>  drivers/gpu/drm/i915/intel_display.c | 67 
>> +---
>>  drivers/gpu/drm/i915/intel_drv.h |  3 +-
>>  drivers/gpu/drm/i915/intel_sprite.c  | 34 ++
>>  5 files changed, 92 insertions(+), 21 deletions(-)
>>
>> --
>> 1.9.1
>>
>> ___
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>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH][drm-next] drm/i915/gvt: ensure -ve return value is handled correctly

[Zhenyu Wang]

On 2017.09.19 16:55:34 +0100, Colin King wrote:
> From: Colin Ian King 
> 
> An earlier fix changed the return type from find_bb_size however the
> integer return is being assigned to a unsigned int so the -ve error
> check will never be detected. Make bb_size an int to fix this.
> 
> Detected by CoverityScan CID#1456886 ("Unsigned compared against 0")
> 
> Fixes: 1e3197d6ad73 ("drm/i915/gvt: Refine error handling for 
> perform_bb_shadow")
> Signed-off-by: Colin Ian King 
> ---
>  drivers/gpu/drm/i915/gvt/cmd_parser.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c 
> b/drivers/gpu/drm/i915/gvt/cmd_parser.c
> index 2c0ccbb817dc..f41cbf664b69 100644
> --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
> +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
> @@ -1628,7 +1628,7 @@ static int perform_bb_shadow(struct parser_exec_state 
> *s)
>   struct intel_shadow_bb_entry *entry_obj;
>   struct intel_vgpu *vgpu = s->vgpu;
>   unsigned long gma = 0;
> - uint32_t bb_size;
> + int bb_size;
>   void *dst = NULL;
>   int ret = 0;
>  

Applied this, thanks!

-- 
Open Source Technology Center, Intel ltd.

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Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with drm/i915/cnp: Display Wa #1179: WaHardHangonHotPlug (rev3)

[Rodrigo Vivi]

On Tue, Sep 19, 2017 at 08:28:16PM +, Patchwork wrote:
> == Series Details ==
> 
> Series: series starting with drm/i915/cnp: Display Wa #1179: 
> WaHardHangonHotPlug (rev3)
> URL   : https://patchwork.freedesktop.org/series/30067/
> State : failure
> 
> == Summary ==
> 
>   CHK include/config/kernel.release
>   CHK include/generated/uapi/linux/version.h
>   CHK include/generated/utsrelease.h
>   CHK include/generated/bounds.h
>   CHK include/generated/timeconst.h
>   CHK include/generated/asm-offsets.h
>   CALLscripts/checksyscalls.sh
>   CHK scripts/mod/devicetable-offsets.h
>   CHK include/generated/compile.h
>   CHK kernel/config_data.h
>   CC [M]  drivers/gpu/drm/i915/i915_drv.o
> In file included from drivers/gpu/drm/i915/i915_drv.h:55:0,
>  from drivers/gpu/drm/i915/i915_drv.c:49:
> drivers/gpu/drm/i915/i915_reg.h:7480:0: error: 
> "CHASSIS_CLK_REQ_DURATION_MASK" redefined [-Werror]
>  #define  CHASSIS_CLK_REQ_DURATION_MASK (0xf<<8)
>  
> drivers/gpu/drm/i915/i915_reg.h:7474:0: note: this is the location of the 
> previous definition
>  #define  CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8)
>  
> drivers/gpu/drm/i915/i915_reg.h:7481:0: error: "CHASSIS_CLK_REQ_DURATION" 
> redefined [-Werror]
>  #define  CHASSIS_CLK_REQ_DURATION(x) ((x)<<8)
>  
> drivers/gpu/drm/i915/i915_reg.h:7475:0: note: this is the location of the 
> previous definition
>  #define  CHASSIS_CLK_REQ_DURATION(x) ((x) << 8)

It seems CI is not removing the previous version properly before applying this 
new version...

or something else similarly odd happening...

>  
> cc1: all warnings being treated as errors
> scripts/Makefile.build:311: recipe for target 
> 'drivers/gpu/drm/i915/i915_drv.o' failed
> make[4]: *** [drivers/gpu/drm/i915/i915_drv.o] Error 1
> scripts/Makefile.build:570: recipe for target 'drivers/gpu/drm/i915' failed
> make[3]: *** [drivers/gpu/drm/i915] Error 2
> scripts/Makefile.build:570: recipe for target 'drivers/gpu/drm' failed
> make[2]: *** [drivers/gpu/drm] Error 2
> scripts/Makefile.build:570: recipe for target 'drivers/gpu' failed
> make[1]: *** [drivers/gpu] Error 2
> Makefile:1019: recipe for target 'drivers' failed
> make: *** [drivers] Error 2
> 
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915: Unset legacy_cursor_update early in intel_atomic_commit, v3.

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915: Unset legacy_cursor_update early 
in intel_atomic_commit, v3.
URL   : https://patchwork.freedesktop.org/series/30587/
State : success

== Summary ==

Test perf:
Subgroup polling:
fail   -> PASS   (shard-hsw) fdo#102252 +1
Test kms_flip:
Subgroup rcs-wf_vblank-vs-dpms:
dmesg-warn -> PASS   (shard-hsw)

fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-hswtotal:2317 pass:1245 dwarn:3   dfail:0   fail:12  skip:1057 
time:9699s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5748/shards.html
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/cnl: Add support slice/subslice/eu configs (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/cnl: Add support slice/subslice/eu 
configs (rev2)
URL   : https://patchwork.freedesktop.org/series/30549/
State : failure

== Summary ==

Series 30549v2 series starting with [1/2] drm/i915/cnl: Add support 
slice/subslice/eu configs
https://patchwork.freedesktop.org/api/1.0/series/30549/revisions/2/mbox/

Test gem_exec_suspend:
Subgroup basic-s3:
pass   -> INCOMPLETE (fi-kbl-r) fdo#102850
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
pass   -> FAIL   (fi-snb-2600) fdo#100215
Test kms_flip:
Subgroup basic-flip-vs-wf_vblank:
pass   -> INCOMPLETE (fi-bxt-j4205)
Test kms_frontbuffer_tracking:
Subgroup basic:
dmesg-warn -> PASS   (fi-kbl-7500u)
Test kms_pipe_crc_basic:
Subgroup hang-read-crc-pipe-b:
incomplete -> DMESG-WARN (fi-cfl-s) fdo#102294
Subgroup suspend-read-crc-pipe-a:
incomplete -> PASS   (fi-kbl-7500u)
Test drv_module_reload:
Subgroup basic-reload-inject:
pass   -> DMESG-WARN (fi-glk-1) fdo#102777

fdo#102850 https://bugs.freedesktop.org/show_bug.cgi?id=102850
fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#102294 https://bugs.freedesktop.org/show_bug.cgi?id=102294
fdo#102777 https://bugs.freedesktop.org/show_bug.cgi?id=102777

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:440s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:467s
fi-blb-e6850 total:289  pass:224  dwarn:1   dfail:0   fail:0   skip:64  
time:416s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:509s
fi-bwr-2160  total:289  pass:184  dwarn:0   dfail:0   fail:0   skip:105 
time:278s
fi-bxt-j4205 total:219  pass:197  dwarn:0   dfail:0   fail:0   skip:21 
fi-byt-j1900 total:289  pass:254  dwarn:1   dfail:0   fail:0   skip:34  
time:494s
fi-byt-n2820 total:289  pass:250  dwarn:1   dfail:0   fail:0   skip:38  
time:486s
fi-cfl-s total:289  pass:222  dwarn:35  dfail:0   fail:0   skip:32  
time:538s
fi-elk-e7500 total:289  pass:230  dwarn:0   dfail:0   fail:0   skip:59  
time:407s
fi-glk-1 total:289  pass:259  dwarn:1   dfail:0   fail:0   skip:29  
time:566s
fi-hsw-4770  total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:424s
fi-hsw-4770r total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:406s
fi-ilk-650   total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:432s
fi-ivb-3520m total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:487s
fi-ivb-3770  total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:459s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:470s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:576s
fi-kbl-r total:118  pass:97   dwarn:0   dfail:0   fail:0   skip:20 
fi-pnv-d510  total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:544s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:454s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:753s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:490s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:482s
fi-snb-2520m total:289  pass:251  dwarn:0   dfail:0   fail:0   skip:38  
time:575s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:1   skip:39  
time:412s

bf6ecf6d25c1c45e576643b7d7a65e8b1e6b4f01 drm-tip: 2017y-09m-19d-17h-23m-04s UTC 
integration manifest
b954a7b1e47c drm/i915/cnl: Fix SSEU Device Status.
1c6198647321 drm/i915/cnl: Add support slice/subslice/eu configs

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5757/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v8] drm/i915/edp: Be less aggressive about changing link config on eDP

[Jim Bride]

This set of changes has some history to them.  There were several attempts
to add what was called "fast link training" to i915, which actually wasn't
fast link training as per the DP spec.  These changes were:

commit 5fa836a9d859 ("drm/i915: DP link training optimization")
commit 4e96c97742f4 ("drm/i915: eDP link training optimization")

which were eventually hand-reverted by:

commit 34511dce4b35 ("drm/i915: Revert DisplayPort fast link training
 feature")

in kernel 4.7-rc4.  The eDP pieces of the above revert, however, had some
very bad side-effects on PSR functionality on Skylake. The issue at
hand is that when PSR exits i915 briefly emits TP1 followed by TP2/3
(depending on the original link configuration) in order to quickly get
the source and sink back in synchronization across the link before handing
control back to the i915.  There's an assumption that none of the link
configuration information has changed (and thus it's still valid) since the
last full link training operation.  The revert above was identified via a
bisect as the cause of some of Skylake's PSR woes.  This patch, largely
based on commit 4e96c97742f4 ("drm/i915: eDP link training optimization")
puts the eDP portions of this patch back in place.  None of the flickering
issues that spurred the revert have been seen, and I suspect the real
culprits here were addressed by some of the recent link training changes
that Manasi has implemented, and PSR on Skylake is definitely more happy
with these changes in-place.

v2 and v3: Rebase
v4: * Clean up accesses to train_set_valid a bit for easier
  reading. (Chris)
* Rebase
v5: * Checkpatch cleanup
* Rebase
v6: * is_edp() => intel_dp_is_edp()
* rebase
v7: * Remove extraneous is_edp() prototype (Rodrigo)
v8: Rebase

Cc: Chris Wilson 
Cc: Rodrigo Vivi 
Cc: Paulo Zanoni 
Cc: Manasi D Navare 
Cc: Mika Kahola 
Cc: Jani Nikula 
Fixes: 34511dce4 ("drm/i915: Revert DisplayPort fast link training feature")
Reviewed-by: Manasi Navare 
Signed-off-by: Jim Bride 
---
 drivers/gpu/drm/i915/intel_dp.c   |  2 ++
 drivers/gpu/drm/i915/intel_dp_link_training.c | 15 ++-
 drivers/gpu/drm/i915/intel_drv.h  |  1 +
 3 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 8db6b11..aee7e9b 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4748,6 +4748,7 @@ intel_dp_long_pulse(struct intel_connector 
*intel_connector)
intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 
intel_dp->reset_link_params = false;
+   intel_dp->train_set_valid = false;
}
 
intel_dp_print_rates(intel_dp);
@@ -6017,6 +6018,7 @@ intel_dp_init_connector(struct intel_digital_port 
*intel_dig_port,
intel_dp_set_source_rates(intel_dp);
 
intel_dp->reset_link_params = true;
+   intel_dp->train_set_valid = false;
intel_dp->pps_pipe = INVALID_PIPE;
intel_dp->active_pipe = INVALID_PIPE;
 
diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c 
b/drivers/gpu/drm/i915/intel_dp_link_training.c
index 05907fa..79fe369 100644
--- a/drivers/gpu/drm/i915/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
@@ -94,7 +94,8 @@ static bool
 intel_dp_reset_link_train(struct intel_dp *intel_dp,
uint8_t dp_train_pat)
 {
-   memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
+   if (!intel_dp->train_set_valid)
+   memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
intel_dp_set_signal_levels(intel_dp);
return intel_dp_set_link_train(intel_dp, dp_train_pat);
 }
@@ -162,9 +163,18 @@ intel_dp_link_training_clock_recovery(struct intel_dp 
*intel_dp)
   DP_TRAINING_PATTERN_1 |
   DP_LINK_SCRAMBLING_DISABLE)) {
DRM_ERROR("failed to enable link training\n");
+   intel_dp->train_set_valid = false;
return false;
}
 
+   /*
+* The initial set of link parameters are set by this point, so go
+* ahead and set intel_dp->train_set_valid to false in case any of
+* the succeeding steps fail.  It will be set back to true if we were
+* able to achieve clock recovery in the specified configuration.
+*/
+   intel_dp->train_set_valid = false;
+
voltage_tries = 1;
max_vswing_tries = 0;
for (;;) {
@@ -179,6 +189,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp 
*intel_dp)
 
if (drm_dp_clock_recovery_ok(link_status, 
intel_dp->lane_count)) {

Re: [Intel-gfx] [PATCH v7] drm/i915/edp: Be less aggressive about changing link config on eDP

[Jim Bride]

On Tue, Sep 19, 2017 at 12:55:24PM -0700, Rodrigo Vivi wrote:
> On Fri, Sep 15, 2017 at 06:19:12PM +, Manasi Navare wrote:
> > The patch looks good for eDP link training optimizations.
> > 
> > Reviewed-by: Manasi Navare 
> 
> I haven't merged this patch yet because I'd like an Ack from Jani.
> 
> Also I'd like to hear from Mika if he believes it is safe or not.

Mika looked at it a few months ago and thought it would be ok.  It
can't hurt to have him look at it again, though.

> On his revert commit he wrote:
> "It has been found out that in some HW combination the DisplayPort
>  fast link training feature caused screen flickering. Let's revert
>  this feature for now until we can ensure that the feature works for
>  all platforms."
> 
> I don't want to merge this patch to fix a feature that is disabled
> by default with the risk of bringing flickerings back.
> 
> But even if we decide to go ahead and merge I believe we need to
> resend the test and collect a full round of CI that now runs
> all IGT tests.

I assume you mean resend the patch here.  I'll do that.

Jim

> Thanks,
> Rodrigo.
> 
> 
> > 
> > Manasi
> > 
> > On Tue, Aug 22, 2017 at 09:34:46AM -0700, Jim Bride wrote:
> > > This set of changes has some history to them.  There were several attempts
> > > to add what was called "fast link training" to i915, which actually wasn't
> > > fast link training as per the DP spec.  These changes were:
> > > 
> > > commit 5fa836a9d859 ("drm/i915: DP link training optimization")
> > > commit 4e96c97742f4 ("drm/i915: eDP link training optimization")
> > > 
> > > which were eventually hand-reverted by:
> > > 
> > > commit 34511dce4b35 ("drm/i915: Revert DisplayPort fast link training
> > >  feature")
> > > 
> > > in kernel 4.7-rc4.  The eDP pieces of the above revert, however, had some
> > > very bad side-effects on PSR functionality on Skylake. The issue at
> > > hand is that when PSR exits i915 briefly emits TP1 followed by TP2/3
> > > (depending on the original link configuration) in order to quickly get
> > > the source and sink back in synchronization across the link before handing
> > > control back to the i915.  There's an assumption that none of the link
> > > configuration information has changed (and thus it's still valid) since 
> > > the
> > > last full link training operation.  The revert above was identified via a
> > > bisect as the cause of some of Skylake's PSR woes.  This patch, largely
> > > based on commit 4e96c97742f4 ("drm/i915: eDP link training optimization")
> > > puts the eDP portions of this patch back in place.  None of the flickering
> > > issues that spurred the revert have been seen, and I suspect the real
> > > culprits here were addressed by some of the recent link training changes
> > > that Manasi has implemented, and PSR on Skylake is definitely more happy
> > > with these changes in-place.
> > > 
> > > v2 and v3: Rebase
> > > v4: * Clean up accesses to train_set_valid a bit for easier
> > >   reading. (Chris)
> > > * Rebase
> > > v5: * Checkpatch cleanup
> > > * Rebase
> > > v6: * is_edp() => intel_dp_is_edp()
> > > * rebase
> > > v7: * Remove extraneous is_edp() prototype (Rodrigo)
> > > 
> > > Cc: Chris Wilson 
> > > Cc: Rodrigo Vivi 
> > > Cc: Paulo Zanoni 
> > > Cc: Manasi D Navare 
> > > Cc: Mika Kahola 
> > > Cc: Jani Nikula 
> > > Fixes: 34511dce4 ("drm/i915: Revert DisplayPort fast link training 
> > > feature")
> > > Signed-off-by: Jim Bride 
> > > ---
> > >  drivers/gpu/drm/i915/intel_dp.c   |  2 ++
> > >  drivers/gpu/drm/i915/intel_dp_link_training.c | 15 ++-
> > >  drivers/gpu/drm/i915/intel_drv.h  |  1 +
> > >  3 files changed, 17 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_dp.c 
> > > b/drivers/gpu/drm/i915/intel_dp.c
> > > index e385658..38bc7e0 100644
> > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > @@ -4750,6 +4750,7 @@ intel_dp_long_pulse(struct intel_connector 
> > > *intel_connector)
> > >   intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
> > >  
> > >   intel_dp->reset_link_params = false;
> > > + intel_dp->train_set_valid = false;
> > >   }
> > >  
> > >   intel_dp_print_rates(intel_dp);
> > > @@ -6019,6 +6020,7 @@ intel_dp_init_connector(struct intel_digital_port 
> > > *intel_dig_port,
> > >   intel_dp_set_source_rates(intel_dp);
> > >  
> > >   intel_dp->reset_link_params = true;
> > > + intel_dp->train_set_valid = false;
> > >   intel_dp->pps_pipe = INVALID_PIPE;
> > >   intel_dp->active_pipe = INVALID_PIPE;
> > >  
> > > diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c 
> > > b/drivers/gpu/drm/i915/intel_dp_link_training.c
> > > index 

Re: [Intel-gfx] [PATCH 1/2] drm/i915/cnl: Add support slice/subslice/eu configs

[Oscar Mateo]

On 09/19/2017 02:02 PM, Rodrigo Vivi wrote:

From: Ben Widawsky 

Cannonlake Slice and Subslice information has changed.

This patch initially provided by Ben adds the proper sseu
initialization.

v2: This v2 done by Rodrigo includes:
 - Fix on Total slices count by avoiding [1][2] and [2][2].
 - Inclusion of EU Per Subslice.
 - Commit message.
v3: This v3 done by Rodrigo includes:
 - Handle all possible bits and extra fuse register.
 - Use INTEL_GEN macro.
 - Fully assume uniform distribution so remove union
   with eu_per_subslice and add proper the comment.
v4: This v4 done by Rodrigo includes:
 - Consider all bits available: 6 bits for slices [27:22]
   and 4 for subslices [21:18].

Cc: Oscar Mateo 
Signed-off-by: Ben Widawsky 
Signed-off-by: Rodrigo Vivi 
---
  drivers/gpu/drm/i915/i915_reg.h  |  8 +++
  drivers/gpu/drm/i915/intel_device_info.c | 37 +++-
  2 files changed, 44 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 94b40a469afd..9f4b8faf2982 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2730,6 +2730,11 @@ enum i915_power_well_id {
  #define   GEN9_F2_SS_DIS_SHIFT20
  #define   GEN9_F2_SS_DIS_MASK (0xf << GEN9_F2_SS_DIS_SHIFT)
  
+#define   GEN10_F2_S_ENA_SHIFT		22

+#define   GEN10_F2_S_ENA_MASK  (0x3f << GEN10_F2_S_ENA_SHIFT)
+#define   GEN10_F2_SS_DIS_SHIFT18
+#define   GEN10_F2_SS_DIS_MASK (0xf << GEN10_F2_SS_DIS_SHIFT)


H... I thought you were going to read less registers for the EU 
count, but yes, this also works :)



+
  #define GEN8_EU_DISABLE0  _MMIO(0x9134)
  #define   GEN8_EU_DIS0_S0_MASK0xff
  #define   GEN8_EU_DIS0_S1_SHIFT   24
@@ -2745,6 +2750,9 @@ enum i915_power_well_id {
  
  #define GEN9_EU_DISABLE(slice)		_MMIO(0x9134 + (slice)*0x4)
  
+#define GEN10_EU_DISABLE3		_MMIO(0x9140)

+#define   GEN10_EU_DIS_SS_MASK 0xff
+
  #define GEN6_BSD_SLEEP_PSMI_CONTROL   _MMIO(0x12050)
  #define   GEN6_BSD_SLEEP_MSG_DISABLE  (1 << 0)
  #define   GEN6_BSD_SLEEP_FLUSH_DISABLE(1 << 2)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c 
b/drivers/gpu/drm/i915/intel_device_info.c
index 43831b09b47a..85693811c1b0 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -82,6 +82,39 @@ void intel_device_info_dump(struct drm_i915_private 
*dev_priv)
  #undef PRINT_FLAG
  }
  
+static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)

+{
+   struct sseu_dev_info *sseu = _device_info(dev_priv)->sseu;
+   const u32 fuse2 = I915_READ(GEN8_FUSE2);
+
+   sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>
+   GEN10_F2_S_ENA_SHIFT;
+   sseu->subslice_mask = (1 << 3) - 1;


But this should be now: (1 << 4) - 1 (or maybe use a local ss_max for 
clarity, like in the other patch)



+   sseu->subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
+GEN10_F2_SS_DIS_SHIFT);
+
+   sseu->eu_total = hweight32(~I915_READ(GEN8_EU_DISABLE0));
+   sseu->eu_total += hweight32(~I915_READ(GEN8_EU_DISABLE1));
+   sseu->eu_total += hweight32(~I915_READ(GEN8_EU_DISABLE2));
+   sseu->eu_total += hweight8(~(I915_READ(GEN10_EU_DISABLE3) &
+GEN10_EU_DIS_SS_MASK));
+
+   /*
+* CNL is expected to always have a uniform distribution
+* of EU across subslices with the exception that any one
+* EU in any one subslice may be fused off for die
+* recovery.
+*/
+   sseu->eu_per_subslice = sseu_subslice_total(sseu) ?
+   DIV_ROUND_UP(sseu->eu_total,
+sseu_subslice_total(sseu)) : 0;
+
+   /* No restrictions on Power Gating */
+   sseu->has_slice_pg = 1;
+   sseu->has_subslice_pg = 1;
+   sseu->has_eu_pg = 1;
+}
+
  static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
  {
struct sseu_dev_info *sseu = _device_info(dev_priv)->sseu;
@@ -409,8 +442,10 @@ void intel_device_info_runtime_init(struct 
drm_i915_private *dev_priv)
cherryview_sseu_info_init(dev_priv);
else if (IS_BROADWELL(dev_priv))
broadwell_sseu_info_init(dev_priv);
-   else if (INTEL_INFO(dev_priv)->gen >= 9)
+   else if (INTEL_GEN(dev_priv) == 9)
gen9_sseu_info_init(dev_priv);
+   else if (INTEL_GEN(dev_priv) >= 10)
+   gen10_sseu_info_init(dev_priv);
  
  	DRM_DEBUG_DRIVER("slice mask: %04x\n", info->sseu.slice_mask);

DRM_DEBUG_DRIVER("slice total: %u\n", hweight8(info->sseu.slice_mask));


___
Intel-gfx mailing 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Skylake plane update/disable unifications [v5]

[Patchwork]

== Series Details ==

Series: drm/i915: Skylake plane update/disable unifications [v5]
URL   : https://patchwork.freedesktop.org/series/30622/
State : success

== Summary ==

Series 30622v1 drm/i915: Skylake plane update/disable unifications [v5]
https://patchwork.freedesktop.org/api/1.0/series/30622/revisions/1/mbox/

Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-legacy:
pass   -> FAIL   (fi-snb-2600) fdo#100215
Test kms_frontbuffer_tracking:
Subgroup basic:
dmesg-warn -> PASS   (fi-kbl-7500u)
Test kms_pipe_crc_basic:
Subgroup hang-read-crc-pipe-b:
incomplete -> DMESG-WARN (fi-cfl-s) fdo#102294 +1
Subgroup suspend-read-crc-pipe-a:
incomplete -> PASS   (fi-kbl-7500u)
Test drv_module_reload:
Subgroup basic-reload-inject:
pass   -> DMESG-WARN (fi-glk-1) fdo#102777

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#102294 https://bugs.freedesktop.org/show_bug.cgi?id=102294
fdo#102777 https://bugs.freedesktop.org/show_bug.cgi?id=102777

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:441s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:466s
fi-blb-e6850 total:289  pass:224  dwarn:1   dfail:0   fail:0   skip:64  
time:420s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:518s
fi-bwr-2160  total:289  pass:184  dwarn:0   dfail:0   fail:0   skip:105 
time:280s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:506s
fi-byt-j1900 total:289  pass:254  dwarn:1   dfail:0   fail:0   skip:34  
time:492s
fi-byt-n2820 total:289  pass:250  dwarn:1   dfail:0   fail:0   skip:38  
time:490s
fi-cfl-s total:241  pass:188  dwarn:24  dfail:0   fail:0   skip:28 
fi-elk-e7500 total:289  pass:230  dwarn:0   dfail:0   fail:0   skip:59  
time:411s
fi-glk-1 total:289  pass:259  dwarn:1   dfail:0   fail:0   skip:29  
time:564s
fi-hsw-4770  total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:425s
fi-hsw-4770r total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:403s
fi-ilk-650   total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:429s
fi-ivb-3520m total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:482s
fi-ivb-3770  total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:466s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:469s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:578s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:594s
fi-pnv-d510  total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:545s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:448s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:749s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:490s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:477s
fi-snb-2520m total:289  pass:251  dwarn:0   dfail:0   fail:0   skip:38  
time:563s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:1   skip:39  
time:417s

bf6ecf6d25c1c45e576643b7d7a65e8b1e6b4f01 drm-tip: 2017y-09m-19d-17h-23m-04s UTC 
integration manifest
90a2854704de drm/i915: adjust get_crtc_fence_y_offset() to use base.y instead 
of crtc.y
1d569ba6f52d drm/i915: dspaddr_offset doesn't need to be more than local 
variable
5a876f8f82a2 drm/i915: Unify skylake plane disable
0bac61118182 drm/i915: Unify skylake plane update
0d5bc0782481 drm/i915: move adjusted_x/y from crtc to cache.

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5756/
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 2/2] drm/i915/cnl: Fix SSEU Device Status.

[Rodrigo Vivi]

CNL adds an extra register for slice/subslice information.
Although no SKU is planed with an extra slice let's already
handle this extra piece of information so we don't have the
risk in future of getting a part that might have chosen this
part of the die instead of other slices or anything like that.

Also if subslice is disabled the information of eu ack for that
is garbage, so let's skip checks for eu if subslice is disabled
as we skip the subslice if slice is disabled.

The rest is pretty much like gen9.

v2: Remove IS_CANNONLAKE from gen9 status function.

Cc: Oscar Mateo 
Signed-off-by: Rodrigo Vivi 
Reviewed-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 54 +++--
 drivers/gpu/drm/i915/i915_reg.h |  6 +
 2 files changed, 58 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index ca6fa6d122c6..e86d2be4b815 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4575,6 +4575,54 @@ static void cherryview_sseu_device_status(struct 
drm_i915_private *dev_priv,
}
 }
 
+static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
+struct sseu_dev_info *sseu)
+{
+   const struct intel_device_info *info = INTEL_INFO(dev_priv);
+   int s_max = 4, ss_max = 3;
+   int s, ss;
+   u32 s_reg[s_max], eu_reg[2 * s_max], eu_mask[2];
+
+   for (s = 0; s < s_max; s++) {
+   s_reg[s] = I915_READ(GEN10_SLICE_PGCTL_ACK(s));
+   eu_reg[2 * s] = I915_READ(GEN10_SS01_EU_PGCTL_ACK(s));
+   eu_reg[2 * s + 1] = I915_READ(GEN10_SS23_EU_PGCTL_ACK(s));
+   }
+
+   eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
+GEN9_PGCTL_SSA_EU19_ACK |
+GEN9_PGCTL_SSA_EU210_ACK |
+GEN9_PGCTL_SSA_EU311_ACK;
+   eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
+GEN9_PGCTL_SSB_EU19_ACK |
+GEN9_PGCTL_SSB_EU210_ACK |
+GEN9_PGCTL_SSB_EU311_ACK;
+
+   for (s = 0; s < s_max; s++) {
+   if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
+   /* skip disabled slice */
+   continue;
+
+   sseu->slice_mask |= BIT(s);
+   sseu->subslice_mask = info->sseu.subslice_mask;
+
+   for (ss = 0; ss < ss_max; ss++) {
+   unsigned int eu_cnt;
+
+   if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss
+   /* skip disabled subslice */
+   continue;
+
+   eu_cnt = 2 * hweight32(eu_reg[2 * s + ss / 2] &
+  eu_mask[ss % 2]);
+   sseu->eu_total += eu_cnt;
+   sseu->eu_per_subslice = max_t(unsigned int,
+ sseu->eu_per_subslice,
+ eu_cnt);
+   }
+   }
+}
+
 static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
struct sseu_dev_info *sseu)
 {
@@ -4610,7 +4658,7 @@ static void gen9_sseu_device_status(struct 
drm_i915_private *dev_priv,
 
sseu->slice_mask |= BIT(s);
 
-   if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
+   if (IS_GEN9_BC(dev_priv))
sseu->subslice_mask =
INTEL_INFO(dev_priv)->sseu.subslice_mask;
 
@@ -4716,8 +4764,10 @@ static int i915_sseu_status(struct seq_file *m, void 
*unused)
cherryview_sseu_device_status(dev_priv, );
} else if (IS_BROADWELL(dev_priv)) {
broadwell_sseu_device_status(dev_priv, );
-   } else if (INTEL_GEN(dev_priv) >= 9) {
+   } else if (IS_GEN9(dev_priv)) {
gen9_sseu_device_status(dev_priv, );
+   } else if (INTEL_GEN(dev_priv) >= 10) {
+   gen10_sseu_device_status(dev_priv, );
}
 
intel_runtime_pm_put(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9f4b8faf2982..93b688666419 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8018,11 +8018,17 @@ enum {
 #define   CHV_EU311_PG_ENABLE  (1<<1)
 
 #define GEN9_SLICE_PGCTL_ACK(slice)_MMIO(0x804c + (slice)*0x4)
+#define GEN10_SLICE_PGCTL_ACK(slice)   ((slice) == 3 ? _MMIO(0x8080) : \
+GEN9_SLICE_PGCTL_ACK((slice)))
 #define   GEN9_PGCTL_SLICE_ACK (1 << 0)
 #define   GEN9_PGCTL_SS_ACK(subslice)  (1 << (2 + (subslice)*2))
 
 #define GEN9_SS01_EU_PGCTL_ACK(slice)  _MMIO(0x805c + (slice)*0x8)
+#define GEN10_SS01_EU_PGCTL_ACK(slice) ((slice) == 3 ? _MMIO(0x808c) : \
+  

[Intel-gfx] [PATCH 1/2] drm/i915/cnl: Add support slice/subslice/eu configs

[Rodrigo Vivi]

From: Ben Widawsky 

Cannonlake Slice and Subslice information has changed.

This patch initially provided by Ben adds the proper sseu
initialization.

v2: This v2 done by Rodrigo includes:
- Fix on Total slices count by avoiding [1][2] and [2][2].
- Inclusion of EU Per Subslice.
- Commit message.
v3: This v3 done by Rodrigo includes:
- Handle all possible bits and extra fuse register.
- Use INTEL_GEN macro.
- Fully assume uniform distribution so remove union
  with eu_per_subslice and add proper the comment.
v4: This v4 done by Rodrigo includes:
- Consider all bits available: 6 bits for slices [27:22]
  and 4 for subslices [21:18].

Cc: Oscar Mateo 
Signed-off-by: Ben Widawsky 
Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/i915_reg.h  |  8 +++
 drivers/gpu/drm/i915/intel_device_info.c | 37 +++-
 2 files changed, 44 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 94b40a469afd..9f4b8faf2982 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2730,6 +2730,11 @@ enum i915_power_well_id {
 #define   GEN9_F2_SS_DIS_SHIFT 20
 #define   GEN9_F2_SS_DIS_MASK  (0xf << GEN9_F2_SS_DIS_SHIFT)
 
+#define   GEN10_F2_S_ENA_SHIFT 22
+#define   GEN10_F2_S_ENA_MASK  (0x3f << GEN10_F2_S_ENA_SHIFT)
+#define   GEN10_F2_SS_DIS_SHIFT18
+#define   GEN10_F2_SS_DIS_MASK (0xf << GEN10_F2_SS_DIS_SHIFT)
+
 #define GEN8_EU_DISABLE0   _MMIO(0x9134)
 #define   GEN8_EU_DIS0_S0_MASK 0xff
 #define   GEN8_EU_DIS0_S1_SHIFT24
@@ -2745,6 +2750,9 @@ enum i915_power_well_id {
 
 #define GEN9_EU_DISABLE(slice) _MMIO(0x9134 + (slice)*0x4)
 
+#define GEN10_EU_DISABLE3  _MMIO(0x9140)
+#define   GEN10_EU_DIS_SS_MASK 0xff
+
 #define GEN6_BSD_SLEEP_PSMI_CONTROL_MMIO(0x12050)
 #define   GEN6_BSD_SLEEP_MSG_DISABLE   (1 << 0)
 #define   GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c 
b/drivers/gpu/drm/i915/intel_device_info.c
index 43831b09b47a..85693811c1b0 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -82,6 +82,39 @@ void intel_device_info_dump(struct drm_i915_private 
*dev_priv)
 #undef PRINT_FLAG
 }
 
+static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
+{
+   struct sseu_dev_info *sseu = _device_info(dev_priv)->sseu;
+   const u32 fuse2 = I915_READ(GEN8_FUSE2);
+
+   sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>
+   GEN10_F2_S_ENA_SHIFT;
+   sseu->subslice_mask = (1 << 3) - 1;
+   sseu->subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
+GEN10_F2_SS_DIS_SHIFT);
+
+   sseu->eu_total = hweight32(~I915_READ(GEN8_EU_DISABLE0));
+   sseu->eu_total += hweight32(~I915_READ(GEN8_EU_DISABLE1));
+   sseu->eu_total += hweight32(~I915_READ(GEN8_EU_DISABLE2));
+   sseu->eu_total += hweight8(~(I915_READ(GEN10_EU_DISABLE3) &
+GEN10_EU_DIS_SS_MASK));
+
+   /*
+* CNL is expected to always have a uniform distribution
+* of EU across subslices with the exception that any one
+* EU in any one subslice may be fused off for die
+* recovery.
+*/
+   sseu->eu_per_subslice = sseu_subslice_total(sseu) ?
+   DIV_ROUND_UP(sseu->eu_total,
+sseu_subslice_total(sseu)) : 0;
+
+   /* No restrictions on Power Gating */
+   sseu->has_slice_pg = 1;
+   sseu->has_subslice_pg = 1;
+   sseu->has_eu_pg = 1;
+}
+
 static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
 {
struct sseu_dev_info *sseu = _device_info(dev_priv)->sseu;
@@ -409,8 +442,10 @@ void intel_device_info_runtime_init(struct 
drm_i915_private *dev_priv)
cherryview_sseu_info_init(dev_priv);
else if (IS_BROADWELL(dev_priv))
broadwell_sseu_info_init(dev_priv);
-   else if (INTEL_INFO(dev_priv)->gen >= 9)
+   else if (INTEL_GEN(dev_priv) == 9)
gen9_sseu_info_init(dev_priv);
+   else if (INTEL_GEN(dev_priv) >= 10)
+   gen10_sseu_info_init(dev_priv);
 
DRM_DEBUG_DRIVER("slice mask: %04x\n", info->sseu.slice_mask);
DRM_DEBUG_DRIVER("slice total: %u\n", hweight8(info->sseu.slice_mask));
-- 
2.13.5

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[Intel-gfx] ✓ Fi.CI.IGT: success for i915 PMU and engine busy stats (rev10)

[Patchwork]

== Series Details ==

Series: i915 PMU and engine busy stats (rev10)
URL   : https://patchwork.freedesktop.org/series/27488/
State : success

== Summary ==

Test kms_flip:
Subgroup rcs-wf_vblank-vs-dpms:
dmesg-warn -> PASS   (shard-hsw)
Test perf:
Subgroup polling:
fail   -> PASS   (shard-hsw) fdo#102252 +1

fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-hswtotal:2317 pass:1245 dwarn:3   dfail:0   fail:12  skip:1057 
time:9592s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5747/shards.html
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Re: [Intel-gfx] [PATCH v4 1/3] drm/i915/gvt: Add gvt_debug in i915_params for GVT-g log classification

[Zhenyu Wang]

On 2017.09.19 18:17:04 +0800, Shuo Liu wrote:
> On Tue 19.Sep'17 at 10:22:16 +0100, Chris Wilson wrote:
> > Quoting Shuo Liu (2017-09-19 08:54:43)
> > > Signed-off-by: Shuo Liu 
> > > ---
> > >  drivers/gpu/drm/i915/i915_params.c | 13 +
> > >  drivers/gpu/drm/i915/i915_params.h |  1 +
> > >  2 files changed, 14 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_params.c 
> > > b/drivers/gpu/drm/i915/i915_params.c
> > > index 8ab003d..ceeae1d 100644
> > > --- a/drivers/gpu/drm/i915/i915_params.c
> > > +++ b/drivers/gpu/drm/i915/i915_params.c
> > > @@ -65,6 +65,7 @@ struct i915_params i915 __read_mostly = {
> > > .inject_load_failure = 0,
> > > .enable_dpcd_backlight = false,
> > > .enable_gvt = false,
> > > +   .debug_gvt = 0,
> > >  };
> > > 
> > >  module_param_named(modeset, i915.modeset, int, 0400);
> > > @@ -257,3 +258,15 @@ struct i915_params i915 __read_mostly = {
> > >  module_param_named(enable_gvt, i915.enable_gvt, bool, 0400);
> > >  MODULE_PARM_DESC(enable_gvt,
> > > "Enable support for Intel GVT-g graphics virtualization host 
> > > support(default:false)");
> > > +
> > > +module_param_named(debug_gvt, i915.debug_gvt, int, 0600);
> > > +MODULE_PARM_DESC(debug_gvt, "Enable GVT-g debug output, where each bit 
> > > enables a category.\n"
> > > +   "Bit 0 (0x01) will enable CORE messages (GVT-g 
> > > core message)\n"
> > > +   "Bit 1 (0x02) will enable IRQ messages (GVT-g 
> > > interrupt message)\n"
> > > +   "Bit 2 (0x04) will enable MM messages (GVT-g 
> > > memory management message)\n"
> > > +   "Bit 3 (0x08) will enable MMIO messages (GVT-g 
> > > MMIO message)\n"
> > > +   "Bit 4 (0x10) will enable DPY messages (GVT-g 
> > > display message)\n"
> > > +   "Bit 5 (0x20) will enable EL messages (GVT-g 
> > > execlist message)\n"
> > > +   "Bit 6 (0x40) will enable SCHED messages (GVT-g 
> > > schedule message)\n"
> > > +   "Bit 7 (0x80) will enable RENDER messages (GVT-g 
> > > render message)\n"
> > > +   "Bit 8 (0x100) will enable CMD messages (GVT-g 
> > > command message)");
> > > diff --git a/drivers/gpu/drm/i915/i915_params.h 
> > > b/drivers/gpu/drm/i915/i915_params.h
> > > index ac84470..cd29c78 100644
> > > --- a/drivers/gpu/drm/i915/i915_params.h
> > > +++ b/drivers/gpu/drm/i915/i915_params.h
> > > @@ -54,6 +54,7 @@
> > > func(int, edp_vswing); \
> > > func(int, reset); \
> > > func(unsigned int, inject_load_failure); \
> > > +   func(int, debug_gvt); \
> > > /* leave bools at the end to not create holes */ \
> > > func(bool, alpha_support); \
> > > func(bool, enable_cmd_parser); \
> > 
> > Note that you are not forced to use i915_params. If you have gvt only
> > module options that you don't want exposed outside of gvt, just create
> > them within gvt.
> Have talked this with Zhenyu, his suggestion is put params together as
> gvt is in i915 module.

As gvt is in i915 module now, so I think better to put all the params
in one place instead of any surprise.

> > 
> > Having said that, I would strongly advise against having module options,
> > and I would advise you to go the dyndebug route instead of copying a
> > rectangular wheel.
> Thanks Chris. dyndebug might be an option. The disadvantage of dyndebug
> is complicated to use, expecially in bootup debugging (add a long
> cmdline to enable interesting messages). Module option is
> straightforward. Zhenyu, any comments on this?
> 

yeah, I think moving to dyndebug is better than module option and boot debug
shouldn't be that hard right? as we're mostly with file seperation for different
function unit.

-- 
Open Source Technology Center, Intel ltd.

$gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827


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[Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [v6,1/3] drm/i915: Rename global i915 to i915_modparams

[Patchwork]

== Series Details ==

Series: series starting with [v6,1/3] drm/i915: Rename global i915 to 
i915_modparams
URL   : https://patchwork.freedesktop.org/series/30621/
State : warning

== Summary ==

Series 30621v1 series starting with [v6,1/3] drm/i915: Rename global i915 to 
i915_modparams
https://patchwork.freedesktop.org/api/1.0/series/30621/revisions/1/mbox/

Test gem_exec_flush:
Subgroup basic-wb-set-default:
pass   -> DMESG-WARN (fi-kbl-7500u)
Test gem_exec_store:
Subgroup basic-all:
pass   -> DMESG-WARN (fi-kbl-7500u) fdo#102849
Test gem_exec_suspend:
Subgroup basic-s3:
pass   -> INCOMPLETE (fi-kbl-7500u) fdo#102850
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
pass   -> FAIL   (fi-snb-2600) fdo#100215
Test kms_pipe_crc_basic:
Subgroup hang-read-crc-pipe-b:
incomplete -> DMESG-WARN (fi-cfl-s) fdo#102294

fdo#102849 https://bugs.freedesktop.org/show_bug.cgi?id=102849
fdo#102850 https://bugs.freedesktop.org/show_bug.cgi?id=102850
fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#102294 https://bugs.freedesktop.org/show_bug.cgi?id=102294

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:441s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:473s
fi-blb-e6850 total:289  pass:224  dwarn:1   dfail:0   fail:0   skip:64  
time:420s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:516s
fi-bwr-2160  total:289  pass:184  dwarn:0   dfail:0   fail:0   skip:105 
time:278s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:502s
fi-byt-j1900 total:289  pass:254  dwarn:1   dfail:0   fail:0   skip:34  
time:490s
fi-byt-n2820 total:289  pass:250  dwarn:1   dfail:0   fail:0   skip:38  
time:492s
fi-cfl-s total:289  pass:223  dwarn:34  dfail:0   fail:0   skip:32  
time:538s
fi-elk-e7500 total:289  pass:230  dwarn:0   dfail:0   fail:0   skip:59  
time:417s
fi-glk-1 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:563s
fi-hsw-4770  total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:424s
fi-hsw-4770r total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:405s
fi-ilk-650   total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:428s
fi-ivb-3520m total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:477s
fi-ivb-3770  total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:462s
fi-kbl-7500u total:118  pass:98   dwarn:3   dfail:0   fail:0   skip:16 
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:572s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:585s
fi-pnv-d510  total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:544s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:456s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:752s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:484s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:468s
fi-snb-2520m total:289  pass:251  dwarn:0   dfail:0   fail:0   skip:38  
time:569s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:1   skip:39  
time:421s

bf6ecf6d25c1c45e576643b7d7a65e8b1e6b4f01 drm-tip: 2017y-09m-19d-17h-23m-04s UTC 
integration manifest
2187f151c6b7 drm/i915: Make i915_modparams members const
4e7790c6d8bb drm/i915: Prepare error capture to work with const modparams
0bea9f1ba391 drm/i915: Rename global i915 to i915_modparams

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5755/
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Re: [Intel-gfx] [PATCH 1/2] drm/i915/cnl: Add support slice/subslice/eu configs

[Oscar Mateo]

On 09/18/2017 11:49 AM, Rodrigo Vivi wrote:

From: Ben Widawsky 

Cannonlake Slice and Subslice information has changed.

This patch initially provided by Ben adds the proper sseu
initialization.

v2: This v2 done by Rodrigo includes:
 - Fix on Total slices count by avoiding [1][2] and [2][2].
 - Inclusion of EU Per Subslice.
 - Commit message.
v3: This v3 done by Rodrigo includes:
 - Handle all possible bits and extra fuse register.
 - Use INTEL_GEN macro.
 - Fully assume uniform distribution so remove union
   with eu_per_subslice and add proper the comment.

Cc: Oscar Mateo 
Signed-off-by: Ben Widawsky 
Signed-off-by: Rodrigo Vivi 
---
  drivers/gpu/drm/i915/i915_reg.h  |  8 +++
  drivers/gpu/drm/i915/intel_device_info.c | 37 +++-
  2 files changed, 44 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 94b40a469afd..4db5deddfb9f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2730,6 +2730,11 @@ enum i915_power_well_id {
  #define   GEN9_F2_SS_DIS_SHIFT20
  #define   GEN9_F2_SS_DIS_MASK (0xf << GEN9_F2_SS_DIS_SHIFT)
  
+#define   GEN10_F2_S_ENA_SHIFT		22

+#define   GEN10_F2_S_ENA_MASK  (0xf << GEN10_F2_S_ENA_SHIFT)
+#define   GEN10_F2_SS_DIS_SHIFT18
+#define   GEN10_F2_SS_DIS_MASK (0x7 << GEN10_F2_SS_DIS_SHIFT)
+
  #define GEN8_EU_DISABLE0  _MMIO(0x9134)
  #define   GEN8_EU_DIS0_S0_MASK0xff
  #define   GEN8_EU_DIS0_S1_SHIFT   24
@@ -2745,6 +2750,9 @@ enum i915_power_well_id {
  
  #define GEN9_EU_DISABLE(slice)		_MMIO(0x9134 + (slice)*0x4)
  
+#define GEN10_EU_DISABLE3		_MMIO(0x9140)

+#define   GEN10_EU_DIS_SS_MASK 0xff
+
  #define GEN6_BSD_SLEEP_PSMI_CONTROL   _MMIO(0x12050)
  #define   GEN6_BSD_SLEEP_MSG_DISABLE  (1 << 0)
  #define   GEN6_BSD_SLEEP_FLUSH_DISABLE(1 << 2)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c 
b/drivers/gpu/drm/i915/intel_device_info.c
index 43831b09b47a..85693811c1b0 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -82,6 +82,39 @@ void intel_device_info_dump(struct drm_i915_private 
*dev_priv)
  #undef PRINT_FLAG
  }
  
+static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)

+{
+   struct sseu_dev_info *sseu = _device_info(dev_priv)->sseu;
+   const u32 fuse2 = I915_READ(GEN8_FUSE2);
+
+   sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>
+   GEN10_F2_S_ENA_SHIFT;
+   sseu->subslice_mask = (1 << 3) - 1;
+   sseu->subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
+GEN10_F2_SS_DIS_SHIFT);
+
+   sseu->eu_total = hweight32(~I915_READ(GEN8_EU_DISABLE0));
+   sseu->eu_total += hweight32(~I915_READ(GEN8_EU_DISABLE1));
+   sseu->eu_total += hweight32(~I915_READ(GEN8_EU_DISABLE2));
+   sseu->eu_total += hweight8(~(I915_READ(GEN10_EU_DISABLE3) &
+GEN10_EU_DIS_SS_MASK));


This looks better than before, but since we are only reading 4 bits for 
the slice mask (GEN10_F2_S_ENA_MASK = 0xf), why do we bother with slices 
4 and 5 for the EU count?



+   /*
+* CNL is expected to always have a uniform distribution
+* of EU across subslices with the exception that any one
+* EU in any one subslice may be fused off for die
+* recovery.
+*/
+   sseu->eu_per_subslice = sseu_subslice_total(sseu) ?
+   DIV_ROUND_UP(sseu->eu_total,
+sseu_subslice_total(sseu)) : 0;
+
+   /* No restrictions on Power Gating */
+   sseu->has_slice_pg = 1;
+   sseu->has_subslice_pg = 1;
+   sseu->has_eu_pg = 1;
+}
+
  static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
  {
struct sseu_dev_info *sseu = _device_info(dev_priv)->sseu;
@@ -409,8 +442,10 @@ void intel_device_info_runtime_init(struct 
drm_i915_private *dev_priv)
cherryview_sseu_info_init(dev_priv);
else if (IS_BROADWELL(dev_priv))
broadwell_sseu_info_init(dev_priv);
-   else if (INTEL_INFO(dev_priv)->gen >= 9)
+   else if (INTEL_GEN(dev_priv) == 9)
gen9_sseu_info_init(dev_priv);
+   else if (INTEL_GEN(dev_priv) >= 10)
+   gen10_sseu_info_init(dev_priv);
  
  	DRM_DEBUG_DRIVER("slice mask: %04x\n", info->sseu.slice_mask);

DRM_DEBUG_DRIVER("slice total: %u\n", hweight8(info->sseu.slice_mask));


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Re: [Intel-gfx] [PATCH 2/2] drm/i915/cnl: Fix SSEU Device Status.

[Oscar Mateo]

On 09/18/2017 11:49 AM, Rodrigo Vivi wrote:

CNL adds an extra register for slice/subslice information.
Although no SKU is planed with an extra slice let's already
handle this extra piece of information so we don't have the
risk in future of getting a part that might have chosen this
part of the die instead of other slices or anything like that.

Also if subslice is disabled the information of eu ack for that
is garbage, so let's skip checks for eu if subslice is disabled
as we skip the subslice if slice is disabled.

The rest is pretty much like gen9.

Cc: Oscar Mateo 
Signed-off-by: Rodrigo Vivi 
---
  drivers/gpu/drm/i915/i915_debugfs.c | 52 -
  drivers/gpu/drm/i915/i915_reg.h |  6 +
  2 files changed, 57 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index ca6fa6d122c6..3bf9304baf33 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4575,6 +4575,54 @@ static void cherryview_sseu_device_status(struct 
drm_i915_private *dev_priv,
}
  }
  
+static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,

+struct sseu_dev_info *sseu)
+{
+   const struct intel_device_info *info = INTEL_INFO(dev_priv);
+   int s_max = 4, ss_max = 3;
+   int s, ss;
+   u32 s_reg[s_max], eu_reg[2 * s_max], eu_mask[2];
+
+   for (s = 0; s < s_max; s++) {
+   s_reg[s] = I915_READ(GEN10_SLICE_PGCTL_ACK(s));
+   eu_reg[2 * s] = I915_READ(GEN10_SS01_EU_PGCTL_ACK(s));
+   eu_reg[2 * s + 1] = I915_READ(GEN10_SS23_EU_PGCTL_ACK(s));
+   }
+
+   eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
+GEN9_PGCTL_SSA_EU19_ACK |
+GEN9_PGCTL_SSA_EU210_ACK |
+GEN9_PGCTL_SSA_EU311_ACK;
+   eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
+GEN9_PGCTL_SSB_EU19_ACK |
+GEN9_PGCTL_SSB_EU210_ACK |
+GEN9_PGCTL_SSB_EU311_ACK;
+
+   for (s = 0; s < s_max; s++) {
+   if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
+   /* skip disabled slice */
+   continue;
+
+   sseu->slice_mask |= BIT(s);
+   sseu->subslice_mask = info->sseu.subslice_mask;
+
+   for (ss = 0; ss < ss_max; ss++) {
+   unsigned int eu_cnt;
+
+   if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss
+   /* skip disabled subslice */
+   continue;
+
+   eu_cnt = 2 * hweight32(eu_reg[2 * s + ss / 2] &
+  eu_mask[ss % 2]);
+   sseu->eu_total += eu_cnt;
+   sseu->eu_per_subslice = max_t(unsigned int,
+ sseu->eu_per_subslice,
+ eu_cnt);
+   }
+   }
+}
+
  static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
struct sseu_dev_info *sseu)
  {
@@ -4716,8 +4764,10 @@ static int i915_sseu_status(struct seq_file *m, void 
*unused)
cherryview_sseu_device_status(dev_priv, );
} else if (IS_BROADWELL(dev_priv)) {
broadwell_sseu_device_status(dev_priv, );
-   } else if (INTEL_GEN(dev_priv) >= 9) {
+   } else if (IS_GEN9(dev_priv)) {
gen9_sseu_device_status(dev_priv, );
+   } else if (INTEL_GEN(dev_priv) >= 10) {
+   gen10_sseu_device_status(dev_priv, );
}
  
  	intel_runtime_pm_put(dev_priv);

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4db5deddfb9f..a8cb9c17e6df 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8018,11 +8018,17 @@ enum {
  #define   CHV_EU311_PG_ENABLE (1<<1)
  
  #define GEN9_SLICE_PGCTL_ACK(slice)	_MMIO(0x804c + (slice)*0x4)

+#define GEN10_SLICE_PGCTL_ACK(slice)   ((slice) == 3 ? _MMIO(0x8080) : \
+GEN9_SLICE_PGCTL_ACK((slice)))
  #define   GEN9_PGCTL_SLICE_ACK(1 << 0)
  #define   GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice)*2))
  
  #define GEN9_SS01_EU_PGCTL_ACK(slice)	_MMIO(0x805c + (slice)*0x8)

+#define GEN10_SS01_EU_PGCTL_ACK(slice) ((slice) == 3 ? _MMIO(0x808c) : \
+GEN9_SS01_EU_PGCTL_ACK((slice)))
  #define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice)*0x8)
+#define GEN10_SS23_EU_PGCTL_ACK(slice) ((slice) == 3 ? _MMIO(0x8090) : \
+GEN9_SS23_EU_PGCTL_ACK((slice)))
  #define   GEN9_PGCTL_SSA_EU08_ACK (1 << 0)
  #define   GEN9_PGCTL_SSA_EU19_ACK (1 << 2)
  #define   GEN9_PGCTL_SSA_EU210_ACK(1 << 

Re: [Intel-gfx] [PATCH 02/14] drm/i915: Create intel_uc_init_mmio to initialize MMIO interface prior to uc init

[Michal Wajdeczko]

On Tue, 19 Sep 2017 19:27:39 +0200, Sagar Arun Kamble  
 wrote:



This patch adds new function intel_uc_init_mmio which will initialize
MMIO access related variables prior to uc load/init.

v2: Removed unnecessary export of guc_send_init_regs. Created
intel_uc_init_mmio that currently wraps guc_init_send_regs. (Michal)

Cc: Michal Wajdeczko 
Cc: Michał Winiarski 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/i915_drv.c | 2 ++
 drivers/gpu/drm/i915/intel_uc.c | 7 +--
 drivers/gpu/drm/i915/intel_uc.h | 1 +
 3 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c  
b/drivers/gpu/drm/i915/i915_drv.c

index 5c111ea..ef4f84d 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1002,6 +1002,8 @@ static int i915_driver_init_mmio(struct  
drm_i915_private *dev_priv)

intel_uncore_init(dev_priv);
+   intel_uc_init_mmio(dev_priv);
+
ret = intel_engines_init_mmio(dev_priv);
if (ret)
goto err_uncore;
diff --git a/drivers/gpu/drm/i915/intel_uc.c  
b/drivers/gpu/drm/i915/intel_uc.c

index b91f848..f2ccb7c 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -288,6 +288,11 @@ static void guc_init_send_regs(struct intel_guc  
*guc)

guc->send_regs.fw_domains = fw_domains;
 }
+void intel_uc_init_mmio(struct drm_i915_private *dev_priv)
+{
+   guc_init_send_regs(_priv->guc);
+}
+
 static void guc_capture_load_err_log(struct intel_guc *guc)
 {
if (!guc->log.vma || i915.guc_log_level < 0)
@@ -309,8 +314,6 @@ static int guc_enable_communication(struct intel_guc  
*guc)

 {
struct drm_i915_private *dev_priv = guc_to_i915(guc);
-   guc_init_send_regs(guc);
-
if (HAS_GUC_CT(dev_priv))
return intel_guc_enable_ct(guc);
diff --git a/drivers/gpu/drm/i915/intel_uc.h  
b/drivers/gpu/drm/i915/intel_uc.h

index 8560a7e..60bf814 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -206,6 +206,7 @@ struct intel_huc {
 void intel_uc_init_early(struct drm_i915_private *dev_priv);
 void intel_uc_init_fw(struct drm_i915_private *dev_priv);
 void intel_uc_fini_fw(struct drm_i915_private *dev_priv);
+void intel_uc_init_mmio(struct drm_i915_private *dev_priv);


As init_mmio() is called prior to init_fw() please try to keep
the same order in their declarations.

Michal


 int intel_uc_init_hw(struct drm_i915_private *dev_priv);
 void intel_uc_fini_hw(struct drm_i915_private *dev_priv);
 int intel_guc_sample_forcewake(struct intel_guc *guc);

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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with drm/i915/cnp: Display Wa #1179: WaHardHangonHotPlug (rev3)

[Patchwork]

== Series Details ==

Series: series starting with drm/i915/cnp: Display Wa #1179: 
WaHardHangonHotPlug (rev3)
URL   : https://patchwork.freedesktop.org/series/30067/
State : failure

== Summary ==

  CHK include/config/kernel.release
  CHK include/generated/uapi/linux/version.h
  CHK include/generated/utsrelease.h
  CHK include/generated/bounds.h
  CHK include/generated/timeconst.h
  CHK include/generated/asm-offsets.h
  CALLscripts/checksyscalls.sh
  CHK scripts/mod/devicetable-offsets.h
  CHK include/generated/compile.h
  CHK kernel/config_data.h
  CC [M]  drivers/gpu/drm/i915/i915_drv.o
In file included from drivers/gpu/drm/i915/i915_drv.h:55:0,
 from drivers/gpu/drm/i915/i915_drv.c:49:
drivers/gpu/drm/i915/i915_reg.h:7480:0: error: "CHASSIS_CLK_REQ_DURATION_MASK" 
redefined [-Werror]
 #define  CHASSIS_CLK_REQ_DURATION_MASK (0xf<<8)
 
drivers/gpu/drm/i915/i915_reg.h:7474:0: note: this is the location of the 
previous definition
 #define  CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8)
 
drivers/gpu/drm/i915/i915_reg.h:7481:0: error: "CHASSIS_CLK_REQ_DURATION" 
redefined [-Werror]
 #define  CHASSIS_CLK_REQ_DURATION(x) ((x)<<8)
 
drivers/gpu/drm/i915/i915_reg.h:7475:0: note: this is the location of the 
previous definition
 #define  CHASSIS_CLK_REQ_DURATION(x) ((x) << 8)
 
cc1: all warnings being treated as errors
scripts/Makefile.build:311: recipe for target 'drivers/gpu/drm/i915/i915_drv.o' 
failed
make[4]: *** [drivers/gpu/drm/i915/i915_drv.o] Error 1
scripts/Makefile.build:570: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:570: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:570: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1019: recipe for target 'drivers' failed
make: *** [drivers] Error 2

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[Intel-gfx] ✓ Fi.CI.BAT: success for GuC code restructuring and fixes (rev3)

[Patchwork]

== Series Details ==

Series: GuC code restructuring and fixes (rev3)
URL   : https://patchwork.freedesktop.org/series/30351/
State : success

== Summary ==

Series 30351v3 GuC code restructuring and fixes
https://patchwork.freedesktop.org/api/1.0/series/30351/revisions/3/mbox/

Test kms_frontbuffer_tracking:
Subgroup basic:
dmesg-warn -> PASS   (fi-kbl-7500u)
Test kms_pipe_crc_basic:
Subgroup hang-read-crc-pipe-b:
incomplete -> DMESG-WARN (fi-cfl-s) fdo#102294 +1
Subgroup suspend-read-crc-pipe-a:
incomplete -> PASS   (fi-kbl-7500u)
Test drv_module_reload:
Subgroup basic-reload:
pass   -> DMESG-WARN (fi-glk-1) fdo#102777

fdo#102294 https://bugs.freedesktop.org/show_bug.cgi?id=102294
fdo#102777 https://bugs.freedesktop.org/show_bug.cgi?id=102777

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:439s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:472s
fi-blb-e6850 total:289  pass:224  dwarn:1   dfail:0   fail:0   skip:64  
time:415s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:512s
fi-bwr-2160  total:289  pass:184  dwarn:0   dfail:0   fail:0   skip:105 
time:278s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:498s
fi-byt-j1900 total:289  pass:254  dwarn:1   dfail:0   fail:0   skip:34  
time:488s
fi-byt-n2820 total:289  pass:250  dwarn:1   dfail:0   fail:0   skip:38  
time:497s
fi-cfl-s total:245  pass:188  dwarn:26  dfail:0   fail:0   skip:30 
fi-elk-e7500 total:289  pass:230  dwarn:0   dfail:0   fail:0   skip:59  
time:416s
fi-glk-1 total:289  pass:259  dwarn:1   dfail:0   fail:0   skip:29  
time:568s
fi-hsw-4770  total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:423s
fi-hsw-4770r total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:403s
fi-ilk-650   total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:430s
fi-ivb-3520m total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:480s
fi-ivb-3770  total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:468s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:467s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:575s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:583s
fi-pnv-d510  total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:546s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:452s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:750s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:489s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:469s
fi-snb-2520m total:289  pass:251  dwarn:0   dfail:0   fail:0   skip:38  
time:569s
fi-snb-2600  total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:422s

bf6ecf6d25c1c45e576643b7d7a65e8b1e6b4f01 drm-tip: 2017y-09m-19d-17h-23m-04s UTC 
integration manifest
a6f7a1534535 drm/i915: Reorganize HuC authentication
427e3bf35bdb drm/i915/guc: Enable default/critical logging in GuC by default 
from GuC v9
b7626345d6b6 drm/i915/guc: Remove i915_guc_log_unregister
d9376dd928c1 drm/i915/guc: Fix GuC cleanup in unload path
202d501afe14 drm/i915/guc: Reuse GuC suspend functionality in reset path
9c6b660e184f drm/i915/guc: Update suspend functionality in intel_uc_suspend path
c4218b4ff8aa drm/i915/guc: Update GuC ggtt.invalidate/interrupts/communication 
across RPM suspend/resume
c7db4b2debc1 drm/i915/guc: Update prototype/name of GuC suspend/resume fns and 
move to intel_guc.c
e5cc64cd4532 drm/i915: Create uc runtime and system suspend/resume helpers
2f5030791f7f drm/i915/guc: Move GuC specific functionality from intel_uc.c to 
intel_guc.c
c22d27f3b0a0 drm/i915: Create intel_guc.h, intel_huc.h and intel_uc_common.h
83e0c1e93c4b drm/i915/guc: Create intel_guc_init_early
46df37fea2a0 drm/i915: Create intel_uc_init_mmio to initialize MMIO interface 
prior to uc init
48c6aa4afa19 drm/i915/guc: Pass intel_guc struct as parameter to 
intel_guc_wopcm_size

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5753/
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Re: [Intel-gfx] [PATCH 01/14] drm/i915/guc: Pass intel_guc struct as parameter to intel_guc_wopcm_size

[Michal Wajdeczko]

On Tue, 19 Sep 2017 19:27:38 +0200, Sagar Arun Kamble  
 wrote:



Pass intel_guc struct as parameter to intel_guc_wopcm_size instead of
drm_i915_private. intel_guc_suspend/resume parameters are not updated in
this patch as those functions are updated in the upcoming patches.



hmm, missing answer to the "why" question.


Cc: Michal Wajdeczko 
Cc: Michał Winiarski 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/intel_guc_loader.c | 3 ++-
 drivers/gpu/drm/i915/intel_uc.c | 4 ++--
 drivers/gpu/drm/i915/intel_uc.h | 2 +-
 3 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c  
b/drivers/gpu/drm/i915/intel_guc_loader.c

index 8b0ae7f..6ee7c16 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -250,8 +250,9 @@ static int guc_ucode_xfer_dma(struct  
drm_i915_private *dev_priv,

return ret;
 }
-u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv)
+u32 intel_guc_wopcm_size(struct intel_guc *guc)


Maybe better option would be to convert this function into inline
as it is used only in uc.c file.

Michal


 {
+   struct drm_i915_private *dev_priv = guc_to_i915(guc);
u32 wopcm_size = GUC_WOPCM_TOP;
/* On BXT, the top of WOPCM is reserved for RC6 context */
diff --git a/drivers/gpu/drm/i915/intel_uc.c  
b/drivers/gpu/drm/i915/intel_uc.c

index 0178ba4..b91f848 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -188,7 +188,7 @@ static void fetch_uc_fw(struct drm_i915_private  
*dev_priv,

size = uc_fw->header_size + uc_fw->ucode_size;
/* Top 32k of WOPCM is reserved (8K stack + 24k RC6 context). */
-   if (size > intel_guc_wopcm_size(dev_priv)) {
+   if (size > intel_guc_wopcm_size(_priv->guc)) {
DRM_ERROR("Firmware is too large to fit in WOPCM\n");
goto fail;
}
@@ -353,7 +353,7 @@ int intel_uc_init_hw(struct drm_i915_private  
*dev_priv)

}
/* init WOPCM */
-   I915_WRITE(GUC_WOPCM_SIZE, intel_guc_wopcm_size(dev_priv));
+   I915_WRITE(GUC_WOPCM_SIZE, intel_guc_wopcm_size(guc));
I915_WRITE(DMA_GUC_WOPCM_OFFSET,
   GUC_WOPCM_OFFSET_VALUE | HUC_LOADING_AGENT_GUC);
diff --git a/drivers/gpu/drm/i915/intel_uc.h  
b/drivers/gpu/drm/i915/intel_uc.h

index 7703c9a..8560a7e 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -227,7 +227,7 @@ static inline void intel_guc_notify(struct intel_guc  
*guc)

 int intel_guc_init_hw(struct intel_guc *guc);
 int intel_guc_suspend(struct drm_i915_private *dev_priv);
 int intel_guc_resume(struct drm_i915_private *dev_priv);
-u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv);
+u32 intel_guc_wopcm_size(struct intel_guc *guc);
/* i915_guc_submission.c */
 int i915_guc_submission_init(struct drm_i915_private *dev_priv);

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Re: [Intel-gfx] [PATCH 00/14] GuC code restructuring and fixes

[Michal Wajdeczko]

On Tue, 19 Sep 2017 19:27:37 +0200, Sagar Arun Kamble  
 wrote:


This series is based on reviews from  
https://patchwork.freedesktop.org/series/30502/.


Cc: Michal Wajdeczko 
Cc: Michał Winiarski 

Sagar Arun Kamble (14):
  drm/i915/guc: Pass intel_guc struct as parameter to
intel_guc_wopcm_size
  drm/i915: Create intel_uc_init_mmio to initialize MMIO interface prior
to uc init
  drm/i915/guc: Create intel_guc_init_early
  drm/i915: Create intel_guc.h, intel_huc.h and intel_uc_common.h
  drm/i915/guc: Move GuC specific functionality from intel_uc.c to
intel_guc.c
  drm/i915: Create uc runtime and system suspend/resume helpers
  drm/i915/guc: Update prototype/name of GuC suspend/resume fns and move
to intel_guc.c
  drm/i915/guc: Update GuC ggtt.invalidate/interrupts/communication
across RPM suspend/resume
  drm/i915/guc: Update suspend functionality in intel_uc_suspend path
  drm/i915/guc: Reuse GuC suspend functionality in reset path
  drm/i915/guc: Fix GuC cleanup in unload path
  drm/i915/guc: Remove i915_guc_log_unregister
  drm/i915/guc: Enable default/critical logging in GuC by default from
GuC v9
  drm/i915: Reorganize HuC authentication



Refactoring whole guc code in one series can be very long task.
By adding more and more fixes here you're preventing merge of the
most important patch.

Michal


 drivers/gpu/drm/i915/Makefile  |   1 +
 drivers/gpu/drm/i915/i915_drv.c|  28 +++-
 drivers/gpu/drm/i915/i915_gem.c|   9 +-
 drivers/gpu/drm/i915/i915_guc_submission.c |  54 +--
 drivers/gpu/drm/i915/intel_guc.c   | 246  
+

 drivers/gpu/drm/i915/intel_guc.h   | 185 ++
 drivers/gpu/drm/i915/intel_guc_fwif.h  |   4 +-
 drivers/gpu/drm/i915/intel_guc_loader.c|   3 +-
 drivers/gpu/drm/i915/intel_guc_log.c   |  25 ++-
 drivers/gpu/drm/i915/intel_huc.c   |  22 +--
 drivers/gpu/drm/i915/intel_huc.h   |  41 +
 drivers/gpu/drm/i915/intel_uc.c| 165 ++-
 drivers/gpu/drm/i915/intel_uc.h| 205  
++--

 drivers/gpu/drm/i915/intel_uc_common.h |  67 
 14 files changed, 653 insertions(+), 402 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_guc.c
 create mode 100644 drivers/gpu/drm/i915/intel_guc.h
 create mode 100644 drivers/gpu/drm/i915/intel_huc.h
 create mode 100644 drivers/gpu/drm/i915/intel_uc_common.h

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Re: [Intel-gfx] [RFC 10/11] drm/i915: Export engine stats API to other users

[Rogozhkin, Dmitry V]

On Tue, 2017-09-19 at 12:50 -0700, Ben Widawsky wrote:
> On 17-09-15 10:49:56, Tvrtko Ursulin wrote:
> >
> >On 14/09/2017 21:26, Chris Wilson wrote:
> >>Quoting Tvrtko Ursulin (2017-09-11 16:25:58)
> >>>From: Tvrtko Ursulin 
> >>>
> >>>Other kernel users might want to look at total GPU busyness
> >>>in order to implement things like package power distribution
> >>>algorithms more efficiently.
> >>
> >>Who are we exporting these symbols to? Will you not need all the module
> >>ref handling and load ordering like around ips and audio?
> >
> >Hm yes indeed, I forgot about that.
> >
> >Perhaps Ben could comment on who is the user. If it is purely for 
> >internal explorations, I'll stick the patch at the end of the series 
> >as it is. If it has a more serious user I would need to implement a 
> >proper solution.
> >
> >Regards,
> >
> >Tvrtko
> 
> P-state driver was looking to use this as a way to make determinations about 
> how
> much to limit CPU frequency. Srinivas was privy to the original discussion
> 

I personally was surprised to see private API exposed rather than reuse
of PMU API. Do they really need a private path?

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gvt: ensure -ve return value is handled correctly

[Patchwork]

== Series Details ==

Series: drm/i915/gvt: ensure -ve return value is handled correctly
URL   : https://patchwork.freedesktop.org/series/30604/
State : success

== Summary ==

Series 30604v1 drm/i915/gvt: ensure -ve return value is handled correctly
https://patchwork.freedesktop.org/api/1.0/series/30604/revisions/1/mbox/

Test gem_exec_suspend:
Subgroup basic-s3:
pass   -> INCOMPLETE (fi-kbl-7500u) fdo#102850
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
pass   -> FAIL   (fi-snb-2600) fdo#100215
Test kms_pipe_crc_basic:
Subgroup hang-read-crc-pipe-b:
incomplete -> DMESG-WARN (fi-cfl-s) fdo#102294
Test drv_module_reload:
Subgroup basic-reload:
pass   -> DMESG-WARN (fi-glk-1) fdo#102777

fdo#102850 https://bugs.freedesktop.org/show_bug.cgi?id=102850
fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#102294 https://bugs.freedesktop.org/show_bug.cgi?id=102294
fdo#102777 https://bugs.freedesktop.org/show_bug.cgi?id=102777

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:440s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:468s
fi-blb-e6850 total:289  pass:224  dwarn:1   dfail:0   fail:0   skip:64  
time:422s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:514s
fi-bwr-2160  total:289  pass:184  dwarn:0   dfail:0   fail:0   skip:105 
time:279s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:495s
fi-byt-j1900 total:289  pass:254  dwarn:1   dfail:0   fail:0   skip:34  
time:490s
fi-byt-n2820 total:289  pass:250  dwarn:1   dfail:0   fail:0   skip:38  
time:490s
fi-cfl-s total:289  pass:222  dwarn:35  dfail:0   fail:0   skip:32  
time:543s
fi-elk-e7500 total:289  pass:230  dwarn:0   dfail:0   fail:0   skip:59  
time:416s
fi-glk-1 total:289  pass:259  dwarn:1   dfail:0   fail:0   skip:29  
time:567s
fi-hsw-4770  total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:427s
fi-hsw-4770r total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:403s
fi-ilk-650   total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:434s
fi-ivb-3520m total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:490s
fi-ivb-3770  total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:466s
fi-kbl-7500u total:118  pass:100  dwarn:1   dfail:0   fail:0   skip:16 
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:572s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:587s
fi-pnv-d510  total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:542s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:453s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:748s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:490s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:476s
fi-snb-2520m total:289  pass:251  dwarn:0   dfail:0   fail:0   skip:38  
time:572s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:1   skip:39  
time:412s

bf6ecf6d25c1c45e576643b7d7a65e8b1e6b4f01 drm-tip: 2017y-09m-19d-17h-23m-04s UTC 
integration manifest
85130ca1c516 drm/i915/gvt: ensure -ve return value is handled correctly

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5752/
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Re: [Intel-gfx] [PATCH v7] drm/i915/edp: Be less aggressive about changing link config on eDP

[Rodrigo Vivi]

On Fri, Sep 15, 2017 at 06:19:12PM +, Manasi Navare wrote:
> The patch looks good for eDP link training optimizations.
> 
> Reviewed-by: Manasi Navare 

I haven't merged this patch yet because I'd like an Ack from Jani.

Also I'd like to hear from Mika if he believes it is safe or not.

On his revert commit he wrote:
"It has been found out that in some HW combination the DisplayPort
 fast link training feature caused screen flickering. Let's revert
 this feature for now until we can ensure that the feature works for
 all platforms."

I don't want to merge this patch to fix a feature that is disabled
by default with the risk of bringing flickerings back.

But even if we decide to go ahead and merge I believe we need to
resend the test and collect a full round of CI that now runs
all IGT tests.

Thanks,
Rodrigo.


> 
> Manasi
> 
> On Tue, Aug 22, 2017 at 09:34:46AM -0700, Jim Bride wrote:
> > This set of changes has some history to them.  There were several attempts
> > to add what was called "fast link training" to i915, which actually wasn't
> > fast link training as per the DP spec.  These changes were:
> > 
> > commit 5fa836a9d859 ("drm/i915: DP link training optimization")
> > commit 4e96c97742f4 ("drm/i915: eDP link training optimization")
> > 
> > which were eventually hand-reverted by:
> > 
> > commit 34511dce4b35 ("drm/i915: Revert DisplayPort fast link training
> >  feature")
> > 
> > in kernel 4.7-rc4.  The eDP pieces of the above revert, however, had some
> > very bad side-effects on PSR functionality on Skylake. The issue at
> > hand is that when PSR exits i915 briefly emits TP1 followed by TP2/3
> > (depending on the original link configuration) in order to quickly get
> > the source and sink back in synchronization across the link before handing
> > control back to the i915.  There's an assumption that none of the link
> > configuration information has changed (and thus it's still valid) since the
> > last full link training operation.  The revert above was identified via a
> > bisect as the cause of some of Skylake's PSR woes.  This patch, largely
> > based on commit 4e96c97742f4 ("drm/i915: eDP link training optimization")
> > puts the eDP portions of this patch back in place.  None of the flickering
> > issues that spurred the revert have been seen, and I suspect the real
> > culprits here were addressed by some of the recent link training changes
> > that Manasi has implemented, and PSR on Skylake is definitely more happy
> > with these changes in-place.
> > 
> > v2 and v3: Rebase
> > v4: * Clean up accesses to train_set_valid a bit for easier
> >   reading. (Chris)
> > * Rebase
> > v5: * Checkpatch cleanup
> > * Rebase
> > v6: * is_edp() => intel_dp_is_edp()
> > * rebase
> > v7: * Remove extraneous is_edp() prototype (Rodrigo)
> > 
> > Cc: Chris Wilson 
> > Cc: Rodrigo Vivi 
> > Cc: Paulo Zanoni 
> > Cc: Manasi D Navare 
> > Cc: Mika Kahola 
> > Cc: Jani Nikula 
> > Fixes: 34511dce4 ("drm/i915: Revert DisplayPort fast link training feature")
> > Signed-off-by: Jim Bride 
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c   |  2 ++
> >  drivers/gpu/drm/i915/intel_dp_link_training.c | 15 ++-
> >  drivers/gpu/drm/i915/intel_drv.h  |  1 +
> >  3 files changed, 17 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c 
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index e385658..38bc7e0 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -4750,6 +4750,7 @@ intel_dp_long_pulse(struct intel_connector 
> > *intel_connector)
> > intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
> >  
> > intel_dp->reset_link_params = false;
> > +   intel_dp->train_set_valid = false;
> > }
> >  
> > intel_dp_print_rates(intel_dp);
> > @@ -6019,6 +6020,7 @@ intel_dp_init_connector(struct intel_digital_port 
> > *intel_dig_port,
> > intel_dp_set_source_rates(intel_dp);
> >  
> > intel_dp->reset_link_params = true;
> > +   intel_dp->train_set_valid = false;
> > intel_dp->pps_pipe = INVALID_PIPE;
> > intel_dp->active_pipe = INVALID_PIPE;
> >  
> > diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c 
> > b/drivers/gpu/drm/i915/intel_dp_link_training.c
> > index 05907fa..79fe369 100644
> > --- a/drivers/gpu/drm/i915/intel_dp_link_training.c
> > +++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
> > @@ -94,7 +94,8 @@ static bool
> >  intel_dp_reset_link_train(struct intel_dp *intel_dp,
> > uint8_t dp_train_pat)
> >  {
> > -   memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
> > +   if (!intel_dp->train_set_valid)
> > +   memset(intel_dp->train_set, 0, 

Re: [Intel-gfx] [RFC 10/11] drm/i915: Export engine stats API to other users

[Ben Widawsky]

On 17-09-15 10:49:56, Tvrtko Ursulin wrote:


On 14/09/2017 21:26, Chris Wilson wrote:

Quoting Tvrtko Ursulin (2017-09-11 16:25:58)

From: Tvrtko Ursulin 

Other kernel users might want to look at total GPU busyness
in order to implement things like package power distribution
algorithms more efficiently.


Who are we exporting these symbols to? Will you not need all the module
ref handling and load ordering like around ips and audio?


Hm yes indeed, I forgot about that.

Perhaps Ben could comment on who is the user. If it is purely for 
internal explorations, I'll stick the patch at the end of the series 
as it is. If it has a more serious user I would need to implement a 
proper solution.


Regards,

Tvrtko


P-state driver was looking to use this as a way to make determinations about how
much to limit CPU frequency. Srinivas was privy to the original discussion

--
Ben Widawsky, Intel Open Source Technology Center
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[Intel-gfx] [PATCH 0/5] drm/i915: Skylake plane update/disable unifications [v5]

[Juha-Pekka Heikkila]

[v5] use clipped y coordinate at get_crtc_fence_y_offset() (ville syrjälä)

[v4] rebase

[v3] Took into account fbc adjusted y/x for primary plane (ville syrjälä)

[v2] Fixed missed references which were brough on rebase.

/Juha-Pekka

Juha-Pekka Heikkila (5):
  drm/i915: move adjusted_x/y from crtc to cache.
  drm/i915: Unify skylake plane update
  drm/i915: Unify skylake plane disable
  drm/i915: dspaddr_offset doesn't need to be more than local variable
  drm/i915: adjust get_crtc_fence_y_offset() to use base.y instead of
crtc.y

 drivers/gpu/drm/i915/i915_drv.h  |  10 +++
 drivers/gpu/drm/i915/intel_display.c | 119 ---
 drivers/gpu/drm/i915/intel_drv.h |  11 ++--
 drivers/gpu/drm/i915/intel_fbc.c |  14 +++--
 drivers/gpu/drm/i915/intel_sprite.c  |   4 +-
 5 files changed, 38 insertions(+), 120 deletions(-)

-- 
2.7.4

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[Intel-gfx] [PATCH 3/5] drm/i915: Unify skylake plane disable

[Juha-Pekka Heikkila]

Don't handle skylake primary plane separately as it is similar
plane as the others.

Signed-off-by: Juha-Pekka Heikkila 
---
 drivers/gpu/drm/i915/intel_display.c | 21 ++---
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 drivers/gpu/drm/i915/intel_sprite.c  |  2 +-
 3 files changed, 4 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index f8ee434..48d5975 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3554,23 +3554,6 @@ u32 skl_plane_ctl(const struct intel_crtc_state 
*crtc_state,
return plane_ctl;
 }
 
-static void skylake_disable_primary_plane(struct intel_plane *primary,
- struct intel_crtc *crtc)
-{
-   struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
-   enum plane_id plane_id = primary->id;
-   enum pipe pipe = primary->pipe;
-   unsigned long irqflags;
-
-   spin_lock_irqsave(_priv->uncore.lock, irqflags);
-
-   I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
-   I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
-   POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
-
-   spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
-}
-
 static int
 __intel_display_resume(struct drm_device *dev,
   struct drm_atomic_state *state,
@@ -13155,7 +13138,7 @@ intel_primary_plane_create(struct drm_i915_private 
*dev_priv, enum pipe pipe)
modifiers = skl_format_modifiers_ccs;
 
primary->update_plane = skl_update_plane;
-   primary->disable_plane = skylake_disable_primary_plane;
+   primary->disable_plane = skl_disable_plane;
} else if (INTEL_GEN(dev_priv) >= 9) {
intel_primary_formats = skl_primary_formats;
num_formats = ARRAY_SIZE(skl_primary_formats);
@@ -13165,7 +13148,7 @@ intel_primary_plane_create(struct drm_i915_private 
*dev_priv, enum pipe pipe)
modifiers = skl_format_modifiers_noccs;
 
primary->update_plane = skl_update_plane;
-   primary->disable_plane = skylake_disable_primary_plane;
+   primary->disable_plane = skl_disable_plane;
} else if (INTEL_GEN(dev_priv) >= 4) {
intel_primary_formats = i965_primary_formats;
num_formats = ARRAY_SIZE(i965_primary_formats);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 7b225d0..56fb493 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1920,6 +1920,7 @@ void intel_pipe_update_end(struct intel_crtc_state 
*new_crtc_state);
 void skl_update_plane(struct intel_plane *plane,
  const struct intel_crtc_state *crtc_state,
  const struct intel_plane_state *plane_state);
+void skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc);
 
 /* intel_tv.c */
 void intel_tv_init(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c 
b/drivers/gpu/drm/i915/intel_sprite.c
index 2ec4108..22598c2 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -305,7 +305,7 @@ skl_update_plane(struct intel_plane *plane,
spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
 }
 
-static void
+void
 skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
 {
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
-- 
2.7.4

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[Intel-gfx] [PATCH 5/5] drm/i915: adjust get_crtc_fence_y_offset() to use base.y instead of crtc.y

[Juha-Pekka Heikkila]

This is to use clipped y coordinate here. I left get_crtc_fence_y_offset()
function itself in place as oneliner to maintain comment above it why this
is done.

Signed-off-by: Juha-Pekka Heikkila 
---
 drivers/gpu/drm/i915/i915_drv.h  |  2 ++
 drivers/gpu/drm/i915/intel_fbc.c | 11 +--
 2 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 17960ba..f7c1162 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1103,6 +1103,8 @@ struct intel_fbc {
 */
int adjusted_x;
int adjusted_y;
+
+   int base_y;
} plane;
 
struct {
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index dc059808..a65af80 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -69,12 +69,10 @@ static inline bool no_fbc_on_multiple_pipes(struct 
drm_i915_private *dev_priv)
  * address we program because it starts at the real start of the buffer, so we
  * have to take this into consideration here.
  */
-static unsigned int get_crtc_fence_y_offset(struct intel_crtc *crtc)
+static unsigned int get_crtc_fence_y_offset(struct intel_fbc *fbc)
 {
-   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-   struct intel_fbc *fbc = _priv->fbc;
-
-   return crtc->base.y - fbc->state_cache.plane.adjusted_y;
+   return fbc->state_cache.plane.base_y
+   - fbc->state_cache.plane.adjusted_y;
 }
 
 /*
@@ -762,6 +760,7 @@ static void intel_fbc_update_state_cache(struct intel_crtc 
*crtc,
cache->plane.visible = plane_state->base.visible;
cache->plane.adjusted_x = plane_state->main.x;
cache->plane.adjusted_y = plane_state->main.y;
+   cache->plane.base_y = plane_state->base.src.y1 >> 16;
 
if (!cache->plane.visible)
return;
@@ -893,7 +892,7 @@ static void intel_fbc_get_reg_params(struct intel_crtc 
*crtc,
 
params->crtc.pipe = crtc->pipe;
params->crtc.plane = crtc->plane;
-   params->crtc.fence_y_offset = get_crtc_fence_y_offset(crtc);
+   params->crtc.fence_y_offset = get_crtc_fence_y_offset(fbc);
 
params->fb.format = cache->fb.format;
params->fb.stride = cache->fb.stride;
-- 
2.7.4

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[Intel-gfx] [PATCH 1/5] drm/i915: move adjusted_x/y from crtc to cache.

[Juha-Pekka Heikkila]

Signed-off-by: Juha-Pekka Heikkila 
---
 drivers/gpu/drm/i915/i915_drv.h  |  8 
 drivers/gpu/drm/i915/intel_display.c | 10 ++
 drivers/gpu/drm/i915/intel_drv.h |  2 --
 drivers/gpu/drm/i915/intel_fbc.c | 11 ---
 4 files changed, 22 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6d7d871..17960ba 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1095,6 +1095,14 @@ struct intel_fbc {
int src_w;
int src_h;
bool visible;
+   /*
+* Display surface base address adjustement for
+* pageflips. Note that on gen4+ this only adjusts up
+* to a tile, offsets within a tile are handled in
+* the hw itself (with the TILEOFF register).
+*/
+   int adjusted_x;
+   int adjusted_y;
} plane;
 
struct {
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 8599e42..92e8370 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3307,6 +3307,7 @@ static void i9xx_update_primary_plane(struct intel_plane 
*primary,
int x = plane_state->main.x;
int y = plane_state->main.y;
unsigned long irqflags;
+   struct intel_fbc *fbc = _priv->fbc;
 
linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 
@@ -3315,8 +3316,8 @@ static void i9xx_update_primary_plane(struct intel_plane 
*primary,
else
crtc->dspaddr_offset = linear_offset;
 
-   crtc->adjusted_x = x;
-   crtc->adjusted_y = y;
+   fbc->state_cache.plane.adjusted_x = x;
+   fbc->state_cache.plane.adjusted_y = y;
 
spin_lock_irqsave(_priv->uncore.lock, irqflags);
 
@@ -3577,6 +3578,7 @@ static void skylake_update_primary_plane(struct 
intel_plane *plane,
int dst_w = drm_rect_width(_state->base.dst);
int dst_h = drm_rect_height(_state->base.dst);
unsigned long irqflags;
+   struct intel_fbc *fbc = _priv->fbc;
 
/* Sizes are 0 based */
src_w--;
@@ -3586,8 +3588,8 @@ static void skylake_update_primary_plane(struct 
intel_plane *plane,
 
crtc->dspaddr_offset = surf_addr;
 
-   crtc->adjusted_x = src_x;
-   crtc->adjusted_y = src_y;
+   fbc->state_cache.plane.adjusted_x = src_x;
+   fbc->state_cache.plane.adjusted_y = src_y;
 
spin_lock_irqsave(_priv->uncore.lock, irqflags);
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 3078076..62aada7 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -807,8 +807,6 @@ struct intel_crtc {
 * gen4+ this only adjusts up to a tile, offsets within a tile are
 * handled in the hw itself (with the TILEOFF register). */
u32 dspaddr_offset;
-   int adjusted_x;
-   int adjusted_y;
 
struct intel_crtc_state *config;
 
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index 58a772d..dc059808 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -71,7 +71,10 @@ static inline bool no_fbc_on_multiple_pipes(struct 
drm_i915_private *dev_priv)
  */
 static unsigned int get_crtc_fence_y_offset(struct intel_crtc *crtc)
 {
-   return crtc->base.y - crtc->adjusted_y;
+   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+   struct intel_fbc *fbc = _priv->fbc;
+
+   return crtc->base.y - fbc->state_cache.plane.adjusted_y;
 }
 
 /*
@@ -727,8 +730,8 @@ static bool intel_fbc_hw_tracking_covers_screen(struct 
intel_crtc *crtc)
 
intel_fbc_get_plane_source_size(>state_cache, _w,
_h);
-   effective_w += crtc->adjusted_x;
-   effective_h += crtc->adjusted_y;
+   effective_w += fbc->state_cache.plane.adjusted_x;
+   effective_h += fbc->state_cache.plane.adjusted_y;
 
return effective_w <= max_w && effective_h <= max_h;
 }
@@ -757,6 +760,8 @@ static void intel_fbc_update_state_cache(struct intel_crtc 
*crtc,
cache->plane.src_w = drm_rect_width(_state->base.src) >> 16;
cache->plane.src_h = drm_rect_height(_state->base.src) >> 16;
cache->plane.visible = plane_state->base.visible;
+   cache->plane.adjusted_x = plane_state->main.x;
+   cache->plane.adjusted_y = plane_state->main.y;
 
if (!cache->plane.visible)
return;
-- 
2.7.4

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[Intel-gfx] [PATCH 2/5] drm/i915: Unify skylake plane update

[Juha-Pekka Heikkila]

Don't handle skylake primary plane separately as it is similar
plane as the others.

Signed-off-by: Juha-Pekka Heikkila 
---
 drivers/gpu/drm/i915/intel_display.c | 82 +---
 drivers/gpu/drm/i915/intel_drv.h |  3 ++
 drivers/gpu/drm/i915/intel_sprite.c  |  2 +-
 3 files changed, 6 insertions(+), 81 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 92e8370..f8ee434 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3554,84 +3554,6 @@ u32 skl_plane_ctl(const struct intel_crtc_state 
*crtc_state,
return plane_ctl;
 }
 
-static void skylake_update_primary_plane(struct intel_plane *plane,
-const struct intel_crtc_state 
*crtc_state,
-const struct intel_plane_state 
*plane_state)
-{
-   struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
-   struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
-   const struct drm_framebuffer *fb = plane_state->base.fb;
-   enum plane_id plane_id = plane->id;
-   enum pipe pipe = plane->pipe;
-   u32 plane_ctl = plane_state->ctl;
-   unsigned int rotation = plane_state->base.rotation;
-   u32 stride = skl_plane_stride(fb, 0, rotation);
-   u32 aux_stride = skl_plane_stride(fb, 1, rotation);
-   u32 surf_addr = plane_state->main.offset;
-   int scaler_id = plane_state->scaler_id;
-   int src_x = plane_state->main.x;
-   int src_y = plane_state->main.y;
-   int src_w = drm_rect_width(_state->base.src) >> 16;
-   int src_h = drm_rect_height(_state->base.src) >> 16;
-   int dst_x = plane_state->base.dst.x1;
-   int dst_y = plane_state->base.dst.y1;
-   int dst_w = drm_rect_width(_state->base.dst);
-   int dst_h = drm_rect_height(_state->base.dst);
-   unsigned long irqflags;
-   struct intel_fbc *fbc = _priv->fbc;
-
-   /* Sizes are 0 based */
-   src_w--;
-   src_h--;
-   dst_w--;
-   dst_h--;
-
-   crtc->dspaddr_offset = surf_addr;
-
-   fbc->state_cache.plane.adjusted_x = src_x;
-   fbc->state_cache.plane.adjusted_y = src_y;
-
-   spin_lock_irqsave(_priv->uncore.lock, irqflags);
-
-   if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
-   I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
- PLANE_COLOR_PIPE_GAMMA_ENABLE |
- PLANE_COLOR_PIPE_CSC_ENABLE |
- PLANE_COLOR_PLANE_GAMMA_DISABLE);
-   }
-
-   I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
-   I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x);
-   I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
-   I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
-   I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
- (plane_state->aux.offset - surf_addr) | aux_stride);
-   I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id),
- (plane_state->aux.y << 16) | plane_state->aux.x);
-
-   if (scaler_id >= 0) {
-   uint32_t ps_ctrl = 0;
-
-   WARN_ON(!dst_w || !dst_h);
-   ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) |
-   crtc_state->scaler_state.scalers[scaler_id].mode;
-   I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
-   I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
-   I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | 
dst_y);
-   I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | 
dst_h);
-   I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
-   } else {
-   I915_WRITE_FW(PLANE_POS(pipe, plane_id), (dst_y << 16) | dst_x);
-   }
-
-   I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
- intel_plane_ggtt_offset(plane_state) + surf_addr);
-
-   POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
-
-   spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
-}
-
 static void skylake_disable_primary_plane(struct intel_plane *primary,
  struct intel_crtc *crtc)
 {
@@ -13232,7 +13154,7 @@ intel_primary_plane_create(struct drm_i915_private 
*dev_priv, enum pipe pipe)
num_formats = ARRAY_SIZE(skl_primary_formats);
modifiers = skl_format_modifiers_ccs;
 
-   primary->update_plane = skylake_update_primary_plane;
+   primary->update_plane = skl_update_plane;
primary->disable_plane = skylake_disable_primary_plane;
} else if (INTEL_GEN(dev_priv) >= 9) {
intel_primary_formats = skl_primary_formats;
@@ -13242,7 +13164,7 @@ intel_primary_plane_create(struct drm_i915_private 
*dev_priv, enum pipe pipe)
else

[Intel-gfx] [PATCH 4/5] drm/i915: dspaddr_offset doesn't need to be more than local variable

[Juha-Pekka Heikkila]

Move u32 dspaddr_offset from struct intel_crtc member into local
variable in i9xx_update_primary_plane()

Signed-off-by: Juha-Pekka Heikkila 
---
 drivers/gpu/drm/i915/intel_display.c | 12 ++--
 drivers/gpu/drm/i915/intel_drv.h |  5 -
 2 files changed, 6 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 48d5975..d214977 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3298,7 +3298,6 @@ static void i9xx_update_primary_plane(struct intel_plane 
*primary,
  const struct intel_plane_state 
*plane_state)
 {
struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
-   struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
const struct drm_framebuffer *fb = plane_state->base.fb;
enum plane plane = primary->plane;
u32 linear_offset;
@@ -3308,13 +3307,14 @@ static void i9xx_update_primary_plane(struct 
intel_plane *primary,
int y = plane_state->main.y;
unsigned long irqflags;
struct intel_fbc *fbc = _priv->fbc;
+   u32 dspaddr_offset;
 
linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 
if (INTEL_GEN(dev_priv) >= 4)
-   crtc->dspaddr_offset = plane_state->main.offset;
+   dspaddr_offset = plane_state->main.offset;
else
-   crtc->dspaddr_offset = linear_offset;
+   dspaddr_offset = linear_offset;
 
fbc->state_cache.plane.adjusted_x = x;
fbc->state_cache.plane.adjusted_y = y;
@@ -3343,18 +3343,18 @@ static void i9xx_update_primary_plane(struct 
intel_plane *primary,
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
I915_WRITE_FW(DSPSURF(plane),
  intel_plane_ggtt_offset(plane_state) +
- crtc->dspaddr_offset);
+ dspaddr_offset);
I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x);
} else if (INTEL_GEN(dev_priv) >= 4) {
I915_WRITE_FW(DSPSURF(plane),
  intel_plane_ggtt_offset(plane_state) +
- crtc->dspaddr_offset);
+ dspaddr_offset);
I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x);
I915_WRITE_FW(DSPLINOFF(plane), linear_offset);
} else {
I915_WRITE_FW(DSPADDR(plane),
  intel_plane_ggtt_offset(plane_state) +
- crtc->dspaddr_offset);
+ dspaddr_offset);
}
POSTING_READ_FW(reg);
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 56fb493..a92c2e2 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -803,11 +803,6 @@ struct intel_crtc {
unsigned long long enabled_power_domains;
struct intel_overlay *overlay;
 
-   /* Display surface base address adjustement for pageflips. Note that on
-* gen4+ this only adjusts up to a tile, offsets within a tile are
-* handled in the hw itself (with the TILEOFF register). */
-   u32 dspaddr_offset;
-
struct intel_crtc_state *config;
 
/* global reset count when the last flip was submitted */
-- 
2.7.4

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[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915: always update ELD connector type after get modes

[Patchwork]

== Series Details ==

Series: drm/i915: always update ELD connector type after get modes
URL   : https://patchwork.freedesktop.org/series/30602/
State : warning

== Summary ==

Series 30602v1 drm/i915: always update ELD connector type after get modes
https://patchwork.freedesktop.org/api/1.0/series/30602/revisions/1/mbox/

Test kms_addfb_basic:
Subgroup clobberred-modifier:
pass   -> DMESG-WARN (fi-kbl-7500u)
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-legacy:
pass   -> FAIL   (fi-snb-2600) fdo#100215
Test kms_frontbuffer_tracking:
Subgroup basic:
dmesg-warn -> PASS   (fi-kbl-7500u)
Test kms_pipe_crc_basic:
Subgroup hang-read-crc-pipe-b:
incomplete -> DMESG-WARN (fi-cfl-s) fdo#102294

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#102294 https://bugs.freedesktop.org/show_bug.cgi?id=102294

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:438s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:473s
fi-blb-e6850 total:289  pass:224  dwarn:1   dfail:0   fail:0   skip:64  
time:417s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:513s
fi-bwr-2160  total:289  pass:184  dwarn:0   dfail:0   fail:0   skip:105 
time:278s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:503s
fi-byt-j1900 total:289  pass:254  dwarn:1   dfail:0   fail:0   skip:34  
time:491s
fi-byt-n2820 total:289  pass:250  dwarn:1   dfail:0   fail:0   skip:38  
time:497s
fi-cfl-s total:289  pass:223  dwarn:34  dfail:0   fail:0   skip:32  
time:540s
fi-elk-e7500 total:289  pass:230  dwarn:0   dfail:0   fail:0   skip:59  
time:421s
fi-glk-1 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:564s
fi-hsw-4770  total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:422s
fi-hsw-4770r total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:405s
fi-ilk-650   total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:425s
fi-ivb-3520m total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:490s
fi-ivb-3770  total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:461s
fi-kbl-7500u total:245  pass:222  dwarn:2   dfail:0   fail:0   skip:20 
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:582s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:587s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:445s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:750s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:487s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:471s
fi-snb-2520m total:289  pass:251  dwarn:0   dfail:0   fail:0   skip:38  
time:563s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:1   skip:39  
time:415s
fi-pnv-d510 failed to connect after reboot

bf6ecf6d25c1c45e576643b7d7a65e8b1e6b4f01 drm-tip: 2017y-09m-19d-17h-23m-04s UTC 
integration manifest
690262d1dc43 drm/i915: always update ELD connector type after get modes

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5751/
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[Intel-gfx] [PATCH v6 3/3] drm/i915: Make i915_modparams members const

[Michal Wajdeczko]

We should discourage developers from modifying modparams.
Introduce special macro for easier tracking of changes done
in modparams and enforce its use by defining existing modparams
members as const. Note that defining whole modparams struct
as const makes checkpatch unhappy.

v2: rebased

Credits-to: Coccinelle

@@
identifier n;
expression e;
@@
(
-   i915_modparams.n = e;
+   i915_modparams_set(n, e);
)

Signed-off-by: Michal Wajdeczko 
Cc: Jani Nikula 
Cc: Chris Wilson 
Cc: Tvrtko Ursulin 
Cc: Ville Syrjala 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_drv.c | 12 ++--
 drivers/gpu/drm/i915/i915_params.c  |  4 ++--
 drivers/gpu/drm/i915/i915_params.h  |  7 ++-
 drivers/gpu/drm/i915/intel_fbc.c|  2 +-
 drivers/gpu/drm/i915/intel_guc_log.c| 10 +-
 drivers/gpu/drm/i915/intel_gvt.c|  4 ++--
 drivers/gpu/drm/i915/intel_psr.c|  2 +-
 drivers/gpu/drm/i915/intel_ringbuffer.c |  2 +-
 drivers/gpu/drm/i915/intel_runtime_pm.c |  4 ++--
 drivers/gpu/drm/i915/intel_uc.c | 18 ++
 drivers/gpu/drm/i915/intel_uncore.c | 14 +++---
 11 files changed, 43 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 7056bb2..99b47c5 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1032,9 +1032,9 @@ static void i915_driver_cleanup_mmio(struct 
drm_i915_private *dev_priv)
 
 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
 {
-   i915_modparams.enable_execlists =
+   i915_modparams_set(enable_execlists,
intel_sanitize_enable_execlists(dev_priv,
-   
i915_modparams.enable_execlists);
+   
i915_modparams.enable_execlists));
 
/*
 * i915.enable_ppgtt is read-only, so do an early pass to validate the
@@ -1042,13 +1042,13 @@ static void intel_sanitize_options(struct 
drm_i915_private *dev_priv)
 * do this now so that we can print out any log messages once rather
 * than every time we check intel_enable_ppgtt().
 */
-   i915_modparams.enable_ppgtt =
+   i915_modparams_set(enable_ppgtt,
intel_sanitize_enable_ppgtt(dev_priv,
-   i915_modparams.enable_ppgtt);
+   i915_modparams.enable_ppgtt));
DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915_modparams.enable_ppgtt);
 
-   i915_modparams.semaphores =
-   intel_sanitize_semaphores(dev_priv, i915_modparams.semaphores);
+   i915_modparams_set(semaphores,
+   intel_sanitize_semaphores(dev_priv, i915_modparams.semaphores));
DRM_DEBUG_DRIVER("use GPU semaphores? %s\n",
 yesno(i915_modparams.semaphores));
 
diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index ec65341..2a8fa9b 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -26,10 +26,10 @@
 #include "i915_drv.h"
 
 #define i915_param_named(name, T, perm, desc) \
-   module_param_named(name, i915_modparams.name, T, perm); \
+   module_param_named(name, i915_modparams.name##_writable, T, perm); \
MODULE_PARM_DESC(name, desc)
 #define i915_param_named_unsafe(name, T, perm, desc) \
-   module_param_named_unsafe(name, i915_modparams.name, T, perm); \
+   module_param_named_unsafe(name, i915_modparams.name##_writable, T, 
perm); \
MODULE_PARM_DESC(name, desc)
 
 struct i915_params i915_modparams __read_mostly = {
diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index a2cbb47..e7b2845 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -70,7 +70,7 @@
func(bool, enable_dpcd_backlight); \
func(bool, enable_gvt)
 
-#define MEMBER(T, member) T member
+#define MEMBER(T, member) union { const T member; T member##_writable; }
 struct i915_params {
I915_PARAMS_FOR_EACH(MEMBER);
 };
@@ -78,5 +78,10 @@ struct i915_params {
 
 extern struct i915_params i915_modparams __read_mostly;
 
+#define i915_modparams_set(name, value)\
+({ \
+   i915_modparams.name##_writable = value; \
+})
+
 #endif
 
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index 8e3a055..13fa354 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -1355,7 +1355,7 @@ void intel_fbc_init(struct drm_i915_private *dev_priv)
if (need_fbc_vtd_wa(dev_priv))
mkwrite_device_info(dev_priv)->has_fbc = false;
 
-   i915_modparams.enable_fbc 

[Intel-gfx] [PATCH v6 1/3] drm/i915: Rename global i915 to i915_modparams

[Michal Wajdeczko]

Our global struct with params is named exactly the same way
as new preferred name for the drm_i915_private function parameter.
To avoid such name reuse lets use different name for the global.

v5: pure rename
v6: fix

Credits-to: Coccinelle

@@
identifier n;
@@
(
-   i915.n
+   i915_modparams.n
)

Signed-off-by: Michal Wajdeczko 
Cc: Jani Nikula 
Cc: Chris Wilson 
Cc: Tvrtko Ursulin 
Cc: Ville Syrjala 
Cc: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/gvt/render.c |  2 +-
 drivers/gpu/drm/i915/i915_debugfs.c   | 14 
 drivers/gpu/drm/i915/i915_drv.c   | 34 ++
 drivers/gpu/drm/i915/i915_drv.h   | 10 +++---
 drivers/gpu/drm/i915/i915_gem.c   |  4 +--
 drivers/gpu/drm/i915/i915_gem_context.c   | 12 +++
 drivers/gpu/drm/i915/i915_gem_execbuffer.c|  2 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c   |  6 ++--
 drivers/gpu/drm/i915/i915_gpu_error.c |  6 ++--
 drivers/gpu/drm/i915/i915_guc_submission.c|  2 +-
 drivers/gpu/drm/i915/i915_irq.c   |  2 +-
 drivers/gpu/drm/i915/i915_params.c|  6 ++--
 drivers/gpu/drm/i915/i915_params.h|  2 +-
 drivers/gpu/drm/i915/i915_pci.c   |  6 ++--
 drivers/gpu/drm/i915/i915_perf.c  |  6 ++--
 drivers/gpu/drm/i915/intel_bios.c |  7 ++--
 drivers/gpu/drm/i915/intel_crt.c  |  4 +--
 drivers/gpu/drm/i915/intel_device_info.c  |  2 +-
 drivers/gpu/drm/i915/intel_display.c  | 12 +++
 drivers/gpu/drm/i915/intel_dp.c   |  4 +--
 drivers/gpu/drm/i915/intel_dp_aux_backlight.c |  2 +-
 drivers/gpu/drm/i915/intel_drv.h  |  2 +-
 drivers/gpu/drm/i915/intel_engine_cs.c|  4 +--
 drivers/gpu/drm/i915/intel_fbc.c  | 11 +++---
 drivers/gpu/drm/i915/intel_guc_loader.c   | 13 +++
 drivers/gpu/drm/i915/intel_guc_log.c  | 26 +++---
 drivers/gpu/drm/i915/intel_gvt.c  | 12 +++
 drivers/gpu/drm/i915/intel_hangcheck.c|  2 +-
 drivers/gpu/drm/i915/intel_huc.c  |  4 +--
 drivers/gpu/drm/i915/intel_lrc.c  |  4 +--
 drivers/gpu/drm/i915/intel_lvds.c |  4 +--
 drivers/gpu/drm/i915/intel_opregion.c |  2 +-
 drivers/gpu/drm/i915/intel_panel.c|  8 ++---
 drivers/gpu/drm/i915/intel_pm.c   |  6 ++--
 drivers/gpu/drm/i915/intel_psr.c  | 10 +++---
 drivers/gpu/drm/i915/intel_ringbuffer.c   |  8 ++---
 drivers/gpu/drm/i915/intel_runtime_pm.c   | 17 -
 drivers/gpu/drm/i915/intel_uc.c   | 51 ++-
 drivers/gpu/drm/i915/intel_uncore.c   | 22 ++--
 39 files changed, 182 insertions(+), 169 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/render.c 
b/drivers/gpu/drm/i915/gvt/render.c
index 2ea5422..6d066cf 100644
--- a/drivers/gpu/drm/i915/gvt/render.c
+++ b/drivers/gpu/drm/i915/gvt/render.c
@@ -293,7 +293,7 @@ static void switch_mmio_to_vgpu(struct intel_vgpu *vgpu, 
int ring_id)
 */
if (mmio->in_context &&
((ctx_ctrl & inhibit_mask) != inhibit_mask) &&
-   i915.enable_execlists)
+   i915_modparams.enable_execlists)
continue;
 
if (mmio->mask)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index ca6fa6d..13fc259 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -67,7 +67,7 @@ static int i915_capabilities(struct seq_file *m, void *data)
 #undef PRINT_FLAG
 
kernel_param_lock(THIS_MODULE);
-#define PRINT_PARAM(T, x) seq_print_param(m, #x, #T, );
+#define PRINT_PARAM(T, x) seq_print_param(m, #x, #T, _modparams.x);
I915_PARAMS_FOR_EACH(PRINT_PARAM);
 #undef PRINT_PARAM
kernel_param_unlock(THIS_MODULE);
@@ -1267,7 +1267,7 @@ static int i915_hangcheck_info(struct seq_file *m, void 
*unused)
if (waitqueue_active(_priv->gpu_error.reset_queue))
seq_puts(m, "struct_mutex blocked for reset\n");
 
-   if (!i915.enable_hangcheck) {
+   if (!i915_modparams.enable_hangcheck) {
seq_puts(m, "Hangcheck disabled\n");
return 0;
}
@@ -1702,7 +1702,7 @@ static int i915_ips_status(struct seq_file *m, void 
*unused)
intel_runtime_pm_get(dev_priv);
 
seq_printf(m, "Enabled by kernel parameter: %s\n",
-  yesno(i915.enable_ips));
+  yesno(i915_modparams.enable_ips));
 
if (INTEL_GEN(dev_priv) >= 8) {
seq_puts(m, "Currently: unknown\n");
@@ -2017,7 +2017,7 @@ static int i915_dump_lrc(struct seq_file *m, void *unused)
enum intel_engine_id 

[Intel-gfx] [PATCH v6 2/3] drm/i915: Prepare error capture to work with const modparams

[Michal Wajdeczko]

We are planning to enforce "read_mostly" access to modparams.
Let start handle modparams as it was already defined as const.

Signed-off-by: Michal Wajdeczko 
---
 drivers/gpu/drm/i915/i915_gpu_error.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
b/drivers/gpu/drm/i915/i915_gpu_error.c
index c7aaf62..15fe8ed 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -820,7 +820,7 @@ static void i915_error_object_free(struct 
drm_i915_error_object *obj)
kfree(obj);
 }
 
-static __always_inline void free_param(const char *type, void *x)
+static __always_inline void free_param(const char *type, const void *x)
 {
if (!__builtin_strcmp(type, "char *"))
kfree(*(void **)x);
@@ -1680,7 +1680,7 @@ static void i915_capture_gen_state(struct 
drm_i915_private *dev_priv,
   sizeof(error->device_info));
 }
 
-static __always_inline void dup_param(const char *type, void *x)
+static __always_inline void dup_param(const char *type, const void *x)
 {
if (!__builtin_strcmp(type, "char *"))
*(void **)x = kstrdup(*(void **)x, GFP_ATOMIC);
@@ -1696,7 +1696,7 @@ static int capture(void *data)
ktime_to_timeval(ktime_sub(ktime_get(),
   error->i915->gt.last_init_time));
 
-   error->params = i915_modparams;
+   memcpy(>params, _modparams, sizeof(i915_modparams));
 #define DUP(T, x) dup_param(#T, >params.x);
I915_PARAMS_FOR_EACH(DUP);
 #undef DUP
-- 
2.7.4

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Re: [Intel-gfx] [PATCH 8/9] drm/i915/dp: Protect link training with connection mutex

[Pandiyan, Dhinakaran]

On Tue, 2017-09-19 at 15:42 +0300, Ville Syrjälä wrote:
> On Mon, Sep 18, 2017 at 09:50:30PM +, Pandiyan, Dhinakaran wrote:
> > On Fri, 2017-09-15 at 13:10 +0300, Ville Syrjälä wrote:
> > > On Tue, Sep 12, 2017 at 04:57:29PM -0700, Dhinakaran Pandiyan wrote:
> > > > The other instances of link training are protected with
> > > > connection_mutex, so do the same in check_mst_status() too.
> > > > 
> > > > Signed-off-by: Dhinakaran Pandiyan 
> > > > ---
> > > >  drivers/gpu/drm/i915/intel_dp.c | 4 
> > > >  1 file changed, 4 insertions(+)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c 
> > > > b/drivers/gpu/drm/i915/intel_dp.c
> > > > index aab9ba31f79e..644463ba313e 100644
> > > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > > @@ -4191,6 +4191,7 @@ static void intel_dp_handle_test_request(struct 
> > > > intel_dp *intel_dp)
> > > >  static int
> > > >  intel_dp_check_mst_status(struct intel_dp *intel_dp)
> > > >  {
> > > > +   struct drm_device *dev = intel_dp_to_dev(intel_dp);
> > > > bool bret;
> > > > u8 esi[DP_DPRX_ESI_LEN] = { 0 };
> > > > int ret = 0;
> > > > @@ -4205,8 +4206,11 @@ intel_dp_check_mst_status(struct intel_dp 
> > > > *intel_dp)
> > > > if (intel_dp->active_mst_links &&
> > > > !drm_dp_channel_eq_ok([10], 
> > > > intel_dp->lane_count)) {
> > > > DRM_DEBUG_KMS("channel EQ not ok, 
> > > > retraining\n");
> > > > +
> > > > +   
> > > > drm_modeset_lock(>mode_config.connection_mutex, NULL);
> > > > intel_dp_start_link_train(intel_dp);
> > > > intel_dp_stop_link_train(intel_dp);
> > > > +   
> > > > drm_modeset_unlock(>mode_config.connection_mutex);
> > > 
> > > This can deadlock. We should not grab any modeset locks from the
> > > dig_work. I had some patches at some point to move the link training to
> > > the hotplug work so SST. I don't think I had the MST side really sorted
> > > out at any point.
> > 
> > Interesting, the only lock we grab in this path from the work function
> > is the connection_mutex. So, I am not clear how this will deadlock. This
> > lock around link training is also at the same depth as the one around
> > link training in intel_dp_short_pulse(). Wouldn't that also deadlock if
> > that's the case?
> 
> Theoretically. Though I think the deadlock is only likely to happen with
> MST since that requires sideband to work during a modeset when we have
> connection_mutex already locked. So modeset code will be waiting for
> sideband to happen, and hpd_pulse which is responsible for doing sideband
> is waiting on the lock already held by the modeset. Thus we're stuck.
> 

disable_dp and enable_dp are the ones that use sideband messages during
modeset. But, there doesn't seem to be any real dependency on the
sideband messages, mostly because there is not much we do differently
when a downstream reply does not arrive.

Having said that, now that I know you (moving link training over to
hotplug work) and Maarten (link training vs modeset) already have code
to deal with this properly, this patch should be dropped. Thanks for the
review!


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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v5,1/3] drm/i915: Rename global i915 to i915_modparams

[Patchwork]

== Series Details ==

Series: series starting with [v5,1/3] drm/i915: Rename global i915 to 
i915_modparams
URL   : https://patchwork.freedesktop.org/series/30600/
State : failure

== Summary ==

  CHK include/config/kernel.release
  CHK include/generated/uapi/linux/version.h
  CHK include/generated/utsrelease.h
  CHK include/generated/bounds.h
  CHK include/generated/timeconst.h
  CHK include/generated/asm-offsets.h
  CALLscripts/checksyscalls.sh
  CHK scripts/mod/devicetable-offsets.h
  CHK include/generated/compile.h
  CHK kernel/config_data.h
  CC [M]  drivers/gpu/drm/i915/intel_gvt.o
drivers/gpu/drm/i915/intel_gvt.c: In function ‘intel_gvt_sanitize_options’:
drivers/gpu/drm/i915/intel_gvt.c:76:2: error: implicit declaration of function 
‘i915_modparams_mkwrite’ [-Werror=implicit-function-declaration]
  i915_modparams_mkwrite()->enable_gvt = 0;
  ^~
drivers/gpu/drm/i915/intel_gvt.c:76:26: error: invalid type argument of ‘->’ 
(have ‘int’)
  i915_modparams_mkwrite()->enable_gvt = 0;
  ^~
drivers/gpu/drm/i915/intel_gvt.c: In function ‘intel_gvt_init’:
drivers/gpu/drm/i915/intel_gvt.c:126:26: error: invalid type argument of ‘->’ 
(have ‘int’)
  i915_modparams_mkwrite()->enable_gvt = 0;
  ^~
cc1: all warnings being treated as errors
scripts/Makefile.build:311: recipe for target 
'drivers/gpu/drm/i915/intel_gvt.o' failed
make[4]: *** [drivers/gpu/drm/i915/intel_gvt.o] Error 1
scripts/Makefile.build:570: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:570: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:570: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1019: recipe for target 'drivers' failed
make: *** [drivers] Error 2

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Stop engines before reset (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Stop engines before reset (rev2)
URL   : https://patchwork.freedesktop.org/series/30357/
State : success

== Summary ==

Series 30357v2 drm/i915: Stop engines before reset
https://patchwork.freedesktop.org/api/1.0/series/30357/revisions/2/mbox/

Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
pass   -> FAIL   (fi-ivb-3770) fdo#100215
Test kms_frontbuffer_tracking:
Subgroup basic:
dmesg-warn -> PASS   (fi-kbl-7500u)
Test kms_pipe_crc_basic:
Subgroup hang-read-crc-pipe-b:
incomplete -> DMESG-WARN (fi-cfl-s) fdo#102294
Subgroup suspend-read-crc-pipe-a:
incomplete -> PASS   (fi-kbl-7500u)

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#102294 https://bugs.freedesktop.org/show_bug.cgi?id=102294

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:437s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:466s
fi-blb-e6850 total:289  pass:224  dwarn:1   dfail:0   fail:0   skip:64  
time:419s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:505s
fi-bwr-2160  total:289  pass:184  dwarn:0   dfail:0   fail:0   skip:105 
time:278s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:503s
fi-byt-j1900 total:289  pass:254  dwarn:1   dfail:0   fail:0   skip:34  
time:503s
fi-byt-n2820 total:289  pass:250  dwarn:1   dfail:0   fail:0   skip:38  
time:491s
fi-cfl-s total:289  pass:223  dwarn:34  dfail:0   fail:0   skip:32  
time:547s
fi-elk-e7500 total:289  pass:230  dwarn:0   dfail:0   fail:0   skip:59  
time:417s
fi-glk-1 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:570s
fi-hsw-4770  total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:421s
fi-hsw-4770r total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:407s
fi-ilk-650   total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:432s
fi-ivb-3520m total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:487s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:1   skip:28  
time:458s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:480s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:574s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:586s
fi-pnv-d510  total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:543s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:449s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:750s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:491s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:473s
fi-snb-2520m total:289  pass:251  dwarn:0   dfail:0   fail:0   skip:38  
time:567s
fi-snb-2600  total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:415s

bf6ecf6d25c1c45e576643b7d7a65e8b1e6b4f01 drm-tip: 2017y-09m-19d-17h-23m-04s UTC 
integration manifest
b6d41b3cd871 drm/i915: Stop engines before reset

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5749/
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Unset legacy_cursor_update early in intel_atomic_commit, v3.

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915: Unset legacy_cursor_update early 
in intel_atomic_commit, v3.
URL   : https://patchwork.freedesktop.org/series/30587/
State : success

== Summary ==

Series 30587v1 series starting with [1/2] drm/i915: Unset legacy_cursor_update 
early in intel_atomic_commit, v3.
https://patchwork.freedesktop.org/api/1.0/series/30587/revisions/1/mbox/

Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
pass   -> FAIL   (fi-snb-2600) fdo#100215
Test kms_frontbuffer_tracking:
Subgroup basic:
dmesg-warn -> PASS   (fi-kbl-7500u)
Test kms_pipe_crc_basic:
Subgroup hang-read-crc-pipe-b:
incomplete -> DMESG-WARN (fi-cfl-s) fdo#102294
Subgroup suspend-read-crc-pipe-a:
incomplete -> PASS   (fi-kbl-7500u)

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#102294 https://bugs.freedesktop.org/show_bug.cgi?id=102294

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:439s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:472s
fi-blb-e6850 total:289  pass:224  dwarn:1   dfail:0   fail:0   skip:64  
time:420s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:515s
fi-bwr-2160  total:289  pass:184  dwarn:0   dfail:0   fail:0   skip:105 
time:280s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:519s
fi-byt-j1900 total:289  pass:254  dwarn:1   dfail:0   fail:0   skip:34  
time:492s
fi-byt-n2820 total:289  pass:250  dwarn:1   dfail:0   fail:0   skip:38  
time:492s
fi-cfl-s total:289  pass:222  dwarn:35  dfail:0   fail:0   skip:32  
time:539s
fi-elk-e7500 total:289  pass:230  dwarn:0   dfail:0   fail:0   skip:59  
time:415s
fi-glk-1 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:562s
fi-hsw-4770  total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:426s
fi-hsw-4770r total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:405s
fi-ilk-650   total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:430s
fi-ivb-3520m total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:491s
fi-ivb-3770  total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:460s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:476s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:575s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:586s
fi-pnv-d510  total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:543s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:449s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:751s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:489s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:470s
fi-snb-2520m total:289  pass:251  dwarn:0   dfail:0   fail:0   skip:38  
time:560s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:1   skip:39  
time:412s

bf6ecf6d25c1c45e576643b7d7a65e8b1e6b4f01 drm-tip: 2017y-09m-19d-17h-23m-04s UTC 
integration manifest
fa47d22ff51e drm/i915: Skip vblank waits for cursor updates when watermarks 
dont need updating
e318ccc3d8f0 drm/i915: Unset legacy_cursor_update early in intel_atomic_commit, 
v3.

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5748/
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[Intel-gfx] ✓ Fi.CI.BAT: success for i915 PMU and engine busy stats (rev10)

[Patchwork]

== Series Details ==

Series: i915 PMU and engine busy stats (rev10)
URL   : https://patchwork.freedesktop.org/series/27488/
State : success

== Summary ==

Series 27488v10 i915 PMU and engine busy stats
https://patchwork.freedesktop.org/api/1.0/series/27488/revisions/10/mbox/

Test chamelium:
Subgroup dp-crc-fast:
pass   -> FAIL   (fi-kbl-7500u) fdo#102514
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-legacy:
pass   -> FAIL   (fi-snb-2600) fdo#100215
Test kms_frontbuffer_tracking:
Subgroup basic:
dmesg-warn -> PASS   (fi-kbl-7500u)
Test kms_pipe_crc_basic:
Subgroup hang-read-crc-pipe-b:
incomplete -> DMESG-WARN (fi-cfl-s) fdo#102294
Subgroup suspend-read-crc-pipe-a:
incomplete -> PASS   (fi-kbl-7500u)
Test drv_module_reload:
Subgroup basic-reload:
pass   -> DMESG-WARN (fi-glk-1) fdo#102777

fdo#102514 https://bugs.freedesktop.org/show_bug.cgi?id=102514
fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#102294 https://bugs.freedesktop.org/show_bug.cgi?id=102294
fdo#102777 https://bugs.freedesktop.org/show_bug.cgi?id=102777

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:437s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:473s
fi-blb-e6850 total:289  pass:224  dwarn:1   dfail:0   fail:0   skip:64  
time:420s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:510s
fi-bwr-2160  total:289  pass:184  dwarn:0   dfail:0   fail:0   skip:105 
time:280s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:509s
fi-byt-j1900 total:289  pass:254  dwarn:1   dfail:0   fail:0   skip:34  
time:495s
fi-byt-n2820 total:289  pass:250  dwarn:1   dfail:0   fail:0   skip:38  
time:495s
fi-cfl-s total:289  pass:223  dwarn:34  dfail:0   fail:0   skip:32  
time:541s
fi-elk-e7500 total:289  pass:230  dwarn:0   dfail:0   fail:0   skip:59  
time:419s
fi-glk-1 total:289  pass:259  dwarn:1   dfail:0   fail:0   skip:29  
time:567s
fi-hsw-4770  total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:426s
fi-hsw-4770r total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:405s
fi-ilk-650   total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:422s
fi-ivb-3520m total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:483s
fi-ivb-3770  total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:463s
fi-kbl-7500u total:289  pass:263  dwarn:1   dfail:0   fail:1   skip:24  
time:461s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:575s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:586s
fi-pnv-d510  total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:539s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:453s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:748s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:489s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:474s
fi-snb-2520m total:289  pass:251  dwarn:0   dfail:0   fail:0   skip:38  
time:568s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:1   skip:39  
time:422s

bf6ecf6d25c1c45e576643b7d7a65e8b1e6b4f01 drm-tip: 2017y-09m-19d-17h-23m-04s UTC 
integration manifest
5fee33211526 drm/i915: Gate engine stats collection with a static key
6fd166bf3f7a drm/i915/pmu: Wire up engine busy stats to PMU
5af6d7183c9a drm/i915: Engine busy time tracking
a2bcdfd1a9fc drm/i915: Wrap context schedule notification
dafaeae6847c drm/i915/pmu: Suspend sampling when GPU is idle
9aa4b74f8ca3 drm/i915/pmu: Expose a PMU interface for perf queries
808c73b2abb2 drm/i915: Extract intel_get_cagf
fa5db5906dea drm/i915: Convert intel_rc6_residency_us to ns

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5747/
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Re: [Intel-gfx] [PATCH] Idleness DRRS:

[Rodrigo Vivi]

On Tue, Sep 19, 2017 at 10:46:49AM +, Ramalingam C wrote:
> 
> 
> On Tuesday 19 September 2017 01:24 AM, Rodrigo Vivi wrote:
> > On Mon, Sep 18, 2017 at 08:52:12AM +,  wrote:
> > > From: Lohith BS 
> > > 
> > >   By default the DRRS state will be at DRRS_HIGH_RR. When a Display
> > >   content is Idle for more than 1Sec Idleness will be declared and
> > >   DRRS_LOW_RR will be invoked, changing the refresh rate to the
> > >   lower most refresh rate supported by the panel. As soon as there
> > >   is a display content change there will be a DRRS state transition
> > >   as DRRS_LOW_RR--> DRRS_HIGH_RR, changing the refresh rate to the
> > >   highest refresh rate supported by the panel.
> > > 
> > > To test this, Idleness DRRS IGT will probe the DRRS state at below
> > > instances and compare with the expected state.
> > > 
> > >   InstanceExpected State
> > > 1. Immediately after rendering the still imageDRRS_HIGH_RR
> > > 2. After a delay of 1.2SecDRRS_LOW_RR
> > > 3. After changing the frame bufferDRRS_HIGH_RR
> > > 4. After a delay of 1.2SecDRRS_LOW_RR
> > > 5. After changing the frame bufferDRRS_HIGH_RR
> > > 6. After a delay of 1.2SecDRRS_LOW_RR
> > > 
> > > The test checks the driver DRRS state from the debugfs entry. To check the
> > > actual refresh-rate, the number of vblanks received per sec.
> > > The refresh-rate calculated is checked against the expected refresh-rate
> > > with a tolerance value of 2.
> > > 
> > > This patch is a continuation of the earlier work
> > > https://patchwork.freedesktop.org/patch/45472/ towards igt for idleness
> > > 
> > > DRRS. The code is tested on Broxton BXT_T platform.
> > > 
> > > v2: Addressed the comments and suggestions from Vlad, Marius.
> > > The signoff details from the earlier work are also included.
> > > 
> > > v3: Modified vblank rate calculation by using reply-sequence, provided by
> > > drmWaitVBlank, as suggested by Chris Wilson.
> > > 
> > > v4: As suggested from Chris Wilson and Daniel Vetter
> > >   1) Avoided using pthread for calculating vblank refresh rate,
> > >  instead used drmWaitVBlank reply sequence.
> > >   2) Avoided using kernel-specific info like transitional delays,
> > >  instead polling mechanism with timeout is used.
> > >   3) Included edp-DRRS as a subtest in kms_frontbuffer_tracking.c,
> > >  instead of having a separate test.
> > > 
> > > v5: This patch adds DRRS as a new feature in the kms_frontbuffer_tracking 
> > > IGT.
> > >  DRRS switch to lower vrefresh rate is tested at slow-draw subtest.
> > > 
> > >   Note:
> > >   1) Currently kernel doesn't have support to enable and disable the DRRS
> > >  feature dynamically(as in case of PSR). Hence if the panel supports
> > >  DRRS it will be enabled by default.
> > > 
> > >   This is in continuation of last patch 
> > > "https://patchwork.freedesktop.org/patch/162726/;
> > > 
> > > Signed-off-by: Lohith BS 
> > > Signed-off-by: Ramalingam C 
> > > Signed-off-by: Vandana Kannan 
> > > Signed-off-by: aknautiy 
> > > ---
> > >   tests/kms_frontbuffer_tracking.c | 161 
> > > ---
> > >   1 file changed, 152 insertions(+), 9 deletions(-)
> > > 
> > > diff --git a/tests/kms_frontbuffer_tracking.c 
> > > b/tests/kms_frontbuffer_tracking.c
> > > index a068c8a..4f44109 100644
> > > --- a/tests/kms_frontbuffer_tracking.c
> > > +++ b/tests/kms_frontbuffer_tracking.c
> > > @@ -34,7 +34,7 @@
> > >   IGT_TEST_DESCRIPTION("Test the Kernel's frontbuffer tracking mechanism 
> > > and "
> > > -  "its related features: FBC and PSR");
> > > +  "its related features: FBC DRRS and PSR");
> > >   /*
> > >* One of the aspects of this test is that, for every subtest, we try 
> > > different
> > > @@ -105,8 +105,9 @@ struct test_mode {
> > >   FEATURE_NONE  = 0,
> > >   FEATURE_FBC   = 1,
> > >   FEATURE_PSR   = 2,
> > > - FEATURE_COUNT = 4,
> > > - FEATURE_DEFAULT = 4,
> > > + FEATURE_DRRS  = 4,
> > > + FEATURE_COUNT = 6,
> > > + FEATURE_DEFAULT = 6,
> > >   } feature;
> > >   /* Possible pixel formats. We just use FORMAT_DEFAULT for most 
> > > tests and
> > > @@ -180,6 +181,9 @@ struct {
> > >   bool can_test;
> > >   } psr = {
> > >   .can_test = false,
> > > +},
> > > +drrs  = {
> > > + .can_test = false,
> > >   };
> > > @@ -822,6 +826,52 @@ static void psr_print_status(void)
> > >   igt_info("PSR status:\n%s\n", buf);
> > >   }
> > > +static bool is_drrs_high(void)
> > > +{
> > > + char buf[256];
> > > +
> > > + debugfs_read("i915_drrs_status", buf);
> > > + 

Re: [Intel-gfx] [PATCH v2] drm/i915/mst: Use MST sideband message transactions for dpms control

[Pandiyan, Dhinakaran]

On Wed, 2017-09-13 at 13:06 -0700, Dhinakaran Pandiyan wrote:
> Use the POWER_DOWN_PHY and POWER_UP_PHY sideband message transactions to
> set power states for downstream sinks. Apart from giving us the ability
> to set power state for individual sinks, this fixes the below test for
> me.
> 
> $ xrandr --display :0 --output DP-2-2-8 --off
> $ xrandr --display :0 --output DP-2-2-1 --off
> $ xrandr --display :0 --output DP-2-2-8 --auto #Black screen
> $ xrandr --display :0 --output DP-2-2-1 --auto
> 
> v2: Modify and document the dpms and port disable order (Ville)
> Add comment explaining is_mst = !crtc_state equivalence(Ville, Maarten)
> 

The patch probably does not fix all problems of these bugs, but some
problems do go away.

References: https://bugs.freedesktop.org/show_bug.cgi?id=90963
References: https://bugs.freedesktop.org/show_bug.cgi?id=88124

Thanks for the reviews.
-DK


> Cc: Ville Syrjälä 
> Cc: Lyude 
> Cc: Maarten Lankhorst 
> Signed-off-by: Dhinakaran Pandiyan 
> ---
>  drivers/gpu/drm/i915/intel_ddi.c| 18 ++
>  drivers/gpu/drm/i915/intel_dp_mst.c | 13 +
>  2 files changed, 23 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 1da3bb2cc4b4..0053d66393f8 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2161,7 +2161,8 @@ static void intel_ddi_pre_enable_dp(struct 
> intel_encoder *encoder,
>   intel_prepare_dp_ddi_buffers(encoder);
>  
>   intel_ddi_init_dp_buf_reg(encoder);
> - intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
> + if (!link_mst)
> + intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
>   intel_dp_start_link_train(intel_dp);
>   if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
>   intel_dp_stop_link_train(intel_dp);
> @@ -2235,12 +2236,21 @@ static void intel_ddi_post_disable(struct 
> intel_encoder *intel_encoder,
>   uint32_t val;
>   bool wait = false;
>  
> - /* old_crtc_state and old_conn_state are NULL when called from DP_MST */
> -
>   if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
> + /*
> +  * old_crtc_state and old_conn_state are NULL when called from
> +  * DP_MST. The main connector associated with this port is never
> +  * bound to a crtc for MST.
> +  */
> + bool is_mst = !old_crtc_state;
>   struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>  
> - intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
> + /*
> +  * Power down sink before disabling the port, otherwise we end
> +  * up getting interrupts from the sink on detecting link loss.
> +  */
> + if (!is_mst)
> + intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
>   }
>  
>   val = I915_READ(DDI_BUF_CTL(port));
> diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c 
> b/drivers/gpu/drm/i915/intel_dp_mst.c
> index 8e3aad0ea60b..187f3f05a828 100644
> --- a/drivers/gpu/drm/i915/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/intel_dp_mst.c
> @@ -164,15 +164,19 @@ static void intel_mst_post_disable_dp(struct 
> intel_encoder *encoder,
>  
>   drm_dp_mst_deallocate_vcpi(_dp->mst_mgr, connector->port);
>  
> + /*
> +  * Power down mst path before disabling the port, otherwise we end
> +  * up getting interrupts from the sink upon detecting link loss.
> +  */
> + drm_dp_send_power_updown_phy(_dp->mst_mgr, connector->port,
> +  false);
> +
>   intel_dp->active_mst_links--;
>  
>   intel_mst->connector = NULL;
> - if (intel_dp->active_mst_links == 0) {
> + if (intel_dp->active_mst_links == 0)
>   intel_dig_port->base.post_disable(_dig_port->base,
> NULL, NULL);
> -
> - intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
> - }
>  }
>  
>  static void intel_mst_pre_enable_dp(struct intel_encoder *encoder,
> @@ -197,6 +201,7 @@ static void intel_mst_pre_enable_dp(struct intel_encoder 
> *encoder,
>  
>   DRM_DEBUG_KMS("%d\n", intel_dp->active_mst_links);
>  
> + drm_dp_send_power_updown_phy(_dp->mst_mgr, connector->port, true);
>   if (intel_dp->active_mst_links == 0)
>   intel_dig_port->base.pre_enable(_dig_port->base,
>   pipe_config, NULL);
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[Intel-gfx] [PATCH] dim: Accept author x signed-off based on email, but warn.

[Rodrigo Vivi]

It seems Patchwork or SMTP servers are messing some patches
and changing the original git's author name on git per "Last, First".
So we end up with a mismatch were signed-off uses one name format
and author is using another format.

So, let's check for email addresses instead.

However let's continue to WARN so commiters can take action on it
before pushing patch upstream with incorrect "Last, First" name.

Cc: Jani Nikula 
Cc: Joonas Lahtinen 
Signed-off-by: Rodrigo Vivi 
---
 dim | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/dim b/dim
index dbaeb1ec944d..13cc5f00209d 100755
--- a/dim
+++ b/dim
@@ -690,11 +690,16 @@ function checkpatch_commit_push
 
# use real names for people with many different email addresses
author=$(git show -s $sha1 --format="format:%an")
+   author_email=$(git show -s $sha1 --format="format:%ae")
committer=$(git show -s $sha1 --format="format:%cn")
 
# check for author sign-off
if ! git show -s $sha1 | grep -qi "S.*-by:.*$author"  ; then
-   warn_or_fail "$sha1 is lacking author of sign-off"
+   if git show -s $sha1 | grep -qi "S.*-by:.*$author_email"  ; then
+   echoerr "WARNING: Author name mismatch. Patchwork or 
SMTP messing it up. Consider fixing it before pushing it."
+   else
+   warn_or_fail "$sha1 is lacking author of sign-off"
+   fi
fi
 
# check for committer sign-off
-- 
2.13.5

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[Intel-gfx] [PATCH 29/31] drm/i915/slpc: Add Broxton SLPC support

[Sagar Arun Kamble]

From: Tom O'Rourke 

Adds has_slpc to broxton info.

v1: Adjusted slpc version check for major version 8.
Added message if version mismatch happens for easier debug. (Sagar)

v2-v3: Rebase.

v4: Commit message update.

v5: Rebase. Updated check in sanitize_slpc_option.

Signed-off-by: Tom O'Rourke 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/i915_pci.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 26eb673..026dc0c 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -484,6 +484,7 @@
 
 static const struct intel_device_info intel_broxton_info __initconst = {
GEN9_LP_FEATURES,
+   .has_slpc = 1,
.platform = INTEL_BROXTON,
.ddb_size = 512,
 };
-- 
1.9.1

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[Intel-gfx] [PATCH 25/31] drm/i915/slpc: Add enable/disable controls for SLPC tasks

[Sagar Arun Kamble]

From: Tom O'Rourke 

Adds debugfs hooks for enabling/disabling each SLPC task.

The enable/disable debugfs files are
i915_slpc_gtperf, i915_slpc_balancer, and i915_slpc_dcc.

Each of these can take the values:
"default", "enabled", or "disabled"

v1: update for SLPC v2015.2.4
dfps and turbo merged and renamed "gtperf"
ibc split out and renamed "balancer"
Avoid magic numbers (Jon Bloomfield)

v2-v3: Rebase.

v5: Moved slpc_enable_disable_set and slpc_enable_disable_get to
intel_slpc.c. s/slpc_enable_disable_get/intel_slpc_task_status
and s/slpc_enable_disable_set/intel_slpc_task_control. Prepared
separate functions to update the task status only in the SLPC
shared memory. Passing dev_priv as parameter.

v6: Rebase. s/slpc_param_show|write/slpc_task_param_show|write.
Moved functions to intel_slpc.c. RPM Get/Put added before setting
parameters and sending RESET event explicitly. (Sagar)

Signed-off-by: Tom O'Rourke 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/i915_debugfs.c |   3 +
 drivers/gpu/drm/i915/intel_slpc.c   | 184 
 drivers/gpu/drm/i915/intel_slpc.h   |   3 +
 3 files changed, 190 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 0a04f3d..e6fd63f 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4942,6 +4942,9 @@ static int i915_hpd_storm_ctl_open(struct inode *inode, 
struct file *file)
const struct file_operations *fops;
 } i915_debugfs_files[] = {
{"i915_wedged", _wedged_fops},
+   {"i915_slpc_gtperf", _slpc_gtperf_fops},
+   {"i915_slpc_balancer", _slpc_balancer_fops},
+   {"i915_slpc_dcc", _slpc_dcc_fops},
{"i915_max_freq", _max_freq_fops},
{"i915_min_freq", _min_freq_fops},
{"i915_cache_sharing", _cache_sharing_fops},
diff --git a/drivers/gpu/drm/i915/intel_slpc.c 
b/drivers/gpu/drm/i915/intel_slpc.c
index 0c094f0..512d88b 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -842,3 +842,187 @@ static ssize_t slpc_param_ctl_write(struct file *file, 
const char __user *ubuf,
.release = single_release,
.write = slpc_param_ctl_write
 };
+
+static void slpc_task_param_show(struct seq_file *m, u32 enable_id,
+u32 disable_id)
+{
+   struct drm_i915_private *dev_priv = m->private;
+   const char *status;
+   u64 val;
+   int ret;
+
+   ret = intel_slpc_task_status(_priv->guc.slpc, ,
+enable_id, disable_id);
+
+   if (ret) {
+   seq_printf(m, "error %d\n", ret);
+   } else {
+   switch (val) {
+   case SLPC_PARAM_TASK_DEFAULT:
+   status = "default\n";
+   break;
+
+   case SLPC_PARAM_TASK_ENABLED:
+   status = "enabled\n";
+   break;
+
+   case SLPC_PARAM_TASK_DISABLED:
+   status = "disabled\n";
+   break;
+
+   default:
+   status = "unknown\n";
+   break;
+   }
+
+   seq_puts(m, status);
+   }
+}
+
+static int slpc_task_param_write(struct seq_file *m, const char __user *ubuf,
+   size_t len, u32 enable_id, u32 disable_id)
+{
+   struct drm_i915_private *dev_priv = m->private;
+   u64 val;
+   int ret = 0;
+   char buf[10];
+
+   if (len >= sizeof(buf))
+   ret = -EINVAL;
+   else if (copy_from_user(buf, ubuf, len))
+   ret = -EFAULT;
+   else
+   buf[len] = '\0';
+
+   if (!ret) {
+   if (!strncmp(buf, "default", 7))
+   val = SLPC_PARAM_TASK_DEFAULT;
+   else if (!strncmp(buf, "enabled", 7))
+   val = SLPC_PARAM_TASK_ENABLED;
+   else if (!strncmp(buf, "disabled", 8))
+   val = SLPC_PARAM_TASK_DISABLED;
+   else
+   ret = -EINVAL;
+   }
+
+   if (!ret)
+   ret = intel_slpc_task_control(_priv->guc.slpc, val,
+ enable_id, disable_id);
+
+   return ret;
+}
+
+static int slpc_gtperf_show(struct seq_file *m, void *data)
+{
+   slpc_task_param_show(m, SLPC_PARAM_TASK_ENABLE_GTPERF,
+   SLPC_PARAM_TASK_DISABLE_GTPERF);
+
+   return 0;
+}
+
+static int slpc_gtperf_open(struct inode *inode, struct file *file)
+{
+   struct drm_i915_private *dev_priv = inode->i_private;
+
+   return single_open(file, slpc_gtperf_show, dev_priv);
+}
+
+static ssize_t slpc_gtperf_write(struct file *file, const char __user *ubuf,
+ size_t len, loff_t *offp)
+{
+   

[Intel-gfx] [PATCH 31/31] drm/i915/slpc: Add Geminilake SLPC support

[Sagar Arun Kamble]

Adds has_slpc to geminilake info.

Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/i915_pci.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index d89d6fc..738e214 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -491,6 +491,7 @@
 
 static const struct intel_device_info intel_geminilake_info __initconst = {
GEN9_LP_FEATURES,
+   .has_slpc = 1,
.platform = INTEL_GEMINILAKE,
.ddb_size = 1024,
.color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 }
-- 
1.9.1

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[Intel-gfx] [PATCH 30/31] drm/i915/slpc: Add Kabylake SLPC support

[Sagar Arun Kamble]

Adds has_slpc to kabylake info.

Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/i915_pci.c   | 1 +
 drivers/gpu/drm/i915/intel_slpc.c | 4 ++--
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 026dc0c..d89d6fc 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -502,6 +502,7 @@
.platform = INTEL_KABYLAKE, \
.has_csr = 1, \
.has_guc = 1, \
+   .has_slpc = 1, \
.has_ipc = 1, \
.ddb_size = 896
 
diff --git a/drivers/gpu/drm/i915/intel_slpc.c 
b/drivers/gpu/drm/i915/intel_slpc.c
index 512d88b..b723b46 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -71,9 +71,9 @@ static unsigned int slpc_get_platform_sku(struct 
drm_i915_private *dev_priv)
 {
enum slpc_platform_sku platform_sku;
 
-   if (IS_SKL_ULX(dev_priv))
+   if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv))
platform_sku = SLPC_PLATFORM_SKU_ULX;
-   else if (IS_SKL_ULT(dev_priv))
+   else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv))
platform_sku = SLPC_PLATFORM_SKU_ULT;
else
platform_sku = SLPC_PLATFORM_SKU_DT;
-- 
1.9.1

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[Intel-gfx] [PATCH 11/31] drm/i915: Introduce separate status variable for RC6 and Ring frequency setup

[Sagar Arun Kamble]

Defined new struct intel_rc6 to hold RC6 specific state and
intel_ring_pstate to hold ring specific state.

Cc: Imre Deak 
Cc: Chris Wilson 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/i915_drv.c |  2 +-
 drivers/gpu/drm/i915/i915_drv.h | 10 +++
 drivers/gpu/drm/i915/intel_pm.c | 58 ++---
 3 files changed, 54 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index a6dbad3..f13a3de 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2486,7 +2486,7 @@ static int intel_runtime_suspend(struct device *kdev)
struct drm_i915_private *dev_priv = to_i915(dev);
int ret;
 
-   if (WARN_ON_ONCE(!(dev_priv->pm.rps.enabled && intel_rc6_enabled(
+   if (WARN_ON_ONCE(!(dev_priv->pm.rc6.enabled && intel_rc6_enabled(
return -ENODEV;
 
if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e3264e5..a09952d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1352,8 +1352,18 @@ struct intel_rps {
struct intel_rps_ei ei;
 };
 
+struct intel_rc6 {
+   bool enabled;
+};
+
+struct intel_ring_pstate {
+   bool configured;
+};
+
 struct intel_gen6_power_mgmt {
struct intel_rps rps;
+   struct intel_rc6 rc6;
+   struct intel_ring_pstate ring_pstate;
struct delayed_work autoenable_work;
 
/*
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0c46f81..ac20dbf 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7881,8 +7881,12 @@ static void intel_init_emon(struct drm_i915_private 
*dev_priv)
 
 static inline void intel_update_ring_freq(struct drm_i915_private *i915)
 {
-   if (NEEDS_RING_FREQ_UPDATE(i915))
+   if (NEEDS_RING_FREQ_UPDATE(i915)) {
+   if (READ_ONCE(i915->pm.ring_pstate.configured))
+   return;
gen6_update_ring_freq(i915);
+   i915->pm.ring_pstate.configured = true;
+   }
 }
 
 void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
@@ -7975,7 +7979,8 @@ void intel_suspend_gt_powersave(struct drm_i915_private 
*dev_priv)
 
 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
 {
-   dev_priv->pm.rps.enabled = true; /* force disabling */
+   dev_priv->pm.rps.enabled = true; /* force RPS disabling */
+   dev_priv->pm.rc6.enabled = true; /* force RC6 disabling */
intel_disable_gt_powersave(dev_priv);
 
gen6_reset_rps_interrupts(dev_priv);
@@ -7983,6 +7988,9 @@ void intel_sanitize_gt_powersave(struct drm_i915_private 
*dev_priv)
 
 void intel_disable_rc6(struct drm_i915_private *dev_priv)
 {
+   if (!READ_ONCE(dev_priv->pm.rc6.enabled))
+   return;
+
if (INTEL_GEN(dev_priv) >= 9)
gen9_disable_rc6(dev_priv);
else if (IS_CHERRYVIEW(dev_priv))
@@ -7991,10 +7999,15 @@ void intel_disable_rc6(struct drm_i915_private 
*dev_priv)
valleyview_disable_rc6(dev_priv);
else if (INTEL_GEN(dev_priv) >= 6)
gen6_disable_rc6(dev_priv);
+
+   dev_priv->pm.rc6.enabled = false;
 }
 
 void intel_disable_rps(struct drm_i915_private *dev_priv)
 {
+   if (!READ_ONCE(dev_priv->pm.rps.enabled))
+   return;
+
if (INTEL_GEN(dev_priv) >= 9)
gen9_disable_rps(dev_priv);
else if (IS_CHERRYVIEW(dev_priv))
@@ -8005,24 +8018,30 @@ void intel_disable_rps(struct drm_i915_private 
*dev_priv)
gen6_disable_rps(dev_priv);
else if (IS_IRONLAKE_M(dev_priv))
ironlake_disable_drps(dev_priv);
+
+   dev_priv->pm.rps.enabled = false;
 }
 
 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
 {
-   if (!READ_ONCE(dev_priv->pm.rps.enabled))
-   return;
-
mutex_lock(_priv->pm.pcu_lock);
 
intel_disable_rc6(dev_priv);
intel_disable_rps(dev_priv);
+   if (NEEDS_RING_FREQ_UPDATE(dev_priv))
+   dev_priv->pm.ring_pstate.configured = false;
 
-   dev_priv->pm.rps.enabled = false;
mutex_unlock(_priv->pm.pcu_lock);
 }
 
 void intel_enable_rc6(struct drm_i915_private *dev_priv)
 {
+   /* We shouldn't be disabling as we submit, so this should be less
+* racy than it appears!
+*/
+   if (READ_ONCE(dev_priv->pm.rc6.enabled))
+   return;
+
if (IS_CHERRYVIEW(dev_priv))
cherryview_enable_rc6(dev_priv);
else if (IS_VALLEYVIEW(dev_priv))
@@ -8033,10 +8052,18 @@ void intel_enable_rc6(struct drm_i915_private *dev_priv)
gen8_enable_rc6(dev_priv);
else if (INTEL_GEN(dev_priv) >= 6)
gen6_enable_rc6(dev_priv);
+

[Intel-gfx] [PATCH 13/31] drm/i915/slpc: Add has_slpc capability flag

[Sagar Arun Kamble]

From: Tom O'Rourke 

Add has_slpc capablity flag to indicate GuC firmware
supports single loop power control (SLPC).  SLPC is
a replacement for some host-based power management
features.

v1: fix whitespace (Sagar)

Reviewed-by: David Weinehall 
Signed-off-by: Tom O'Rourke 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/i915_drv.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5fcebb8..428cb1c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -791,6 +791,7 @@ struct intel_csr {
func(has_rc6p); \
func(has_resource_streamer); \
func(has_runtime_pm); \
+   func(has_slpc); \
func(has_snoop); \
func(unfenced_needs_alignment); \
func(cursor_needs_physical); \
@@ -3162,6 +3163,7 @@ static inline unsigned int i915_sg_segment_size(void)
 #define HAS_GUC_UCODE(dev_priv)(HAS_GUC(dev_priv))
 #define HAS_GUC_SCHED(dev_priv)(HAS_GUC(dev_priv))
 #define HAS_HUC_UCODE(dev_priv)(HAS_GUC(dev_priv))
+#define HAS_SLPC(dev_priv) ((dev_priv)->info.has_slpc)
 
 #define HAS_RESOURCE_STREAMER(dev_priv) 
((dev_priv)->info.has_resource_streamer)
 
-- 
1.9.1

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[Intel-gfx] [PATCH 20/31] drm/i915/slpc: Add parameter set/unset/get, task control/status functions

[Sagar Arun Kamble]

SLPC behavior can be changed through set of parameters.
These parameters can be updated and queried from i915 though
Host to GuC SLPC events. This patch adds parameter update
events for setting/unsetting/getting parameters. SLPC has
various tasks for controlling different controls. This patch
adds functions to control and query the task status.

v1: Use host2guc_slpc
update slcp_param_id enum values for SLPC 2015.2.4
return void instead of ignored error code (Paulo)

v2: Checkpatch update.

v3: Rebase.

v4: Updated with GuC firmware v9.

v5: Updated input structure to host2guc_slpc. Added functions
to update only parameters in the SLPC shared memory. This
will allow to setup shared data with all parameters and send
single event to SLPC take them into effect. Commit message
update. (Sagar)

v6: Rearranged helpers to use them in slpc_shared_data_init.
Added definition of SLPC_KMD_MAX_PARAM.

v7: Added definition of host2guc_slpc with rearrangement of patches.
Added task control/status functions.

v8: Rebase w.r.t s/intel_guc_send/intel_guc_send_mmio.

Cc: Michal Wajdeczko 
Signed-off-by: Tom O'Rourke 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/intel_guc.c  |  21 -
 drivers/gpu/drm/i915/intel_guc.h  |   2 +
 drivers/gpu/drm/i915/intel_slpc.c | 185 ++
 drivers/gpu/drm/i915/intel_slpc.h |   8 ++
 4 files changed, 215 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index a92c7e8..656bae9 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -67,9 +67,11 @@ void intel_guc_init_send_regs(struct intel_guc *guc)
 /*
  * This function implements the MMIO based host to GuC interface.
  */
-int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len)
+int __intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len,
+ u32 *output)
 {
struct drm_i915_private *dev_priv = guc_to_i915(guc);
+   union slpc_event_output_header header;
u32 status;
int i;
int ret;
@@ -115,12 +117,29 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 
*action, u32 len)
 action[0], ret, status, I915_READ(SOFT_SCRATCH(15)));
}
 
+   /*
+* Output data from Host to GuC SLPC actions is populated in scratch
+* registers SOFT_SCRATCH(1) to SOFT_SCRATCH(14) based on event.
+* Currently only SLPC action status in GuC is meaningful as Host
+* can query only overridden parameters and that are fetched from
+* Host-GuC SLPC shared data.
+*/
+   if (output && !ret) {
+   output[0] = header.value = I915_READ(SOFT_SCRATCH(1));
+   ret = header.status;
+   }
+
intel_uncore_forcewake_put(dev_priv, guc->send_regs.fw_domains);
mutex_unlock(>send_mutex);
 
return ret;
 }
 
+int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len)
+{
+   return __intel_guc_send_mmio(guc, action, len, NULL);
+}
+
 int intel_guc_sample_forcewake(struct intel_guc *guc)
 {
struct drm_i915_private *dev_priv = guc_to_i915(guc);
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index b835d30..c27d2dd 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -132,6 +132,8 @@ struct intel_guc {
 int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len);
 void gen8_guc_raise_irq(struct intel_guc *guc);
 void intel_guc_init_send_regs(struct intel_guc *guc);
+int __intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len,
+ u32 *output);
 int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len);
 int intel_guc_sample_forcewake(struct intel_guc *guc);
 int intel_guc_runtime_suspend(struct intel_guc *guc);
diff --git a/drivers/gpu/drm/i915/intel_slpc.c 
b/drivers/gpu/drm/i915/intel_slpc.c
index 73e7bf5..f47d81e 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -132,6 +132,191 @@ int slpc_mem_task_control(struct slpc_shared_data *data, 
u64 val,
return ret;
 }
 
+static void host2guc_slpc(struct intel_slpc *slpc,
+ struct slpc_event_input *input, u32 len)
+{
+   struct intel_guc *guc = slpc_to_guc(slpc);
+   u32 *data;
+   u32 output[SLPC_EVENT_MAX_OUTPUT_ARGS];
+   int ret = 0;
+
+   /*
+* We have only 15 scratch registers for communication.
+* the first we will use for the event ID in input and
+* output data. Event processing status will be present
+* in SOFT_SCRATCH(1) register.
+*/
+   BUILD_BUG_ON(SLPC_EVENT_MAX_INPUT_ARGS > 14);
+   BUILD_BUG_ON(SLPC_EVENT_MAX_OUTPUT_ARGS < 1);
+   

[Intel-gfx] [PATCH 21/31] drm/i915/slpc: Send RESET event to enable SLPC during Load/TDR

[Sagar Arun Kamble]

Send host2guc SLPC reset event to GuC post GuC load.
Post this, i915 can ascertain if SLPC has started running successfully
through shared data. This check is done during intel_init_gt_powersave.
This allows to get initial configuration setup by SLPC and if needed
move to Host RPS if SLPC runs into issues.
On TDR/Engine reset i915 should send extra flag
SLPC_RESET_FLAG_TDR_OCCURREDto clear SLPC state as appropriate.

v1: Extract host2guc_slpc to handle slpc status code
coding style changes (Paulo)
Removed WARN_ON for checking msb of gtt address of
shared gem obj. (ChrisW)
host2guc_action to i915_guc_action change.(Sagar)
Updating SLPC enabled status. (Sagar)

v2: Commit message update. (David)

v3: Rebase.

v4: Added DRM_INFO message when SLPC is enabled.

v5: Updated patch as host2guc_slpc is moved to earlier patch.
SLPC activation status message put after checking the
state from shared data during intel_init_gt_powersave.

v6: Added definition of host2guc_slpc and clflush the shared data only
for required size. Setting state to NOT_RUNNING before sending RESET
event. Output data for SLPC actions is to be retrieved during
intel_guc_send with lock protection so created wrapper
__intel_guc_send that outputs GuC output data if needed. Clearing
pm_rps_events on confirming SLPC RUNNING status so that even if
host touches any of the PM registers by mistake it should not have
any effect. (Sagar)

v7: Added save/restore_default_rps as Uncore sanitize will clear the
RP_CONTROL setup by BIOS. s/i915_ggtt_offset/guc_ggtt_offset.

v8: Added support for handling TDR based SLPC reset. Added functions
host2guc_slpc_tdr_reset, intel_slpc_reset_prepare and
intel_slpc_tdr_reset to handle TDR based SLPC reset.

Cc: Michal Wajdeczko 
Signed-off-by: Tom O'Rourke 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/i915_drv.c   |   2 +
 drivers/gpu/drm/i915/i915_irq.c   |   7 +-
 drivers/gpu/drm/i915/intel_pm.c   |  10 +++
 drivers/gpu/drm/i915/intel_slpc.c | 170 ++
 drivers/gpu/drm/i915/intel_slpc.h |   9 ++
 drivers/gpu/drm/i915/intel_uc.c   |   1 +
 6 files changed, 198 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index f13a3de..932f9ef 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1074,6 +1074,8 @@ static int i915_driver_init_hw(struct drm_i915_private 
*dev_priv)
 
intel_sanitize_options(dev_priv);
 
+   intel_slpc_save_default_rps(_priv->guc.slpc);
+
ret = i915_ggtt_probe_hw(dev_priv);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 4a1554c..2d5ad13 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2838,8 +2838,13 @@ void i915_handle_error(struct drm_i915_private *dev_priv,
}
}
 
-   if (!engine_mask)
+   if (!engine_mask) {
+   if (intel_slpc_active(_priv->guc.slpc)) {
+   intel_slpc_reset_prepare(_priv->guc.slpc);
+   intel_slpc_tdr_reset(_priv->guc.slpc);
+   }
goto out;
+   }
 
/* Full reset needs the mutex, stop any other user trying to do so. */
if (test_and_set_bit(I915_RESET_BACKOFF, _priv->gpu_error.flags)) {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6b2b7f8..c2065f2 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7918,6 +7918,16 @@ void intel_init_gt_powersave(struct drm_i915_private 
*dev_priv)
intel_runtime_pm_get(dev_priv);
}
 
+   if (intel_slpc_enabled()) {
+   dev_priv->guc.slpc.active =
+   intel_slpc_get_status(_priv->guc.slpc);
+   if (!intel_slpc_active(_priv->guc.slpc)) {
+   i915.enable_slpc = 0;
+   intel_sanitize_gt_powersave(dev_priv);
+   } else
+   dev_priv->pm_rps_events = 0;
+   }
+
mutex_lock(_priv->drm.struct_mutex);
mutex_lock(_priv->pm.pcu_lock);
 
diff --git a/drivers/gpu/drm/i915/intel_slpc.c 
b/drivers/gpu/drm/i915/intel_slpc.c
index f47d81e..57e69d4 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -390,6 +390,140 @@ static void slpc_shared_data_init(struct intel_slpc *slpc)
kunmap_atomic(data);
 }
 
+static void host2guc_slpc_reset(struct intel_slpc *slpc)
+{
+   struct slpc_event_input data = {0};
+   u32 shared_data_gtt_offset = guc_ggtt_offset(slpc->vma);
+
+   data.header.value = SLPC_EVENT(SLPC_EVENT_RESET, 2);
+   data.args[0] = shared_data_gtt_offset;
+   data.args[1] = 0;
+
+   host2guc_slpc(slpc, , 4);
+}
+

[Intel-gfx] [PATCH 22/31] drm/i915/slpc: Send SHUTDOWN event

[Sagar Arun Kamble]

From: Tom O'Rourke 

Send SLPC shutdown event during disable, suspend, and reset
operations. Sending shutdown event while already shutdown
is OK.

v1: Return void instead of ignored error code (Paulo)
Removed WARN_ON for checking msb of gtt address of
shared gem obj. (ChrisW)
Added SLPC state update during disable, suspend and reset.
Changed semantics of reset. It is supposed to just disable. (Sagar)

v2-v4: Rebase.

v5: Updated the input data structure. (Sagar)

v6: Rebase.

v7: s/i915_ggtt_offset/guc_ggtt_offset.

v8: Updated the status check post disabling to wait for 20us. (Sagar)

Signed-off-by: Tom O'Rourke 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/intel_slpc.c | 27 +++
 1 file changed, 27 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_slpc.c 
b/drivers/gpu/drm/i915/intel_slpc.c
index 57e69d4..b0a17ef 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -427,6 +427,18 @@ static void host2guc_slpc_query_task_state(struct 
intel_slpc *slpc)
host2guc_slpc(slpc, , 4);
 }
 
+static void host2guc_slpc_shutdown(struct intel_slpc *slpc)
+{
+   struct slpc_event_input data = {0};
+   u32 shared_data_gtt_offset = guc_ggtt_offset(slpc->vma);
+
+   data.header.value = SLPC_EVENT(SLPC_EVENT_SHUTDOWN, 2);
+   data.args[0] = shared_data_gtt_offset;
+   data.args[1] = 0;
+
+   host2guc_slpc(slpc, , 4);
+}
+
 void intel_slpc_query_task_state(struct intel_slpc *slpc)
 {
if (slpc->active)
@@ -598,6 +610,21 @@ void intel_slpc_tdr_reset(struct intel_slpc *slpc)
slpc->tdr_reset = false;
 }
 
+static bool intel_slpc_disabled(struct intel_slpc *slpc)
+{
+   struct slpc_shared_data data;
+
+   intel_slpc_read_shared_data(slpc, );
+   return (data.global_state == SLPC_GLOBAL_STATE_NOT_RUNNING);
+}
+
 void intel_slpc_disable(struct intel_slpc *slpc)
 {
+   host2guc_slpc_shutdown(slpc);
+
+   /* Ensure SLPC is not running prior to releasing Shared data */
+   if (wait_for_us(intel_slpc_disabled(slpc), 20))
+   WARN_ONCE(true, "SLPC shutdown failed\n");
+
+   slpc->active = false;
 }
-- 
1.9.1

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[Intel-gfx] [PATCH 17/31] drm/i915/slpc: Enable SLPC in GuC if supported

[Sagar Arun Kamble]

From: Tom O'Rourke 

If slpc enabled, then add enable SLPC flag to guc
control parameter during guc load.

v1: Use intel_slpc_enabled() (Paulo)

v2-v4: Rebase.

v5: Changed intel_slpc_enabled() to i915.enable_slpc. (Sagar)

v6: Changed i915.enable_slpc to intel_slpc_enabled(). (Sagar)

Signed-off-by: Tom O'Rourke 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/intel_guc_loader.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c 
b/drivers/gpu/drm/i915/intel_guc_loader.c
index 4550620..0a71d04 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -131,6 +131,9 @@ static void guc_params_init(struct drm_i915_private 
*dev_priv)
params[GUC_CTL_FEATURE] |= GUC_CTL_DISABLE_SCHEDULER |
GUC_CTL_VCS2_ENABLED;
 
+   if (intel_slpc_enabled())
+   params[GUC_CTL_FEATURE] |= GUC_CTL_ENABLE_SLPC;
+
params[GUC_CTL_LOG_PARAMS] = guc->log.flags;
 
if (i915.guc_log_level >= 0) {
-- 
1.9.1

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[Intel-gfx] [PATCH 27/31] drm/i915/slpc: Add SLPC banner to RPS debugfs interfaces.

[Sagar Arun Kamble]

When SLPC is controlling frequency requests, RPS state related to
autotuning is no longer valid. Make user aware through banner
upfront. Value read from register RPNSWREQ likely has the frequency
requested last by GuC SLPC.

v1: Replace HAS_SLPC with intel_slpc_active (Paulo)
Avoid magic numbers (Nick)
Use a function for repeated code (Jon)

v2: Add "SLPC Active" to i915_frequency_info output and
don't update cur_freq as it is driver internal request. (Chris)

v3: Removing sysfs interface gt_req_freq_mhz out of this patch
for proper division of functionality. (Sagar)

v4: idle_freq, boost_freq are also not used with SLPC.

v5: Added SLPC banner to i915_rps_boost_info and keep printing
driver internal values. (Chris)

v6: Commit message update.

Signed-off-by: Tom O'Rourke 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 7a0838f..a873565 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1195,6 +1195,9 @@ static int i915_frequency_info(struct seq_file *m, void 
*unused)
 
intel_runtime_pm_get(dev_priv);
 
+   if (intel_slpc_active(_priv->guc.slpc))
+   seq_puts(m, "SLPC Active\n");
+
if (IS_GEN5(dev_priv)) {
u16 rgvswctl = I915_READ16(MEMSWCTL);
u16 rgvstat = I915_READ16(MEMSTAT_ILK);
@@ -2409,6 +2412,9 @@ static int i915_rps_boost_info(struct seq_file *m, void 
*data)
struct intel_rps *rps = _priv->pm.rps;
struct drm_file *file;
 
+   if (intel_slpc_active(_priv->guc.slpc))
+   seq_puts(m, "SLPC Active\n");
+
seq_printf(m, "RPS enabled? %d\n", rps->enabled);
seq_printf(m, "GPU busy? %s [%d requests]\n",
   yesno(dev_priv->gt.awake), dev_priv->gt.active_requests);
-- 
1.9.1

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[Intel-gfx] [PATCH 26/31] drm/i915/slpc: Add i915_slpc_info to debugfs

[Sagar Arun Kamble]

From: Tom O'Rourke 

i915_slpc_info shows the contents of SLPC shared data
parsed into text format.

v1: Reformat slpc info (Radek)
squashed query task state info
in slpc info, kunmap before seq_print (Paulo)
return void instead of ignored return value (Paulo)
Avoid magic numbers and use local variables (Jon Bloomfield)
Removed WARN_ON for checking msb of gtt address of
shared gem obj. (ChrisW)
Moved definition of power plan and power source to earlier
patch in the series.
drm/i915/slpc: Allocate/Release/Initialize SLPC shared data
(Akash)

v2-v3: Rebase.

v4: Updated with GuC firmware v9.

v5: Updated host2guc_slpc_query_task_state with struct slpc_input_event
structure. Removed unnecessary checks of vma from i915_slpc_info.
Created helpers for reading the SLPC shared data and string form of
SLPC state. (Sagar)

Signed-off-by: Tom O'Rourke 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 165 
 1 file changed, 165 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index e6fd63f..7a0838f 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1023,6 +1023,170 @@ static int i915_error_state_open(struct inode *inode, 
struct file *file)
NULL, i915_next_seqno_set,
"0x%llx\n");
 
+static int i915_slpc_info(struct seq_file *m, void *unused)
+{
+   struct drm_i915_private *dev_priv = node_to_i915(m->private);
+   int i, value;
+   struct slpc_shared_data data;
+   enum slpc_global_state global_state;
+   enum slpc_platform_sku platform_sku;
+   struct slpc_task_state_data *task_data;
+   enum slpc_power_plan power_plan;
+   enum slpc_power_source power_source;
+
+   if (!dev_priv->guc.slpc.active)
+   return -ENODEV;
+
+   intel_runtime_pm_get(dev_priv);
+   mutex_lock(_priv->pm.pcu_lock);
+
+   intel_slpc_read_shared_data(_priv->guc.slpc, );
+
+   mutex_unlock(_priv->pm.pcu_lock);
+   intel_runtime_pm_put(dev_priv);
+
+   seq_printf(m, "shared data size: %d\n", data.shared_data_size);
+
+   global_state = (enum slpc_global_state) data.global_state;
+   seq_printf(m, "global state: %d (", global_state);
+   seq_printf(m, "%s)\n", intel_slpc_get_state_str(global_state));
+
+   platform_sku = (enum slpc_platform_sku)
+   data.platform_info.platform_sku;
+   seq_printf(m, "sku: %d (", platform_sku);
+   switch (platform_sku) {
+   case SLPC_PLATFORM_SKU_UNDEFINED:
+   seq_puts(m, "undefined)\n");
+   break;
+   case SLPC_PLATFORM_SKU_ULX:
+   seq_puts(m, "ULX)\n");
+   break;
+   case SLPC_PLATFORM_SKU_ULT:
+   seq_puts(m, "ULT)\n");
+   break;
+   case SLPC_PLATFORM_SKU_T:
+   seq_puts(m, "T)\n");
+   break;
+   case SLPC_PLATFORM_SKU_MOBL:
+   seq_puts(m, "Mobile)\n");
+   break;
+   case SLPC_PLATFORM_SKU_DT:
+   seq_puts(m, "DT)\n");
+   break;
+   case SLPC_PLATFORM_SKU_UNKNOWN:
+   default:
+   seq_puts(m, "unknown)\n");
+   break;
+   }
+   seq_printf(m, "slice count: %d\n",
+  data.platform_info.slice_count);
+
+   seq_printf(m, "power plan/source: 0x%x\n\tplan:\t",
+  data.platform_info.power_plan_source);
+   power_plan = (enum slpc_power_plan) SLPC_POWER_PLAN(
+   data.platform_info.power_plan_source);
+   power_source = (enum slpc_power_source) SLPC_POWER_SOURCE(
+   data.platform_info.power_plan_source);
+   switch (power_plan) {
+   case SLPC_POWER_PLAN_UNDEFINED:
+   seq_puts(m, "undefined");
+   break;
+   case SLPC_POWER_PLAN_BATTERY_SAVER:
+   seq_puts(m, "battery saver");
+   break;
+   case SLPC_POWER_PLAN_BALANCED:
+   seq_puts(m, "balanced");
+   break;
+   case SLPC_POWER_PLAN_PERFORMANCE:
+   seq_puts(m, "performance");
+   break;
+   case SLPC_POWER_PLAN_UNKNOWN:
+   default:
+   seq_puts(m, "unknown");
+   break;
+   }
+   seq_puts(m, "\n\tsource:\t");
+   switch (power_source) {
+   case SLPC_POWER_SOURCE_UNDEFINED:
+   seq_puts(m, "undefined\n");
+   break;
+   case SLPC_POWER_SOURCE_AC:
+   seq_puts(m, "AC\n");
+   break;
+   case SLPC_POWER_SOURCE_DC:
+   seq_puts(m, "DC\n");
+   break;
+   case SLPC_POWER_SOURCE_UNKNOWN:
+   default:
+   seq_puts(m, "unknown\n");
+   break;

[Intel-gfx] [PATCH 24/31] drm/i915/slpc: Add debugfs support to read/write/revert the parameters

[Sagar Arun Kamble]

This patch adds two debugfs interfaces:
1. i915_slpc_paramlist: List of all parameters that Host can configure.
   Currently listing id and description of each.
2. i915_slpc_param_ctl: This allows to change the parameters. Syntax is:
   echo "write  " > i915_slpc_param_ctl.
   echo "read " > i915_slpc_param_ctl; cat i915_slpc_param_ctl
   revert allows to set to default SLPC internal values. Syntax is:
   echo "revert " > i915_slpc_param_ctl.

Added support to set/read parameters and unset the parameters which will
revert them to default SLPC internal values. Also added RPM ref. cover
around set/unset calls. Explicit SLPC reset is needed on setting/unsetting
some of the parameters.

Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/i915_debugfs.c |  19 +
 drivers/gpu/drm/i915/intel_slpc.c   | 158 
 drivers/gpu/drm/i915/intel_slpc.h   |   6 ++
 3 files changed, 183 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index dbfe185..0a04f3d 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2352,6 +2352,23 @@ static int i915_huc_load_status_info(struct seq_file *m, 
void *data)
return 0;
 }
 
+static int i915_slpc_paramlist_info(struct seq_file *m, void *data)
+{
+   struct drm_i915_private *dev_priv = node_to_i915(m->private);
+   int i;
+
+   if (!dev_priv->guc.slpc.active) {
+   seq_puts(m, "SLPC not active\n");
+   return 0;
+   }
+
+   seq_puts(m, "Param id\tParam description\n");
+   for (i = 0; i < SLPC_MAX_PARAM; i++)
+   seq_printf(m, "%8d\t%s\n", slpc_paramlist[i].id,
+  slpc_paramlist[i].description);
+   return 0;
+}
+
 static int i915_guc_load_status_info(struct seq_file *m, void *data)
 {
struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -4881,6 +4898,7 @@ static int i915_hpd_storm_ctl_open(struct inode *inode, 
struct file *file)
{"i915_guc_load_err_log_dump", i915_guc_log_dump, 0, (void *)1},
{"i915_guc_stage_pool", i915_guc_stage_pool, 0},
{"i915_huc_load_status", i915_huc_load_status_info, 0},
+   {"i915_slpc_paramlist", i915_slpc_paramlist_info, 0},
{"i915_frequency_info", i915_frequency_info, 0},
{"i915_hangcheck_info", i915_hangcheck_info, 0},
{"i915_reset_info", i915_reset_info, 0},
@@ -4944,6 +4962,7 @@ static int i915_hpd_storm_ctl_open(struct inode *inode, 
struct file *file)
{"i915_dp_test_type", _displayport_test_type_fops},
{"i915_dp_test_active", _displayport_test_active_fops},
{"i915_guc_log_control", _guc_log_control_fops},
+   {"i915_slpc_param_ctl", _slpc_param_ctl_fops},
{"i915_hpd_storm_ctl", _hpd_storm_ctl_fops},
{"i915_ipc_status", _ipc_status_fops}
 };
diff --git a/drivers/gpu/drm/i915/intel_slpc.c 
b/drivers/gpu/drm/i915/intel_slpc.c
index d0fd402..0c094f0 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -25,6 +25,8 @@
 #include 
 #include "i915_drv.h"
 #include "intel_uc.h"
+#include 
+#include 
 
 struct slpc_param slpc_paramlist[SLPC_MAX_PARAM] = {
{SLPC_PARAM_TASK_ENABLE_GTPERF, "Enable task GTPERF"},
@@ -684,3 +686,159 @@ void intel_slpc_disable(struct intel_slpc *slpc)
 
slpc->active = false;
 }
+
+static int slpc_param_ctl_show(struct seq_file *m, void *data)
+{
+   struct drm_i915_private *dev_priv = m->private;
+   struct intel_slpc *slpc = _priv->guc.slpc;
+
+   if (!slpc->active) {
+   seq_puts(m, "SLPC not active\n");
+   return 0;
+   }
+
+   seq_printf(m, "%s=%u, override=%s\n",
+   slpc_paramlist[slpc->debug_param_id].description,
+   slpc->debug_param_value,
+   yesno(!!slpc->debug_param_override));
+
+   return 0;
+}
+
+static int slpc_param_ctl_open(struct inode *inode, struct file *file)
+{
+   return single_open(file, slpc_param_ctl_show, inode->i_private);
+}
+
+static const char *read_token = "read", *write_token = "write",
+ *revert_token = "revert";
+
+/*
+ * Parse SLPC parameter control strings: (Similar to Pipe CRC handling)
+ *   command: wsp* op wsp+ param id wsp+ [value] wsp*
+ *   op: "read"/"write"/"revert"
+ *   param id: slpc_param_id
+ *   value: u32 value
+ *   wsp: (#0x20 | #0x9 | #0xA)+
+ *
+ * eg.:
+ *  "read 0"   -> read SLPC_PARAM_TASK_ENABLE_GTPERF
+ *  "write 7 500"  -> set SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ to 500MHz
+ *  "revert 7" -> revert SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ to
+ *default value.
+ */
+static int slpc_param_ctl_parse(char *buf, size_t len, char **op,
+   u32 *id, u32 *value)
+{
+#define MAX_WORDS 3
+   int n_words;
+   char *words[MAX_WORDS];
+   

[Intel-gfx] [PATCH 23/31] drm/i915/slpc: Add support for min/max frequency control

[Sagar Arun Kamble]

Update sysfs and debugfs functions to set SLPC
parameters when setting max/min frequency.

v1: Update for SLPC 2015.2.4 (params for both slice and unslice)
Replace HAS_SLPC with intel_slpc_active() (Paulo)

v2-v4: Rebase.

v5: Removed typecasting the frequency values to u32. (Chris)
Changed intel_slpc_active to guc.slpc.enabled. Carved out
SLPC helpers to set min and max frequencies.

v6: Rebase. Doing explicit SLPC reset on setting frequency to start sane
and covered with RPM get/put. Caching SLPC limits post enabling first.

v7: Rebase due to change in the dev_priv->pm.rps structure.

Signed-off-by: Tom O'Rourke 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 48 ---
 drivers/gpu/drm/i915/i915_sysfs.c   | 36 
 drivers/gpu/drm/i915/intel_slpc.c   | 56 +
 drivers/gpu/drm/i915/intel_slpc.h   |  5 
 4 files changed, 135 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 9356a69..dbfe185 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4381,7 +4381,13 @@ static ssize_t cur_wm_latency_write(struct file *file, 
const char __user *ubuf,
if (INTEL_GEN(dev_priv) < 6)
return -ENODEV;
 
-   *val = intel_gpu_freq(dev_priv, dev_priv->pm.rps.max_freq_softlimit);
+   if (intel_slpc_active(_priv->guc.slpc))
+   *val = intel_gpu_freq(dev_priv,
+ dev_priv->guc.slpc.max_unslice_freq);
+   else
+   *val = intel_gpu_freq(dev_priv,
+ dev_priv->pm.rps.max_freq_softlimit);
+
return 0;
 }
 
@@ -4398,20 +4404,32 @@ static ssize_t cur_wm_latency_write(struct file *file, 
const char __user *ubuf,
 
DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
 
+   intel_runtime_pm_get(dev_priv);
+
ret = mutex_lock_interruptible(_priv->pm.pcu_lock);
-   if (ret)
+   if (ret) {
+   intel_runtime_pm_put(dev_priv);
return ret;
+   }
 
/*
 * Turbo will still be enabled, but won't go above the set value.
 */
val = intel_freq_opcode(dev_priv, val);
 
+   if (intel_slpc_active(_priv->guc.slpc)) {
+   ret = intel_slpc_max_freq_set(_priv->guc.slpc, val);
+   mutex_unlock(_priv->pm.pcu_lock);
+   intel_runtime_pm_put(dev_priv);
+   return ret;
+   }
+
hw_max = rps->max_freq;
hw_min = rps->min_freq;
 
if (val < hw_min || val > hw_max || val < rps->min_freq_softlimit) {
mutex_unlock(_priv->pm.pcu_lock);
+   intel_runtime_pm_put(dev_priv);
return -EINVAL;
}
 
@@ -4422,6 +4440,8 @@ static ssize_t cur_wm_latency_write(struct file *file, 
const char __user *ubuf,
 
mutex_unlock(_priv->pm.pcu_lock);
 
+   intel_runtime_pm_put(dev_priv);
+
return 0;
 }
 
@@ -4437,7 +4457,13 @@ static ssize_t cur_wm_latency_write(struct file *file, 
const char __user *ubuf,
if (INTEL_GEN(dev_priv) < 6)
return -ENODEV;
 
-   *val = intel_gpu_freq(dev_priv, dev_priv->pm.rps.min_freq_softlimit);
+   if (intel_slpc_active(_priv->guc.slpc))
+   *val = intel_gpu_freq(dev_priv,
+ dev_priv->guc.slpc.min_unslice_freq);
+   else
+   *val = intel_gpu_freq(dev_priv,
+ dev_priv->pm.rps.min_freq_softlimit);
+
return 0;
 }
 
@@ -4453,21 +4479,33 @@ static ssize_t cur_wm_latency_write(struct file *file, 
const char __user *ubuf,
 
DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
 
+   intel_runtime_pm_get(dev_priv);
+
ret = mutex_lock_interruptible(_priv->pm.pcu_lock);
-   if (ret)
+   if (ret) {
+   intel_runtime_pm_put(dev_priv);
return ret;
+   }
 
/*
 * Turbo will still be enabled, but won't go below the set value.
 */
val = intel_freq_opcode(dev_priv, val);
 
+   if (intel_slpc_active(_priv->guc.slpc)) {
+   ret = intel_slpc_min_freq_set(_priv->guc.slpc, val);
+   mutex_unlock(_priv->pm.pcu_lock);
+   intel_runtime_pm_put(dev_priv);
+   return ret;
+   }
+
hw_max = dev_priv->pm.rps.max_freq;
hw_min = dev_priv->pm.rps.min_freq;
 
if (val < hw_min ||
val > hw_max || val > dev_priv->pm.rps.max_freq_softlimit) {
mutex_unlock(_priv->pm.pcu_lock);
+   intel_runtime_pm_put(dev_priv);
return -EINVAL;
}
 
@@ -4478,6 +4516,8 @@ static ssize_t cur_wm_latency_write(struct file *file, 
const char __user *ubuf,
 

[Intel-gfx] [PATCH 28/31] drm/i915/slpc: Add SKL SLPC Support

[Sagar Arun Kamble]

From: Tom O'Rourke 

This patch adds has_slpc to skylake info.

The SLPC interface has changed and could continue to
change. Only GuC versions known to be compatible are
supported here.

v1: Move slpc_version_check to intel_guc_ucode_init.
fix whitespace (Sagar)
Moved version check to different patch as has_slpc
should not be updated based on it. Instead module parameter
should be updated based on version check. (Sagar)
Added support to skylake_gt3 as well. (Sagar)

Reviewed-by: David Weinehall 
Signed-off-by: Tom O'Rourke 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/i915_pci.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 853002f..26eb673 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -426,6 +426,7 @@
.platform = INTEL_SKYLAKE, \
.has_csr = 1, \
.has_guc = 1, \
+   .has_slpc = 1, \
.ddb_size = 896
 
 static const struct intel_device_info intel_skylake_gt1_info __initconst = {
-- 
1.9.1

___
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[Intel-gfx] [PATCH 18/31] drm/i915/slpc: Add SLPC communication interfaces

[Sagar Arun Kamble]

Communication with SLPC is via Host to GuC interrupt through
shared data and parameters. This patch defines the structure of
shared data, parameters, data structure to be passed as input and
received as output from SLPC. This patch also defines the events
to be sent as input and status values output by GuC on processing
SLPC events. SLPC shared data has details of SKU type, Slice count,
IA Perf MSR values, SLPC state, Power source/plan, SLPC tasks status.
Parameters allow overriding task control, frequency range etc.

v1: fix whitespace (Sagar)

v2-v3: Rebase.

v4: Updated with GuC firmware v9.

v5: Added definition of input and output data structures for SLPC
events. Updated commit message.

v6: Removed definition of host2guc_slpc. Will be added in the next
patch that uses it. Commit subject update. Rebase.

v7: Added definition of SLPC_RESET_FLAG_TDR_OCCURRED to be sent
throgh SLPC reset in case of engine reset. Moved all Host/SLPC
interfaces from later patches to this patch. Commit message update.

v8: Updated value of SLPC_RESET_FLAG_TDR_OCCURRED.

Signed-off-by: Tom O'Rourke 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/intel_slpc.c |  39 +++
 drivers/gpu/drm/i915/intel_slpc.h | 207 ++
 2 files changed, 246 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_slpc.c 
b/drivers/gpu/drm/i915/intel_slpc.c
index 06abda5..a3db63c 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -25,6 +25,45 @@
 #include "i915_drv.h"
 #include "intel_uc.h"
 
+struct slpc_param slpc_paramlist[SLPC_MAX_PARAM] = {
+   {SLPC_PARAM_TASK_ENABLE_GTPERF, "Enable task GTPERF"},
+   {SLPC_PARAM_TASK_DISABLE_GTPERF, "Disable task GTPERF"},
+   {SLPC_PARAM_TASK_ENABLE_BALANCER, "Enable task BALANCER"},
+   {SLPC_PARAM_TASK_DISABLE_BALANCER, "Disable task BALANCER"},
+   {SLPC_PARAM_TASK_ENABLE_DCC, "Enable task DCC"},
+   {SLPC_PARAM_TASK_DISABLE_DCC, "Disable task DCC"},
+   {SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+   "Minimum GT frequency request for unslice"},
+   {SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
+   "Maximum GT frequency request for unslice"},
+   {SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ,
+   "Minimum GT frequency request for slice"},
+   {SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ,
+   "Maximum GT frequency request for slice"},
+   {SLPC_PARAM_GTPERF_THRESHOLD_MAX_FPS,
+   "If non-zero, algorithm will slow down "
+   "frame-based applications to this frame-rate"},
+   {SLPC_PARAM_GLOBAL_DISABLE_GT_FREQ_MANAGEMENT,
+   "Lock GT frequency request to RPe"},
+   {SLPC_PARAM_GTPERF_ENABLE_FRAMERATE_STALLING,
+   "Set to TRUE to enable slowing framerate"},
+   {SLPC_PARAM_GLOBAL_DISABLE_RC6_MODE_CHANGE,
+   "Prevent from changing the RC mode"},
+   {SLPC_PARAM_GLOBAL_OC_UNSLICE_FREQ_MHZ,
+   "Override fused value of unslice RP0"},
+   {SLPC_PARAM_GLOBAL_OC_SLICE_FREQ_MHZ,
+   "Override fused value of slice RP0"},
+   {SLPC_PARAM_GLOBAL_ENABLE_IA_GT_BALANCING,
+   "TRUE means enable Intelligent Bias Control"},
+   {SLPC_PARAM_GLOBAL_ENABLE_ADAPTIVE_BURST_TURBO,
+   "TRUE = enable eval mode when transitioning "
+   "from idle to active."},
+   {SLPC_PARAM_GLOBAL_ENABLE_EVAL_MODE,
+   "FALSE = disable eval mode completely"},
+   {SLPC_PARAM_GLOBAL_ENABLE_BALANCER_IN_NON_GAMING_MODE,
+   "Enable IBC when non-Gaming Mode is enabled"}
+};
+
 void intel_slpc_init(struct intel_slpc *slpc)
 {
 }
diff --git a/drivers/gpu/drm/i915/intel_slpc.h 
b/drivers/gpu/drm/i915/intel_slpc.h
index f68671f..ac4cb65 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -38,6 +38,213 @@ static inline bool intel_slpc_active(struct intel_slpc 
*slpc)
return slpc->active;
 }
 
+enum slpc_status {
+   SLPC_STATUS_OK = 0,
+   SLPC_STATUS_ERROR = 1,
+   SLPC_STATUS_ILLEGAL_COMMAND = 2,
+   SLPC_STATUS_INVALID_ARGS = 3,
+   SLPC_STATUS_INVALID_PARAMS = 4,
+   SLPC_STATUS_INVALID_DATA = 5,
+   SLPC_STATUS_OUT_OF_RANGE = 6,
+   SLPC_STATUS_NOT_SUPPORTED = 7,
+   SLPC_STATUS_NOT_IMPLEMENTED = 8,
+   SLPC_STATUS_NO_DATA = 9,
+   SLPC_STATUS_EVENT_NOT_REGISTERED = 10,
+   SLPC_STATUS_REGISTER_LOCKED = 11,
+   SLPC_STATUS_TEMPORARILY_UNAVAILABLE = 12,
+   SLPC_STATUS_VALUE_ALREADY_SET = 13,
+   SLPC_STATUS_VALUE_ALREADY_UNSET = 14,
+   SLPC_STATUS_VALUE_NOT_CHANGED = 15,
+   

[Intel-gfx] [PATCH 15/31] drm/i915/slpc: Sanitize GuC version

[Sagar Arun Kamble]

From: Tom O'Rourke 

The SLPC interface is dependent on GuC version.
Only GuC versions known to be compatible are supported here.

SLPC with GuC firmware v9 is supported with this series.

v1: Updated with modified sanitize_slpc_option in earlier patch.

v2-v3: Rebase.

v4: Updated support for GuC firmware v9.

v5: Commit subject updated.

v6: Commit subject and message update. Add support condition as >=v9.

v7: Sanitizing GuC version in intel_uc_init_fw for SLPC compatibility.
Added info. print for needed version and pointer to 01.org.

v8: s/FIRMWARE_URL/I915_FIRMWARE_URL, Macro added for SLPC required GuC
Major version and rearrangement for sanitization. (MichalW, Joonas)

v9: Checking major_ver_found to sanitize SLPC option enable_slpc post
fetching the firmware as with Custom firmware loaded through
guc_firmware_path parameter, major_ver_wanted are cleared. (Lukasz)

v10: Moved the I915_FIRMWARE_URL macro to intel_uc_common.h.

Signed-off-by: Tom O'Rourke 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/intel_csr.c| 15 ++-
 drivers/gpu/drm/i915/intel_guc.h|  1 +
 drivers/gpu/drm/i915/intel_guc_loader.c | 15 +++
 drivers/gpu/drm/i915/intel_uc.c |  1 +
 drivers/gpu/drm/i915/intel_uc_common.h  |  2 ++
 5 files changed, 25 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index 965988f..56c56f5 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -52,11 +52,6 @@
 MODULE_FIRMWARE(I915_CSR_BXT);
 #define BXT_CSR_VERSION_REQUIRED   CSR_VERSION(1, 7)
 
-#define FIRMWARE_URL  "https://01.org/linuxgraphics/downloads/firmware;
-
-
-
-
 #define CSR_MAX_FW_SIZE0x2FFF
 #define CSR_DEFAULT_FW_OFFSET  0x
 
@@ -309,11 +304,12 @@ static uint32_t *parse_csr_fw(struct drm_i915_private 
*dev_priv,
 
if (csr->version != required_version) {
DRM_INFO("Refusing to load DMC firmware v%u.%u,"
-" please use v%u.%u [" FIRMWARE_URL "].\n",
+" please use v%u.%u [%s].\n",
 CSR_VERSION_MAJOR(csr->version),
 CSR_VERSION_MINOR(csr->version),
 CSR_VERSION_MAJOR(required_version),
-CSR_VERSION_MINOR(required_version));
+CSR_VERSION_MINOR(required_version),
+I915_FIRMWARE_URL);
return NULL;
}
 
@@ -420,8 +416,9 @@ static void csr_load_work_fn(struct work_struct *work)
} else {
dev_notice(dev_priv->drm.dev,
   "Failed to load DMC firmware"
-  " [" FIRMWARE_URL "],"
-  " disabling runtime power management.\n");
+  " [%s],"
+  " disabling runtime power management.\n",
+  I915_FIRMWARE_URL);
}
 
release_firmware(fw);
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index a894991..3821bf2 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -159,6 +159,7 @@ static inline void intel_guc_init_early(struct intel_guc 
*guc)
 int intel_guc_select_fw(struct intel_guc *guc);
 int intel_guc_init_hw(struct intel_guc *guc);
 u32 intel_guc_wopcm_size(struct intel_guc *guc);
+void intel_guc_fetch_sanitize_options(struct intel_guc *guc);
 
 /* i915_guc_submission.c */
 int i915_guc_submission_init(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c 
b/drivers/gpu/drm/i915/intel_guc_loader.c
index 6ee7c16..4550620 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -64,6 +64,8 @@
 #define GLK_FW_MAJOR 10
 #define GLK_FW_MINOR 56
 
+#define I915_SLPC_REQUIRED_GUC_MAJOR 9
+
 #define GUC_FW_PATH(platform, major, minor) \
"i915/" __stringify(platform) "_guc_ver" __stringify(major) "_" 
__stringify(minor) ".bin"
 
@@ -418,3 +420,16 @@ int intel_guc_select_fw(struct intel_guc *guc)
 
return 0;
 }
+
+void intel_guc_fetch_sanitize_options(struct intel_guc *guc)
+{
+   if (guc->fw.major_ver_found <
+   I915_SLPC_REQUIRED_GUC_MAJOR) {
+   DRM_INFO("SLPC not supported with GuC firmware"
+" v%u, please use v%u+ [%s].\n",
+guc->fw.major_ver_found,
+I915_SLPC_REQUIRED_GUC_MAJOR,
+I915_FIRMWARE_URL);
+   i915.enable_slpc = 0;
+   }
+}
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index eeec986..350027f 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -194,6 +194,7 @@ static void 

[Intel-gfx] [PATCH 19/31] drm/i915/slpc: Allocate/Release/Initialize SLPC shared data

[Sagar Arun Kamble]

Populate SLPC shared data with required default values for
Slice count, Power source/plan, IA Perf MSRs.

v1: Update for SLPC interface version 2015.2.4
intel_slpc_active() returns 1 if slpc initialized (Paulo)
change default host_os to "Windows"
Spelling fixes (Sagar Kamble and Nick Hoath)
Added WARN for checking if upper 32bits of GTT offset
of shared object are zero. (ChrisW)
Changed function call from gem_allocate/release_guc_obj to
i915_guc_allocate/release_gem_obj. (Sagar)
Updated commit message and moved POWER_PLAN and POWER_SOURCE
definition from later patch. (Akash)
Add struct_mutex locking while allocating/releasing slpc shared
object. This was caught by CI BAT. Adding SLPC state variable
to determine if it is active as it not just dependent on shared
data setup.
Rebase with guc_allocate_vma related changes.

v2: WARN_ON for platform_sku validity and space changes.(David)
Checkpatch update.

v3: Fixing WARNING in igt@drv_module_reload_basic found in trybot BAT
with SLPC Enabled.

v4: Updated support for GuC v9. s/slice_total/hweight8(slice_mask)/(Dave).

v5: SLPC vma mapping changes and removed explicit type conversions.(Chris).
s/freq_unslice_max|min/unslice__max|min_freq.

v6: Commit message update. s/msr_value/val for reuse later.

v7: Set default values for tasks and min frequency parameters.
Moved initialization with allocation of data so that post GuC load
earlier parameters persist.

v8: Added check for SLPC status during cleanup of shared data. SLPC
disabling is asynchronous and should complete within 10us.

v9: Enabling Balancer task in SLPC.

Signed-off-by: Tom O'Rourke 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/intel_drv.h  |   1 +
 drivers/gpu/drm/i915/intel_pm.c   |   2 +-
 drivers/gpu/drm/i915/intel_slpc.c | 167 ++
 drivers/gpu/drm/i915/intel_slpc.h |   1 +
 4 files changed, 170 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 0cf04eb..df3d544 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1876,6 +1876,7 @@ bool chv_phy_powergate_ch(struct drm_i915_private 
*dev_priv, enum dpio_phy phy,
 void gen6_rps_idle(struct drm_i915_private *dev_priv);
 void gen6_rps_boost(struct drm_i915_gem_request *rq,
struct intel_rps_client *rps);
+void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv);
 void g4x_wm_get_hw_state(struct drm_device *dev);
 void vlv_wm_get_hw_state(struct drm_device *dev);
 void ilk_wm_get_hw_state(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e5607e5..6b2b7f8 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6486,7 +6486,7 @@ int sanitize_rc6_option(struct drm_i915_private 
*dev_priv, int enable_rc6)
return INTEL_RC6_ENABLE;
 }
 
-static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
+void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
 {
/* All of these values are in units of 50MHz */
 
diff --git a/drivers/gpu/drm/i915/intel_slpc.c 
b/drivers/gpu/drm/i915/intel_slpc.c
index a3db63c..73e7bf5 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -22,6 +22,7 @@
  *
  */
 #include 
+#include 
 #include "i915_drv.h"
 #include "intel_uc.h"
 
@@ -64,12 +65,178 @@ struct slpc_param slpc_paramlist[SLPC_MAX_PARAM] = {
"Enable IBC when non-Gaming Mode is enabled"}
 };
 
+static unsigned int slpc_get_platform_sku(struct drm_i915_private *dev_priv)
+{
+   enum slpc_platform_sku platform_sku;
+
+   if (IS_SKL_ULX(dev_priv))
+   platform_sku = SLPC_PLATFORM_SKU_ULX;
+   else if (IS_SKL_ULT(dev_priv))
+   platform_sku = SLPC_PLATFORM_SKU_ULT;
+   else
+   platform_sku = SLPC_PLATFORM_SKU_DT;
+
+   WARN_ON(platform_sku > 0xFF);
+
+   return platform_sku;
+}
+
+static unsigned int slpc_get_slice_count(struct drm_i915_private *dev_priv)
+{
+   unsigned int slice_count = 1;
+
+   if (IS_SKYLAKE(dev_priv))
+   slice_count = hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask);
+
+   return slice_count;
+}
+
+void slpc_mem_set_param(struct slpc_shared_data *data,
+ u32 id,
+ u32 value)
+{
+   data->override_parameters_set_bits[id >> 5]
+   |= (1 << (id % 32));
+   data->override_parameters_values[id] = value;
+}
+
+void slpc_mem_unset_param(struct slpc_shared_data *data,
+   u32 id)
+{
+   data->override_parameters_set_bits[id >> 5]
+   &= (~(1 << (id % 32)));
+   

[Intel-gfx] [PATCH 14/31] drm/i915/slpc: Add enable_slpc module parameter

[Sagar Arun Kamble]

From: Tom O'Rourke 

i915.enable_slpc is used to override the default for slpc usage.
The expected values are -1=auto, 0=disabled [default], 1=enabled.

Sanitize i915.enable_slpc to either 0 or 1 based on HAS_SLPC() and
GuC load and submission options.

v1: Add early call to sanitize enable_slpc in intel_guc_ucode_init
Remove sanitize enable_slpc call before firmware version check
is performed. (ChrisW)
Version check is added in next patch and that will be done as
part of slpc_enable_sanitize function in the next patch. (Sagar)
Updated slpc option sanitize function call for platforms without
GuC support. This was caught by CI BAT.

v2: Changed parameter to dev_priv for HAS_SLPC macro. (David)
Code indentation based on checkpatch.

v3: Rebase.

v4: Moved sanitization of SLPC option post GuC load.

v5: Removed function intel_slpc_enabled. Planning to rely only on
kernel parameter. Moved sanitization prior to GuC load to use the
parameter during SLPC state setup during to GuC load. (Sagar)

v6: Commit message update. Rebase.

v7: Moved SLPC option sanitization to intel_uc_sanitize_options.

v8: Clearing SLPC option on GuC load failure. Change moved from later
patch. (Sagar)

Suggested-by: Paulo Zanoni 
Signed-off-by: Tom O'Rourke 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/i915_params.c |  5 +
 drivers/gpu/drm/i915/i915_params.h |  1 +
 drivers/gpu/drm/i915/intel_uc.c| 15 +++
 3 files changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index d32d761..a14db53 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -43,6 +43,7 @@ struct i915_params i915 __read_mostly = {
.enable_dc = -1,
.enable_fbc = -1,
.enable_execlists = -1,
+   .enable_slpc = 0,
.enable_hangcheck = true,
.enable_ppgtt = -1,
.enable_psr = -1,
@@ -139,6 +140,10 @@ struct i915_params i915 __read_mostly = {
"Override execlists usage. "
"(-1=auto [default], 0=disabled, 1=enabled)");
 
+i915_param_named_unsafe(enable_slpc, int, 0400,
+   "Override single-loop-power-controller (slpc) usage. "
+   "(-1=auto, 0=disabled [default], 1=enabled)");
+
 i915_param_named_unsafe(enable_psr, int, 0600,
"Enable PSR "
"(0=disabled, 1=enabled - link mode chosen per-platform, 2=force 
link-standby mode, 3=force link-off mode) "
diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index ac84470..d5c7bfb 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -41,6 +41,7 @@
func(int, enable_ppgtt); \
func(int, enable_execlists); \
func(int, enable_psr); \
+   func(int, enable_slpc); \
func(int, disable_power_well); \
func(int, enable_ips); \
func(int, invert_brightness); \
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index bb31243..eeec986 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -69,6 +69,7 @@ void intel_uc_sanitize_options(struct drm_i915_private 
*dev_priv)
 
i915.enable_guc_loading = 0;
i915.enable_guc_submission = 0;
+   i915.enable_slpc = 0;
return;
}
 
@@ -92,6 +93,18 @@ void intel_uc_sanitize_options(struct drm_i915_private 
*dev_priv)
/* A negative value means "use platform default" */
if (i915.enable_guc_submission < 0)
i915.enable_guc_submission = HAS_GUC_SCHED(dev_priv);
+
+   /* slpc requires hardware support and compatible firmware */
+   if (!HAS_SLPC(dev_priv))
+   i915.enable_slpc = 0;
+
+   /* slpc requires guc loaded */
+   if (!i915.enable_guc_loading)
+   i915.enable_slpc = 0;
+
+   /* slpc requires guc submission */
+   if (!i915.enable_guc_submission)
+   i915.enable_slpc = 0;
 }
 
 void intel_uc_init_early(struct drm_i915_private *dev_priv)
@@ -400,6 +413,8 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
i915.enable_guc_loading = 0;
DRM_NOTE("GuC firmware loading disabled\n");
 
+   i915.enable_slpc = 0;
+
return ret;
 }
 
-- 
1.9.1

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[Intel-gfx] [PATCH 10/31] drm/i915: Create generic functions to control RC6, RPS

[Sagar Arun Kamble]

Prepared generic functions intel_enable_rc6, intel_disable_rc6,
intel_enable_rps and intel_disable_rps functions to setup RC6/RPS
based on platforms.

Cc: Imre Deak 
Cc: Chris Wilson 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/intel_pm.c | 95 ++---
 1 file changed, 61 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 54e7577..0c46f81 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7981,74 +7981,101 @@ void intel_sanitize_gt_powersave(struct 
drm_i915_private *dev_priv)
gen6_reset_rps_interrupts(dev_priv);
 }
 
-void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
+void intel_disable_rc6(struct drm_i915_private *dev_priv)
 {
-   if (!READ_ONCE(dev_priv->pm.rps.enabled))
-   return;
-
-   mutex_lock(_priv->pm.pcu_lock);
-
-   if (INTEL_GEN(dev_priv) >= 9) {
+   if (INTEL_GEN(dev_priv) >= 9)
gen9_disable_rc6(dev_priv);
-   gen9_disable_rps(dev_priv);
-   } else if (IS_CHERRYVIEW(dev_priv)) {
+   else if (IS_CHERRYVIEW(dev_priv))
cherryview_disable_rc6(dev_priv);
-   cherryview_disable_rps(dev_priv);
-   } else if (IS_VALLEYVIEW(dev_priv)) {
+   else if (IS_VALLEYVIEW(dev_priv))
valleyview_disable_rc6(dev_priv);
-   valleyview_disable_rps(dev_priv);
-   } else if (INTEL_GEN(dev_priv) >= 6) {
+   else if (INTEL_GEN(dev_priv) >= 6)
gen6_disable_rc6(dev_priv);
+}
+
+void intel_disable_rps(struct drm_i915_private *dev_priv)
+{
+   if (INTEL_GEN(dev_priv) >= 9)
+   gen9_disable_rps(dev_priv);
+   else if (IS_CHERRYVIEW(dev_priv))
+   cherryview_disable_rps(dev_priv);
+   else if (IS_VALLEYVIEW(dev_priv))
+   valleyview_disable_rps(dev_priv);
+   else if (INTEL_GEN(dev_priv) >= 6)
gen6_disable_rps(dev_priv);
-   }  else if (IS_IRONLAKE_M(dev_priv)) {
+   else if (IS_IRONLAKE_M(dev_priv))
ironlake_disable_drps(dev_priv);
-   }
-
-   dev_priv->pm.rps.enabled = false;
-   mutex_unlock(_priv->pm.pcu_lock);
 }
 
-void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
+void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
 {
-   /* We shouldn't be disabling as we submit, so this should be less
-* racy than it appears!
-*/
-   if (READ_ONCE(dev_priv->pm.rps.enabled))
-   return;
-
-   /* Powersaving is controlled by the host when inside a VM */
-   if (intel_vgpu_active(dev_priv))
+   if (!READ_ONCE(dev_priv->pm.rps.enabled))
return;
 
mutex_lock(_priv->pm.pcu_lock);
 
-   if (IS_CHERRYVIEW(dev_priv)) {
+   intel_disable_rc6(dev_priv);
+   intel_disable_rps(dev_priv);
+
+   dev_priv->pm.rps.enabled = false;
+   mutex_unlock(_priv->pm.pcu_lock);
+}
+
+void intel_enable_rc6(struct drm_i915_private *dev_priv)
+{
+   if (IS_CHERRYVIEW(dev_priv))
cherryview_enable_rc6(dev_priv);
+   else if (IS_VALLEYVIEW(dev_priv))
+   valleyview_enable_rc6(dev_priv);
+   else if (INTEL_GEN(dev_priv) >= 9)
+   gen9_enable_rc6(dev_priv);
+   else if (IS_BROADWELL(dev_priv))
+   gen8_enable_rc6(dev_priv);
+   else if (INTEL_GEN(dev_priv) >= 6)
+   gen6_enable_rc6(dev_priv);
+}
+
+void intel_enable_rps(struct drm_i915_private *dev_priv)
+{
+   if (IS_CHERRYVIEW(dev_priv)) {
cherryview_enable_rps(dev_priv);
} else if (IS_VALLEYVIEW(dev_priv)) {
-   valleyview_enable_rc6(dev_priv);
valleyview_enable_rps(dev_priv);
} else if (INTEL_GEN(dev_priv) >= 9) {
-   gen9_enable_rc6(dev_priv);
gen9_enable_rps(dev_priv);
} else if (IS_BROADWELL(dev_priv)) {
-   gen8_enable_rc6(dev_priv);
gen8_enable_rps(dev_priv);
} else if (INTEL_GEN(dev_priv) >= 6) {
-   gen6_enable_rc6(dev_priv);
gen6_enable_rps(dev_priv);
} else if (IS_IRONLAKE_M(dev_priv)) {
ironlake_enable_drps(dev_priv);
intel_init_emon(dev_priv);
}
 
-   intel_update_ring_freq(dev_priv);
-
WARN_ON(dev_priv->pm.rps.max_freq < dev_priv->pm.rps.min_freq);
WARN_ON(dev_priv->pm.rps.idle_freq > dev_priv->pm.rps.max_freq);
 
WARN_ON(dev_priv->pm.rps.efficient_freq < dev_priv->pm.rps.min_freq);
WARN_ON(dev_priv->pm.rps.efficient_freq > dev_priv->pm.rps.max_freq);
+}
+
+void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
+{
+   /* We shouldn't be disabling as we submit, so this should be less
+* racy than it appears!
+*/
+   if 

[Intel-gfx] [PATCH 16/31] drm/i915/slpc: Lay out SLPC init/enable/disable/cleanup helpers

[Sagar Arun Kamble]

SLPC operates based on parameters setup in shared data between
i915 and GuC SLPC. This is to be created/initialized in intel_slpc_init.
From there onwards i915 can control the SLPC operations by Enabling,
Disabling complete SLPC or changing SLPC parameters. During cleanup
SLPC shared data has to be freed.
With this patch on platforms with SLPC support we call intel_slpc_*()
functions from GuC setup functions and do not use Host rps functions.
With SLPC, intel_enable_gt_powersave will only handle RC6. In the later
patch intel_init_gt_powersave will check if SLPC has started running
through shared data and update initial state that i915 needs like
frequency limits if needed.

v1: Return void instead of ignored error code (Paulo)
enable/disable RC6 in SLPC flows (Sagar)
replace HAS_SLPC() use with intel_slpc_enabled()
or intel_slpc_active() (Paulo)
Fix for renaming gen9_disable_rps to gen9_disable_rc6 in
"drm/i915/bxt: Explicitly clear the Turbo control register"
Defer RC6 and SLPC enabling to intel_gen6_powersave_work. (Sagar)
Performance drop with SLPC was happening as ring frequency table
was not programmed when SLPC was enabled. This patch programs ring
frequency table with SLPC. Initial reset of SLPC is based on kernel
parameter as planning to add slpc state in intel_slpc_active. Cleanup
is also based on kernel parameter as SLPC gets disabled in
disable/suspend.(Sagar)

v2: Usage of INTEL_GEN instead of INTEL_INFO->gen (David)
Checkpatch update.

v3: Rebase

v4: Removed reset functions to comply with *_gt_powersave routines.
(Sagar)

v5: Removed intel_slpc_active. Relying on slpc.active for control flows
that are based on SLPC active status in GuC. State setup/cleanup needed
for SLPC is handled using kernel parameter i915.enable_slpc. Moved SLPC
init and enabling to GuC enable path as SLPC in GuC can start doing the
setup post GuC init. Commit message update. (Sagar)

v6: Rearranged function definitions.

v7: Makefile rearrangement. Reducing usage of i915.enable_slpc and relying
mostly on rps.rps_enabled to bypass Host RPS flows. Commit message
update.

v8: Changed parameters for SLPC functions to struct intel_slpc*.

v9: Reinstated intel_slpc_active and intel_slpc_enabled as they are more
meaningful.

v10: Rebase changes due to creation of intel_guc.h. Updates in
 intel_guc_cleanup w.r.t slpc cleanup.

Signed-off-by: Tom O'Rourke 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/Makefile |  1 +
 drivers/gpu/drm/i915/i915_drv.h   | 12 ++
 drivers/gpu/drm/i915/intel_guc.c  |  3 +++
 drivers/gpu/drm/i915/intel_guc.h  |  3 +++
 drivers/gpu/drm/i915/intel_pm.c   | 19 +++-
 drivers/gpu/drm/i915/intel_slpc.c | 42 ++
 drivers/gpu/drm/i915/intel_slpc.h | 47 +++
 drivers/gpu/drm/i915/intel_uc.c   | 20 +
 8 files changed, 142 insertions(+), 5 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_slpc.c
 create mode 100644 drivers/gpu/drm/i915/intel_slpc.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index d1327f6..62bf4f6e 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -64,6 +64,7 @@ i915-y += intel_uc.o \
  intel_guc_log.o \
  intel_guc_loader.o \
  intel_huc.o \
+ intel_slpc.o \
  i915_guc_submission.o
 
 # autogenerated null render state
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 428cb1c..af633c6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2748,6 +2748,18 @@ static inline struct drm_i915_private 
*guc_to_i915(struct intel_guc *guc)
return container_of(guc, struct drm_i915_private, guc);
 }
 
+static inline struct intel_guc *slpc_to_guc(struct intel_slpc *slpc)
+{
+   return container_of(slpc, struct intel_guc, slpc);
+}
+
+static inline struct drm_i915_private *slpc_to_i915(struct intel_slpc *slpc)
+{
+   struct intel_guc *guc = slpc_to_guc(slpc);
+
+   return guc_to_i915(guc);
+}
+
 static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc)
 {
return container_of(huc, struct drm_i915_private, huc);
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index f4dc708..a92c7e8 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -226,6 +226,9 @@ void intel_guc_cleanup(struct intel_guc *guc)
 
if (i915.enable_guc_submission)
i915_guc_submission_cleanup(dev_priv);
+
+   if (intel_slpc_enabled())
+   intel_slpc_cleanup(>slpc);
 }
 
 /**
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 3821bf2..b835d30 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h

[Intel-gfx] [PATCH 12/31] drm/i915: Define RPS idle, busy, boost function pointers

[Sagar Arun Kamble]

These will allow to define nop functions when SLPC is in use.
Initialized with gen6_rps_idle, gen6_rps_busy and gen6_rps_boost
during intel_enable_rps.

Cc: Imre Deak 
Cc: Chris Wilson 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/i915_drv.h |  5 +
 drivers/gpu/drm/i915/i915_gem.c |  6 +++---
 drivers/gpu/drm/i915/i915_gem_request.c |  2 +-
 drivers/gpu/drm/i915/intel_display.c|  2 +-
 drivers/gpu/drm/i915/intel_pm.c | 24 
 5 files changed, 34 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a09952d..5fcebb8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1350,6 +1350,11 @@ struct intel_rps {
 
/* manual wa residency calculations */
struct intel_rps_ei ei;
+
+   void (*idle)(struct drm_i915_private *dev_priv);
+   void (*busy)(struct drm_i915_private *dev_priv);
+   void (*boost)(struct drm_i915_gem_request *rq,
+ struct intel_rps_client *rps);
 };
 
 struct intel_rc6 {
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 76e1bb2..efea38a 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -388,7 +388,7 @@ int i915_gem_object_unbind(struct drm_i915_gem_object *obj)
 */
if (rps) {
if (INTEL_GEN(rq->i915) >= 6)
-   gen6_rps_boost(rq, rps);
+   rq->i915->pm.rps.boost(rq, rps);
else
rps = NULL;
}
@@ -2991,7 +2991,7 @@ void i915_gem_reset(struct drm_i915_private *dev_priv)
intel_sanitize_gt_powersave(dev_priv);
intel_enable_gt_powersave(dev_priv);
if (INTEL_GEN(dev_priv) >= 6)
-   gen6_rps_busy(dev_priv);
+   dev_priv->pm.rps.busy(dev_priv);
}
 }
 
@@ -3199,7 +3199,7 @@ bool i915_gem_unset_wedged(struct drm_i915_private *i915)
rearm_hangcheck = false;
 
if (INTEL_GEN(dev_priv) >= 6)
-   gen6_rps_idle(dev_priv);
+   dev_priv->pm.rps.idle(dev_priv);
intel_runtime_pm_put(dev_priv);
 out_unlock:
mutex_unlock(>struct_mutex);
diff --git a/drivers/gpu/drm/i915/i915_gem_request.c 
b/drivers/gpu/drm/i915/i915_gem_request.c
index 023af2d..8ebd660 100644
--- a/drivers/gpu/drm/i915/i915_gem_request.c
+++ b/drivers/gpu/drm/i915/i915_gem_request.c
@@ -257,7 +257,7 @@ static void mark_busy(struct drm_i915_private *i915)
intel_enable_gt_powersave(i915);
i915_update_gfx_val(i915);
if (INTEL_GEN(i915) >= 6)
-   gen6_rps_busy(i915);
+   i915->pm.rps.busy(i915);
 
queue_delayed_work(i915->wq,
   >gt.retire_work,
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index eb53093..7505e3e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12607,7 +12607,7 @@ static int do_rps_boost(struct wait_queue_entry *_wait,
struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
struct drm_i915_gem_request *rq = wait->request;
 
-   gen6_rps_boost(rq, NULL);
+   rq->i915->pm.rps.boost(rq, NULL);
i915_gem_request_put(rq);
 
drm_crtc_vblank_put(wait->crtc);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ac20dbf..20ec8f4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7889,6 +7889,22 @@ static inline void intel_update_ring_freq(struct 
drm_i915_private *i915)
}
 }
 
+static void rps_idle_nop(struct drm_i915_private *dev_priv)
+{
+   DRM_DEBUG_DRIVER("\n");
+}
+
+static void rps_busy_nop(struct drm_i915_private *dev_priv)
+{
+   DRM_DEBUG_DRIVER("\n");
+}
+
+static void rps_boost_nop(struct drm_i915_gem_request *rq,
+ struct intel_rps_client *rps)
+{
+   DRM_DEBUG_DRIVER("\n");
+}
+
 void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
 {
struct intel_rps *rps = _priv->pm.rps;
@@ -7943,6 +7959,10 @@ void intel_init_gt_powersave(struct drm_i915_private 
*dev_priv)
/* Finally allow us to boost to max by default */
rps->boost_freq = rps->max_freq;
 
+   dev_priv->pm.rps.idle = rps_idle_nop;
+   dev_priv->pm.rps.busy = rps_busy_nop;
+   dev_priv->pm.rps.boost = rps_boost_nop;
+
mutex_unlock(_priv->pm.pcu_lock);
mutex_unlock(_priv->drm.struct_mutex);
 
@@ -8064,6 +8084,10 @@ void intel_enable_rps(struct drm_i915_private *dev_priv)
if (READ_ONCE(dev_priv->pm.rps.enabled))
return;
 
+   dev_priv->pm.rps.idle = gen6_rps_idle;
+   dev_priv->pm.rps.busy = gen6_rps_busy;
+   dev_priv->pm.rps.boost = 

[Intel-gfx] [PATCH 07/31] drm/i915: Name structure in dev_priv that contains RPS/RC6 state as "pm"

[Sagar Arun Kamble]

Prepared substructure rps for RPS related state. autoenable_work and
pcu_lock are used for RC6 hence they are defined outside rps structure.
Renamed the RPS lock as pcu_lock.

Cc: Chris Wilson 
Cc: Imre Deak 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/i915_debugfs.c| 117 +-
 drivers/gpu/drm/i915/i915_drv.c|   2 +-
 drivers/gpu/drm/i915/i915_drv.h|  12 +-
 drivers/gpu/drm/i915/i915_gem_request.c|   2 +-
 drivers/gpu/drm/i915/i915_guc_submission.c |   8 +-
 drivers/gpu/drm/i915/i915_irq.c|  86 +++
 drivers/gpu/drm/i915/i915_sysfs.c  |  70 +++---
 drivers/gpu/drm/i915/intel_cdclk.c |  40 ++--
 drivers/gpu/drm/i915/intel_display.c   |  12 +-
 drivers/gpu/drm/i915/intel_drv.h   |   2 +-
 drivers/gpu/drm/i915/intel_pm.c| 363 +++--
 drivers/gpu/drm/i915/intel_runtime_pm.c|  16 +-
 drivers/gpu/drm/i915/intel_sideband.c  |   6 +-
 13 files changed, 379 insertions(+), 357 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 8126c2c..9356a69 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1026,6 +1026,7 @@ static int i915_error_state_open(struct inode *inode, 
struct file *file)
 static int i915_frequency_info(struct seq_file *m, void *unused)
 {
struct drm_i915_private *dev_priv = node_to_i915(m->private);
+   struct intel_rps *rps = _priv->pm.rps;
int ret = 0;
 
intel_runtime_pm_get(dev_priv);
@@ -1043,7 +1044,7 @@ static int i915_frequency_info(struct seq_file *m, void 
*unused)
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
u32 freq_sts;
 
-   mutex_lock(_priv->rps.hw_lock);
+   mutex_lock(_priv->pm.pcu_lock);
freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
@@ -1052,21 +1053,21 @@ static int i915_frequency_info(struct seq_file *m, void 
*unused)
   intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
 
seq_printf(m, "current GPU freq: %d MHz\n",
-  intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
+  intel_gpu_freq(dev_priv, rps->cur_freq));
 
seq_printf(m, "max GPU freq: %d MHz\n",
-  intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
+  intel_gpu_freq(dev_priv, rps->max_freq));
 
seq_printf(m, "min GPU freq: %d MHz\n",
-  intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
+  intel_gpu_freq(dev_priv, rps->min_freq));
 
seq_printf(m, "idle GPU freq: %d MHz\n",
-  intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
+  intel_gpu_freq(dev_priv, rps->idle_freq));
 
seq_printf(m,
   "efficient (RPe) frequency: %d MHz\n",
-  intel_gpu_freq(dev_priv, 
dev_priv->rps.efficient_freq));
-   mutex_unlock(_priv->rps.hw_lock);
+  intel_gpu_freq(dev_priv, rps->efficient_freq));
+   mutex_unlock(_priv->pm.pcu_lock);
} else if (INTEL_GEN(dev_priv) >= 6) {
u32 rp_state_limits;
u32 gt_perf_status;
@@ -1146,7 +1147,7 @@ static int i915_frequency_info(struct seq_file *m, void 
*unused)
seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, 
MASK=0x%08x\n",
   pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
-  dev_priv->rps.pm_intrmsk_mbz);
+  rps->pm_intrmsk_mbz);
seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
seq_printf(m, "Render p-state ratio: %d\n",
   (gt_perf_status & (INTEL_GEN(dev_priv) >= 9 ? 
0x1ff00 : 0xff00)) >> 8);
@@ -1166,8 +1167,7 @@ static int i915_frequency_info(struct seq_file *m, void 
*unused)
   rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
seq_printf(m, "RP PREV UP: %d (%dus)\n",
   rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
-   seq_printf(m, "Up threshold: %d%%\n",
-  dev_priv->rps.up_threshold);
+   seq_printf(m, "Up threshold: %d%%\n", rps->up_threshold);
 
seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
   rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
@@ -1175,8 +1175,7 @@ static int i915_frequency_info(struct seq_file 

[Intel-gfx] [PATCH 08/31] drm/i915: Rename intel_enable_rc6 to intel_rc6_enabled

[Sagar Arun Kamble]

This function gives the status of RC6, whether disabled or if
enabled then which state. intel_enable_rc6 will be used for
enabling RC6 in the next patch.

Cc: Chris Wilson 
Cc: Imre Deak 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/i915_drv.c   |  2 +-
 drivers/gpu/drm/i915/i915_sysfs.c |  2 +-
 drivers/gpu/drm/i915/intel_drv.h  |  2 +-
 drivers/gpu/drm/i915/intel_guc.c  |  3 ++-
 drivers/gpu/drm/i915/intel_pm.c   | 12 ++--
 5 files changed, 11 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 6cc1162..a6dbad3 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2486,7 +2486,7 @@ static int intel_runtime_suspend(struct device *kdev)
struct drm_i915_private *dev_priv = to_i915(dev);
int ret;
 
-   if (WARN_ON_ONCE(!(dev_priv->pm.rps.enabled && intel_enable_rc6(
+   if (WARN_ON_ONCE(!(dev_priv->pm.rps.enabled && intel_rc6_enabled(
return -ENODEV;
 
if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c 
b/drivers/gpu/drm/i915/i915_sysfs.c
index c16e907..8add849 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -49,7 +49,7 @@ static u32 calc_residency(struct drm_i915_private *dev_priv,
 static ssize_t
 show_rc6_mask(struct device *kdev, struct device_attribute *attr, char *buf)
 {
-   return snprintf(buf, PAGE_SIZE, "%x\n", intel_enable_rc6());
+   return snprintf(buf, PAGE_SIZE, "%x\n", intel_rc6_enabled());
 }
 
 static ssize_t
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f7db720..0cf04eb 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1900,7 +1900,7 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc 
*intel_crtc,
  struct intel_crtc_state *cstate);
 void intel_init_ipc(struct drm_i915_private *dev_priv);
 void intel_enable_ipc(struct drm_i915_private *dev_priv);
-static inline int intel_enable_rc6(void)
+static inline int intel_rc6_enabled(void)
 {
return i915.enable_rc6;
 }
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index c731cff..f4dc708 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -128,7 +128,8 @@ int intel_guc_sample_forcewake(struct intel_guc *guc)
 
action[0] = INTEL_GUC_ACTION_SAMPLE_FORCEWAKE;
/* WaRsDisableCoarsePowerGating:skl,bxt */
-   if (!intel_enable_rc6() || NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
+   if (!intel_rc6_enabled() ||
+   NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
action[1] = 0;
else
/* bit 0 and 1 are for Render and Media domain separately */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b89677a..b83751e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6606,7 +6606,7 @@ static void gen9_enable_rc6(struct drm_i915_private 
*dev_priv)
I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
 
/* 3a: Enable RC6 */
-   if (intel_enable_rc6() & INTEL_RC6_ENABLE)
+   if (intel_rc6_enabled() & INTEL_RC6_ENABLE)
rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
@@ -6655,7 +6655,7 @@ static void gen8_enable_rc6(struct drm_i915_private 
*dev_priv)
I915_WRITE(GEN6_RC6_THRESHOLD, 5); /* 50/125ms per EI */
 
/* 3: Enable RC6 */
-   if (intel_enable_rc6() & INTEL_RC6_ENABLE)
+   if (intel_rc6_enabled() & INTEL_RC6_ENABLE)
rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
intel_print_rc6_info(dev_priv, rc6_mask);
I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
@@ -6749,7 +6749,7 @@ static void gen6_enable_rc6(struct drm_i915_private 
*dev_priv)
I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
 
/* Check if we are enabling RC6 */
-   rc6_mode = intel_enable_rc6();
+   rc6_mode = intel_rc6_enabled();
if (rc6_mode & INTEL_RC6_ENABLE)
rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
 
@@ -7251,7 +7251,7 @@ static void cherryview_enable_rc6(struct drm_i915_private 
*dev_priv)
pcbr = I915_READ(VLV_PCBR);
 
/* 3: Enable RC6 */
-   if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
+   if ((intel_rc6_enabled() & INTEL_RC6_ENABLE) &&
(pcbr >> VLV_PCBR_ADDR_SHIFT))
rc6_mode = GEN7_RC_CTL_TO_MODE;
 
@@ -7345,7 +7345,7 @@ static void valleyview_enable_rc6(struct drm_i915_private 
*dev_priv)
  VLV_MEDIA_RC6_COUNT_EN |
  

[Intel-gfx] [PATCH 02/31] drm/i915: Separate RPS and RC6 handling for gen6+

[Sagar Arun Kamble]

This patch separates enable/disable of RC6 and RPS for gen6+
platforms prior to VLV.

Cc: Imre Deak 
Cc: Chris Wilson 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 17 +++---
 drivers/gpu/drm/i915/intel_pm.c | 44 +
 2 files changed, 38 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index ca6fa6d..3e4677b 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1136,6 +1136,13 @@ static int i915_frequency_info(struct seq_file *m, void 
*unused)
pm_iir = I915_READ(GEN8_GT_IIR(2));
pm_mask = I915_READ(GEN6_PMINTRMSK);
}
+   seq_printf(m, "Video Turbo Mode: %s\n",
+  yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
+   seq_printf(m, "HW control enabled: %s\n",
+  yesno(rpmodectl & GEN6_RP_ENABLE));
+   seq_printf(m, "SW control enabled: %s\n",
+  yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==
+ GEN6_RP_MEDIA_SW_MODE));
seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, 
MASK=0x%08x\n",
   pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
@@ -1479,7 +1486,7 @@ static int vlv_drpc_info(struct seq_file *m)
 static int gen6_drpc_info(struct seq_file *m)
 {
struct drm_i915_private *dev_priv = node_to_i915(m->private);
-   u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
+   u32 gt_core_status, rcctl1, rc6vids = 0;
u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
unsigned forcewake_count;
int count = 0;
@@ -1498,7 +1505,6 @@ static int gen6_drpc_info(struct seq_file *m)
gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
 
-   rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
rcctl1 = I915_READ(GEN6_RC_CONTROL);
if (INTEL_GEN(dev_priv) >= 9) {
gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
@@ -1509,13 +1515,6 @@ static int gen6_drpc_info(struct seq_file *m)
sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, );
mutex_unlock(_priv->rps.hw_lock);
 
-   seq_printf(m, "Video Turbo Mode: %s\n",
-  yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
-   seq_printf(m, "HW control enabled: %s\n",
-  yesno(rpmodectl1 & GEN6_RP_ENABLE));
-   seq_printf(m, "SW control enabled: %s\n",
-  yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
- GEN6_RP_MEDIA_SW_MODE));
seq_printf(m, "RC1e Enabled: %s\n",
   yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
seq_printf(m, "RC6 Enabled: %s\n",
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index adfeb7b..f78a1e8 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6326,9 +6326,13 @@ static void gen9_disable_rps(struct drm_i915_private 
*dev_priv)
I915_WRITE(GEN6_RP_CONTROL, 0);
 }
 
-static void gen6_disable_rps(struct drm_i915_private *dev_priv)
+static void gen6_disable_rc6(struct drm_i915_private *dev_priv)
 {
I915_WRITE(GEN6_RC_CONTROL, 0);
+}
+
+static void gen6_disable_rps(struct drm_i915_private *dev_priv)
+{
I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
I915_WRITE(GEN6_RP_CONTROL, 0);
 }
@@ -6686,7 +6690,7 @@ static void gen8_enable_rps(struct drm_i915_private 
*dev_priv)
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 }
 
-static void gen6_enable_rps(struct drm_i915_private *dev_priv)
+static void gen6_enable_rc6(struct drm_i915_private *dev_priv)
 {
struct intel_engine_cs *engine;
enum intel_engine_id id;
@@ -6697,12 +6701,6 @@ static void gen6_enable_rps(struct drm_i915_private 
*dev_priv)
 
WARN_ON(!mutex_is_locked(_priv->rps.hw_lock));
 
-   /* Here begins a magic sequence of register writes to enable
-* auto-downclocking.
-*
-* Perhaps there might be some value in exposing these to
-* userspace...
-*/
I915_WRITE(GEN6_RC_STATE, 0);
 
/* Clear the DBG now so we don't confuse earlier errors */
@@ -6756,12 +6754,6 @@ static void gen6_enable_rps(struct drm_i915_private 
*dev_priv)
   GEN6_RC_CTL_EI_MODE(1) |
   GEN6_RC_CTL_HW_ENABLE);
 
-   /* Power down if completely idle for over 50ms */
-   I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 5);
-   I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
-
-   reset_rps(dev_priv, gen6_set_rps);
-
rc6vids = 0;
ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, 

[Intel-gfx] [PATCH 05/31] drm/i915: Separate RPS and RC6 handling for CHV

[Sagar Arun Kamble]

This patch separates enable/disable of RC6 and RPS for CHV.

Cc: Imre Deak 
Cc: Chris Wilson 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/intel_pm.c | 29 -
 1 file changed, 24 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8bbe037..f8bfcff 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6337,11 +6337,16 @@ static void gen6_disable_rps(struct drm_i915_private 
*dev_priv)
I915_WRITE(GEN6_RP_CONTROL, 0);
 }
 
-static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
+static void cherryview_disable_rc6(struct drm_i915_private *dev_priv)
 {
I915_WRITE(GEN6_RC_CONTROL, 0);
 }
 
+static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
+{
+   I915_WRITE(GEN6_RP_CONTROL, 0);
+}
+
 static void valleyview_disable_rc6(struct drm_i915_private *dev_priv)
 {
/* we're doing forcewake before Disabling RC6,
@@ -7196,11 +7201,11 @@ static void valleyview_cleanup_gt_powersave(struct 
drm_i915_private *dev_priv)
valleyview_cleanup_pctx(dev_priv);
 }
 
-static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
+static void cherryview_enable_rc6(struct drm_i915_private *dev_priv)
 {
struct intel_engine_cs *engine;
enum intel_engine_id id;
-   u32 gtfifodbg, val, rc6_mode = 0, pcbr;
+   u32 gtfifodbg, rc6_mode = 0, pcbr;
 
WARN_ON(!mutex_is_locked(_priv->rps.hw_lock));
 
@@ -7249,7 +7254,19 @@ static void cherryview_enable_rps(struct 
drm_i915_private *dev_priv)
 
I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
 
-   /* 4 Program defaults and thresholds for RPS*/
+   intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+}
+
+static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
+{
+   u32 val;
+
+   WARN_ON(!mutex_is_locked(_priv->rps.hw_lock));
+
+
+   intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+
+   /* 1: Program defaults and thresholds for RPS*/
I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100);
I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
@@ -7258,7 +7275,7 @@ static void cherryview_enable_rps(struct drm_i915_private 
*dev_priv)
 
I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
 
-   /* 5: Enable RPS */
+   /* 2: Enable RPS */
I915_WRITE(GEN6_RP_CONTROL,
   GEN6_RP_MEDIA_HW_NORMAL_MODE |
   GEN6_RP_MEDIA_IS_GFX |
@@ -7957,6 +7974,7 @@ void intel_disable_gt_powersave(struct drm_i915_private 
*dev_priv)
gen9_disable_rc6(dev_priv);
gen9_disable_rps(dev_priv);
} else if (IS_CHERRYVIEW(dev_priv)) {
+   cherryview_disable_rc6(dev_priv);
cherryview_disable_rps(dev_priv);
} else if (IS_VALLEYVIEW(dev_priv)) {
valleyview_disable_rc6(dev_priv);
@@ -7987,6 +8005,7 @@ void intel_enable_gt_powersave(struct drm_i915_private 
*dev_priv)
mutex_lock(_priv->rps.hw_lock);
 
if (IS_CHERRYVIEW(dev_priv)) {
+   cherryview_enable_rc6(dev_priv);
cherryview_enable_rps(dev_priv);
} else if (IS_VALLEYVIEW(dev_priv)) {
valleyview_enable_rc6(dev_priv);
-- 
1.9.1

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[Intel-gfx] [PATCH 06/31] drm/i915: Name i915_runtime_pm structure in dev_priv as "rpm"

[Sagar Arun Kamble]

Will be using pm for state containing RPS/RC6 state in the next patch.

Cc: Imre Deak 
Cc: Chris Wilson 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/i915_drv.c |  8 
 drivers/gpu/drm/i915/i915_drv.h |  2 +-
 drivers/gpu/drm/i915/i915_gpu_error.c   |  4 ++--
 drivers/gpu/drm/i915/i915_irq.c |  8 
 drivers/gpu/drm/i915/intel_drv.h| 10 +-
 drivers/gpu/drm/i915/intel_pm.c |  4 ++--
 drivers/gpu/drm/i915/intel_runtime_pm.c | 10 +-
 7 files changed, 23 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index ec0e770..d155316 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2533,12 +2533,12 @@ static int intel_runtime_suspend(struct device *kdev)
intel_uncore_suspend(dev_priv);
 
enable_rpm_wakeref_asserts(dev_priv);
-   WARN_ON_ONCE(atomic_read(_priv->pm.wakeref_count));
+   WARN_ON_ONCE(atomic_read(_priv->rpm.wakeref_count));
 
if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
DRM_ERROR("Unclaimed access detected prior to suspending\n");
 
-   dev_priv->pm.suspended = true;
+   dev_priv->rpm.suspended = true;
 
/*
 * FIXME: We really should find a document that references the arguments
@@ -2584,11 +2584,11 @@ static int intel_runtime_resume(struct device *kdev)
 
DRM_DEBUG_KMS("Resuming device\n");
 
-   WARN_ON_ONCE(atomic_read(_priv->pm.wakeref_count));
+   WARN_ON_ONCE(atomic_read(_priv->rpm.wakeref_count));
disable_rpm_wakeref_asserts(dev_priv);
 
intel_opregion_notify_adapter(dev_priv, PCI_D0);
-   dev_priv->pm.suspended = false;
+   dev_priv->rpm.suspended = false;
if (intel_uncore_unclaimed_mmio(dev_priv))
DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4d5ffde..49dfc3d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2512,7 +2512,7 @@ struct drm_i915_private {
bool distrust_bios_wm;
} wm;
 
-   struct i915_runtime_pm pm;
+   struct i915_runtime_pm rpm;
 
struct {
bool initialized;
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 0c77967..23e9abf 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1665,8 +1665,8 @@ static void i915_capture_gen_state(struct 
drm_i915_private *dev_priv,
   struct i915_gpu_state *error)
 {
error->awake = dev_priv->gt.awake;
-   error->wakelock = atomic_read(_priv->pm.wakeref_count);
-   error->suspended = dev_priv->pm.suspended;
+   error->wakelock = atomic_read(_priv->rpm.wakeref_count);
+   error->suspended = dev_priv->rpm.suspended;
 
error->iommu = -1;
 #ifdef CONFIG_INTEL_IOMMU
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 4d0e8f7..e44d894 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -4118,7 +4118,7 @@ int intel_irq_install(struct drm_i915_private *dev_priv)
 * interrupts as enabled _before_ actually enabling them to avoid
 * special cases in our ordering checks.
 */
-   dev_priv->pm.irqs_enabled = true;
+   dev_priv->rpm.irqs_enabled = true;
 
return drm_irq_install(_priv->drm, dev_priv->drm.pdev->irq);
 }
@@ -4134,7 +4134,7 @@ void intel_irq_uninstall(struct drm_i915_private 
*dev_priv)
 {
drm_irq_uninstall(_priv->drm);
intel_hpd_cancel_work(dev_priv);
-   dev_priv->pm.irqs_enabled = false;
+   dev_priv->rpm.irqs_enabled = false;
 }
 
 /**
@@ -4147,7 +4147,7 @@ void intel_irq_uninstall(struct drm_i915_private 
*dev_priv)
 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
 {
dev_priv->drm.driver->irq_uninstall(_priv->drm);
-   dev_priv->pm.irqs_enabled = false;
+   dev_priv->rpm.irqs_enabled = false;
synchronize_irq(dev_priv->drm.irq);
 }
 
@@ -4160,7 +4160,7 @@ void intel_runtime_pm_disable_interrupts(struct 
drm_i915_private *dev_priv)
  */
 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
 {
-   dev_priv->pm.irqs_enabled = true;
+   dev_priv->rpm.irqs_enabled = true;
dev_priv->drm.driver->irq_preinstall(_priv->drm);
dev_priv->drm.driver->irq_postinstall(_priv->drm);
 }
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 3078076..76ef34b 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1252,7 +1252,7 @@ static inline bool intel_irqs_enabled(struct 
drm_i915_private *dev_priv)
 * We only use 

[Intel-gfx] [PATCH 09/31] drm/i915: Create generic function to setup ring frequency table

[Sagar Arun Kamble]

Prepared intel_update_ring_freq function to setup ring frequency
for applicable platforms determined by macro - NEEDS_RING_FREQ_UPDATE

Cc: Imre Deak 
Cc: Chris Wilson 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/intel_pm.c | 19 +++
 1 file changed, 15 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b83751e..54e7577 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7872,6 +7872,19 @@ static void intel_init_emon(struct drm_i915_private 
*dev_priv)
dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
 }
 
+#define NEEDS_RING_FREQ_UPDATE(i915) \
+  (((INTEL_GEN(i915) >= 9) && \
+(IS_GEN9_BC(i915) || IS_CANNONLAKE(i915))) || \
+   (IS_BROADWELL(i915)) || \
+   ((INTEL_GEN(i915) >= 6) && \
+(!IS_CHERRYVIEW(i915) && !IS_VALLEYVIEW(i915
+
+static inline void intel_update_ring_freq(struct drm_i915_private *i915)
+{
+   if (NEEDS_RING_FREQ_UPDATE(i915))
+   gen6_update_ring_freq(i915);
+}
+
 void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
 {
struct intel_rps *rps = _priv->pm.rps;
@@ -8018,21 +8031,19 @@ void intel_enable_gt_powersave(struct drm_i915_private 
*dev_priv)
} else if (INTEL_GEN(dev_priv) >= 9) {
gen9_enable_rc6(dev_priv);
gen9_enable_rps(dev_priv);
-   if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
-   gen6_update_ring_freq(dev_priv);
} else if (IS_BROADWELL(dev_priv)) {
gen8_enable_rc6(dev_priv);
gen8_enable_rps(dev_priv);
-   gen6_update_ring_freq(dev_priv);
} else if (INTEL_GEN(dev_priv) >= 6) {
gen6_enable_rc6(dev_priv);
gen6_enable_rps(dev_priv);
-   gen6_update_ring_freq(dev_priv);
} else if (IS_IRONLAKE_M(dev_priv)) {
ironlake_enable_drps(dev_priv);
intel_init_emon(dev_priv);
}
 
+   intel_update_ring_freq(dev_priv);
+
WARN_ON(dev_priv->pm.rps.max_freq < dev_priv->pm.rps.min_freq);
WARN_ON(dev_priv->pm.rps.idle_freq > dev_priv->pm.rps.max_freq);
 
-- 
1.9.1

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[Intel-gfx] [PATCH 04/31] drm/i915: Separate RPS and RC6 handling for VLV

[Sagar Arun Kamble]

This patch separates enable/disable of RC6 and RPS for VLV.

Cc: Imre Deak 
Cc: Chris Wilson 
Signed-off-by: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 12 +---
 drivers/gpu/drm/i915/intel_pm.c | 57 -
 2 files changed, 39 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 3e4677b..8126c2c 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1454,21 +1454,11 @@ static void print_rc6_res(struct seq_file *m,
 static int vlv_drpc_info(struct seq_file *m)
 {
struct drm_i915_private *dev_priv = node_to_i915(m->private);
-   u32 rpmodectl1, rcctl1, pw_status;
+   u32 rcctl1, pw_status;
 
pw_status = I915_READ(VLV_GTLC_PW_STATUS);
-   rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
rcctl1 = I915_READ(GEN6_RC_CONTROL);
 
-   seq_printf(m, "Video Turbo Mode: %s\n",
-  yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
-   seq_printf(m, "Turbo enabled: %s\n",
-  yesno(rpmodectl1 & GEN6_RP_ENABLE));
-   seq_printf(m, "HW control enabled: %s\n",
-  yesno(rpmodectl1 & GEN6_RP_ENABLE));
-   seq_printf(m, "SW control enabled: %s\n",
-  yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
- GEN6_RP_MEDIA_SW_MODE));
seq_printf(m, "RC6 Enabled: %s\n",
   yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
GEN6_RC_CTL_EI_MODE(1;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6de69ae..8bbe037 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6342,7 +6342,7 @@ static void cherryview_disable_rps(struct 
drm_i915_private *dev_priv)
I915_WRITE(GEN6_RC_CONTROL, 0);
 }
 
-static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
+static void valleyview_disable_rc6(struct drm_i915_private *dev_priv)
 {
/* we're doing forcewake before Disabling RC6,
 * This what the BIOS expects when going into suspend */
@@ -6353,6 +6353,11 @@ static void valleyview_disable_rps(struct 
drm_i915_private *dev_priv)
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 }
 
+static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
+{
+   I915_WRITE(GEN6_RP_CONTROL, 0);
+}
+
 static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
 {
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
@@ -7280,11 +7285,11 @@ static void cherryview_enable_rps(struct 
drm_i915_private *dev_priv)
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 }
 
-static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
+static void valleyview_enable_rc6(struct drm_i915_private *dev_priv)
 {
struct intel_engine_cs *engine;
enum intel_engine_id id;
-   u32 gtfifodbg, val, rc6_mode = 0;
+   u32 gtfifodbg, rc6_mode = 0;
 
WARN_ON(!mutex_is_locked(_priv->rps.hw_lock));
 
@@ -7303,22 +7308,6 @@ static void valleyview_enable_rps(struct 
drm_i915_private *dev_priv)
/*  Disable RC states. */
I915_WRITE(GEN6_RC_CONTROL, 0);
 
-   I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100);
-   I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
-   I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
-   I915_WRITE(GEN6_RP_UP_EI, 66000);
-   I915_WRITE(GEN6_RP_DOWN_EI, 35);
-
-   I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
-
-   I915_WRITE(GEN6_RP_CONTROL,
-  GEN6_RP_MEDIA_TURBO |
-  GEN6_RP_MEDIA_HW_NORMAL_MODE |
-  GEN6_RP_MEDIA_IS_GFX |
-  GEN6_RP_ENABLE |
-  GEN6_RP_UP_BUSY_AVG |
-  GEN6_RP_DOWN_IDLE_CONT);
-
I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x0028);
I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
@@ -7343,6 +7332,34 @@ static void valleyview_enable_rps(struct 
drm_i915_private *dev_priv)
 
I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
 
+   intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+}
+
+static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
+{
+   u32 val;
+
+   WARN_ON(!mutex_is_locked(_priv->rps.hw_lock));
+
+   /* If VLV, Forcewake all wells, else re-direct to regular path */
+   intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+
+   I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100);
+   I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
+   I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
+   I915_WRITE(GEN6_RP_UP_EI, 66000);
+   I915_WRITE(GEN6_RP_DOWN_EI, 35);
+
+   I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
+
+   I915_WRITE(GEN6_RP_CONTROL,
+  GEN6_RP_MEDIA_TURBO |
+