[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [01/23] drm/i915: Reduce context HW ID lifetime

[Patchwork]

== Series Details ==

Series: series starting with [01/23] drm/i915: Reduce context HW ID lifetime
URL   : https://patchwork.freedesktop.org/series/49157/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4769_full -> Patchwork_10086_full =

== Summary - SUCCESS ==

  No regressions found.

  

== Known issues ==

  Here are the changes found in Patchwork_10086_full that come from known 
issues:

  === IGT changes ===

 Possible fixes 

igt@drv_suspend@shrink:
  shard-snb:  FAIL (fdo#106886) -> PASS

igt@kms_flip@absolute-wf_vblank:
  shard-kbl:  DMESG-WARN (fdo#103558, fdo#105602) -> PASS +25

igt@kms_flip@flip-vs-modeset-vs-hang:
  shard-kbl:  DMESG-WARN (fdo#103558, fdo#105602, fdo#103313) -> 
PASS

igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-gtt:
  shard-glk:  FAIL (fdo#103167) -> PASS

igt@kms_setmode@basic:
  shard-apl:  FAIL (fdo#99912) -> PASS


  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103313 https://bugs.freedesktop.org/show_bug.cgi?id=103313
  fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
  fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
  fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (5 -> 5) ==

  No changes in participating hosts


== Build changes ==

* Linux: CI_DRM_4769 -> Patchwork_10086

  CI_DRM_4769: ced90ae07f3004a5fe83f26bc8f2205340b9b5a8 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4627: e0c3033a57d85c0d2eb33af0451afa16edc79f10 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10086: 839f4ddf3d7196ac9ada5fdc69c613d192ef2d0f @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ 
git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10086/shards.html
___
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm: Reject unknown legacy bpp and dpeth for drm_mode_addfb ioctl

[Patchwork]

== Series Details ==

Series: drm: Reject unknown legacy bpp and dpeth for drm_mode_addfb ioctl
URL   : https://patchwork.freedesktop.org/series/49150/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4769_full -> Patchwork_10085_full =

== Summary - SUCCESS ==

  No regressions found.

  

== Known issues ==

  Here are the changes found in Patchwork_10085_full that come from known 
issues:

  === IGT changes ===

 Issues hit 

igt@drv_suspend@forcewake:
  shard-apl:  PASS -> INCOMPLETE (fdo#103927)

igt@kms_busy@extended-modeset-hang-newfb-render-b:
  shard-glk:  PASS -> INCOMPLETE (k.org#198133, fdo#103359)

igt@kms_cursor_legacy@cursor-vs-flip-toggle:
  shard-hsw:  PASS -> FAIL (fdo#103355)

igt@kms_flip@flip-vs-expired-vblank-interruptible:
  shard-glk:  PASS -> FAIL (fdo#105363, fdo#102887)


 Possible fixes 

igt@drv_suspend@shrink:
  shard-snb:  FAIL (fdo#106886) -> PASS

igt@kms_flip@absolute-wf_vblank:
  shard-kbl:  DMESG-WARN (fdo#105602, fdo#103558) -> PASS +25

igt@kms_flip@flip-vs-modeset-vs-hang:
  shard-kbl:  DMESG-WARN (fdo#105602, fdo#103313, fdo#103558) -> 
PASS

igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-gtt:
  shard-glk:  FAIL (fdo#103167) -> PASS

igt@kms_setmode@basic:
  shard-apl:  FAIL (fdo#99912) -> PASS


  fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103313 https://bugs.freedesktop.org/show_bug.cgi?id=103313
  fdo#103355 https://bugs.freedesktop.org/show_bug.cgi?id=103355
  fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
  fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
  fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
  k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133


== Participating hosts (5 -> 5) ==

  No changes in participating hosts


== Build changes ==

* Linux: CI_DRM_4769 -> Patchwork_10085

  CI_DRM_4769: ced90ae07f3004a5fe83f26bc8f2205340b9b5a8 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4627: e0c3033a57d85c0d2eb33af0451afa16edc79f10 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10085: 98e6d2db475f03e2baa8818a7bc12d0490a6e961 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ 
git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10085/shards.html
___
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Re: [Intel-gfx] [PATCH] drm/i915/dp_mst: Fix enabling pipe clock for all streams

[Dhinakaran Pandiyan]

On Tue, 2018-09-04 at 16:19 -0700, Rodrigo Vivi wrote:
> On Tue, Sep 04, 2018 at 03:53:51PM -0700, Dhinakaran Pandiyan wrote:
> > On Tuesday, September 4, 2018 5:54:16 AM PDT Imre Deak wrote:
> > > On Tue, Sep 04, 2018 at 03:08:16PM +0300, Jani Nikula wrote:
> > > > On Fri, 31 Aug 2018, Imre Deak  wrote:
> > > > > commit afb2c4437dae ("drm/i915/ddi: Push pipe clock enabling
> > > > > to
> > > > > encoders")
> > > > > inadvertently stopped enabling the pipe clock for any DP-MST
> > > > > stream
> > > > > after the first one. It also rearranged the pipe clock
> > > > > enabling wrt.
> > > > > initial MST payload allocation step (which may or may not be
> > > > > a
> > > > > problem, but it's contrary to the spec.).
> > > > > 
> > > > > Fix things by making the above commit truly a non-functional
> > > > > change.
> > > > 
> > > > What kind of MST setups do we have in CI? Why didn't they catch
> > > > this?
> > > 
> > > What we'd need is a dock/other branch device with an DP-MST input
> > > and
> > > two outputs. That would exercise the case that broke here.
> > > 
> > 
> > I had the same question. We have  these two in CI, but both have
> > only one 
> > external display attached.
> > fi-kbl-7560u  Dell XPS 13 Kaby Lake / i7-7560u / Iris Plus
> > Graphics 640 GT3e  
> > eDP, DELL TB16->TB->DP-MST
> > fi-cfl-s3 Intel Coffee Lake-S RVP Coffee Lake eDP-PSR, DP-
> > MST (HDMI)
> > 
> > Tomi,
> > Is it possible to have another external display connected to one of
> > these?
> 
> or to both of them?!
> 
:) Not sure why I wanted only one of them.


> I'm seeing MST related regressions since 4.16 so I'd like to have few
> different configuration if possible with more than one monitor.

A 4K@60Hz monitor along with a full-HD (or higher) monitor will be
useful to test the link BW code too. Together, they should be exceeding
the 63 vcpi slot limit. We can then write new IGT's to verify that.


> 
> at least one kind of dock and one kind of chain both with 2 monitors
> plugged in would be good.


___
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[Intel-gfx] [PATCH xf86-video-intel] sna/io: Align the linear source buffer to cache line for 2d blt of SKL+

[Guang Bai]

On SKL+ the linear source buffer has to start from cache line boundary
to meet the 2d engine source copy requirements. Apply this cache line
alignment policy for SKL+ only.

v2: Apply these changes only to SKL+ for not breaking old platforms
based on Chris Wilson's reviews.

Cc: Chris Wilson 
Signed-off-by: Guang Bai 
---
 src/sna/sna_io.c | 47 +++
 1 file changed, 35 insertions(+), 12 deletions(-)

diff --git a/src/sna/sna_io.c b/src/sna/sna_io.c
index d32bd58..ae82d1f 100644
--- a/src/sna/sna_io.c
+++ b/src/sna/sna_io.c
@@ -1064,7 +1064,7 @@ tile:
if (kgem->gen >= 0100) {
cmd |= 8;
do {
-   int nbox_this_time, rem;
+   int nbox_this_time, rem, pitch_aligned;
 
nbox_this_time = nbox;
rem = kgem_batch_space(kgem);
@@ -1077,12 +1077,19 @@ tile:
 
/* Count the total number of bytes to be read and 
allocate a
 * single buffer large enough. Or if it is very small, 
combine
-* with other allocations. */
+* with other allocations. Each sub-buffer starting 
point has
+* to be aligned to 64 bytes to conform SKL+ hardware 
requirments.
+* Align the pitch of each sub-buffer to 64 bytes for 
simplicities.
+*/
offset = 0;
for (n = 0; n < nbox_this_time; n++) {
int height = box[n].y2 - box[n].y1;
int width = box[n].x2 - box[n].x1;
-   offset += PITCH(width, 
dst->drawable.bitsPerPixel >> 3) * height;
+   if (kgem->gen >= 0110) {
+   pitch_aligned = ALIGN(PITCH(width, 
dst->drawable.bitsPerPixel >> 3), 64);
+   offset += pitch_aligned * height;
+   } else
+   offset += PITCH(width, 
dst->drawable.bitsPerPixel >> 3) * height;
}
 
src_bo = kgem_create_buffer(kgem, offset,
@@ -1113,14 +1120,24 @@ tile:
assert(box->x1 + dst_dx >= 0);
assert(box->y1 + dst_dy >= 0);
 
-   memcpy_blt(src, (char *)ptr + offset,
-  dst->drawable.bitsPerPixel,
-  stride, pitch,
-  box->x1 + src_dx, box->y1 + 
src_dy,
-  0, 0,
-  width, height);
+   if (kgem->gen >= 0110) {
+   pitch_aligned = ALIGN(pitch, 
64);
+   memcpy_blt(src, (char *)ptr + 
offset,
+  
dst->drawable.bitsPerPixel,
+  stride, 
pitch_aligned,
+  box->x1 + src_dx, 
box->y1 + src_dy,
+  0, 0,
+  width, height);
+   } else
+   memcpy_blt(src, (char *)ptr + 
offset,
+  
dst->drawable.bitsPerPixel,
+  stride, pitch,
+  box->x1 + src_dx, 
box->y1 + src_dy,
+  0, 0,
+  width, height);
 
assert(kgem->mode == KGEM_BLT);
+
b = kgem->batch + kgem->nbatch;
b[0] = cmd;
b[1] = br13;
@@ -1133,16 +1150,22 @@ tile:
 
KGEM_RELOC_FENCED,
 0);
b[6] = 0;
-   b[7] = pitch;
+   if (kgem->gen >= 0110)
+   b[7] = pitch_aligned;
+   else
+   b[7] = pitch;
+
*(uint64_t *)(b+8) =
kgem_add_reloc64(kgem, 
kgem->nbatch + 8, src

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Be defensive and don't assume PSR has any commit to sync against

[Patchwork]

== Series Details ==

Series: drm/i915: Be defensive and don't assume PSR has any commit to sync 
against
URL   : https://patchwork.freedesktop.org/series/49141/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4767_full -> Patchwork_10084_full =

== Summary - SUCCESS ==

  No regressions found.

  

== Known issues ==

  Here are the changes found in Patchwork_10084_full that come from known 
issues:

  === IGT changes ===

 Issues hit 

igt@drv_suspend@shrink:
  shard-hsw:  PASS -> INCOMPLETE (fdo#106886, fdo#103540)
  shard-kbl:  PASS -> FAIL (fdo#106886)

igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
  shard-hsw:  PASS -> FAIL (fdo#105767) +1

igt@kms_cursor_legacy@cursor-vs-flip-toggle:
  shard-hsw:  PASS -> FAIL (fdo#103355) +1


 Possible fixes 

igt@kms_flip@flip-vs-expired-vblank-interruptible:
  shard-glk:  FAIL (fdo#105363, fdo#102887) -> PASS

igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-pwrite:
  shard-glk:  FAIL (fdo#103167) -> PASS

igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
  shard-glk:  INCOMPLETE (fdo#103359, k.org#198133) -> PASS

igt@kms_setmode@basic:
  shard-apl:  FAIL (fdo#99912) -> PASS


  fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103355 https://bugs.freedesktop.org/show_bug.cgi?id=103355
  fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
  fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#105767 https://bugs.freedesktop.org/show_bug.cgi?id=105767
  fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
  k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133


== Participating hosts (5 -> 5) ==

  No changes in participating hosts


== Build changes ==

* Linux: CI_DRM_4767 -> Patchwork_10084

  CI_DRM_4767: e9b69bafd3c2c13a8b9fa8e7a410f5d5ef32e328 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4626: bfce01d8c93dbd86e6ab04ca1afb844e0cbc8078 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10084: 23e6b7e3848fb3bbf675255440b077f6187a81a5 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ 
git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10084/shards.html
___
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Re: [Intel-gfx] [PATCH] drm/i915/dp_mst: Fix enabling pipe clock for all streams

[Rodrigo Vivi]

On Tue, Sep 04, 2018 at 03:53:51PM -0700, Dhinakaran Pandiyan wrote:
> On Tuesday, September 4, 2018 5:54:16 AM PDT Imre Deak wrote:
> > On Tue, Sep 04, 2018 at 03:08:16PM +0300, Jani Nikula wrote:
> > > On Fri, 31 Aug 2018, Imre Deak  wrote:
> > > > commit afb2c4437dae ("drm/i915/ddi: Push pipe clock enabling to
> > > > encoders")
> > > > inadvertently stopped enabling the pipe clock for any DP-MST stream
> > > > after the first one. It also rearranged the pipe clock enabling wrt.
> > > > initial MST payload allocation step (which may or may not be a
> > > > problem, but it's contrary to the spec.).
> > > > 
> > > > Fix things by making the above commit truly a non-functional change.
> > > 
> > > What kind of MST setups do we have in CI? Why didn't they catch this?
> > 
> > What we'd need is a dock/other branch device with an DP-MST input and
> > two outputs. That would exercise the case that broke here.
> > 
> I had the same question. We have  these two in CI, but both have only one 
> external display attached.
> fi-kbl-7560u  Dell XPS 13 Kaby Lake / i7-7560u / Iris Plus Graphics 640 
> GT3e  
> eDP, DELL TB16->TB->DP-MST
> fi-cfl-s3 Intel Coffee Lake-S RVP Coffee Lake eDP-PSR, DP-MST (HDMI)
> 
> Tomi,
> Is it possible to have another external display connected to one of these?

or to both of them?!

I'm seeing MST related regressions since 4.16 so I'd like to have few
different configuration if possible with more than one monitor.

at least one kind of dock and one kind of chain both with 2 monitors
plugged in would be good.

> 
> 
> > > BR,
> > > Jani.
> > > 
> > > > Fixes: commit afb2c4437dae ("drm/i915/ddi: Push pipe clock enabling to
> > > > encoders") Bugzilla:
> > > > https://bugs.freedesktop.org/show_bug.cgi?id=107365
> > > > Reported-by: Lyude Paul 
> > > > Reported-by: dmummensch...@web.de
> > > > Tested-by: dmummensch...@web.de
> > > > Cc: Lyude Paul 
> > > > Cc: dmummensch...@web.de
> > > > Cc: Ville Syrjälä 
> > > > Cc: Rodrigo Vivi 
> > > > Cc: Chris Wilson 
> > > > Signed-off-by: Imre Deak 
> > > > ---
> > > > 
> > > >  drivers/gpu/drm/i915/intel_ddi.c| 17 +
> > > >  drivers/gpu/drm/i915/intel_dp_mst.c |  4 
> > > >  2 files changed, 13 insertions(+), 8 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> > > > b/drivers/gpu/drm/i915/intel_ddi.c index f3b115ce4029..dcb1a98d624d
> > > > 100644
> > > > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > > > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > > > @@ -2912,7 +2912,8 @@ static void intel_ddi_pre_enable_dp(struct
> > > > intel_encoder *encoder,> > 
> > > > icl_enable_phy_clock_gating(dig_port);
> > > > 
> > > > -   intel_ddi_enable_pipe_clock(crtc_state);
> > > > +   if (!is_mst)
> > > > +   intel_ddi_enable_pipe_clock(crtc_state);
> > > > 
> > > >  }
> > > >  
> > > >  static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
> > > > 
> > > > @@ -3015,14 +3016,14 @@ static void intel_ddi_post_disable_dp(struct
> > > > intel_encoder *encoder,> > 
> > > > bool is_mst = intel_crtc_has_type(old_crtc_state,
> > > > 
> > > >   INTEL_OUTPUT_DP_MST);
> > > > 
> > > > -   intel_ddi_disable_pipe_clock(old_crtc_state);
> > > > -
> > > > -   /*
> > > > -* Power down sink before disabling the port, otherwise we end
> > > > -* up getting interrupts from the sink on detecting link loss.
> > > > -*/
> > > > -   if (!is_mst)
> > > > +   if (!is_mst) {
> > > > +   intel_ddi_disable_pipe_clock(old_crtc_state);
> > > > +   /*
> > > > +* Power down sink before disabling the port, otherwise 
> > > > we end
> > > > +* up getting interrupts from the sink on detecting 
> > > > link loss.
> > > > +*/
> > > > 
> > > > intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
> > > > 
> > > > +   }
> > > > 
> > > > intel_disable_ddi_buf(encoder);
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c
> > > > b/drivers/gpu/drm/i915/intel_dp_mst.c index 352e5216cc65..77920f1a3da1
> > > > 100644
> > > > --- a/drivers/gpu/drm/i915/intel_dp_mst.c
> > > > +++ b/drivers/gpu/drm/i915/intel_dp_mst.c
> > > > @@ -166,6 +166,8 @@ static void intel_mst_post_disable_dp(struct
> > > > intel_encoder *encoder,> > 
> > > > struct intel_connector *connector =
> > > > 
> > > > to_intel_connector(old_conn_state->connector);
> > > > 
> > > > +   intel_ddi_disable_pipe_clock(old_crtc_state);
> > > > +
> > > > 
> > > > /* this can fail */
> > > > drm_dp_check_act_status(&intel_dp->mst_mgr);
> > > > /* and this can also fail */
> > > > 
> > > > @@ -249,6 +251,8 @@ static void intel_mst_pre_enable_dp(struct
> > > > intel_encoder *encoder,> > 
> > > > I915_WRITE(DP_TP_STATUS(port), temp);
> > > > 
> > > > ret = drm_dp_u

[Intel-gfx] ✓ Fi.CI.IGT: success for igt/pm_rpm: Reload the module with full mmio debugging

[Patchwork]

== Series Details ==

Series: igt/pm_rpm: Reload the module with full mmio debugging
URL   : https://patchwork.freedesktop.org/series/49138/
State : success

== Summary ==

= CI Bug Log - changes from IGT_4625_full -> IGTPW_1785_full =

== Summary - SUCCESS ==

  No regressions found.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/49138/revisions/1/mbox/

== Known issues ==

  Here are the changes found in IGTPW_1785_full that come from known issues:

  === IGT changes ===

 Issues hit 

igt@drv_suspend@shrink:
  shard-hsw:  PASS -> INCOMPLETE (fdo#106886, fdo#103540)

igt@kms_color@pipe-b-ctm-0-75:
  shard-apl:  PASS -> DMESG-WARN (fdo#103558, fdo#105602) +10

igt@kms_frontbuffer_tracking@fbc-shrfb-scaledprimary:
  shard-glk:  PASS -> FAIL (fdo#103167) +1

igt@testdisplay:
  shard-glk:  PASS -> INCOMPLETE (fdo#107093, k.org#198133, 
fdo#103359)


 Possible fixes 

igt@kms_available_modes_crc@available_mode_test_crc:
  shard-snb:  FAIL (fdo#106641) -> PASS

igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-gtt:
  shard-snb:  INCOMPLETE (fdo#105411) -> PASS

igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-cpu:
  shard-glk:  FAIL (fdo#103167) -> PASS +2

igt@kms_plane@pixel-format-pipe-a-planes:
  shard-snb:  FAIL (fdo#107749) -> PASS

igt@kms_rotation_crc@sprite-rotation-180:
  shard-snb:  FAIL (fdo#103925) -> PASS


  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
  fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
  fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
  fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925
  fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411
  fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
  fdo#106641 https://bugs.freedesktop.org/show_bug.cgi?id=106641
  fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886
  fdo#107093 https://bugs.freedesktop.org/show_bug.cgi?id=107093
  fdo#107749 https://bugs.freedesktop.org/show_bug.cgi?id=107749
  k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133


== Participating hosts (5 -> 5) ==

  No changes in participating hosts


== Build changes ==

* IGT: IGT_4625 -> IGTPW_1785
* Linux: CI_DRM_4763 -> CI_DRM_4766

  CI_DRM_4763: 1f8c06844acac7a349fb80471afcc09f33c6cfc0 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  CI_DRM_4766: 0d35b9d0b3a74c41ac1ffe1a34aa9c98d2a3a0b9 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_1785: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1785/
  IGT_4625: 67fbe2967889484f1248d851c068e1021f2dc332 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1785/shards.html
___
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Re: [Intel-gfx] [PATCH] drm/i915/dp_mst: Fix enabling pipe clock for all streams

[Dhinakaran Pandiyan]

On Tuesday, September 4, 2018 5:54:16 AM PDT Imre Deak wrote:
> On Tue, Sep 04, 2018 at 03:08:16PM +0300, Jani Nikula wrote:
> > On Fri, 31 Aug 2018, Imre Deak  wrote:
> > > commit afb2c4437dae ("drm/i915/ddi: Push pipe clock enabling to
> > > encoders")
> > > inadvertently stopped enabling the pipe clock for any DP-MST stream
> > > after the first one. It also rearranged the pipe clock enabling wrt.
> > > initial MST payload allocation step (which may or may not be a
> > > problem, but it's contrary to the spec.).
> > > 
> > > Fix things by making the above commit truly a non-functional change.
> > 
> > What kind of MST setups do we have in CI? Why didn't they catch this?
> 
> What we'd need is a dock/other branch device with an DP-MST input and
> two outputs. That would exercise the case that broke here.
> 
I had the same question. We have  these two in CI, but both have only one 
external display attached.
fi-kbl-7560uDell XPS 13 Kaby Lake / i7-7560u / Iris Plus Graphics 640 
GT3e  
eDP, DELL TB16->TB->DP-MST
fi-cfl-s3   Intel Coffee Lake-S RVP Coffee Lake eDP-PSR, DP-MST (HDMI)

Tomi,
Is it possible to have another external display connected to one of these?


> > BR,
> > Jani.
> > 
> > > Fixes: commit afb2c4437dae ("drm/i915/ddi: Push pipe clock enabling to
> > > encoders") Bugzilla:
> > > https://bugs.freedesktop.org/show_bug.cgi?id=107365
> > > Reported-by: Lyude Paul 
> > > Reported-by: dmummensch...@web.de
> > > Tested-by: dmummensch...@web.de
> > > Cc: Lyude Paul 
> > > Cc: dmummensch...@web.de
> > > Cc: Ville Syrjälä 
> > > Cc: Rodrigo Vivi 
> > > Cc: Chris Wilson 
> > > Signed-off-by: Imre Deak 
> > > ---
> > > 
> > >  drivers/gpu/drm/i915/intel_ddi.c| 17 +
> > >  drivers/gpu/drm/i915/intel_dp_mst.c |  4 
> > >  2 files changed, 13 insertions(+), 8 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> > > b/drivers/gpu/drm/i915/intel_ddi.c index f3b115ce4029..dcb1a98d624d
> > > 100644
> > > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > > @@ -2912,7 +2912,8 @@ static void intel_ddi_pre_enable_dp(struct
> > > intel_encoder *encoder,> > 
> > >   icl_enable_phy_clock_gating(dig_port);
> > > 
> > > - intel_ddi_enable_pipe_clock(crtc_state);
> > > + if (!is_mst)
> > > + intel_ddi_enable_pipe_clock(crtc_state);
> > > 
> > >  }
> > >  
> > >  static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
> > > 
> > > @@ -3015,14 +3016,14 @@ static void intel_ddi_post_disable_dp(struct
> > > intel_encoder *encoder,> > 
> > >   bool is_mst = intel_crtc_has_type(old_crtc_state,
> > >   
> > > INTEL_OUTPUT_DP_MST);
> > > 
> > > - intel_ddi_disable_pipe_clock(old_crtc_state);
> > > -
> > > - /*
> > > -  * Power down sink before disabling the port, otherwise we end
> > > -  * up getting interrupts from the sink on detecting link loss.
> > > -  */
> > > - if (!is_mst)
> > > + if (!is_mst) {
> > > + intel_ddi_disable_pipe_clock(old_crtc_state);
> > > + /*
> > > +  * Power down sink before disabling the port, otherwise we end
> > > +  * up getting interrupts from the sink on detecting link loss.
> > > +  */
> > > 
> > >   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
> > > 
> > > + }
> > > 
> > >   intel_disable_ddi_buf(encoder);
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c
> > > b/drivers/gpu/drm/i915/intel_dp_mst.c index 352e5216cc65..77920f1a3da1
> > > 100644
> > > --- a/drivers/gpu/drm/i915/intel_dp_mst.c
> > > +++ b/drivers/gpu/drm/i915/intel_dp_mst.c
> > > @@ -166,6 +166,8 @@ static void intel_mst_post_disable_dp(struct
> > > intel_encoder *encoder,> > 
> > >   struct intel_connector *connector =
> > >   
> > >   to_intel_connector(old_conn_state->connector);
> > > 
> > > + intel_ddi_disable_pipe_clock(old_crtc_state);
> > > +
> > > 
> > >   /* this can fail */
> > >   drm_dp_check_act_status(&intel_dp->mst_mgr);
> > >   /* and this can also fail */
> > > 
> > > @@ -249,6 +251,8 @@ static void intel_mst_pre_enable_dp(struct
> > > intel_encoder *encoder,> > 
> > >   I915_WRITE(DP_TP_STATUS(port), temp);
> > >   
> > >   ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr);
> > > 
> > > +
> > > + intel_ddi_enable_pipe_clock(pipe_config);
> > > 
> > >  }
> > >  
> > >  static void intel_mst_enable_dp(struct intel_encoder *encoder,
> 
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx




___
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [01/23] drm/i915: Reduce context HW ID lifetime

[Patchwork]

== Series Details ==

Series: series starting with [01/23] drm/i915: Reduce context HW ID lifetime
URL   : https://patchwork.freedesktop.org/series/49157/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4769 -> Patchwork_10086 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/49157/revisions/1/mbox/

== Known issues ==

  Here are the changes found in Patchwork_10086 that come from known issues:

  === IGT changes ===

 Issues hit 

igt@gem_exec_suspend@basic-s3:
  fi-blb-e6850:   PASS -> INCOMPLETE (fdo#107718)

igt@kms_flip@basic-flip-vs-dpms:
  fi-kbl-r:   PASS -> DMESG-WARN (fdo#105602)

igt@kms_frontbuffer_tracking@basic:
  fi-byt-clapper: PASS -> FAIL (fdo#103167)

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
  fi-snb-2520m:   PASS -> INCOMPLETE (fdo#103713)


 Possible fixes 

igt@kms_flip@basic-plain-flip:
  fi-ilk-650: DMESG-WARN (fdo#106387) -> PASS +2

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
  fi-bdw-samus:   DMESG-WARN (fdo#107494) -> PASS

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
  fi-cnl-psr: DMESG-WARN (fdo#104951) -> PASS

igt@kms_psr@primary_page_flip:
  fi-cnl-psr: FAIL (fdo#107336) -> PASS


  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
  fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951
  fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
  fdo#106387 https://bugs.freedesktop.org/show_bug.cgi?id=106387
  fdo#107336 https://bugs.freedesktop.org/show_bug.cgi?id=107336
  fdo#107494 https://bugs.freedesktop.org/show_bug.cgi?id=107494
  fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718


== Participating hosts (48 -> 43) ==

  Additional (1): fi-pnv-d510 
  Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan 
fi-ctg-p8600 fi-skl-6700hq 


== Build changes ==

* Linux: CI_DRM_4769 -> Patchwork_10086

  CI_DRM_4769: ced90ae07f3004a5fe83f26bc8f2205340b9b5a8 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4627: e0c3033a57d85c0d2eb33af0451afa16edc79f10 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10086: 839f4ddf3d7196ac9ada5fdc69c613d192ef2d0f @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

839f4ddf3d71 drm/i915: Serialise concurrent calls to i915_gem_set_wedged()
318b8a7e9da4 drm/i915: Mark up Ironlake ips with rpm wakerefs
0815d4eecb58 drm/i915: Complain if hsw_get_pipe_config acquires the same power 
well twice
d467de58f069 drm/i915/dp: Markup pps lock power well
bfb58f028bc8 drm/i915: Track the wakeref used to initialise display power 
domains
1f950437390d drm/i915: Markup paired operations on display power domains
011f0dab532a drm/i915: Syntatic sugar for using intel_runtime_pm
0e5cd2856b69 drm/i915: Markup paired operations on wakerefs
c8b527abd7f5 drm/i915: Track all held rpm wakerefs
f5e5e1732bd4 drm/i915: Attach the pci match data to the device upon creation
fa0b7f94b44a drm/i915: Cache the error string
0c32e06efa4a drm/i915: Clear the error PTE just once on finish
79bd577c5774 drm/i915: Handle incomplete Z_FINISH for compressed error states
85f92b3ad0b5 drm/i915/execlists: Assert the queue is non-empty on unsubmitting
76d02ab168e3 drm/i915: Remove debugfs/i915_ppgtt_info
3d1e691c76dc drm/i915: Report the number of closed vma held by each context in 
debugfs
47868ad3229b drm/i915/execlists: Onion unwind for logical_ring_init() failure
eded3ed0adbe drm/i915/execlists: Use coherent writes into the context image
c57b5226773f drm/i915/execlists: Delay updating ring register state after resume
3612d9a0f807 drm/i915/selftests: Basic stress test for rapid context switching
0dc2e7376733 drm/i915: Missed interrupt simulation is no more, tell the world
12f688340874 drm/i915/execlists: Avoid kicking priority on the current context
d7ddd5a81ce5 drm/i915: Reduce context HW ID lifetime

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10086/issues.html
___
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Reduce context HW ID lifetime (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Reduce context HW ID lifetime (rev3)
URL   : https://patchwork.freedesktop.org/series/44134/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4767_full -> Patchwork_10083_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_10083_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10083_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

== Possible new issues ==

  Here are the unknown changes that may have been introduced in 
Patchwork_10083_full:

  === IGT changes ===

 Warnings 

igt@pm_rc6_residency@rc6-accuracy:
  shard-kbl:  PASS -> SKIP


== Known issues ==

  Here are the changes found in Patchwork_10083_full that come from known 
issues:

  === IGT changes ===

 Issues hit 

igt@kms_color@pipe-b-gamma:
  shard-kbl:  PASS -> DMESG-WARN (fdo#103558, fdo#105602) +3

igt@kms_flip@flip-vs-expired-vblank:
  shard-glk:  PASS -> FAIL (fdo#102887, fdo#105363)

igt@kms_flip@flip-vs-panning-vs-hang:
  shard-kbl:  PASS -> DMESG-WARN (fdo#103558, fdo#103313, 
fdo#105602) +6

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
  shard-kbl:  PASS -> DMESG-WARN (fdo#103558, fdo#105079, 
fdo#103841, fdo#105602)

igt@pm_rpm@gem-mmap-cpu:
  shard-apl:  PASS -> DMESG-WARN (fdo#103558, fdo#105602) +18

igt@pm_rpm@i2c:
  shard-kbl:  PASS -> DMESG-FAIL (fdo#103558, fdo#103313, 
fdo#105602)


 Possible fixes 

igt@kms_flip@flip-vs-expired-vblank-interruptible:
  shard-glk:  FAIL (fdo#102887, fdo#105363) -> PASS

igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-pwrite:
  shard-glk:  FAIL (fdo#103167) -> PASS

igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
  shard-glk:  INCOMPLETE (fdo#103359, k.org#198133) -> PASS


  fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103313 https://bugs.freedesktop.org/show_bug.cgi?id=103313
  fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
  fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
  fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841
  fdo#105079 https://bugs.freedesktop.org/show_bug.cgi?id=105079
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
  k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133


== Participating hosts (5 -> 5) ==

  No changes in participating hosts


== Build changes ==

* Linux: CI_DRM_4767 -> Patchwork_10083

  CI_DRM_4767: e9b69bafd3c2c13a8b9fa8e7a410f5d5ef32e328 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4626: bfce01d8c93dbd86e6ab04ca1afb844e0cbc8078 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10083: 9a6f6d0994b229642ebe29974173f89352efd764 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ 
git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10083/shards.html
___
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [01/23] drm/i915: Reduce context HW ID lifetime

[Patchwork]

== Series Details ==

Series: series starting with [01/23] drm/i915: Reduce context HW ID lifetime
URL   : https://patchwork.freedesktop.org/series/49157/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Commit: drm/i915: Reduce context HW ID lifetime
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3686:16: warning: expression 
using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3688:16: warning: expression 
using sizeof(void)

Commit: drm/i915/execlists: Avoid kicking priority on the current context
Okay!

Commit: drm/i915: Missed interrupt simulation is no more, tell the world
Okay!

Commit: drm/i915/selftests: Basic stress test for rapid context switching
+./include/linux/slab.h:631:13: error: undefined identifier 
'__builtin_mul_overflow'
+./include/linux/slab.h:631:13: warning: call with no type!

Commit: drm/i915/execlists: Delay updating ring register state after resume
Okay!

Commit: drm/i915/execlists: Use coherent writes into the context image
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3688:16: warning: expression 
using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3694:16: warning: expression 
using sizeof(void)

Commit: drm/i915/execlists: Onion unwind for logical_ring_init() failure
Okay!

Commit: drm/i915: Report the number of closed vma held by each context in 
debugfs
Okay!

Commit: drm/i915: Remove debugfs/i915_ppgtt_info
Okay!

Commit: drm/i915/execlists: Assert the queue is non-empty on unsubmitting
Okay!

Commit: drm/i915: Handle incomplete Z_FINISH for compressed error states
Okay!

Commit: drm/i915: Clear the error PTE just once on finish
Okay!

Commit: drm/i915: Cache the error string
+drivers/gpu/drm/i915/i915_gpu_error.c:854:25: warning: Using plain integer as 
NULL pointer
+drivers/gpu/drm/i915/i915_gpu_error.c:918:23: warning: expression using 
sizeof(void)
+drivers/gpu/drm/i915/i915_gpu_error.c:918:23: warning: expression using 
sizeof(void)
+drivers/gpu/drm/i915/i915_sysfs.c:531:23: warning: expression using 
sizeof(void)
+drivers/gpu/drm/i915/i915_sysfs.c:531:23: warning: expression using 
sizeof(void)

Commit: drm/i915: Attach the pci match data to the device upon creation
Okay!

Commit: drm/i915: Track all held rpm wakerefs
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3694:16: warning: expression 
using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3701:16: warning: expression 
using sizeof(void)

Commit: drm/i915: Markup paired operations on wakerefs
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3701:16: warning: expression 
using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3705:16: warning: expression 
using sizeof(void)

Commit: drm/i915: Syntatic sugar for using intel_runtime_pm
Okay!

Commit: drm/i915: Markup paired operations on display power domains
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3705:16: warning: expression 
using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3707:16: warning: expression 
using sizeof(void)

Commit: drm/i915: Track the wakeref used to initialise display power domains
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3707:16: warning: expression 
using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3709:16: warning: expression 
using sizeof(void)

Commit: drm/i915/dp: Markup pps lock power well
Okay!

Commit: drm/i915: Complain if hsw_get_pipe_config acquires the same power well 
twice
Okay!

Commit: drm/i915: Mark up Ironlake ips with rpm wakerefs
Okay!

Commit: drm/i915: Serialise concurrent calls to i915_gem_set_wedged()
Okay!

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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/23] drm/i915: Reduce context HW ID lifetime

[Patchwork]

== Series Details ==

Series: series starting with [01/23] drm/i915: Reduce context HW ID lifetime
URL   : https://patchwork.freedesktop.org/series/49157/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
d7ddd5a81ce5 drm/i915: Reduce context HW ID lifetime
-:61: CHECK:UNCOMMENTED_DEFINITION: struct mutex definition without comment
#61: FILE: drivers/gpu/drm/i915/i915_drv.h:1864:
+   struct mutex mutex;

total: 0 errors, 0 warnings, 1 checks, 433 lines checked
12f688340874 drm/i915/execlists: Avoid kicking priority on the current context
-:49: ERROR:SPACING: space prohibited after that open parenthesis '('
#49: FILE: drivers/gpu/drm/i915/intel_guc_submission.c:774:
+   if ( __guc_dequeue(engine))

total: 1 errors, 0 warnings, 0 checks, 103 lines checked
0dc2e7376733 drm/i915: Missed interrupt simulation is no more, tell the world
3612d9a0f807 drm/i915/selftests: Basic stress test for rapid context switching
-:120: WARNING:ALLOC_ARRAY_ARGS: kcalloc uses number as first arg, sizeof is 
generally wrong
#120: FILE: drivers/gpu/drm/i915/selftests/i915_gem_context.c:127:
+   ctx = kcalloc(sizeof(*ctx), nctx, GFP_KERNEL);

total: 0 errors, 1 warnings, 0 checks, 203 lines checked
c57b5226773f drm/i915/execlists: Delay updating ring register state after resume
-:68: CHECK:SPACING: spaces preferred around that '+' (ctx:VxV)
#68: FILE: drivers/gpu/drm/i915/intel_lrc.c:2891:
+   ce->lrc_reg_state[CTX_RING_HEAD+1] = 0;
   ^

-:69: CHECK:SPACING: spaces preferred around that '+' (ctx:VxV)
#69: FILE: drivers/gpu/drm/i915/intel_lrc.c:2892:
+   ce->lrc_reg_state[CTX_RING_TAIL+1] = 0;
   ^

total: 0 errors, 0 warnings, 2 checks, 52 lines checked
eded3ed0adbe drm/i915/execlists: Use coherent writes into the context image
-:56: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#56: FILE: drivers/gpu/drm/i915/i915_perf.c:1851:
+   regs = i915_gem_object_pin_map(ce->state->obj,
+ i915_coherent_map_type(dev_priv));

total: 0 errors, 0 warnings, 1 checks, 71 lines checked
47868ad3229b drm/i915/execlists: Onion unwind for logical_ring_init() failure
3d1e691c76dc drm/i915: Report the number of closed vma held by each context in 
debugfs
-:43: WARNING:LONG_LINE: line over 100 characters
#43: FILE: drivers/gpu/drm/i915/i915_debugfs.c:350:
+   seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu 
inactive, %llu global, %llu shared, %llu unbound, %llu closed)\n", \

total: 0 errors, 1 warnings, 0 checks, 169 lines checked
76d02ab168e3 drm/i915: Remove debugfs/i915_ppgtt_info
85f92b3ad0b5 drm/i915/execlists: Assert the queue is non-empty on unsubmitting
-:9: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description 
(prefer a maximum 75 chars per line)
#9: 
<0>[  531.960431] drv_self-48067 527402570us : intel_gpu_reset: 
engine_mask=1, ret=0, retry=0

total: 0 errors, 1 warnings, 0 checks, 7 lines checked
79bd577c5774 drm/i915: Handle incomplete Z_FINISH for compressed error states
0c32e06efa4a drm/i915: Clear the error PTE just once on finish
fa0b7f94b44a drm/i915: Cache the error string
f5e5e1732bd4 drm/i915: Attach the pci match data to the device upon creation
-:83: WARNING:AVOID_BUG: Avoid crashing the kernel - try using WARN_ON & 
recovery code rather than BUG() or BUG_ON()
#83: FILE: drivers/gpu/drm/i915/i915_drv.c:1353:
+   BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * 
BITS_PER_BYTE);

total: 0 errors, 1 warnings, 0 checks, 107 lines checked
c8b527abd7f5 drm/i915: Track all held rpm wakerefs
-:105: CHECK:UNCOMMENTED_DEFINITION: spinlock_t definition without comment
#105: FILE: drivers/gpu/drm/i915/i915_drv.h:1293:
+   spinlock_t debug_lock;

total: 0 errors, 0 warnings, 1 checks, 571 lines checked
0e5cd2856b69 drm/i915: Markup paired operations on wakerefs
-:707: WARNING:NEW_TYPEDEFS: do not add new typedefs
#707: FILE: drivers/gpu/drm/i915/i915_drv.h:130:
+typedef depot_stack_handle_t intel_wakeref_t;

total: 0 errors, 1 warnings, 0 checks, 1970 lines checked
011f0dab532a drm/i915: Syntatic sugar for using intel_runtime_pm
-:491: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible 
side-effects?
#491: FILE: drivers/gpu/drm/i915/intel_drv.h:2062:
+#define with_intel_runtime_pm(i915, wf) \
+   for (wf = intel_runtime_pm_get(i915); wf; \
+intel_runtime_pm_put(i915, wf), wf = 0)

-:491: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'wf' - possible side-effects?
#491: FILE: drivers/gpu/drm/i915/intel_drv.h:2062:
+#define with_intel_runtime_pm(i915, wf) \
+   for (wf = intel_runtime_pm_get(i915); wf; \
+intel_runtime_pm_put(i915, wf), wf = 0)

-:495: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible 
side-effects?
#495: FILE: drivers/gpu/drm/i9

[Intel-gfx] [PATCH 11/23] drm/i915: Handle incomplete Z_FINISH for compressed error states

[Chris Wilson]

The final call to zlib_deflate(Z_FINISH) may require more output
space to be allocated and so needs to re-invoked. Failure to do so in
the current code leads to incomplete zlib streams (albeit intact due to
the use of Z_SYNC_FLUSH) resulting in the occasional short object
capture.

Testcase: igt/i915-error-capture.js
Fixes: 0a97015d45ee ("drm/i915: Compress GPU objects in error state")
Signed-off-by: Chris Wilson 
Cc: Joonas Lahtinen 
Cc:  # v4.10+
---
 drivers/gpu/drm/i915/i915_gpu_error.c | 60 +--
 1 file changed, 47 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
b/drivers/gpu/drm/i915/i915_gpu_error.c
index f7f2aa71d8d9..2eb26ea38d7c 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -237,6 +237,7 @@ static int compress_page(struct compress *c,
 struct drm_i915_error_object *dst)
 {
struct z_stream_s *zstream = &c->zstream;
+   int flush = Z_NO_FLUSH;
 
zstream->next_in = src;
if (c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE))
@@ -257,8 +258,11 @@ static int compress_page(struct compress *c,
zstream->avail_out = PAGE_SIZE;
}
 
-   if (zlib_deflate(zstream, Z_SYNC_FLUSH) != Z_OK)
+   if (zlib_deflate(zstream, flush) != Z_OK)
return -EIO;
+
+   if (zstream->avail_out)
+   flush = Z_SYNC_FLUSH;
} while (zstream->avail_in);
 
/* Fallback to uncompressed if we increase size? */
@@ -268,19 +272,43 @@ static int compress_page(struct compress *c,
return 0;
 }
 
-static void compress_fini(struct compress *c,
+static int compress_flush(struct compress *c,
  struct drm_i915_error_object *dst)
 {
struct z_stream_s *zstream = &c->zstream;
+   unsigned long page;
 
-   if (dst) {
-   zlib_deflate(zstream, Z_FINISH);
-   dst->unused = zstream->avail_out;
-   }
+   do {
+   switch (zlib_deflate(zstream, Z_FINISH)) {
+   case Z_OK: /* more space requested */
+   page = __get_free_page(GFP_ATOMIC | __GFP_NOWARN);
+   if (!page)
+   return -ENOMEM;
+
+   dst->pages[dst->page_count++] = (void *)page;
+   zstream->next_out = (void *)page;
+   zstream->avail_out = PAGE_SIZE;
+   break;
+   case Z_STREAM_END:
+   goto end;
+   default: /* any error */
+   return -EIO;
+   }
+   } while (1);
+
+end:
+   memset(zstream->next_out, 0, zstream->avail_out);
+   dst->unused = zstream->avail_out;
+   return 0;
+}
+
+static void compress_fini(struct compress *c,
+ struct drm_i915_error_object *dst)
+{
+   struct z_stream_s *zstream = &c->zstream;
 
zlib_deflateEnd(zstream);
kfree(zstream->workspace);
-
if (c->tmp)
free_page((unsigned long)c->tmp);
 }
@@ -319,6 +347,12 @@ static int compress_page(struct compress *c,
return 0;
 }
 
+static int compress_flush(struct compress *c,
+ struct drm_i915_error_object *dst)
+{
+   return 0;
+}
+
 static void compress_fini(struct compress *c,
  struct drm_i915_error_object *dst)
 {
@@ -951,15 +985,15 @@ i915_error_object_create(struct drm_i915_private *i915,
if (ret)
goto unwind;
}
-   goto out;
 
+   if (compress_flush(&compress, dst)) {
 unwind:
-   while (dst->page_count--)
-   free_page((unsigned long)dst->pages[dst->page_count]);
-   kfree(dst);
-   dst = NULL;
+   while (dst->page_count--)
+   free_page((unsigned long)dst->pages[dst->page_count]);
+   kfree(dst);
+   dst = NULL;
+   }
 
-out:
compress_fini(&compress, dst);
ggtt->vm.clear_range(&ggtt->vm, slot, PAGE_SIZE);
return dst;
-- 
2.19.0.rc1

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[Intel-gfx] [PATCH 02/23] drm/i915/execlists: Avoid kicking priority on the current context

[Chris Wilson]

If the request is currently on the HW (in port 0), then we do not need
to kick the submission tasklet to evaluate whether we should be
preempting itself in order to execute it again.

In the case that was annoying me:

   execlists_schedule: rq(18:211173).prio=0 -> 2
   need_preempt: last(18:211174).prio=0, queue.prio=2

We are bumping the priority of the first of a pair of requests running
in the current context. Then when evaluating preempt, we would see that
that our priority request is higher than the last executing request in
ELSP0 and so trigger preemption, not realising that our intended request
was already executing.

v2: As we assume state of the execlists->port[] that is only valid while
we hold the timeline lock we have to repeat some earlier tests that on
the validity of the node.
v3: Wrap guc submission under the timeline.lock as is now the way of all
things.

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/intel_guc_submission.c | 18 +++--
 drivers/gpu/drm/i915/intel_lrc.c| 41 +++--
 2 files changed, 36 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c 
b/drivers/gpu/drm/i915/intel_guc_submission.c
index 07b9d313b019..7b878790228a 100644
--- a/drivers/gpu/drm/i915/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/intel_guc_submission.c
@@ -771,19 +771,8 @@ static bool __guc_dequeue(struct intel_engine_cs *engine)
 
 static void guc_dequeue(struct intel_engine_cs *engine)
 {
-   unsigned long flags;
-   bool submit;
-
-   local_irq_save(flags);
-
-   spin_lock(&engine->timeline.lock);
-   submit = __guc_dequeue(engine);
-   spin_unlock(&engine->timeline.lock);
-
-   if (submit)
+   if ( __guc_dequeue(engine))
guc_submit(engine);
-
-   local_irq_restore(flags);
 }
 
 static void guc_submission_tasklet(unsigned long data)
@@ -792,6 +781,9 @@ static void guc_submission_tasklet(unsigned long data)
struct intel_engine_execlists * const execlists = &engine->execlists;
struct execlist_port *port = execlists->port;
struct i915_request *rq;
+   unsigned long flags;
+
+   spin_lock_irqsave(&engine->timeline.lock, flags);
 
rq = port_request(port);
while (rq && i915_request_completed(rq)) {
@@ -815,6 +807,8 @@ static void guc_submission_tasklet(unsigned long data)
 
if (!execlists_is_active(execlists, EXECLISTS_ACTIVE_PREEMPT))
guc_dequeue(engine);
+
+   spin_unlock_irqrestore(&engine->timeline.lock, flags);
 }
 
 static struct i915_request *
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 9b1f0e5211a0..f2630911337f 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -355,13 +355,8 @@ execlists_unwind_incomplete_requests(struct 
intel_engine_execlists *execlists)
 {
struct intel_engine_cs *engine =
container_of(execlists, typeof(*engine), execlists);
-   unsigned long flags;
-
-   spin_lock_irqsave(&engine->timeline.lock, flags);
 
__unwind_incomplete_requests(engine);
-
-   spin_unlock_irqrestore(&engine->timeline.lock, flags);
 }
 
 static inline void
@@ -1233,9 +1228,13 @@ static void execlists_schedule(struct i915_request 
*request,
 
engine = sched_lock_engine(node, engine);
 
+   /* Recheck after acquiring the engine->timeline.lock */
if (prio <= node->attr.priority)
continue;
 
+   if (i915_sched_node_signaled(node))
+   continue;
+
node->attr.priority = prio;
if (!list_empty(&node->link)) {
if (last != engine) {
@@ -1244,14 +1243,34 @@ static void execlists_schedule(struct i915_request 
*request,
}
GEM_BUG_ON(pl->priority != prio);
list_move_tail(&node->link, &pl->requests);
+   } else {
+   /*
+* If the request is not in the priolist queue because
+* it is not yet runnable, then it doesn't contribute
+* to our preemption decisions. On the other hand,
+* if the request is on the HW, it too is not in the
+* queue; but in that case we may still need to reorder
+* the inflight requests.
+*/
+   if 
(!i915_sw_fence_done(&sched_to_request(node)->submit))
+   continue;
}
 
-   if (prio > engine->execlists.queue_priority &&
-   i915_sw_fence_done(&sched_to_request(node)->submit)) {
-   /* defer submission until after all of our updates */
-   __update_queue(engine, prio);
-   tasklet_hi_schedule(

[Intel-gfx] [PATCH 08/23] drm/i915: Report the number of closed vma held by each context in debugfs

[Chris Wilson]

Include the total size of closed vma when reporting the per_ctx_stats of
debugfs/i915_gem_objects.

Whilst adjusting the context tracking, note that we can simply use our
list of contexts in i915->contexts rather than circumlocute via
dev->filelist and the per-file context idr.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 113 +++-
 1 file changed, 42 insertions(+), 71 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index b4744a68cd88..03637da325ab 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -302,6 +302,7 @@ struct file_stats {
u64 total, unbound;
u64 global, shared;
u64 active, inactive;
+   u64 closed;
 };
 
 static int per_file_stats(int id, void *ptr, void *data)
@@ -336,6 +337,9 @@ static int per_file_stats(int id, void *ptr, void *data)
stats->active += vma->node.size;
else
stats->inactive += vma->node.size;
+
+   if (i915_vma_is_closed(vma))
+   stats->closed += vma->node.size;
}
 
return 0;
@@ -343,7 +347,7 @@ static int per_file_stats(int id, void *ptr, void *data)
 
 #define print_file_stats(m, name, stats) do { \
if (stats.count) \
-   seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu 
inactive, %llu global, %llu shared, %llu unbound)\n", \
+   seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu 
inactive, %llu global, %llu shared, %llu unbound, %llu closed)\n", \
   name, \
   stats.count, \
   stats.total, \
@@ -351,7 +355,8 @@ static int per_file_stats(int id, void *ptr, void *data)
   stats.inactive, \
   stats.global, \
   stats.shared, \
-  stats.unbound); \
+  stats.unbound, \
+  stats.closed); \
 } while (0)
 
 static void print_batch_pool_stats(struct seq_file *m,
@@ -377,44 +382,44 @@ static void print_batch_pool_stats(struct seq_file *m,
print_file_stats(m, "[k]batch pool", stats);
 }
 
-static int per_file_ctx_stats(int idx, void *ptr, void *data)
+static void print_context_stats(struct seq_file *m,
+   struct drm_i915_private *i915)
 {
-   struct i915_gem_context *ctx = ptr;
-   struct intel_engine_cs *engine;
-   enum intel_engine_id id;
-
-   for_each_engine(engine, ctx->i915, id) {
-   struct intel_context *ce = to_intel_context(ctx, engine);
+   struct file_stats kstats = {};
+   struct i915_gem_context *ctx;
 
-   if (ce->state)
-   per_file_stats(0, ce->state->obj, data);
-   if (ce->ring)
-   per_file_stats(0, ce->ring->vma->obj, data);
-   }
+   list_for_each_entry(ctx, &i915->contexts.list, link) {
+   struct file_stats stats = { .file_priv = ctx->file_priv };
+   struct intel_engine_cs *engine;
+   enum intel_engine_id id;
 
-   return 0;
-}
+   for_each_engine(engine, i915, id) {
+   struct intel_context *ce = to_intel_context(ctx, 
engine);
 
-static void print_context_stats(struct seq_file *m,
-   struct drm_i915_private *dev_priv)
-{
-   struct drm_device *dev = &dev_priv->drm;
-   struct file_stats stats;
-   struct drm_file *file;
+   if (ce->state)
+   per_file_stats(0, ce->state->obj, &kstats);
+   if (ce->ring)
+   per_file_stats(0, ce->ring->vma->obj, &kstats);
+   }
 
-   memset(&stats, 0, sizeof(stats));
+   if (!IS_ERR_OR_NULL(stats.file_priv)) {
+   struct drm_file *file = stats.file_priv->file;
+   struct task_struct *task;
 
-   mutex_lock(&dev->struct_mutex);
-   if (dev_priv->kernel_context)
-   per_file_ctx_stats(0, dev_priv->kernel_context, &stats);
+   spin_lock(&file->table_lock);
+   idr_for_each(&file->object_idr, per_file_stats, &stats);
+   spin_unlock(&file->table_lock);
 
-   list_for_each_entry(file, &dev->filelist, lhead) {
-   struct drm_i915_file_private *fpriv = file->driver_priv;
-   idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats);
+   rcu_read_lock();
+   task = pid_task(ctx->pid ?: file->pid, PIDTYPE_PID);
+   print_file_stats(m,
+task ? task->comm : "",
+stats);
+   rcu_read_unlock();
+

[Intel-gfx] [PATCH 07/23] drm/i915/execlists: Onion unwind for logical_ring_init() failure

[Chris Wilson]

Fix up the error unwind for logical_ring_init() failing by moving the
cleanup into the callers who own the various bits of state during
initialisation.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/intel_lrc.c | 18 +++---
 1 file changed, 11 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 31207996c6f1..939e0fa7523f 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2413,7 +2413,7 @@ static int logical_ring_init(struct intel_engine_cs 
*engine)
 
ret = intel_engine_init_common(engine);
if (ret)
-   goto error;
+   return ret;
 
if (HAS_LOGICAL_RING_ELSQ(i915)) {
execlists->submit_reg = i915->regs +
@@ -2455,10 +2455,6 @@ static int logical_ring_init(struct intel_engine_cs 
*engine)
reset_csb_pointers(execlists);
 
return 0;
-
-error:
-   intel_logical_ring_cleanup(engine);
-   return ret;
 }
 
 int logical_render_ring_init(struct intel_engine_cs *engine)
@@ -2481,10 +2477,14 @@ int logical_render_ring_init(struct intel_engine_cs 
*engine)
engine->emit_breadcrumb = gen8_emit_breadcrumb_rcs;
engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_rcs_sz;
 
-   ret = intel_engine_create_scratch(engine, PAGE_SIZE);
+   ret = logical_ring_init(engine);
if (ret)
return ret;
 
+   ret = intel_engine_create_scratch(engine, PAGE_SIZE);
+   if (ret)
+   goto err_cleanup_common;
+
ret = intel_init_workaround_bb(engine);
if (ret) {
/*
@@ -2496,7 +2496,11 @@ int logical_render_ring_init(struct intel_engine_cs 
*engine)
  ret);
}
 
-   return logical_ring_init(engine);
+   return 0;
+
+err_cleanup_common:
+   intel_engine_cleanup_common(engine);
+   return ret;
 }
 
 int logical_xcs_ring_init(struct intel_engine_cs *engine)
-- 
2.19.0.rc1

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[Intel-gfx] [PATCH 04/23] drm/i915/selftests: Basic stress test for rapid context switching

[Chris Wilson]

We need to exercise the HW and submission paths for switching contexts
rapidly to check that features such as execlists' wa_tail are adequate.
Plus it's an interesting baseline latency metric.

Signed-off-by: Chris Wilson 
---
 .../gpu/drm/i915/selftests/i915_gem_context.c | 185 ++
 1 file changed, 185 insertions(+)

diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c 
b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
index 1c92560d35da..d8004bf5a4f0 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
@@ -22,6 +22,8 @@
  *
  */
 
+#include 
+
 #include "../i915_selftest.h"
 #include "i915_random.h"
 #include "igt_flush_test.h"
@@ -32,6 +34,188 @@
 
 #define DW_PER_PAGE (PAGE_SIZE / sizeof(u32))
 
+struct live_test {
+   struct drm_i915_private *i915;
+   const char *func;
+   const char *name;
+
+   unsigned int reset_count;
+};
+
+static int begin_live_test(struct live_test *t,
+  struct drm_i915_private *i915,
+  const char *func,
+  const char *name)
+{
+   int err;
+
+   t->i915 = i915;
+   t->func = func;
+   t->name = name;
+
+   err = i915_gem_wait_for_idle(i915,
+I915_WAIT_LOCKED,
+MAX_SCHEDULE_TIMEOUT);
+   if (err) {
+   pr_err("%s(%s): failed to idle before, with err=%d!",
+  func, name, err);
+   return err;
+   }
+
+   i915->gpu_error.missed_irq_rings = 0;
+   t->reset_count = i915_reset_count(&i915->gpu_error);
+
+   return 0;
+}
+
+static int end_live_test(struct live_test *t)
+{
+   struct drm_i915_private *i915 = t->i915;
+
+   i915_retire_requests(i915);
+
+   if (wait_for(intel_engines_are_idle(i915), 10)) {
+   pr_err("%s(%s): GPU not idle\n", t->func, t->name);
+   return -EIO;
+   }
+
+   if (t->reset_count != i915_reset_count(&i915->gpu_error)) {
+   pr_err("%s(%s): GPU was reset %d times!\n",
+  t->func, t->name,
+  i915_reset_count(&i915->gpu_error) - t->reset_count);
+   return -EIO;
+   }
+
+   if (i915->gpu_error.missed_irq_rings) {
+   pr_err("%s(%s): Missed interrupts on engines %lx\n",
+  t->func, t->name, i915->gpu_error.missed_irq_rings);
+   return -EIO;
+   }
+
+   return 0;
+}
+
+static int live_nop_switch(void *arg)
+{
+   const unsigned int nctx = 1024;
+   struct drm_i915_private *i915 = arg;
+   struct intel_engine_cs *engine;
+   struct i915_gem_context **ctx;
+   enum intel_engine_id id;
+   struct drm_file *file;
+   struct live_test t;
+   unsigned long n;
+   int err = -ENODEV;
+
+   /*
+* Create as many contexts as we can feasibly get away with
+* and check we can switch between them rapidly.
+*
+* Serves as very simple stress test for submission and HW switching
+* between contexts.
+*/
+
+   if (!DRIVER_CAPS(i915)->has_logical_contexts)
+   return 0;
+
+   file = mock_file(i915);
+   if (IS_ERR(file))
+   return PTR_ERR(file);
+
+   mutex_lock(&i915->drm.struct_mutex);
+
+   ctx = kcalloc(sizeof(*ctx), nctx, GFP_KERNEL);
+   if (!ctx) {
+   err = -ENOMEM;
+   goto out_unlock;
+   }
+
+   for (n = 0; n < nctx; n++) {
+   ctx[n] = i915_gem_create_context(i915, file->driver_priv);
+   if (IS_ERR(ctx[n])) {
+   err = PTR_ERR(ctx[n]);
+   goto out_unlock;
+   }
+   }
+
+   for_each_engine(engine, i915, id) {
+   struct i915_request *request;
+   unsigned long end_time, prime;
+   ktime_t times[2] = {};
+
+   times[0] = ktime_get_raw();
+   for (n = 0; n < nctx; n++) {
+   request = i915_request_alloc(engine, ctx[n]);
+   i915_request_add(request);
+   }
+   i915_request_wait(request,
+ I915_WAIT_LOCKED,
+ MAX_SCHEDULE_TIMEOUT);
+   times[1] = ktime_get_raw();
+
+   pr_info("Populated %d contexts on %s in %lluns\n",
+   nctx, engine->name, ktime_to_ns(times[1] - times[0]));
+
+   err = begin_live_test(&t, i915, __func__, engine->name);
+   if (err)
+   goto out_unlock;
+
+   end_time = jiffies + i915_selftest.timeout_jiffies;
+   for_each_prime_number_from(prime, 2, 8192) {
+   times[1] = ktime_get_raw();
+
+   for (n = 0; n < prime; n++) {
+   request = i915

[Intel-gfx] [PATCH 18/23] drm/i915: Markup paired operations on display power domains

[Chris Wilson]

The majority of runtime-pm operations are bounded and scoped within a
function; these are easy to verify that the wakeref are handled
correctly. We can employ the compiler to help us, and reduce the number
of wakerefs tracked when debugging, by passing around cookies provided
by the various rpm_get functions to their rpm_put counterpart. This
makes the pairing explicit, and given the required wakeref cookie the
compiler can verify that we pass an initialised value to the rpm_put
(quite handy for double checking error paths).

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 35 ++--
 drivers/gpu/drm/i915/i915_drv.h |  2 +
 drivers/gpu/drm/i915/i915_gem.c |  4 +-
 drivers/gpu/drm/i915/intel_audio.c  |  3 +-
 drivers/gpu/drm/i915/intel_cdclk.c  | 10 ++--
 drivers/gpu/drm/i915/intel_crt.c| 25 +
 drivers/gpu/drm/i915/intel_csr.c| 25 +++--
 drivers/gpu/drm/i915/intel_ddi.c| 36 -
 drivers/gpu/drm/i915/intel_display.c| 70 +++-
 drivers/gpu/drm/i915/intel_dp.c | 29 +-
 drivers/gpu/drm/i915/intel_dpll_mgr.c   | 66 +++
 drivers/gpu/drm/i915/intel_drv.h| 17 --
 drivers/gpu/drm/i915/intel_hdmi.c   | 18 ---
 drivers/gpu/drm/i915/intel_i2c.c| 20 +++
 drivers/gpu/drm/i915/intel_lvds.c   |  8 +--
 drivers/gpu/drm/i915/intel_pipe_crc.c   |  6 ++-
 drivers/gpu/drm/i915/intel_pm.c |  7 ++-
 drivers/gpu/drm/i915/intel_runtime_pm.c | 71 -
 drivers/gpu/drm/i915/intel_sprite.c | 24 ++---
 drivers/gpu/drm/i915/vlv_dsi.c  |  8 +--
 20 files changed, 313 insertions(+), 171 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 98fa216d19bb..b1fdaa8875cb 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -627,10 +627,12 @@ static void gen8_display_interrupt_info(struct seq_file 
*m)
 
for_each_pipe(dev_priv, pipe) {
enum intel_display_power_domain power_domain;
+   intel_wakeref_t wakeref;
 
power_domain = POWER_DOMAIN_PIPE(pipe);
-   if (!intel_display_power_get_if_enabled(dev_priv,
-   power_domain)) {
+   wakeref = intel_display_power_get_if_enabled(dev_priv,
+   power_domain);
+   if (!wakeref) {
seq_printf(m, "Pipe %c power disabled\n",
   pipe_name(pipe));
continue;
@@ -645,7 +647,7 @@ static void gen8_display_interrupt_info(struct seq_file *m)
   pipe_name(pipe),
   I915_READ(GEN8_DE_PIPE_IER(pipe)));
 
-   intel_display_power_put(dev_priv, power_domain);
+   intel_display_power_put(dev_priv, power_domain, wakeref);
}
 
seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
@@ -681,6 +683,8 @@ static int i915_interrupt_info(struct seq_file *m, void 
*data)
wakeref = intel_runtime_pm_get(dev_priv);
 
if (IS_CHERRYVIEW(dev_priv)) {
+   intel_wakeref_t pref;
+
seq_printf(m, "Master Interrupt Control:\t%08x\n",
   I915_READ(GEN8_MASTER_IRQ));
 
@@ -696,8 +700,9 @@ static int i915_interrupt_info(struct seq_file *m, void 
*data)
enum intel_display_power_domain power_domain;
 
power_domain = POWER_DOMAIN_PIPE(pipe);
-   if (!intel_display_power_get_if_enabled(dev_priv,
-   power_domain)) {
+   pref = intel_display_power_get_if_enabled(dev_priv,
+ power_domain);
+   if (!pref) {
seq_printf(m, "Pipe %c power disabled\n",
   pipe_name(pipe));
continue;
@@ -707,17 +712,17 @@ static int i915_interrupt_info(struct seq_file *m, void 
*data)
   pipe_name(pipe),
   I915_READ(PIPESTAT(pipe)));
 
-   intel_display_power_put(dev_priv, power_domain);
+   intel_display_power_put(dev_priv, power_domain, pref);
}
 
-   intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
+   pref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
seq_printf(m, "Port hotplug:\t%08x\n",
   I915_READ(PORT_HOTPLUG_EN));
seq_printf(m, "DPFLIPSTAT:\t%08x\n",
   I915_READ(VLV_DPFLIPSTAT));
seq_printf(m, "DPINVGTT:\t%08x\n",

[Intel-gfx] [PATCH 12/23] drm/i915: Clear the error PTE just once on finish

[Chris Wilson]

We do not need to continually clear our dedicated PTE for error capture
as it will be updated and invalidated to the next object. Only at the
end do we wish to be sure that the PTE doesn't point back to any buffer.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_gpu_error.c | 10 +-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 2eb26ea38d7c..3bd4f957abb9 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -995,7 +995,6 @@ i915_error_object_create(struct drm_i915_private *i915,
}
 
compress_fini(&compress, dst);
-   ggtt->vm.clear_range(&ggtt->vm, slot, PAGE_SIZE);
return dst;
 }
 
@@ -1775,6 +1774,14 @@ static unsigned long capture_find_epoch(const struct 
i915_gpu_state *error)
return epoch;
 }
 
+static void capture_finish(struct i915_gpu_state *error)
+{
+   struct i915_ggtt *ggtt = &error->i915->ggtt;
+   const u64 slot = ggtt->error_capture.start;
+
+   ggtt->vm.clear_range(&ggtt->vm, slot, PAGE_SIZE);
+}
+
 static int capture(void *data)
 {
struct i915_gpu_state *error = data;
@@ -1799,6 +1806,7 @@ static int capture(void *data)
 
error->epoch = capture_find_epoch(error);
 
+   capture_finish(error);
return 0;
 }
 
-- 
2.19.0.rc1

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[Intel-gfx] [PATCH 21/23] drm/i915: Complain if hsw_get_pipe_config acquires the same power well twice

[Chris Wilson]

As we only release each power well once, we assume that each transcoder
maps to a different domain. Complain if this is not so.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/intel_display.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 3b76087af74a..d6b74ae2c0a8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9392,6 +9392,8 @@ static bool hsw_get_transcoder_state(struct intel_crtc 
*crtc,
power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
return false;
+
+   WARN_ON(*power_domain_mask & BIT_ULL(power_domain));
*power_domain_mask |= BIT_ULL(power_domain);
 
tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
@@ -9419,6 +9421,8 @@ static bool bxt_get_dsi_transcoder_state(struct 
intel_crtc *crtc,
power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
continue;
+
+   WARN_ON(*power_domain_mask & BIT_ULL(power_domain));
*power_domain_mask |= BIT_ULL(power_domain);
 
/*
@@ -9550,7 +9554,9 @@ static bool haswell_get_pipe_config(struct intel_crtc 
*crtc,
 
power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
+   WARN_ON(power_domain_mask & BIT_ULL(power_domain));
power_domain_mask |= BIT_ULL(power_domain);
+
if (INTEL_GEN(dev_priv) >= 9)
skylake_get_pfit_config(crtc, pipe_config);
else
-- 
2.19.0.rc1

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[Intel-gfx] [PATCH 03/23] drm/i915: Missed interrupt simulation is no more, tell the world

[Chris Wilson]

Using the guc, we cannot disable the user interrupt generation as we use
it for driving submission. And from Icelake, we no longer have the
ability to individually mask interrupt generation from each engine,
disabling our ability to fake missed interrupts.

In both cases, report back to userspace that the missed interrupt
generator is no longer available.

Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 1f7051e97afb..b4744a68cd88 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4117,6 +4117,17 @@ i915_ring_test_irq_set(void *data, u64 val)
 {
struct drm_i915_private *i915 = data;
 
+   /* GuC keeps the user interrupt permanently enabled for submission */
+   if (USES_GUC_SUBMISSION(i915))
+   return -ENODEV;
+
+   /*
+* From icl, we can no longer individually mask interrupt generation
+* from each engine.
+*/
+   if (INTEL_GEN(i915) >= 11)
+   return -ENODEV;
+
val &= INTEL_INFO(i915)->ring_mask;
DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
 
-- 
2.19.0.rc1

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[Intel-gfx] [PATCH 17/23] drm/i915: Syntatic sugar for using intel_runtime_pm

[Chris Wilson]

Frequently, we use intel_runtime_pm_get/_put around a small block.
Formalise that usage by providing a macro to define such a block with an
automatic closure to scope the intel_runtime_pm wakeref to that block,
i.e. macro abuse smelling of python.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_debugfs.c  | 163 ++-
 drivers/gpu/drm/i915/i915_gem.c  |  10 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c  |  23 ++--
 drivers/gpu/drm/i915/i915_gem_shrinker.c |  44 +++---
 drivers/gpu/drm/i915/i915_pmu.c  |   7 +-
 drivers/gpu/drm/i915/i915_sysfs.c|   7 +-
 drivers/gpu/drm/i915/intel_drv.h |   8 ++
 drivers/gpu/drm/i915/intel_guc_log.c |  26 ++--
 drivers/gpu/drm/i915/intel_huc.c |   7 +-
 drivers/gpu/drm/i915/intel_panel.c   |  18 +--
 drivers/gpu/drm/i915/intel_uncore.c  |  30 ++---
 11 files changed, 162 insertions(+), 181 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index dbfe4e456d97..98fa216d19bb 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -952,9 +952,9 @@ static int i915_gpu_info_open(struct inode *inode, struct 
file *file)
struct i915_gpu_state *gpu;
intel_wakeref_t wakeref;
 
-   wakeref = intel_runtime_pm_get(i915);
-   gpu = i915_capture_gpu_state(i915);
-   intel_runtime_pm_put(i915, wakeref);
+   gpu = NULL;
+   with_intel_runtime_pm(i915, wakeref)
+   gpu = i915_capture_gpu_state(i915);
if (!gpu)
return -ENOMEM;
 
@@ -1015,9 +1015,8 @@ i915_next_seqno_set(void *data, u64 val)
if (ret)
return ret;
 
-   wakeref = intel_runtime_pm_get(dev_priv);
-   ret = i915_gem_set_global_seqno(dev, val);
-   intel_runtime_pm_put(dev_priv, wakeref);
+   with_intel_runtime_pm(dev_priv, wakeref)
+   ret = i915_gem_set_global_seqno(dev, val);
 
mutex_unlock(&dev->struct_mutex);
 
@@ -1305,17 +1304,15 @@ static int i915_hangcheck_info(struct seq_file *m, void 
*unused)
return 0;
}
 
-   wakeref = intel_runtime_pm_get(dev_priv);
+   with_intel_runtime_pm(dev_priv, wakeref) {
+   for_each_engine(engine, dev_priv, id) {
+   acthd[id] = intel_engine_get_active_head(engine);
+   seqno[id] = intel_engine_get_seqno(engine);
+   }
 
-   for_each_engine(engine, dev_priv, id) {
-   acthd[id] = intel_engine_get_active_head(engine);
-   seqno[id] = intel_engine_get_seqno(engine);
+   intel_engine_get_instdone(dev_priv->engine[RCS], &instdone);
}
 
-   intel_engine_get_instdone(dev_priv->engine[RCS], &instdone);
-
-   intel_runtime_pm_put(dev_priv, wakeref);
-
if (timer_pending(&dev_priv->gpu_error.hangcheck_work.timer))
seq_printf(m, "Hangcheck active, timer fires in %dms\n",
   
jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
@@ -1591,18 +1588,16 @@ static int i915_drpc_info(struct seq_file *m, void 
*unused)
 {
struct drm_i915_private *dev_priv = node_to_i915(m->private);
intel_wakeref_t wakeref;
-   int err;
-
-   wakeref = intel_runtime_pm_get(dev_priv);
-
-   if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
-   err = vlv_drpc_info(m);
-   else if (INTEL_GEN(dev_priv) >= 6)
-   err = gen6_drpc_info(m);
-   else
-   err = ironlake_drpc_info(m);
+   int err = -ENODEV;
 
-   intel_runtime_pm_put(dev_priv, wakeref);
+   with_intel_runtime_pm(dev_priv, wakeref) {
+   if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
+   err = vlv_drpc_info(m);
+   else if (INTEL_GEN(dev_priv) >= 6)
+   err = gen6_drpc_info(m);
+   else
+   err = ironlake_drpc_info(m);
+   }
 
return err;
 }
@@ -2167,9 +2162,8 @@ static int i915_huc_load_status_info(struct seq_file *m, 
void *data)
p = drm_seq_file_printer(m);
intel_uc_fw_dump(&dev_priv->huc.fw, &p);
 
-   wakeref = intel_runtime_pm_get(dev_priv);
-   seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2));
-   intel_runtime_pm_put(dev_priv, wakeref);
+   with_intel_runtime_pm(dev_priv, wakeref)
+   seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2));
 
return 0;
 }
@@ -2179,7 +2173,6 @@ static int i915_guc_load_status_info(struct seq_file *m, 
void *data)
struct drm_i915_private *dev_priv = node_to_i915(m->private);
intel_wakeref_t wakeref;
struct drm_printer p;
-   u32 tmp, i;
 
if (!HAS_GUC(dev_priv))
return -ENODEV;
@@ -2187,22 +2180,23 @@ static int i915_guc_load_status_info(struct seq_file 
*m, void *data)
p = drm_seq_file_pri

[Intel-gfx] [PATCH 14/23] drm/i915: Attach the pci match data to the device upon creation

[Chris Wilson]

Attach our device_info to the our i915 private on creation so that it is
always available for inspection.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_drv.c | 66 +++--
 1 file changed, 38 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 77a4a01ddc08..12f4f929 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -870,7 +870,6 @@ static void intel_detect_preproduction_hw(struct 
drm_i915_private *dev_priv)
 /**
  * i915_driver_init_early - setup state not requiring device access
  * @dev_priv: device private
- * @ent: the matching pci_device_id
  *
  * Initialize everything that is a "SW-only" state, that is state not
  * requiring accessing the device or exposing the driver via kernel internal
@@ -878,25 +877,13 @@ static void intel_detect_preproduction_hw(struct 
drm_i915_private *dev_priv)
  * system memory allocation, setting up device specific attributes and
  * function hooks not requiring accessing the device.
  */
-static int i915_driver_init_early(struct drm_i915_private *dev_priv,
- const struct pci_device_id *ent)
+static int i915_driver_init_early(struct drm_i915_private *dev_priv)
 {
-   const struct intel_device_info *match_info =
-   (struct intel_device_info *)ent->driver_data;
-   struct intel_device_info *device_info;
int ret = 0;
 
if (i915_inject_load_failure())
return -ENODEV;
 
-   /* Setup the write-once "constant" device info */
-   device_info = mkwrite_device_info(dev_priv);
-   memcpy(device_info, match_info, sizeof(*device_info));
-   device_info->device_id = dev_priv->drm.pdev->device;
-
-   BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
-sizeof(device_info->platform_mask) * BITS_PER_BYTE);
-   BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * 
BITS_PER_BYTE);
spin_lock_init(&dev_priv->irq_lock);
spin_lock_init(&dev_priv->gpu_error.lock);
mutex_init(&dev_priv->backlight_lock);
@@ -1335,6 +1322,39 @@ static void i915_welcome_messages(struct 
drm_i915_private *dev_priv)
DRM_INFO("DRM_I915_DEBUG_RUNTIME_PM enabled\n");
 }
 
+static struct drm_i915_private *
+i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
+{
+   const struct intel_device_info *match_info =
+   (struct intel_device_info *)ent->driver_data;
+   struct intel_device_info *device_info;
+   struct drm_i915_private *i915;
+
+   i915 = kzalloc(sizeof(*i915), GFP_KERNEL);
+   if (!i915)
+   return NULL;
+
+   if (drm_dev_init(&i915->drm, &driver, &pdev->dev)) {
+   kfree(i915);
+   return NULL;
+   }
+
+   i915->drm.pdev = pdev;
+   i915->drm.dev_private = i915;
+   pci_set_drvdata(pdev, &i915->drm);
+
+   /* Setup the write-once "constant" device info */
+   device_info = mkwrite_device_info(i915);
+   memcpy(device_info, match_info, sizeof(*device_info));
+   device_info->device_id = pdev->device;
+
+   BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
+sizeof(device_info->platform_mask) * BITS_PER_BYTE);
+   BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * 
BITS_PER_BYTE);
+
+   return i915;
+}
+
 /**
  * i915_driver_load - setup chip and create an initial config
  * @pdev: PCI device
@@ -1357,24 +1377,15 @@ int i915_driver_load(struct pci_dev *pdev, const struct 
pci_device_id *ent)
if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
driver.driver_features &= ~DRIVER_ATOMIC;
 
-   ret = -ENOMEM;
-   dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
-   if (dev_priv)
-   ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
-   if (ret) {
-   DRM_DEV_ERROR(&pdev->dev, "allocation failed\n");
-   goto out_free;
-   }
-
-   dev_priv->drm.pdev = pdev;
-   dev_priv->drm.dev_private = dev_priv;
+   dev_priv = i915_driver_create(pdev, ent);
+   if (!dev_priv)
+   return -ENOMEM;
 
ret = pci_enable_device(pdev);
if (ret)
goto out_fini;
 
-   pci_set_drvdata(pdev, &dev_priv->drm);
-   ret = i915_driver_init_early(dev_priv, ent);
+   ret = i915_driver_init_early(dev_priv);
if (ret < 0)
goto out_pci_disable;
 
@@ -1426,7 +1437,6 @@ int i915_driver_load(struct pci_dev *pdev, const struct 
pci_device_id *ent)
 out_fini:
i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
drm_dev_fini(&dev_priv->drm);
-out_free:
kfree(dev_priv);
pci_set_drvdata(pdev, NULL);
return ret;
-- 
2.19.0.rc1

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[Intel-gfx] [PATCH 06/23] drm/i915/execlists: Use coherent writes into the context image

[Chris Wilson]

That we use a WB mapping for updating the RING_TAIL register inside the
context image even on !llc machines has been a source of consternation
for every reader. It appears to work on bsw+, but it may just have been
that we have been incredibly bad at detecting the errors.

v2: With extra enthusiasm.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_drv.h | 6 ++
 drivers/gpu/drm/i915/i915_gem.c | 2 ++
 drivers/gpu/drm/i915/i915_perf.c| 3 ++-
 drivers/gpu/drm/i915/intel_engine_cs.c  | 2 +-
 drivers/gpu/drm/i915/intel_lrc.c| 8 +---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
 6 files changed, 17 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 767615ecdea5..db006ff73827 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3073,6 +3073,12 @@ enum i915_map_type {
I915_MAP_FORCE_WC = I915_MAP_WC | I915_MAP_OVERRIDE,
 };
 
+static inline enum i915_map_type
+i915_coherent_map_type(struct drm_i915_private *i915)
+{
+   return HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC;
+}
+
 /**
  * i915_gem_object_pin_map - return a contiguous mapping of the entire object
  * @obj: the object to map into kernel address space
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 89834ce19acd..d6f2bbd6a0dc 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -5417,6 +5417,8 @@ static int __intel_engines_record_defaults(struct 
drm_i915_private *i915)
for_each_engine(engine, i915, id) {
struct i915_vma *state;
 
+   GEM_BUG_ON(to_intel_context(ctx, engine)->pin_count);
+
state = to_intel_context(ctx, engine)->state;
if (!state)
continue;
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index ccb20230df2c..0dabfeb2297a 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1847,7 +1847,8 @@ static int gen8_configure_all_contexts(struct 
drm_i915_private *dev_priv,
if (!ce->state)
continue;
 
-   regs = i915_gem_object_pin_map(ce->state->obj, I915_MAP_WB);
+   regs = i915_gem_object_pin_map(ce->state->obj,
+ i915_coherent_map_type(dev_priv));
if (IS_ERR(regs))
return PTR_ERR(regs);
 
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 10cd051ba29e..c99f2cb9b0e1 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1150,7 +1150,7 @@ void intel_engines_unpark(struct drm_i915_private *i915)
map = NULL;
if (engine->default_state)
map = i915_gem_object_pin_map(engine->default_state,
- I915_MAP_WB);
+ I915_MAP_FORCE_WB);
if (!IS_ERR_OR_NULL(map))
engine->pinned_default_state = map;
 
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 38b90ee4034a..31207996c6f1 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1313,7 +1313,7 @@ static int __context_pin(struct i915_gem_context *ctx, 
struct i915_vma *vma)
 * on an active context (which by nature is already on the GPU).
 */
if (!(vma->flags & I915_VMA_GLOBAL_BIND)) {
-   err = i915_gem_object_set_to_gtt_domain(vma->obj, true);
+   err = i915_gem_object_set_to_wc_domain(vma->obj, true);
if (err)
return err;
}
@@ -1341,7 +1341,9 @@ __execlists_context_pin(struct intel_engine_cs *engine,
if (ret)
goto err;
 
-   vaddr = i915_gem_object_pin_map(ce->state->obj, I915_MAP_WB);
+   vaddr = i915_gem_object_pin_map(ce->state->obj,
+   i915_coherent_map_type(ctx->i915) |
+   I915_MAP_OVERRIDE);
if (IS_ERR(vaddr)) {
ret = PTR_ERR(vaddr);
goto unpin_vma;
@@ -2770,7 +2772,7 @@ populate_lr_context(struct i915_gem_context *ctx,
void *defaults;
 
defaults = i915_gem_object_pin_map(engine->default_state,
-  I915_MAP_WB);
+  I915_MAP_FORCE_WB);
if (IS_ERR(defaults)) {
ret = PTR_ERR(defaults);
goto err_unpin_ctx;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 472939f5c18f..266c6d047d10 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/dri

[Intel-gfx] [PATCH 16/23] drm/i915: Markup paired operations on wakerefs

[Chris Wilson]

The majority of runtime-pm operations are bounded and scoped within a
function; these are easy to verify that the wakeref are handled
correctly. We can employ the compiler to help us, and reduce the number
of wakerefs tracked when debugging, by passing around cookies provided
by the various rpm_get functions to their rpm_put counterpart. This
makes the pairing explicit, and given the required wakeref cookie the
compiler can verify that we pass an initialised value to the rpm_put
(quite handy for double checking error paths).

For regular builds, the compiler should be able to eliminate the unused
local variables and the program growth should be minimal. Fwiw, it came
out as a net improvement as gcc was able to refactor rpm_get and
rpm_get_if_in_use together,

add/remove: 1/1 grow/shrink: 20/9 up/down: 191/-268 (-77)
Function old new   delta
intel_runtime_pm_put_unchecked - 136+136
i915_gem_unpark  396 406 +10
intel_runtime_pm_get 135 141  +6
intel_runtime_pm_get_noresume136 141  +5
i915_perf_open_ioctl43754379  +4
i915_gpu_busy 72  76  +4
i915_gem_idle_work_handler   954 958  +4
capture 68146818  +4
mock_gem_device 14331436  +3
__execlists_submission_tasklet  25732576  +3
i915_sample  756 758  +2
intel_guc_submission_disable 364 365  +1
igt_mmap_offset_exhaustion  10351036  +1
i915_runtime_pm_status   257 258  +1
i915_rps_boost_info 13581359  +1
i915_hangcheck_info 12291230  +1
i915_gem_switch_to_kernel_context682 683  +1
i915_gem_suspend 410 411  +1
i915_gem_resume  254 255  +1
i915_gem_park190 191  +1
i915_engine_info 279 280  +1
intel_rps_mark_interactive   194 193  -1
i915_hangcheck_elapsed  15261525  -1
i915_gem_wait_for_idle   298 297  -1
i915_drop_caches_set 555 554  -1
execlists_submission_tasklet 126 125  -1
aliasing_gtt_bind_vma235 234  -1
i915_gem_retire_work_handler 144 142  -2
igt_evict_contexts.part  916 910  -6
intel_runtime_pm_get_if_in_use   141  23-118
intel_runtime_pm_put 136   --136

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/gvt/aperture_gm.c|   8 +-
 drivers/gpu/drm/i915/gvt/gvt.h|   2 +-
 drivers/gpu/drm/i915/gvt/sched_policy.c   |   2 +-
 drivers/gpu/drm/i915/gvt/scheduler.c  |   4 +-
 drivers/gpu/drm/i915/i915_debugfs.c   | 130 +++---
 drivers/gpu/drm/i915/i915_drv.h   |   6 +-
 drivers/gpu/drm/i915/i915_gem.c   |  57 +---
 drivers/gpu/drm/i915/i915_gem_execbuffer.c|   5 +-
 drivers/gpu/drm/i915/i915_gem_fence_reg.c |   6 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c   |  22 +--
 drivers/gpu/drm/i915/i915_gem_shrinker.c  |  27 ++--
 drivers/gpu/drm/i915/i915_irq.c   |   5 +-
 drivers/gpu/drm/i915/i915_perf.c  |  10 +-
 drivers/gpu/drm/i915/i915_pmu.c   |  26 ++--
 drivers/gpu/drm/i915/i915_sysfs.c |  24 ++--
 drivers/gpu/drm/i915/intel_display.c  |   5 +-
 drivers/gpu/drm/i915/intel_drv.h  |  15 +-
 drivers/gpu/drm/i915/intel_engine_cs.c|  12 +-
 drivers/gpu/drm/i915/intel_fbdev.c|   7 +-
 drivers/gpu/drm/i915/intel_guc_log.c  |  15 +-
 drivers/gpu/drm/i915/intel_hotplug.c  |   5 +-
 drivers/gpu/drm/i915/intel_huc.c  |   5 +-
 drivers/gpu/drm/i915/intel_panel.c|   5 +-
 drivers/gpu/drm/i915/intel_runtime_pm.c   |  89 +---
 drivers/gpu/drm/i915/intel_uncore.c   |   5 +-
 drivers/gpu/drm/i915/selftests/huge_pages.c   |   5 +-
 drivers/gpu/drm/i915/selftests/i915_gem.c |  29 ++--
 .../gpu/drm/i915/selftests/i915_gem_context.c |  12 +-
 .../gpu/drm/i915/selftests/i915_gem_evict.c   |  11 +-
 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c |  10 +-
 .../gpu/drm/i915/selftests/i915_gem_object.c  |  18 ++-
 .../gpu/drm/i915/selftests/intel_hangcheck.c  |   5 +-
 32 files changed, 382 insertions(+), 205 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/aperture_gm.c 
b/drivers/gpu/drm/i915/gvt/aperture_gm.c
index fe754022e356..6372ece10880 100644
--- a/drivers/gpu/drm/i915/gvt/ap

[Intel-gfx] [PATCH 20/23] drm/i915/dp: Markup pps lock power well

[Chris Wilson]

Track where and when we acquire and release the power well for pps
access along the dp aux link, with a view to detecting if we leak any
wakerefs.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/intel_dp.c | 223 +---
 1 file changed, 116 insertions(+), 107 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 4c897d63f8d2..98c43c4b38db 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -652,28 +652,35 @@ intel_dp_init_panel_power_sequencer_registers(struct 
intel_dp *intel_dp,
 static void
 intel_dp_pps_init(struct intel_dp *intel_dp);
 
-static void pps_lock(struct intel_dp *intel_dp)
+static intel_wakeref_t pps_lock(struct intel_dp *intel_dp)
 {
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+   intel_wakeref_t wakeref;
 
/*
 * See intel_power_sequencer_reset() why we need
 * a power domain reference here.
 */
-   intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
+   wakeref = intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
 
mutex_lock(&dev_priv->pps_mutex);
+
+   return wakeref;
 }
 
-static void pps_unlock(struct intel_dp *intel_dp)
+static intel_wakeref_t pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t 
wakeref)
 {
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 
mutex_unlock(&dev_priv->pps_mutex);
 
-   intel_display_power_put_unchecked(dev_priv, intel_dp->aux_power_domain);
+   intel_display_power_put(dev_priv, intel_dp->aux_power_domain, wakeref);
+   return 0;
 }
 
+#define with_pps_lock(dp, wf) \
+   for (wf = pps_lock(dp); wf; wf = pps_unlock(dp, wf))
+
 static void
 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 {
@@ -1022,30 +1029,30 @@ static int edp_notify_handler(struct notifier_block 
*this, unsigned long code,
struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
 edp_notifier);
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+   intel_wakeref_t wakeref;
 
if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART)
return 0;
 
-   pps_lock(intel_dp);
-
-   if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
-   enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
-   i915_reg_t pp_ctrl_reg, pp_div_reg;
-   u32 pp_div;
-
-   pp_ctrl_reg = PP_CONTROL(pipe);
-   pp_div_reg  = PP_DIVISOR(pipe);
-   pp_div = I915_READ(pp_div_reg);
-   pp_div &= PP_REFERENCE_DIVIDER_MASK;
-
-   /* 0x1F write to PP_DIV_REG sets max cycle delay */
-   I915_WRITE(pp_div_reg, pp_div | 0x1F);
-   I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
-   msleep(intel_dp->panel_power_cycle_delay);
+   with_pps_lock(intel_dp, wakeref) {
+   if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
+   enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
+   i915_reg_t pp_ctrl_reg, pp_div_reg;
+   u32 pp_div;
+
+   pp_ctrl_reg = PP_CONTROL(pipe);
+   pp_div_reg  = PP_DIVISOR(pipe);
+   pp_div = I915_READ(pp_div_reg);
+   pp_div &= PP_REFERENCE_DIVIDER_MASK;
+
+   /* 0x1F write to PP_DIV_REG sets max cycle delay */
+   I915_WRITE(pp_div_reg, pp_div | 0x1F);
+   I915_WRITE(pp_ctrl_reg,
+  PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
+   msleep(intel_dp->panel_power_cycle_delay);
+   }
}
 
-   pps_unlock(intel_dp);
-
return 0;
 }
 
@@ -1231,16 +1238,17 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
to_i915(intel_dig_port->base.base.dev);
i915_reg_t ch_ctl, ch_data[5];
uint32_t aux_clock_divider;
+   intel_wakeref_t wakeref;
int i, ret, recv_bytes;
-   uint32_t status;
int try, clock = 0;
+   uint32_t status;
bool vdd;
 
ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
for (i = 0; i < ARRAY_SIZE(ch_data); i++)
ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
 
-   pps_lock(intel_dp);
+   wakeref = pps_lock(intel_dp);
 
/*
 * We will be called with VDD already enabled for dpcd/edid/oui reads.
@@ -1384,7 +1392,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
if (vdd)
edp_panel_vdd_off(intel_dp, false);
 
-   pps_unlock(intel_dp);
+   pps_unlock(intel_dp, wakeref);
 
return ret;
 }
@@ -2347,15 +2355,15 @@ static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
  */
 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
 {
+   intel_wak

[Intel-gfx] [PATCH 15/23] drm/i915: Track all held rpm wakerefs

[Chris Wilson]

Everytime we take a wakeref, record the stack trace of where it was
taken; clearing the set if we ever drop back to no owners. For debugging
a rpm leak, we can look at all the current wakerefs and check if they
have a matching rpm_put.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/Kconfig.debug|   2 +-
 drivers/gpu/drm/i915/i915_debugfs.c   |   6 +
 drivers/gpu/drm/i915/i915_drv.c   |   8 +-
 drivers/gpu/drm/i915/i915_drv.h   |   7 +
 drivers/gpu/drm/i915/intel_drv.h  |  44 ++-
 drivers/gpu/drm/i915/intel_runtime_pm.c   | 267 --
 .../gpu/drm/i915/selftests/mock_gem_device.c  |   8 +-
 7 files changed, 292 insertions(+), 50 deletions(-)

diff --git a/drivers/gpu/drm/i915/Kconfig.debug 
b/drivers/gpu/drm/i915/Kconfig.debug
index 9e36ffb5eb7c..a97929c47466 100644
--- a/drivers/gpu/drm/i915/Kconfig.debug
+++ b/drivers/gpu/drm/i915/Kconfig.debug
@@ -21,11 +21,11 @@ config DRM_I915_DEBUG
 select DEBUG_FS
 select PREEMPT_COUNT
 select I2C_CHARDEV
+select STACKDEPOT
 select DRM_DP_AUX_CHARDEV
 select X86_MSR # used by igt/pm_rpm
 select DRM_VGEM # used by igt/prime_vgem (dmabuf interop checks)
 select DRM_DEBUG_MM if DRM=y
-select STACKDEPOT if DRM=y # for DRM_DEBUG_MM
select DRM_DEBUG_SELFTEST
select SW_SYNC # signaling validation framework (igt/syncobj*)
select DRM_I915_SW_FENCE_DEBUG_OBJECTS
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 39f319c49def..6d2e1cc61906 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2699,6 +2699,12 @@ static int i915_runtime_pm_status(struct seq_file *m, 
void *unused)
   pci_power_name(pdev->current_state),
   pdev->current_state);
 
+   if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)) {
+   struct drm_printer p = drm_seq_file_printer(m);
+
+   print_intel_runtime_pm_wakeref(dev_priv, &p);
+   }
+
return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 12f4f929..9c5efffebc95 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -895,6 +895,7 @@ static int i915_driver_init_early(struct drm_i915_private 
*dev_priv)
mutex_init(&dev_priv->pps_mutex);
 
i915_memcpy_init_early(dev_priv);
+   intel_runtime_pm_init_early(dev_priv);
 
ret = i915_workqueues_init(dev_priv);
if (ret < 0)
@@ -1480,8 +1481,7 @@ void i915_driver_unload(struct drm_device *dev)
i915_driver_cleanup_mmio(dev_priv);
 
enable_rpm_wakeref_asserts(dev_priv);
-
-   WARN_ON(atomic_read(&dev_priv->runtime_pm.wakeref_count));
+   intel_runtime_pm_cleanup(dev_priv);
 }
 
 static void i915_driver_release(struct drm_device *dev)
@@ -1687,6 +1687,8 @@ static int i915_drm_suspend_late(struct drm_device *dev, 
bool hibernation)
 
 out:
enable_rpm_wakeref_asserts(dev_priv);
+   if (!dev_priv->uncore.user_forcewake.count)
+   intel_runtime_pm_cleanup(dev_priv);
 
return ret;
 }
@@ -2641,7 +2643,7 @@ static int intel_runtime_suspend(struct device *kdev)
}
 
enable_rpm_wakeref_asserts(dev_priv);
-   WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
+   intel_runtime_pm_cleanup(dev_priv);
 
if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
DRM_ERROR("Unclaimed access detected prior to suspending\n");
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index db006ff73827..7b1fcaa8c1fd 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -45,6 +45,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 #include 
@@ -1287,6 +1288,12 @@ struct i915_runtime_pm {
atomic_t wakeref_count;
bool suspended;
bool irqs_enabled;
+
+#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
+   spinlock_t debug_lock;
+   depot_stack_handle_t *debug_owners;
+   unsigned long debug_count;
+#endif
 };
 
 enum intel_pipe_crc_source {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f5731215210a..6d64f78f821d 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -41,6 +41,8 @@
 #include 
 #include 
 
+struct drm_printer;
+
 /**
  * __wait_for - magic wait macro
  *
@@ -1958,6 +1960,7 @@ int intel_psr_wait_for_idle(const struct intel_crtc_state 
*new_crtc_state,
u32 *out_value);
 
 /* intel_runtime_pm.c */
+void intel_runtime_pm_init_early(struct drm_i915_private *dev_priv);
 int intel_power_domains_init(struct drm_i915_private *);
 void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool 
resume);
@@ -1

[Intel-gfx] [PATCH 10/23] drm/i915/execlists: Assert the queue is non-empty on unsubmitting

[Chris Wilson]

In the sequence

<0>[  531.960431] drv_self-48067 527402570us : intel_gpu_reset: 
engine_mask=1, ret=0, retry=0
<0>[  531.960431] drv_self-48067 527402571us : execlists_reset: rcs0 
request global=115de, current=71133
<0>[  531.960431] drv_self-48067d..1 527402571us : 
execlists_cancel_port_requests: rcs0:port0 global=71134 (fence 826b:198), 
(current 71133)
<0>[  531.960431] drv_self-48067d..1 527402572us : 
execlists_cancel_port_requests: rcs0:port1 global=71135 (fence 826c:53), 
(current 71133)
<0>[  531.960431] drv_self-48067d..1 527402572us : __i915_request_unsubmit: 
rcs0 fence 826c:53 <- global=71135, current 71133
<0>[  531.960431] drv_self-48067d..1 527402579us : __i915_request_unsubmit: 
rcs0 fence 826b:198 <- global=71134, current 71133
<0>[  531.960431] drv_self-48067 527402613us : 
intel_engine_cancel_stop_cs: rcs0
<0>[  531.960431] drv_self-48067 527402624us : execlists_reset_finish: 
rcs0

we are missing the execlists_submission_tasklet() invocation before the
execlists_reset_fini() implying that either the queue is empty, or we
failed to schedule and run the tasklet on finish. Add an assert so we
are sure that on unsubmitting the incomplete request after reset, the
queue is indeed populated.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/intel_lrc.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 939e0fa7523f..fddd6a71f391 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -344,6 +344,7 @@ static void __unwind_incomplete_requests(struct 
intel_engine_cs *engine)
last_prio = rq_prio(rq);
p = lookup_priolist(engine, last_prio);
}
+   GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root));
 
GEM_BUG_ON(p->priority != rq_prio(rq));
list_add(&rq->sched.link, &p->requests);
-- 
2.19.0.rc1

___
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[Intel-gfx] [PATCH 19/23] drm/i915: Track the wakeref used to initialise display power domains

[Chris Wilson]

On module load and unload, we grab the POWER_DOMAIN_INIT powerwells and
transfer them to the runtime-pm code. We can use our wakeref tracking to
verify that the wakeref is indeed passed from init to enable, and
disable to fini; and across suspend.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_debugfs.c |   3 +
 drivers/gpu/drm/i915/i915_drv.h |   2 +
 drivers/gpu/drm/i915/intel_runtime_pm.c | 146 +---
 3 files changed, 85 insertions(+), 66 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index b1fdaa8875cb..a6d2e3496a09 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2695,6 +2695,9 @@ static int i915_runtime_pm_status(struct seq_file *m, 
void *unused)
if (!HAS_RUNTIME_PM(dev_priv))
seq_puts(m, "Runtime power management not supported\n");
 
+   seq_printf(m, "Runtime power management: %s\n",
+  enableddisabled(!dev_priv->power_domains.wakeref));
+
seq_printf(m, "GPU idle: %s (epoch %u)\n",
   yesno(!dev_priv->gt.awake), dev_priv->gt.epoch);
seq_printf(m, "IRQs disabled: %s\n",
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c497c781f936..34cd9e189cfb 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -943,6 +943,8 @@ struct i915_power_domains {
bool display_core_suspended;
int power_well_count;
 
+   intel_wakeref_t wakeref;
+
struct mutex lock;
int domain_use_count[POWER_DOMAIN_NUM];
struct i915_power_well *power_wells;
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index f0debe757840..20f546dc2490 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -3974,7 +3974,7 @@ static void intel_power_domains_verify_state(struct 
drm_i915_private *dev_priv);
 
 /**
  * intel_power_domains_init_hw - initialize hardware power domain state
- * @dev_priv: i915 device instance
+ * @i915: i915 device instance
  * @resume: Called from resume code paths or not
  *
  * This function initializes the hardware power domain state and enables all
@@ -3988,27 +3988,27 @@ static void intel_power_domains_verify_state(struct 
drm_i915_private *dev_priv);
  * intel_power_domains_enable()) and must be paired with
  * intel_power_domains_fini_hw().
  */
-void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool 
resume)
+void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume)
 {
-   struct i915_power_domains *power_domains = &dev_priv->power_domains;
+   struct i915_power_domains *power_domains = &i915->power_domains;
 
power_domains->initializing = true;
 
-   if (IS_ICELAKE(dev_priv)) {
-   icl_display_core_init(dev_priv, resume);
-   } else if (IS_CANNONLAKE(dev_priv)) {
-   cnl_display_core_init(dev_priv, resume);
-   } else if (IS_GEN9_BC(dev_priv)) {
-   skl_display_core_init(dev_priv, resume);
-   } else if (IS_GEN9_LP(dev_priv)) {
-   bxt_display_core_init(dev_priv, resume);
-   } else if (IS_CHERRYVIEW(dev_priv)) {
+   if (IS_ICELAKE(i915)) {
+   icl_display_core_init(i915, resume);
+   } else if (IS_CANNONLAKE(i915)) {
+   cnl_display_core_init(i915, resume);
+   } else if (IS_GEN9_BC(i915)) {
+   skl_display_core_init(i915, resume);
+   } else if (IS_GEN9_LP(i915)) {
+   bxt_display_core_init(i915, resume);
+   } else if (IS_CHERRYVIEW(i915)) {
mutex_lock(&power_domains->lock);
-   chv_phy_control_init(dev_priv);
+   chv_phy_control_init(i915);
mutex_unlock(&power_domains->lock);
-   } else if (IS_VALLEYVIEW(dev_priv)) {
+   } else if (IS_VALLEYVIEW(i915)) {
mutex_lock(&power_domains->lock);
-   vlv_cmnlane_wa(dev_priv);
+   vlv_cmnlane_wa(i915);
mutex_unlock(&power_domains->lock);
}
 
@@ -4018,18 +4018,20 @@ void intel_power_domains_init_hw(struct 
drm_i915_private *dev_priv, bool resume)
 * resources powered until display HW readout is complete. We drop
 * this reference in intel_power_domains_enable().
 */
-   intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
+   power_domains->wakeref =
+   intel_display_power_get(i915, POWER_DOMAIN_INIT);
+
/* Disable power support if the user asked so. */
if (!i915_modparams.disable_power_well)
-   intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
-   intel_power_domains_sync_hw(dev_priv);
+   intel_display_power_get(i915, POWER_DOMAIN_INIT);
+   intel_power_domains_sync_hw(i915);
 
power_domains->initializing = false;
 }
 
 /**
  * intel_p

[Intel-gfx] [PATCH 09/23] drm/i915: Remove debugfs/i915_ppgtt_info

[Chris Wilson]

The information presented here is not relevant to current development.
We can either use the context information, but more often we want to
inspect the active gpu state.

The ulterior motive is to eradicate dev->filelist.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_debugfs.c | 119 
 1 file changed, 119 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 03637da325ab..245d714b2bba 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2037,124 +2037,6 @@ static int i915_swizzle_info(struct seq_file *m, void 
*data)
return 0;
 }
 
-static int per_file_ctx(int id, void *ptr, void *data)
-{
-   struct i915_gem_context *ctx = ptr;
-   struct seq_file *m = data;
-   struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
-
-   if (!ppgtt) {
-   seq_printf(m, "  no ppgtt for context %d\n",
-  ctx->user_handle);
-   return 0;
-   }
-
-   if (i915_gem_context_is_default(ctx))
-   seq_puts(m, "  default context:\n");
-   else
-   seq_printf(m, "  context %d:\n", ctx->user_handle);
-   ppgtt->debug_dump(ppgtt, m);
-
-   return 0;
-}
-
-static void gen8_ppgtt_info(struct seq_file *m,
-   struct drm_i915_private *dev_priv)
-{
-   struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
-   struct intel_engine_cs *engine;
-   enum intel_engine_id id;
-   int i;
-
-   if (!ppgtt)
-   return;
-
-   for_each_engine(engine, dev_priv, id) {
-   seq_printf(m, "%s\n", engine->name);
-   for (i = 0; i < 4; i++) {
-   u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
-   pdp <<= 32;
-   pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
-   seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
-   }
-   }
-}
-
-static void gen6_ppgtt_info(struct seq_file *m,
-   struct drm_i915_private *dev_priv)
-{
-   struct intel_engine_cs *engine;
-   enum intel_engine_id id;
-
-   if (IS_GEN6(dev_priv))
-   seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
-
-   for_each_engine(engine, dev_priv, id) {
-   seq_printf(m, "%s\n", engine->name);
-   if (IS_GEN7(dev_priv))
-   seq_printf(m, "GFX_MODE: 0x%08x\n",
-  I915_READ(RING_MODE_GEN7(engine)));
-   seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
-  I915_READ(RING_PP_DIR_BASE(engine)));
-   seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
-  I915_READ(RING_PP_DIR_BASE_READ(engine)));
-   seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
-  I915_READ(RING_PP_DIR_DCLV(engine)));
-   }
-   if (dev_priv->mm.aliasing_ppgtt) {
-   struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
-
-   seq_puts(m, "aliasing PPGTT:\n");
-   seq_printf(m, "pd gtt offset: 0x%08x\n", 
ppgtt->pd.base.ggtt_offset);
-
-   ppgtt->debug_dump(ppgtt, m);
-   }
-
-   seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
-}
-
-static int i915_ppgtt_info(struct seq_file *m, void *data)
-{
-   struct drm_i915_private *dev_priv = node_to_i915(m->private);
-   struct drm_device *dev = &dev_priv->drm;
-   struct drm_file *file;
-   int ret;
-
-   mutex_lock(&dev->filelist_mutex);
-   ret = mutex_lock_interruptible(&dev->struct_mutex);
-   if (ret)
-   goto out_unlock;
-
-   intel_runtime_pm_get(dev_priv);
-
-   if (INTEL_GEN(dev_priv) >= 8)
-   gen8_ppgtt_info(m, dev_priv);
-   else if (INTEL_GEN(dev_priv) >= 6)
-   gen6_ppgtt_info(m, dev_priv);
-
-   list_for_each_entry_reverse(file, &dev->filelist, lhead) {
-   struct drm_i915_file_private *file_priv = file->driver_priv;
-   struct task_struct *task;
-
-   task = get_pid_task(file->pid, PIDTYPE_PID);
-   if (!task) {
-   ret = -ESRCH;
-   goto out_rpm;
-   }
-   seq_printf(m, "\nproc: %s\n", task->comm);
-   put_task_struct(task);
-   idr_for_each(&file_priv->context_idr, per_file_ctx,
-(void *)(unsigned long)m);
-   }
-
-out_rpm:
-   intel_runtime_pm_put(dev_priv);
-   mutex_unlock(&dev->struct_mutex);
-out_unlock:
-   mutex_unlock(&dev->filelist_mutex);
-   return ret;
-}
-
 static int count_irq_waiters(struct drm_i915_private *i915)
 {
struct intel_engine_cs *engine;
@@ -4743,7 +4625,6 @@ static const struct drm_info_list i915_debugfs_list[] = {
{"i915_context_status", i915_context_status, 0},
{"

[Intel-gfx] [PATCH 23/23] drm/i915: Serialise concurrent calls to i915_gem_set_wedged()

[Chris Wilson]

Make i915_gem_set_wedged() and i915_gem_unset_wedged() behaviour more
consistently if called concurrently.

Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/i915_gem.c   | 32 ++-
 drivers/gpu/drm/i915/i915_gpu_error.h |  4 ++-
 .../gpu/drm/i915/selftests/mock_gem_device.c  |  1 +
 3 files changed, 28 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 05a4cd15a81e..e1e8fae123e8 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3323,10 +3323,15 @@ static void nop_complete_submit_request(struct 
i915_request *request)
 
 void i915_gem_set_wedged(struct drm_i915_private *i915)
 {
+   struct i915_gpu_error *error = &i915->gpu_error;
struct intel_engine_cs *engine;
enum intel_engine_id id;
 
-   GEM_TRACE("start\n");
+   mutex_lock(&error->wedge_mutex);
+   if (test_bit(I915_WEDGED, &error->flags)) {
+   mutex_unlock(&error->wedge_mutex);
+   return;
+   }
 
if (GEM_SHOW_DEBUG()) {
struct drm_printer p = drm_debug_printer(__func__);
@@ -3335,8 +3340,7 @@ void i915_gem_set_wedged(struct drm_i915_private *i915)
intel_engine_dump(engine, &p, "%s\n", engine->name);
}
 
-   if (test_and_set_bit(I915_WEDGED, &i915->gpu_error.flags))
-   goto out;
+   GEM_TRACE("start\n");
 
/*
 * First, stop submission to hw, but do not yet complete requests by
@@ -3396,20 +3400,28 @@ void i915_gem_set_wedged(struct drm_i915_private *i915)
i915_gem_reset_finish_engine(engine);
}
 
-out:
+   smp_mb__before_atomic();
+   set_bit(I915_WEDGED, &error->flags);
+
GEM_TRACE("end\n");
+   mutex_unlock(&error->wedge_mutex);
 
-   wake_up_all(&i915->gpu_error.reset_queue);
+   wake_up_all(&error->reset_queue);
 }
 
 bool i915_gem_unset_wedged(struct drm_i915_private *i915)
 {
+   struct i915_gpu_error *error = &i915->gpu_error;
struct i915_timeline *tl;
+   bool ret = false;
 
lockdep_assert_held(&i915->drm.struct_mutex);
-   if (!test_bit(I915_WEDGED, &i915->gpu_error.flags))
+
+   if (!test_bit(I915_WEDGED, &error->flags))
return true;
 
+   mutex_lock(&error->wedge_mutex);
+
GEM_TRACE("start\n");
 
/*
@@ -3443,7 +3455,7 @@ bool i915_gem_unset_wedged(struct drm_i915_private *i915)
 */
if (dma_fence_default_wait(&rq->fence, true,
   MAX_SCHEDULE_TIMEOUT) < 0)
-   return false;
+   goto unlock;
}
i915_retire_requests(i915);
GEM_BUG_ON(i915->gt.active_requests);
@@ -3464,8 +3476,11 @@ bool i915_gem_unset_wedged(struct drm_i915_private *i915)
 
smp_mb__before_atomic(); /* complete takeover before enabling execbuf */
clear_bit(I915_WEDGED, &i915->gpu_error.flags);
+   ret = true;
+unlock:
+   mutex_unlock(&i915->gpu_error.wedge_mutex);
 
-   return true;
+   return ret;
 }
 
 static void
@@ -5792,6 +5807,7 @@ int i915_gem_init_early(struct drm_i915_private *dev_priv)
  i915_gem_idle_work_handler);
init_waitqueue_head(&dev_priv->gpu_error.wait_queue);
init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
+   mutex_init(&dev_priv->gpu_error.wedge_mutex);
 
atomic_set(&dev_priv->mm.bsd_engine_dispatch_index, 0);
 
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.h 
b/drivers/gpu/drm/i915/i915_gpu_error.h
index 1c1bc0c23468..4f5c5be56002 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.h
+++ b/drivers/gpu/drm/i915/i915_gpu_error.h
@@ -269,8 +269,8 @@ struct i915_gpu_error {
 #define I915_RESET_BACKOFF 0
 #define I915_RESET_HANDOFF 1
 #define I915_RESET_MODESET 2
+#define I915_RESET_ENGINE  3
 #define I915_WEDGED(BITS_PER_LONG - 1)
-#define I915_RESET_ENGINE  (I915_WEDGED - I915_NUM_ENGINES)
 
/** Number of times an engine has been reset */
u32 reset_engine_count[I915_NUM_ENGINES];
@@ -281,6 +281,8 @@ struct i915_gpu_error {
/** Reason for the current *global* reset */
const char *reason;
 
+   struct mutex wedge_mutex; /* serialises wedging/unwedging */
+
/**
 * Waitqueue to signal when a hang is detected. Used to for waiters
 * to release the struct_mutex for the reset to procede.
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c 
b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 0eb283e7fc96..a4cd459c320d 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -188,6 +188,7 @@ struct drm_i915_private *mock_gem_device(void)
 
init_waitqueue_head(&i915->gpu_error.wait_queue);
init_waitqueue_head(&i915->gpu_error.reset_qu

[Intel-gfx] [PATCH 05/23] drm/i915/execlists: Delay updating ring register state after resume

[Chris Wilson]

Now that we reload both RING_HEAD and RING_TAIL when rebinding the
context, we do not need to scrub those registers immediately on resume.

v2: Handle the perma-pinned contexts.

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/intel_lrc.c | 29 +++--
 1 file changed, 11 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index f2630911337f..38b90ee4034a 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2860,13 +2860,14 @@ static int execlists_context_deferred_alloc(struct 
i915_gem_context *ctx,
return ret;
 }
 
-void intel_lr_context_resume(struct drm_i915_private *dev_priv)
+void intel_lr_context_resume(struct drm_i915_private *i915)
 {
struct intel_engine_cs *engine;
struct i915_gem_context *ctx;
enum intel_engine_id id;
 
-   /* Because we emit WA_TAIL_DWORDS there may be a disparity
+   /*
+* Because we emit WA_TAIL_DWORDS there may be a disparity
 * between our bookkeeping in ce->ring->head and ce->ring->tail and
 * that stored in context. As we only write new commands from
 * ce->ring->tail onwards, everything before that is junk. If the GPU
@@ -2876,28 +2877,20 @@ void intel_lr_context_resume(struct drm_i915_private 
*dev_priv)
 * So to avoid that we reset the context images upon resume. For
 * simplicity, we just zero everything out.
 */
-   list_for_each_entry(ctx, &dev_priv->contexts.list, link) {
-   for_each_engine(engine, dev_priv, id) {
+   list_for_each_entry(ctx, &i915->contexts.list, link) {
+   for_each_engine(engine, i915, id) {
struct intel_context *ce =
to_intel_context(ctx, engine);
-   u32 *reg;
-
-   if (!ce->state)
-   continue;
 
-   reg = i915_gem_object_pin_map(ce->state->obj,
- I915_MAP_WB);
-   if (WARN_ON(IS_ERR(reg)))
+   if (!ce->ring)
continue;
 
-   reg += LRC_STATE_PN * PAGE_SIZE / sizeof(*reg);
-   reg[CTX_RING_HEAD+1] = 0;
-   reg[CTX_RING_TAIL+1] = 0;
-
-   ce->state->obj->mm.dirty = true;
-   i915_gem_object_unpin_map(ce->state->obj);
-
intel_ring_reset(ce->ring, 0);
+
+   if (ce->pin_count) { /* otherwise done in context_pin */
+   ce->lrc_reg_state[CTX_RING_HEAD+1] = 0;
+   ce->lrc_reg_state[CTX_RING_TAIL+1] = 0;
+   }
}
}
 }
-- 
2.19.0.rc1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH 01/23] drm/i915: Reduce context HW ID lifetime

[Chris Wilson]

Future gen reduce the number of bits we will have available to
differentiate between contexts, so reduce the lifetime of the ID
assignment from that of the context to its current active cycle (i.e.
only while it is pinned for use by the HW, will it have a constant ID).
This means that instead of a max of 2k allocated contexts (worst case
before fun with bit twiddling), we instead have a limit of 2k in flight
contexts (minus a few that have been pinned by the kernel or by perf).

To reduce the number of contexts id we require, we allocate a context id
on first and mark it as pinned for as long as the GEM context itself is,
that is we keep it pinned it while active on each engine. If we exhaust
our context id space, then we try to reclaim an id from an idle context.
In the extreme case where all context ids are pinned by active contexts,
we force the system to idle in order to recover ids.

We cannot reduce the scope of an HW-ID to an engine (allowing the same
gem_context to have different ids on each engine) as in the future we
will need to preassign an id before we know which engine the
context is being executed on.

v2: Improved commentary (Tvrtko) [I tried at least]

References: https://bugs.freedesktop.org/show_bug.cgi?id=107788
Signed-off-by: Chris Wilson 
Cc: Lionel Landwerlin 
Cc: Tvrtko Ursulin 
Cc: Mika Kuoppala 
Cc: Michel Thierry 
Cc: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
---
 drivers/gpu/drm/i915/i915_debugfs.c   |   5 +-
 drivers/gpu/drm/i915/i915_drv.h   |   2 +
 drivers/gpu/drm/i915/i915_gem_context.c   | 222 +-
 drivers/gpu/drm/i915/i915_gem_context.h   |  23 ++
 drivers/gpu/drm/i915/intel_lrc.c  |   8 +
 drivers/gpu/drm/i915/selftests/mock_context.c |  11 +-
 6 files changed, 201 insertions(+), 70 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 4ad0e2ed8610..1f7051e97afb 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1953,7 +1953,10 @@ static int i915_context_status(struct seq_file *m, void 
*unused)
return ret;
 
list_for_each_entry(ctx, &dev_priv->contexts.list, link) {
-   seq_printf(m, "HW context %u ", ctx->hw_id);
+   seq_puts(m, "HW context ");
+   if (!list_empty(&ctx->hw_id_link))
+   seq_printf(m, "%x [pin %u]", ctx->hw_id,
+  atomic_read(&ctx->hw_id_pin_count));
if (ctx->pid) {
struct task_struct *task;
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5a4da5b723fd..767615ecdea5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1861,6 +1861,7 @@ struct drm_i915_private {
struct mutex av_mutex;
 
struct {
+   struct mutex mutex;
struct list_head list;
struct llist_head free_list;
struct work_struct free_work;
@@ -1873,6 +1874,7 @@ struct drm_i915_private {
 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
 #define MAX_GUC_CONTEXT_HW_ID (1 << 20) /* exclusive */
 #define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */
+   struct list_head hw_id_list;
} contexts;
 
u32 fdi_rx_config;
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index f15a039772db..747b8170a15a 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -115,6 +115,95 @@ static void lut_close(struct i915_gem_context *ctx)
rcu_read_unlock();
 }
 
+static inline int new_hw_id(struct drm_i915_private *i915, gfp_t gfp)
+{
+   unsigned int max;
+
+   lockdep_assert_held(&i915->contexts.mutex);
+
+   if (INTEL_GEN(i915) >= 11)
+   max = GEN11_MAX_CONTEXT_HW_ID;
+   else if (USES_GUC_SUBMISSION(i915))
+   /*
+* When using GuC in proxy submission, GuC consumes the
+* highest bit in the context id to indicate proxy submission.
+*/
+   max = MAX_GUC_CONTEXT_HW_ID;
+   else
+   max = MAX_CONTEXT_HW_ID;
+
+   return ida_simple_get(&i915->contexts.hw_ida, 0, max, gfp);
+}
+
+static int steal_hw_id(struct drm_i915_private *i915)
+{
+   struct i915_gem_context *ctx, *cn;
+   LIST_HEAD(pinned);
+   int id = -ENOSPC;
+
+   lockdep_assert_held(&i915->contexts.mutex);
+
+   list_for_each_entry_safe(ctx, cn,
+&i915->contexts.hw_id_list, hw_id_link) {
+   if (atomic_read(&ctx->hw_id_pin_count)) {
+   list_move_tail(&ctx->hw_id_link, &pinned);
+   continue;
+   }
+
+   GEM_BUG_ON(!ctx->hw_id); /* perma-pinned kernel context */
+   list_del_init(&ctx->hw_id_link);
+   id = ctx->hw

[Intel-gfx] [PATCH 13/23] drm/i915: Cache the error string

[Chris Wilson]

Currently, we convert the error state into a string every time we read
from sysfs (and sysfs reads in page size (4KiB) chunks). We do try to
window the string and only capture the portion that is being read, but
that means that we must always convert up to the window to find the
start. For a very large error state bordering on EXEC_OBJECT_CAPTURE
abuse, this is noticeable as it degrades to O(N^2)!

As we do not have a convenient hook for sysfs open(), and we would like
to keep the lazy conversion into a string, do the conversion of the
whole string on the first read and keep the string until the error state
is freed.

v2: Don't double advance simple_read_from_buffer
v3: Due to extreme pain of lack of vrealloc, use a scatterlist
v4: Keep the forward iterator loosely cached

Reported-by: Jason Ekstrand 
Testcase: igt/gem_exec_capture/many*
Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Jason Ekstrand 
---
 drivers/gpu/drm/i915/i915_debugfs.c   |  32 +-
 drivers/gpu/drm/i915/i915_gpu_error.c | 402 +++---
 drivers/gpu/drm/i915/i915_gpu_error.h |  28 +-
 drivers/gpu/drm/i915/i915_sysfs.c |  27 +-
 4 files changed, 273 insertions(+), 216 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 245d714b2bba..39f319c49def 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -914,30 +914,28 @@ static int i915_gem_fence_regs_info(struct seq_file *m, 
void *data)
 static ssize_t gpu_state_read(struct file *file, char __user *ubuf,
  size_t count, loff_t *pos)
 {
-   struct i915_gpu_state *error = file->private_data;
-   struct drm_i915_error_state_buf str;
+   struct i915_gpu_state *error;
ssize_t ret;
-   loff_t tmp;
+   void *buf;
 
+   error = file->private_data;
if (!error)
return 0;
 
-   ret = i915_error_state_buf_init(&str, error->i915, count, *pos);
-   if (ret)
-   return ret;
-
-   ret = i915_error_state_to_str(&str, error);
-   if (ret)
-   goto out;
+   /* Bounce buffer required because of kernfs __user API convenience. */
+   buf = kmalloc(count, GFP_KERNEL);
+   if (!buf)
+   return -ENOMEM;
 
-   tmp = 0;
-   ret = simple_read_from_buffer(ubuf, count, &tmp, str.buf, str.bytes);
-   if (ret < 0)
-   goto out;
+   ret = i915_gpu_state_copy_to_buffer(error, buf, *pos, count);
+   if (ret > 0) {
+   if (!copy_to_user(ubuf, buf, ret))
+   *pos += ret;
+   else
+   ret = -EFAULT;
+   }
 
-   *pos = str.start + ret;
-out:
-   i915_error_state_buf_release(&str);
+   kfree(buf);
return ret;
 }
 
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 3bd4f957abb9..36476725b13c 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -28,6 +28,8 @@
  */
 
 #include 
+#include 
+#include 
 #include 
 #include 
 #include 
@@ -77,112 +79,110 @@ static const char *purgeable_flag(int purgeable)
return purgeable ? " purgeable" : "";
 }
 
-static bool __i915_error_ok(struct drm_i915_error_state_buf *e)
+static void __sg_set_buf(struct scatterlist *sg,
+void *addr, unsigned int len, loff_t it)
 {
-
-   if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) {
-   e->err = -ENOSPC;
-   return false;
-   }
-
-   if (e->bytes == e->size - 1 || e->err)
-   return false;
-
-   return true;
+   sg->page_link = (unsigned long)virt_to_page(addr);
+   sg->offset = offset_in_page(addr);
+   sg->length = len;
+   sg->dma_address = it;
 }
 
-static bool __i915_error_seek(struct drm_i915_error_state_buf *e,
- unsigned len)
+static bool __i915_error_grow(struct drm_i915_error_state_buf *e, size_t len)
 {
-   if (e->pos + len <= e->start) {
-   e->pos += len;
+   if (!len)
return false;
-   }
 
-   /* First vsnprintf needs to fit in its entirety for memmove */
-   if (len >= e->size) {
-   e->err = -EIO;
-   return false;
-   }
+   if (e->bytes + len + 1 > e->size) {
+   if (e->bytes) {
+   __sg_set_buf(e->cur++, e->buf, e->bytes, e->iter);
+   e->iter += e->bytes;
+   e->buf = NULL;
+   e->bytes = 0;
+   }
 
-   return true;
-}
+   if (e->cur == e->end) {
+   struct scatterlist *sgl;
 
-static void __i915_error_advance(struct drm_i915_error_state_buf *e,
-unsigned len)
-{
-   /* If this is first printf in this window, adjust it so that
-* start position matches start of the buffer
- 

[Intel-gfx] [PATCH 22/23] drm/i915: Mark up Ironlake ips with rpm wakerefs

[Chris Wilson]

Currently Ironlake operates under the assumption that rpm awake (and its
error checking is disabled). As such, we have missed a few places where we
access registers without taking the rpm wakeref and thus trigger
warnings. intel_ips being one culprit.

As this involved adding a potentially sleeping rpm_get, we have to
rearrange the spinlocks slightly and so switch to acquiring a device-ref
under the spinlock rather than hold the spinlock for the whole
operation. To be consistent, we make the change in pattern common to the
intel_ips interface even though this adds a few more atomic operations
than necessary in a few cases.

v2: Sagar noted the mb around setting mch_dev were overkill as we only
need ordering there, and that i915_emon_status was still using
struct_mutex for no reason, but lacked rpm.

Signed-off-by: Chris Wilson 
Cc: Sagar Arun Kamble 
---
 drivers/gpu/drm/i915/i915_debugfs.c |  29 +++--
 drivers/gpu/drm/i915/i915_drv.c |   3 +
 drivers/gpu/drm/i915/intel_pm.c | 172 ++--
 3 files changed, 103 insertions(+), 101 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index a6d2e3496a09..2e25205e984a 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1758,27 +1758,24 @@ static int i915_sr_status(struct seq_file *m, void 
*unused)
 
 static int i915_emon_status(struct seq_file *m, void *unused)
 {
-   struct drm_i915_private *dev_priv = node_to_i915(m->private);
-   struct drm_device *dev = &dev_priv->drm;
-   unsigned long temp, chipset, gfx;
-   int ret;
+   struct drm_i915_private *i915 = node_to_i915(m->private);
+   intel_wakeref_t wakeref;
 
-   if (!IS_GEN5(dev_priv))
+   if (!IS_GEN5(i915))
return -ENODEV;
 
-   ret = mutex_lock_interruptible(&dev->struct_mutex);
-   if (ret)
-   return ret;
+   with_intel_runtime_pm(i915, wakeref) {
+   unsigned long temp, chipset, gfx;
 
-   temp = i915_mch_val(dev_priv);
-   chipset = i915_chipset_val(dev_priv);
-   gfx = i915_gfx_val(dev_priv);
-   mutex_unlock(&dev->struct_mutex);
+   temp = i915_mch_val(i915);
+   chipset = i915_chipset_val(i915);
+   gfx = i915_gfx_val(i915);
 
-   seq_printf(m, "GMCH temp: %ld\n", temp);
-   seq_printf(m, "Chipset power: %ld\n", chipset);
-   seq_printf(m, "GFX power: %ld\n", gfx);
-   seq_printf(m, "Total power: %ld\n", chipset + gfx);
+   seq_printf(m, "GMCH temp: %ld\n", temp);
+   seq_printf(m, "Chipset power: %ld\n", chipset);
+   seq_printf(m, "GFX power: %ld\n", gfx);
+   seq_printf(m, "Total power: %ld\n", chipset + gfx);
+   }
 
return 0;
 }
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9c5efffebc95..ace7706d1d5e 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1452,6 +1452,9 @@ void i915_driver_unload(struct drm_device *dev)
 
i915_driver_unregister(dev_priv);
 
+   /* Flush any external code that still may be under the RCU lock */
+   synchronize_rcu();
+
if (i915_gem_suspend(dev_priv))
DRM_ERROR("failed to idle hardware; continuing to unload!\n");
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 409825ab890c..d10ded624025 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6141,10 +6141,6 @@ void intel_init_ipc(struct drm_i915_private *dev_priv)
  */
 DEFINE_SPINLOCK(mchdev_lock);
 
-/* Global for IPS driver to get at the current i915 device. Protected by
- * mchdev_lock. */
-static struct drm_i915_private *i915_mch_dev;
-
 bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
 {
u16 rgvswctl;
@@ -7787,16 +7783,17 @@ static unsigned long __i915_chipset_val(struct 
drm_i915_private *dev_priv)
 
 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
 {
-   unsigned long val;
+   intel_wakeref_t wakeref;
+   unsigned long val = 0;
 
if (!IS_GEN5(dev_priv))
return 0;
 
-   spin_lock_irq(&mchdev_lock);
-
-   val = __i915_chipset_val(dev_priv);
-
-   spin_unlock_irq(&mchdev_lock);
+   with_intel_runtime_pm(dev_priv, wakeref) {
+   spin_lock_irq(&mchdev_lock);
+   val = __i915_chipset_val(dev_priv);
+   spin_unlock_irq(&mchdev_lock);
+   }
 
return val;
 }
@@ -7873,14 +7870,16 @@ static void __i915_update_gfx_val(struct 
drm_i915_private *dev_priv)
 
 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
 {
+   intel_wakeref_t wakeref;
+
if (!IS_GEN5(dev_priv))
return;
 
-   spin_lock_irq(&mchdev_lock);
-
-   __i915_update_gfx_val(dev_priv);
-
-   spin_unlock_irq(&mchdev_lock);
+   with_intel_runtime_pm(dev_priv, w

Re: [Intel-gfx] [PATCH] drm: Reject unknown legacy bpp and dpeth for drm_mode_addfb ioctl

[Daniel Vetter]

On Tue, Sep 04, 2018 at 09:53:19PM +0100, Chris Wilson wrote:
> Since this is handling user provided bpp and depth, we need to sanity
> check and propagate the EINVAL back rather than assume what the insane
> client intended and fill the logs with DRM_ERROR.
> 
> Signed-off-by: Chris Wilson 
> Cc: Daniel Vetter 
> Cc: Ville Syrjälä 
> ---
> So I am presuming that r.pixel_format == 0 is rejected elsewhere for the
> internal users (as if any would deliberately provoke the error)!

Could maybe add a DRM_FORMAT_INVALID at the end of drm_fourcc.h, and then
switch over the various format/modifier tables to being zero terminated.
Well DRM_FORMAT_MOD_INVALID can't be 0 because that means linear. Anyway,
I digress, this loks good.

And yes drm_internal_framebuffer_create makes sure you have a real fourcc
code, not a figment of your imagination (or more profane, stack garbage).

Reviewed-by: Daniel Vetter 

Same as with the previous one, igt would be sweet on top.
-Daniel

> ---
>  drivers/gpu/drm/drm_fourcc.c  | 4 ++--
>  drivers/gpu/drm/drm_framebuffer.c | 5 -
>  2 files changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
> index 35c1e2742c27..34595c5b55c9 100644
> --- a/drivers/gpu/drm/drm_fourcc.c
> +++ b/drivers/gpu/drm/drm_fourcc.c
> @@ -69,8 +69,8 @@ uint32_t drm_mode_legacy_fb_format(uint32_t bpp, uint32_t 
> depth)
>   fmt = DRM_FORMAT_ARGB;
>   break;
>   default:
> - DRM_ERROR("bad bpp, assuming x8r8g8b8 pixel format\n");
> - fmt = DRM_FORMAT_XRGB;
> + DRM_DEBUG("bad bpp [%d] and depth [%d]\n", bpp, depth);
> + fmt = 0;
>   break;
>   }
>  
> diff --git a/drivers/gpu/drm/drm_framebuffer.c 
> b/drivers/gpu/drm/drm_framebuffer.c
> index 781af1d42d76..7641bddfe367 100644
> --- a/drivers/gpu/drm/drm_framebuffer.c
> +++ b/drivers/gpu/drm/drm_framebuffer.c
> @@ -112,12 +112,15 @@ int drm_mode_addfb(struct drm_device *dev, struct 
> drm_mode_fb_cmd *or,
>   struct drm_mode_fb_cmd2 r = {};
>   int ret;
>  
> + r.pixel_format = drm_mode_legacy_fb_format(or->bpp, or->depth);
> + if (!r.pixel_format)
> + return -EINVAL;
> +
>   /* convert to new format and call new ioctl */
>   r.fb_id = or->fb_id;
>   r.width = or->width;
>   r.height = or->height;
>   r.pitches[0] = or->pitch;
> - r.pixel_format = drm_mode_legacy_fb_format(or->bpp, or->depth);
>   r.handles[0] = or->handle;
>  
>   if (r.pixel_format == DRM_FORMAT_XRGB2101010 &&
> -- 
> 2.19.0.rc1
> 

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm: Reject unknown legacy bpp and dpeth for drm_mode_addfb ioctl

[Patchwork]

== Series Details ==

Series: drm: Reject unknown legacy bpp and dpeth for drm_mode_addfb ioctl
URL   : https://patchwork.freedesktop.org/series/49150/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4769 -> Patchwork_10085 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/49150/revisions/1/mbox/

== Known issues ==

  Here are the changes found in Patchwork_10085 that come from known issues:

  === IGT changes ===

 Issues hit 

igt@gem_exec_suspend@basic-s3:
  fi-kbl-soraka:  NOTRUN -> INCOMPLETE (fdo#107556, fdo#107774)

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
  fi-glk-dsi: PASS -> INCOMPLETE (k.org#198133, fdo#103359)
  fi-byt-clapper: PASS -> FAIL (fdo#103191, fdo#107362)


 Possible fixes 

igt@drv_module_reload@basic-reload:
  fi-blb-e6850:   INCOMPLETE (fdo#107718) -> PASS

igt@kms_flip@basic-plain-flip:
  fi-ilk-650: DMESG-WARN (fdo#106387) -> PASS +2

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
  fi-bdw-samus:   DMESG-WARN (fdo#107494) -> PASS

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
  fi-cnl-psr: DMESG-WARN (fdo#104951) -> PASS


  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
  fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951
  fdo#106387 https://bugs.freedesktop.org/show_bug.cgi?id=106387
  fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
  fdo#107494 https://bugs.freedesktop.org/show_bug.cgi?id=107494
  fdo#107556 https://bugs.freedesktop.org/show_bug.cgi?id=107556
  fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718
  fdo#107774 https://bugs.freedesktop.org/show_bug.cgi?id=107774
  k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133


== Participating hosts (48 -> 45) ==

  Additional (2): fi-kbl-soraka fi-pnv-d510 
  Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan 
fi-hsw-4200u 


== Build changes ==

* Linux: CI_DRM_4769 -> Patchwork_10085

  CI_DRM_4769: ced90ae07f3004a5fe83f26bc8f2205340b9b5a8 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4627: e0c3033a57d85c0d2eb33af0451afa16edc79f10 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10085: 98e6d2db475f03e2baa8818a7bc12d0490a6e961 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

98e6d2db475f drm: Reject unknown legacy bpp and dpeth for drm_mode_addfb ioctl

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10085/issues.html
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: optimzie eDP 1.4 config

[Patchwork]

== Series Details ==

Series: drm/i915: optimzie eDP 1.4 config
URL   : https://patchwork.freedesktop.org/series/49131/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4766_full -> Patchwork_10082_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_10082_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10082_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

== Possible new issues ==

  Here are the unknown changes that may have been introduced in 
Patchwork_10082_full:

  === IGT changes ===

 Warnings 

igt@kms_draw_crc@draw-method-rgb565-blt-xtiled:
  shard-snb:  PASS -> SKIP +3


== Known issues ==

  Here are the changes found in Patchwork_10082_full that come from known 
issues:

  === IGT changes ===

 Issues hit 

igt@kms_flip@2x-flip-vs-expired-vblank:
  shard-glk:  PASS -> FAIL (fdo#105363)

igt@perf@blocking:
  shard-hsw:  PASS -> FAIL (fdo#102252)


 Possible fixes 

igt@drv_suspend@shrink:
  shard-hsw:  INCOMPLETE (fdo#103540, fdo#106886) -> PASS

igt@gem_exec_await@wide-contexts:
  shard-glk:  FAIL (fdo#105900) -> PASS
  shard-apl:  FAIL (fdo#106680, fdo#105900) -> PASS

igt@kms_flip@flip-vs-expired-vblank:
  shard-glk:  FAIL (fdo#105363, fdo#102887) -> PASS

igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-cpu:
  shard-glk:  FAIL (fdo#103167) -> PASS +1

igt@kms_setmode@basic:
  shard-apl:  FAIL (fdo#99912) -> PASS


  fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
  fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#105900 https://bugs.freedesktop.org/show_bug.cgi?id=105900
  fdo#106680 https://bugs.freedesktop.org/show_bug.cgi?id=106680
  fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (5 -> 5) ==

  No changes in participating hosts


== Build changes ==

* Linux: CI_DRM_4766 -> Patchwork_10082

  CI_DRM_4766: 0d35b9d0b3a74c41ac1ffe1a34aa9c98d2a3a0b9 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4625: 67fbe2967889484f1248d851c068e1021f2dc332 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10082: 2602078fba7029858fdc79ab45b750805f759ac2 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ 
git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10082/shards.html
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Re: [Intel-gfx] [PATCH] drm/i915: Be defensive and don't assume PSR has any commit to sync against

[Pandiyan, Dhinakaran]

On Tue, 2018-09-04 at 19:12 +0100, Chris Wilson wrote:
> Quoting Ville Syrjälä (2018-09-04 19:06:29)
> > On Tue, Sep 04, 2018 at 08:59:32PM +0300, Ville Syrjälä wrote:
> > > On Tue, Sep 04, 2018 at 06:44:14PM +0100, Chris Wilson wrote:
> > > > Quoting Ville Syrjälä (2018-09-04 18:39:53)
> > > > > On Tue, Sep 04, 2018 at 05:29:02PM +0100, Chris Wilson wrote:
> > > > > > If the previous modeset commit has completed and is no
> > > > > > longer part of
> > > > > > the crtc state, skip waiting for it.
> > > > > > 
> > > > > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=1077
> > > > > > 92
> > > > > > Fixes: c44301fce614 ("drm/i915: Allow control of PSR at
> > > > > > runtime through debugfs, v6")
> > > > > > Signed-off-by: Chris Wilson 
> > > > > > Cc: Maarten Lankhorst 
> > > > > > Cc: Rodrigo Vivi 
> > > > > > Cc: Dhinakaran Pandiyan 
> > > > > > ---
> > > > > >  drivers/gpu/drm/i915/intel_psr.c | 16 ++--
> > > > > >  1 file changed, 10 insertions(+), 6 deletions(-)
> > > > > > 
> > > > > > diff --git a/drivers/gpu/drm/i915/intel_psr.c
> > > > > > b/drivers/gpu/drm/i915/intel_psr.c
> > > > > > index 21984d4c08ed..bddc9c7c681e 100644
> > > > > > --- a/drivers/gpu/drm/i915/intel_psr.c
> > > > > > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > > > > > @@ -834,6 +834,7 @@ int intel_psr_set_debugfs_mode(struct
> > > > > > drm_i915_private *dev_priv,
> > > > > >   struct drm_device *dev = &dev_priv->drm;
> > > > > >   struct drm_connector_state *conn_state;
> > > > > >   struct intel_crtc_state *crtc_state = NULL;
> > > > > > + struct drm_crtc_commit *commit = NULL;
> > > > > >   struct drm_crtc *crtc;
> > > > > >   struct intel_dp *dp;
> > > > > >   int ret;
> > > > > > @@ -860,12 +861,15 @@ int intel_psr_set_debugfs_mode(struct
> > > > > > drm_i915_private *dev_priv,
> > > > > >   return ret;
> > > > > >  
> > > > > >   crtc_state = to_intel_crtc_state(crtc-
> > > > > > >state);
> > > > > > - ret =
> > > > > > wait_for_completion_interruptible(&crtc_state->base.commit-
> > > > > > >hw_done);
> > > > > > - } else
> > > > > > - ret =
> > > > > > wait_for_completion_interruptible(&conn_state->commit-
> > > > > > >hw_done);
> > > > > > -
> > > > > > - if (ret)
> > > > > > - return ret;
> > > > > > + commit = crtc_state->base.commit;
> > > > > > + } else {
> > > > > > + commit = conn_state->commit;
> > > > > 
> > > > > I can't even find where we clear state->commit after its
> > > > > done.
> > > > > Do we just leave it pointing at freed memory or something?
> > > > > Also I
> > > > > can't figure out why drm_atomic_helper_commit_hw_done()
> > > > > copies
> > > > > the commit also to the old state.
> > > > 
> > > > Let me be the messenger then ;) commit is NULL at this point, I
> > > > just
> > > > presumed it was intentional.
> > > 
> > > My expectation would be that it gets cleared somewhere, but I
> > > simply
> > > can't find any such code.
> > 
> > Actually it looks like there is no such code. The event based
> > release_crtc_commit() thing gets its own reference so presumably
> > the
> > original reference stays with the state until the state itself gets
> > destroyed.
> 
> Happy with the it never had a commit theory, or is this a deeper
> problem
> that needs root causing?

Just so that I understand this correctly, even if there was a prior
commit, state->commit would have been freed when completion was
signaled. Is that right?


> -Chris
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[Intel-gfx] [PATCH] drm: Reject unknown legacy bpp and dpeth for drm_mode_addfb ioctl

[Chris Wilson]

Since this is handling user provided bpp and depth, we need to sanity
check and propagate the EINVAL back rather than assume what the insane
client intended and fill the logs with DRM_ERROR.

Signed-off-by: Chris Wilson 
Cc: Daniel Vetter 
Cc: Ville Syrjälä 
---
So I am presuming that r.pixel_format == 0 is rejected elsewhere for the
internal users (as if any would deliberately provoke the error)!
---
 drivers/gpu/drm/drm_fourcc.c  | 4 ++--
 drivers/gpu/drm/drm_framebuffer.c | 5 -
 2 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index 35c1e2742c27..34595c5b55c9 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -69,8 +69,8 @@ uint32_t drm_mode_legacy_fb_format(uint32_t bpp, uint32_t 
depth)
fmt = DRM_FORMAT_ARGB;
break;
default:
-   DRM_ERROR("bad bpp, assuming x8r8g8b8 pixel format\n");
-   fmt = DRM_FORMAT_XRGB;
+   DRM_DEBUG("bad bpp [%d] and depth [%d]\n", bpp, depth);
+   fmt = 0;
break;
}
 
diff --git a/drivers/gpu/drm/drm_framebuffer.c 
b/drivers/gpu/drm/drm_framebuffer.c
index 781af1d42d76..7641bddfe367 100644
--- a/drivers/gpu/drm/drm_framebuffer.c
+++ b/drivers/gpu/drm/drm_framebuffer.c
@@ -112,12 +112,15 @@ int drm_mode_addfb(struct drm_device *dev, struct 
drm_mode_fb_cmd *or,
struct drm_mode_fb_cmd2 r = {};
int ret;
 
+   r.pixel_format = drm_mode_legacy_fb_format(or->bpp, or->depth);
+   if (!r.pixel_format)
+   return -EINVAL;
+
/* convert to new format and call new ioctl */
r.fb_id = or->fb_id;
r.width = or->width;
r.height = or->height;
r.pitches[0] = or->pitch;
-   r.pixel_format = drm_mode_legacy_fb_format(or->bpp, or->depth);
r.handles[0] = or->handle;
 
if (r.pixel_format == DRM_FORMAT_XRGB2101010 &&
-- 
2.19.0.rc1

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Re: [Intel-gfx] [PATCH 09/14] drm: Update todo.rst

[Emil Velikov]

On 4 September 2018 at 13:19, Daniel Vetter  wrote:
> On Mon, Sep 03, 2018 at 06:38:44PM +0100, Emil Velikov wrote:
>> On 3 September 2018 at 17:54, Daniel Vetter  wrote:
>>
>> > -Hide legacy cruft better
>> > -
>> > -
>> > -Way back DRM supported only drivers which shadow-attached to PCI devices 
>> > with
>> > -userspace or fbdev drivers setting up outputs. Modern DRM drivers take 
>> > charge
>> > -of the entire device, you can spot them with the DRIVER_MODESET flag.
>> > -
>> > -Unfortunately there's still large piles of legacy code around which needs 
>> > to
>> > -be hidden so that driver writers don't accidentally end up using it. And 
>> > to
>> > -prevent security issues in those legacy IOCTLs from being exploited on 
>> > modern
>> > -drivers. This has multiple possible subtasks:
>> > -
>>
>> > -* Extract support code for legacy features into a ``drm-legacy.ko`` kernel
>> > -  module and compile it only when one of the legacy drivers is enabled.
>> > -
>> This isn't done,
>
> Yup, but I kinda figured I'll give up on this idea. The code is hidden
> well enough, I don't think a drm-legacy.ko will buy us much. Except lots
> of churn on older driver's Kconfig entries for no purpose.
>
> There's been a patch already a while back to hide the legacy drivers
> better, and Dave nacked it. So I'm not really for pushing this idea
> anymore as a good task for newbies (which todo.rst tries to collect).
>
> Want me to explain this a bit better in the commit message?

I have sort-of been chipping on that. Now the grand master approach
you've used, but still.
Up-to you if you'd want to drop, but please add a small mention in the
commit message.

Thanks
Emil
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Re: [Intel-gfx] [PATCH 06/14] drm: extract drm_atomic_uapi.c

[Rodrigo Vivi]

On Mon, Sep 03, 2018 at 06:54:31PM +0200, Daniel Vetter wrote:
> This leaves all the commit/check and state handling in drm_atomic.c,
> while pulling all the uapi glue and the huge ioctl itself into a
> seprate file.
> 
> This seems to almost perfectly split the rather big drm_atomic.c file
> into 2 equal sizes.
> 
> Also adjust the kerneldoc and type a very terse overview text.
> 
> v2: Rebase.
> 
> v3: Fix tiny typo.
> 
> Signed-off-by: Daniel Vetter 
> Cc: David Airlie 
> Cc: Gustavo Padovan 
> Cc: Maarten Lankhorst 
> Cc: Sean Paul 
> Cc: Jani Nikula 
> Cc: Joonas Lahtinen 
> Cc: Rodrigo Vivi 
> Cc: Rob Clark 
> Cc: Eric Anholt 
> Cc: intel-gfx@lists.freedesktop.org
> Cc: linux-arm-...@vger.kernel.org
> Cc: freedr...@lists.freedesktop.org
> ---
>  Documentation/gpu/drm-kms.rst|   11 +-
>  drivers/gpu/drm/Makefile |3 +-
>  drivers/gpu/drm/drm_atomic.c | 1359 +
>  drivers/gpu/drm/drm_atomic_helper.c  |1 +
>  drivers/gpu/drm/drm_atomic_uapi.c| 1393 ++
>  drivers/gpu/drm/drm_crtc_helper.c|1 +
>  drivers/gpu/drm/drm_crtc_internal.h  |5 +
>  drivers/gpu/drm/drm_framebuffer.c|1 +
>  drivers/gpu/drm/drm_gem_framebuffer_helper.c |1 +
>  drivers/gpu/drm/drm_plane_helper.c   |1 +
>  drivers/gpu/drm/i915/intel_display.c |1 +
>  drivers/gpu/drm/msm/msm_atomic.c |2 +
>  drivers/gpu/drm/vc4/vc4_crtc.c   |1 +
>  drivers/gpu/drm/vc4/vc4_plane.c  |1 +
>  include/drm/drm_atomic.h |   16 -
>  include/drm/drm_atomic_uapi.h|   58 +
>  16 files changed, 1480 insertions(+), 1375 deletions(-)
>  create mode 100644 drivers/gpu/drm/drm_atomic_uapi.c
>  create mode 100644 include/drm/drm_atomic_uapi.h
> 
> diff --git a/Documentation/gpu/drm-kms.rst b/Documentation/gpu/drm-kms.rst
> index 3a9dd68b97c9..4b1501b4835b 100644
> --- a/Documentation/gpu/drm-kms.rst
> +++ b/Documentation/gpu/drm-kms.rst
> @@ -287,6 +287,15 @@ Atomic Mode Setting Function Reference
>  .. kernel-doc:: drivers/gpu/drm/drm_atomic.c
> :export:
>  
> +Atomic Mode Setting IOCTL and UAPI Functions
> +
> +
> +.. kernel-doc:: drivers/gpu/drm/drm_atomic_uapi.c
> +   :doc: overview
> +
> +.. kernel-doc:: drivers/gpu/drm/drm_atomic_uapi.c
> +   :export:
> +
>  CRTC Abstraction
>  
>  
> @@ -563,7 +572,7 @@ Tile Group Property
>  Explicit Fencing Properties
>  ---
>  
> -.. kernel-doc:: drivers/gpu/drm/drm_atomic.c
> +.. kernel-doc:: drivers/gpu/drm/drm_atomic_uapi.c
> :doc: explicit fencing properties
>  
>  Existing KMS Properties
> diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
> index a6771cef85e2..bc6a16a3c36e 100644
> --- a/drivers/gpu/drm/Makefile
> +++ b/drivers/gpu/drm/Makefile
> @@ -18,7 +18,8 @@ drm-y   :=  drm_auth.o drm_bufs.o drm_cache.o \
>   drm_encoder.o drm_mode_object.o drm_property.o \
>   drm_plane.o drm_color_mgmt.o drm_print.o \
>   drm_dumb_buffers.o drm_mode_config.o drm_vblank.o \
> - drm_syncobj.o drm_lease.o drm_writeback.o drm_client.o
> + drm_syncobj.o drm_lease.o drm_writeback.o drm_client.o \
> + drm_atomic_uapi.o
>  
>  drm-$(CONFIG_DRM_LIB_RANDOM) += lib/drm_random.o
>  drm-$(CONFIG_DRM_VM) += drm_vm.o
> diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
> index 29a4e6959358..19634e03b78e 100644
> --- a/drivers/gpu/drm/drm_atomic.c
> +++ b/drivers/gpu/drm/drm_atomic.c
> @@ -28,6 +28,7 @@
>  
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -309,285 +310,6 @@ drm_atomic_get_crtc_state(struct drm_atomic_state 
> *state,
>  }
>  EXPORT_SYMBOL(drm_atomic_get_crtc_state);
>  
> -static void set_out_fence_for_crtc(struct drm_atomic_state *state,
> -struct drm_crtc *crtc, s32 __user *fence_ptr)
> -{
> - state->crtcs[drm_crtc_index(crtc)].out_fence_ptr = fence_ptr;
> -}
> -
> -static s32 __user *get_out_fence_for_crtc(struct drm_atomic_state *state,
> -   struct drm_crtc *crtc)
> -{
> - s32 __user *fence_ptr;
> -
> - fence_ptr = state->crtcs[drm_crtc_index(crtc)].out_fence_ptr;
> - state->crtcs[drm_crtc_index(crtc)].out_fence_ptr = NULL;
> -
> - return fence_ptr;
> -}
> -
> -static int set_out_fence_for_connector(struct drm_atomic_state *state,
> - struct drm_connector *connector,
> - s32 __user *fence_ptr)
> -{
> - unsigned int index = drm_connector_index(connector);
> -
> - if (!fence_ptr)
> - return 0;
> -
> - if (put_user(-1, fence_ptr))
> - return -EFAULT;
> -
> - state->connectors[index].out_fence_ptr = fence_ptr;
> -
> - return 0;

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Pull intel_uncore_arm_unclaimed_mmio_detection() under the spinlock

[Patchwork]

== Series Details ==

Series: drm/i915: Pull intel_uncore_arm_unclaimed_mmio_detection() under the 
spinlock
URL   : https://patchwork.freedesktop.org/series/49128/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4766_full -> Patchwork_10081_full =

== Summary - SUCCESS ==

  No regressions found.

  

== Known issues ==

  Here are the changes found in Patchwork_10081_full that come from known 
issues:

  === IGT changes ===

 Issues hit 

igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions:
  shard-hsw:  PASS -> FAIL (fdo#103355)


 Possible fixes 

igt@drv_suspend@shrink:
  shard-hsw:  INCOMPLETE (fdo#103540, fdo#106886) -> PASS

igt@gem_exec_await@wide-contexts:
  shard-glk:  FAIL (fdo#105900) -> PASS
  shard-apl:  FAIL (fdo#105900, fdo#106680) -> PASS

igt@kms_flip@flip-vs-expired-vblank:
  shard-glk:  FAIL (fdo#102887, fdo#105363) -> PASS

igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-cpu:
  shard-glk:  FAIL (fdo#103167) -> PASS

igt@kms_setmode@basic:
  shard-apl:  FAIL (fdo#99912) -> PASS


  fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103355 https://bugs.freedesktop.org/show_bug.cgi?id=103355
  fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#105900 https://bugs.freedesktop.org/show_bug.cgi?id=105900
  fdo#106680 https://bugs.freedesktop.org/show_bug.cgi?id=106680
  fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (5 -> 5) ==

  No changes in participating hosts


== Build changes ==

* Linux: CI_DRM_4766 -> Patchwork_10081

  CI_DRM_4766: 0d35b9d0b3a74c41ac1ffe1a34aa9c98d2a3a0b9 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4625: 67fbe2967889484f1248d851c068e1021f2dc332 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10081: c81f7041022f991c7b1b9c1b323653beb538a14b @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ 
git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10081/shards.html
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[Intel-gfx] [PATCH xf86-video-intel] sna/io: Align the linear source buffer to cache line for 2d blt of SKL+

[Guang Bai]

On SKL+ the linear source buffer has to start from cache line boundary
to meet the 2d engine source copy requirements. Apply this cache line
alignment policy for SKL+ only.

Signed-off-by: Guang Bai 
---
 src/sna/sna_io.c | 47 +++
 1 file changed, 35 insertions(+), 12 deletions(-)

diff --git a/src/sna/sna_io.c b/src/sna/sna_io.c
index d32bd58..48d9354 100644
--- a/src/sna/sna_io.c
+++ b/src/sna/sna_io.c
@@ -1064,7 +1064,7 @@ tile:
if (kgem->gen >= 0100) {
cmd |= 8;
do {
-   int nbox_this_time, rem;
+   int nbox_this_time, rem, pitch_aligned;
 
nbox_this_time = nbox;
rem = kgem_batch_space(kgem);
@@ -1077,12 +1077,19 @@ tile:
 
/* Count the total number of bytes to be read and 
allocate a
 * single buffer large enough. Or if it is very small, 
combine
-* with other allocations. */
+* with other allocations. Each sub-buffer starting 
point has
+* to be aligned to 64 bytes to conform latest hardware 
requirments.
+* Align the pitch of each sub-buffer to 64 bytes for 
simplicities.
+*/
offset = 0;
for (n = 0; n < nbox_this_time; n++) {
int height = box[n].y2 - box[n].y1;
int width = box[n].x2 - box[n].x1;
-   offset += PITCH(width, 
dst->drawable.bitsPerPixel >> 3) * height;
+   if (kgem->gen >= 0110) {
+   pitch_aligned = ALIGN(PITCH(width, 
dst->drawable.bitsPerPixel >> 3), 64);
+   offset += pitch_aligned * height;
+   } else
+   offset += PITCH(width, 
dst->drawable.bitsPerPixel >> 3) * height;
}
 
src_bo = kgem_create_buffer(kgem, offset,
@@ -1113,14 +1120,24 @@ tile:
assert(box->x1 + dst_dx >= 0);
assert(box->y1 + dst_dy >= 0);
 
-   memcpy_blt(src, (char *)ptr + offset,
-  dst->drawable.bitsPerPixel,
-  stride, pitch,
-  box->x1 + src_dx, box->y1 + 
src_dy,
-  0, 0,
-  width, height);
+   if (kgem->gen >= 0110) {
+   pitch_aligned = ALIGN(pitch, 
64);
+   memcpy_blt(src, (char *)ptr + 
offset,
+  
dst->drawable.bitsPerPixel,
+  stride, 
pitch_aligned,
+  box->x1 + src_dx, 
box->y1 + src_dy,
+  0, 0,
+  width, height);
+   } else
+   memcpy_blt(src, (char *)ptr + 
offset,
+  
dst->drawable.bitsPerPixel,
+  stride, pitch,
+  box->x1 + src_dx, 
box->y1 + src_dy,
+  0, 0,
+  width, height);
 
assert(kgem->mode == KGEM_BLT);
+
b = kgem->batch + kgem->nbatch;
b[0] = cmd;
b[1] = br13;
@@ -1133,16 +1150,22 @@ tile:
 
KGEM_RELOC_FENCED,
 0);
b[6] = 0;
-   b[7] = pitch;
+   if (kgem->gen >= 0110)
+   b[7] = pitch_aligned;
+   else
+   b[7] = pitch;
+
*(uint64_t *)(b+8) =
kgem_add_reloc64(kgem, 
kgem->nbatch + 8, src_bo,
 
I915_GEM_DOMAIN_RENDER << 16 |

Re: [Intel-gfx] [PATCH] drm/i915: Be defensive and don't assume PSR has any commit to sync against

[Chris Wilson]

Quoting Ville Syrjälä (2018-09-04 19:06:29)
> On Tue, Sep 04, 2018 at 08:59:32PM +0300, Ville Syrjälä wrote:
> > On Tue, Sep 04, 2018 at 06:44:14PM +0100, Chris Wilson wrote:
> > > Quoting Ville Syrjälä (2018-09-04 18:39:53)
> > > > On Tue, Sep 04, 2018 at 05:29:02PM +0100, Chris Wilson wrote:
> > > > > If the previous modeset commit has completed and is no longer part of
> > > > > the crtc state, skip waiting for it.
> > > > > 
> > > > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107792
> > > > > Fixes: c44301fce614 ("drm/i915: Allow control of PSR at runtime 
> > > > > through debugfs, v6")
> > > > > Signed-off-by: Chris Wilson 
> > > > > Cc: Maarten Lankhorst 
> > > > > Cc: Rodrigo Vivi 
> > > > > Cc: Dhinakaran Pandiyan 
> > > > > ---
> > > > >  drivers/gpu/drm/i915/intel_psr.c | 16 ++--
> > > > >  1 file changed, 10 insertions(+), 6 deletions(-)
> > > > > 
> > > > > diff --git a/drivers/gpu/drm/i915/intel_psr.c 
> > > > > b/drivers/gpu/drm/i915/intel_psr.c
> > > > > index 21984d4c08ed..bddc9c7c681e 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_psr.c
> > > > > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > > > > @@ -834,6 +834,7 @@ int intel_psr_set_debugfs_mode(struct 
> > > > > drm_i915_private *dev_priv,
> > > > >   struct drm_device *dev = &dev_priv->drm;
> > > > >   struct drm_connector_state *conn_state;
> > > > >   struct intel_crtc_state *crtc_state = NULL;
> > > > > + struct drm_crtc_commit *commit = NULL;
> > > > >   struct drm_crtc *crtc;
> > > > >   struct intel_dp *dp;
> > > > >   int ret;
> > > > > @@ -860,12 +861,15 @@ int intel_psr_set_debugfs_mode(struct 
> > > > > drm_i915_private *dev_priv,
> > > > >   return ret;
> > > > >  
> > > > >   crtc_state = to_intel_crtc_state(crtc->state);
> > > > > - ret = 
> > > > > wait_for_completion_interruptible(&crtc_state->base.commit->hw_done);
> > > > > - } else
> > > > > - ret = 
> > > > > wait_for_completion_interruptible(&conn_state->commit->hw_done);
> > > > > -
> > > > > - if (ret)
> > > > > - return ret;
> > > > > + commit = crtc_state->base.commit;
> > > > > + } else {
> > > > > + commit = conn_state->commit;
> > > > 
> > > > I can't even find where we clear state->commit after its done.
> > > > Do we just leave it pointing at freed memory or something? Also I
> > > > can't figure out why drm_atomic_helper_commit_hw_done() copies
> > > > the commit also to the old state.
> > > 
> > > Let me be the messenger then ;) commit is NULL at this point, I just
> > > presumed it was intentional.
> > 
> > My expectation would be that it gets cleared somewhere, but I simply
> > can't find any such code.
> 
> Actually it looks like there is no such code. The event based
> release_crtc_commit() thing gets its own reference so presumably the
> original reference stays with the state until the state itself gets
> destroyed.

Happy with the it never had a commit theory, or is this a deeper problem
that needs root causing?
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915: Be defensive and don't assume PSR has any commit to sync against

[Ville Syrjälä]

On Tue, Sep 04, 2018 at 08:59:32PM +0300, Ville Syrjälä wrote:
> On Tue, Sep 04, 2018 at 06:44:14PM +0100, Chris Wilson wrote:
> > Quoting Ville Syrjälä (2018-09-04 18:39:53)
> > > On Tue, Sep 04, 2018 at 05:29:02PM +0100, Chris Wilson wrote:
> > > > If the previous modeset commit has completed and is no longer part of
> > > > the crtc state, skip waiting for it.
> > > > 
> > > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107792
> > > > Fixes: c44301fce614 ("drm/i915: Allow control of PSR at runtime through 
> > > > debugfs, v6")
> > > > Signed-off-by: Chris Wilson 
> > > > Cc: Maarten Lankhorst 
> > > > Cc: Rodrigo Vivi 
> > > > Cc: Dhinakaran Pandiyan 
> > > > ---
> > > >  drivers/gpu/drm/i915/intel_psr.c | 16 ++--
> > > >  1 file changed, 10 insertions(+), 6 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/intel_psr.c 
> > > > b/drivers/gpu/drm/i915/intel_psr.c
> > > > index 21984d4c08ed..bddc9c7c681e 100644
> > > > --- a/drivers/gpu/drm/i915/intel_psr.c
> > > > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > > > @@ -834,6 +834,7 @@ int intel_psr_set_debugfs_mode(struct 
> > > > drm_i915_private *dev_priv,
> > > >   struct drm_device *dev = &dev_priv->drm;
> > > >   struct drm_connector_state *conn_state;
> > > >   struct intel_crtc_state *crtc_state = NULL;
> > > > + struct drm_crtc_commit *commit = NULL;
> > > >   struct drm_crtc *crtc;
> > > >   struct intel_dp *dp;
> > > >   int ret;
> > > > @@ -860,12 +861,15 @@ int intel_psr_set_debugfs_mode(struct 
> > > > drm_i915_private *dev_priv,
> > > >   return ret;
> > > >  
> > > >   crtc_state = to_intel_crtc_state(crtc->state);
> > > > - ret = 
> > > > wait_for_completion_interruptible(&crtc_state->base.commit->hw_done);
> > > > - } else
> > > > - ret = 
> > > > wait_for_completion_interruptible(&conn_state->commit->hw_done);
> > > > -
> > > > - if (ret)
> > > > - return ret;
> > > > + commit = crtc_state->base.commit;
> > > > + } else {
> > > > + commit = conn_state->commit;
> > > 
> > > I can't even find where we clear state->commit after its done.
> > > Do we just leave it pointing at freed memory or something? Also I
> > > can't figure out why drm_atomic_helper_commit_hw_done() copies
> > > the commit also to the old state.
> > 
> > Let me be the messenger then ;) commit is NULL at this point, I just
> > presumed it was intentional.
> 
> My expectation would be that it gets cleared somewhere, but I simply
> can't find any such code.

Actually it looks like there is no such code. The event based
release_crtc_commit() thing gets its own reference so presumably the
original reference stays with the state until the state itself gets
destroyed.

-- 
Ville Syrjälä
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Re: [Intel-gfx] [PATCH] drm/i915: Be defensive and don't assume PSR has any commit to sync against

[Ville Syrjälä]

On Tue, Sep 04, 2018 at 06:44:14PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjälä (2018-09-04 18:39:53)
> > On Tue, Sep 04, 2018 at 05:29:02PM +0100, Chris Wilson wrote:
> > > If the previous modeset commit has completed and is no longer part of
> > > the crtc state, skip waiting for it.
> > > 
> > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107792
> > > Fixes: c44301fce614 ("drm/i915: Allow control of PSR at runtime through 
> > > debugfs, v6")
> > > Signed-off-by: Chris Wilson 
> > > Cc: Maarten Lankhorst 
> > > Cc: Rodrigo Vivi 
> > > Cc: Dhinakaran Pandiyan 
> > > ---
> > >  drivers/gpu/drm/i915/intel_psr.c | 16 ++--
> > >  1 file changed, 10 insertions(+), 6 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_psr.c 
> > > b/drivers/gpu/drm/i915/intel_psr.c
> > > index 21984d4c08ed..bddc9c7c681e 100644
> > > --- a/drivers/gpu/drm/i915/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > > @@ -834,6 +834,7 @@ int intel_psr_set_debugfs_mode(struct 
> > > drm_i915_private *dev_priv,
> > >   struct drm_device *dev = &dev_priv->drm;
> > >   struct drm_connector_state *conn_state;
> > >   struct intel_crtc_state *crtc_state = NULL;
> > > + struct drm_crtc_commit *commit = NULL;
> > >   struct drm_crtc *crtc;
> > >   struct intel_dp *dp;
> > >   int ret;
> > > @@ -860,12 +861,15 @@ int intel_psr_set_debugfs_mode(struct 
> > > drm_i915_private *dev_priv,
> > >   return ret;
> > >  
> > >   crtc_state = to_intel_crtc_state(crtc->state);
> > > - ret = 
> > > wait_for_completion_interruptible(&crtc_state->base.commit->hw_done);
> > > - } else
> > > - ret = 
> > > wait_for_completion_interruptible(&conn_state->commit->hw_done);
> > > -
> > > - if (ret)
> > > - return ret;
> > > + commit = crtc_state->base.commit;
> > > + } else {
> > > + commit = conn_state->commit;
> > 
> > I can't even find where we clear state->commit after its done.
> > Do we just leave it pointing at freed memory or something? Also I
> > can't figure out why drm_atomic_helper_commit_hw_done() copies
> > the commit also to the old state.
> 
> Let me be the messenger then ;) commit is NULL at this point, I just
> presumed it was intentional.

My expectation would be that it gets cleared somewhere, but I simply
can't find any such code. So the only explanation I have now is that
there has never been any commits on that crtc/connector before and
that's why it's NULL.

Based on that theory this does seem sane, so
Reviewed-by: Ville Syrjälä 

-- 
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Re: [Intel-gfx] [PATCH] drm/i915: Be defensive and don't assume PSR has any commit to sync against

[Chris Wilson]

Quoting Ville Syrjälä (2018-09-04 18:39:53)
> On Tue, Sep 04, 2018 at 05:29:02PM +0100, Chris Wilson wrote:
> > If the previous modeset commit has completed and is no longer part of
> > the crtc state, skip waiting for it.
> > 
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107792
> > Fixes: c44301fce614 ("drm/i915: Allow control of PSR at runtime through 
> > debugfs, v6")
> > Signed-off-by: Chris Wilson 
> > Cc: Maarten Lankhorst 
> > Cc: Rodrigo Vivi 
> > Cc: Dhinakaran Pandiyan 
> > ---
> >  drivers/gpu/drm/i915/intel_psr.c | 16 ++--
> >  1 file changed, 10 insertions(+), 6 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c 
> > b/drivers/gpu/drm/i915/intel_psr.c
> > index 21984d4c08ed..bddc9c7c681e 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -834,6 +834,7 @@ int intel_psr_set_debugfs_mode(struct drm_i915_private 
> > *dev_priv,
> >   struct drm_device *dev = &dev_priv->drm;
> >   struct drm_connector_state *conn_state;
> >   struct intel_crtc_state *crtc_state = NULL;
> > + struct drm_crtc_commit *commit = NULL;
> >   struct drm_crtc *crtc;
> >   struct intel_dp *dp;
> >   int ret;
> > @@ -860,12 +861,15 @@ int intel_psr_set_debugfs_mode(struct 
> > drm_i915_private *dev_priv,
> >   return ret;
> >  
> >   crtc_state = to_intel_crtc_state(crtc->state);
> > - ret = 
> > wait_for_completion_interruptible(&crtc_state->base.commit->hw_done);
> > - } else
> > - ret = 
> > wait_for_completion_interruptible(&conn_state->commit->hw_done);
> > -
> > - if (ret)
> > - return ret;
> > + commit = crtc_state->base.commit;
> > + } else {
> > + commit = conn_state->commit;
> 
> I can't even find where we clear state->commit after its done.
> Do we just leave it pointing at freed memory or something? Also I
> can't figure out why drm_atomic_helper_commit_hw_done() copies
> the commit also to the old state.

Let me be the messenger then ;) commit is NULL at this point, I just
presumed it was intentional.
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915: Rename full ppgtt configuration to be more generic

[Bob Paauwe]

On Fri, 31 Aug 2018 13:21:40 -0700
Rodrigo Vivi  wrote:

> On Fri, Aug 31, 2018 at 04:51:29PM +0100, Chris Wilson wrote:
> > Quoting Bob Paauwe (2018-08-31 16:47:04)  
> > > For ppgtt, what we're really interested in is the number of page
> > > walk levels for each platform. Rename the device info fields to
> > > reflect this:
> > > 
> > > .has_full_48b_ppgtt  -> .has_full_4lvl_ppgtt
> > > .has_full_ppgtt  -> .has_full_3lvl_ppgtt
> > > 
> > > Also add a new field, full_ppgtt_bits, that defines the actual
> > > address range.  This gives us more flexibility and will work for
> > > cases where we have platforms with different address ranges but
> > > share the same page walk levels.
> > > 
> > > Signed-off-by: Bob Paauwe 
> > > CC: Rodrigo Vivi 
> > > CC: Michel Thierry 
> > > ---
> > >  drivers/gpu/drm/i915/i915_drv.h  |  4 +--
> > >  drivers/gpu/drm/i915/i915_gem_context.c  |  2 +-
> > >  drivers/gpu/drm/i915/i915_gem_execbuffer.c   |  2 +-
> > >  drivers/gpu/drm/i915/i915_gem_gtt.c  | 34 
> > > +---
> > >  drivers/gpu/drm/i915/i915_params.c   |  3 ++-
> > >  drivers/gpu/drm/i915/i915_pci.c  | 17 +++-
> > >  drivers/gpu/drm/i915/intel_device_info.h |  7 +++--
> > >  drivers/gpu/drm/i915/selftests/huge_pages.c  |  2 +-
> > >  drivers/gpu/drm/i915/selftests/i915_gem_evict.c  |  2 +-
> > >  drivers/gpu/drm/i915/selftests/i915_gem_gtt.c|  2 +-
> > >  drivers/gpu/drm/i915/selftests/mock_gem_device.c |  2 ++
> > >  11 files changed, 45 insertions(+), 32 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.h 
> > > b/drivers/gpu/drm/i915/i915_drv.h
> > > index e5b9d3c77139..b9f7903e60d1 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > @@ -2569,8 +2569,8 @@ intel_info(const struct drm_i915_private *dev_priv)
> > >  #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
> > >  
> > >  #define USES_PPGTT(dev_priv)   (i915_modparams.enable_ppgtt)
> > > -#define USES_FULL_PPGTT(dev_priv)  (i915_modparams.enable_ppgtt >= 2)
> > > -#define USES_FULL_48BIT_PPGTT(dev_priv)
> > > (i915_modparams.enable_ppgtt == 3)
> > > +#define USES_FULL_3LVL_PPGTT(dev_priv) (i915_modparams.enable_ppgtt >= 2)
> > > +#define USES_FULL_4LVL_PPGTT(dev_priv) (i915_modparams.enable_ppgtt == 3)
> > >  #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
> > > GEM_BUG_ON((sizes) == 0); \
> > > ((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
> > > diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
> > > b/drivers/gpu/drm/i915/i915_gem_context.c
> > > index f15a039772db..a0dc3170b358 100644
> > > --- a/drivers/gpu/drm/i915/i915_gem_context.c
> > > +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> > > @@ -361,7 +361,7 @@ i915_gem_create_context(struct drm_i915_private 
> > > *dev_priv,
> > > if (IS_ERR(ctx))
> > > return ctx;
> > >  
> > > -   if (USES_FULL_PPGTT(dev_priv)) {
> > > +   if (USES_FULL_3LVL_PPGTT(dev_priv)) {  
> > 
> > That is not an improvement. It really is a question of whether or not
> > full-ppgtt is enabled.  
> 
> I think we do need this change, but only with USES_FULL_PPGTT macro
> and the rest should be checked with the full_ppgtt number of bits if
> needed.
> 

USES_FULL_PPGTT() is currently used to mean at least 3 level, but could
be 4 level so I get Chris's point that USES_FULL_3LVL_PPGTT doesn't
really work, at least not as a simple substitution.

There are only a couple of places where we care that it's actually 4
level so changing those to actually check the number of bits seems to
make sense to me.  Either

#define USES_FULL_4LVL_PPGTT(i915) (i915.number_of_bits > 32)

or just use the condition without the macro where needed.

> >   
> > > struct i915_hw_ppgtt *ppgtt;
> > >  
> > > ppgtt = i915_ppgtt_create(dev_priv, file_priv);
> > > diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c 
> > > b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> > > index a926d7d47183..166f1ea1786f 100644
> > > --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> > > +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> > > @@ -2201,7 +2201,7 @@ i915_gem_do_execbuffer(struct drm_device *dev,
> > > eb.flags = (unsigned int *)(eb.vma + args->buffer_count + 1);
> > >  
> > > eb.invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS;
> > > -   if (USES_FULL_PPGTT(eb.i915))
> > > +   if (USES_FULL_3LVL_PPGTT(eb.i915))  
> > 
> > Again the same complaint.
> > 
> > I think you need to rethink the semantics carefully.
> > -Chris
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx  



-- 
--
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Intel Corp.  Folsom, CA
(916) 356-6193

Re: [Intel-gfx] [PATCH] drm/i915: Be defensive and don't assume PSR has any commit to sync against

[Ville Syrjälä]

On Tue, Sep 04, 2018 at 05:29:02PM +0100, Chris Wilson wrote:
> If the previous modeset commit has completed and is no longer part of
> the crtc state, skip waiting for it.
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107792
> Fixes: c44301fce614 ("drm/i915: Allow control of PSR at runtime through 
> debugfs, v6")
> Signed-off-by: Chris Wilson 
> Cc: Maarten Lankhorst 
> Cc: Rodrigo Vivi 
> Cc: Dhinakaran Pandiyan 
> ---
>  drivers/gpu/drm/i915/intel_psr.c | 16 ++--
>  1 file changed, 10 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_psr.c 
> b/drivers/gpu/drm/i915/intel_psr.c
> index 21984d4c08ed..bddc9c7c681e 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -834,6 +834,7 @@ int intel_psr_set_debugfs_mode(struct drm_i915_private 
> *dev_priv,
>   struct drm_device *dev = &dev_priv->drm;
>   struct drm_connector_state *conn_state;
>   struct intel_crtc_state *crtc_state = NULL;
> + struct drm_crtc_commit *commit = NULL;
>   struct drm_crtc *crtc;
>   struct intel_dp *dp;
>   int ret;
> @@ -860,12 +861,15 @@ int intel_psr_set_debugfs_mode(struct drm_i915_private 
> *dev_priv,
>   return ret;
>  
>   crtc_state = to_intel_crtc_state(crtc->state);
> - ret = 
> wait_for_completion_interruptible(&crtc_state->base.commit->hw_done);
> - } else
> - ret = 
> wait_for_completion_interruptible(&conn_state->commit->hw_done);
> -
> - if (ret)
> - return ret;
> + commit = crtc_state->base.commit;
> + } else {
> + commit = conn_state->commit;

I can't even find where we clear state->commit after its done.
Do we just leave it pointing at freed memory or something? Also I
can't figure out why drm_atomic_helper_commit_hw_done() copies
the commit also to the old state.

> + }
> + if (commit) {
> + ret = wait_for_completion_interruptible(&commit->hw_done);
> + if (ret)
> + return ret;
> + }
>  
>   ret = mutex_lock_interruptible(&dev_priv->psr.lock);
>   if (ret)
> -- 
> 2.19.0.rc1
> 
> ___
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Re: [Intel-gfx] [PATCH v1] drm/i915: Skip modeset for cdclk changes if possible

[Kumar, Abhay]

+Susanta

From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of 
Kumar, Abhay
Sent: Tuesday, August 28, 2018 5:55 PM
To: Ville Syrjälä 
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v1] drm/i915: Skip modeset for cdclk changes if 
possible




On 8/28/2018 5:39 AM, Ville Syrjälä wrote:

On Mon, Aug 27, 2018 at 11:50:32AM -0700, Abhay Kumar wrote:

From: Ville Syrjälä 




If we have only a single active pipe and the cdclk change only requires

the cd2x divider to be updated bxt+ can do the update with forcing a full

modeset on the pipe. Try to hook that up.



Signed-off-by: Ville Syrjälä 


Signed-off-by: Abhay Kumar 

---

 drivers/gpu/drm/i915/i915_drv.h  |   3 +-

 drivers/gpu/drm/i915/i915_reg.h  |   3 +-

 drivers/gpu/drm/i915/intel_cdclk.c   | 105 +--

 drivers/gpu/drm/i915/intel_display.c |  20 ++-

 drivers/gpu/drm/i915/intel_drv.h |   9 ++-

 5 files changed, 105 insertions(+), 35 deletions(-)





@@ -12252,12 +12253,24 @@ static int intel_modeset_checks(struct 
drm_atomic_state *state)

  return ret;

   }



+

   /* All pipes must be switched off while we change the cdclk. */

-  if (intel_cdclk_needs_modeset(&dev_priv->cdclk.actual,

-   &intel_state->cdclk.actual)) {

+  if (is_power_of_2(intel_state->active_crtcs) &&

+  intel_cdclk_needs_cd2x_update(dev_priv,

+  &dev_priv->cdclk.actual,

+  &intel_state->cdclk.actual)) {

+  ret = intel_lock_all_pipes(state);

+  if (ret < 0)

+ return ret;

+

+  intel_state->cdclk.pipe = ilog2(intel_state->active_crtcs);



BTW on further reflection this probably isn't quite sufficient. Let's

say we have a commit with allow_modeset=true, but we aren't actually

required to do a modeset based on any of the state changes. If we still

have to change cdclk we should actually be doing the cd2x update

atomically with the plane updates, or we should do it before or after

the plane updates depending on whether the cdclk freq is going up or

down.



Doing the update atomically with the plane updates might be nicer in the

end, but for that we would likely need to split the .set_cdclk() hooks

into three parts (pre+commit+post). Whereas just doing the update before

or after the plane updates as needed would probably be a little simpler.
Yeah. That might also get rid of cdclk mismatch warning during multiple suspend 
resume cycle.

[  280.600259] cdclk state doesn't match!

[  280.600270] calling  1-8+ @ 3110, parent: usb1, cb: usb_dev_resume

[  280.600276] WARNING: CPU: 3 PID: 5224 at /mnt/host/source/src/third_party/ker

nel/v4.14/drivers/gpu/drm/i915/intel_cdclk.c:1867 intel_set_cdclk+0xaa/0xdb

[  280.600277] Modules linked in: cmac rfcomm uinput snd_soc_sst_bxt_da7219_max9

8357a snd_soc_hdac_hdmi snd_soc_dmic lzo lzo_compress snd_soc_skl snd_soc_skl_ip

c snd_soc_sst_ipc snd_soc_sst_dsp snd_soc_acpi snd_hda_ext_core snd_hda_core

[  280.600307] calling  phy0+ @ 3102, parent: :00:0c.0, cb: wiphy_resume [cf

g80211]

[  280.600308]  zram snd_soc_max98357a acpi_als snd_soc_da7219 bridge stp llc ip

t_MASQUERADE nf_nat_masquerade_ipv4 xt_mark fuse snd_seq_dummy snd_seq snd_seq_d

evice btusb btrtl btbcm iio_trig_sysfs btintel uvcvideo bluetooth videobuf2_vmal

loc videobuf2_memops videobuf2_v4l2 ecdh_generic videobuf2_core cros_ec_sensors

cros_ec_sensors_ring cros_ec_sensors_core industrialio_triggered_buffer kfifo_bu

[  280.600346] RDX: b8258dd0 RSI: 0002 RDI: b8258db0

[  280.600347] RBP: bb9546b73aa0 R08:  R09: 

[  280.600348] R10:  R11: b86d8518 R12: a2207579

[  280.600349] R13: a22075793d24 R14:  R15: a2202eec9800

000

[  280.600352] CS:  0010 DS:  ES:  CR0: 80050033

[  280.600353] CR2: 7f43c04d0e50 CR3: 000224112000 CR4: 003406e0

[  280.600354] Call Trace:

[  280.600361]  intel_atomic_commit_tail+0x20a/0xacb

[  280.600363]  ? intel_atomic_commit_ready+0x44/0x4c

[  280.600365]  intel_atomic_commit+0x227/0x238

[  280.600368]  glk_force_audio_cdclk+0x9f/0x119

[  280.600370]  i915_audio_component_get_power+0x3e/0x4d

[  280.600376]  snd_hdac_display_power+0x53/0x97 [snd_hda_core]

[  280.600379] calling  1-9+ @ 3086, parent: usb1, cb: usb_dev_resume

[  280.600384]  skl_resume+0x3a/0x17a [snd_soc_skl]

[  280.600387]  ? pci_pm_suspend_noirq+0x1e9/0x1e9

[  280.600391]  dpm_run_callback+0x59/0xbf

[  280.600394]  device_resume+0x192/0x1d4

[  280.600396]  dpm_resume+0x145/0x1da

[  280.600398]  dpm_resume_end+0x11/0x1a

[  280.60040

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Be defensive and don't assume PSR has any commit to sync against

[Patchwork]

== Series Details ==

Series: drm/i915: Be defensive and don't assume PSR has any commit to sync 
against
URL   : https://patchwork.freedesktop.org/series/49141/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4767 -> Patchwork_10084 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/49141/revisions/1/mbox/

== Known issues ==

  Here are the changes found in Patchwork_10084 that come from known issues:

  === IGT changes ===

 Issues hit 

igt@gem_exec_suspend@basic-s3:
  fi-kbl-soraka:  NOTRUN -> INCOMPLETE (fdo#107774, fdo#107556)


 Possible fixes 

igt@gem_exec_suspend@basic-s3:
  fi-cfl-8109u:   DMESG-WARN (fdo#107345) -> PASS +1

igt@gem_exec_suspend@basic-s4-devices:
  fi-kbl-7500u:   DMESG-WARN (fdo#105128, fdo#107139) -> PASS

igt@kms_flip@basic-flip-vs-modeset:
  fi-cfl-8109u:   INCOMPLETE (fdo#107468) -> PASS


  fdo#105128 https://bugs.freedesktop.org/show_bug.cgi?id=105128
  fdo#107139 https://bugs.freedesktop.org/show_bug.cgi?id=107139
  fdo#107345 https://bugs.freedesktop.org/show_bug.cgi?id=107345
  fdo#107468 https://bugs.freedesktop.org/show_bug.cgi?id=107468
  fdo#107556 https://bugs.freedesktop.org/show_bug.cgi?id=107556
  fdo#107774 https://bugs.freedesktop.org/show_bug.cgi?id=107774


== Participating hosts (50 -> 46) ==

  Additional (1): fi-kbl-soraka 
  Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan 
fi-hsw-4200u 


== Build changes ==

* Linux: CI_DRM_4767 -> Patchwork_10084

  CI_DRM_4767: e9b69bafd3c2c13a8b9fa8e7a410f5d5ef32e328 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4626: bfce01d8c93dbd86e6ab04ca1afb844e0cbc8078 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10084: 23e6b7e3848fb3bbf675255440b077f6187a81a5 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

23e6b7e3848f drm/i915: Be defensive and don't assume PSR has any commit to sync 
against

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10084/issues.html
___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.BAT: success for igt/pm_rpm: Reload the module with full mmio debugging

[Patchwork]

== Series Details ==

Series: igt/pm_rpm: Reload the module with full mmio debugging
URL   : https://patchwork.freedesktop.org/series/49138/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4766 -> IGTPW_1785 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/49138/revisions/1/mbox/

== Known issues ==

  Here are the changes found in IGTPW_1785 that come from known issues:

  === IGT changes ===

 Issues hit 

igt@gem_exec_suspend@basic-s4-devices:
  fi-blb-e6850:   PASS -> INCOMPLETE (fdo#107718)

igt@kms_chamelium@hdmi-hpd-fast:
  fi-kbl-7500u:   SKIP -> FAIL (fdo#103841, fdo#102672)

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
  fi-cfl-8109u:   PASS -> INCOMPLETE (fdo#106070)


 Possible fixes 

igt@pm_rpm@module-reload:
  fi-bsw-kefka:   DMESG-WARN (fdo#107704) -> PASS
  fi-bsw-n3050:   DMESG-WARN (fdo#107704) -> PASS
  fi-byt-j1900:   DMESG-WARN (fdo#107704) -> PASS
  fi-byt-n2820:   DMESG-WARN (fdo#107704) -> PASS


  fdo#102672 https://bugs.freedesktop.org/show_bug.cgi?id=102672
  fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841
  fdo#106070 https://bugs.freedesktop.org/show_bug.cgi?id=106070
  fdo#107704 https://bugs.freedesktop.org/show_bug.cgi?id=107704
  fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718


== Participating hosts (49 -> 44) ==

  Additional (1): fi-hsw-4770r 
  Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan 
fi-ctg-p8600 fi-pnv-d510 


== Build changes ==

* IGT: IGT_4625 -> IGTPW_1785

  CI_DRM_4766: 0d35b9d0b3a74c41ac1ffe1a34aa9c98d2a3a0b9 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_1785: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1785/
  IGT_4625: 67fbe2967889484f1248d851c068e1021f2dc332 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1785/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH] drm/i915: Be defensive and don't assume PSR has any commit to sync against

[Chris Wilson]

If the previous modeset commit has completed and is no longer part of
the crtc state, skip waiting for it.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107792
Fixes: c44301fce614 ("drm/i915: Allow control of PSR at runtime through 
debugfs, v6")
Signed-off-by: Chris Wilson 
Cc: Maarten Lankhorst 
Cc: Rodrigo Vivi 
Cc: Dhinakaran Pandiyan 
---
 drivers/gpu/drm/i915/intel_psr.c | 16 ++--
 1 file changed, 10 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 21984d4c08ed..bddc9c7c681e 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -834,6 +834,7 @@ int intel_psr_set_debugfs_mode(struct drm_i915_private 
*dev_priv,
struct drm_device *dev = &dev_priv->drm;
struct drm_connector_state *conn_state;
struct intel_crtc_state *crtc_state = NULL;
+   struct drm_crtc_commit *commit = NULL;
struct drm_crtc *crtc;
struct intel_dp *dp;
int ret;
@@ -860,12 +861,15 @@ int intel_psr_set_debugfs_mode(struct drm_i915_private 
*dev_priv,
return ret;
 
crtc_state = to_intel_crtc_state(crtc->state);
-   ret = 
wait_for_completion_interruptible(&crtc_state->base.commit->hw_done);
-   } else
-   ret = 
wait_for_completion_interruptible(&conn_state->commit->hw_done);
-
-   if (ret)
-   return ret;
+   commit = crtc_state->base.commit;
+   } else {
+   commit = conn_state->commit;
+   }
+   if (commit) {
+   ret = wait_for_completion_interruptible(&commit->hw_done);
+   if (ret)
+   return ret;
+   }
 
ret = mutex_lock_interruptible(&dev_priv->psr.lock);
if (ret)
-- 
2.19.0.rc1

___
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Reduce context HW ID lifetime (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Reduce context HW ID lifetime (rev3)
URL   : https://patchwork.freedesktop.org/series/44134/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4767 -> Patchwork_10083 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/44134/revisions/3/mbox/

== Known issues ==

  Here are the changes found in Patchwork_10083 that come from known issues:

  === IGT changes ===

 Issues hit 

igt@gem_exec_suspend@basic-s3:
  fi-kbl-soraka:  NOTRUN -> INCOMPLETE (fdo#107774, fdo#107556)


 Possible fixes 

igt@gem_exec_suspend@basic-s3:
  fi-cfl-8109u:   DMESG-WARN (fdo#107345) -> PASS +1

igt@gem_exec_suspend@basic-s4-devices:
  fi-kbl-7500u:   DMESG-WARN (fdo#105128, fdo#107139) -> PASS

igt@kms_flip@basic-flip-vs-modeset:
  fi-cfl-8109u:   INCOMPLETE (fdo#107468) -> PASS


  fdo#105128 https://bugs.freedesktop.org/show_bug.cgi?id=105128
  fdo#107139 https://bugs.freedesktop.org/show_bug.cgi?id=107139
  fdo#107345 https://bugs.freedesktop.org/show_bug.cgi?id=107345
  fdo#107468 https://bugs.freedesktop.org/show_bug.cgi?id=107468
  fdo#107556 https://bugs.freedesktop.org/show_bug.cgi?id=107556
  fdo#107774 https://bugs.freedesktop.org/show_bug.cgi?id=107774


== Participating hosts (50 -> 45) ==

  Additional (1): fi-kbl-soraka 
  Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan 
fi-ctg-p8600 fi-kbl-7560u 


== Build changes ==

* Linux: CI_DRM_4767 -> Patchwork_10083

  CI_DRM_4767: e9b69bafd3c2c13a8b9fa8e7a410f5d5ef32e328 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4626: bfce01d8c93dbd86e6ab04ca1afb844e0cbc8078 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10083: 9a6f6d0994b229642ebe29974173f89352efd764 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

9a6f6d0994b2 drm/i915: Reduce context HW ID lifetime

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10083/issues.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH i-g-t] igt/pm_rpm: Reload the module with full mmio debugging

[Chris Wilson]

Our unclaimed mmio access debugging is lazy, doing cheap checks
periodically and only if they fail do a full check around every mmio
access. When testing for runtime pm, enable the full mmio debugging from
the initial load.

Signed-off-by: Chris Wilson 
Cc: Imre Deak 
Reviewed-by: Imre Deak 
---
 tests/pm_rpm.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/tests/pm_rpm.c b/tests/pm_rpm.c
index e3bb6227a..c24fd95bb 100644
--- a/tests/pm_rpm.c
+++ b/tests/pm_rpm.c
@@ -2058,7 +2058,7 @@ int main(int argc, char *argv[])
igt_subtest("module-reload") {
igt_debug("Reload w/o display\n");
igt_i915_driver_unload();
-   igt_assert_eq(igt_i915_driver_load("disable_display=1"), 0);
+   igt_assert_eq(igt_i915_driver_load("disable_display=1 
mmio_debug=-1"), 0);
 
igt_assert(setup_environment());
igt_assert(igt_wait(device_in_pci_d3(), 2000, 100));
@@ -2066,13 +2066,16 @@ int main(int argc, char *argv[])
 
igt_debug("Reload as normal\n");
igt_i915_driver_unload();
-   igt_assert_eq(igt_i915_driver_load(NULL), 0);
+   igt_assert_eq(igt_i915_driver_load("mmio_debug=-1"), 0);
 
igt_assert(setup_environment());
igt_assert(igt_wait(device_in_pci_d3(), 2000, 100));
if (enable_one_screen_with_type(&ms_data, SCREEN_TYPE_ANY))
drm_resources_equal_subtest();
teardown_environment();
+
+   /* Remove our mmio_debugging module */
+   igt_i915_driver_unload();
}
 
igt_exit();
-- 
2.19.0.rc1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Reduce context HW ID lifetime (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Reduce context HW ID lifetime (rev3)
URL   : https://patchwork.freedesktop.org/series/44134/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Commit: drm/i915: Reduce context HW ID lifetime
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3686:16: warning: expression 
using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3688:16: warning: expression 
using sizeof(void)

___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Reduce context HW ID lifetime (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: Reduce context HW ID lifetime (rev3)
URL   : https://patchwork.freedesktop.org/series/44134/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
9a6f6d0994b2 drm/i915: Reduce context HW ID lifetime
-:61: CHECK:UNCOMMENTED_DEFINITION: struct mutex definition without comment
#61: FILE: drivers/gpu/drm/i915/i915_drv.h:1864:
+   struct mutex mutex;

total: 0 errors, 0 warnings, 1 checks, 433 lines checked

___
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v2] drm/i915: Reduce context HW ID lifetime

[Chris Wilson]

Future gen reduce the number of bits we will have available to
differentiate between contexts, so reduce the lifetime of the ID
assignment from that of the context to its current active cycle (i.e.
only while it is pinned for use by the HW, will it have a constant ID).
This means that instead of a max of 2k allocated contexts (worst case
before fun with bit twiddling), we instead have a limit of 2k in flight
contexts (minus a few that have been pinned by the kernel or by perf).

To reduce the number of contexts id we require, we allocate a context id
on first and mark it as pinned for as long as the GEM context itself is,
that is we keep it pinned it while active on each engine. If we exhaust
our context id space, then we try to reclaim an id from an idle context.
In the extreme case where all context ids are pinned by active contexts,
we force the system to idle in order to recover ids.

We cannot reduce the scope of an HW-ID to an engine (allowing the same
gem_context to have different ids on each engine) as in the future we
will need to preassign an id before we know which engine the
context is being executed on.

v2: Improved commentary (Tvrtko) [I tried at least]

References: https://bugs.freedesktop.org/show_bug.cgi?id=107788
Signed-off-by: Chris Wilson 
Cc: Lionel Landwerlin 
Cc: Tvrtko Ursulin 
Cc: Mika Kuoppala 
Cc: Michel Thierry 
Cc: Michal Wajdeczko 
Cc: Daniele Ceraolo Spurio 
---
 drivers/gpu/drm/i915/i915_debugfs.c   |   5 +-
 drivers/gpu/drm/i915/i915_drv.h   |   2 +
 drivers/gpu/drm/i915/i915_gem_context.c   | 222 +-
 drivers/gpu/drm/i915/i915_gem_context.h   |  23 ++
 drivers/gpu/drm/i915/intel_lrc.c  |   8 +
 drivers/gpu/drm/i915/selftests/mock_context.c |  11 +-
 6 files changed, 201 insertions(+), 70 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 4ad0e2ed8610..1f7051e97afb 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1953,7 +1953,10 @@ static int i915_context_status(struct seq_file *m, void 
*unused)
return ret;
 
list_for_each_entry(ctx, &dev_priv->contexts.list, link) {
-   seq_printf(m, "HW context %u ", ctx->hw_id);
+   seq_puts(m, "HW context ");
+   if (!list_empty(&ctx->hw_id_link))
+   seq_printf(m, "%x [pin %u]", ctx->hw_id,
+  atomic_read(&ctx->hw_id_pin_count));
if (ctx->pid) {
struct task_struct *task;
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5a4da5b723fd..767615ecdea5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1861,6 +1861,7 @@ struct drm_i915_private {
struct mutex av_mutex;
 
struct {
+   struct mutex mutex;
struct list_head list;
struct llist_head free_list;
struct work_struct free_work;
@@ -1873,6 +1874,7 @@ struct drm_i915_private {
 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
 #define MAX_GUC_CONTEXT_HW_ID (1 << 20) /* exclusive */
 #define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */
+   struct list_head hw_id_list;
} contexts;
 
u32 fdi_rx_config;
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index f15a039772db..747b8170a15a 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -115,6 +115,95 @@ static void lut_close(struct i915_gem_context *ctx)
rcu_read_unlock();
 }
 
+static inline int new_hw_id(struct drm_i915_private *i915, gfp_t gfp)
+{
+   unsigned int max;
+
+   lockdep_assert_held(&i915->contexts.mutex);
+
+   if (INTEL_GEN(i915) >= 11)
+   max = GEN11_MAX_CONTEXT_HW_ID;
+   else if (USES_GUC_SUBMISSION(i915))
+   /*
+* When using GuC in proxy submission, GuC consumes the
+* highest bit in the context id to indicate proxy submission.
+*/
+   max = MAX_GUC_CONTEXT_HW_ID;
+   else
+   max = MAX_CONTEXT_HW_ID;
+
+   return ida_simple_get(&i915->contexts.hw_ida, 0, max, gfp);
+}
+
+static int steal_hw_id(struct drm_i915_private *i915)
+{
+   struct i915_gem_context *ctx, *cn;
+   LIST_HEAD(pinned);
+   int id = -ENOSPC;
+
+   lockdep_assert_held(&i915->contexts.mutex);
+
+   list_for_each_entry_safe(ctx, cn,
+&i915->contexts.hw_id_list, hw_id_link) {
+   if (atomic_read(&ctx->hw_id_pin_count)) {
+   list_move_tail(&ctx->hw_id_link, &pinned);
+   continue;
+   }
+
+   GEM_BUG_ON(!ctx->hw_id); /* perma-pinned kernel context */
+   list_del_init(&ctx->hw_id_link);
+   id = ctx->hw

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: optimzie eDP 1.4 config

[Patchwork]

== Series Details ==

Series: drm/i915: optimzie eDP 1.4 config
URL   : https://patchwork.freedesktop.org/series/49131/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4766 -> Patchwork_10082 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/49131/revisions/1/mbox/

== Known issues ==

  Here are the changes found in Patchwork_10082 that come from known issues:

  === IGT changes ===

 Issues hit 

igt@kms_pipe_crc_basic@hang-read-crc-pipe-b:
  fi-byt-clapper: PASS -> FAIL (fdo#103191, fdo#107362)

igt@prime_vgem@basic-fence-flip:
  fi-ilk-650: PASS -> FAIL (fdo#104008)


  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008
  fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362


== Participating hosts (49 -> 44) ==

  Additional (1): fi-hsw-4770r 
  Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan 
fi-ctg-p8600 fi-pnv-d510 


== Build changes ==

* Linux: CI_DRM_4766 -> Patchwork_10082

  CI_DRM_4766: 0d35b9d0b3a74c41ac1ffe1a34aa9c98d2a3a0b9 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4625: 67fbe2967889484f1248d851c068e1021f2dc332 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10082: 2602078fba7029858fdc79ab45b750805f759ac2 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

2602078fba70 drm/i915: optimzie eDP 1.4 config

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10082/issues.html
___
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[Intel-gfx] [drm-tip:drm-tip 144/320] debug.c:undefined reference to `save_stack_trace'

[kbuild test robot]

Hi Daniel,

FYI, the error/warning still remains.

tree:   git://anongit.freedesktop.org/drm/drm-tip drm-tip
head:   1b18cb66428cffa748719cf900b2decac3690029
commit: 7928ca5cc786fdc0269342f1b9e22c2af939b989 [144/320] RFC: debugobjects: 
capture stack traces at _init() time
config: m68k-allyesconfig (attached as .config)
compiler: m68k-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
wget 
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O 
~/bin/make.cross
chmod +x ~/bin/make.cross
git checkout 7928ca5cc786fdc0269342f1b9e22c2af939b989
# save the attached .config to linux build tree
GCC_VERSION=7.2.0 make.cross ARCH=m68k 
:: branch date: 9 hours ago
:: commit date: 3 weeks ago

All errors (new ones prefixed by >>):

   kernel/dma/debug.o: In function `dma_entry_alloc':
>> debug.c:(.text+0x11c2): undefined reference to `save_stack_trace'
   kernel/backtracetest.o: In function `backtrace_regression_test':
   backtracetest.c:(.text+0xd8): undefined reference to `save_stack_trace'
   mm/slub.o: In function `set_track':
>> slub.c:(.text+0x12b4): undefined reference to `save_stack_trace'
   fs/btrfs/ref-verify.o: In function `btrfs_ref_tree_mod':
   ref-verify.c:(.text+0x92e): undefined reference to `save_stack_trace'
   lib/debugobjects.o: In function `save_stack.isra.0':
>> debugobjects.c:(.text+0x9f2): undefined reference to `save_stack_trace'

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation


.config.gz
Description: application/gzip
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Pull intel_uncore_arm_unclaimed_mmio_detection() under the spinlock

[Patchwork]

== Series Details ==

Series: drm/i915: Pull intel_uncore_arm_unclaimed_mmio_detection() under the 
spinlock
URL   : https://patchwork.freedesktop.org/series/49128/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4766 -> Patchwork_10081 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/49128/revisions/1/mbox/

== Known issues ==

  Here are the changes found in Patchwork_10081 that come from known issues:

  === IGT changes ===

 Issues hit 

igt@gem_exec_suspend@basic-s3:
  fi-kbl-soraka:  NOTRUN -> INCOMPLETE (fdo#107774, fdo#107556)

igt@kms_frontbuffer_tracking@basic:
  fi-hsw-peppy:   PASS -> DMESG-WARN (fdo#102614)
  fi-byt-clapper: PASS -> FAIL (fdo#103167)

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
  fi-bxt-dsi: PASS -> INCOMPLETE (fdo#103927)


  fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#107556 https://bugs.freedesktop.org/show_bug.cgi?id=107556
  fdo#107774 https://bugs.freedesktop.org/show_bug.cgi?id=107774


== Participating hosts (49 -> 46) ==

  Additional (2): fi-kbl-soraka fi-hsw-4770r 
  Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan 
fi-hsw-4200u 


== Build changes ==

* Linux: CI_DRM_4766 -> Patchwork_10081

  CI_DRM_4766: 0d35b9d0b3a74c41ac1ffe1a34aa9c98d2a3a0b9 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4625: 67fbe2967889484f1248d851c068e1021f2dc332 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10081: c81f7041022f991c7b1b9c1b323653beb538a14b @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

c81f7041022f drm/i915: Pull intel_uncore_arm_unclaimed_mmio_detection() under 
the spinlock

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10081/issues.html
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Re: [Intel-gfx] [PATCH i-g-t] lib/pm_rpm: Reload the module with full mmio debugging

[Imre Deak]

On Tue, Sep 04, 2018 at 03:21:09PM +0100, Chris Wilson wrote:
> Quoting Imre Deak (2018-09-04 15:14:06)
> > On Tue, Sep 04, 2018 at 11:20:04AM +0100, Chris Wilson wrote:
> > > Our unclaimed mmio access debugging is lazy, doing cheap checks
> > > periodically and only if they fail do a full check around every mmio
> > > access. When testing for runtime pm, enable the full mmio debugging from
> > > the initial load.
> > > 
> > > Signed-off-by: Chris Wilson 
> > > Cc: Imre Deak 
> > > ---
> > >  tests/pm_rpm.c | 7 +--
> > >  1 file changed, 5 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/tests/pm_rpm.c b/tests/pm_rpm.c
> > > index e3bb6227a..91aef0889 100644
> > > --- a/tests/pm_rpm.c
> > > +++ b/tests/pm_rpm.c
> > > @@ -2058,7 +2058,7 @@ int main(int argc, char *argv[])
> > >   igt_subtest("module-reload") {
> > >   igt_debug("Reload w/o display\n");
> > >   igt_i915_driver_unload();
> > > - igt_assert_eq(igt_i915_driver_load("disable_display=1"), 0);
> > > + igt_assert_eq(igt_i915_driver_load("disable_display=1 
> > > mmio_debug=2147483647"), 0);
> > >  
> > >   igt_assert(setup_environment());
> > >   igt_assert(igt_wait(device_in_pci_d3(), 2000, 100));
> > > @@ -2066,13 +2066,16 @@ int main(int argc, char *argv[])
> > >  
> > >   igt_debug("Reload as normal\n");
> > >   igt_i915_driver_unload();
> > > - igt_assert_eq(igt_i915_driver_load(NULL), 0);
> > > + 
> > > igt_assert_eq(igt_i915_driver_load("mmio_debug=2147483647"), 0);
> > 
> > Could've been in hex.
> -1 should work as well as INT_MAX, I was just a bit dubious about that
> claim at the time. But the kernel looks to be happy enough to start
> counting down from -1.
> 
> > >   igt_assert(setup_environment());
> > >   igt_assert(igt_wait(device_in_pci_d3(), 2000, 100));
> > >   if (enable_one_screen_with_type(&ms_data, SCREEN_TYPE_ANY))
> > >   drm_resources_equal_subtest();
> > >   teardown_environment();
> > > +
> > > + /* Remove our mmio_debugging module */
> > > + igt_i915_driver_unload();
> > 
> > What loads it again?
> 
> We automatically load it upon a failed drm_driver_open(). We have a list
> of modules to try and modprobe if we find no matching /dev/dri/* fd.

Ok, missed that. Looks ok:
Reviewed-by: Imre Deak 

> -Chris
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Double check we didn't miss an unclaimed register access

[Patchwork]

== Series Details ==

Series: drm/i915: Double check we didn't miss an unclaimed register access
URL   : https://patchwork.freedesktop.org/series/49121/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4763_full -> Patchwork_10079_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_10079_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10079_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

== Possible new issues ==

  Here are the unknown changes that may have been introduced in 
Patchwork_10079_full:

  === IGT changes ===

 Warnings 

igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack:
  shard-snb:  SKIP -> PASS

igt@pm_rc6_residency@rc6-accuracy:
  shard-kbl:  PASS -> SKIP


== Known issues ==

  Here are the changes found in Patchwork_10079_full that come from known 
issues:

  === IGT changes ===

 Issues hit 

igt@gem_exec_schedule@pi-ringfull-bsd2:
  shard-kbl:  NOTRUN -> FAIL (fdo#103158)

igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-plflip-blt:
  shard-glk:  PASS -> FAIL (fdo#103167)

igt@perf@polling:
  shard-hsw:  PASS -> FAIL (fdo#102252)


 Possible fixes 

igt@gem_ppgtt@blt-vs-render-ctxn:
  shard-kbl:  INCOMPLETE (fdo#106023, fdo#103665) -> PASS

igt@kms_setmode@basic:
  shard-kbl:  FAIL (fdo#99912) -> PASS


  fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
  fdo#103158 https://bugs.freedesktop.org/show_bug.cgi?id=103158
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (5 -> 5) ==

  No changes in participating hosts


== Build changes ==

* Linux: CI_DRM_4763 -> Patchwork_10079

  CI_DRM_4763: 1f8c06844acac7a349fb80471afcc09f33c6cfc0 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4622: 022be555443eaa3317da6a9a451cf2c9dfcd6ab8 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10079: 905bbb627b514b8a80e0788139f6ba46c8baed0e @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ 
git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10079/shards.html
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Re: [Intel-gfx] [PATCH] drm/i915: optimzie eDP 1.4 config

[Chris Wilson]

Quoting Lee, Shawn C (2018-09-04 15:55:41)
> eDP 1.4 introduce a new link rates flexibility and selection.
> It provided system specific link rate optimization and power
> efficiency. We should keep eDP 1.3 and older version to use
> max link rate approach to avoid any side effect. And eDP 1.4
> used the optimization link rate and lane count setting.
> 
> Cc: Matt Atwood 
> Signed-off-by: Lee, Shawn C 
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 6 --
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 436c22de33b6..903d640fe712 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1953,8 +1953,10 @@ intel_dp_compute_link_config(struct intel_encoder 
> *encoder,
>  * configuration, and typically these values correspond to the
>  * native resolution of the panel.
>  */

Having just finished a comment explaining why we override the limits for
eDP, the following logic is confusing without at least a mention above.

> -   limits.min_lane_count = limits.max_lane_count;
> -   limits.min_clock = limits.max_clock;
> +   if (intel_dp->edp_dpcd[0] <= DP_EDP_13) {
> +   limits.min_lane_count = limits.max_lane_count;
> +   limits.min_clock = limits.max_clock;
> +   }
> }
>  
> intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
> -- 
> 2.7.4
> 
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[Intel-gfx] [PATCH] drm/i915: optimzie eDP 1.4 config

[Lee, Shawn C]

eDP 1.4 introduce a new link rates flexibility and selection.
It provided system specific link rate optimization and power
efficiency. We should keep eDP 1.3 and older version to use
max link rate approach to avoid any side effect. And eDP 1.4
used the optimization link rate and lane count setting.

Cc: Matt Atwood 
Signed-off-by: Lee, Shawn C 
---
 drivers/gpu/drm/i915/intel_dp.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 436c22de33b6..903d640fe712 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1953,8 +1953,10 @@ intel_dp_compute_link_config(struct intel_encoder 
*encoder,
 * configuration, and typically these values correspond to the
 * native resolution of the panel.
 */
-   limits.min_lane_count = limits.max_lane_count;
-   limits.min_clock = limits.max_clock;
+   if (intel_dp->edp_dpcd[0] <= DP_EDP_13) {
+   limits.min_lane_count = limits.max_lane_count;
+   limits.min_clock = limits.max_clock;
+   }
}
 
intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
-- 
2.7.4

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Re: [Intel-gfx] [PATCH i-g-t] lib/pm_rpm: Reload the module with full mmio debugging

[Chris Wilson]

Quoting Imre Deak (2018-09-04 15:14:06)
> On Tue, Sep 04, 2018 at 11:20:04AM +0100, Chris Wilson wrote:
> > Our unclaimed mmio access debugging is lazy, doing cheap checks
> > periodically and only if they fail do a full check around every mmio
> > access. When testing for runtime pm, enable the full mmio debugging from
> > the initial load.
> > 
> > Signed-off-by: Chris Wilson 
> > Cc: Imre Deak 
> > ---
> >  tests/pm_rpm.c | 7 +--
> >  1 file changed, 5 insertions(+), 2 deletions(-)
> > 
> > diff --git a/tests/pm_rpm.c b/tests/pm_rpm.c
> > index e3bb6227a..91aef0889 100644
> > --- a/tests/pm_rpm.c
> > +++ b/tests/pm_rpm.c
> > @@ -2058,7 +2058,7 @@ int main(int argc, char *argv[])
> >   igt_subtest("module-reload") {
> >   igt_debug("Reload w/o display\n");
> >   igt_i915_driver_unload();
> > - igt_assert_eq(igt_i915_driver_load("disable_display=1"), 0);
> > + igt_assert_eq(igt_i915_driver_load("disable_display=1 
> > mmio_debug=2147483647"), 0);
> >  
> >   igt_assert(setup_environment());
> >   igt_assert(igt_wait(device_in_pci_d3(), 2000, 100));
> > @@ -2066,13 +2066,16 @@ int main(int argc, char *argv[])
> >  
> >   igt_debug("Reload as normal\n");
> >   igt_i915_driver_unload();
> > - igt_assert_eq(igt_i915_driver_load(NULL), 0);
> > + igt_assert_eq(igt_i915_driver_load("mmio_debug=2147483647"), 
> > 0);
> 
> Could've been in hex.
-1 should work as well as INT_MAX, I was just a bit dubious about that
claim at the time. But the kernel looks to be happy enough to start
counting down from -1.

> >   igt_assert(setup_environment());
> >   igt_assert(igt_wait(device_in_pci_d3(), 2000, 100));
> >   if (enable_one_screen_with_type(&ms_data, SCREEN_TYPE_ANY))
> >   drm_resources_equal_subtest();
> >   teardown_environment();
> > +
> > + /* Remove our mmio_debugging module */
> > + igt_i915_driver_unload();
> 
> What loads it again?

We automatically load it upon a failed drm_driver_open(). We have a list
of modules to try and modprobe if we find no matching /dev/dri/* fd.
-Chris
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Re: [Intel-gfx] [PATCH 14/14] drm/vmwgfx: Add FIXME comments for customer page_flip handlers

[Daniel Vetter]

On Tue, Sep 4, 2018 at 3:45 PM, Thomas Hellstrom  wrote:
> On 09/03/2018 06:54 PM, Daniel Vetter wrote:
>>
>> The idea behind allowing drivers to override legacy ioctls (instead of
>> using the generic implementations unconditionally) is to handle bugs
>> in old driver-specific userspace. Like e.g. vmw_kms_set_config does,
>> to work around some vmwgfx userspace not clearing its ioctl structs
>> properly.
>>
>> But you can't use it to augment semantics and put in additional
>> checks, since from a correctly working userspace's pov there should
>> not be any difference in behaviour between the legacy and the atomic
>> paths.
>>
>> vmwgfx seems to be doing some strange things in its page_flip
>> handlers. Since I'm not an expert of this codebase just wrap some
>> FIXME comments around the potentially problematic code.
>>
> Thanks for the patch, Daniel
>
> Your comments seem valid. We'll try to fix this internally before the next
> merge window rather than to add the FIXMEs

Sounds all good to me. And if you have questions I'm happy to help out
(and use that generally as an opportunity to improve the docs).

Thanks, Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH i-g-t] lib/pm_rpm: Reload the module with full mmio debugging

[Imre Deak]

On Tue, Sep 04, 2018 at 11:20:04AM +0100, Chris Wilson wrote:
> Our unclaimed mmio access debugging is lazy, doing cheap checks
> periodically and only if they fail do a full check around every mmio
> access. When testing for runtime pm, enable the full mmio debugging from
> the initial load.
> 
> Signed-off-by: Chris Wilson 
> Cc: Imre Deak 
> ---
>  tests/pm_rpm.c | 7 +--
>  1 file changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/tests/pm_rpm.c b/tests/pm_rpm.c
> index e3bb6227a..91aef0889 100644
> --- a/tests/pm_rpm.c
> +++ b/tests/pm_rpm.c
> @@ -2058,7 +2058,7 @@ int main(int argc, char *argv[])
>   igt_subtest("module-reload") {
>   igt_debug("Reload w/o display\n");
>   igt_i915_driver_unload();
> - igt_assert_eq(igt_i915_driver_load("disable_display=1"), 0);
> + igt_assert_eq(igt_i915_driver_load("disable_display=1 
> mmio_debug=2147483647"), 0);
>  
>   igt_assert(setup_environment());
>   igt_assert(igt_wait(device_in_pci_d3(), 2000, 100));
> @@ -2066,13 +2066,16 @@ int main(int argc, char *argv[])
>  
>   igt_debug("Reload as normal\n");
>   igt_i915_driver_unload();
> - igt_assert_eq(igt_i915_driver_load(NULL), 0);
> + igt_assert_eq(igt_i915_driver_load("mmio_debug=2147483647"), 0);

Could've been in hex.

>  
>   igt_assert(setup_environment());
>   igt_assert(igt_wait(device_in_pci_d3(), 2000, 100));
>   if (enable_one_screen_with_type(&ms_data, SCREEN_TYPE_ANY))
>   drm_resources_equal_subtest();
>   teardown_environment();
> +
> + /* Remove our mmio_debugging module */
> + igt_i915_driver_unload();

What loads it again?

>   }
>  
>   igt_exit();
> -- 
> 2.19.0.rc1
> 
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Re: [Intel-gfx] [PATCH v9 2/2] drm/i915: Adding YUV444 packed format support for skl+

[Ville Syrjälä]

On Tue, Sep 04, 2018 at 03:52:51PM +0200, Maarten Lankhorst wrote:
> Op 04-09-18 om 15:50 schreef Ville Syrjälä:
> > On Tue, Sep 04, 2018 at 02:47:51PM +0200, Maarten Lankhorst wrote:
> >> Op 30-08-18 om 16:24 schreef Stanislav Lisovskiy:
> >>> PLANE_CTL_FORMAT_AYUV is already supported, according to hardware
> >>> specification.
> >>>
> >>> v2: Edited commit message, removed redundant whitespaces.
> >>>
> >>> v3: Fixed fallthrough logic for the format switch cases.
> >>>
> >>> v4: Yet again fixed fallthrough logic, to reuse code from other case
> >>> labels.
> >>>
> >>> v5: Started to use XYUV instead of AYUV, as we don't use alpha.
> >>>
> >>> v6: Removed unneeded initializer for new XYUV format.
> >>>
> >>> v7: Added scaling support for DRM_FORMAT_XYUV
> >>>
> >>> v8: Edited commit message to be more clear about skl+, renamed
> >>> PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this format
> >>> doesn't support per-pixel alpha. Fixed minor code issues.
> >>>
> >>> v9: Moved DRM format check to proper place in intel_framebuffer_init.
> >>>
> >>> Signed-off-by: Stanislav Lisovskiy 
> >>> ---
> >>>  drivers/gpu/drm/i915/i915_reg.h  |  2 +-
> >>>  drivers/gpu/drm/i915/intel_display.c | 15 +++
> >>>  drivers/gpu/drm/i915/intel_sprite.c  |  1 +
> >>>  3 files changed, 17 insertions(+), 1 deletion(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/i915_reg.h 
> >>> b/drivers/gpu/drm/i915/i915_reg.h
> >>> index 8534f88a60f6..e0c8480aaa02 100644
> >>> --- a/drivers/gpu/drm/i915/i915_reg.h
> >>> +++ b/drivers/gpu/drm/i915/i915_reg.h
> >>> @@ -6499,7 +6499,7 @@ enum {
> >>>  #define   PLANE_CTL_FORMAT_XRGB_2101010  (2 << 24)
> >>>  #define   PLANE_CTL_FORMAT_XRGB_ (4 << 24)
> >>>  #define   PLANE_CTL_FORMAT_XRGB_16161616F(6 << 24)
> >>> -#define   PLANE_CTL_FORMAT_AYUV  (8 << 24)
> >>> +#define   PLANE_CTL_FORMAT_XYUV  (8 << 24)
> >>>  #define   PLANE_CTL_FORMAT_INDEXED   (12 << 24)
> >>>  #define   PLANE_CTL_FORMAT_RGB_565   (14 << 24)
> >>>  #define   ICL_PLANE_CTL_FORMAT_MASK  (0x1f << 23)
> >>> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> >>> b/drivers/gpu/drm/i915/intel_display.c
> >>> index 30fdfd1a3037..9323708db71f 100644
> >>> --- a/drivers/gpu/drm/i915/intel_display.c
> >>> +++ b/drivers/gpu/drm/i915/intel_display.c
> >>> @@ -86,6 +86,7 @@ static const uint32_t skl_primary_formats[] = {
> >>>   DRM_FORMAT_YVYU,
> >>>   DRM_FORMAT_UYVY,
> >>>   DRM_FORMAT_VYUY,
> >>> + DRM_FORMAT_XYUV,
> >>>  };
> >>>  
> >>>  static const uint32_t skl_pri_planar_formats[] = {
> >>> @@ -101,6 +102,7 @@ static const uint32_t skl_pri_planar_formats[] = {
> >>>   DRM_FORMAT_YVYU,
> >>>   DRM_FORMAT_UYVY,
> >>>   DRM_FORMAT_VYUY,
> >>> + DRM_FORMAT_XYUV,
> >>>   DRM_FORMAT_NV12,
> >>>  };
> >>>  
> >>> @@ -2672,6 +2674,8 @@ int skl_format_to_fourcc(int format, bool 
> >>> rgb_order, bool alpha)
> >>>   return DRM_FORMAT_RGB565;
> >>>   case PLANE_CTL_FORMAT_NV12:
> >>>   return DRM_FORMAT_NV12;
> >>> + case PLANE_CTL_FORMAT_XYUV:
> >>> + return DRM_FORMAT_XYUV;
> >>>   default:
> >>>   case PLANE_CTL_FORMAT_XRGB_:
> >>>   if (rgb_order) {
> >>> @@ -3501,6 +3505,8 @@ static u32 skl_plane_ctl_format(uint32_t 
> >>> pixel_format)
> >>>   return PLANE_CTL_FORMAT_XRGB_2101010;
> >>>   case DRM_FORMAT_XBGR2101010:
> >>>   return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
> >>> + case DRM_FORMAT_XYUV:
> >>> + return PLANE_CTL_FORMAT_XYUV;
> >>>   case DRM_FORMAT_YUYV:
> >>>   return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
> >>>   case DRM_FORMAT_YVYU:
> >>> @@ -4959,6 +4965,7 @@ static int skl_update_scaler_plane(struct 
> >>> intel_crtc_state *crtc_state,
> >>>   case DRM_FORMAT_UYVY:
> >>>   case DRM_FORMAT_VYUY:
> >>>   case DRM_FORMAT_NV12:
> >>> + case DRM_FORMAT_XYUV:
> >>>   break;
> >>>   default:
> >>>   DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 
> >>> 0x%x\n",
> >>> @@ -13414,6 +13421,7 @@ static bool skl_plane_format_mod_supported(struct 
> >>> drm_plane *_plane,
> >>>   case DRM_FORMAT_UYVY:
> >>>   case DRM_FORMAT_VYUY:
> >>>   case DRM_FORMAT_NV12:
> >>> + case DRM_FORMAT_XYUV:
> >>>   if (modifier == I915_FORMAT_MOD_Yf_TILED)
> >>>   return true;
> >>>   /* fall through */
> >>> @@ -14540,6 +14548,13 @@ static int intel_framebuffer_init(struct 
> >>> intel_framebuffer *intel_fb,
> >>>   goto err;
> >>>   }
> >>>   break;
> >>> + case DRM_FORMAT_XYUV:
> >>> + if (INTEL_GEN(dev_priv) < 9) {
> >>> + DRM_DEBUG_KMS("unsupported pixel format: %s\n",
> >>> +   
> >>> drm_get_format_name(mode_cmd->pixel_format, &format_name));
> >>> + goto err;
> >>> + }
> >>> + break;
> >> This hunk isn't needed. DRM core rejects any format

[Intel-gfx] ✗ Fi.CI.IGT: failure for Add XYUV format support (rev5)

[Patchwork]

== Series Details ==

Series: Add XYUV format support (rev5)
URL   : https://patchwork.freedesktop.org/series/48007/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4763_full -> Patchwork_10078_full =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_10078_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10078_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

== Possible new issues ==

  Here are the unknown changes that may have been introduced in 
Patchwork_10078_full:

  === IGT changes ===

 Possible regressions 

igt@kms_available_modes_crc@available_mode_test_crc:
  shard-apl:  PASS -> FAIL


 Warnings 

igt@kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack:
  shard-snb:  SKIP -> PASS


== Known issues ==

  Here are the changes found in Patchwork_10078_full that come from known 
issues:

  === IGT changes ===

 Issues hit 

igt@kms_cursor_legacy@cursor-vs-flip-toggle:
  shard-hsw:  PASS -> FAIL (fdo#103355)

igt@kms_flip@flip-vs-expired-vblank-interruptible:
  shard-glk:  PASS -> FAIL (fdo#102887, fdo#105363)

igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-plflip-blt:
  shard-glk:  PASS -> FAIL (fdo#103167)


  fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103355 https://bugs.freedesktop.org/show_bug.cgi?id=103355
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363


== Participating hosts (5 -> 5) ==

  No changes in participating hosts


== Build changes ==

* Linux: CI_DRM_4763 -> Patchwork_10078

  CI_DRM_4763: 1f8c06844acac7a349fb80471afcc09f33c6cfc0 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4622: 022be555443eaa3317da6a9a451cf2c9dfcd6ab8 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10078: 5c8a6f919689dd4a640ddadc5ba8c0ce07025a45 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ 
git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10078/shards.html
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Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] lib/pm: Increase snd module probe timeout to 10s

[Imre Deak]

On Tue, Sep 04, 2018 at 11:19:38AM +0100, Chris Wilson wrote:
> 5s is often not enough for the sound module to finish loading, so bump
> the timeout to 10s. For fun, poll quicker over the 1s!
> 
> Signed-off-by: Chris Wilson 
> Cc: Imre Deak 

Reviewed-by: Imre Deak 

> ---
>  lib/igt_pm.c | 7 +--
>  1 file changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/lib/igt_pm.c b/lib/igt_pm.c
> index e86fa4a40..615463a08 100644
> --- a/lib/igt_pm.c
> +++ b/lib/igt_pm.c
> @@ -258,12 +258,15 @@ void igt_pm_enable_audio_runtime_pm(void)
>   if (__igt_pm_audio_runtime_power_save[0])
>   return;
>  
> - for (int count = 0; count < 5; count++) {
> + for (int count = 0; count < 110; count++) {
>   if (!__igt_pm_enable_audio_runtime_pm())
>   return;
>  
>   /* modprobe(sna-hda-intel) acts async so poll for sysfs */
> - sleep(1);
> + if (count < 100)
> + usleep(10 * 1000); /* poll at 10ms for the first 1s */
> + else
> + sleep(1);
>   }
>  
>   err = __igt_pm_enable_audio_runtime_pm();
> -- 
> 2.19.0.rc1
> 
> ___
> igt-dev mailing list
> igt-...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
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Re: [Intel-gfx] [PATCH v9 2/2] drm/i915: Adding YUV444 packed format support for skl+

[Maarten Lankhorst]

Op 04-09-18 om 15:50 schreef Ville Syrjälä:
> On Tue, Sep 04, 2018 at 02:47:51PM +0200, Maarten Lankhorst wrote:
>> Op 30-08-18 om 16:24 schreef Stanislav Lisovskiy:
>>> PLANE_CTL_FORMAT_AYUV is already supported, according to hardware
>>> specification.
>>>
>>> v2: Edited commit message, removed redundant whitespaces.
>>>
>>> v3: Fixed fallthrough logic for the format switch cases.
>>>
>>> v4: Yet again fixed fallthrough logic, to reuse code from other case
>>> labels.
>>>
>>> v5: Started to use XYUV instead of AYUV, as we don't use alpha.
>>>
>>> v6: Removed unneeded initializer for new XYUV format.
>>>
>>> v7: Added scaling support for DRM_FORMAT_XYUV
>>>
>>> v8: Edited commit message to be more clear about skl+, renamed
>>> PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this format
>>> doesn't support per-pixel alpha. Fixed minor code issues.
>>>
>>> v9: Moved DRM format check to proper place in intel_framebuffer_init.
>>>
>>> Signed-off-by: Stanislav Lisovskiy 
>>> ---
>>>  drivers/gpu/drm/i915/i915_reg.h  |  2 +-
>>>  drivers/gpu/drm/i915/intel_display.c | 15 +++
>>>  drivers/gpu/drm/i915/intel_sprite.c  |  1 +
>>>  3 files changed, 17 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h 
>>> b/drivers/gpu/drm/i915/i915_reg.h
>>> index 8534f88a60f6..e0c8480aaa02 100644
>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>> @@ -6499,7 +6499,7 @@ enum {
>>>  #define   PLANE_CTL_FORMAT_XRGB_2101010(2 << 24)
>>>  #define   PLANE_CTL_FORMAT_XRGB_   (4 << 24)
>>>  #define   PLANE_CTL_FORMAT_XRGB_16161616F  (6 << 24)
>>> -#define   PLANE_CTL_FORMAT_AYUV(8 << 24)
>>> +#define   PLANE_CTL_FORMAT_XYUV(8 << 24)
>>>  #define   PLANE_CTL_FORMAT_INDEXED (12 << 24)
>>>  #define   PLANE_CTL_FORMAT_RGB_565 (14 << 24)
>>>  #define   ICL_PLANE_CTL_FORMAT_MASK(0x1f << 23)
>>> diff --git a/drivers/gpu/drm/i915/intel_display.c 
>>> b/drivers/gpu/drm/i915/intel_display.c
>>> index 30fdfd1a3037..9323708db71f 100644
>>> --- a/drivers/gpu/drm/i915/intel_display.c
>>> +++ b/drivers/gpu/drm/i915/intel_display.c
>>> @@ -86,6 +86,7 @@ static const uint32_t skl_primary_formats[] = {
>>> DRM_FORMAT_YVYU,
>>> DRM_FORMAT_UYVY,
>>> DRM_FORMAT_VYUY,
>>> +   DRM_FORMAT_XYUV,
>>>  };
>>>  
>>>  static const uint32_t skl_pri_planar_formats[] = {
>>> @@ -101,6 +102,7 @@ static const uint32_t skl_pri_planar_formats[] = {
>>> DRM_FORMAT_YVYU,
>>> DRM_FORMAT_UYVY,
>>> DRM_FORMAT_VYUY,
>>> +   DRM_FORMAT_XYUV,
>>> DRM_FORMAT_NV12,
>>>  };
>>>  
>>> @@ -2672,6 +2674,8 @@ int skl_format_to_fourcc(int format, bool rgb_order, 
>>> bool alpha)
>>> return DRM_FORMAT_RGB565;
>>> case PLANE_CTL_FORMAT_NV12:
>>> return DRM_FORMAT_NV12;
>>> +   case PLANE_CTL_FORMAT_XYUV:
>>> +   return DRM_FORMAT_XYUV;
>>> default:
>>> case PLANE_CTL_FORMAT_XRGB_:
>>> if (rgb_order) {
>>> @@ -3501,6 +3505,8 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
>>> return PLANE_CTL_FORMAT_XRGB_2101010;
>>> case DRM_FORMAT_XBGR2101010:
>>> return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
>>> +   case DRM_FORMAT_XYUV:
>>> +   return PLANE_CTL_FORMAT_XYUV;
>>> case DRM_FORMAT_YUYV:
>>> return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
>>> case DRM_FORMAT_YVYU:
>>> @@ -4959,6 +4965,7 @@ static int skl_update_scaler_plane(struct 
>>> intel_crtc_state *crtc_state,
>>> case DRM_FORMAT_UYVY:
>>> case DRM_FORMAT_VYUY:
>>> case DRM_FORMAT_NV12:
>>> +   case DRM_FORMAT_XYUV:
>>> break;
>>> default:
>>> DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 
>>> 0x%x\n",
>>> @@ -13414,6 +13421,7 @@ static bool skl_plane_format_mod_supported(struct 
>>> drm_plane *_plane,
>>> case DRM_FORMAT_UYVY:
>>> case DRM_FORMAT_VYUY:
>>> case DRM_FORMAT_NV12:
>>> +   case DRM_FORMAT_XYUV:
>>> if (modifier == I915_FORMAT_MOD_Yf_TILED)
>>> return true;
>>> /* fall through */
>>> @@ -14540,6 +14548,13 @@ static int intel_framebuffer_init(struct 
>>> intel_framebuffer *intel_fb,
>>> goto err;
>>> }
>>> break;
>>> +   case DRM_FORMAT_XYUV:
>>> +   if (INTEL_GEN(dev_priv) < 9) {
>>> +   DRM_DEBUG_KMS("unsupported pixel format: %s\n",
>>> + 
>>> drm_get_format_name(mode_cmd->pixel_format, &format_name));
>>> +   goto err;
>>> +   }
>>> +   break;
>> This hunk isn't needed. DRM core rejects any formats not in the format 
>> arrays.
> There is no formats array for addfb. My patches to elimintate this ugly
> code by cross checking with every plane got stuck in limbo.
>
Link?

Lets fix that.

_

Re: [Intel-gfx] [PATCH v9 2/2] drm/i915: Adding YUV444 packed format support for skl+

[Ville Syrjälä]

On Tue, Sep 04, 2018 at 02:47:51PM +0200, Maarten Lankhorst wrote:
> Op 30-08-18 om 16:24 schreef Stanislav Lisovskiy:
> > PLANE_CTL_FORMAT_AYUV is already supported, according to hardware
> > specification.
> >
> > v2: Edited commit message, removed redundant whitespaces.
> >
> > v3: Fixed fallthrough logic for the format switch cases.
> >
> > v4: Yet again fixed fallthrough logic, to reuse code from other case
> > labels.
> >
> > v5: Started to use XYUV instead of AYUV, as we don't use alpha.
> >
> > v6: Removed unneeded initializer for new XYUV format.
> >
> > v7: Added scaling support for DRM_FORMAT_XYUV
> >
> > v8: Edited commit message to be more clear about skl+, renamed
> > PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this format
> > doesn't support per-pixel alpha. Fixed minor code issues.
> >
> > v9: Moved DRM format check to proper place in intel_framebuffer_init.
> >
> > Signed-off-by: Stanislav Lisovskiy 
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h  |  2 +-
> >  drivers/gpu/drm/i915/intel_display.c | 15 +++
> >  drivers/gpu/drm/i915/intel_sprite.c  |  1 +
> >  3 files changed, 17 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h 
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 8534f88a60f6..e0c8480aaa02 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -6499,7 +6499,7 @@ enum {
> >  #define   PLANE_CTL_FORMAT_XRGB_2101010(2 << 24)
> >  #define   PLANE_CTL_FORMAT_XRGB_   (4 << 24)
> >  #define   PLANE_CTL_FORMAT_XRGB_16161616F  (6 << 24)
> > -#define   PLANE_CTL_FORMAT_AYUV(8 << 24)
> > +#define   PLANE_CTL_FORMAT_XYUV(8 << 24)
> >  #define   PLANE_CTL_FORMAT_INDEXED (12 << 24)
> >  #define   PLANE_CTL_FORMAT_RGB_565 (14 << 24)
> >  #define   ICL_PLANE_CTL_FORMAT_MASK(0x1f << 23)
> > diff --git a/drivers/gpu/drm/i915/intel_display.c 
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 30fdfd1a3037..9323708db71f 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -86,6 +86,7 @@ static const uint32_t skl_primary_formats[] = {
> > DRM_FORMAT_YVYU,
> > DRM_FORMAT_UYVY,
> > DRM_FORMAT_VYUY,
> > +   DRM_FORMAT_XYUV,
> >  };
> >  
> >  static const uint32_t skl_pri_planar_formats[] = {
> > @@ -101,6 +102,7 @@ static const uint32_t skl_pri_planar_formats[] = {
> > DRM_FORMAT_YVYU,
> > DRM_FORMAT_UYVY,
> > DRM_FORMAT_VYUY,
> > +   DRM_FORMAT_XYUV,
> > DRM_FORMAT_NV12,
> >  };
> >  
> > @@ -2672,6 +2674,8 @@ int skl_format_to_fourcc(int format, bool rgb_order, 
> > bool alpha)
> > return DRM_FORMAT_RGB565;
> > case PLANE_CTL_FORMAT_NV12:
> > return DRM_FORMAT_NV12;
> > +   case PLANE_CTL_FORMAT_XYUV:
> > +   return DRM_FORMAT_XYUV;
> > default:
> > case PLANE_CTL_FORMAT_XRGB_:
> > if (rgb_order) {
> > @@ -3501,6 +3505,8 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
> > return PLANE_CTL_FORMAT_XRGB_2101010;
> > case DRM_FORMAT_XBGR2101010:
> > return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
> > +   case DRM_FORMAT_XYUV:
> > +   return PLANE_CTL_FORMAT_XYUV;
> > case DRM_FORMAT_YUYV:
> > return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
> > case DRM_FORMAT_YVYU:
> > @@ -4959,6 +4965,7 @@ static int skl_update_scaler_plane(struct 
> > intel_crtc_state *crtc_state,
> > case DRM_FORMAT_UYVY:
> > case DRM_FORMAT_VYUY:
> > case DRM_FORMAT_NV12:
> > +   case DRM_FORMAT_XYUV:
> > break;
> > default:
> > DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 
> > 0x%x\n",
> > @@ -13414,6 +13421,7 @@ static bool skl_plane_format_mod_supported(struct 
> > drm_plane *_plane,
> > case DRM_FORMAT_UYVY:
> > case DRM_FORMAT_VYUY:
> > case DRM_FORMAT_NV12:
> > +   case DRM_FORMAT_XYUV:
> > if (modifier == I915_FORMAT_MOD_Yf_TILED)
> > return true;
> > /* fall through */
> > @@ -14540,6 +14548,13 @@ static int intel_framebuffer_init(struct 
> > intel_framebuffer *intel_fb,
> > goto err;
> > }
> > break;
> > +   case DRM_FORMAT_XYUV:
> > +   if (INTEL_GEN(dev_priv) < 9) {
> > +   DRM_DEBUG_KMS("unsupported pixel format: %s\n",
> > + 
> > drm_get_format_name(mode_cmd->pixel_format, &format_name));
> > +   goto err;
> > +   }
> > +   break;
> This hunk isn't needed. DRM core rejects any formats not in the format arrays.

There is no formats array for addfb. My patches to elimintate this ugly
code by cross checking with every plane got stuck in limbo.

-- 
Ville Syrjälä
Intel
-
Intel Finland 

Re: [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/icl: Fix context RPCS programming (rev2)

[Tvrtko Ursulin]

On 03/09/2018 13:53, Patchwork wrote:

== Series Details ==

Series: drm/i915/icl: Fix context RPCS programming (rev2)
URL   : https://patchwork.freedesktop.org/series/49005/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4757 -> Patchwork_10070 =

== Summary - SUCCESS ==

   No regressions found.

   External URL: 
https://patchwork.freedesktop.org/api/1.0/series/49005/revisions/2/mbox/

== Possible new issues ==

   Here are the unknown changes that may have been introduced in 
Patchwork_10070:

   === IGT changes ===

  Warnings 

 {igt@pm_rpm@module-reload}:
   fi-hsw-4770r:   PASS -> SKIP

 
== Known issues ==


   Here are the changes found in Patchwork_10070 that come from known issues:

   === IGT changes ===

  Issues hit 

 igt@drv_module_reload@basic-reload-inject:
   fi-hsw-4770r:   PASS -> DMESG-WARN (fdo#107425)

 {igt@pm_rpm@module-reload}:
   fi-cnl-psr: PASS -> WARN (fdo#107708, fdo#107602)

 
  Possible fixes 


 igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence:
   {fi-byt-clapper}:   FAIL (fdo#103191, fdo#107362) -> PASS

 igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
   fi-bxt-dsi: INCOMPLETE (fdo#103927) -> PASS

 igt@kms_psr@primary_page_flip:
   fi-cnl-psr: FAIL (fdo#107336) -> PASS

 
   {name}: This element is suppressed. This means it is ignored when computing

   the status of the difference (SUCCESS, WARNING, or FAILURE).

   fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
   fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
   fdo#107336 https://bugs.freedesktop.org/show_bug.cgi?id=107336
   fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
   fdo#107425 https://bugs.freedesktop.org/show_bug.cgi?id=107425
   fdo#107602 https://bugs.freedesktop.org/show_bug.cgi?id=107602
   fdo#107708 https://bugs.freedesktop.org/show_bug.cgi?id=107708


== Participating hosts (53 -> 48) ==

   Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan 
fi-hsw-4200u


== Build changes ==

 * Linux: CI_DRM_4757 -> Patchwork_10070

   CI_DRM_4757: 1465de895e2b5d9e74e9a85189c9075155efa30d @ 
git://anongit.freedesktop.org/gfx-ci/linux
   IGT_4621: 125eee6e981eac0a004aeb4f327439a132ceac5c @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
   Patchwork_10070: 9a2751c01ca21789da2a8f95dab23033540ad6c9 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

9a2751c01ca2 drm/i915/icl: Fix context RPCS programming


Pushed, thanks for the review!

Regards,

Tvrtko

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Re: [Intel-gfx] [PATCH i-g-t] igt/pm_rps: Clear previous high load on high->low transition

[Katarzyna Dec]

On Tue, Sep 04, 2018 at 01:49:56PM +0100, Chris Wilson wrote:
> Make sure we do flush out the previous spinner and delay signaling
> transition completion until we do.
> 
> References: https://bugs.freedesktop.org/show_bug.cgi?id=102250
> Signed-off-by: Chris Wilson 
> Cc: Katarzyna Dec 
> ---
>  tests/pm_rps.c | 26 +-
>  1 file changed, 21 insertions(+), 5 deletions(-)
> 
> diff --git a/tests/pm_rps.c b/tests/pm_rps.c
> index 84e71fa8a..23b33f41b 100644
> --- a/tests/pm_rps.c
> +++ b/tests/pm_rps.c
> @@ -218,6 +218,7 @@ static void load_helper_set_load(enum load load)
>  
>  static void load_helper_run(enum load load)
>  {
> + bool dummy;
>   int link[2];
>  
>   /*
> @@ -233,13 +234,14 @@ static void load_helper_run(enum load load)
>  
>   lh.exit = false;
>   lh.load = load;
> - lh.signal = false;
> + lh.signal = true;
>  
>   pipe(link);
>   lh.link = link[1];
>  
>   igt_fork_helper(&lh.igt_proc) {
>   igt_spin_t *spin[2] = {};
> + bool prev_load;
>   uint32_t handle;
>  
>   signal(SIGUSR1, load_helper_signal_handler);
> @@ -247,10 +249,14 @@ static void load_helper_run(enum load load)
>  
>   igt_debug("Applying %s load...\n", lh.load ? "high" : "low");
>  
> + prev_load = lh.load == HIGH;
I would add parenthesis to improve clarity: 
prev_load = (lh.load == HIGH);

Despite this:
Reviewed-by: Katarzyna Dec 
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Re: [Intel-gfx] [PATCH] drm/i915: Reduce context HW ID lifetime

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-09-03 10:59:01)
> 
> On 31/08/2018 13:36, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2018-08-30 17:23:43)
> >>
> >> On 30/08/2018 11:24, Chris Wilson wrote:
> >>> +static int assign_hw_id(struct drm_i915_private *i915, unsigned int *out)
> >>> +{
> >>> + int ret;
> >>> +
> >>> + lockdep_assert_held(&i915->contexts.mutex);
> >>> +
> >>> + ret = new_hw_id(i915, GFP_KERNEL | __GFP_RETRY_MAYFAIL | 
> >>> __GFP_NOWARN);
> >>> + if (unlikely(ret < 0)) {
> >>> + ret = steal_hw_id(i915);
> >>> + if (ret < 0) /* once again for the correct erro code */
> >>
> >> errno
> >>
> >>> + ret = new_hw_id(i915, GFP_KERNEL);
> >>
> >> Hmm.. shouldn't you try GFP_KERNEL before attempting to steal? Actually
> >> I think you should branch based on -ENOSPC (steal) vs -ENOMEM (retry
> >> with GFP_KERNEL). Which would actually mean something like:
> > 
> > I was applying the same strategy as we use elsewhere. Penalise any
> > driver cache before hitting reclaim.
> > 
> > I think that is fair from an application of soft backpressure point of
> > view. (Lack of backpressure is probably a sore point for many.)
> 
> My concern was lack of a phase which avoids hw id stealing for loads 
> with few contexts but heavy memory pressure. Sounded like a thing worth 
> "robustifying" against - you don't think so?

Do we care much at the point where we fail to direct reclaim a page for
the ida allocator?

It's a tough call, and I think erring on the side of the rest of the
system vs new requests is best overall in an enlightened self-interest
pov. I completely agree we can construct cases where giving up amounts
to priority-inversion and an unfortunate DoS of important clients, but
my gut feeling is that they typical desktop would remain more responsive
with i915 giving up first.

Thank goodness we are not RT.
-Chris
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Re: [Intel-gfx] [PATCH 14/14] drm/vmwgfx: Add FIXME comments for customer page_flip handlers

[Thomas Hellstrom]

On 09/03/2018 06:54 PM, Daniel Vetter wrote:

The idea behind allowing drivers to override legacy ioctls (instead of
using the generic implementations unconditionally) is to handle bugs
in old driver-specific userspace. Like e.g. vmw_kms_set_config does,
to work around some vmwgfx userspace not clearing its ioctl structs
properly.

But you can't use it to augment semantics and put in additional
checks, since from a correctly working userspace's pov there should
not be any difference in behaviour between the legacy and the atomic
paths.

vmwgfx seems to be doing some strange things in its page_flip
handlers. Since I'm not an expert of this codebase just wrap some
FIXME comments around the potentially problematic code.


Thanks for the patch, Daniel

Your comments seem valid. We'll try to fix this internally before the 
next merge window rather than to add the FIXMEs


/Thomas

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Re: [Intel-gfx] [PATCH] drm/i915: Double check we didn't miss an unclaimed register access

[Chris Wilson]

Quoting Mika Kuoppala (2018-09-04 13:56:07)
> Chris Wilson  writes:
> 
> > Quoting Chris Wilson (2018-09-04 13:38:27)
> >> Quoting Mika Kuoppala (2018-09-04 13:34:12)
> >> > Chris Wilson  writes:
> >> > 
> >> > > Currently, if the user has enabled mmio-debug around each register
> >> > > access, we presume that we have then checked them all. However, it is
> >> > > still possible through omission (raw register access) or external
> >> > > interaction that the unclaimed access was not highlighted.
> >> > >
> >> > > Signed-off-by: Chris Wilson 
> >> > > Cc: Mika Kuoppala 
> >> > > ---
> >> > >  drivers/gpu/drm/i915/intel_uncore.c | 13 +++--
> >> > >  1 file changed, 7 insertions(+), 6 deletions(-)
> >> > >
> >> > > diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
> >> > > b/drivers/gpu/drm/i915/intel_uncore.c
> >> > > index 20f2f5ad9c3f..05f0cda18501 100644
> >> > > --- a/drivers/gpu/drm/i915/intel_uncore.c
> >> > > +++ b/drivers/gpu/drm/i915/intel_uncore.c
> >> > > @@ -2283,15 +2283,16 @@ bool intel_uncore_unclaimed_mmio(struct 
> >> > > drm_i915_private *dev_priv)
> >> > >  bool
> >> > >  intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private 
> >> > > *dev_priv)
> >> > >  {
> >> > > - if (unlikely(i915_modparams.mmio_debug ||
> >> > > -  dev_priv->uncore.unclaimed_mmio_check <= 0))
> >> > > + if (unlikely(dev_priv->uncore.unclaimed_mmio_check <= 0))
> >> > >   return false;
> >> > >
> >> > 
> >> > We could catch the readers attention by marking this as READ_ONCE.
> >> > 
> >> > 
> >> > And then take spinlock here before checking for unclaimed.
> >> 
> >> Could do, feels like overkill, but not contentious.
> >
> > Implied here, is improving unclaimed_mmio_check a fundamental
> > requirement for this patch or additional work? I think the latter.
> 
> Additional work. Was just thinking aloud about the
> possible races in this area.
> 
> Patch does what it says.
> 
> Reviewed-by: Mika Kuoppala 

Plonked itin . When I remember, I'll rerun the mmio-debugging patch for
pm_rpm/module-reload and see what happens now.
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Re: [Intel-gfx] [PATCH] drm/i915: Pull intel_uncore_arm_unclaimed_mmio_detection() under the spinlock

[Mika Kuoppala]

Chris Wilson  writes:

> Elsewhere we manipulate uncore.unclaimed_mmio_check and
> i915_param.mmio_debug under the irq lock (e.g. preserving the current
> value across a user forcewake grab), but do not protect the manipulation
> inside intel_uncore_arm_unclaimed_mmio_detection() from concurrent
> access, even from itself. This is an issue as we do call
> arm_unclaimed_mmio_detection from multiple threads without coordination.
>
> Suggested-by: Mika Kuoppala 
> Signed-off-by: Chris Wilson 
> Cc: Mika Kuoppala 
> ---
>  drivers/gpu/drm/i915/intel_uncore.c | 13 ++---
>  1 file changed, 10 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
> b/drivers/gpu/drm/i915/intel_uncore.c
> index 05f0cda18501..3ad302c66254 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -2283,8 +2283,12 @@ bool intel_uncore_unclaimed_mmio(struct 
> drm_i915_private *dev_priv)
>  bool
>  intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv)
>  {
> + bool ret = false;
> +
> + spin_lock_irq(&dev_priv->uncore.lock);
> +
>   if (unlikely(dev_priv->uncore.unclaimed_mmio_check <= 0))
> - return false;
> + goto out;
>  
>   if (unlikely(intel_uncore_unclaimed_mmio(dev_priv))) {
>   if (!i915_modparams.mmio_debug) {
> @@ -2294,10 +2298,13 @@ intel_uncore_arm_unclaimed_mmio_detection(struct 
> drm_i915_private *dev_priv)
>   i915_modparams.mmio_debug++;
>   }
>   dev_priv->uncore.unclaimed_mmio_check--;
> - return true;
> + ret = true;
>   }
>  
> - return false;
> +out:
> + spin_unlock_irq(&dev_priv->uncore.lock);
> +
> + return ret;

Patchbot didn't see how the future will unfold. I did.

Reviewed-by: Mika Kuoppala 

>  }
>  
>  static enum forcewake_domains
> -- 
> 2.19.0.rc1
>
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Re: [Intel-gfx] [PATCH] drm/i915/ringbuffer: Move double invalidate to after pd flush

[Chris Wilson]

Quoting Mika Kuoppala (2018-09-04 14:22:17)
> Chris Wilson  writes:
> 
> > Continuing the fun of trying to find exactly the delay that is
> > sufficient to ensure that the page directory is fully loaded between
> > context switches, move the extra flush added in commit 70b73f9ac113
> > ("drm/i915/ringbuffer: Delay after invalidating gen6+ xcs") to just
> > after we flush the pd. Entirely based on the empirical data of running
> > failing tests in a loop until we survive a day (before the mtbf is 10-30
> > minutes).
> >
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107769
> > References: 70b73f9ac113 ("drm/i915/ringbuffer: Delay after invalidating 
> > gen6+ xcs")
> > Signed-off-by: Chris Wilson 
> > ---
> >  drivers/gpu/drm/i915/intel_ringbuffer.c | 40 ++---
> >  1 file changed, 22 insertions(+), 18 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
> > b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > index 86604dd1c5a5..472939f5c18f 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > @@ -1707,9 +1707,29 @@ static int switch_context(struct i915_request *rq)
> >   }
> >  
> >   if (ppgtt) {
> > + ret = engine->emit_flush(rq, EMIT_INVALIDATE);
> > + if (ret)
> > + goto err_mm;
> > +
> >   ret = flush_pd_dir(rq);
> >   if (ret)
> >   goto err_mm;
> > +
> > + /*
> > +  * Not only do we need a full barrier (post-sync write) after
> > +  * invalidating the TLBs, but we need to wait a little bit
> > +  * longer. Whether this is merely delaying us, or the
> > +  * subsequent flush is a key part of serialising with the
> > +  * post-sync op, this extra pass appears vital before a
> > +  * mm switch!
> > +  */
> > + ret = engine->emit_flush(rq, EMIT_INVALIDATE);
> > + if (ret)
> > + goto err_mm;
> > +
> > + ret = engine->emit_flush(rq, EMIT_FLUSH);
> > + if (ret)
> > + goto err_mm;
> 
> Someone said that proof is in the pudding. Just could
> be more fun if someone would show us the recipe.

Hah, in the Coca-Cola Company two people know the secret, we are much
more secure than that!
-Chris
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Re: [Intel-gfx] [PATCH v2] drm/i915: Fix ICL+ HDMI clock readout

[Ville Syrjälä]

On Mon, Sep 03, 2018 at 10:21:30PM -0700, Rodrigo Vivi wrote:
> On Mon, Sep 03, 2018 at 05:28:41PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä 
> > 
> > Copy the 38.4 vs. 19.2 MHz ref clock exception from the dpll
> > mgr into the clock readout function as well.
> > 
> > v2: Refactor the code into a common function
> > s/is_icl/gen11+/ (Rodrigo)
> 
> neat
> 
> > 
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107722
> > Signed-off-by: Ville Syrjälä 
> > Reviewed-by: Rodrigo Vivi  #v1
> 
> Reviewed-by: Rodrigo Vivi 

Thanks. Pushed.

> 
> > ---
> >  drivers/gpu/drm/i915/intel_ddi.c  |  2 +-
> >  drivers/gpu/drm/i915/intel_dpll_mgr.c | 23 +++
> >  drivers/gpu/drm/i915/intel_dpll_mgr.h |  1 +
> >  3 files changed, 17 insertions(+), 9 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> > b/drivers/gpu/drm/i915/intel_ddi.c
> > index f3b115ce4029..3e64488a2b0a 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -1414,7 +1414,7 @@ static int cnl_calc_wrpll_link(struct 
> > drm_i915_private *dev_priv,
> > break;
> > }
> >  
> > -   ref_clock = dev_priv->cdclk.hw.ref;
> > +   ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
> >  
> > dco_freq = (cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * ref_clock;
> >  
> > diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c 
> > b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > index 04d41bc1a4bb..e6cac9225536 100644
> > --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > @@ -2212,6 +2212,20 @@ static void cnl_wrpll_params_populate(struct 
> > skl_wrpll_params *params,
> > params->dco_fraction = dco & 0x7fff;
> >  }
> >  
> > +int cnl_hdmi_pll_ref_clock(struct drm_i915_private *dev_priv)
> > +{
> > +   int ref_clock = dev_priv->cdclk.hw.ref;
> > +
> > +   /*
> > +* For ICL+, the spec states: if reference frequency is 38.4,
> > +* use 19.2 because the DPLL automatically divides that by 2.
> > +*/
> > +   if (INTEL_GEN(dev_priv) >= 11 && ref_clock == 38400)
> > +   ref_clock = 19200;
> > +
> > +   return ref_clock;
> > +}
> > +
> >  static bool
> >  cnl_ddi_calculate_wrpll(int clock,
> > struct drm_i915_private *dev_priv,
> > @@ -2251,14 +2265,7 @@ cnl_ddi_calculate_wrpll(int clock,
> >  
> > cnl_wrpll_get_multipliers(best_div, &pdiv, &qdiv, &kdiv);
> >  
> > -   ref_clock = dev_priv->cdclk.hw.ref;
> > -
> > -   /*
> > -* For ICL, the spec states: if reference frequency is 38.4, use 19.2
> > -* because the DPLL automatically divides that by 2.
> > -*/
> > -   if (IS_ICELAKE(dev_priv) && ref_clock == 38400)
> > -   ref_clock = 19200;
> > +   ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
> >  
> > cnl_wrpll_params_populate(wrpll_params, best_dco, ref_clock, pdiv, qdiv,
> >   kdiv);
> > diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h 
> > b/drivers/gpu/drm/i915/intel_dpll_mgr.h
> > index 7e522cf4f13f..bf0de8a4dc63 100644
> > --- a/drivers/gpu/drm/i915/intel_dpll_mgr.h
> > +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h
> > @@ -344,5 +344,6 @@ void intel_dpll_dump_hw_state(struct drm_i915_private 
> > *dev_priv,
> >   struct intel_dpll_hw_state *hw_state);
> >  int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,
> >uint32_t pll_id);
> > +int cnl_hdmi_pll_ref_clock(struct drm_i915_private *dev_priv);
> >  
> >  #endif /* _INTEL_DPLL_MGR_H_ */
> > -- 
> > 2.16.4
> > 
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-- 
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Re: [Intel-gfx] [PATCH 2/2] drm/i915: reword documentation of possible pci_device_id struct

[Jani Nikula]

On Tue, 28 Aug 2018, Lucas De Marchi  wrote:
> On Tue, Aug 28, 2018 at 07:05:46PM +0100, Chris Wilson wrote:
>> Quoting Lucas De Marchi (2018-08-28 18:41:46)
>> > Document it like a real struct for ease of copy and paste, remove
>> > comment of C99 compatibility and document that in some cases the first 2
>> 
>> I do recall that we couldn't use either C99 or class due to userspace
>
> you can't actually use a c++ compiler.
>
> For C it works with any of -std=c99, gnu99, c11, gnu11, c17, gnu17.
> Tested with both gcc and clang. I've never heard of class being a
> reserved keyword and section 6.4.5 of said standard doesn't list it
> neither.
>
> Here the struct definition is in a *comment*... i.e. the user will copy
> and paste somewhere else and probably change __u16 to uint16_t in
> userspace. If he's building with g++, he can name the field to something
> else.
>
> If it was something we were defining in this header than I would agree
> with you... to retain compatibility with c++, not c99.

I always thought the comment told you not to use designated initializers
(introduced in C99), which would both impose a minimum C version
requirement as well as bring .class = foo in the code, which requires
more than just renaming the field with C++.

BR,
Jani.

>
> Lucas De Marchi
>
>> compatibility... The essence is that we need a reminder that we can't
>> assume the relaxed nature of kcc here.
>> -Chris
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Re: [Intel-gfx] [PATCH] drm/i915/ringbuffer: Move double invalidate to after pd flush

[Mika Kuoppala]

Chris Wilson  writes:

> Continuing the fun of trying to find exactly the delay that is
> sufficient to ensure that the page directory is fully loaded between
> context switches, move the extra flush added in commit 70b73f9ac113
> ("drm/i915/ringbuffer: Delay after invalidating gen6+ xcs") to just
> after we flush the pd. Entirely based on the empirical data of running
> failing tests in a loop until we survive a day (before the mtbf is 10-30
> minutes).
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107769
> References: 70b73f9ac113 ("drm/i915/ringbuffer: Delay after invalidating 
> gen6+ xcs")
> Signed-off-by: Chris Wilson 
> ---
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 40 ++---
>  1 file changed, 22 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c 
> b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 86604dd1c5a5..472939f5c18f 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -1707,9 +1707,29 @@ static int switch_context(struct i915_request *rq)
>   }
>  
>   if (ppgtt) {
> + ret = engine->emit_flush(rq, EMIT_INVALIDATE);
> + if (ret)
> + goto err_mm;
> +
>   ret = flush_pd_dir(rq);
>   if (ret)
>   goto err_mm;
> +
> + /*
> +  * Not only do we need a full barrier (post-sync write) after
> +  * invalidating the TLBs, but we need to wait a little bit
> +  * longer. Whether this is merely delaying us, or the
> +  * subsequent flush is a key part of serialising with the
> +  * post-sync op, this extra pass appears vital before a
> +  * mm switch!
> +  */
> + ret = engine->emit_flush(rq, EMIT_INVALIDATE);
> + if (ret)
> + goto err_mm;
> +
> + ret = engine->emit_flush(rq, EMIT_FLUSH);
> + if (ret)
> + goto err_mm;

Someone said that proof is in the pudding. Just could
be more fun if someone would show us the recipe.

Acked-by: Mika Kuoppala 


>   }
>  
>   if (ctx->remap_slice) {
> @@ -1947,7 +1967,7 @@ static void gen6_bsd_submit_request(struct i915_request 
> *request)
>   intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
>  }
>  
> -static int emit_mi_flush_dw(struct i915_request *rq, u32 flags)
> +static int mi_flush_dw(struct i915_request *rq, u32 flags)
>  {
>   u32 cmd, *cs;
>  
> @@ -1985,23 +2005,7 @@ static int emit_mi_flush_dw(struct i915_request *rq, 
> u32 flags)
>  
>  static int gen6_flush_dw(struct i915_request *rq, u32 mode, u32 invflags)
>  {
> - int err;
> -
> - /*
> -  * Not only do we need a full barrier (post-sync write) after
> -  * invalidating the TLBs, but we need to wait a little bit
> -  * longer. Whether this is merely delaying us, or the
> -  * subsequent flush is a key part of serialising with the
> -  * post-sync op, this extra pass appears vital before a
> -  * mm switch!
> -  */
> - if (mode & EMIT_INVALIDATE) {
> - err = emit_mi_flush_dw(rq, invflags);
> - if (err)
> - return err;
> - }
> -
> - return emit_mi_flush_dw(rq, 0);
> + return mi_flush_dw(rq, mode & EMIT_INVALIDATE ? invflags : 0);
>  }
>  
>  static int gen6_bsd_ring_flush(struct i915_request *rq, u32 mode)
> -- 
> 2.19.0.rc1
>
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[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Pull intel_uncore_arm_unclaimed_mmio_detection() under the spinlock

[Patchwork]

== Series Details ==

Series: drm/i915: Pull intel_uncore_arm_unclaimed_mmio_detection() under the 
spinlock
URL   : https://patchwork.freedesktop.org/series/49128/
State : failure

== Summary ==

Applying: drm/i915: Pull intel_uncore_arm_unclaimed_mmio_detection() under the 
spinlock
Using index info to reconstruct a base tree...
M   drivers/gpu/drm/i915/intel_uncore.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/intel_uncore.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/intel_uncore.c
error: Failed to merge in the changes.
Patch failed at 0001 drm/i915: Pull intel_uncore_arm_unclaimed_mmio_detection() 
under the spinlock
Use 'git am --show-current-patch' to see the failed patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

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[Intel-gfx] [PATCH] drm/i915: Pull intel_uncore_arm_unclaimed_mmio_detection() under the spinlock

[Chris Wilson]

Elsewhere we manipulate uncore.unclaimed_mmio_check and
i915_param.mmio_debug under the irq lock (e.g. preserving the current
value across a user forcewake grab), but do not protect the manipulation
inside intel_uncore_arm_unclaimed_mmio_detection() from concurrent
access, even from itself. This is an issue as we do call
arm_unclaimed_mmio_detection from multiple threads without coordination.

Suggested-by: Mika Kuoppala 
Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/intel_uncore.c | 13 ++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
b/drivers/gpu/drm/i915/intel_uncore.c
index 05f0cda18501..3ad302c66254 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -2283,8 +2283,12 @@ bool intel_uncore_unclaimed_mmio(struct drm_i915_private 
*dev_priv)
 bool
 intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv)
 {
+   bool ret = false;
+
+   spin_lock_irq(&dev_priv->uncore.lock);
+
if (unlikely(dev_priv->uncore.unclaimed_mmio_check <= 0))
-   return false;
+   goto out;
 
if (unlikely(intel_uncore_unclaimed_mmio(dev_priv))) {
if (!i915_modparams.mmio_debug) {
@@ -2294,10 +2298,13 @@ intel_uncore_arm_unclaimed_mmio_detection(struct 
drm_i915_private *dev_priv)
i915_modparams.mmio_debug++;
}
dev_priv->uncore.unclaimed_mmio_check--;
-   return true;
+   ret = true;
}
 
-   return false;
+out:
+   spin_unlock_irq(&dev_priv->uncore.lock);
+
+   return ret;
 }
 
 static enum forcewake_domains
-- 
2.19.0.rc1

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Re: [Intel-gfx] [PATCH] drm/i915: Double check we didn't miss an unclaimed register access

[Mika Kuoppala]

Chris Wilson  writes:

> Quoting Chris Wilson (2018-09-04 13:38:27)
>> Quoting Mika Kuoppala (2018-09-04 13:34:12)
>> > Chris Wilson  writes:
>> > 
>> > > Currently, if the user has enabled mmio-debug around each register
>> > > access, we presume that we have then checked them all. However, it is
>> > > still possible through omission (raw register access) or external
>> > > interaction that the unclaimed access was not highlighted.
>> > >
>> > > Signed-off-by: Chris Wilson 
>> > > Cc: Mika Kuoppala 
>> > > ---
>> > >  drivers/gpu/drm/i915/intel_uncore.c | 13 +++--
>> > >  1 file changed, 7 insertions(+), 6 deletions(-)
>> > >
>> > > diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
>> > > b/drivers/gpu/drm/i915/intel_uncore.c
>> > > index 20f2f5ad9c3f..05f0cda18501 100644
>> > > --- a/drivers/gpu/drm/i915/intel_uncore.c
>> > > +++ b/drivers/gpu/drm/i915/intel_uncore.c
>> > > @@ -2283,15 +2283,16 @@ bool intel_uncore_unclaimed_mmio(struct 
>> > > drm_i915_private *dev_priv)
>> > >  bool
>> > >  intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private 
>> > > *dev_priv)
>> > >  {
>> > > - if (unlikely(i915_modparams.mmio_debug ||
>> > > -  dev_priv->uncore.unclaimed_mmio_check <= 0))
>> > > + if (unlikely(dev_priv->uncore.unclaimed_mmio_check <= 0))
>> > >   return false;
>> > >
>> > 
>> > We could catch the readers attention by marking this as READ_ONCE.
>> > 
>> > 
>> > And then take spinlock here before checking for unclaimed.
>> 
>> Could do, feels like overkill, but not contentious.
>
> Implied here, is improving unclaimed_mmio_check a fundamental
> requirement for this patch or additional work? I think the latter.

Additional work. Was just thinking aloud about the
possible races in this area.

Patch does what it says.

Reviewed-by: Mika Kuoppala 
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Re: [Intel-gfx] [PATCH] drm/i915/dp_mst: Fix enabling pipe clock for all streams

[Imre Deak]

On Tue, Sep 04, 2018 at 03:08:16PM +0300, Jani Nikula wrote:
> On Fri, 31 Aug 2018, Imre Deak  wrote:
> > commit afb2c4437dae ("drm/i915/ddi: Push pipe clock enabling to encoders")
> > inadvertently stopped enabling the pipe clock for any DP-MST stream
> > after the first one. It also rearranged the pipe clock enabling wrt.
> > initial MST payload allocation step (which may or may not be a
> > problem, but it's contrary to the spec.).
> >
> > Fix things by making the above commit truly a non-functional change.
> 
> What kind of MST setups do we have in CI? Why didn't they catch this?

What we'd need is a dock/other branch device with an DP-MST input and
two outputs. That would exercise the case that broke here.

> 
> BR,
> Jani.
> 
> 
> 
> >
> > Fixes: commit afb2c4437dae ("drm/i915/ddi: Push pipe clock enabling to 
> > encoders")
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107365
> > Reported-by: Lyude Paul 
> > Reported-by: dmummensch...@web.de
> > Tested-by: dmummensch...@web.de
> > Cc: Lyude Paul 
> > Cc: dmummensch...@web.de
> > Cc: Ville Syrjälä 
> > Cc: Rodrigo Vivi 
> > Cc: Chris Wilson 
> > Signed-off-by: Imre Deak 
> > ---
> >  drivers/gpu/drm/i915/intel_ddi.c| 17 +
> >  drivers/gpu/drm/i915/intel_dp_mst.c |  4 
> >  2 files changed, 13 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> > b/drivers/gpu/drm/i915/intel_ddi.c
> > index f3b115ce4029..dcb1a98d624d 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -2912,7 +2912,8 @@ static void intel_ddi_pre_enable_dp(struct 
> > intel_encoder *encoder,
> >  
> > icl_enable_phy_clock_gating(dig_port);
> >  
> > -   intel_ddi_enable_pipe_clock(crtc_state);
> > +   if (!is_mst)
> > +   intel_ddi_enable_pipe_clock(crtc_state);
> >  }
> >  
> >  static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
> > @@ -3015,14 +3016,14 @@ static void intel_ddi_post_disable_dp(struct 
> > intel_encoder *encoder,
> > bool is_mst = intel_crtc_has_type(old_crtc_state,
> >   INTEL_OUTPUT_DP_MST);
> >  
> > -   intel_ddi_disable_pipe_clock(old_crtc_state);
> > -
> > -   /*
> > -* Power down sink before disabling the port, otherwise we end
> > -* up getting interrupts from the sink on detecting link loss.
> > -*/
> > -   if (!is_mst)
> > +   if (!is_mst) {
> > +   intel_ddi_disable_pipe_clock(old_crtc_state);
> > +   /*
> > +* Power down sink before disabling the port, otherwise we end
> > +* up getting interrupts from the sink on detecting link loss.
> > +*/
> > intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
> > +   }
> >  
> > intel_disable_ddi_buf(encoder);
> >  
> > diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c 
> > b/drivers/gpu/drm/i915/intel_dp_mst.c
> > index 352e5216cc65..77920f1a3da1 100644
> > --- a/drivers/gpu/drm/i915/intel_dp_mst.c
> > +++ b/drivers/gpu/drm/i915/intel_dp_mst.c
> > @@ -166,6 +166,8 @@ static void intel_mst_post_disable_dp(struct 
> > intel_encoder *encoder,
> > struct intel_connector *connector =
> > to_intel_connector(old_conn_state->connector);
> >  
> > +   intel_ddi_disable_pipe_clock(old_crtc_state);
> > +
> > /* this can fail */
> > drm_dp_check_act_status(&intel_dp->mst_mgr);
> > /* and this can also fail */
> > @@ -249,6 +251,8 @@ static void intel_mst_pre_enable_dp(struct 
> > intel_encoder *encoder,
> > I915_WRITE(DP_TP_STATUS(port), temp);
> >  
> > ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr);
> > +
> > +   intel_ddi_enable_pipe_clock(pipe_config);
> >  }
> >  
> >  static void intel_mst_enable_dp(struct intel_encoder *encoder,
> 
> -- 
> Jani Nikula, Intel Open Source Graphics Center
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[Intel-gfx] [PATCH i-g-t] igt/pm_rps: Clear previous high load on high->low transition

[Chris Wilson]

Make sure we do flush out the previous spinner and delay signaling
transition completion until we do.

References: https://bugs.freedesktop.org/show_bug.cgi?id=102250
Signed-off-by: Chris Wilson 
Cc: Katarzyna Dec 
---
 tests/pm_rps.c | 26 +-
 1 file changed, 21 insertions(+), 5 deletions(-)

diff --git a/tests/pm_rps.c b/tests/pm_rps.c
index 84e71fa8a..23b33f41b 100644
--- a/tests/pm_rps.c
+++ b/tests/pm_rps.c
@@ -218,6 +218,7 @@ static void load_helper_set_load(enum load load)
 
 static void load_helper_run(enum load load)
 {
+   bool dummy;
int link[2];
 
/*
@@ -233,13 +234,14 @@ static void load_helper_run(enum load load)
 
lh.exit = false;
lh.load = load;
-   lh.signal = false;
+   lh.signal = true;
 
pipe(link);
lh.link = link[1];
 
igt_fork_helper(&lh.igt_proc) {
igt_spin_t *spin[2] = {};
+   bool prev_load;
uint32_t handle;
 
signal(SIGUSR1, load_helper_signal_handler);
@@ -247,10 +249,14 @@ static void load_helper_run(enum load load)
 
igt_debug("Applying %s load...\n", lh.load ? "high" : "low");
 
+   prev_load = lh.load == HIGH;
spin[0] = __igt_spin_batch_new(drm_fd);
-   if (lh.load == HIGH)
+   if (prev_load)
spin[1] = __igt_spin_batch_new(drm_fd);
+   prev_load = !prev_load; /* send the initial signal */
while (!lh.exit) {
+   bool high_load;
+
handle = spin[0]->handle;
igt_spin_batch_end(spin[0]);
while (gem_bo_busy(drm_fd, handle))
@@ -259,13 +265,20 @@ static void load_helper_run(enum load load)
igt_spin_batch_free(drm_fd, spin[0]);
usleep(100);
 
-   spin[0] = spin[1];
-   spin[lh.load == HIGH] = __igt_spin_batch_new(drm_fd);
+   high_load = lh.load == HIGH;
+   if (!high_load && spin[1]) {
+   igt_spin_batch_free(drm_fd, spin[1]);
+   spin[1] = NULL;
+   } else {
+   spin[0] = spin[1];
+   }
+   spin[high_load] = __igt_spin_batch_new(drm_fd);
 
-   if (lh.signal) {
+   if (lh.signal && high_load != prev_load) {
write(lh.link, &lh.signal, sizeof(lh.signal));
lh.signal = false;
}
+   prev_load = high_load;
}
 
handle = spin[0]->handle;
@@ -294,6 +307,9 @@ static void load_helper_run(enum load load)
 
close(lh.link);
lh.link = link[0];
+
+   /* wait for our helper to complete its first round */
+   igt_assert_eq(read(lh.link, &dummy, sizeof(dummy)), sizeof(dummy));
 }
 
 static void load_helper_stop(void)
-- 
2.19.0.rc1

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Re: [Intel-gfx] [PATCH v9 2/2] drm/i915: Adding YUV444 packed format support for skl+

[Maarten Lankhorst]

Op 30-08-18 om 16:24 schreef Stanislav Lisovskiy:
> PLANE_CTL_FORMAT_AYUV is already supported, according to hardware
> specification.
>
> v2: Edited commit message, removed redundant whitespaces.
>
> v3: Fixed fallthrough logic for the format switch cases.
>
> v4: Yet again fixed fallthrough logic, to reuse code from other case
> labels.
>
> v5: Started to use XYUV instead of AYUV, as we don't use alpha.
>
> v6: Removed unneeded initializer for new XYUV format.
>
> v7: Added scaling support for DRM_FORMAT_XYUV
>
> v8: Edited commit message to be more clear about skl+, renamed
> PLANE_CTL_FORMAT_AYUV to PLANE_CTL_FORMAT_XYUV as this format
> doesn't support per-pixel alpha. Fixed minor code issues.
>
> v9: Moved DRM format check to proper place in intel_framebuffer_init.
>
> Signed-off-by: Stanislav Lisovskiy 
> ---
>  drivers/gpu/drm/i915/i915_reg.h  |  2 +-
>  drivers/gpu/drm/i915/intel_display.c | 15 +++
>  drivers/gpu/drm/i915/intel_sprite.c  |  1 +
>  3 files changed, 17 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8534f88a60f6..e0c8480aaa02 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6499,7 +6499,7 @@ enum {
>  #define   PLANE_CTL_FORMAT_XRGB_2101010  (2 << 24)
>  #define   PLANE_CTL_FORMAT_XRGB_ (4 << 24)
>  #define   PLANE_CTL_FORMAT_XRGB_16161616F(6 << 24)
> -#define   PLANE_CTL_FORMAT_AYUV  (8 << 24)
> +#define   PLANE_CTL_FORMAT_XYUV  (8 << 24)
>  #define   PLANE_CTL_FORMAT_INDEXED   (12 << 24)
>  #define   PLANE_CTL_FORMAT_RGB_565   (14 << 24)
>  #define   ICL_PLANE_CTL_FORMAT_MASK  (0x1f << 23)
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index 30fdfd1a3037..9323708db71f 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -86,6 +86,7 @@ static const uint32_t skl_primary_formats[] = {
>   DRM_FORMAT_YVYU,
>   DRM_FORMAT_UYVY,
>   DRM_FORMAT_VYUY,
> + DRM_FORMAT_XYUV,
>  };
>  
>  static const uint32_t skl_pri_planar_formats[] = {
> @@ -101,6 +102,7 @@ static const uint32_t skl_pri_planar_formats[] = {
>   DRM_FORMAT_YVYU,
>   DRM_FORMAT_UYVY,
>   DRM_FORMAT_VYUY,
> + DRM_FORMAT_XYUV,
>   DRM_FORMAT_NV12,
>  };
>  
> @@ -2672,6 +2674,8 @@ int skl_format_to_fourcc(int format, bool rgb_order, 
> bool alpha)
>   return DRM_FORMAT_RGB565;
>   case PLANE_CTL_FORMAT_NV12:
>   return DRM_FORMAT_NV12;
> + case PLANE_CTL_FORMAT_XYUV:
> + return DRM_FORMAT_XYUV;
>   default:
>   case PLANE_CTL_FORMAT_XRGB_:
>   if (rgb_order) {
> @@ -3501,6 +3505,8 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
>   return PLANE_CTL_FORMAT_XRGB_2101010;
>   case DRM_FORMAT_XBGR2101010:
>   return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
> + case DRM_FORMAT_XYUV:
> + return PLANE_CTL_FORMAT_XYUV;
>   case DRM_FORMAT_YUYV:
>   return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
>   case DRM_FORMAT_YVYU:
> @@ -4959,6 +4965,7 @@ static int skl_update_scaler_plane(struct 
> intel_crtc_state *crtc_state,
>   case DRM_FORMAT_UYVY:
>   case DRM_FORMAT_VYUY:
>   case DRM_FORMAT_NV12:
> + case DRM_FORMAT_XYUV:
>   break;
>   default:
>   DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 
> 0x%x\n",
> @@ -13414,6 +13421,7 @@ static bool skl_plane_format_mod_supported(struct 
> drm_plane *_plane,
>   case DRM_FORMAT_UYVY:
>   case DRM_FORMAT_VYUY:
>   case DRM_FORMAT_NV12:
> + case DRM_FORMAT_XYUV:
>   if (modifier == I915_FORMAT_MOD_Yf_TILED)
>   return true;
>   /* fall through */
> @@ -14540,6 +14548,13 @@ static int intel_framebuffer_init(struct 
> intel_framebuffer *intel_fb,
>   goto err;
>   }
>   break;
> + case DRM_FORMAT_XYUV:
> + if (INTEL_GEN(dev_priv) < 9) {
> + DRM_DEBUG_KMS("unsupported pixel format: %s\n",
> +   
> drm_get_format_name(mode_cmd->pixel_format, &format_name));
> + goto err;
> + }
> + break;
This hunk isn't needed. DRM core rejects any formats not in the format arrays.

Can you add another patch to audit the framebuffer formats in 
intel_framebuffer_init and remove the errors we can no longer hit?
It should be all of them, but might mean we have to add a few more format 
arrays. It will probably be more readable to split it off
to its own function that returns the array and its size.

~Maarten
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Re: [Intel-gfx] [Mesa-dev] [PATCH libdrm] Add basic CONTRIBUTING file

[Daniel Vetter]

On Tue, Sep 04, 2018 at 10:02:40AM +0100, Eric Engestrom wrote:
> On Tuesday, 2018-09-04 16:24:44 +1000, Dave Airlie wrote:
> > On Mon, 3 Sep 2018 at 18:47, Daniel Vetter  wrote:
> > >
> > > I picked up a bunch of the pieces from wayland's version:
> > >
> > > https://gitlab.freedesktop.org/wayland/wayland/blob/master/CONTRIBUTING.md
> > >
> > > The weston one is fairly similar. Then I rather massively trimmed it
> > > down since in reality libdrm is a bit a dumping ground with very few
> > > real rules. The commit rights and CoC sections I've copied verbatim
> > > from igt respectively drm-misc. Weston/Wayland only differ in their
> > > pick of how many patches you need (10 instead of 5). I think for
> > > libdrm this is supremely relevant, since most everyone will get their
> > > commit rights by contributing already to the kernel or mesa and having
> > > commit rights there already.
> > >
> > > Anyway, I figured this is good to get the rules documented, even if
> > > there's mostly not many rules.
> > >
> > > Note: This references maintainers in a MAINTAINERS file, which needs
> > > to be created first.
> > >
> > > Note: With the gitlab migration the entire commit rights process is
> > > still a bit up in the air. But gitlab commit rights and roles are
> > > hierarchical, so we can do libdrm-only maintainer/commiter roles
> > > ("Owner" and "Developer" in gitlab-speak). This should avoid
> > > conflating libdrm roles with mesa roles, useful for those pushing to
> > > libdrm as primarily kernel contributors.
> > 
> > Fine with me,
> > 
> > Acked-by: Dave Airlie 
> > 
> > Dave.
> 
> I think this has gathered enough acks and rbs, you can just push it now
> and if there's anything that should be adjusted we can do that as
> a follow up :)

And pushed.
-Daniel
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Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH] drm/i915: Double check we didn't miss an unclaimed register access

[Chris Wilson]

Quoting Chris Wilson (2018-09-04 13:38:27)
> Quoting Mika Kuoppala (2018-09-04 13:34:12)
> > Chris Wilson  writes:
> > 
> > > Currently, if the user has enabled mmio-debug around each register
> > > access, we presume that we have then checked them all. However, it is
> > > still possible through omission (raw register access) or external
> > > interaction that the unclaimed access was not highlighted.
> > >
> > > Signed-off-by: Chris Wilson 
> > > Cc: Mika Kuoppala 
> > > ---
> > >  drivers/gpu/drm/i915/intel_uncore.c | 13 +++--
> > >  1 file changed, 7 insertions(+), 6 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
> > > b/drivers/gpu/drm/i915/intel_uncore.c
> > > index 20f2f5ad9c3f..05f0cda18501 100644
> > > --- a/drivers/gpu/drm/i915/intel_uncore.c
> > > +++ b/drivers/gpu/drm/i915/intel_uncore.c
> > > @@ -2283,15 +2283,16 @@ bool intel_uncore_unclaimed_mmio(struct 
> > > drm_i915_private *dev_priv)
> > >  bool
> > >  intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private 
> > > *dev_priv)
> > >  {
> > > - if (unlikely(i915_modparams.mmio_debug ||
> > > -  dev_priv->uncore.unclaimed_mmio_check <= 0))
> > > + if (unlikely(dev_priv->uncore.unclaimed_mmio_check <= 0))
> > >   return false;
> > >
> > 
> > We could catch the readers attention by marking this as READ_ONCE.
> > 
> > 
> > And then take spinlock here before checking for unclaimed.
> 
> Could do, feels like overkill, but not contentious.

Implied here, is improving unclaimed_mmio_check a fundamental
requirement for this patch or additional work? I think the latter.
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915: Double check we didn't miss an unclaimed register access

[Chris Wilson]

Quoting Mika Kuoppala (2018-09-04 13:34:12)
> Chris Wilson  writes:
> 
> > Currently, if the user has enabled mmio-debug around each register
> > access, we presume that we have then checked them all. However, it is
> > still possible through omission (raw register access) or external
> > interaction that the unclaimed access was not highlighted.
> >
> > Signed-off-by: Chris Wilson 
> > Cc: Mika Kuoppala 
> > ---
> >  drivers/gpu/drm/i915/intel_uncore.c | 13 +++--
> >  1 file changed, 7 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
> > b/drivers/gpu/drm/i915/intel_uncore.c
> > index 20f2f5ad9c3f..05f0cda18501 100644
> > --- a/drivers/gpu/drm/i915/intel_uncore.c
> > +++ b/drivers/gpu/drm/i915/intel_uncore.c
> > @@ -2283,15 +2283,16 @@ bool intel_uncore_unclaimed_mmio(struct 
> > drm_i915_private *dev_priv)
> >  bool
> >  intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private 
> > *dev_priv)
> >  {
> > - if (unlikely(i915_modparams.mmio_debug ||
> > -  dev_priv->uncore.unclaimed_mmio_check <= 0))
> > + if (unlikely(dev_priv->uncore.unclaimed_mmio_check <= 0))
> >   return false;
> >
> 
> We could catch the readers attention by marking this as READ_ONCE.
> 
> 
> And then take spinlock here before checking for unclaimed.

Could do, feels like overkill, but not contentious.
> 
> We poke here from hangcheck at unknown intervals and I am
> concerned both the trampling on the check values and also
> the register access of the unclaimed debug regs.
> 
> Which also raises the question that should we just move
> the arming check to park/unpark?

We still want around modeset, suspend/resume. I'd rather have the
periodic poking off the main thread (i.e. hangcheck) tbh.
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915: Double check we didn't miss an unclaimed register access

[Mika Kuoppala]

Chris Wilson  writes:

> Currently, if the user has enabled mmio-debug around each register
> access, we presume that we have then checked them all. However, it is
> still possible through omission (raw register access) or external
> interaction that the unclaimed access was not highlighted.
>
> Signed-off-by: Chris Wilson 
> Cc: Mika Kuoppala 
> ---
>  drivers/gpu/drm/i915/intel_uncore.c | 13 +++--
>  1 file changed, 7 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
> b/drivers/gpu/drm/i915/intel_uncore.c
> index 20f2f5ad9c3f..05f0cda18501 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -2283,15 +2283,16 @@ bool intel_uncore_unclaimed_mmio(struct 
> drm_i915_private *dev_priv)
>  bool
>  intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv)
>  {
> - if (unlikely(i915_modparams.mmio_debug ||
> -  dev_priv->uncore.unclaimed_mmio_check <= 0))
> + if (unlikely(dev_priv->uncore.unclaimed_mmio_check <= 0))
>   return false;
>

We could catch the readers attention by marking this as READ_ONCE.


And then take spinlock here before checking for unclaimed.

We poke here from hangcheck at unknown intervals and I am
concerned both the trampling on the check values and also
the register access of the unclaimed debug regs.

Which also raises the question that should we just move
the arming check to park/unpark?

-Mika

>   if (unlikely(intel_uncore_unclaimed_mmio(dev_priv))) {
> - DRM_DEBUG("Unclaimed register detected, "
> -   "enabling oneshot unclaimed register reporting. "
> -   "Please use i915.mmio_debug=N for more 
> information.\n");
> - i915_modparams.mmio_debug++;
> + if (!i915_modparams.mmio_debug) {
> + DRM_DEBUG("Unclaimed register detected, "
> +   "enabling oneshot unclaimed register 
> reporting. "
> +   "Please use i915.mmio_debug=N for more 
> information.\n");
> + i915_modparams.mmio_debug++;
> + }
>   dev_priv->uncore.unclaimed_mmio_check--;
>   return true;
>   }
> -- 
> 2.19.0.rc1
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Re: [Intel-gfx] [PATCH 4/4] drm/i915: enable P010, P012, P016 formats for primary and sprite planes

[Maarten Lankhorst]

Hey,

I like the new series. Looks good to me.

Reviewed-by: Maarten Lankhorst 

Unfortunately, we probably shouldn't merge this until we've fixed IGT to
support the new floating point formats. :(

This requires a new pixman release and a new cairo release, but without
it we can't actually test.

Op 30-08-18 om 14:41 schreef Juha-Pekka Heikkila:
> Enabling of P010, P012 and P016 formats. These formats will
> extend NV12 for larger bit depths.
>
> (Sharma, Swati2) Rename glk format table to follow similar style as on skl.
>
> Signed-off-by: Juha-Pekka Heikkila 
> ---
>  drivers/gpu/drm/i915/intel_display.c | 24 +++-
>  drivers/gpu/drm/i915/intel_sprite.c  | 26 --
>  2 files changed, 47 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index 43efeb4..1a67340 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -104,6 +104,25 @@ static const uint32_t skl_pri_planar_formats[] = {
>   DRM_FORMAT_NV12,
>  };
>  
> +static const uint32_t glk_pri_planar_formats[] = {
> + DRM_FORMAT_C8,
> + DRM_FORMAT_RGB565,
> + DRM_FORMAT_XRGB,
> + DRM_FORMAT_XBGR,
> + DRM_FORMAT_ARGB,
> + DRM_FORMAT_ABGR,
> + DRM_FORMAT_XRGB2101010,
> + DRM_FORMAT_XBGR2101010,
> + DRM_FORMAT_YUYV,
> + DRM_FORMAT_YVYU,
> + DRM_FORMAT_UYVY,
> + DRM_FORMAT_VYUY,
> + DRM_FORMAT_NV12,
> + DRM_FORMAT_P010,
> + DRM_FORMAT_P012,
> + DRM_FORMAT_P016,
> +};
> +
>  static const uint64_t skl_format_modifiers_noccs[] = {
>   I915_FORMAT_MOD_Yf_TILED,
>   I915_FORMAT_MOD_Y_TILED,
> @@ -13721,7 +13740,10 @@ intel_primary_plane_create(struct drm_i915_private 
> *dev_priv, enum pipe pipe)
>   primary->has_ccs = skl_plane_has_ccs(dev_priv, pipe,
>PLANE_PRIMARY);
>  
> - if (skl_plane_has_planar(dev_priv, pipe, PLANE_PRIMARY)) {
> + if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
> + intel_primary_formats = glk_pri_planar_formats;
> + num_formats = ARRAY_SIZE(glk_pri_planar_formats);
> + } else if (skl_plane_has_planar(dev_priv, pipe, PLANE_PRIMARY)) 
> {
>   intel_primary_formats = skl_pri_planar_formats;
>   num_formats = ARRAY_SIZE(skl_pri_planar_formats);
>   } else {
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c 
> b/drivers/gpu/drm/i915/intel_sprite.c
> index 1f1276f..3270fab 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -1294,6 +1294,22 @@ static uint32_t skl_planar_formats[] = {
>   DRM_FORMAT_NV12,
>  };
>  
> +static uint32_t glk_planar_formats[] = {
> + DRM_FORMAT_RGB565,
> + DRM_FORMAT_ABGR,
> + DRM_FORMAT_ARGB,
> + DRM_FORMAT_XBGR,
> + DRM_FORMAT_XRGB,
> + DRM_FORMAT_YUYV,
> + DRM_FORMAT_YVYU,
> + DRM_FORMAT_UYVY,
> + DRM_FORMAT_VYUY,
> + DRM_FORMAT_NV12,
> + DRM_FORMAT_P010,
> + DRM_FORMAT_P012,
> + DRM_FORMAT_P016,
> +};
> +
>  static const uint64_t skl_plane_format_modifiers_noccs[] = {
>   I915_FORMAT_MOD_Yf_TILED,
>   I915_FORMAT_MOD_Y_TILED,
> @@ -1551,8 +1567,14 @@ intel_sprite_plane_create(struct drm_i915_private 
> *dev_priv,
>  
>   if (skl_plane_has_planar(dev_priv, pipe,
>PLANE_SPRITE0 + plane)) {
> - plane_formats = skl_planar_formats;
> - num_plane_formats = ARRAY_SIZE(skl_planar_formats);
> + if (INTEL_GEN(dev_priv) >= 10 ||
> + IS_GEMINILAKE(dev_priv)) {
> + plane_formats = glk_planar_formats;
> + num_plane_formats = 
> ARRAY_SIZE(glk_planar_formats);
> + } else {
> + plane_formats = skl_planar_formats;
> + num_plane_formats = 
> ARRAY_SIZE(skl_planar_formats);
> + }
>   } else {
>   plane_formats = skl_plane_formats;
>   num_plane_formats = ARRAY_SIZE(skl_plane_formats);


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Re: [Intel-gfx] [PATCH 09/14] drm: Update todo.rst

[Daniel Vetter]

On Mon, Sep 03, 2018 at 06:38:44PM +0100, Emil Velikov wrote:
> On 3 September 2018 at 17:54, Daniel Vetter  wrote:
> 
> > -Hide legacy cruft better
> > -
> > -
> > -Way back DRM supported only drivers which shadow-attached to PCI devices 
> > with
> > -userspace or fbdev drivers setting up outputs. Modern DRM drivers take 
> > charge
> > -of the entire device, you can spot them with the DRIVER_MODESET flag.
> > -
> > -Unfortunately there's still large piles of legacy code around which needs 
> > to
> > -be hidden so that driver writers don't accidentally end up using it. And to
> > -prevent security issues in those legacy IOCTLs from being exploited on 
> > modern
> > -drivers. This has multiple possible subtasks:
> > -
> 
> > -* Extract support code for legacy features into a ``drm-legacy.ko`` kernel
> > -  module and compile it only when one of the legacy drivers is enabled.
> > -
> This isn't done,

Yup, but I kinda figured I'll give up on this idea. The code is hidden
well enough, I don't think a drm-legacy.ko will buy us much. Except lots
of churn on older driver's Kconfig entries for no purpose.

There's been a patch already a while back to hide the legacy drivers
better, and Dave nacked it. So I'm not really for pushing this idea
anymore as a good task for newbies (which todo.rst tries to collect).

Want me to explain this a bit better in the commit message?
-Daniel

> 
> > -This is mostly done, the only thing left is to split up ``drm_irq.c`` into
> > -legacy cruft and the parts needed by modern KMS drivers.
> > -
> ... while this one is.
> 
> HTH
> -Emil

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH] drm/i915/dp_mst: Fix enabling pipe clock for all streams

[Jani Nikula]

On Fri, 31 Aug 2018, Imre Deak  wrote:
> commit afb2c4437dae ("drm/i915/ddi: Push pipe clock enabling to encoders")
> inadvertently stopped enabling the pipe clock for any DP-MST stream
> after the first one. It also rearranged the pipe clock enabling wrt.
> initial MST payload allocation step (which may or may not be a
> problem, but it's contrary to the spec.).
>
> Fix things by making the above commit truly a non-functional change.

What kind of MST setups do we have in CI? Why didn't they catch this?

BR,
Jani.



>
> Fixes: commit afb2c4437dae ("drm/i915/ddi: Push pipe clock enabling to 
> encoders")
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107365
> Reported-by: Lyude Paul 
> Reported-by: dmummensch...@web.de
> Tested-by: dmummensch...@web.de
> Cc: Lyude Paul 
> Cc: dmummensch...@web.de
> Cc: Ville Syrjälä 
> Cc: Rodrigo Vivi 
> Cc: Chris Wilson 
> Signed-off-by: Imre Deak 
> ---
>  drivers/gpu/drm/i915/intel_ddi.c| 17 +
>  drivers/gpu/drm/i915/intel_dp_mst.c |  4 
>  2 files changed, 13 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> b/drivers/gpu/drm/i915/intel_ddi.c
> index f3b115ce4029..dcb1a98d624d 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2912,7 +2912,8 @@ static void intel_ddi_pre_enable_dp(struct 
> intel_encoder *encoder,
>  
>   icl_enable_phy_clock_gating(dig_port);
>  
> - intel_ddi_enable_pipe_clock(crtc_state);
> + if (!is_mst)
> + intel_ddi_enable_pipe_clock(crtc_state);
>  }
>  
>  static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
> @@ -3015,14 +3016,14 @@ static void intel_ddi_post_disable_dp(struct 
> intel_encoder *encoder,
>   bool is_mst = intel_crtc_has_type(old_crtc_state,
> INTEL_OUTPUT_DP_MST);
>  
> - intel_ddi_disable_pipe_clock(old_crtc_state);
> -
> - /*
> -  * Power down sink before disabling the port, otherwise we end
> -  * up getting interrupts from the sink on detecting link loss.
> -  */
> - if (!is_mst)
> + if (!is_mst) {
> + intel_ddi_disable_pipe_clock(old_crtc_state);
> + /*
> +  * Power down sink before disabling the port, otherwise we end
> +  * up getting interrupts from the sink on detecting link loss.
> +  */
>   intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
> + }
>  
>   intel_disable_ddi_buf(encoder);
>  
> diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c 
> b/drivers/gpu/drm/i915/intel_dp_mst.c
> index 352e5216cc65..77920f1a3da1 100644
> --- a/drivers/gpu/drm/i915/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/intel_dp_mst.c
> @@ -166,6 +166,8 @@ static void intel_mst_post_disable_dp(struct 
> intel_encoder *encoder,
>   struct intel_connector *connector =
>   to_intel_connector(old_conn_state->connector);
>  
> + intel_ddi_disable_pipe_clock(old_crtc_state);
> +
>   /* this can fail */
>   drm_dp_check_act_status(&intel_dp->mst_mgr);
>   /* and this can also fail */
> @@ -249,6 +251,8 @@ static void intel_mst_pre_enable_dp(struct intel_encoder 
> *encoder,
>   I915_WRITE(DP_TP_STATUS(port), temp);
>  
>   ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr);
> +
> + intel_ddi_enable_pipe_clock(pipe_config);
>  }
>  
>  static void intel_mst_enable_dp(struct intel_encoder *encoder,

-- 
Jani Nikula, Intel Open Source Graphics Center
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Double check we didn't miss an unclaimed register access

[Patchwork]

== Series Details ==

Series: drm/i915: Double check we didn't miss an unclaimed register access
URL   : https://patchwork.freedesktop.org/series/49121/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4763 -> Patchwork_10079 =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_10079 need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10079, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/49121/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_10079:

  === IGT changes ===

 Warnings 

igt@pm_rpm@module-reload:
  fi-hsw-4770r:   PASS -> SKIP


== Known issues ==

  Here are the changes found in Patchwork_10079 that come from known issues:

  === IGT changes ===

 Issues hit 

igt@drv_module_reload@basic-reload-inject:
  fi-hsw-4770r:   PASS -> DMESG-WARN (fdo#107425)

igt@gem_exec_suspend@basic-s4-devices:
  fi-blb-e6850:   PASS -> INCOMPLETE (fdo#107718)

igt@kms_psr@primary_page_flip:
  fi-cnl-psr: PASS -> FAIL (fdo#107336)


 Possible fixes 

igt@kms_pipe_crc_basic@hang-read-crc-pipe-b:
  fi-skl-guc: FAIL (fdo#103191) -> PASS

igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence:
  fi-byt-clapper: FAIL (fdo#103191, fdo#107362) -> PASS

igt@pm_rpm@module-reload:
  fi-cnl-psr: WARN (fdo#107602, fdo#107708) -> PASS


  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#107336 https://bugs.freedesktop.org/show_bug.cgi?id=107336
  fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
  fdo#107425 https://bugs.freedesktop.org/show_bug.cgi?id=107425
  fdo#107602 https://bugs.freedesktop.org/show_bug.cgi?id=107602
  fdo#107708 https://bugs.freedesktop.org/show_bug.cgi?id=107708
  fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718


== Participating hosts (52 -> 47) ==

  Missing(5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan 
fi-hsw-4200u 


== Build changes ==

* Linux: CI_DRM_4763 -> Patchwork_10079

  CI_DRM_4763: 1f8c06844acac7a349fb80471afcc09f33c6cfc0 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4622: 022be555443eaa3317da6a9a451cf2c9dfcd6ab8 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10079: 905bbb627b514b8a80e0788139f6ba46c8baed0e @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

905bbb627b51 drm/i915: Double check we didn't miss an unclaimed register access

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10079/issues.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for Add XYUV format support (rev5)

[Patchwork]

== Series Details ==

Series: Add XYUV format support (rev5)
URL   : https://patchwork.freedesktop.org/series/48007/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4763 -> Patchwork_10078 =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_10078 need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10078, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://patchwork.freedesktop.org/api/1.0/series/48007/revisions/5/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_10078:

  === IGT changes ===

 Warnings 

igt@pm_rpm@module-reload:
  fi-hsw-4770r:   PASS -> SKIP


== Known issues ==

  Here are the changes found in Patchwork_10078 that come from known issues:

  === IGT changes ===

 Issues hit 

igt@drv_module_reload@basic-reload-inject:
  fi-hsw-4770r:   PASS -> DMESG-WARN (fdo#107425)

igt@kms_frontbuffer_tracking@basic:
  fi-hsw-peppy:   PASS -> DMESG-WARN (fdo#102614)

igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
  fi-byt-clapper: PASS -> FAIL (fdo#103191, fdo#107362) +1

igt@kms_psr@primary_page_flip:
  fi-cnl-psr: PASS -> FAIL (fdo#107336)


 Possible fixes 

igt@kms_pipe_crc_basic@hang-read-crc-pipe-b:
  fi-skl-guc: FAIL (fdo#103191) -> PASS

igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence:
  fi-byt-clapper: FAIL (fdo#103191, fdo#107362) -> PASS

igt@pm_rpm@module-reload:
  fi-cnl-psr: WARN (fdo#107602, fdo#107708) -> PASS


 Warnings 

igt@pm_rpm@module-reload:
  fi-bsw-n3050:   DMESG-WARN (fdo#107704) -> DMESG-FAIL (fdo#107704)


  fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#107336 https://bugs.freedesktop.org/show_bug.cgi?id=107336
  fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
  fdo#107425 https://bugs.freedesktop.org/show_bug.cgi?id=107425
  fdo#107602 https://bugs.freedesktop.org/show_bug.cgi?id=107602
  fdo#107704 https://bugs.freedesktop.org/show_bug.cgi?id=107704
  fdo#107708 https://bugs.freedesktop.org/show_bug.cgi?id=107708


== Participating hosts (52 -> 46) ==

  Missing(6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks 
fi-bsw-cyan fi-ctg-p8600 


== Build changes ==

* Linux: CI_DRM_4763 -> Patchwork_10078

  CI_DRM_4763: 1f8c06844acac7a349fb80471afcc09f33c6cfc0 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4622: 022be555443eaa3317da6a9a451cf2c9dfcd6ab8 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10078: 5c8a6f919689dd4a640ddadc5ba8c0ce07025a45 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

5c8a6f919689 drm/i915: Adding YUV444 packed format support for skl+
65e3d6aeadbe drm: Introduce new DRM_FORMAT_XYUV

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10078/issues.html
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[Intel-gfx] [PATCH] drm/i915: Double check we didn't miss an unclaimed register access

[Chris Wilson]

Currently, if the user has enabled mmio-debug around each register
access, we presume that we have then checked them all. However, it is
still possible through omission (raw register access) or external
interaction that the unclaimed access was not highlighted.

Signed-off-by: Chris Wilson 
Cc: Mika Kuoppala 
---
 drivers/gpu/drm/i915/intel_uncore.c | 13 +++--
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
b/drivers/gpu/drm/i915/intel_uncore.c
index 20f2f5ad9c3f..05f0cda18501 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -2283,15 +2283,16 @@ bool intel_uncore_unclaimed_mmio(struct 
drm_i915_private *dev_priv)
 bool
 intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv)
 {
-   if (unlikely(i915_modparams.mmio_debug ||
-dev_priv->uncore.unclaimed_mmio_check <= 0))
+   if (unlikely(dev_priv->uncore.unclaimed_mmio_check <= 0))
return false;
 
if (unlikely(intel_uncore_unclaimed_mmio(dev_priv))) {
-   DRM_DEBUG("Unclaimed register detected, "
- "enabling oneshot unclaimed register reporting. "
- "Please use i915.mmio_debug=N for more 
information.\n");
-   i915_modparams.mmio_debug++;
+   if (!i915_modparams.mmio_debug) {
+   DRM_DEBUG("Unclaimed register detected, "
+ "enabling oneshot unclaimed register 
reporting. "
+ "Please use i915.mmio_debug=N for more 
information.\n");
+   i915_modparams.mmio_debug++;
+   }
dev_priv->uncore.unclaimed_mmio_check--;
return true;
}
-- 
2.19.0.rc1

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