Re: [Intel-gfx] [PATCH v2 1/5] drm/edid: Add CTA-861-G modes with VIC < 128
On 7/11/2019 4:02 PM, Ville Syrjala wrote:
From: Ville Syrjälä
Fill out our list of cea modes with the new stuff from CTA-861-G.
We only do the modes with VIC < 128 here. Adding the higher
numbered VICs will need some slight code refactoring first.
Cc: Hans Verkuil
Cc: Shashank Sharma
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_edid.c | 100 +
1 file changed, 100 insertions(+)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 82a4ceed3fcf..bcd9ed569d64 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -1275,6 +1275,106 @@ static const struct drm_display_mode edid_cea_modes[] =
{
4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
.vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
+ /* 108 - 1280x720@48Hz 16:9 */
+ { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 9, 1280, 2240,
+ 2280, 2500, 0, 720, 725, 730, 750, 0,
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+ .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
+ /* 109 - 1280x720@48Hz 64:27 */
+ { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 9, 1280, 2240,
+ 2280, 2500, 0, 720, 725, 730, 750, 0,
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+ .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
+ /* 110 - 1680x720@48Hz 64:27 */
+ { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490,
+ 2530, 2750, 0, 720, 725, 730, 750, 0,
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+ .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
+ /* 111 - 1920x1080@48Hz 16:9 */
+ { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
+ 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+ .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
+ /* 112 - 1920x1080@48Hz 64:27 */
+ { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
+ 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+ .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
+ /* 113 - 2560x1080@48Hz 64:27 */
+ { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558,
+ 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+ .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
+ /* 114 - 3840x2160@48Hz 16:9 */
+ { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
+ 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+ .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
+ /* 115 - 4096x2160@48Hz 256:135 */
+ { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116,
+ 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+ .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135,
},
+ /* 116 - 3840x2160@48Hz 64:27 */
+ { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
+ 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+ .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
+ /* 117 - 3840x2160@100Hz 16:9 */
+ { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
+ 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+ .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
+ /* 118 - 3840x2160@120Hz 16:9 */
+ { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
+ 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+ .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
+ /* 119 - 3840x2160@100Hz 64:27 */
+ { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
+ 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+ .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
+ /* 120 - 3840x2160@120Hz 64:27 */
+ { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
+ 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
+
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: We don't need display's suspend/resume operations when !HAS_DISPLAY (rev5)
== Series Details == Series: drm/i915: We don't need display's suspend/resume operations when !HAS_DISPLAY (rev5) URL : https://patchwork.freedesktop.org/series/60839/ State : success == Summary == CI Bug Log - changes from CI_DRM_6507_full -> Patchwork_13696_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13696_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_tiled_swapping@non-threaded: - shard-glk: [PASS][1] -> [DMESG-WARN][2] ([fdo#108686]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6507/shard-glk4/igt@gem_tiled_swapp...@non-threaded.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13696/shard-glk5/igt@gem_tiled_swapp...@non-threaded.html * igt@kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([fdo#108566]) +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6507/shard-kbl7/igt@kms_cursor_...@pipe-a-cursor-suspend.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13696/shard-kbl6/igt@kms_cursor_...@pipe-a-cursor-suspend.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-skl: [PASS][5] -> [INCOMPLETE][6] ([fdo#109507]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6507/shard-skl4/igt@kms_f...@flip-vs-suspend-interruptible.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13696/shard-skl4/igt@kms_f...@flip-vs-suspend-interruptible.html * igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw: - shard-iclb: [PASS][7] -> [FAIL][8] ([fdo#103167]) +3 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6507/shard-iclb7/igt@kms_frontbuffer_track...@fbc-1p-pri-indfb-multidraw.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13696/shard-iclb4/igt@kms_frontbuffer_track...@fbc-1p-pri-indfb-multidraw.html * igt@kms_frontbuffer_tracking@fbc-stridechange: - shard-snb: [PASS][9] -> [SKIP][10] ([fdo#109271]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6507/shard-snb2/igt@kms_frontbuffer_track...@fbc-stridechange.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13696/shard-snb1/igt@kms_frontbuffer_track...@fbc-stridechange.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-apl: [PASS][11] -> [DMESG-WARN][12] ([fdo#108566]) +4 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6507/shard-apl4/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13696/shard-apl1/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-skl: [PASS][13] -> [INCOMPLETE][14] ([fdo#104108]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6507/shard-skl4/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-c-planes.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13696/shard-skl9/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-c-planes.html * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [PASS][15] -> [FAIL][16] ([fdo#108145]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6507/shard-skl5/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13696/shard-skl5/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html * igt@kms_plane_lowres@pipe-a-tiling-y: - shard-iclb: [PASS][17] -> [FAIL][18] ([fdo#103166]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6507/shard-iclb6/igt@kms_plane_low...@pipe-a-tiling-y.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13696/shard-iclb7/igt@kms_plane_low...@pipe-a-tiling-y.html * igt@kms_psr2_su@frontbuffer: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109642] / [fdo#111068]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6507/shard-iclb2/igt@kms_psr2...@frontbuffer.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13696/shard-iclb1/igt@kms_psr2...@frontbuffer.html * igt@kms_psr@psr2_primary_page_flip: - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109441]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6507/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13696/shard-iclb7/igt@kms_psr@psr2_primary_page_flip.html * igt@kms_psr@suspend: - shard-skl: [PASS][23] -> [INCOMPLETE][24] ([fdo#108972]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6507/shard-skl6/igt@kms_...@suspend.html [24]:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/icl: Remove set but not used variable 'src_y'
== Series Details ==
Series: drm/i915/icl: Remove set but not used variable 'src_y'
URL : https://patchwork.freedesktop.org/series/63923/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6508 -> Patchwork_13698
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13698/
Known issues
Here are the changes found in Patchwork_13698 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_contexts:
- fi-skl-iommu: [PASS][1] -> [INCOMPLETE][2] ([fdo#111050])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6508/fi-skl-iommu/igt@i915_selftest@live_contexts.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13698/fi-skl-iommu/igt@i915_selftest@live_contexts.html
Possible fixes
* {igt@gem_ctx_switch@rcs0}:
- fi-icl-guc: [INCOMPLETE][3] ([fdo#107713]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6508/fi-icl-guc/igt@gem_ctx_swi...@rcs0.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13698/fi-icl-guc/igt@gem_ctx_swi...@rcs0.html
* igt@gem_exec_reloc@basic-write-cpu-noreloc:
- fi-icl-u3: [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6508/fi-icl-u3/igt@gem_exec_re...@basic-write-cpu-noreloc.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13698/fi-icl-u3/igt@gem_exec_re...@basic-write-cpu-noreloc.html
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [INCOMPLETE][7] ([fdo#107718]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6508/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13698/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][9] ([fdo#109485]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6508/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13698/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
[fdo#111050]: https://bugs.freedesktop.org/show_bug.cgi?id=111050
Participating hosts (52 -> 45)
--
Additional (1): fi-icl-dsi
Missing(8): fi-ilk-m540 fi-byt-squawks fi-icl-u2 fi-bsw-cyan fi-apl-guc
fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6508 -> Patchwork_13698
CI_DRM_6508: 9b39702210b8ac35297570f29f496517f3dea062 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5102: 6038ace76016d8892f4d13aef5301f71ca1a6e2d @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13698: 1e57f809b80d4e4e40e75fb9d8ae89424c4ccdaf @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
1e57f809b80d drm/i915/icl: Remove set but not used variable 'src_y'
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13698/
___
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Flush extra hard after writing relocations through the GTT
== Series Details == Series: drm/i915: Flush extra hard after writing relocations through the GTT URL : https://patchwork.freedesktop.org/series/63914/ State : success == Summary == CI Bug Log - changes from CI_DRM_6507_full -> Patchwork_13695_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13695_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_tiled_swapping@non-threaded: - shard-glk: [PASS][1] -> [DMESG-WARN][2] ([fdo#108686]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6507/shard-glk4/igt@gem_tiled_swapp...@non-threaded.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13695/shard-glk9/igt@gem_tiled_swapp...@non-threaded.html * igt@kms_flip@basic-flip-vs-modeset: - shard-snb: [PASS][3] -> [INCOMPLETE][4] ([fdo#105411]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6507/shard-snb2/igt@kms_f...@basic-flip-vs-modeset.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13695/shard-snb1/igt@kms_f...@basic-flip-vs-modeset.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite: - shard-iclb: [PASS][5] -> [FAIL][6] ([fdo#103167]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6507/shard-iclb3/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13695/shard-iclb8/igt@kms_frontbuffer_track...@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes: - shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([fdo#108566]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6507/shard-kbl7/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-a-planes.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13695/shard-kbl6/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-a-planes.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([fdo#108566]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6507/shard-apl4/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13695/shard-apl4/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [PASS][11] -> [FAIL][12] ([fdo#108145]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6507/shard-skl5/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13695/shard-skl5/igt@kms_plane_alpha_bl...@pipe-a-constant-alpha-min.html * igt@kms_psr2_su@frontbuffer: - shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#109642] / [fdo#111068]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6507/shard-iclb2/igt@kms_psr2...@frontbuffer.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13695/shard-iclb3/igt@kms_psr2...@frontbuffer.html * igt@kms_psr@psr2_primary_page_flip: - shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109441]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6507/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13695/shard-iclb4/igt@kms_psr@psr2_primary_page_flip.html * igt@kms_vblank@pipe-c-query-busy: - shard-iclb: [PASS][17] -> [INCOMPLETE][18] ([fdo#107713]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6507/shard-iclb4/igt@kms_vbl...@pipe-c-query-busy.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13695/shard-iclb7/igt@kms_vbl...@pipe-c-query-busy.html Possible fixes * igt@i915_pm_rpm@i2c: - shard-hsw: [FAIL][19] ([fdo#104097]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6507/shard-hsw4/igt@i915_pm_...@i2c.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13695/shard-hsw1/igt@i915_pm_...@i2c.html * igt@i915_pm_rps@waitboost: - shard-skl: [FAIL][21] ([fdo#102250]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6507/shard-skl9/igt@i915_pm_...@waitboost.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13695/shard-skl9/igt@i915_pm_...@waitboost.html * igt@i915_suspend@fence-restore-tiled2untiled: - shard-apl: [DMESG-WARN][23] ([fdo#108566]) -> [PASS][24] +3 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6507/shard-apl4/igt@i915_susp...@fence-restore-tiled2untiled.html [24]:
[Intel-gfx] [PATCH -next] drm/i915/icl: Remove set but not used variable 'src_y'
Fixes gcc '-Wunused-but-set-variable' warning: drivers/gpu/drm/i915/display/intel_sprite.c: In function 'g4x_sprite_check_scaling': drivers/gpu/drm/i915/display/intel_sprite.c:1494:13: warning: variable 'src_y' set but not used [-Wunused-but-set-variable] Reported-by: Hulk Robot Signed-off-by: YueHaibing --- drivers/gpu/drm/i915/display/intel_sprite.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index 34586f29be60..9c3367491f04 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -1491,7 +1491,7 @@ g4x_sprite_check_scaling(struct intel_crtc_state *crtc_state, const struct drm_framebuffer *fb = plane_state->base.fb; const struct drm_rect *src = _state->base.src; const struct drm_rect *dst = _state->base.dst; - int src_x, src_y, src_w, src_h, crtc_w, crtc_h; + int src_x, src_w, src_h, crtc_w, crtc_h; const struct drm_display_mode *adjusted_mode = _state->base.adjusted_mode; unsigned int cpp = fb->format->cpp[0]; @@ -1502,7 +1502,6 @@ g4x_sprite_check_scaling(struct intel_crtc_state *crtc_state, crtc_h = drm_rect_height(dst); src_x = src->x1 >> 16; - src_y = src->y1 >> 16; src_w = drm_rect_width(src) >> 16; src_h = drm_rect_height(src) >> 16; ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dsi: remove set but not used variable 'hfront_porch'
== Series Details ==
Series: drm/i915/dsi: remove set but not used variable 'hfront_porch'
URL : https://patchwork.freedesktop.org/series/63922/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6508 -> Patchwork_13697
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13697/
Known issues
Here are the changes found in Patchwork_13697 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_create@basic-files:
- fi-icl-u2: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713] /
[fdo#109100])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6508/fi-icl-u2/igt@gem_ctx_cre...@basic-files.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13697/fi-icl-u2/igt@gem_ctx_cre...@basic-files.html
* igt@i915_selftest@live_contexts:
- fi-skl-iommu: [PASS][3] -> [INCOMPLETE][4] ([fdo#111050])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6508/fi-skl-iommu/igt@i915_selftest@live_contexts.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13697/fi-skl-iommu/igt@i915_selftest@live_contexts.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7567u: [PASS][5] -> [FAIL][6] ([fdo#109485])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6508/fi-kbl-7567u/igt@kms_chamel...@hdmi-hpd-fast.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13697/fi-kbl-7567u/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@prime_vgem@basic-fence-flip:
- fi-ilk-650: [PASS][7] -> [DMESG-WARN][8] ([fdo#106387]) +1
similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6508/fi-ilk-650/igt@prime_v...@basic-fence-flip.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13697/fi-ilk-650/igt@prime_v...@basic-fence-flip.html
Possible fixes
* {igt@gem_ctx_switch@rcs0}:
- fi-icl-guc: [INCOMPLETE][9] ([fdo#107713]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6508/fi-icl-guc/igt@gem_ctx_swi...@rcs0.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13697/fi-icl-guc/igt@gem_ctx_swi...@rcs0.html
* igt@gem_exec_reloc@basic-write-cpu-noreloc:
- fi-icl-u3: [DMESG-WARN][11] ([fdo#107724]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6508/fi-icl-u3/igt@gem_exec_re...@basic-write-cpu-noreloc.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13697/fi-icl-u3/igt@gem_exec_re...@basic-write-cpu-noreloc.html
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [INCOMPLETE][13] ([fdo#107718]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6508/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13697/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][15] ([fdo#109485]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6508/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13697/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#106387]: https://bugs.freedesktop.org/show_bug.cgi?id=106387
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
[fdo#111050]: https://bugs.freedesktop.org/show_bug.cgi?id=111050
Participating hosts (52 -> 47)
--
Additional (1): fi-icl-dsi
Missing(6): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6508 -> Patchwork_13697
CI_DRM_6508: 9b39702210b8ac35297570f29f496517f3dea062 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5102: 6038ace76016d8892f4d13aef5301f71ca1a6e2d @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13697: e8b2113f517738d7db73b516f1879c04780289a4 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
e8b2113f5177 drm/i915/dsi: remove set but not used variable 'hfront_porch'
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13697/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/1] drm/vblank: drop use of DRM_WAIT_ON()
== Series Details == Series: series starting with [1/1] drm/vblank: drop use of DRM_WAIT_ON() URL : https://patchwork.freedesktop.org/series/63913/ State : success == Summary == CI Bug Log - changes from CI_DRM_6507_full -> Patchwork_13694_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13694_full that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live_hangcheck: - shard-iclb: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713] / [fdo#108569]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6507/shard-iclb5/igt@i915_selftest@live_hangcheck.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13694/shard-iclb6/igt@i915_selftest@live_hangcheck.html * igt@kms_fbcon_fbt@fbc-suspend: - shard-skl: [PASS][3] -> [FAIL][4] ([fdo#103833]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6507/shard-skl8/igt@kms_fbcon_...@fbc-suspend.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13694/shard-skl9/igt@kms_fbcon_...@fbc-suspend.html * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite: - shard-iclb: [PASS][5] -> [FAIL][6] ([fdo#103167]) +6 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6507/shard-iclb2/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-shrfb-draw-pwrite.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13694/shard-iclb5/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-shrfb-draw-pwrite.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-blt: - shard-skl: [PASS][7] -> [FAIL][8] ([fdo#108040]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6507/shard-skl8/igt@kms_frontbuffer_track...@fbc-1p-primscrn-pri-shrfb-draw-blt.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13694/shard-skl9/igt@kms_frontbuffer_track...@fbc-1p-primscrn-pri-shrfb-draw-blt.html * igt@kms_frontbuffer_tracking@fbc-suspend: - shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([fdo#108566]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6507/shard-kbl7/igt@kms_frontbuffer_track...@fbc-suspend.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13694/shard-kbl6/igt@kms_frontbuffer_track...@fbc-suspend.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-blt: - shard-skl: [PASS][11] -> [FAIL][12] ([fdo#103167]) +2 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6507/shard-skl8/igt@kms_frontbuffer_track...@psr-1p-primscrn-pri-shrfb-draw-blt.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13694/shard-skl9/igt@kms_frontbuffer_track...@psr-1p-primscrn-pri-shrfb-draw-blt.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([fdo#108566]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6507/shard-apl4/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13694/shard-apl6/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [PASS][15] -> [FAIL][16] ([fdo#108145]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6507/shard-skl8/igt@kms_plane_alpha_bl...@pipe-a-coverage-7efc.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13694/shard-skl9/igt@kms_plane_alpha_bl...@pipe-a-coverage-7efc.html * igt@kms_plane_lowres@pipe-a-tiling-y: - shard-iclb: [PASS][17] -> [FAIL][18] ([fdo#103166]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6507/shard-iclb6/igt@kms_plane_low...@pipe-a-tiling-y.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13694/shard-iclb8/igt@kms_plane_low...@pipe-a-tiling-y.html * igt@kms_psr2_su@frontbuffer: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109642] / [fdo#111068]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6507/shard-iclb2/igt@kms_psr2...@frontbuffer.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13694/shard-iclb4/igt@kms_psr2...@frontbuffer.html * igt@kms_psr@psr2_primary_page_flip: - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109441]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6507/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13694/shard-iclb5/igt@kms_psr@psr2_primary_page_flip.html * igt@kms_setmode@basic: - shard-kbl: [PASS][23] -> [FAIL][24] ([fdo#99912]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6507/shard-kbl3/igt@kms_setm...@basic.html [24]:
[Intel-gfx] [PATCH -next] drm/i915/dsi: remove set but not used variable 'hfront_porch'
Fixes gcc '-Wunused-but-set-variable' warning: drivers/gpu/drm/i915/display/icl_dsi.c: In function 'gen11_dsi_set_transcoder_timings': drivers/gpu/drm/i915/display/icl_dsi.c:768:6: warning: variable 'hfront_porch' set but not used [-Wunused-but-set-variable] It is never used and can be removed. Reported-by: Hulk Robot Signed-off-by: YueHaibing --- drivers/gpu/drm/i915/display/icl_dsi.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index 4d952accfaaa..a42348be0438 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -763,7 +763,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, enum transcoder dsi_trans; /* horizontal timings */ u16 htotal, hactive, hsync_start, hsync_end, hsync_size; - u16 hfront_porch, hback_porch; + u16 hback_porch; /* vertical timings */ u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift; @@ -772,8 +772,6 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, hsync_start = adjusted_mode->crtc_hsync_start; hsync_end = adjusted_mode->crtc_hsync_end; hsync_size = hsync_end - hsync_start; - hfront_porch = (adjusted_mode->crtc_hsync_start - - adjusted_mode->crtc_hdisplay); hback_porch = (adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end); vactive = adjusted_mode->crtc_vdisplay; ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v1 10/11] drm/mediatek: direct include of drm.h in mtk_drm_gem.c
Hi, Sam: You could apply this patch into drm-misc-next by yourself, thanks. Regards, CK On Fri, 2019-07-19 at 09:30 +0800, CK Hu wrote: > On Thu, 2019-07-18 at 18:15 +0200, Sam Ravnborg wrote: > > Do not rely on including drm.h from drm_file.h, > > as the include in drm_file.h will be dropped. > > > > Acked-by: CK Hu > > > Signed-off-by: Sam Ravnborg > > Cc: CK Hu > > Cc: Philipp Zabel > > Cc: Matthias Brugger > > Cc: linux-arm-ker...@lists.infradead.org > > Cc: linux-media...@lists.infradead.org > > --- > > drivers/gpu/drm/mediatek/mtk_drm_gem.c | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_gem.c > > b/drivers/gpu/drm/mediatek/mtk_drm_gem.c > > index 9434f88c6341..ca672f1d140d 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_gem.c > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_gem.c > > @@ -5,6 +5,7 @@ > > > > #include > > > > +#include > > #include > > #include > > #include > ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v1 10/11] drm/mediatek: direct include of drm.h in mtk_drm_gem.c
On Thu, 2019-07-18 at 18:15 +0200, Sam Ravnborg wrote: > Do not rely on including drm.h from drm_file.h, > as the include in drm_file.h will be dropped. > Acked-by: CK Hu > Signed-off-by: Sam Ravnborg > Cc: CK Hu > Cc: Philipp Zabel > Cc: Matthias Brugger > Cc: linux-arm-ker...@lists.infradead.org > Cc: linux-media...@lists.infradead.org > --- > drivers/gpu/drm/mediatek/mtk_drm_gem.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_gem.c > b/drivers/gpu/drm/mediatek/mtk_drm_gem.c > index 9434f88c6341..ca672f1d140d 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_gem.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_gem.c > @@ -5,6 +5,7 @@ > > #include > > +#include > #include > #include > #include ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [igt-dev] [PATCH V6 i-g-t 2/6] kms_writeback: Add initial writeback tests
On Thu, Jul 18, 2019 at 8:15 AM liviu.du...@arm.com wrote:
>
> On Thu, Jul 18, 2019 at 09:56:39AM +, Ser, Simon wrote:
> > On Thu, 2019-07-18 at 10:49 +0100, liviu.du...@arm.com wrote:
> > > On Wed, Jul 17, 2019 at 11:46:39AM +, Ser, Simon wrote:
> > > > Thanks for the clarification!
> > > >
> > > > On Tue, 2019-07-16 at 16:22 +0100, liviu.du...@arm.com wrote:
> > > > > > > > +static void invalid_out_fence(igt_output_t *output, igt_fb_t
> > > > > > > > *valid_fb, igt_fb_t *invalid_fb)
> > > > > > > > +{
> > > > > > > > + int i, ret;
> > > > > > > > + int32_t out_fence;
> > > > > > > > + struct {
> > > > > > > > + uint32_t fb_id;
> > > > > > > > + bool ptr_valid;
> > > > > > > > + int32_t *out_fence_ptr;
> > > > > > > > + } invalid_tests[] = {
> > > > > > > > + {
> > > > > > > > + /* No output buffer, but the
> > > > > > > > WRITEBACK_OUT_FENCE_PTR set. */
> > > > > > > > + .fb_id = 0,
> > > > > > > > + .ptr_valid = true,
> > > > > > > > + .out_fence_ptr = _fence,
> > > > > > > > + },
> > > > > > > > + {
> > > > > > > > + /* Invalid output buffer. */
> > > > > > > > + .fb_id = invalid_fb->fb_id,
> > > > > > > > + .ptr_valid = true,
> > > > > > > > + .out_fence_ptr = _fence,
> > > > > > > > + },
> > > > > > >
> > > > > > > This doesn't belong in this function (invalid_out_fence), since
> > > > > > > this
> > > > > > > checks an invalid framebuffer, not an invalid fence. We should
> > > > > > > probably
> > > > > > > move it to writeback_fb_id (and rename that function to test_fb?).
> > > > >
> > > > > It tries to test that you can't trick the driver to do any work on a
> > > > > fence if
> > > > > the framebuffer is invalid, so the set of tests tries: no fb with
> > > > > valid fence,
> > > > > invalid fb with valid fence, valid fb but invalid fence and assumes
> > > > > that no
> > > > > fb with invalid fence is a NOP anyway.
> > > >
> > > > Yeah, that makes sense, it's just confusing to put it in a function
> > > > named invalid_out_fence. Here the out fence is valid, but the output
> > > > buffer isn't, so it should probably be moved away (or this function
> > > > should be renamed).
> > >
> > > Don't want to offend or anything, but this does sound like bikeshedding.
> > > You
> > > have a couple of parameters that you want to have a test for because they
> > > are
> > > linked together (output framebuffer and fence) and you go through the
> > > combination of possible bad options in the test. Not sure what name we
> > > can use
> > > for the function, other than maybe 'test_invalid_parameters'? Given that
> > > 2/3
> > > tests an invalid out fence, the name was thought to be relevant.
> > >
> > > Having invalid out buffer test separate into its own test brings no
> > > benefits, IMHO.
> >
> > Well, the issue is that I've been confused when reviewing the patch
> > series. I had trouble understanding what the test does and why. I also
> > had trouble to identify that do_writeback_test never submits a
> > writeback operation (see other e-mail).
> >
> > A name that is relevant "all the time, most of the time", is not
> > relevant at all in my opinion. It just tricks the reader into thinking
> > the test does one thing, while it also does something else.
> >
> > If it would be obvious, I wouldn't mind. But here IMHO it hurts
> > readability. So I'd prefer to rename the function.
>
> I take your comments as a valid point.
>
> Does "test_invalid_parameters" sound like a good name for the function? Is so,
> Rodrigo, can you please use that name in the next revision of the patch?
Sure, I'll do that.
Thanks
> >
> > If you think it's obvious, then maybe it's just me. I'd love to hear
> > from others if they have a different opinion.
> >
> > (As a side note, I agree I have a tendency to bikeshed, I try to mark
> > my bikesheddings behind "nit:" flags.)
>
> I've only said "it sounded like" :)
>
> Best regards,
> Liviu
>
> >
> > > Best regards,
> > > Liviu
> > >
> > > > > > > > + {
> > > > > > > > + /* Invalid WRITEBACK_OUT_FENCE_PTR. */
> > > > > > > > + .fb_id = valid_fb->fb_id,
> > > > > > > > + .ptr_valid = false,
> > > > > > > > + .out_fence_ptr = (int32_t *)0x8,
> > > > > > > > + },
> > > > > > > > + };
> > > > > > > > +
> > > > > > > > + for (i = 0; i < ARRAY_SIZE(invalid_tests); i++) {
> > > > > > > > + ret = do_writeback_test(output,
> > > > > > > > DRM_MODE_ATOMIC_ALLOW_MODESET,
> > > > > > > > + invalid_tests[i].fb_id,
> > > > > > > > +
> > > > > > > > invalid_tests[i].out_fence_ptr,
> > > > > > > > + invalid_tests[i].ptr_valid);
> > > > > > > > + igt_assert(ret != 0);
> > > > > > >
> > > > > > > Maybe we can
Re: [Intel-gfx] [PATCH] drm/i915/vbt: Fix VBT parsing for the PSR section
Hi,
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This commit has been processed because it contains a "Fixes:" tag,
fixing commit: 88a0d9606aff drm/i915/vbt: Parse and use the new field with PSR2
TP2/3 wakeup time.
The bot has tested the following trees: v5.2.1.
v5.2.1: Failed to apply! Possible dependencies:
231dcffc234f ("drm/i915/bios: add BDB block comments before definitions")
843444ed1301 ("drm/i915/bios: sort BDB block definitions using block ID")
f87f6599c843 ("drm/i915/bios: reserve struct bdb_ prefix for BDB blocks")
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Re: [Intel-gfx] [PATCH 2/4] drm/i915: Use maximum write flush for pwrite_gtt
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v5.2.1: Failed to apply! Possible dependencies:
09407579abf5 ("drm/i915: Store the default sseu setup on the engine")
10be98a77c55 ("drm/i915: Move more GEM objects under gem/")
112ed2d31a46 ("drm/i915: Move GraphicsTechnology files under gt/")
5e5d2e209e08 ("drm/i915: Split GEM object type definition to its own
header")
6951e5893b48 ("drm/i915: Move GEM object domain management from
struct_mutex to local")
98932149aeb9 ("drm/i915: Move object->pages API to i915_gem_object.[ch]")
v5.1.18: Failed to apply! Possible dependencies:
10be98a77c55 ("drm/i915: Move more GEM objects under gem/")
112ed2d31a46 ("drm/i915: Move GraphicsTechnology files under gt/")
13f1bfd3b332 ("drm/i915: Make object/vma allocation caches global")
2caffbf11762 ("drm/i915: Revoke mmaps and prevent access to fence registers
across reset")
32eb6bcfdda9 ("drm/i915: Make request allocation caches global")
39e2f501c1b4 ("drm/i915: Split struct intel_context definition to its own
header")
5e5d2e209e08 ("drm/i915: Split GEM object type definition to its own
header")
6951e5893b48 ("drm/i915: Move GEM object domain management from
struct_mutex to local")
7ae1940014ef ("drm/i915: Defer removing fence register tracking to rpm
wakeup")
7e3d9a59410d ("drm/i915: Track active engines within a context")
7f4127c4839b ("drm/i915: Use time based guilty context banning")
98932149aeb9 ("drm/i915: Move object->pages API to i915_gem_object.[ch]")
ba4fda620a5f ("drm/i915: Optionally disable automatic recovery after a GPU
reset")
c2400ec3b6d1 ("drm/i915: add Makefile magic for testing headers are
self-contained")
v4.19.59: Failed to apply! Possible dependencies:
0e39037b3165 ("drm/i915: Cache the error string")
10be98a77c55 ("drm/i915: Move more GEM objects under gem/")
112ed2d31a46 ("drm/i915: Move GraphicsTechnology files under gt/")
16e4dd0342a8 ("drm/i915: Markup paired operations on wakerefs")
39e2f501c1b4 ("drm/i915: Split struct intel_context definition to its own
header")
52c0fdb25c7c ("drm/i915: Replace global breadcrumbs with per-context
interrupt tracking")
538ef96b9dae ("drm/i915/gem: Track the rpm wakerefs")
5e5d2e209e08 ("drm/i915: Split GEM object type definition to its own
header")
6951e5893b48 ("drm/i915: Move GEM object domain management from
struct_mutex to local")
6b048706f407 ("drm/i915: Forcibly flush unwanted requests in drop-caches")
87f1ef225242 ("drm/i915: Record the sseu configuration per-context &
engine")
95fd94a645f7 ("drm/i915: avoid rebuilding i915_gpu_error.o on version
string updates")
98932149aeb9 ("drm/i915: Move object->pages API to i915_gem_object.[ch]")
c0a6aa7ec2c3 ("drm/i915: Show actual alongside requested frequency in
debugfs/i915_rps_boost_info")
c2400ec3b6d1 ("drm/i915: add Makefile magic for testing headers are
self-contained")
c44301fce614 ("drm/i915: Allow control of PSR at runtime through debugfs,
v6")
cab870b7fdf3 ("drm/i915/ilk: Fix warning when reading emon_status with no
output")
e6154e4cb8b0 ("drm/i915: Skip the ERR_PTR error state")
eb8d0f5af4ec ("drm/i915: Remove GPU reset dependence on struct_mutex")
fb6f0b64e455 ("drm/i915: Prevent machine hang from Broxton's vtd w/a and
error capture")
v4.14.133: Failed to apply! Possible dependencies:
3bd4073524fa ("drm/i915: Consolidate get_fence with pin_fence")
465c403cb508 ("drm/i915: introduce simple gemfs")
66df1014efba ("drm/i915: Keep a small stash of preallocated WC pages")
7393b7ee3a9c ("drm/i915/debugfs: include some gtt page size metrics")
73ebd503034c ("drm/i915: make mappable struct resource centric")
7789422665f5 ("drm/i915: make dsm struct resource centric")
82ad6443a55e ("drm/i915/gtt: Rename i915_hw_ppgtt base member")
969b0950a188 ("drm/i915: Add interface to reserve fence registers for vGPU")
a65adaf8a834 ("drm/i915: Track user GTT faulting per-vma")
b1ace60107e6 ("drm/i915: give stolen_usable_size a more suitable home")
b7128ef125b4 ("drm/i915: prefer resource_size_t for everything stolen")
da1dd0dbe024 ("drm/i915: Make the report about a bogus stolen reserved area
an error")
db7fb60593e4 ("drm/i915: Check if the stolen memory "reserved" area is
enabled or not")
e91ef99b9543 ("drm/i915/selftests: Remember to create the fake preempt
context")
f773568b6ff8 ("drm/i915: nuke the duplicated stolen discovery")
v4.9.185: Failed to apply! Possible dependencies:
0e70447605f4 ("drm/i915: Move common code out of i915_gpu_error.c")
1b36595ffb35 ("drm/i915: Show RING registers through debugfs")
28a60dee2ce6 ("drm/i915/gvt: vGPU HW
Re: [Intel-gfx] [PATCH] drm/i915: Flush extra hard after writing relocations through the GTT
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Unable to calculate
v5.1.18: Failed to apply! Possible dependencies:
Unable to calculate
v4.19.59: Failed to apply! Possible dependencies:
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v4.14.133: Failed to apply! Possible dependencies:
3bd4073524fa ("drm/i915: Consolidate get_fence with pin_fence")
465c403cb508 ("drm/i915: introduce simple gemfs")
66df1014efba ("drm/i915: Keep a small stash of preallocated WC pages")
7393b7ee3a9c ("drm/i915/debugfs: include some gtt page size metrics")
73ebd503034c ("drm/i915: make mappable struct resource centric")
7789422665f5 ("drm/i915: make dsm struct resource centric")
82ad6443a55e ("drm/i915/gtt: Rename i915_hw_ppgtt base member")
969b0950a188 ("drm/i915: Add interface to reserve fence registers for vGPU")
a65adaf8a834 ("drm/i915: Track user GTT faulting per-vma")
b1ace60107e6 ("drm/i915: give stolen_usable_size a more suitable home")
b7128ef125b4 ("drm/i915: prefer resource_size_t for everything stolen")
da1dd0dbe024 ("drm/i915: Make the report about a bogus stolen reserved area
an error")
db7fb60593e4 ("drm/i915: Check if the stolen memory "reserved" area is
enabled or not")
e91ef99b9543 ("drm/i915/selftests: Remember to create the fake preempt
context")
f773568b6ff8 ("drm/i915: nuke the duplicated stolen discovery")
v4.9.185: Failed to apply! Possible dependencies:
04d348ae3f0a ("drm/i915/gvt: vGPU display virtualization")
12d14cc43b34 ("drm/i915/gvt: Introduce a framework for tracking HW
registers.")
28a60dee2ce6 ("drm/i915/gvt: vGPU HW resource management")
3f728236c516 ("drm/i915/gvt: trace stub")
4c7d62c6b8a2 ("drm/i915: Markup GEM API with lockdep asserts")
4d60c5fd3f87 ("drm/i915/gvt: vGPU PCI configuration space virtualization")
579cea5f30f2 ("drm/i915/gvt: golden virtual HW state management")
650bc63568e4 ("drm/i915: Amalgamate execbuffer parameter structures")
718659a63054 ("drm/i915: Rename some warts in the VMA API")
82d375d1b568 ("drm/i915/gvt: Introduce basic vGPU life cycle management")
8453d674ae7e ("drm/i915/gvt: vGPU execlist virtualization")
c8fe6a6811a7 ("drm/i915/gvt: vGPU interrupt virtualization.")
e39c5add3221 ("drm/i915/gvt: vGPU MMIO virtualization")
e473405783c0 ("drm/i915/gvt: vGPU workload scheduler")
e95433c73a11 ("drm/i915: Rearrange i915_wait_request() accounting with
callers")
v4.4.185: Failed to apply! Possible dependencies:
033908aed5a5 ("drm/i915: mark GEM object pages dirty when mapped & written
by the CPU")
058d88c4330f ("drm/i915: Track pinned VMA")
09cfcb456941 ("drm/i915: Split out load time HW initialization")
0a9d2bed5557 ("drm/i915/skl: Making DC6 entry is the last call in suspend
flow.")
188c1ab7769d ("drm/i915: Add struct_mutex locking for
debugs/i915_gem_framebuffer")
1f814daca43a ("drm/i915: add support for checking if we hold an RPM
reference")
31a39207f04a ("drm/i915: Cache kmap between relocations")
399bb5b6db02 ("drm/i915: Move allocation of various workqueues earlier
during init")
414b7999b8be ("drm/i915/gen9: Remove csr.state, csr_lock and related code.")
506a8e87d8d2 ("drm/i915: Add soft-pinning API for execbuffer")
62106b4f6b91 ("drm/i915: Rename dev_priv->gtt to dev_priv->ggtt")
72e96d6450c0 ("drm/i915: Refer to GGTT {,VM} consistently")
73dfc227ff5c ("drm/i915/skl: init/uninit display core as part of the HW
power domain state")
8da32727ac0e ("drm/i915: Remove i915_gem_obj_size")
934acce3c069 ("drm/i915: Avoid writing relocs with addresses in
non-canonical form")
9e2793f6e4e2 ("drm/i915: compile-time consistency check on __EXEC_OBJECT
flags")
ad5c3d3ffbb2 ("drm/i915: Move MCHBAR setup earlier during init")
bc87229f323e ("drm/i915/skl: enable PC9/10 power states during
suspend-to-idle")
be12a86b46e8 ("drm/i915: Show pin mapped status in describe_obj")
d50415cc6c83 ("drm/i915: Refactor execbuffer relocation writing")
f514c2d84285 ("drm/i915/gen9: flush DMC fw loading work during system
suspend")
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How should we proceed with this patch?
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Thanks,
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/dp/dsc: Add Support for all BPCs supported by TGL (rev3)
== Series Details == Series: drm/dp/dsc: Add Support for all BPCs supported by TGL (rev3) URL : https://patchwork.freedesktop.org/series/63526/ State : success == Summary == CI Bug Log - changes from CI_DRM_6506_full -> Patchwork_13693_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13693_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@bcs0-s3: - shard-kbl: [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6506/shard-kbl2/igt@gem_ctx_isolat...@bcs0-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13693/shard-kbl6/igt@gem_ctx_isolat...@bcs0-s3.html * igt@gem_ctx_isolation@rcs0-s3: - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([fdo#108566]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6506/shard-apl7/igt@gem_ctx_isolat...@rcs0-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13693/shard-apl1/igt@gem_ctx_isolat...@rcs0-s3.html * igt@i915_pm_rpm@i2c: - shard-hsw: [PASS][5] -> [FAIL][6] ([fdo#104097]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6506/shard-hsw6/igt@i915_pm_...@i2c.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13693/shard-hsw1/igt@i915_pm_...@i2c.html * igt@kms_cursor_edge_walk@pipe-a-128x128-bottom-edge: - shard-snb: [PASS][7] -> [SKIP][8] ([fdo#109271] / [fdo#109278]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6506/shard-snb5/igt@kms_cursor_edge_w...@pipe-a-128x128-bottom-edge.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13693/shard-snb4/igt@kms_cursor_edge_w...@pipe-a-128x128-bottom-edge.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite: - shard-iclb: [PASS][9] -> [FAIL][10] ([fdo#103167]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6506/shard-iclb1/igt@kms_frontbuffer_track...@fbc-1p-primscrn-cur-indfb-draw-pwrite.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13693/shard-iclb2/igt@kms_frontbuffer_track...@fbc-1p-primscrn-cur-indfb-draw-pwrite.html * igt@kms_frontbuffer_tracking@fbc-suspend: - shard-skl: [PASS][11] -> [INCOMPLETE][12] ([fdo#104108]) +2 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6506/shard-skl8/igt@kms_frontbuffer_track...@fbc-suspend.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13693/shard-skl9/igt@kms_frontbuffer_track...@fbc-suspend.html * igt@kms_psr@no_drrs: - shard-iclb: [PASS][13] -> [FAIL][14] ([fdo#108341]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6506/shard-iclb5/igt@kms_psr@no_drrs.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13693/shard-iclb1/igt@kms_psr@no_drrs.html * igt@kms_psr@psr2_basic: - shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109441]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6506/shard-iclb2/igt@kms_psr@psr2_basic.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13693/shard-iclb8/igt@kms_psr@psr2_basic.html * igt@kms_setmode@basic: - shard-skl: [PASS][17] -> [FAIL][18] ([fdo#99912]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6506/shard-skl7/igt@kms_setm...@basic.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13693/shard-skl6/igt@kms_setm...@basic.html Possible fixes * igt@gem_exec_flush@basic-wb-rw-default: - shard-iclb: [INCOMPLETE][19] ([fdo#107713]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6506/shard-iclb7/igt@gem_exec_fl...@basic-wb-rw-default.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13693/shard-iclb5/igt@gem_exec_fl...@basic-wb-rw-default.html * igt@gem_partial_pwrite_pread@writes-after-reads-snoop: - shard-iclb: [INCOMPLETE][21] ([fdo#107713] / [fdo#109100]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6506/shard-iclb1/igt@gem_partial_pwrite_pr...@writes-after-reads-snoop.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13693/shard-iclb2/igt@gem_partial_pwrite_pr...@writes-after-reads-snoop.html * igt@gem_tiled_swapping@non-threaded: - shard-glk: [DMESG-WARN][23] ([fdo#108686]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6506/shard-glk6/igt@gem_tiled_swapp...@non-threaded.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13693/shard-glk7/igt@gem_tiled_swapp...@non-threaded.html * igt@i915_suspend@fence-restore-tiled2untiled: - shard-apl: [DMESG-WARN][25] ([fdo#108566]) -> [PASS][26] +3 similar issues [25]:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: We don't need display's suspend/resume operations when !HAS_DISPLAY (rev5)
== Series Details ==
Series: drm/i915: We don't need display's suspend/resume operations when
!HAS_DISPLAY (rev5)
URL : https://patchwork.freedesktop.org/series/60839/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6507 -> Patchwork_13696
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13696/
Known issues
Here are the changes found in Patchwork_13696 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_create@basic-files:
- fi-icl-u2: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713] /
[fdo#109100])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6507/fi-icl-u2/igt@gem_ctx_cre...@basic-files.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13696/fi-icl-u2/igt@gem_ctx_cre...@basic-files.html
* igt@i915_selftest@live_contexts:
- fi-skl-iommu: [PASS][3] -> [INCOMPLETE][4] ([fdo#111050])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6507/fi-skl-iommu/igt@i915_selftest@live_contexts.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13696/fi-skl-iommu/igt@i915_selftest@live_contexts.html
* igt@kms_busy@basic-flip-c:
- fi-kbl-7500u: [PASS][5] -> [SKIP][6] ([fdo#109271] / [fdo#109278])
+2 similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6507/fi-kbl-7500u/igt@kms_b...@basic-flip-c.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13696/fi-kbl-7500u/igt@kms_b...@basic-flip-c.html
* igt@kms_chamelium@dp-hpd-fast:
- fi-kbl-7500u: [PASS][7] -> [DMESG-WARN][8] ([fdo#103558] /
[fdo#105602])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6507/fi-kbl-7500u/igt@kms_chamel...@dp-hpd-fast.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13696/fi-kbl-7500u/igt@kms_chamel...@dp-hpd-fast.html
Possible fixes
* igt@kms_chamelium@dp-edid-read:
- fi-kbl-7500u: [WARN][9] ([fdo#109483]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6507/fi-kbl-7500u/igt@kms_chamel...@dp-edid-read.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13696/fi-kbl-7500u/igt@kms_chamel...@dp-edid-read.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][11] ([fdo#109485]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6507/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13696/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@kms_frontbuffer_tracking@basic:
- {fi-icl-u4}:[FAIL][13] ([fdo#103167]) -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6507/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13696/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
[fdo#111050]: https://bugs.freedesktop.org/show_bug.cgi?id=111050
Participating hosts (53 -> 45)
--
Additional (1): fi-bsw-n3050
Missing(9): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan
fi-byt-clapper fi-icl-u3 fi-icl-y fi-icl-dsi fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6507 -> Patchwork_13696
CI_DRM_6507: a607eef7a42e6788090f1ff4de30ed821ad87ad9 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5102: 6038ace76016d8892f4d13aef5301f71ca1a6e2d @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13696: 95a35650cf1f2f54d2bb507c8c541d4f1ffb3c8d @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
95a35650cf1f drm/i915: We don't need display's suspend/resume operations when
!HAS_DISPLAY
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13696/
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Re: [Intel-gfx] [PATCH] drm/i915: We don't need display's suspend/resume operations when !HAS_DISPLAY
On Thu, Jul 18, 2019 at 10:25:51PM +0100, Chris Wilson wrote:
> Quoting Rodrigo Vivi (2019-07-18 22:14:45)
> > On Thu, Jul 18, 2019 at 09:58:16PM +0100, Chris Wilson wrote:
> > > Quoting Rodrigo Vivi (2019-07-18 21:49:12)
> > > > +void intel_display_power_resume_early(struct drm_i915_private *i915)
> > > > +{
> > > > + if (!HAS_DISPLAY(i915))
> > > > + return;
> > > > +
> > > > + if (INTEL_GEN(i915) >= 11 || IS_GEN9_LP(i915)) {
> > > > + gen9_sanitize_dc_state(i915);
> > >
> > > Are you sure that whatever state you are resuming from agrees with your
> > > notion of !display? The sanitize routines are supposed to be about
> > > cleaning up after third parties who don't play by the same rules.
> >
> > I don't expect any function setting any kind of dc states when we don't
> > have display. Besides the path that sets DC_STATE_EN is and neeeds to
> > be sanitized is also covered by this patch and this shouldn't happen.
> >
> > Or am I missing something else?
>
> It's not about us, it's about whatever else runs in between. And
> remember !HAS_DISPLAY() is also a user setting, not merely a reflection
> of probed hw.
ouch, we need to get rid of those runtime writes to info struct :/
I wonder if it worth to add a intel_display_sanitize to be called
when toggling info-num_pipes to 0 along with that DRM_ERROR...
or just call it before !HAS_DISPLAY with a XXX comment...
other ideas?
> -Chris
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Re: [Intel-gfx] [PATCH] drm/i915: We don't need display's suspend/resume operations when !HAS_DISPLAY
Quoting Rodrigo Vivi (2019-07-18 22:14:45)
> On Thu, Jul 18, 2019 at 09:58:16PM +0100, Chris Wilson wrote:
> > Quoting Rodrigo Vivi (2019-07-18 21:49:12)
> > > +void intel_display_power_resume_early(struct drm_i915_private *i915)
> > > +{
> > > + if (!HAS_DISPLAY(i915))
> > > + return;
> > > +
> > > + if (INTEL_GEN(i915) >= 11 || IS_GEN9_LP(i915)) {
> > > + gen9_sanitize_dc_state(i915);
> >
> > Are you sure that whatever state you are resuming from agrees with your
> > notion of !display? The sanitize routines are supposed to be about
> > cleaning up after third parties who don't play by the same rules.
>
> I don't expect any function setting any kind of dc states when we don't
> have display. Besides the path that sets DC_STATE_EN is and neeeds to
> be sanitized is also covered by this patch and this shouldn't happen.
>
> Or am I missing something else?
It's not about us, it's about whatever else runs in between. And
remember !HAS_DISPLAY() is also a user setting, not merely a reflection
of probed hw.
-Chris
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: We don't need display's suspend/resume operations when !HAS_DISPLAY (rev5)
== Series Details == Series: drm/i915: We don't need display's suspend/resume operations when !HAS_DISPLAY (rev5) URL : https://patchwork.freedesktop.org/series/60839/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: We don't need display's suspend/resume operations when !HAS_DISPLAY +drivers/gpu/drm/i915/display/intel_display_power.c:4440:6: warning: symbol 'hsw_enable_pc8' was not declared. Should it be static? +drivers/gpu/drm/i915/display/intel_display_power.c:4456:6: warning: symbol 'hsw_disable_pc8' was not declared. Should it be static? +drivers/gpu/drm/i915/display/intel_display_power.c:4556:6: warning: symbol 'bxt_display_core_init' was not declared. Should it be static? +drivers/gpu/drm/i915/display/intel_display_power.c:4588:6: warning: symbol 'bxt_display_core_uninit' was not declared. Should it be static? +drivers/gpu/drm/i915/display/intel_display_power.c:4679:6: warning: symbol 'icl_display_core_init' was not declared. Should it be static? +drivers/gpu/drm/i915/display/intel_display_power.c:4715:6: warning: symbol 'icl_display_core_uninit' was not declared. Should it be static? +drivers/gpu/drm/i915/display/intel_display_power.c:726:6: warning: symbol 'gen9_sanitize_dc_state' was not declared. Should it be static? +drivers/gpu/drm/i915/display/intel_display_power.c:786:6: warning: symbol 'bxt_enable_dc9' was not declared. Should it be static? +drivers/gpu/drm/i915/display/intel_display_power.c:801:6: warning: symbol 'bxt_disable_dc9' was not declared. Should it be static? +drivers/gpu/drm/i915/display/intel_display_power.c:855:6: warning: symbol 'gen9_enable_dc5' was not declared. Should it be static? +drivers/gpu/drm/i915/display/intel_display_power.c:879:6: warning: symbol 'skl_enable_dc6' was not declared. Should it be static? ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: We don't need display's suspend/resume operations when !HAS_DISPLAY
On Thu, Jul 18, 2019 at 09:58:16PM +0100, Chris Wilson wrote:
> Quoting Rodrigo Vivi (2019-07-18 21:49:12)
> > +void intel_display_power_resume_early(struct drm_i915_private *i915)
> > +{
> > + if (!HAS_DISPLAY(i915))
> > + return;
> > +
> > + if (INTEL_GEN(i915) >= 11 || IS_GEN9_LP(i915)) {
> > + gen9_sanitize_dc_state(i915);
>
> Are you sure that whatever state you are resuming from agrees with your
> notion of !display? The sanitize routines are supposed to be about
> cleaning up after third parties who don't play by the same rules.
I don't expect any function setting any kind of dc states when we don't
have display. Besides the path that sets DC_STATE_EN is and neeeds to
be sanitized is also covered by this patch and this shouldn't happen.
Or am I missing something else?
> -Chris
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Re: [Intel-gfx] [PATCH 03/22] drm/i915/tgl: update ddi/tc clock_off bits
On Fri, 2019-07-12 at 18:09 -0700, Lucas De Marchi wrote:
> From: Mahesh Kumar
>
> In GEN 12 PORT_C DDI clk_off bit is not equally distanced to A/B,
> it's at offset 24. Similarly TC port (5/6) clk off bits are at
> offset 22/23. Extend the macros to cover the additional ports.
>
Reviewed-by: Matt Atwood
> Cc: Matt Roper
> Signed-off-by: Mahesh Kumar
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/i915_reg.h | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index def71fd2e4d1..d873d9fbbf0e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9749,8 +9749,9 @@ enum skl_power_gate {
>
> #define ICL_DPCLKA_CFGCR0_MMIO(0x164280)
> #define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10,
> 11, 24))
> -#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) ==
> PORT_TC4 ? \
> - 21 : (tc_port) +
> 12))
> +#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 <<
> ((tc_port) < PORT_TC4 ? \
> +(tc_port) + 12 :
> \
> +(tc_port) -
> PORT_TC4 + 21))
> #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)((phy) * 2)
> #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 <<
> ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
> #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) <<
> ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
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Re: [Intel-gfx] [PATCH] drm/i915: We don't need display's suspend/resume operations when !HAS_DISPLAY
Quoting Rodrigo Vivi (2019-07-18 21:49:12)
> +void intel_display_power_resume_early(struct drm_i915_private *i915)
> +{
> + if (!HAS_DISPLAY(i915))
> + return;
> +
> + if (INTEL_GEN(i915) >= 11 || IS_GEN9_LP(i915)) {
> + gen9_sanitize_dc_state(i915);
Are you sure that whatever state you are resuming from agrees with your
notion of !display? The sanitize routines are supposed to be about
cleaning up after third parties who don't play by the same rules.
-Chris
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Re: [Intel-gfx] drm/i915/vbt: Fix VBT parsing for the PSR section
Tested-by: François Guerraz ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] vt: Grab console_lock around con_is_bound in show_bind
Am 18.07.2019 um 10:09 schrieb Daniel Vetter:
Not really harmful not to, but also not harm in grabbing the lock. And
this shuts up a new WARNING I introduced in commit ddde3c18b700 ("vt:
More locking checks").
Reported-by: Jens Remus
Cc: linux-ker...@vger.kernel.org
Cc: dri-de...@lists.freedesktop.org
Cc: linux-fb...@vger.kernel.org
Cc: linux-s...@vger.kernel.org
Cc: Greg Kroah-Hartman
Cc: Nicolas Pitre
Cc: Martin Hostettler
Cc: Adam Borowski
Cc: Mikulas Patocka
Signed-off-by: Daniel Vetter
Cc: Daniel Vetter
Cc: Sam Ravnborg
---
drivers/tty/vt/vt.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
Thank you for the quick fix! Looks fine to me. Did test with cat as well
as our dump2tar utility. The warning is gone.
Tested-by: Jens Remus
Regards,
Jens Remus
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Re: [Intel-gfx] drm/i915/vbt: Fix VBT parsing for the PSR section
Tested-by: François Guerraz On Dell XPS 9350 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: We don't need display's suspend/resume operations when !HAS_DISPLAY
Suspend resume is broken if we try to enable/disable dc9 on
cases with disabled displays.
v2: Make checkpatch happy:
- braces {} are not necessary for single statement blocks
v3: Also move hsw/bdw PC8 sequences since they are related to
display PM anyways. (Ville)
v4: Rebase after a long time, plus Move functions to the new
intel_display_power so we can stop exporting platform specific
functions as pointed by Jani.
v5: Remove unnecessary braces.
Cc: Ville Syrjälä
Cc: José Roberto de Souza
Cc: Jani Nikula
Signed-off-by: Rodrigo Vivi
---
.../drm/i915/display/intel_display_power.c| 67 +++
.../drm/i915/display/intel_display_power.h| 17 ++---
drivers/gpu/drm/i915/i915_drv.c | 58
3 files changed, 84 insertions(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 93a148684c53..530b119a3a3b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5189,3 +5189,70 @@ static void intel_power_domains_verify_state(struct
drm_i915_private *i915)
}
#endif
+
+void intel_display_power_suspend_late(struct drm_i915_private *i915)
+{
+ if (!HAS_DISPLAY(i915))
+ return;
+
+ if (INTEL_GEN(i915) >= 11 || IS_GEN9_LP(i915))
+ bxt_enable_dc9(i915);
+ else if (IS_HASWELL(i915) || IS_BROADWELL(i915))
+ hsw_enable_pc8(i915);
+}
+
+void intel_display_power_resume_early(struct drm_i915_private *i915)
+{
+ if (!HAS_DISPLAY(i915))
+ return;
+
+ if (INTEL_GEN(i915) >= 11 || IS_GEN9_LP(i915)) {
+ gen9_sanitize_dc_state(i915);
+ bxt_disable_dc9(i915);
+ } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
+ hsw_disable_pc8(i915);
+ }
+}
+
+void intel_display_power_suspend(struct drm_i915_private *i915)
+{
+ if (!HAS_DISPLAY(i915))
+ return;
+
+ if (INTEL_GEN(i915) >= 11) {
+ icl_display_core_uninit(i915);
+ bxt_enable_dc9(i915);
+ } else if (IS_GEN9_LP(i915)) {
+ bxt_display_core_uninit(i915);
+ bxt_enable_dc9(i915);
+ } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
+ hsw_enable_pc8(i915);
+ }
+}
+
+void intel_display_power_resume(struct drm_i915_private *i915)
+{
+ if (!HAS_DISPLAY(i915))
+ return;
+
+ if (INTEL_GEN(i915) >= 11) {
+ bxt_disable_dc9(i915);
+ icl_display_core_init(i915, true);
+ if (i915->csr.dmc_payload) {
+ if (i915->csr.allowed_dc_mask &
+ DC_STATE_EN_UPTO_DC6)
+ skl_enable_dc6(i915);
+ else if (i915->csr.allowed_dc_mask &
+DC_STATE_EN_UPTO_DC5)
+ gen9_enable_dc5(i915);
+ }
+ } else if (IS_GEN9_LP(i915)) {
+ bxt_disable_dc9(i915);
+ bxt_display_core_init(i915, true);
+ if (i915->csr.dmc_payload &&
+ (i915->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
+ gen9_enable_dc5(i915);
+ } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
+ hsw_disable_pc8(i915);
+ }
+}
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
b/drivers/gpu/drm/i915/display/intel_display_power.h
index e4d2c1ba24b0..97f2562fc5d3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -232,27 +232,20 @@ struct i915_power_domains {
for_each_power_well_reverse(__dev_priv, __power_well)
\
for_each_if((__power_well)->desc->domains & (__domain_mask))
-void skl_enable_dc6(struct drm_i915_private *dev_priv);
-void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
-void bxt_enable_dc9(struct drm_i915_private *dev_priv);
-void bxt_disable_dc9(struct drm_i915_private *dev_priv);
-void gen9_enable_dc5(struct drm_i915_private *dev_priv);
-
int intel_power_domains_init(struct drm_i915_private *dev_priv);
void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool
resume);
void intel_power_domains_driver_remove(struct drm_i915_private *dev_priv);
-void icl_display_core_init(struct drm_i915_private *dev_priv, bool resume);
-void icl_display_core_uninit(struct drm_i915_private *dev_priv);
void intel_power_domains_enable(struct drm_i915_private *dev_priv);
void intel_power_domains_disable(struct drm_i915_private *dev_priv);
void intel_power_domains_suspend(struct drm_i915_private *dev_priv,
enum i915_drm_suspend_mode);
void intel_power_domains_resume(struct
[Intel-gfx] [PATCH] drm/i915: We don't need display's suspend/resume operations when !HAS_DISPLAY
Suspend resume is broken if we try to enable/disable dc9 on
cases with disabled displays.
v2: Make checkpatch happy:
- braces {} are not necessary for single statement blocks
v3: Also move hsw/bdw PC8 sequences since they are related to
display PM anyways. (Ville)
v4: Rebase after a long time, plus Move functions to the new
intel_display_power so we can stop exporting platform specific
functions as pointed by Jani.
Cc: Ville Syrjälä
Cc: José Roberto de Souza
Cc: Jani Nikula
Signed-off-by: Rodrigo Vivi
---
.../drm/i915/display/intel_display_power.c| 67 +++
.../drm/i915/display/intel_display_power.h| 17 ++---
drivers/gpu/drm/i915/i915_drv.c | 56
3 files changed, 84 insertions(+), 56 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 93a148684c53..530b119a3a3b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5189,3 +5189,70 @@ static void intel_power_domains_verify_state(struct
drm_i915_private *i915)
}
#endif
+
+void intel_display_power_suspend_late(struct drm_i915_private *i915)
+{
+ if (!HAS_DISPLAY(i915))
+ return;
+
+ if (INTEL_GEN(i915) >= 11 || IS_GEN9_LP(i915))
+ bxt_enable_dc9(i915);
+ else if (IS_HASWELL(i915) || IS_BROADWELL(i915))
+ hsw_enable_pc8(i915);
+}
+
+void intel_display_power_resume_early(struct drm_i915_private *i915)
+{
+ if (!HAS_DISPLAY(i915))
+ return;
+
+ if (INTEL_GEN(i915) >= 11 || IS_GEN9_LP(i915)) {
+ gen9_sanitize_dc_state(i915);
+ bxt_disable_dc9(i915);
+ } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
+ hsw_disable_pc8(i915);
+ }
+}
+
+void intel_display_power_suspend(struct drm_i915_private *i915)
+{
+ if (!HAS_DISPLAY(i915))
+ return;
+
+ if (INTEL_GEN(i915) >= 11) {
+ icl_display_core_uninit(i915);
+ bxt_enable_dc9(i915);
+ } else if (IS_GEN9_LP(i915)) {
+ bxt_display_core_uninit(i915);
+ bxt_enable_dc9(i915);
+ } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
+ hsw_enable_pc8(i915);
+ }
+}
+
+void intel_display_power_resume(struct drm_i915_private *i915)
+{
+ if (!HAS_DISPLAY(i915))
+ return;
+
+ if (INTEL_GEN(i915) >= 11) {
+ bxt_disable_dc9(i915);
+ icl_display_core_init(i915, true);
+ if (i915->csr.dmc_payload) {
+ if (i915->csr.allowed_dc_mask &
+ DC_STATE_EN_UPTO_DC6)
+ skl_enable_dc6(i915);
+ else if (i915->csr.allowed_dc_mask &
+DC_STATE_EN_UPTO_DC5)
+ gen9_enable_dc5(i915);
+ }
+ } else if (IS_GEN9_LP(i915)) {
+ bxt_disable_dc9(i915);
+ bxt_display_core_init(i915, true);
+ if (i915->csr.dmc_payload &&
+ (i915->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
+ gen9_enable_dc5(i915);
+ } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
+ hsw_disable_pc8(i915);
+ }
+}
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
b/drivers/gpu/drm/i915/display/intel_display_power.h
index e4d2c1ba24b0..97f2562fc5d3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -232,27 +232,20 @@ struct i915_power_domains {
for_each_power_well_reverse(__dev_priv, __power_well)
\
for_each_if((__power_well)->desc->domains & (__domain_mask))
-void skl_enable_dc6(struct drm_i915_private *dev_priv);
-void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
-void bxt_enable_dc9(struct drm_i915_private *dev_priv);
-void bxt_disable_dc9(struct drm_i915_private *dev_priv);
-void gen9_enable_dc5(struct drm_i915_private *dev_priv);
-
int intel_power_domains_init(struct drm_i915_private *dev_priv);
void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool
resume);
void intel_power_domains_driver_remove(struct drm_i915_private *dev_priv);
-void icl_display_core_init(struct drm_i915_private *dev_priv, bool resume);
-void icl_display_core_uninit(struct drm_i915_private *dev_priv);
void intel_power_domains_enable(struct drm_i915_private *dev_priv);
void intel_power_domains_disable(struct drm_i915_private *dev_priv);
void intel_power_domains_suspend(struct drm_i915_private *dev_priv,
enum i915_drm_suspend_mode);
void intel_power_domains_resume(struct drm_i915_private *dev_priv);
-void
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Flush extra hard after writing relocations through the GTT
== Series Details ==
Series: drm/i915: Flush extra hard after writing relocations through the GTT
URL : https://patchwork.freedesktop.org/series/63914/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6507 -> Patchwork_13695
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13695/
Known issues
Here are the changes found in Patchwork_13695 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_basic@create-close:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6507/fi-icl-u3/igt@gem_ba...@create-close.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13695/fi-icl-u3/igt@gem_ba...@create-close.html
Possible fixes
* igt@i915_pm_rpm@module-reload:
- fi-icl-dsi: [INCOMPLETE][3] ([fdo#107713] / [fdo#108840]) ->
[PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6507/fi-icl-dsi/igt@i915_pm_...@module-reload.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13695/fi-icl-dsi/igt@i915_pm_...@module-reload.html
* igt@kms_chamelium@dp-edid-read:
- fi-kbl-7500u: [WARN][5] ([fdo#109483]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6507/fi-kbl-7500u/igt@kms_chamel...@dp-edid-read.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13695/fi-kbl-7500u/igt@kms_chamel...@dp-edid-read.html
* igt@kms_frontbuffer_tracking@basic:
- {fi-icl-u4}:[FAIL][7] ([fdo#103167]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6507/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13695/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
Participating hosts (53 -> 47)
--
Additional (1): fi-bsw-n3050
Missing(7): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6507 -> Patchwork_13695
CI_DRM_6507: a607eef7a42e6788090f1ff4de30ed821ad87ad9 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5102: 6038ace76016d8892f4d13aef5301f71ca1a6e2d @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13695: de07dfecc2ae9935216c545ff0a480130a730a7c @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
de07dfecc2ae drm/i915: Flush extra hard after writing relocations through the
GTT
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13695/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 01/22] drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization
On Fri, 2019-07-12 at 18:09 -0700, Lucas De Marchi wrote:
> According to the spec when initializing the display in TGL we should
> not
> set PORT_CL_DW12 for the Aux channel of the combo PHYs. We will re-
> use the
> power well hooks from ICL so only set this register on gen < 12.
>
> v2: Generalize check for gen 12 (suggested by José)
> v3: Rebase after enum phy introduction
>
Reviewed-by: Matt Atwood
> Cc: Imre Deak
> Cc: Matt Roper
> Signed-off-by: Lucas De Marchi
> Reviewed-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/display/intel_display_power.c | 12
> 1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 93a148684c53..dd2a50b8ba0a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -458,8 +458,10 @@ icl_combo_phy_aux_power_well_enable(struct
> drm_i915_private *dev_priv,
> val = I915_READ(regs->driver);
> I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx));
>
> - val = I915_READ(ICL_PORT_CL_DW12(phy));
> - I915_WRITE(ICL_PORT_CL_DW12(phy), val | ICL_LANE_ENABLE_AUX);
> + if (INTEL_GEN(dev_priv) < 12) {
> + val = I915_READ(ICL_PORT_CL_DW12(phy));
> + I915_WRITE(ICL_PORT_CL_DW12(phy), val |
> ICL_LANE_ENABLE_AUX);
> + }
>
> hsw_wait_for_power_well_enable(dev_priv, power_well);
>
> @@ -487,8 +489,10 @@ icl_combo_phy_aux_power_well_disable(struct
> drm_i915_private *dev_priv,
> enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx);
> u32 val;
>
> - val = I915_READ(ICL_PORT_CL_DW12(phy));
> - I915_WRITE(ICL_PORT_CL_DW12(phy), val & ~ICL_LANE_ENABLE_AUX);
> + if (INTEL_GEN(dev_priv) < 12) {
> + val = I915_READ(ICL_PORT_CL_DW12(phy));
> + I915_WRITE(ICL_PORT_CL_DW12(phy), val &
> ~ICL_LANE_ENABLE_AUX);
> + }
>
> val = I915_READ(regs->driver);
> I915_WRITE(regs->driver, val & ~HSW_PWR_WELL_CTL_REQ(pw_idx));
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 02/22] drm/i915/tgl: select correct bit for port select
On Fri, 2019-07-12 at 18:09 -0700, Lucas De Marchi wrote:
> From: Mahesh Kumar
>
> Bit definitions for port-select got changed for TRANS_CLK_SEL &
> TRANS_DDI_FUNC_CTL registers in TGL.
>
> v2 (Lucas):
> - Nuke TRANS_DDI_PORT_NONE since it's 0: we are already clearing
> {TGL_,}TRANS_DDI_PORT_MASK (suggested by Ville)
> - Also cover haswell_get_ddi_port_state() in intel_display.c that
> was
> missing
> - Define macros using the _SHIFT macros so we don't lose other
> users
>
Reviewed-by: Matt Atwood
> Cc: Ville Syrjälä
> Signed-off-by: Mahesh Kumar
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 47 +++---
> --
> drivers/gpu/drm/i915/display/intel_display.c | 6 ++-
> drivers/gpu/drm/i915/i915_reg.h | 11 +++--
> 3 files changed, 50 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 8445244aa593..339c01e567ab 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1773,7 +1773,10 @@ void intel_ddi_enable_transcoder_func(const
> struct intel_crtc_state *crtc_state)
>
> /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode
> */
> temp = TRANS_DDI_FUNC_ENABLE;
> - temp |= TRANS_DDI_SELECT_PORT(port);
> + if (INTEL_GEN(dev_priv) >= 12)
> + temp |= TGL_TRANS_DDI_SELECT_PORT(port);
> + else
> + temp |= TRANS_DDI_SELECT_PORT(port);
>
> switch (crtc_state->pipe_bpp) {
> case 18:
> @@ -1853,8 +1856,13 @@ void intel_ddi_disable_transcoder_func(const
> struct intel_crtc_state *crtc_state
> i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
> u32 val = I915_READ(reg);
>
> - val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK |
> TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
> - val |= TRANS_DDI_PORT_NONE;
> + if (INTEL_GEN(dev_priv) >= 12) {
> + val &= ~(TRANS_DDI_FUNC_ENABLE |
> TGL_TRANS_DDI_PORT_MASK |
> + TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
> + } else {
> + val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK |
> + TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
> + }
> I915_WRITE(reg, val);
>
> if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
> @@ -2006,10 +2014,19 @@ static void
> intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
> mst_pipe_mask = 0;
> for_each_pipe(dev_priv, p) {
> enum transcoder cpu_transcoder = (enum transcoder)p;
> + unsigned int port_mask, ddi_select;
> +
> + if (INTEL_GEN(dev_priv) >= 12) {
> + port_mask = TGL_TRANS_DDI_PORT_MASK;
> + ddi_select = TGL_TRANS_DDI_SELECT_PORT(port);
> + } else {
> + port_mask = TRANS_DDI_PORT_MASK;
> + ddi_select = TRANS_DDI_SELECT_PORT(port);
> + }
>
> tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
>
> - if ((tmp & TRANS_DDI_PORT_MASK) !=
> TRANS_DDI_SELECT_PORT(port))
> + if ((tmp & port_mask) != ddi_select)
> continue;
>
> if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
> @@ -2126,9 +2143,14 @@ void intel_ddi_enable_pipe_clock(const struct
> intel_crtc_state *crtc_state)
> enum port port = encoder->port;
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>
> - if (cpu_transcoder != TRANSCODER_EDP)
> - I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
> -TRANS_CLK_SEL_PORT(port));
> + if (cpu_transcoder != TRANSCODER_EDP) {
> + if (INTEL_GEN(dev_priv) >= 12)
> + I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
> +TGL_TRANS_CLK_SEL_PORT(port));
> + else
> + I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
> +TRANS_CLK_SEL_PORT(port));
> + }
> }
>
> void intel_ddi_disable_pipe_clock(const struct intel_crtc_state
> *crtc_state)
> @@ -2136,9 +2158,14 @@ void intel_ddi_disable_pipe_clock(const struct
> intel_crtc_state *crtc_state)
> struct drm_i915_private *dev_priv = to_i915(crtc_state-
> >base.crtc->dev);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>
> - if (cpu_transcoder != TRANSCODER_EDP)
> - I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
> -TRANS_CLK_SEL_DISABLED);
> + if (cpu_transcoder != TRANSCODER_EDP) {
> + if (INTEL_GEN(dev_priv) >= 12)
> + I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
> +TGL_TRANS_CLK_SEL_DISABLED);
> + else
> + I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
> +TRANS_CLK_SEL_DISABLED);
> + }
> }
>
> static void
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/1] drm/vblank: drop use of DRM_WAIT_ON()
== Series Details ==
Series: series starting with [1/1] drm/vblank: drop use of DRM_WAIT_ON()
URL : https://patchwork.freedesktop.org/series/63913/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6507 -> Patchwork_13694
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13694/
Known issues
Here are the changes found in Patchwork_13694 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6507/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13694/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html
* igt@prime_vgem@basic-fence-flip:
- fi-ilk-650: [PASS][3] -> [DMESG-WARN][4] ([fdo#106387])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6507/fi-ilk-650/igt@prime_v...@basic-fence-flip.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13694/fi-ilk-650/igt@prime_v...@basic-fence-flip.html
Possible fixes
* igt@i915_pm_rpm@module-reload:
- fi-icl-dsi: [INCOMPLETE][5] ([fdo#107713] / [fdo#108840]) ->
[PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6507/fi-icl-dsi/igt@i915_pm_...@module-reload.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13694/fi-icl-dsi/igt@i915_pm_...@module-reload.html
* igt@kms_chamelium@dp-edid-read:
- fi-kbl-7500u: [WARN][7] ([fdo#109483]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6507/fi-kbl-7500u/igt@kms_chamel...@dp-edid-read.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13694/fi-kbl-7500u/igt@kms_chamel...@dp-edid-read.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][9] ([fdo#109485]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6507/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13694/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@kms_frontbuffer_tracking@basic:
- {fi-icl-u4}:[FAIL][11] ([fdo#103167]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6507/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13694/fi-icl-u4/igt@kms_frontbuffer_track...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#106387]: https://bugs.freedesktop.org/show_bug.cgi?id=106387
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
Participating hosts (53 -> 47)
--
Additional (1): fi-bsw-n3050
Missing(7): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-icl-y
fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6507 -> Patchwork_13694
CI_DRM_6507: a607eef7a42e6788090f1ff4de30ed821ad87ad9 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5102: 6038ace76016d8892f4d13aef5301f71ca1a6e2d @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13694: d52a61072bb50e83ea8d1e82dffe1b55ff8f7a70 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
d52a61072bb5 drm/vblank: drop use of DRM_WAIT_ON()
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13694/
___
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: YCbCr output fixes and prep work for YCbCr 4:4:4 output (rev2)
== Series Details == Series: drm/i915: YCbCr output fixes and prep work for YCbCr 4:4:4 output (rev2) URL : https://patchwork.freedesktop.org/series/63893/ State : success == Summary == CI Bug Log - changes from CI_DRM_6504_full -> Patchwork_13692_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13692_full that come from known issues: ### IGT changes ### Issues hit * igt@i915_selftest@live_hangcheck: - shard-iclb: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713] / [fdo#108569]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/shard-iclb7/igt@i915_selftest@live_hangcheck.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13692/shard-iclb8/igt@i915_selftest@live_hangcheck.html * igt@kms_flip@modeset-vs-vblank-race-interruptible: - shard-glk: [PASS][3] -> [FAIL][4] ([fdo#103060]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/shard-glk1/igt@kms_f...@modeset-vs-vblank-race-interruptible.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13692/shard-glk7/igt@kms_f...@modeset-vs-vblank-race-interruptible.html - shard-iclb: [PASS][5] -> [INCOMPLETE][6] ([fdo#107713]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/shard-iclb5/igt@kms_f...@modeset-vs-vblank-race-interruptible.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13692/shard-iclb7/igt@kms_f...@modeset-vs-vblank-race-interruptible.html * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render: - shard-iclb: [PASS][7] -> [FAIL][8] ([fdo#103167]) +5 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/shard-iclb8/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-indfb-draw-render.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13692/shard-iclb4/igt@kms_frontbuffer_track...@fbc-1p-offscren-pri-indfb-draw-render.html * igt@kms_frontbuffer_tracking@fbc-stridechange: - shard-snb: [PASS][9] -> [SKIP][10] ([fdo#109271]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/shard-snb6/igt@kms_frontbuffer_track...@fbc-stridechange.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13692/shard-snb1/igt@kms_frontbuffer_track...@fbc-stridechange.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - shard-kbl: [PASS][11] -> [DMESG-WARN][12] ([fdo#108566]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/shard-kbl2/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13692/shard-kbl6/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-apl: [PASS][13] -> [DMESG-WARN][14] ([fdo#108566]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/shard-apl6/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13692/shard-apl8/igt@kms_pl...@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [PASS][15] -> [FAIL][16] ([fdo#108145]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/shard-skl10/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13692/shard-skl6/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html * igt@kms_psr@psr2_cursor_mmap_cpu: - shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#109441]) +4 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13692/shard-iclb7/igt@kms_psr@psr2_cursor_mmap_cpu.html * igt@perf@polling: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#110728]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/shard-skl10/igt@p...@polling.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13692/shard-skl6/igt@p...@polling.html Possible fixes * igt@gem_ctx_isolation@vcs0-s3: - shard-kbl: [DMESG-WARN][21] ([fdo#108566]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/shard-kbl6/igt@gem_ctx_isolat...@vcs0-s3.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13692/shard-kbl1/igt@gem_ctx_isolat...@vcs0-s3.html * igt@i915_pm_rpm@i2c: - shard-hsw: [FAIL][23] ([fdo#104097]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/shard-hsw6/igt@i915_pm_...@i2c.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13692/shard-hsw6/igt@i915_pm_...@i2c.html * igt@kms_cursor_legacy@cursor-vs-flip-atomic: - shard-hsw:
[Intel-gfx] [PATCH] drm/i915: Flush extra hard after writing relocations through the GTT
Recently discovered in commit bdae33b8b82b ("drm/i915: Use maximum write
flush for pwrite_gtt") was that we needed to our full write barrier
before changing the GGTT PTE to ensure that our indirect writes through
the GTT landed before the PTE changed (and the writes end up in a
different page). That also applies to our GGTT relocation path.
Signed-off-by: Chris Wilson
Cc: sta...@vger.kernel.org
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 8a2047c4e7c3..01901dad33f7 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -1019,11 +1019,12 @@ static void reloc_cache_reset(struct reloc_cache *cache)
kunmap_atomic(vaddr);
i915_gem_object_finish_access((struct drm_i915_gem_object
*)cache->node.mm);
} else {
- wmb();
+ struct i915_ggtt *ggtt = cache_to_ggtt(cache);
+
+ intel_gt_flush_ggtt_writes(ggtt->vm.gt);
io_mapping_unmap_atomic((void __iomem *)vaddr);
- if (cache->node.allocated) {
- struct i915_ggtt *ggtt = cache_to_ggtt(cache);
+ if (cache->node.allocated) {
ggtt->vm.clear_range(>vm,
cache->node.start,
cache->node.size);
@@ -1078,6 +1079,7 @@ static void *reloc_iomap(struct drm_i915_gem_object *obj,
void *vaddr;
if (cache->vaddr) {
+ intel_gt_flush_ggtt_writes(ggtt->vm.gt);
io_mapping_unmap_atomic((void __force __iomem *)
unmask_page(cache->vaddr));
} else {
struct i915_vma *vma;
@@ -1119,7 +1121,6 @@ static void *reloc_iomap(struct drm_i915_gem_object *obj,
offset = cache->node.start;
if (cache->node.allocated) {
- wmb();
ggtt->vm.insert_page(>vm,
i915_gem_object_get_dma_address(obj, page),
offset, I915_CACHE_NONE, 0);
--
2.22.0
___
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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/1] drm/vblank: drop use of DRM_WAIT_ON()
== Series Details == Series: series starting with [1/1] drm/vblank: drop use of DRM_WAIT_ON() URL : https://patchwork.freedesktop.org/series/63913/ State : warning == Summary == $ dim checkpatch origin/drm-tip d52a61072bb5 drm/vblank: drop use of DRM_WAIT_ON() -:55: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #55: FILE: drivers/gpu/drm/drm_vblank.c:1676: + wait = wait_event_interruptible_timeout(vblank->queue, + vblank_passed(drm_vblank_count(dev, pipe), req_seq) || total: 0 errors, 0 warnings, 1 checks, 58 lines checked ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/1] drm/vblank: drop use of DRM_WAIT_ON()
From e6f70cb90e0c3c90d45017a8257353652b7e0dcc Mon Sep 17 00:00:00 2001
From: Sam Ravnborg
Date: Thu, 30 May 2019 09:38:47 +0200
Subject: [PATCH] drm/vblank: drop use of DRM_WAIT_ON()
DRM_WAIT_ON() is from the deprecated drm_os_linux header and
the modern replacement is the wait_event_*.
The return values differ, so a conversion is needed to
keep the original interface towards userspace.
Introduced a switch/case to make code obvious and to allow
different debug prints depending on the result.
Signed-off-by: Sam Ravnborg
Reviewed-by: Sean Paul
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: David Airlie
Cc: Daniel Vetter
---
To verify if it works with the fix.
(Added wat variable to handle the situation where we never wait)
Sam
drivers/gpu/drm/drm_vblank.c | 32 ++--
1 file changed, 22 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/drm_vblank.c b/drivers/gpu/drm/drm_vblank.c
index 603ab105125d..4e83f1dfd446 100644
--- a/drivers/gpu/drm/drm_vblank.c
+++ b/drivers/gpu/drm/drm_vblank.c
@@ -31,7 +31,6 @@
#include
#include
#include
-#include
#include
#include "drm_internal.h"
@@ -1576,7 +1575,7 @@ int drm_wait_vblank_ioctl(struct drm_device *dev, void
*data,
struct drm_crtc *crtc;
struct drm_vblank_crtc *vblank;
union drm_wait_vblank *vblwait = data;
- int ret;
+ int ret, wait;
u64 req_seq, seq;
unsigned int pipe_index;
unsigned int flags, pipe, high_pipe;
@@ -1669,22 +1668,35 @@ int drm_wait_vblank_ioctl(struct drm_device *dev, void
*data,
return drm_queue_vblank_event(dev, pipe, req_seq, vblwait,
file_priv);
}
+ wait = 1;
if (req_seq != seq) {
DRM_DEBUG("waiting on vblank count %llu, crtc %u\n",
req_seq, pipe);
- DRM_WAIT_ON(ret, vblank->queue, 3 * HZ,
- vblank_passed(drm_vblank_count(dev, pipe),
- req_seq) ||
- !READ_ONCE(vblank->enabled));
+ wait = wait_event_interruptible_timeout(vblank->queue,
+ vblank_passed(drm_vblank_count(dev, pipe), req_seq) ||
+ !READ_ONCE(vblank->enabled),
+ msecs_to_jiffies(3000));
}
- if (ret != -EINTR) {
+ switch (wait) {
+ case 0:
+ /* timeout */
+ ret = -EBUSY;
drm_wait_vblank_reply(dev, pipe, >reply);
-
- DRM_DEBUG("crtc %d returning %u to client\n",
+ DRM_DEBUG("timeout waiting for vblank. crtc %d returning %u to
client\n",
pipe, vblwait->reply.sequence);
- } else {
+ break;
+ case -ERESTARTSYS:
+ /* interrupted by signal */
+ ret = -EINTR;
DRM_DEBUG("crtc %d vblank wait interrupted by signal\n", pipe);
+ break;
+ default:
+ ret = 0;
+ drm_wait_vblank_reply(dev, pipe, >reply);
+ DRM_DEBUG("crtc %d returning %u to client\n",
+ pipe, vblwait->reply.sequence);
+ break;
}
done:
--
2.20.1
___
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/dp/dsc: Add Support for all BPCs supported by TGL (rev3)
== Series Details == Series: drm/dp/dsc: Add Support for all BPCs supported by TGL (rev3) URL : https://patchwork.freedesktop.org/series/63526/ State : success == Summary == CI Bug Log - changes from CI_DRM_6506 -> Patchwork_13693 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13693/ Known issues Here are the changes found in Patchwork_13693 that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_create@basic-files: - fi-icl-guc: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713] / [fdo#109100]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6506/fi-icl-guc/igt@gem_ctx_cre...@basic-files.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13693/fi-icl-guc/igt@gem_ctx_cre...@basic-files.html * igt@kms_chamelium@dp-edid-read: - fi-cml-u2: [PASS][3] -> [FAIL][4] ([fdo#109483]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6506/fi-cml-u2/igt@kms_chamel...@dp-edid-read.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13693/fi-cml-u2/igt@kms_chamel...@dp-edid-read.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [PASS][5] -> [FAIL][6] ([fdo#109485]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6506/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13693/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html Possible fixes * igt@kms_chamelium@dp-crc-fast: - fi-kbl-7500u: [FAIL][7] ([fdo#109635 ]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6506/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13693/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html * igt@kms_frontbuffer_tracking@basic: - fi-icl-u2: [FAIL][9] ([fdo#103167]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6506/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13693/fi-icl-u2/igt@kms_frontbuffer_track...@basic.html Warnings * igt@i915_pm_rpm@basic-pci-d3-state: - fi-kbl-guc: [FAIL][11] ([fdo#107707]) -> [SKIP][12] ([fdo#109271]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6506/fi-kbl-guc/igt@i915_pm_...@basic-pci-d3-state.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13693/fi-kbl-guc/igt@i915_pm_...@basic-pci-d3-state.html [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#107707]: https://bugs.freedesktop.org/show_bug.cgi?id=107707 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483 [fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485 [fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635 Participating hosts (54 -> 47) -- Missing(7): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus Build changes - * Linux: CI_DRM_6506 -> Patchwork_13693 CI_DRM_6506: a61b72b18433922659d924e66c3ea75ae3ae @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5102: 6038ace76016d8892f4d13aef5301f71ca1a6e2d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13693: 6db3e61a993182318d85e7f29dd718864e20507e @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 6db3e61a9931 drm/dp/dsc: Add Support for all BPCs supported by TGL == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13693/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/4] drm/i915: Use maximum write flush for pwrite_gtt
Quoting Ville Syrjälä (2019-07-18 19:28:43)
> On Thu, Jul 18, 2019 at 03:54:05PM +0100, Chris Wilson wrote:
> > As recently disovered by forcing big-core (!llc) machines to use the GTT
> > paths, we need our full GTT write flush before manipulating the GTT PTE
> > or else the writes may be directed to the wrong page.
> >
> > Signed-off-by: Chris Wilson
> > Cc: Joonas Lahtinen
> > Cc: Matthew Auld
> > Cc: Ville Syrjälä
> > Cc: sta...@vger.kernel.org
> > ---
> > drivers/gpu/drm/i915/i915_gem.c | 5 +++--
> > 1 file changed, 3 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_gem.c
> > b/drivers/gpu/drm/i915/i915_gem.c
> > index fed0bc421a55..c6ba350e6e4f 100644
> > --- a/drivers/gpu/drm/i915/i915_gem.c
> > +++ b/drivers/gpu/drm/i915/i915_gem.c
> > @@ -610,7 +610,8 @@ i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object
> > *obj,
> > unsigned int page_length = PAGE_SIZE - page_offset;
> > page_length = remain < page_length ? remain : page_length;
> > if (node.allocated) {
> > - wmb(); /* flush the write before we modify the GGTT */
> > + /* flush the write before we modify the GGTT */
> > + intel_gt_flush_ggtt_writes(ggtt->vm.gt);
>
> Matches the story told by intel_gt_flush_ggtt_writes().
>
> Reviewed-by: Ville Syrjälä
Ta, pushed to dinq. Hopefully, this may explain some mystery fails!
(Not that any sane userspace does for(;;) { gem_write(); gem_read(); })
-Chris
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Re: [Intel-gfx] [PATCH] drm/i915/vbt: Fix VBT parsing for the PSR section
On Wed, Jul 17, 2019 at 03:34:51PM -0700, Dhinakaran Pandiyan wrote:
> A single 32-bit PSR2 training pattern field follows the sixteen element
> array of PSR table entries in the VBT spec. But, we incorrectly define
> this PSR2 field for each of the PSR table entries. As a result, the PSR1
> training pattern duration for any panel_type != 0 will be parsed
> incorrectly. Secondly, PSR2 training pattern durations for VBTs with bdb
> version >= 226 will also be wrong.
>
> Cc: Rodrigo Vivi
> Cc: José Roberto de Souza
> Cc: sta...@vger.kernel.org
> Cc: sta...@vger.kernel.org #v5.2
> Fixes: 88a0d9606aff ("drm/i915/vbt: Parse and use the new field with PSR2
> TP2/3 wakeup time")
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111088
> Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=204183
> Signed-off-by: Dhinakaran Pandiyan
> Reviewed-by: Ville Syrjälä
> Reviewed-by: José Roberto de Souza
> Acked-by: Rodrigo Vivi
> Tested-by: François Guerraz
pushed, thanks for the patches, reviews and tests.
> ---
> Drivers/gpu/drm/i915/display/intel_bios.c | 2 +-
> drivers/gpu/drm/i915/display/intel_vbt_defs.h | 6 +++---
> 2 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index 21501d565327..b416b394b641 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -766,7 +766,7 @@ parse_psr(struct drm_i915_private *dev_priv, const struct
> bdb_header *bdb)
> }
>
> if (bdb->version >= 226) {
> - u32 wakeup_time = psr_table->psr2_tp2_tp3_wakeup_time;
> + u32 wakeup_time = psr->psr2_tp2_tp3_wakeup_time;
>
> wakeup_time = (wakeup_time >> (2 * panel_type)) & 0x3;
> switch (wakeup_time) {
> diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> index 93f5c9d204d6..09cd37fb0b1c 100644
> --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> @@ -481,13 +481,13 @@ struct psr_table {
> /* TP wake up time in multiple of 100 */
> u16 tp1_wakeup_time;
> u16 tp2_tp3_wakeup_time;
> -
> - /* PSR2 TP2/TP3 wakeup time for 16 panels */
> - u32 psr2_tp2_tp3_wakeup_time;
> } __packed;
>
> struct bdb_psr {
> struct psr_table psr_table[16];
> +
> + /* PSR2 TP2/TP3 wakeup time for 16 panels */
> + u32 psr2_tp2_tp3_wakeup_time;
> } __packed;
>
> /*
> --
> 2.17.1
>
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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm: header maintenance
== Series Details == Series: drm: header maintenance URL : https://patchwork.freedesktop.org/series/63900/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6504_full -> Patchwork_13691_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_13691_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_13691_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_13691_full: ### IGT changes ### Possible regressions * igt@debugfs_test@read_all_entries_display_on: - shard-iclb: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/shard-iclb8/igt@debugfs_test@read_all_entries_display_on.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13691/shard-iclb4/igt@debugfs_test@read_all_entries_display_on.html * igt@kms_vblank@invalid: - shard-kbl: [PASS][3] -> [FAIL][4] +15 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/shard-kbl6/igt@kms_vbl...@invalid.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13691/shard-kbl7/igt@kms_vbl...@invalid.html * igt@kms_vblank@pipe-a-query-idle: - shard-glk: [PASS][5] -> [FAIL][6] +28 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/shard-glk1/igt@kms_vbl...@pipe-a-query-idle.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13691/shard-glk5/igt@kms_vbl...@pipe-a-query-idle.html * igt@kms_vblank@pipe-a-query-idle-hang: - shard-snb: [PASS][7] -> [FAIL][8] +14 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/shard-snb6/igt@kms_vbl...@pipe-a-query-idle-hang.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13691/shard-snb5/igt@kms_vbl...@pipe-a-query-idle-hang.html * igt@kms_vblank@pipe-b-query-forked: - shard-skl: [PASS][9] -> [FAIL][10] +20 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/shard-skl5/igt@kms_vbl...@pipe-b-query-forked.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13691/shard-skl7/igt@kms_vbl...@pipe-b-query-forked.html * igt@kms_vblank@pipe-b-query-idle: - shard-skl: NOTRUN -> [FAIL][11] +2 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13691/shard-skl5/igt@kms_vbl...@pipe-b-query-idle.html * igt@kms_vblank@pipe-b-query-idle-hang: - shard-iclb: [PASS][12] -> [FAIL][13] +21 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/shard-iclb8/igt@kms_vbl...@pipe-b-query-idle-hang.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13691/shard-iclb4/igt@kms_vbl...@pipe-b-query-idle-hang.html * igt@kms_vblank@pipe-b-ts-continuation-dpms-rpm: - shard-apl: [PASS][14] -> [FAIL][15] +22 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/shard-apl2/igt@kms_vbl...@pipe-b-ts-continuation-dpms-rpm.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13691/shard-apl1/igt@kms_vbl...@pipe-b-ts-continuation-dpms-rpm.html * igt@kms_vblank@pipe-c-query-forked-hang: - shard-iclb: NOTRUN -> [FAIL][16] [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13691/shard-iclb6/igt@kms_vbl...@pipe-c-query-forked-hang.html * igt@kms_vblank@pipe-c-ts-continuation-modeset-rpm: - shard-hsw: [PASS][17] -> [FAIL][18] +29 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/shard-hsw4/igt@kms_vbl...@pipe-c-ts-continuation-modeset-rpm.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13691/shard-hsw8/igt@kms_vbl...@pipe-c-ts-continuation-modeset-rpm.html Warnings * igt@kms_flip@2x-flip-vs-expired-vblank: - shard-glk: [FAIL][19] ([fdo#105363]) -> [FAIL][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/shard-glk7/igt@kms_f...@2x-flip-vs-expired-vblank.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13691/shard-glk8/igt@kms_f...@2x-flip-vs-expired-vblank.html Known issues Here are the changes found in Patchwork_13691_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_pwrite@small-gtt-backwards: - shard-apl: [PASS][21] -> [INCOMPLETE][22] ([fdo#103927]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/shard-apl3/igt@gem_pwr...@small-gtt-backwards.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13691/shard-apl2/igt@gem_pwr...@small-gtt-backwards.html * igt@gem_softpin@noreloc-s3: - shard-apl:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/dp/dsc: Add Support for all BPCs supported by TGL (rev3)
== Series Details == Series: drm/dp/dsc: Add Support for all BPCs supported by TGL (rev3) URL : https://patchwork.freedesktop.org/series/63526/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/dp/dsc: Add Support for all BPCs supported by TGL -O:drivers/gpu/drm/i915/display/intel_dp.c:1917:23: warning: expression using sizeof(void) +drivers/gpu/drm/i915/display/intel_dp.c:1917:31: warning: expression using sizeof(void) +drivers/gpu/drm/i915/display/intel_dp.c:1919:31: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/dp/dsc: Add Support for all BPCs supported by TGL
DSC engine on ICL supports only 8 and 10 BPC as the input
BPC. But DSC engine in TGL supports 8, 10 and 12 BPC.
Add 12 BPC support for DSC while calculating compression
configuration.
v2: Remove the separate define TGL_DP_DSC_MAX_SUPPORTED_BPC
and use the value directly.(More such defines can be removed
as part of future patches). (Ville)
v3: Use values directly instead of accessing the defines
everytime for min and max DSC BPC.
Cc: Ville Syrjälä
Cc: Manasi Navare
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_dp.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 0eb5d66f87a7..947c7e911304 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -69,8 +69,6 @@
/* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */
#define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER 61440
-#define DP_DSC_MIN_SUPPORTED_BPC 8
-#define DP_DSC_MAX_SUPPORTED_BPC 10
/* DP DSC throughput values used for slice count calculations KPixels/s */
#define DP_DSC_PEAK_PIXEL_RATE 272
@@ -1914,11 +1912,17 @@ static int intel_dp_dsc_compute_config(struct intel_dp
*intel_dp,
if (!intel_dp_supports_dsc(intel_dp, pipe_config))
return -EINVAL;
- dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC,
- conn_state->max_requested_bpc);
+ /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
+ if (INTEL_GEN(dev_priv) >= 12)
+ dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
+ else
+ dsc_max_bpc = min_t(u8, 10,
+ conn_state->max_requested_bpc);
pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
- if (pipe_bpp < DP_DSC_MIN_SUPPORTED_BPC * 3) {
+
+ /* Min Input BPC for ICL+ is 8 */
+ if (pipe_bpp < 8 * 3) {
DRM_DEBUG_KMS("No DSC support for less than 8bpc\n");
return -EINVAL;
}
--
2.21.0
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Re: [Intel-gfx] [PATCH v1 11/11] drm: drop uapi dependency from drm_file.h
On Thu, Jul 18, 2019 at 06:15:07PM +0200, Sam Ravnborg wrote:
> drm_file used drm_magic_t from uapi/drm/drm.h.
> This is a simple unsigned int.
> Just opencode it as such to break the dependency from this header file
> to uapi.
>
> Signed-off-by: Sam Ravnborg
Passes my build tests, thanks for the clean-ups!
Reviewed-by: Sean Paul
> Suggested-by: Daniel Vetter
> Cc: Sean Paul
> Cc: Liviu Dudau
> Cc: Chris Wilson
> Cc: Maarten Lankhorst
> Cc: Maxime Ripard
> Cc: David Airlie
> Cc: Daniel Vetter
> Cc: Jani Nikula
> Cc: Eric Anholt
> ---
> include/drm/drm_file.h | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/include/drm/drm_file.h b/include/drm/drm_file.h
> index 67af60bb527a..046cd1bf91eb 100644
> --- a/include/drm/drm_file.h
> +++ b/include/drm/drm_file.h
> @@ -34,8 +34,6 @@
> #include
> #include
>
> -#include
> -
> #include
>
> struct dma_fence;
> @@ -227,7 +225,7 @@ struct drm_file {
> struct pid *pid;
>
> /** @magic: Authentication magic, see @authenticated. */
> - drm_magic_t magic;
> + unsigned int magic;
>
> /**
>* @lhead:
> --
> 2.20.1
>
--
Sean Paul, Software Engineer, Google / Chromium OS
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Re: [Intel-gfx] [PATCH v1 04/11] drm/ati_pcigart: drop dependency on drm_os_linux.h
On Thu, Jul 18, 2019 at 08:11:35PM +0200, Sam Ravnborg wrote: > Hi Sean. > > > > Any plans for the other users of DRM_WRITE()? It seems like it'd be > > trivial > > to fix it up for via and mga. I don't really have any background on > > drm_os_linux.h, but it doesn't seem like it'd be that much more effort to > > just > > remove the whole thing. > > During the drmP.h removal I also took care of drm_os_linux.h, > so when the patches land then there will be no users left. > I look forward to delete that file. > > For via I only just posted the patches today. > For mga they already landed in drm-misc-next. > Awesome! I think I was looking at drm-next instead of -misc-next, so happy to hear the future is bright :) Reviewed-by: Sean Paul > I expect that we after next merge window can delete > both drm_os_linux.h and drmP.h. > > Sam -- Sean Paul, Software Engineer, Google / Chromium OS ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/4] drm/i915: Use maximum write flush for pwrite_gtt
On Thu, Jul 18, 2019 at 03:54:05PM +0100, Chris Wilson wrote:
> As recently disovered by forcing big-core (!llc) machines to use the GTT
> paths, we need our full GTT write flush before manipulating the GTT PTE
> or else the writes may be directed to the wrong page.
>
> Signed-off-by: Chris Wilson
> Cc: Joonas Lahtinen
> Cc: Matthew Auld
> Cc: Ville Syrjälä
> Cc: sta...@vger.kernel.org
> ---
> drivers/gpu/drm/i915/i915_gem.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index fed0bc421a55..c6ba350e6e4f 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -610,7 +610,8 @@ i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj,
> unsigned int page_length = PAGE_SIZE - page_offset;
> page_length = remain < page_length ? remain : page_length;
> if (node.allocated) {
> - wmb(); /* flush the write before we modify the GGTT */
> + /* flush the write before we modify the GGTT */
> + intel_gt_flush_ggtt_writes(ggtt->vm.gt);
Matches the story told by intel_gt_flush_ggtt_writes().
Reviewed-by: Ville Syrjälä
> ggtt->vm.insert_page(>vm,
>
> i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT),
>node.start, I915_CACHE_NONE, 0);
> @@ -639,8 +640,8 @@ i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj,
> i915_gem_object_unlock_fence(obj, fence);
> out_unpin:
> mutex_lock(>drm.struct_mutex);
> + intel_gt_flush_ggtt_writes(ggtt->vm.gt);
> if (node.allocated) {
> - wmb();
> ggtt->vm.clear_range(>vm, node.start, node.size);
> remove_mappable_node();
> } else {
> --
> 2.22.0
--
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH 1/4] drm/i915: Drop wmb() inside pread_gtt
On Thu, Jul 18, 2019 at 03:54:04PM +0100, Chris Wilson wrote:
> Inside pread, we only ever read from the GTT so the serialising wmb()
> instructions around the GGTT PTE updates are pointless.
Hard to argue with that.
Reviewed-by: Ville Syrjälä
>
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/i915_gem.c | 3 ---
> 1 file changed, 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index a207b90924e4..fed0bc421a55 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -395,11 +395,9 @@ i915_gem_gtt_pread(struct drm_i915_gem_object *obj,
> unsigned page_length = PAGE_SIZE - page_offset;
> page_length = remain < page_length ? remain : page_length;
> if (node.allocated) {
> - wmb();
> ggtt->vm.insert_page(>vm,
>
> i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT),
>node.start, I915_CACHE_NONE, 0);
> - wmb();
> } else {
> page_base += offset & PAGE_MASK;
> }
> @@ -419,7 +417,6 @@ i915_gem_gtt_pread(struct drm_i915_gem_object *obj,
> out_unpin:
> mutex_lock(>drm.struct_mutex);
> if (node.allocated) {
> - wmb();
> ggtt->vm.clear_range(>vm, node.start, node.size);
> remove_mappable_node();
> } else {
> --
> 2.22.0
>
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--
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Re: [Intel-gfx] [PATCH] drm/i915: Make sure cdclk is high enough for DP audio on VLV/CHV
Quoting Ville Syrjälä (2019-07-18 19:04:56) > On Thu, Jul 18, 2019 at 06:11:08PM +0100, Chris Wilson wrote: > > Quoting Ville Syrjala (2019-07-17 12:45:36) > > > From: Ville Syrjälä > > > > > > On VLV/CHV there is some kind of linkage between the cdclk frequency > > > and the DP link frequency. The spec says: > > > "For DP audio configuration, cdclk frequency shall be set to > > > meet the following requirements: > > > DP Link Frequency(MHz) | Cdclk frequency(MHz) > > > 270| 320 or higher > > > 162| 200 or higher" > > > > > > I suspect that would more accurately be expressed as > > > "cdclk >= DP link clock", and in any case we can express it like > > > that in the code because of the limited set of cdclk and link > > > frequencies we support. > > > > > > Without this we can end up in a situation where the cdclk > > > is too low and enabling DP audio will kill the pipe. Happens > > > eg. with 2560x1440 modes where the 266MHz cdclk is sufficient > > > to pump the pixels (241.5 MHz dotclock) but is too low for > > > the DP audio due to the link frequency being 270 MHz. > > > > > > Cc: sta...@vger.kernel.org > > > Tested-by: Stefan Gottwald > > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=49 > > > Signed-off-by: Ville Syrjälä > > > --- > > > drivers/gpu/drm/i915/display/intel_cdclk.c | 11 +++ > > > 1 file changed, 11 insertions(+) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c > > > b/drivers/gpu/drm/i915/display/intel_cdclk.c > > > index d0581a1ac243..93b0d190c184 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > > > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > > > @@ -2262,6 +2262,17 @@ int intel_crtc_compute_min_cdclk(const struct > > > intel_crtc_state *crtc_state) > > > if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9) > > > min_cdclk = max(2 * 96000, min_cdclk); > > > > > > + /* > > > +* "For DP audio configuration, cdclk frequency shall be set to > > > +* meet the following requirements: > > > +* DP Link Frequency(MHz) | Cdclk frequency(MHz) > > > +* 270| 320 or higher > > > +* 162| 200 or higher" > > > +*/ > > > + if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && > > > + intel_crtc_has_dp_encoder(crtc_state) && > > > crtc_state->has_audio) > > > + min_cdclk = max(crtc_state->port_clock, min_cdclk); > > > > I tracked port_clock down to being the dp link clock (162 or 270) so > > that part of the story checks out. > > > > Judging by the rest of the function, I buy that the cdclk and link clock > > may be inscrutably tied together, and accept the test result that the > > cdclk must be at least the link clock with audio enabled. > > > > It may be that a corner case does require a higher frequency (rather > > than just bumping from 266 to 270), but for here and now > > Yeah there could be some extra headroom required. But our cdclk > can only be 200, 266, 320 or 400 MHz (and 200 won't actually get used > due to inexplicable display failure when try to use it). So in practice > we going to actually get bumped 162->266 and 270->320 here. I should > have expressed that better in the commit message. Also, I didn't find an easy way to confirm the limited set of cdlck. Hmm, actually I was looking at min_cdclk and didn't thin to compare that against any table. Ah, adding a see vlv_calc_cdclk() might have helped me put together the other side. Certainly adding more of a hint that min_cdclk isn't the final clock would help :) -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v1 04/11] drm/ati_pcigart: drop dependency on drm_os_linux.h
Hi Sean. > > Any plans for the other users of DRM_WRITE()? It seems like it'd be trivial > to fix it up for via and mga. I don't really have any background on > drm_os_linux.h, but it doesn't seem like it'd be that much more effort to just > remove the whole thing. During the drmP.h removal I also took care of drm_os_linux.h, so when the patches land then there will be no users left. I look forward to delete that file. For via I only just posted the patches today. For mga they already landed in drm-misc-next. I expect that we after next merge window can delete both drm_os_linux.h and drmP.h. Sam ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Make sure cdclk is high enough for DP audio on VLV/CHV
On Thu, Jul 18, 2019 at 06:11:08PM +0100, Chris Wilson wrote: > Quoting Ville Syrjala (2019-07-17 12:45:36) > > From: Ville Syrjälä > > > > On VLV/CHV there is some kind of linkage between the cdclk frequency > > and the DP link frequency. The spec says: > > "For DP audio configuration, cdclk frequency shall be set to > > meet the following requirements: > > DP Link Frequency(MHz) | Cdclk frequency(MHz) > > 270| 320 or higher > > 162| 200 or higher" > > > > I suspect that would more accurately be expressed as > > "cdclk >= DP link clock", and in any case we can express it like > > that in the code because of the limited set of cdclk and link > > frequencies we support. > > > > Without this we can end up in a situation where the cdclk > > is too low and enabling DP audio will kill the pipe. Happens > > eg. with 2560x1440 modes where the 266MHz cdclk is sufficient > > to pump the pixels (241.5 MHz dotclock) but is too low for > > the DP audio due to the link frequency being 270 MHz. > > > > Cc: sta...@vger.kernel.org > > Tested-by: Stefan Gottwald > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=49 > > Signed-off-by: Ville Syrjälä > > --- > > drivers/gpu/drm/i915/display/intel_cdclk.c | 11 +++ > > 1 file changed, 11 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c > > b/drivers/gpu/drm/i915/display/intel_cdclk.c > > index d0581a1ac243..93b0d190c184 100644 > > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > > @@ -2262,6 +2262,17 @@ int intel_crtc_compute_min_cdclk(const struct > > intel_crtc_state *crtc_state) > > if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9) > > min_cdclk = max(2 * 96000, min_cdclk); > > > > + /* > > +* "For DP audio configuration, cdclk frequency shall be set to > > +* meet the following requirements: > > +* DP Link Frequency(MHz) | Cdclk frequency(MHz) > > +* 270| 320 or higher > > +* 162| 200 or higher" > > +*/ > > + if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && > > + intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio) > > + min_cdclk = max(crtc_state->port_clock, min_cdclk); > > I tracked port_clock down to being the dp link clock (162 or 270) so > that part of the story checks out. > > Judging by the rest of the function, I buy that the cdclk and link clock > may be inscrutably tied together, and accept the test result that the > cdclk must be at least the link clock with audio enabled. > > It may be that a corner case does require a higher frequency (rather > than just bumping from 266 to 270), but for here and now Yeah there could be some extra headroom required. But our cdclk can only be 200, 266, 320 or 400 MHz (and 200 won't actually get used due to inexplicable display failure when try to use it). So in practice we going to actually get bumped 162->266 and 270->320 here. I should have expressed that better in the commit message. > Acked-by: Chris Wilson Thanks. I amended the explanation a bit and pushed to dinq. -- Ville Syrjälä Intel ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v1 10/11] drm/mediatek: direct include of drm.h in mtk_drm_gem.c
On Thu, Jul 18, 2019 at 06:15:06PM +0200, Sam Ravnborg wrote: > Do not rely on including drm.h from drm_file.h, > as the include in drm_file.h will be dropped. > > Signed-off-by: Sam Ravnborg Reviewed-by: Sean Paul > Cc: CK Hu > Cc: Philipp Zabel > Cc: Matthias Brugger > Cc: linux-arm-ker...@lists.infradead.org > Cc: linux-media...@lists.infradead.org > --- > drivers/gpu/drm/mediatek/mtk_drm_gem.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_gem.c > b/drivers/gpu/drm/mediatek/mtk_drm_gem.c > index 9434f88c6341..ca672f1d140d 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_gem.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_gem.c > @@ -5,6 +5,7 @@ > > #include > > +#include > #include > #include > #include > -- > 2.20.1 > -- Sean Paul, Software Engineer, Google / Chromium OS ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v1 09/11] drm: direct include of drm.h in drm_syncobj.c
On Thu, Jul 18, 2019 at 06:15:05PM +0200, Sam Ravnborg wrote: > Do not rely on including drm.h from drm_file.h, > as the include in drm_file.h will be dropped. > > Signed-off-by: Sam Ravnborg Reviewed-by: Sean Paul > Cc: Maarten Lankhorst > Cc: Maxime Ripard > Cc: Sean Paul > Cc: David Airlie > Cc: Daniel Vetter > Cc: Lionel Landwerlin > Cc: Chunming Zhou > Cc: Christian König > --- > drivers/gpu/drm/drm_syncobj.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/gpu/drm/drm_syncobj.c b/drivers/gpu/drm/drm_syncobj.c > index a199c8d56b95..75cb4bb7619e 100644 > --- a/drivers/gpu/drm/drm_syncobj.c > +++ b/drivers/gpu/drm/drm_syncobj.c > @@ -53,6 +53,7 @@ > #include > #include > > +#include > #include > #include > #include > -- > 2.20.1 > -- Sean Paul, Software Engineer, Google / Chromium OS ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v1 08/11] drm: direct include of drm.h in drm_prime.c
On Thu, Jul 18, 2019 at 06:15:04PM +0200, Sam Ravnborg wrote: > Do not rely on including drm.h from drm_file.h, > as the include in drm_file.h will be dropped. > > Signed-off-by: Sam Ravnborg Reviewed-by: Sean Paul > Cc: Maarten Lankhorst > Cc: Maxime Ripard > Cc: Sean Paul > Cc: David Airlie > Cc: Daniel Vetter > Cc: Christian König > Cc: Noralf Trønnes > Cc: Chris Wilson > Cc: Eric Anholt > --- > drivers/gpu/drm/drm_prime.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/gpu/drm/drm_prime.c b/drivers/gpu/drm/drm_prime.c > index 189d980402ad..eca484106cc2 100644 > --- a/drivers/gpu/drm/drm_prime.c > +++ b/drivers/gpu/drm/drm_prime.c > @@ -30,6 +30,7 @@ > #include > #include > > +#include > #include > #include > #include > -- > 2.20.1 > -- Sean Paul, Software Engineer, Google / Chromium OS ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v1 07/11] drm: direct include of drm.h in drm_gem_shmem_helper.c
On Thu, Jul 18, 2019 at 06:15:03PM +0200, Sam Ravnborg wrote: > Do not rely on including drm.h from drm_file.h, > as the include in drm_file.h will be dropped. > > Signed-off-by: Sam Ravnborg Reviewed-by: Sean Paul > Cc: Maarten Lankhorst > Cc: Maxime Ripard > Cc: Sean Paul > Cc: David Airlie > Cc: Daniel Vetter > Cc: Eric Anholt > Cc: Thomas Zimmermann > Cc: Rob Herring > --- > drivers/gpu/drm/drm_gem_shmem_helper.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/gpu/drm/drm_gem_shmem_helper.c > b/drivers/gpu/drm/drm_gem_shmem_helper.c > index 472ea5d81f82..2f64667ac805 100644 > --- a/drivers/gpu/drm/drm_gem_shmem_helper.c > +++ b/drivers/gpu/drm/drm_gem_shmem_helper.c > @@ -10,6 +10,7 @@ > #include > #include > > +#include > #include > #include > #include > -- > 2.20.1 > -- Sean Paul, Software Engineer, Google / Chromium OS ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v1 05/11] drm/vblank: drop use of DRM_WAIT_ON()
On Thu, Jul 18, 2019 at 06:15:01PM +0200, Sam Ravnborg wrote:
> DRM_WAIT_ON() is from the deprecated drm_os_linux header and
> the modern replacement is the wait_event_*.
>
> The return values differ, so a conversion is needed to
> keep the original interface towards userspace.
> Introduced a switch/case to make code obvious and to allow
> different debug prints depending on the result.
>
> Signed-off-by: Sam Ravnborg
Reviewed-by: Sean Paul
> Cc: Maarten Lankhorst
> Cc: Maxime Ripard
> Cc: Sean Paul
> Cc: David Airlie
> Cc: Daniel Vetter
> ---
> drivers/gpu/drm/drm_vblank.c | 29 -
> 1 file changed, 20 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_vblank.c b/drivers/gpu/drm/drm_vblank.c
> index 603ab105125d..8e9ac187500e 100644
> --- a/drivers/gpu/drm/drm_vblank.c
> +++ b/drivers/gpu/drm/drm_vblank.c
> @@ -31,7 +31,6 @@
> #include
> #include
> #include
> -#include
> #include
>
> #include "drm_internal.h"
> @@ -1672,19 +1671,31 @@ int drm_wait_vblank_ioctl(struct drm_device *dev,
> void *data,
> if (req_seq != seq) {
> DRM_DEBUG("waiting on vblank count %llu, crtc %u\n",
> req_seq, pipe);
> - DRM_WAIT_ON(ret, vblank->queue, 3 * HZ,
> - vblank_passed(drm_vblank_count(dev, pipe),
> - req_seq) ||
> - !READ_ONCE(vblank->enabled));
> + ret = wait_event_interruptible_timeout(vblank->queue,
> + vblank_passed(drm_vblank_count(dev, pipe), req_seq) ||
> + !READ_ONCE(vblank->enabled),
> + msecs_to_jiffies(3000));
> }
>
> - if (ret != -EINTR) {
> + switch (ret) {
> + case 0:
> + /* timeout */
> + ret = -EBUSY;
> drm_wait_vblank_reply(dev, pipe, >reply);
> -
> - DRM_DEBUG("crtc %d returning %u to client\n",
> + DRM_DEBUG("timeout waiting for vblank. crtc %d returning %u to
> client\n",
> pipe, vblwait->reply.sequence);
> - } else {
> + break;
> + case -ERESTARTSYS:
> + /* interrupted by signal */
> + ret = -EINTR;
> DRM_DEBUG("crtc %d vblank wait interrupted by signal\n", pipe);
> + break;
> + default:
> + ret = 0;
> + drm_wait_vblank_reply(dev, pipe, >reply);
> + DRM_DEBUG("crtc %d returning %u to client\n",
> + pipe, vblwait->reply.sequence);
> + break;
> }
>
> done:
> --
> 2.20.1
>
--
Sean Paul, Software Engineer, Google / Chromium OS
___
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Re: [Intel-gfx] [PATCH v1 06/11] drm: direct include of drm.h in drm_gem.c
On Thu, Jul 18, 2019 at 06:15:02PM +0200, Sam Ravnborg wrote: > Do not rely on including drm.h from drm_file.h, > as the include in drm_file.h will be dropped. > > Signed-off-by: Sam Ravnborg Reviewed-by: Sean Paul > Cc: Maarten Lankhorst > Cc: Maxime Ripard > Cc: Sean Paul > Cc: David Airlie > Cc: Daniel Vetter > Cc: Eric Anholt > Cc: Thomas Zimmermann > Cc: Rob Herring > --- > drivers/gpu/drm/drm_gem.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c > index e6c12c6ec728..243f43d70f42 100644 > --- a/drivers/gpu/drm/drm_gem.c > +++ b/drivers/gpu/drm/drm_gem.c > @@ -39,6 +39,7 @@ > #include > #include > > +#include > #include > #include > #include > -- > 2.20.1 > -- Sean Paul, Software Engineer, Google / Chromium OS ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v1 04/11] drm/ati_pcigart: drop dependency on drm_os_linux.h
On Thu, Jul 18, 2019 at 06:15:00PM +0200, Sam Ravnborg wrote:
> The drm_os_linux.h header is deprecated.
> Just opencode the sole DRM_WRITE32().
Any plans for the other users of DRM_WRITE()? It seems like it'd be trivial
to fix it up for via and mga. I don't really have any background on
drm_os_linux.h, but it doesn't seem like it'd be that much more effort to just
remove the whole thing.
Sean
>
> Signed-off-by: Sam Ravnborg
> Cc: Maarten Lankhorst
> Cc: Maxime Ripard
> Cc: Sean Paul
> Cc: David Airlie
> Cc: Daniel Vetter
> ---
> drivers/gpu/drm/ati_pcigart.c | 10 ++
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/ati_pcigart.c b/drivers/gpu/drm/ati_pcigart.c
> index 2a413e291a60..580aa2676358 100644
> --- a/drivers/gpu/drm/ati_pcigart.c
> +++ b/drivers/gpu/drm/ati_pcigart.c
> @@ -35,7 +35,6 @@
>
> #include
> #include
> -#include
> #include
> #include
>
> @@ -169,6 +168,7 @@ int drm_ati_pcigart_init(struct drm_device *dev, struct
> drm_ati_pcigart_info *ga
> page_base = (u32) entry->busaddr[i];
>
> for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) {
> + u32 offset;
> u32 val;
>
> switch(gart_info->gart_reg_if) {
> @@ -184,10 +184,12 @@ int drm_ati_pcigart_init(struct drm_device *dev, struct
> drm_ati_pcigart_info *ga
> break;
> }
> if (gart_info->gart_table_location ==
> - DRM_ATI_GART_MAIN)
> + DRM_ATI_GART_MAIN) {
> pci_gart[gart_idx] = cpu_to_le32(val);
> - else
> - DRM_WRITE32(map, gart_idx * sizeof(u32), val);
> + } else {
> + offset = gart_idx * sizeof(u32);
> + writel(val, (void __iomem *)map->handle +
> offset);
> + }
> gart_idx++;
> page_base += ATI_PCIGART_PAGE_SIZE;
> }
> --
> 2.20.1
>
--
Sean Paul, Software Engineer, Google / Chromium OS
___
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Re: [Intel-gfx] [PATCH 18/22] drm/i915/tgl: Define MOCS entries for Tigerlake
On Thu, Jul 18, 2019 at 10:09:27AM -0700, Daniele Ceraolo Spurio wrote:
>
>
> On 7/18/19 6:08 AM, Ville Syrjälä wrote:
> > On Fri, Jul 12, 2019 at 06:09:36PM -0700, Lucas De Marchi wrote:
> >> From: Tomasz Lis
> >>
> >> The MOCS table is published as part of bspec, and versioned. Entries
> >> are supposed to never be modified, but new ones can be added. Adding
> >> entries increases table version. The patch includes version 1 entries.
> >>
> >> Two of the 3 legacy entries used for gen9 are no longer expected to work.
> >> Although we are changing the gen11 table, those changes are supposed to
> >> be backward compatible since we are only touching previously undefined
> >> entries.
> >>
> >> Cc: Joonas Lahtinen
> >> Cc: Mika Kuoppala
> >> Cc: Daniele Ceraolo Spurio
> >> Signed-off-by: Tomasz Lis
> >> Signed-off-by: Lucas De Marchi
> >> ---
> >> drivers/gpu/drm/i915/gt/intel_mocs.c | 25 ++---
> >> 1 file changed, 22 insertions(+), 3 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c
> >> b/drivers/gpu/drm/i915/gt/intel_mocs.c
> >> index 290a5e9b90b9..259e7bec0a63 100644
> >> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> >> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> >> @@ -62,6 +62,10 @@ struct drm_i915_mocs_table {
> >> #define GEN11_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but
> >> configured. */
> >>
> >> /* (e)LLC caching options */
> >> +/*
> >> + * Note: LE_0_PAGETABLE works only up to Gen11; for newer gens it means
> >> + * the same as LE_UC
> >> + */
> >> #define LE_0_PAGETABLE _LE_CACHEABILITY(0)
> >> #define LE_1_UC _LE_CACHEABILITY(1)
> >> #define LE_2_WT _LE_CACHEABILITY(2)
> >> @@ -100,8 +104,9 @@ struct drm_i915_mocs_table {
> >>* of bspec.
> >>*
> >>* Entries not part of the following tables are undefined as far as
> >> - * userspace is concerned and shouldn't be relied upon. For the time
> >> - * being they will be initialized to PTE.
> >> + * userspace is concerned and shouldn't be relied upon. For Gen < 12
> >> + * they will be initialized to PTE. Gen >= 12 onwards don't have a
> >> setting for
> >> + * PTE. We use the same value, but that actually means Uncached.
> >>*
> >>* The last two entries are reserved by the hardware. For ICL+ they
> >>* should be initialized according to bspec and never used, for older
> >> @@ -137,11 +142,13 @@ static const struct drm_i915_mocs_entry
> >> broxton_mocs_table[] = {
> >> };
> >>
> >> #define GEN11_MOCS_ENTRIES \
> >> - /* Base - Uncached (Deprecated) */ \
> >> + /* Gen11: Base - Uncached (Deprecated) */ \
> >> + /* Gen12+: Base - Error (Reserved for Non-Use) */ \
> >>MOCS_ENTRY(I915_MOCS_UNCACHED, \
> >> LE_1_UC | LE_TC_1_LLC, \
> >> L3_1_UC), \
> >>/* Base - L3 + LeCC:PAT (Deprecated) */ \
> >> + /* Gen12+: Base - Reserved */ \
> >>MOCS_ENTRY(I915_MOCS_PTE, \
> >> LE_0_PAGETABLE | LE_TC_1_LLC, \
> >> L3_3_WB), \
> >> @@ -233,6 +240,18 @@ static const struct drm_i915_mocs_entry
> >> broxton_mocs_table[] = {
> >>MOCS_ENTRY(23, \
> >> LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_RSC(1) | LE_SCC(7), \
> >> L3_3_WB), \
> >> + /* Gen12+: HW Reserved - HDC:L1 + L3 + LLC */ \
> >
> > Why is this marked as reserved? From the looks of things 48-61 should
> > just be normal entries that userspace can select to get HDC L1$. And
> > looks like icl already has that stuff. So someone should probably figure
> > out if Mesa/etc. can make use of the HDC L1$, and if so we should add
> > the relevant MOCS entries for icl as well.
>
> Here the reserved terminology is indeed misleading. The 48-59 range is a
> "special" range where L1 usage is implicitly enabled by the HW, as there
> is no explicit L1 toggle in the MOCS registers. The reserved here means
> that the range shouldn't be used for "normal" MOCS settings, but SW can
> freely use these entries as needed. Similarly, MOCS 60 and 61 are
> reserved for other special purposes, but are still usable by SW. The
> only entries SW shouldn't touch are 62 and 63.
>
> Regarding ICL, Gen11 HW doesn't have the capability so no new entries
> are required there.
Hmm. The table doesn't list those entries, but HDC_CHICKEN2 seems to be
saying the features is in there. HDC_MODE also talks about HDC L1$.
Confusing.
>
> >
> >> + MOCS_ENTRY(48, \
> >> + LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
> >> + L3_3_WB), \
> >> + /* Gen12+: HW Reserved - HW Special Case (CCS) */ \
>
> The specs have MOCS 49-51 defined as well.
>
> Daniele
>
> >> + MOCS_ENTRY(60, \
> >> + LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
> >> + L3_1_UC), \
> >> + /* Gen12+: HW Reserved - HW Special Case (Displayable) */ \
> >> + MOCS_ENTRY(61, \
> >> + LE_1_UC | LE_TC_1_LLC | LE_SCF(1), \
> >> + L3_3_WB), \
> >>/* HW Reserved - SW
Re: [Intel-gfx] [PATCH 19/22] drm/i915/tgl: Tigerlake only has global MOCS registers
On 7/12/19 6:09 PM, Lucas De Marchi wrote:
From: Michel Thierry
Until Icelake, each engine had its own set of 64 MOCS registers. In
order to simplify, Tigerlake moves to only 64 Global MOCS registers,
which are no longer part of the engine context. Since these registers
are now global, they also only need to be initialized once.
These new global MOCS registers are located in the same offset of the
render MOCS register from previous platforms.
No, they're not :). They're located in a new range, which overlaps with
the location where the fault register was previously located and that's
why the offset of that one has been changed as well. The code does the
right thing, so only this sentence needs fixing.
the FAULT_TLB_DATA* registers have been moved as well as part of the
re-org, so maybe we can have a patch that just moves all the offsets and
then add the global mocs on top?
From Gen12 onwards, MOCS must specify the target cache (3:2) and LRU
management (5:4) fields and cannot be programmed to 'use the value from
Private PAT', because these fields are no longer part of the PPAT. Also
cacheability control (1:0) field has changed, 00 no longer means 'use
controls from page table', but uncacheable (UC).
Should we put this as a comment in the code somewhere? Although I'm not
sure we have any use for this info since we copy the table straight from
the specs and we should probably trust it is correct.
Daniele
Cc: Daniele Ceraolo Spurio
Cc: Tomasz Lis
Signed-off-by: Michel Thierry
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/intel_gt.c | 12 --
drivers/gpu/drm/i915/gt/intel_mocs.c | 47
drivers/gpu/drm/i915/gt/intel_mocs.h | 1 +
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_gem.c | 1 +
drivers/gpu/drm/i915/i915_gpu_error.c| 11 --
drivers/gpu/drm/i915/i915_pci.c | 3 +-
drivers/gpu/drm/i915/i915_reg.h | 3 ++
drivers/gpu/drm/i915/intel_device_info.h | 1 +
9 files changed, 74 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index f7e69db4019d..958edfda2ba2 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -80,8 +80,11 @@ intel_gt_clear_error_registers(struct intel_gt *gt,
}
if (INTEL_GEN(i915) >= 8) {
- rmw_clear(uncore, GEN8_RING_FAULT_REG, RING_FAULT_VALID);
- intel_uncore_posting_read(uncore, GEN8_RING_FAULT_REG);
+ i915_reg_t fault_reg = (INTEL_GEN(i915) >= 12) ?
+ GEN12_RING_FAULT_REG :
+ GEN8_RING_FAULT_REG;
+ rmw_clear(uncore, fault_reg, RING_FAULT_VALID);
+ intel_uncore_posting_read(uncore, fault_reg);
} else if (INTEL_GEN(i915) >= 6) {
struct intel_engine_cs *engine;
enum intel_engine_id id;
@@ -117,7 +120,10 @@ static void gen6_check_faults(struct intel_gt *gt)
static void gen8_check_faults(struct intel_gt *gt)
{
struct intel_uncore *uncore = gt->uncore;
- u32 fault = intel_uncore_read(uncore, GEN8_RING_FAULT_REG);
+ i915_reg_t fault_reg =
+ (INTEL_GEN(gt->i915) >= 12) ?
+ GEN12_RING_FAULT_REG : GEN8_RING_FAULT_REG;
+ u32 fault = intel_uncore_read(uncore, fault_reg);
if (fault & RING_FAULT_VALID) {
u32 fault_data0, fault_data1;
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c
b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 259e7bec0a63..365d8ff11f23 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -365,6 +365,10 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine)
unsigned int index;
u32 unused_value;
+ /* Platforms with global MOCS do not need per-engine initialization. */
+ if (HAS_GLOBAL_MOCS_REGISTERS(gt->i915))
+ return;
+
/* Called under a blanket forcewake */
assert_forcewakes_active(uncore, FORCEWAKE_ALL);
@@ -389,6 +393,46 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine)
unused_value);
}
+/**
+ * intel_mocs_init_global() - program the global mocs registers
+ * gt: pointer to struct intel_gt
+ *
+ * This function initializes the MOCS global registers.
+ */
+void intel_mocs_init_global(struct intel_gt *gt)
+{
+ struct intel_uncore *uncore = gt->uncore;
+ struct drm_i915_mocs_table table;
+ unsigned int index;
+
+ if (!HAS_GLOBAL_MOCS_REGISTERS(gt->i915))
+ return;
+
+ if (!get_mocs_settings(gt, ))
+ return;
+
+ if (GEM_DEBUG_WARN_ON(table.size > table.n_entries))
+ return;
+
+ for (index = 0; index < table.size; index++)
+
Re: [Intel-gfx] [PATCH v1 03/11] drm: drop uapi dependency from drm_vblank.h
On Thu, Jul 18, 2019 at 06:14:59PM +0200, Sam Ravnborg wrote: > drm_vblank.h included uapi/drm/drm.h. > It turns out this include was not required - delete it. > > Note: uapi/drm/drm.h is included indirect via drm_file.h, > but there are no dependencies in drm_vblank.h so the removal > is legit. > > Signed-off-by: Sam Ravnborg > Reviewed-by: Daniel Vetter > Cc: Maarten Lankhorst > Cc: Maxime Ripard > Cc: Sean Paul > Cc: David Airlie > Cc: Daniel Vetter > Cc: Stefan Agner > Cc: Thierry Reding Reviewed-by: Sean Paul > --- > include/drm/drm_vblank.h | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/include/drm/drm_vblank.h b/include/drm/drm_vblank.h > index e528bb2f659d..9fe4ba8bc622 100644 > --- a/include/drm/drm_vblank.h > +++ b/include/drm/drm_vblank.h > @@ -30,7 +30,6 @@ > > #include > #include > -#include > > struct drm_device; > struct drm_crtc; > -- > 2.20.1 > -- Sean Paul, Software Engineer, Google / Chromium OS ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v1 02/11] drm: drop uapi dependency from drm_print.h
On Thu, Jul 18, 2019 at 06:14:58PM +0200, Sam Ravnborg wrote: > drm_print.h used DRM_NAME - thus adding a dependency from > include/drm/drm_print.h => uapi/drm/drm.h > > Hardcode the name "drm" to break this dependency. > The idea is that there shall be a minimal dependency > between include/drm/* and uapi/* You might also want to clean up the other uses of DRM_NAME in armada and i915 while you're at it. The easiest way to satisfy Chris' usecase and remove the dependency would be to add #define DRM_PRINT_NAME "drm" in drm_print.h and use that. Sean > > Signed-off-by: Sam Ravnborg > Suggested-by: Daniel Vetter > Reviewed-by: Daniel Vetter > Cc: Maarten Lankhorst > Cc: Maxime Ripard > Cc: Sean Paul > Cc: David Airlie > Cc: Rob Clark > Cc: Sean Paul > Cc: Chris Wilson > Cc: Daniel Vetter > --- > include/drm/drm_print.h | 4 +--- > 1 file changed, 1 insertion(+), 3 deletions(-) > > diff --git a/include/drm/drm_print.h b/include/drm/drm_print.h > index a5d6f2f3e430..760d1bd0eaf1 100644 > --- a/include/drm/drm_print.h > +++ b/include/drm/drm_print.h > @@ -32,8 +32,6 @@ > #include > #include > > -#include > - > /** > * DOC: print > * > @@ -287,7 +285,7 @@ void drm_err(const char *format, ...); > /* Macros to make printk easier */ > > #define _DRM_PRINTK(once, level, fmt, ...) \ > - printk##once(KERN_##level "[" DRM_NAME "] " fmt, ##__VA_ARGS__) > + printk##once(KERN_##level "[drm] " fmt, ##__VA_ARGS__) > > #define DRM_INFO(fmt, ...) \ > _DRM_PRINTK(, INFO, fmt, ##__VA_ARGS__) > -- > 2.20.1 > -- Sean Paul, Software Engineer, Google / Chromium OS ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v1 01/11] drm/panel: make drm_panel.h self-contained
On Thu, Jul 18, 2019 at 06:14:57PM +0200, Sam Ravnborg wrote:
> From: Jani Nikula
>
> Fix build warning if drm_panel.h is built with CONFIG_OF=n or
> CONFIG_DRM_PANEL=n and included without the prerequisite err.h:
>
> ./include/drm/drm_panel.h: In function ‘of_drm_find_panel’:
> ./include/drm/drm_panel.h:203:9: error: implicit declaration of function
> ‘ERR_PTR’ [-Werror=implicit-function-declaration]
> return ERR_PTR(-ENODEV);
> ^~~
> ./include/drm/drm_panel.h:203:9: error: returning ‘int’ from a function with
> return type ‘struct drm_panel *’ makes pointer from integer without a cast
> [-Werror=int-conversion]
> return ERR_PTR(-ENODEV);
> ^~~~
>
> Fixes: 5fa8e4a22182 ("drm/panel: Make of_drm_find_panel() return an ERR_PTR()
> instead of NULL")
> Cc: Boris Brezillon
> Signed-off-by: Jani Nikula
> Acked-by: Thierry Reding
> Reviewed-by: Sam Ravnborg
Reviewed-by: Sean Paul
> ---
> include/drm/drm_panel.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/include/drm/drm_panel.h b/include/drm/drm_panel.h
> index 8c738c0e6e9f..26377836141c 100644
> --- a/include/drm/drm_panel.h
> +++ b/include/drm/drm_panel.h
> @@ -24,6 +24,7 @@
> #ifndef __DRM_PANEL_H__
> #define __DRM_PANEL_H__
>
> +#include
> #include
> #include
>
> --
> 2.20.1
>
--
Sean Paul, Software Engineer, Google / Chromium OS
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/4] drm/i915: Drop wmb() inside pread_gtt
== Series Details == Series: series starting with [1/4] drm/i915: Drop wmb() inside pread_gtt URL : https://patchwork.freedesktop.org/series/63895/ State : success == Summary == CI Bug Log - changes from CI_DRM_6504_full -> Patchwork_13690_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13690_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@rcs0-s3: - shard-kbl: [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) +4 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/shard-kbl3/igt@gem_ctx_isolat...@rcs0-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13690/shard-kbl6/igt@gem_ctx_isolat...@rcs0-s3.html * igt@kms_cursor_edge_walk@pipe-c-128x128-top-edge: - shard-iclb: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/shard-iclb2/igt@kms_cursor_edge_w...@pipe-c-128x128-top-edge.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13690/shard-iclb7/igt@kms_cursor_edge_w...@pipe-c-128x128-top-edge.html * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic: - shard-hsw: [PASS][5] -> [FAIL][6] ([fdo#105767]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/shard-hsw4/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-atomic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13690/shard-hsw6/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-atomic.html * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: [PASS][7] -> [FAIL][8] ([fdo#105363]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/shard-skl8/igt@kms_f...@flip-vs-expired-vblank.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13690/shard-skl7/igt@kms_f...@flip-vs-expired-vblank.html * igt@kms_flip@modeset-vs-vblank-race-interruptible: - shard-glk: [PASS][9] -> [FAIL][10] ([fdo#103060]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/shard-glk1/igt@kms_f...@modeset-vs-vblank-race-interruptible.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13690/shard-glk7/igt@kms_f...@modeset-vs-vblank-race-interruptible.html * igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw: - shard-iclb: [PASS][11] -> [FAIL][12] ([fdo#103167]) +6 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/shard-iclb3/igt@kms_frontbuffer_track...@fbc-1p-pri-indfb-multidraw.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13690/shard-iclb2/igt@kms_frontbuffer_track...@fbc-1p-pri-indfb-multidraw.html * igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary: - shard-iclb: [PASS][13] -> [DMESG-WARN][14] ([fdo#107724]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/shard-iclb7/igt@kms_frontbuffer_track...@fbcpsr-indfb-scaledprimary.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13690/shard-iclb1/igt@kms_frontbuffer_track...@fbcpsr-indfb-scaledprimary.html * igt@kms_frontbuffer_tracking@fbcpsr-shrfb-scaledprimary: - shard-iclb: [PASS][15] -> [DMESG-FAIL][16] ([fdo#103167] / [fdo#107724]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/shard-iclb2/igt@kms_frontbuffer_track...@fbcpsr-shrfb-scaledprimary.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13690/shard-iclb1/igt@kms_frontbuffer_track...@fbcpsr-shrfb-scaledprimary.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen: - shard-iclb: [PASS][17] -> [INCOMPLETE][18] ([fdo#106978] / [fdo#107713]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/shard-iclb8/igt@kms_frontbuffer_track...@psr-1p-primscrn-spr-indfb-fullscreen.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13690/shard-iclb7/igt@kms_frontbuffer_track...@psr-1p-primscrn-spr-indfb-fullscreen.html * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/shard-skl10/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13690/shard-skl2/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html * igt@kms_psr@psr2_cursor_mmap_cpu: - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109441]) +5 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13690/shard-iclb1/igt@kms_psr@psr2_cursor_mmap_cpu.html * igt@kms_vblank@pipe-a-ts-continuation-suspend: - shard-apl: [PASS][23] -> [DMESG-WARN][24] ([fdo#108566]) +3 similar issues [23]:
Re: [Intel-gfx] [PATCH] drm/i915/ehl: Use an id of 4 while accessing DPLL4's CR0 and CR1
On Tue, Jul 16, 2019 at 07:13:16PM -0700, Vivek Kasireddy wrote:
> Although, DPLL4 enable and disable is associated with MGPLL1_ENABLE
> register, we can use ICL_DPLL_CFGCR0/CR1 macros to access this dpll's
> CR0 and CR1 registers by passing an id of 4 to these macros.
>
> Reported-by: Ville Syrjälä
> Cc: Ville Syrjälä
> Cc: José Roberto de Souza
> Cc: Matt Roper
> Cc: Imre Deak
> Signed-off-by: Vivek Kasireddy
> ---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 18 ++
> 1 file changed, 14 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 319a26a1ec10..f9bdf8514a53 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -3127,8 +3127,13 @@ static bool icl_pll_get_hw_state(struct
> drm_i915_private *dev_priv,
> hw_state->cfgcr0 = I915_READ(TGL_DPLL_CFGCR0(id));
> hw_state->cfgcr1 = I915_READ(TGL_DPLL_CFGCR1(id));
> } else {
> - hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));
> - hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));
> + if (IS_ELKHARTLAKE(dev_priv) && id == DPLL_ID_EHL_DPLL4) {
> + hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(4));
> + hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(4));
> + } else {
> + hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));
> + hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));
> + }
> }
>
> ret = true;
> @@ -3169,8 +3174,13 @@ static void icl_dpll_write(struct drm_i915_private
> *dev_priv,
> cfgcr0_reg = TGL_DPLL_CFGCR0(id);
> cfgcr1_reg = TGL_DPLL_CFGCR1(id);
> } else {
> - cfgcr0_reg = ICL_DPLL_CFGCR0(id);
> - cfgcr1_reg = ICL_DPLL_CFGCR1(id);
> + if (IS_ELKHARTLAKE(dev_priv) && id == DPLL_ID_EHL_DPLL4) {
> + cfgcr0_reg = ICL_DPLL_CFGCR0(4);
> + cfgcr1_reg = ICL_DPLL_CFGCR1(4);
> + } else {
> + cfgcr0_reg = ICL_DPLL_CFGCR0(id);
> + cfgcr1_reg = ICL_DPLL_CFGCR1(id);
> + }
I was a bit worried this would also affect other parts of the code, but
at least ICL_DPCLKA_CFGCR0_DDI_CLK_SEL() seems to do the right thing
with the id==2, and I couldn't immediately spot other issues.
Also surprising that ci didn't get confused by the fact that this was posted
as a reply to another series. Generally you should avoid replying with
anything except direct replacements for the original patches in the
series.
Pushed to dinq. Thanks for the patch.
> }
>
> I915_WRITE(cfgcr0_reg, hw_state->cfgcr0);
> --
> 2.21.0
--
Ville Syrjälä
Intel
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: YCbCr output fixes and prep work for YCbCr 4:4:4 output (rev2)
== Series Details == Series: drm/i915: YCbCr output fixes and prep work for YCbCr 4:4:4 output (rev2) URL : https://patchwork.freedesktop.org/series/63893/ State : success == Summary == CI Bug Log - changes from CI_DRM_6504 -> Patchwork_13692 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13692/ Known issues Here are the changes found in Patchwork_13692 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_reloc@basic-cpu-read: - fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/fi-icl-u3/igt@gem_exec_re...@basic-cpu-read.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13692/fi-icl-u3/igt@gem_exec_re...@basic-cpu-read.html * igt@gem_exec_suspend@basic-s3: - fi-blb-e6850: [PASS][3] -> [INCOMPLETE][4] ([fdo#107718]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13692/fi-blb-e6850/igt@gem_exec_susp...@basic-s3.html * igt@i915_module_load@reload-with-fault-injection: - fi-icl-dsi: [PASS][5] -> [INCOMPLETE][6] ([fdo#107713]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/fi-icl-dsi/igt@i915_module_l...@reload-with-fault-injection.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13692/fi-icl-dsi/igt@i915_module_l...@reload-with-fault-injection.html Possible fixes * igt@kms_chamelium@dp-edid-read: - fi-cml-u2: [FAIL][7] ([fdo#109483]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/fi-cml-u2/igt@kms_chamel...@dp-edid-read.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13692/fi-cml-u2/igt@kms_chamel...@dp-edid-read.html [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483 Participating hosts (54 -> 47) -- Additional (1): fi-pnv-d510 Missing(8): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-icl-y fi-byt-clapper fi-bdw-samus Build changes - * Linux: CI_DRM_6504 -> Patchwork_13692 CI_DRM_6504: a23df173f63ed05ae452ab478a01131a89938654 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5102: 6038ace76016d8892f4d13aef5301f71ca1a6e2d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13692: 59d67bbd6836f528a66b65075708f5c993b4373a @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 59d67bbd6836 drm/i915: Add PIPECONF YCbCr 4:4:4 programming for ILK-IVB bef6896c1fb2 drm/i915: Set up ILK/SNB csc unit properly for YCbCr output 309ff10d40e5 drm/i915: Document ILK+ pipe csc matrix better 144a053a6025 drm/i915: Add PIPECONF YCbCr 4:4:4 programming for HSW 2408a3989316 drm/i915: Simplify intel_get_crtc_ycbcr_config() 8d8da3e76616 drm/i915: Don't look at unrelated PIPECONF bits for interlaced readout 1ee8d9c20bb1 drm/i915: Switch to using DP_MSA_MISC_* defines ae1f5e8aa2a6 drm/i915: Never set limited_color_range=true for YCbCr output 52a959f564ed drm/i915: Extract intel_hdmi_limited_color_range() 474241913086 drm/i915: Fix AVI infoframe quantization range for YCbCr output 6004b3d70dcf drm/i915: Fix HSW+ DP MSA YCbCr colorspace indication 3b574e4da250 drm/dp: Add definitons for MSA MISC bits == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13692/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/ehl: Add support for DPLL4 (v10)
On Tue, Jul 16, 2019 at 06:54:39PM -0700, Vivek Kasireddy wrote:
> On Wed, 10 Jul 2019 21:47:52 +0300
> Ville Syrjälä wrote:
> Hi Ville,
>
> > On Wed, Jul 03, 2019 at 04:03:53PM -0700, Vivek Kasireddy wrote:
> > > This patch adds support for DPLL4 on EHL that include the
> > > following restrictions:
> > >
> > > - DPLL4 cannot be used with DDIA (combo port A internal eDP usage).
> > > DPLL4 can be used with other DDIs, including DDID
> > > (combo port A external usage).
> > >
> > > - DPLL4 cannot be enabled when DC5 or DC6 are enabled.
> > >
> > > - The DPLL4 enable, lock, power enabled, and power state are
> > > connected to the MGPLL1_ENABLE register.
> > >
> > > v2: (suggestions from Bob Paauwe)
> > > - Rework ehl_get_dpll() function to call intel_find_shared_dpll()
> > > and iterate twice: once for Combo plls and once for MG plls.
> > >
> > > - Use MG pll funcs for DPLL4 instead of creating new ones and modify
> > > mg_pll_enable to include the restrictions for EHL.
> > >
> > > v3: Fix compilation error
> > >
> > > v4: (suggestions from Lucas and Ville)
> > > - Treat DPLL4 as a combo phy PLL and not as MG PLL
> > > - Disable DC states when this DPLL is being enabled
> > > - Reuse icl_get_dpll instead of creating a separate one for EHL
> > >
> > > v5: (suggestion from Ville)
> > > - Refcount the DC OFF power domains during the enabling and
> > > disabling of this DPLL.
> > >
> > > v6: rebase
> > >
> > > v7: (suggestion from Imre)
> > > - Add a new power domain instead of iterating over the domains
> > > assoicated with DC OFF power well.
> > >
> > > v8: (Ville and Imre)
> > > - Rename POWER_DOMAIN_DPLL4 TO POWER_DOMAIN_DPLL_DC_OFF
> > > - Grab a reference in intel_modeset_setup_hw_state() if this
> > > DPLL was already enabled perhaps by BIOS.
> > > - Check for the port type instead of the encoder
> > >
> > > v9: (Ville)
> > > - Move the block of code that grabs a reference to the power domain
> > > POWER_DOMAIN_DPLL_DC_OFF to intel_modeset_readout_hw_state() to
> > > ensure that there is a reference present before this DPLL might get
> > > disabled.
> > >
> > > v10: rebase
> > >
> > > Cc: José Roberto de Souza
> > > Cc: Ville Syrjälä
> > > Cc: Matt Roper
> > > Cc: Imre Deak
> > > Signed-off-by: Vivek Kasireddy
> > > ---
> > > drivers/gpu/drm/i915/display/intel_display.c | 7 +++
> > > .../drm/i915/display/intel_display_power.c| 3 ++
> > > .../drm/i915/display/intel_display_power.h| 1 +
> > > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 47
> > > +-- drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > > | 6 +++ 5 files changed, 60 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > b/drivers/gpu/drm/i915/display/intel_display.c index
> > > 919f5ac844c8..557462208462 100644 ---
> > > a/drivers/gpu/drm/i915/display/intel_display.c +++
> > > b/drivers/gpu/drm/i915/display/intel_display.c @@ -16653,6
> > > +16653,13 @@ static void intel_modeset_readout_hw_state(struct
> > > drm_device *dev) pll->on = pll->info->funcs->get_hw_state(dev_priv,
> > > pll, >state.hw_state);
> > > +
> > > + if (IS_ELKHARTLAKE(dev_priv) && pll->on &&
> > > + pll->info->id == DPLL_ID_EHL_DPLL4) {
> > > + pll->wakeref =
> > > intel_display_power_get(dev_priv,
> > > +
> > > POWER_DOMAIN_DPLL_DC_OFF);
> > > + }
> > > +
> > > pll->state.crtc_mask = 0;
> > > for_each_intel_crtc(dev, crtc) {
> > > struct intel_crtc_state *crtc_state =
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > b/drivers/gpu/drm/i915/display/intel_display_power.c index
> > > c19b958461ca..7437fc71d289 100644 ---
> > > a/drivers/gpu/drm/i915/display/intel_display_power.c +++
> > > b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -118,6
> > > +118,8 @@ intel_display_power_domain_str(enum
> > > intel_display_power_domain domain) return "MODESET"; case
> > > POWER_DOMAIN_GT_IRQ: return "GT_IRQ";
> > > + case POWER_DOMAIN_DPLL_DC_OFF:
> > > + return "DPLL_DC_OFF";
> > > default:
> > > MISSING_CASE(domain);
> > > return "?";
> > > @@ -2455,6 +2457,7 @@ void intel_display_power_put(struct
> > > drm_i915_private *dev_priv, ICL_PW_2_POWER_DOMAINS
> > > | \ BIT_ULL(POWER_DOMAIN_MODESET)
> > > | \ BIT_ULL(POWER_DOMAIN_AUX_A)
> > > | \
> > > + BIT_ULL(POWER_DOMAIN_DPLL_DC_OFF) |
> > > \ BIT_ULL(POWER_DOMAIN_INIT))
> > >
> > > #define ICL_DDI_IO_A_POWER_DOMAINS ( \
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
> > > b/drivers/gpu/drm/i915/display/intel_display_power.h index
> > > ff57b0a7fe59..8f43f7051a16 100644 ---
> > > a/drivers/gpu/drm/i915/display/intel_display_power.h +++
> > > b/drivers/gpu/drm/i915/display/intel_display_power.h @@ -59,6 +59,7
> > > @@ enum intel_display_power_domain { POWER_DOMAIN_GMBUS,
> > >
Re: [Intel-gfx] [PATCH] drm/i915: Make sure cdclk is high enough for DP audio on VLV/CHV
Quoting Ville Syrjala (2019-07-17 12:45:36) > From: Ville Syrjälä > > On VLV/CHV there is some kind of linkage between the cdclk frequency > and the DP link frequency. The spec says: > "For DP audio configuration, cdclk frequency shall be set to > meet the following requirements: > DP Link Frequency(MHz) | Cdclk frequency(MHz) > 270| 320 or higher > 162| 200 or higher" > > I suspect that would more accurately be expressed as > "cdclk >= DP link clock", and in any case we can express it like > that in the code because of the limited set of cdclk and link > frequencies we support. > > Without this we can end up in a situation where the cdclk > is too low and enabling DP audio will kill the pipe. Happens > eg. with 2560x1440 modes where the 266MHz cdclk is sufficient > to pump the pixels (241.5 MHz dotclock) but is too low for > the DP audio due to the link frequency being 270 MHz. > > Cc: sta...@vger.kernel.org > Tested-by: Stefan Gottwald > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=49 > Signed-off-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/display/intel_cdclk.c | 11 +++ > 1 file changed, 11 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c > b/drivers/gpu/drm/i915/display/intel_cdclk.c > index d0581a1ac243..93b0d190c184 100644 > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > @@ -2262,6 +2262,17 @@ int intel_crtc_compute_min_cdclk(const struct > intel_crtc_state *crtc_state) > if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9) > min_cdclk = max(2 * 96000, min_cdclk); > > + /* > +* "For DP audio configuration, cdclk frequency shall be set to > +* meet the following requirements: > +* DP Link Frequency(MHz) | Cdclk frequency(MHz) > +* 270| 320 or higher > +* 162| 200 or higher" > +*/ > + if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && > + intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio) > + min_cdclk = max(crtc_state->port_clock, min_cdclk); I tracked port_clock down to being the dp link clock (162 or 270) so that part of the story checks out. Judging by the rest of the function, I buy that the cdclk and link clock may be inscrutably tied together, and accept the test result that the cdclk must be at least the link clock with audio enabled. It may be that a corner case does require a higher frequency (rather than just bumping from 266 to 270), but for here and now Acked-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 18/22] drm/i915/tgl: Define MOCS entries for Tigerlake
On 7/18/19 6:08 AM, Ville Syrjälä wrote:
On Fri, Jul 12, 2019 at 06:09:36PM -0700, Lucas De Marchi wrote:
From: Tomasz Lis
The MOCS table is published as part of bspec, and versioned. Entries
are supposed to never be modified, but new ones can be added. Adding
entries increases table version. The patch includes version 1 entries.
Two of the 3 legacy entries used for gen9 are no longer expected to work.
Although we are changing the gen11 table, those changes are supposed to
be backward compatible since we are only touching previously undefined
entries.
Cc: Joonas Lahtinen
Cc: Mika Kuoppala
Cc: Daniele Ceraolo Spurio
Signed-off-by: Tomasz Lis
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/intel_mocs.c | 25 ++---
1 file changed, 22 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c
b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 290a5e9b90b9..259e7bec0a63 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -62,6 +62,10 @@ struct drm_i915_mocs_table {
#define GEN11_NUM_MOCS_ENTRIES64 /* 63-64 are reserved, but
configured. */
/* (e)LLC caching options */
+/*
+ * Note: LE_0_PAGETABLE works only up to Gen11; for newer gens it means
+ * the same as LE_UC
+ */
#define LE_0_PAGETABLE_LE_CACHEABILITY(0)
#define LE_1_UC _LE_CACHEABILITY(1)
#define LE_2_WT _LE_CACHEABILITY(2)
@@ -100,8 +104,9 @@ struct drm_i915_mocs_table {
* of bspec.
*
* Entries not part of the following tables are undefined as far as
- * userspace is concerned and shouldn't be relied upon. For the time
- * being they will be initialized to PTE.
+ * userspace is concerned and shouldn't be relied upon. For Gen < 12
+ * they will be initialized to PTE. Gen >= 12 onwards don't have a setting for
+ * PTE. We use the same value, but that actually means Uncached.
*
* The last two entries are reserved by the hardware. For ICL+ they
* should be initialized according to bspec and never used, for older
@@ -137,11 +142,13 @@ static const struct drm_i915_mocs_entry
broxton_mocs_table[] = {
};
#define GEN11_MOCS_ENTRIES \
- /* Base - Uncached (Deprecated) */ \
+ /* Gen11: Base - Uncached (Deprecated) */ \
+ /* Gen12+: Base - Error (Reserved for Non-Use) */ \
MOCS_ENTRY(I915_MOCS_UNCACHED, \
LE_1_UC | LE_TC_1_LLC, \
L3_1_UC), \
/* Base - L3 + LeCC:PAT (Deprecated) */ \
+ /* Gen12+: Base - Reserved */ \
MOCS_ENTRY(I915_MOCS_PTE, \
LE_0_PAGETABLE | LE_TC_1_LLC, \
L3_3_WB), \
@@ -233,6 +240,18 @@ static const struct drm_i915_mocs_entry
broxton_mocs_table[] = {
MOCS_ENTRY(23, \
LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_RSC(1) | LE_SCC(7), \
L3_3_WB), \
+ /* Gen12+: HW Reserved - HDC:L1 + L3 + LLC */ \
Why is this marked as reserved? From the looks of things 48-61 should
just be normal entries that userspace can select to get HDC L1$. And
looks like icl already has that stuff. So someone should probably figure
out if Mesa/etc. can make use of the HDC L1$, and if so we should add
the relevant MOCS entries for icl as well.
Here the reserved terminology is indeed misleading. The 48-59 range is a
"special" range where L1 usage is implicitly enabled by the HW, as there
is no explicit L1 toggle in the MOCS registers. The reserved here means
that the range shouldn't be used for "normal" MOCS settings, but SW can
freely use these entries as needed. Similarly, MOCS 60 and 61 are
reserved for other special purposes, but are still usable by SW. The
only entries SW shouldn't touch are 62 and 63.
Regarding ICL, Gen11 HW doesn't have the capability so no new entries
are required there.
+ MOCS_ENTRY(48, \
+ LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
+ L3_3_WB), \
+ /* Gen12+: HW Reserved - HW Special Case (CCS) */ \
The specs have MOCS 49-51 defined as well.
Daniele
+ MOCS_ENTRY(60, \
+ LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
+ L3_1_UC), \
+ /* Gen12+: HW Reserved - HW Special Case (Displayable) */ \
+ MOCS_ENTRY(61, \
+ LE_1_UC | LE_TC_1_LLC | LE_SCF(1), \
+ L3_3_WB), \
/* HW Reserved - SW program but never use */ \
MOCS_ENTRY(62, \
LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
--
2.21.0
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm: header maintenance
== Series Details ==
Series: drm: header maintenance
URL : https://patchwork.freedesktop.org/series/63900/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6504 -> Patchwork_13691
Summary
---
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13691/
Known issues
Here are the changes found in Patchwork_13691 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_hangcheck:
- fi-icl-u3: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713] /
[fdo#108569])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13691/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [PASS][3] -> [DMESG-WARN][4] ([fdo#102614])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13691/fi-hsw-peppy/igt@kms_frontbuffer_track...@basic.html
Possible fixes
* igt@kms_chamelium@dp-edid-read:
- fi-cml-u2: [FAIL][5] ([fdo#109483]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/fi-cml-u2/igt@kms_chamel...@dp-edid-read.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13691/fi-cml-u2/igt@kms_chamel...@dp-edid-read.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][7] ([fdo#109485]) -> [PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13691/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
Participating hosts (54 -> 45)
--
Additional (1): fi-pnv-d510
Missing(10): fi-kbl-soraka fi-hsw-4770r fi-ilk-m540 fi-byt-squawks
fi-bsw-cyan fi-apl-guc fi-ctg-p8600 fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6504 -> Patchwork_13691
CI_DRM_6504: a23df173f63ed05ae452ab478a01131a89938654 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5102: 6038ace76016d8892f4d13aef5301f71ca1a6e2d @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13691: 96a1d990294f84e9e20e6d0d8d95cf7fcc2c7667 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
96a1d990294f drm: drop uapi dependency from drm_file.h
5e97e4edeb58 drm/mediatek: direct include of drm.h in mtk_drm_gem.c
f01beafe627c drm: direct include of drm.h in drm_syncobj.c
cdd0c64f15fd drm: direct include of drm.h in drm_prime.c
9c025c1aba62 drm: direct include of drm.h in drm_gem_shmem_helper.c
1d8f58ca09c8 drm: direct include of drm.h in drm_gem.c
a64c7d7bde6b drm/vblank: drop use of DRM_WAIT_ON()
3447b6726480 drm/ati_pcigart: drop dependency on drm_os_linux.h
7c8cbcd71261 drm: drop uapi dependency from drm_vblank.h
f605dd5fa4e8 drm: drop uapi dependency from drm_print.h
6910607ff7fd drm/panel: make drm_panel.h self-contained
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13691/
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v1 02/11] drm: drop uapi dependency from drm_print.h
Quoting Sam Ravnborg (2019-07-18 17:14:58) > drm_print.h used DRM_NAME - thus adding a dependency from > include/drm/drm_print.h => uapi/drm/drm.h > > Hardcode the name "drm" to break this dependency. > The idea is that there shall be a minimal dependency > between include/drm/* and uapi/* > > Signed-off-by: Sam Ravnborg > Suggested-by: Daniel Vetter > Reviewed-by: Daniel Vetter > Cc: Maarten Lankhorst > Cc: Maxime Ripard > Cc: Sean Paul > Cc: David Airlie > Cc: Rob Clark > Cc: Sean Paul > Cc: Chris Wilson > Cc: Daniel Vetter > --- > include/drm/drm_print.h | 4 +--- > 1 file changed, 1 insertion(+), 3 deletions(-) > > diff --git a/include/drm/drm_print.h b/include/drm/drm_print.h > index a5d6f2f3e430..760d1bd0eaf1 100644 > --- a/include/drm/drm_print.h > +++ b/include/drm/drm_print.h > @@ -32,8 +32,6 @@ > #include > #include > > -#include > - > /** > * DOC: print > * > @@ -287,7 +285,7 @@ void drm_err(const char *format, ...); > /* Macros to make printk easier */ > > #define _DRM_PRINTK(once, level, fmt, ...) \ > - printk##once(KERN_##level "[" DRM_NAME "] " fmt, ##__VA_ARGS__) > + printk##once(KERN_##level "[drm] " fmt, ##__VA_ARGS__) I guess I'm th only one who #undef DRM_NAME #define DRM_NAME i915 just so that I didn't have inane logs? One might suggest that instead of hardcoding it, follow the pr_fmt() pattern and only add "[drm]" for the drm core. Even then it so useless (which drm driver is this message for???) that I want to remove them all :( -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 05/12] drm/i915: Never set limited_color_range=true for YCbCr output
From: Ville Syrjälä
crtc_state->limited_color_range only applies to RGB output but
we're currently setting it even for YCbCr output. That will
lead to conflicting MSA and PIPECONF settings which can mess
up the image. Let's make sure limited_color_range stays unset
with YCbCr output.
Also WARN if we end up with such a bogus combination when
programming the MSA MISC bits as it's impossible to even
indicate quantization rangle for YCbCr via MSA MISC. YCbCr
output is simply assumed to be limited range always. Note
that VSC SDP does provide a mechanism for full range YCbCr,
so in the future we may want to rethink how we compute/store
this state.
And for good measure we add the same WARN to the HDMI path.
v2: s/==/!=/ in the HDMI WARN
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_ddi.c | 10 +++---
drivers/gpu/drm/i915/display/intel_dp.c | 10 ++
drivers/gpu/drm/i915/display/intel_hdmi.c | 20 +---
3 files changed, 34 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 157c5851a688..7dd54f573f35 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1706,9 +1706,6 @@ void intel_ddi_set_pipe_settings(const struct
intel_crtc_state *crtc_state)
temp = TRANS_MSA_SYNC_CLK;
- if (crtc_state->limited_color_range)
- temp |= TRANS_MSA_CEA_RANGE;
-
switch (crtc_state->pipe_bpp) {
case 18:
temp |= TRANS_MSA_6_BPC;
@@ -1727,6 +1724,13 @@ void intel_ddi_set_pipe_settings(const struct
intel_crtc_state *crtc_state)
break;
}
+ /* nonsense combination */
+ WARN_ON(crtc_state->limited_color_range &&
+ crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
+
+ if (crtc_state->limited_color_range)
+ temp |= TRANS_MSA_CEA_RANGE;
+
/*
* As per DP 1.2 spec section 2.3.4.3 while sending
* YCBCR 444 signals we should program MSA MISC1/0 fields with
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 0eb5d66f87a7..84d2724f0854 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2126,6 +2126,16 @@ bool intel_dp_limited_color_range(const struct
intel_crtc_state *crtc_state,
const struct drm_display_mode *adjusted_mode =
_state->base.adjusted_mode;
+ /*
+* Our YCbCr output is always limited range.
+* crtc_state->limited_color_range only applies to RGB,
+* and it must never be set for YCbCr or we risk setting
+* some conflicting bits in PIPECONF which will mess up
+* the colors on the monitor.
+*/
+ if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
+ return false;
+
if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
/*
* See:
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index ca377ba3a15e..325abd462a46 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -724,6 +724,10 @@ intel_hdmi_compute_avi_infoframe(struct intel_encoder
*encoder,
drm_hdmi_avi_infoframe_colorspace(frame, conn_state);
+ /* nonsense combination */
+ WARN_ON(crtc_state->limited_color_range &&
+ crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
+
if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) {
drm_hdmi_avi_infoframe_quant_range(frame, connector,
adjusted_mode,
@@ -2305,6 +2309,16 @@ static bool intel_hdmi_limited_color_range(const struct
intel_crtc_state *crtc_s
const struct drm_display_mode *adjusted_mode =
_state->base.adjusted_mode;
+ /*
+* Our YCbCr output is always limited range.
+* crtc_state->limited_color_range only applies to RGB,
+* and it must never be set for YCbCr or we risk setting
+* some conflicting bits in PIPECONF which will mess up
+* the colors on the monitor.
+*/
+ if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
+ return false;
+
if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
/* See CEA-861-E - 5.1 Default Encoding Parameters */
return crtc_state->has_hdmi_sink &&
@@ -2341,9 +2355,6 @@ int intel_hdmi_compute_config(struct intel_encoder
*encoder,
if (pipe_config->has_hdmi_sink)
pipe_config->has_infoframe = true;
- pipe_config->limited_color_range =
- intel_hdmi_limited_color_range(pipe_config, conn_state);
-
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm: header maintenance
== Series Details == Series: drm: header maintenance URL : https://patchwork.freedesktop.org/series/63900/ State : warning == Summary == $ dim checkpatch origin/drm-tip 6910607ff7fd drm/panel: make drm_panel.h self-contained f605dd5fa4e8 drm: drop uapi dependency from drm_print.h 7c8cbcd71261 drm: drop uapi dependency from drm_vblank.h 3447b6726480 drm/ati_pcigart: drop dependency on drm_os_linux.h a64c7d7bde6b drm/vblank: drop use of DRM_WAIT_ON() -:42: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #42: FILE: drivers/gpu/drm/drm_vblank.c:1675: + ret = wait_event_interruptible_timeout(vblank->queue, + vblank_passed(drm_vblank_count(dev, pipe), req_seq) || total: 0 errors, 0 warnings, 1 checks, 46 lines checked 1d8f58ca09c8 drm: direct include of drm.h in drm_gem.c 9c025c1aba62 drm: direct include of drm.h in drm_gem_shmem_helper.c cdd0c64f15fd drm: direct include of drm.h in drm_prime.c f01beafe627c drm: direct include of drm.h in drm_syncobj.c 5e97e4edeb58 drm/mediatek: direct include of drm.h in mtk_drm_gem.c 96a1d990294f drm: drop uapi dependency from drm_file.h ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Add HDCP capability info to i915_display_info. (rev2)
== Series Details == Series: drm/i915: Add HDCP capability info to i915_display_info. (rev2) URL : https://patchwork.freedesktop.org/series/63819/ State : success == Summary == CI Bug Log - changes from CI_DRM_6504_full -> Patchwork_13687_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13687_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#110854]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/shard-iclb1/igt@gem_exec_balan...@smoke.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13687/shard-iclb3/igt@gem_exec_balan...@smoke.html * igt@i915_selftest@live_hangcheck: - shard-iclb: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713] / [fdo#108569]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/shard-iclb7/igt@i915_selftest@live_hangcheck.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13687/shard-iclb8/igt@i915_selftest@live_hangcheck.html * igt@i915_suspend@debugfs-reader: - shard-skl: [PASS][5] -> [INCOMPLETE][6] ([fdo#104108]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/shard-skl6/igt@i915_susp...@debugfs-reader.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13687/shard-skl6/igt@i915_susp...@debugfs-reader.html * igt@i915_suspend@fence-restore-tiled2untiled: - shard-apl: [PASS][7] -> [DMESG-WARN][8] ([fdo#108566]) +3 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/shard-apl6/igt@i915_susp...@fence-restore-tiled2untiled.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13687/shard-apl3/igt@i915_susp...@fence-restore-tiled2untiled.html * igt@kms_cursor_crc@pipe-a-cursor-suspend: - shard-skl: [PASS][9] -> [INCOMPLETE][10] ([fdo#110741]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/shard-skl7/igt@kms_cursor_...@pipe-a-cursor-suspend.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13687/shard-skl6/igt@kms_cursor_...@pipe-a-cursor-suspend.html * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic: - shard-hsw: [PASS][11] -> [FAIL][12] ([fdo#105767]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/shard-hsw4/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-atomic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13687/shard-hsw1/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-atomic.html * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: [PASS][13] -> [FAIL][14] ([fdo#105363]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/shard-skl8/igt@kms_f...@flip-vs-expired-vblank.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13687/shard-skl2/igt@kms_f...@flip-vs-expired-vblank.html * igt@kms_flip@modeset-vs-vblank-race-interruptible: - shard-glk: [PASS][15] -> [FAIL][16] ([fdo#103060]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/shard-glk1/igt@kms_f...@modeset-vs-vblank-race-interruptible.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13687/shard-glk9/igt@kms_f...@modeset-vs-vblank-race-interruptible.html * igt@kms_flip_tiling@flip-to-x-tiled: - shard-iclb: [PASS][17] -> [FAIL][18] ([fdo#108134]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/shard-iclb8/igt@kms_flip_til...@flip-to-x-tiled.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13687/shard-iclb6/igt@kms_flip_til...@flip-to-x-tiled.html * igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw: - shard-iclb: [PASS][19] -> [FAIL][20] ([fdo#103167]) +4 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/shard-iclb3/igt@kms_frontbuffer_track...@fbc-1p-pri-indfb-multidraw.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13687/shard-iclb5/igt@kms_frontbuffer_track...@fbc-1p-pri-indfb-multidraw.html * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min: - shard-skl: [PASS][21] -> [FAIL][22] ([fdo#108145]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/shard-skl10/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13687/shard-skl7/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-min.html * igt@kms_plane_lowres@pipe-a-tiling-y: - shard-iclb: [PASS][23] -> [FAIL][24] ([fdo#103166]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/shard-iclb1/igt@kms_plane_low...@pipe-a-tiling-y.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13687/shard-iclb6/igt@kms_plane_low...@pipe-a-tiling-y.html * igt@kms_psr@psr2_cursor_mmap_cpu: - shard-iclb: [PASS][25] -> [SKIP][26] ([fdo#109441]) +6
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: Drop wmb() inside pread_gtt
== Series Details == Series: series starting with [1/4] drm/i915: Drop wmb() inside pread_gtt URL : https://patchwork.freedesktop.org/series/63895/ State : success == Summary == CI Bug Log - changes from CI_DRM_6504 -> Patchwork_13690 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13690/ Known issues Here are the changes found in Patchwork_13690 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s3: - fi-kbl-7567u: [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/fi-kbl-7567u/igt@gem_exec_susp...@basic-s3.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13690/fi-kbl-7567u/igt@gem_exec_susp...@basic-s3.html * igt@i915_module_load@reload-no-display: - fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/fi-icl-u3/igt@i915_module_l...@reload-no-display.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13690/fi-icl-u3/igt@i915_module_l...@reload-no-display.html * igt@i915_selftest@live_hangcheck: - fi-icl-dsi: [PASS][5] -> [INCOMPLETE][6] ([fdo#107713] / [fdo#108569]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13690/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html Possible fixes * igt@kms_chamelium@dp-edid-read: - fi-cml-u2: [FAIL][7] ([fdo#109483]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/fi-cml-u2/igt@kms_chamel...@dp-edid-read.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13690/fi-cml-u2/igt@kms_chamel...@dp-edid-read.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][9] ([fdo#109485]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13690/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483 [fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485 Participating hosts (54 -> 47) -- Additional (1): fi-pnv-d510 Missing(8): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-icl-y fi-byt-clapper fi-bdw-samus Build changes - * Linux: CI_DRM_6504 -> Patchwork_13690 CI_DRM_6504: a23df173f63ed05ae452ab478a01131a89938654 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5102: 6038ace76016d8892f4d13aef5301f71ca1a6e2d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_13690: 7e8db5f4d4f9d58379fd4519ddb4b70b61697e70 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 7e8db5f4d4f9 drm/i915: Flush stale cachelines on set-cache-level de5d49b49195 drm/i915: Flush all user surfaces prior to first use 45e21a6a99db drm/i915: Use maximum write flush for pwrite_gtt 7a958734910b drm/i915: Drop wmb() inside pread_gtt == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13690/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v1 08/11] drm: direct include of drm.h in drm_prime.c
Do not rely on including drm.h from drm_file.h, as the include in drm_file.h will be dropped. Signed-off-by: Sam Ravnborg Cc: Maarten Lankhorst Cc: Maxime Ripard Cc: Sean Paul Cc: David Airlie Cc: Daniel Vetter Cc: Christian König Cc: Noralf Trønnes Cc: Chris Wilson Cc: Eric Anholt --- drivers/gpu/drm/drm_prime.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/drm_prime.c b/drivers/gpu/drm/drm_prime.c index 189d980402ad..eca484106cc2 100644 --- a/drivers/gpu/drm/drm_prime.c +++ b/drivers/gpu/drm/drm_prime.c @@ -30,6 +30,7 @@ #include #include +#include #include #include #include -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v1 07/11] drm: direct include of drm.h in drm_gem_shmem_helper.c
Do not rely on including drm.h from drm_file.h, as the include in drm_file.h will be dropped. Signed-off-by: Sam Ravnborg Cc: Maarten Lankhorst Cc: Maxime Ripard Cc: Sean Paul Cc: David Airlie Cc: Daniel Vetter Cc: Eric Anholt Cc: Thomas Zimmermann Cc: Rob Herring --- drivers/gpu/drm/drm_gem_shmem_helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/drm_gem_shmem_helper.c b/drivers/gpu/drm/drm_gem_shmem_helper.c index 472ea5d81f82..2f64667ac805 100644 --- a/drivers/gpu/drm/drm_gem_shmem_helper.c +++ b/drivers/gpu/drm/drm_gem_shmem_helper.c @@ -10,6 +10,7 @@ #include #include +#include #include #include #include -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v1 10/11] drm/mediatek: direct include of drm.h in mtk_drm_gem.c
Do not rely on including drm.h from drm_file.h, as the include in drm_file.h will be dropped. Signed-off-by: Sam Ravnborg Cc: CK Hu Cc: Philipp Zabel Cc: Matthias Brugger Cc: linux-arm-ker...@lists.infradead.org Cc: linux-media...@lists.infradead.org --- drivers/gpu/drm/mediatek/mtk_drm_gem.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_gem.c b/drivers/gpu/drm/mediatek/mtk_drm_gem.c index 9434f88c6341..ca672f1d140d 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_gem.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_gem.c @@ -5,6 +5,7 @@ #include +#include #include #include #include -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v1 11/11] drm: drop uapi dependency from drm_file.h
drm_file used drm_magic_t from uapi/drm/drm.h.
This is a simple unsigned int.
Just opencode it as such to break the dependency from this header file
to uapi.
Signed-off-by: Sam Ravnborg
Suggested-by: Daniel Vetter
Cc: Sean Paul
Cc: Liviu Dudau
Cc: Chris Wilson
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: David Airlie
Cc: Daniel Vetter
Cc: Jani Nikula
Cc: Eric Anholt
---
include/drm/drm_file.h | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/include/drm/drm_file.h b/include/drm/drm_file.h
index 67af60bb527a..046cd1bf91eb 100644
--- a/include/drm/drm_file.h
+++ b/include/drm/drm_file.h
@@ -34,8 +34,6 @@
#include
#include
-#include
-
#include
struct dma_fence;
@@ -227,7 +225,7 @@ struct drm_file {
struct pid *pid;
/** @magic: Authentication magic, see @authenticated. */
- drm_magic_t magic;
+ unsigned int magic;
/**
* @lhead:
--
2.20.1
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[Intel-gfx] [PATCH v1 05/11] drm/vblank: drop use of DRM_WAIT_ON()
DRM_WAIT_ON() is from the deprecated drm_os_linux header and
the modern replacement is the wait_event_*.
The return values differ, so a conversion is needed to
keep the original interface towards userspace.
Introduced a switch/case to make code obvious and to allow
different debug prints depending on the result.
Signed-off-by: Sam Ravnborg
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: Sean Paul
Cc: David Airlie
Cc: Daniel Vetter
---
drivers/gpu/drm/drm_vblank.c | 29 -
1 file changed, 20 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/drm_vblank.c b/drivers/gpu/drm/drm_vblank.c
index 603ab105125d..8e9ac187500e 100644
--- a/drivers/gpu/drm/drm_vblank.c
+++ b/drivers/gpu/drm/drm_vblank.c
@@ -31,7 +31,6 @@
#include
#include
#include
-#include
#include
#include "drm_internal.h"
@@ -1672,19 +1671,31 @@ int drm_wait_vblank_ioctl(struct drm_device *dev, void
*data,
if (req_seq != seq) {
DRM_DEBUG("waiting on vblank count %llu, crtc %u\n",
req_seq, pipe);
- DRM_WAIT_ON(ret, vblank->queue, 3 * HZ,
- vblank_passed(drm_vblank_count(dev, pipe),
- req_seq) ||
- !READ_ONCE(vblank->enabled));
+ ret = wait_event_interruptible_timeout(vblank->queue,
+ vblank_passed(drm_vblank_count(dev, pipe), req_seq) ||
+ !READ_ONCE(vblank->enabled),
+ msecs_to_jiffies(3000));
}
- if (ret != -EINTR) {
+ switch (ret) {
+ case 0:
+ /* timeout */
+ ret = -EBUSY;
drm_wait_vblank_reply(dev, pipe, >reply);
-
- DRM_DEBUG("crtc %d returning %u to client\n",
+ DRM_DEBUG("timeout waiting for vblank. crtc %d returning %u to
client\n",
pipe, vblwait->reply.sequence);
- } else {
+ break;
+ case -ERESTARTSYS:
+ /* interrupted by signal */
+ ret = -EINTR;
DRM_DEBUG("crtc %d vblank wait interrupted by signal\n", pipe);
+ break;
+ default:
+ ret = 0;
+ drm_wait_vblank_reply(dev, pipe, >reply);
+ DRM_DEBUG("crtc %d returning %u to client\n",
+ pipe, vblwait->reply.sequence);
+ break;
}
done:
--
2.20.1
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[Intel-gfx] [PATCH v1 06/11] drm: direct include of drm.h in drm_gem.c
Do not rely on including drm.h from drm_file.h, as the include in drm_file.h will be dropped. Signed-off-by: Sam Ravnborg Cc: Maarten Lankhorst Cc: Maxime Ripard Cc: Sean Paul Cc: David Airlie Cc: Daniel Vetter Cc: Eric Anholt Cc: Thomas Zimmermann Cc: Rob Herring --- drivers/gpu/drm/drm_gem.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c index e6c12c6ec728..243f43d70f42 100644 --- a/drivers/gpu/drm/drm_gem.c +++ b/drivers/gpu/drm/drm_gem.c @@ -39,6 +39,7 @@ #include #include +#include #include #include #include -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v1 04/11] drm/ati_pcigart: drop dependency on drm_os_linux.h
The drm_os_linux.h header is deprecated.
Just opencode the sole DRM_WRITE32().
Signed-off-by: Sam Ravnborg
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: Sean Paul
Cc: David Airlie
Cc: Daniel Vetter
---
drivers/gpu/drm/ati_pcigart.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/ati_pcigart.c b/drivers/gpu/drm/ati_pcigart.c
index 2a413e291a60..580aa2676358 100644
--- a/drivers/gpu/drm/ati_pcigart.c
+++ b/drivers/gpu/drm/ati_pcigart.c
@@ -35,7 +35,6 @@
#include
#include
-#include
#include
#include
@@ -169,6 +168,7 @@ int drm_ati_pcigart_init(struct drm_device *dev, struct
drm_ati_pcigart_info *ga
page_base = (u32) entry->busaddr[i];
for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) {
+ u32 offset;
u32 val;
switch(gart_info->gart_reg_if) {
@@ -184,10 +184,12 @@ int drm_ati_pcigart_init(struct drm_device *dev, struct
drm_ati_pcigart_info *ga
break;
}
if (gart_info->gart_table_location ==
- DRM_ATI_GART_MAIN)
+ DRM_ATI_GART_MAIN) {
pci_gart[gart_idx] = cpu_to_le32(val);
- else
- DRM_WRITE32(map, gart_idx * sizeof(u32), val);
+ } else {
+ offset = gart_idx * sizeof(u32);
+ writel(val, (void __iomem *)map->handle +
offset);
+ }
gart_idx++;
page_base += ATI_PCIGART_PAGE_SIZE;
}
--
2.20.1
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[Intel-gfx] [PATCH v1 09/11] drm: direct include of drm.h in drm_syncobj.c
Do not rely on including drm.h from drm_file.h, as the include in drm_file.h will be dropped. Signed-off-by: Sam Ravnborg Cc: Maarten Lankhorst Cc: Maxime Ripard Cc: Sean Paul Cc: David Airlie Cc: Daniel Vetter Cc: Lionel Landwerlin Cc: Chunming Zhou Cc: Christian König --- drivers/gpu/drm/drm_syncobj.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/drm_syncobj.c b/drivers/gpu/drm/drm_syncobj.c index a199c8d56b95..75cb4bb7619e 100644 --- a/drivers/gpu/drm/drm_syncobj.c +++ b/drivers/gpu/drm/drm_syncobj.c @@ -53,6 +53,7 @@ #include #include +#include #include #include #include -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v1 02/11] drm: drop uapi dependency from drm_print.h
drm_print.h used DRM_NAME - thus adding a dependency from include/drm/drm_print.h => uapi/drm/drm.h Hardcode the name "drm" to break this dependency. The idea is that there shall be a minimal dependency between include/drm/* and uapi/* Signed-off-by: Sam Ravnborg Suggested-by: Daniel Vetter Reviewed-by: Daniel Vetter Cc: Maarten Lankhorst Cc: Maxime Ripard Cc: Sean Paul Cc: David Airlie Cc: Rob Clark Cc: Sean Paul Cc: Chris Wilson Cc: Daniel Vetter --- include/drm/drm_print.h | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/include/drm/drm_print.h b/include/drm/drm_print.h index a5d6f2f3e430..760d1bd0eaf1 100644 --- a/include/drm/drm_print.h +++ b/include/drm/drm_print.h @@ -32,8 +32,6 @@ #include #include -#include - /** * DOC: print * @@ -287,7 +285,7 @@ void drm_err(const char *format, ...); /* Macros to make printk easier */ #define _DRM_PRINTK(once, level, fmt, ...) \ - printk##once(KERN_##level "[" DRM_NAME "] " fmt, ##__VA_ARGS__) + printk##once(KERN_##level "[drm] " fmt, ##__VA_ARGS__) #define DRM_INFO(fmt, ...) \ _DRM_PRINTK(, INFO, fmt, ##__VA_ARGS__) -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v1 01/11] drm/panel: make drm_panel.h self-contained
From: Jani Nikula
Fix build warning if drm_panel.h is built with CONFIG_OF=n or
CONFIG_DRM_PANEL=n and included without the prerequisite err.h:
./include/drm/drm_panel.h: In function ‘of_drm_find_panel’:
./include/drm/drm_panel.h:203:9: error: implicit declaration of function
‘ERR_PTR’ [-Werror=implicit-function-declaration]
return ERR_PTR(-ENODEV);
^~~
./include/drm/drm_panel.h:203:9: error: returning ‘int’ from a function with
return type ‘struct drm_panel *’ makes pointer from integer without a cast
[-Werror=int-conversion]
return ERR_PTR(-ENODEV);
^~~~
Fixes: 5fa8e4a22182 ("drm/panel: Make of_drm_find_panel() return an ERR_PTR()
instead of NULL")
Cc: Boris Brezillon
Signed-off-by: Jani Nikula
Acked-by: Thierry Reding
Reviewed-by: Sam Ravnborg
---
include/drm/drm_panel.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/drm/drm_panel.h b/include/drm/drm_panel.h
index 8c738c0e6e9f..26377836141c 100644
--- a/include/drm/drm_panel.h
+++ b/include/drm/drm_panel.h
@@ -24,6 +24,7 @@
#ifndef __DRM_PANEL_H__
#define __DRM_PANEL_H__
+#include
#include
#include
--
2.20.1
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[Intel-gfx] [PATCH v1 03/11] drm: drop uapi dependency from drm_vblank.h
drm_vblank.h included uapi/drm/drm.h. It turns out this include was not required - delete it. Note: uapi/drm/drm.h is included indirect via drm_file.h, but there are no dependencies in drm_vblank.h so the removal is legit. Signed-off-by: Sam Ravnborg Reviewed-by: Daniel Vetter Cc: Maarten Lankhorst Cc: Maxime Ripard Cc: Sean Paul Cc: David Airlie Cc: Daniel Vetter Cc: Stefan Agner Cc: Thierry Reding --- include/drm/drm_vblank.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/drm/drm_vblank.h b/include/drm/drm_vblank.h index e528bb2f659d..9fe4ba8bc622 100644 --- a/include/drm/drm_vblank.h +++ b/include/drm/drm_vblank.h @@ -30,7 +30,6 @@ #include #include -#include struct drm_device; struct drm_crtc; -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v1 0/11] drm: header maintenance
First patch from Jani fixes so drm_print.h is self-contained. Next two patches are trivial removal of uapi dependencies. ati_pcigart is fixed to drop use of drm_os_linux.h drm_vblank is likewise fixed to drop use of drm_os_linux.h This was a non-trivial conversion, *review requested!* The remaining patches are preparation for and removal of uapi/drm/drmh from drm_file.h. There were a few files where we had to push include of drm/drm.h out to to have a clean build. CK Hu - please let me apply the mediatek patch to drm-misc-next, as it is required for the final patch. Or push it to drm-misc-next yourself. Sam Jani Nikula (1): drm/panel: make drm_panel.h self-contained Sam Ravnborg (10): drm: drop uapi dependency from drm_print.h drm: drop uapi dependency from drm_vblank.h drm/ati_pcigart: drop dependency on drm_os_linux.h drm/vblank: drop use of DRM_WAIT_ON() drm: direct include of drm.h in drm_gem.c drm: direct include of drm.h in drm_gem_shmem_helper.c drm: direct include of drm.h in drm_prime.c drm: direct include of drm.h in drm_syncobj.c drm/mediatek: direct include of drm.h in mtk_drm_gem.c drm: drop uapi dependency from drm_file.h drivers/gpu/drm/ati_pcigart.c | 10 ++ drivers/gpu/drm/drm_gem.c | 1 + drivers/gpu/drm/drm_gem_shmem_helper.c | 1 + drivers/gpu/drm/drm_prime.c| 1 + drivers/gpu/drm/drm_syncobj.c | 1 + drivers/gpu/drm/drm_vblank.c | 29 - drivers/gpu/drm/mediatek/mtk_drm_gem.c | 1 + include/drm/drm_file.h | 4 +--- include/drm/drm_panel.h| 1 + include/drm/drm_print.h| 4 +--- include/drm/drm_vblank.h | 1 - 11 files changed, 34 insertions(+), 20 deletions(-) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/guc: Allocate non-swappable memory for internal objects
On 7/18/19 2:29 AM, Chris Wilson wrote: All internal GuC objects are perma-pinned into the GGTT and thus not-swapped. We do not need to allocate a shmemfs inode for these, merely a collection of pages to be kept in memory. Signed-off-by: Chris Wilson Cc: Daniele Ceraolo Spurio Cc: Michal Wajdeczko Makes sense. Reviewed-by: Daniele Ceraolo Spurio Daniele --- drivers/gpu/drm/i915/gt/uc/intel_guc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c index 83f2c197375f..d66f8f9c5654 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c @@ -582,7 +582,7 @@ struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size) u64 flags; int ret; - obj = i915_gem_object_create_shmem(gt->i915, size); + obj = i915_gem_object_create_internal(gt->i915, size); if (IS_ERR(obj)) return ERR_CAST(obj); ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915: Drop wmb() inside pread_gtt
== Series Details == Series: series starting with [1/4] drm/i915: Drop wmb() inside pread_gtt URL : https://patchwork.freedesktop.org/series/63895/ State : warning == Summary == $ dim checkpatch origin/drm-tip 7a958734910b drm/i915: Drop wmb() inside pread_gtt 45e21a6a99db drm/i915: Use maximum write flush for pwrite_gtt de5d49b49195 drm/i915: Flush all user surfaces prior to first use -:12: ERROR:BAD_SIGN_OFF: Unrecognized email address: 'stablevger.kernel.org' #12: Cc: stablevger.kernel.org total: 1 errors, 0 warnings, 0 checks, 38 lines checked 7e8db5f4d4f9 drm/i915: Flush stale cachelines on set-cache-level ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: YCbCr output fixes and prep work for YCbCr 4:4:4 output
== Series Details ==
Series: drm/i915: YCbCr output fixes and prep work for YCbCr 4:4:4 output
URL : https://patchwork.freedesktop.org/series/63893/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6504 -> Patchwork_13689
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_13689 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_13689, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13689/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_13689:
### IGT changes ###
Possible regressions
* igt@runner@aborted:
- fi-elk-e7500: NOTRUN -> [FAIL][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13689/fi-elk-e7500/igt@run...@aborted.html
Known issues
Here are the changes found in Patchwork_13689 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_execlists:
- fi-skl-gvtdvm: [PASS][2] -> [DMESG-FAIL][3] ([fdo#08])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13689/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-dsi: [PASS][4] -> [FAIL][5] ([fdo#103167])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/fi-icl-dsi/igt@kms_frontbuffer_track...@basic.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13689/fi-icl-dsi/igt@kms_frontbuffer_track...@basic.html
Possible fixes
* igt@i915_selftest@live_contexts:
- fi-skl-iommu: [INCOMPLETE][6] ([fdo#111050]) -> [PASS][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/fi-skl-iommu/igt@i915_selftest@live_contexts.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13689/fi-skl-iommu/igt@i915_selftest@live_contexts.html
* igt@kms_chamelium@dp-edid-read:
- fi-cml-u2: [FAIL][8] ([fdo#109483]) -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/fi-cml-u2/igt@kms_chamel...@dp-edid-read.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13689/fi-cml-u2/igt@kms_chamel...@dp-edid-read.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#111050]: https://bugs.freedesktop.org/show_bug.cgi?id=111050
[fdo#08]: https://bugs.freedesktop.org/show_bug.cgi?id=08
Participating hosts (54 -> 47)
--
Additional (1): fi-pnv-d510
Missing(8): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan
fi-ctg-p8600 fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6504 -> Patchwork_13689
CI_DRM_6504: a23df173f63ed05ae452ab478a01131a89938654 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5102: 6038ace76016d8892f4d13aef5301f71ca1a6e2d @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13689: 985c707847c7471fcade73d2aa8c9c375ad50913 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
985c707847c7 drm/i915: Add PIPECONF YCbCr 4:4:4 programming for ILK-IVB
1ce37b6590eb drm/i915: Set up ILK/SNB csc unit properly for YCbCr output
a3c1fea79f0b drm/i915: Document ILK+ pipe csc matrix better
9c51a29d74fc drm/i915: Add PIPECONF YCbCr 4:4:4 programming for HSW
806f0a57b948 drm/i915: Simplify intel_get_crtc_ycbcr_config()
6edc454dc574 drm/i915: Don't look at unrelated PIPECONF bits for interlaced
readout
b1b80c557cc9 drm/i915: Switch to using DP_MSA_MISC_* defines
28ba8a634de4 drm/i915: Never set limited_color_range=true for YCbCr output
1cdc700d9b55 drm/i915: Extract intel_hdmi_limited_color_range()
0aca35d5a6a0 drm/i915: Fix AVI infoframe quantization range for YCbCr output
4c049b738100 drm/i915: Fix HSW+ DP MSA YCbCr colorspace indication
b90758beb5b5 drm/dp: Add definitons for MSA MISC bits
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13689/
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Re: [Intel-gfx] [PATCH v2] drm/i915: Add HDCP capability info to i915_display_info.
On 2019-07-18 at 19:34:44 +0530, Anshuman Gupta wrote:
> To identify the HDCP capability of the display connected to CI
> systems, we need to add the hdcp capability probing in i915_display_info.
>
> This will also help to populate the HDCP capability of the CI systems
> to CI H/W logs maintained at https://intel-gfx-ci.01.org/hardware/.
> It will facilitate to determine the kms_content_protection behavior on
> a particular CI system.
>
> v2: Reused the intel_hdcp_info() in i915_hdcp_sink_capability_show(). [Ram]
> Shifted intel_hdcp_info() to the end of intel_dp_info. [Ram]
>
> Cc: daniel.vet...@intel.com
> Cc: ramalinga...@intel.com
> Signed-off-by: Anshuman Gupta
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 40 -
> 1 file changed, 28 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 6b84d04a6a28..d663f65101df 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2569,6 +2569,25 @@ static void intel_panel_info(struct seq_file *m,
> struct intel_panel *panel)
> intel_seq_print_mode(m, 2, mode);
> }
>
> +static void intel_hdcp_info(struct seq_file *m,
> + struct intel_connector *intel_connector)
alignment.
> +{
> + bool hdcp_cap, hdcp2_cap;
> +
> + hdcp_cap = intel_hdcp_capable(intel_connector);
> + hdcp2_cap = intel_hdcp2_capable(intel_connector);
> +
> + if (hdcp_cap)
> + seq_puts(m, "HDCP1.4 ");
> + if (hdcp2_cap)
> + seq_puts(m, "HDCP2.2 ");
> +
> + if (!hdcp_cap && !hdcp2_cap)
> + seq_puts(m, "None");
> +
> + seq_puts(m, "\n");
> +}
> +
> static void intel_dp_info(struct seq_file *m,
> struct intel_connector *intel_connector)
> {
> @@ -2582,6 +2601,10 @@ static void intel_dp_info(struct seq_file *m,
>
> drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports,
> _dp->aux);
> + if (intel_connector->hdcp.shim) {
> + seq_printf(m, "\tHDCP version: ");
use seq_puts() instead.
> + intel_hdcp_info(m, intel_connector);
> + }
> }
>
> static void intel_dp_mst_info(struct seq_file *m,
> @@ -2605,6 +2628,10 @@ static void intel_hdmi_info(struct seq_file *m,
> struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(_encoder->base);
>
> seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
> + if (intel_connector->hdcp.shim) {
> + seq_printf(m, "\tHDCP version: ");
use seq_puts() instead.
BR
-Ram
> + intel_hdcp_info(m, intel_connector);
> + }
> }
>
> static void intel_lvds_info(struct seq_file *m,
> @@ -4528,7 +4555,6 @@ static int i915_hdcp_sink_capability_show(struct
> seq_file *m, void *data)
> {
> struct drm_connector *connector = m->private;
> struct intel_connector *intel_connector = to_intel_connector(connector);
> - bool hdcp_cap, hdcp2_cap;
>
> if (connector->status != connector_status_connected)
> return -ENODEV;
> @@ -4539,17 +4565,7 @@ static int i915_hdcp_sink_capability_show(struct
> seq_file *m, void *data)
>
> seq_printf(m, "%s:%d HDCP version: ", connector->name,
> connector->base.id);
> - hdcp_cap = intel_hdcp_capable(intel_connector);
> - hdcp2_cap = intel_hdcp2_capable(intel_connector);
> -
> - if (hdcp_cap)
> - seq_puts(m, "HDCP1.4 ");
> - if (hdcp2_cap)
> - seq_puts(m, "HDCP2.2 ");
> -
> - if (!hdcp_cap && !hdcp2_cap)
> - seq_puts(m, "None");
> - seq_puts(m, "\n");
> + intel_hdcp_info(m, intel_connector);
>
> return 0;
> }
> --
> 2.21.0
>
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[Intel-gfx] [PULL] drm-misc-next-fixes
Hi team, I am Guest-Maarten this week and next! Not exactly a quiet last PR for the merge window, but I think this is right in line with how things have gone over the rest of 5.3. Although there's more volume than we'd like, I don't think there's anything here that is contraversial. So, welcome komeda to -misc, and happy pulling :-) drm-misc-next-fixes-2019-07-18: - Rip out komeda internal properties and move the driver to -misc (Daniel) - Handle a couple edge cases with incomplete/incorrect cmdline modes (Dmitry) - Fix some silly warnings (Arnd) - Add orientation quirk for newer GPD MicroPCs (Hans) Cc: Daniel Vetter Cc: Liviu Dudau Cc: Dmitry Osipenko Cc: Arnd Bergmann Cc: Hans de Goede Cheers, Sean The following changes since commit daed277e4d5ace0883d30b9be245d35c46289f49: Merge tag 'topic/remove-fbcon-notifiers-2019-06-26' into drm-misc-next-fixes (2019-06-26 12:26:34 +0200) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-next-fixes-2019-07-18 for you to fetch changes up to 7aaddd96d5febcf5b24357a326b3038d49a20532: drm/modes: Don't apply cmdline's rotation if it wasn't specified (2019-07-16 10:34:38 +0200) - Rip out komeda internal properties and move the driver to -misc (Daniel) - Handle a couple edge cases with incomplete/incorrect cmdline modes (Dmitry) - Fix some silly warnings (Arnd) - Add orientation quirk for newer GPD MicroPCs (Hans) Cc: Daniel Vetter Cc: Liviu Dudau Cc: Dmitry Osipenko Cc: Arnd Bergmann Cc: Hans de Goede Arnd Bergmann (2): drm/selftests: reduce stack usage drm: connector: remove bogus NULL check Daniel Vetter (5): drm/komeda: Remove clock ratio property drm/komeda: remove slave_planes property drm/komeda: remove img_enhancement property drm/komeda: Remove layer_split property MAINTAINERS: maintain drm/arm drivers in drm-misc for now Dmitry Osipenko (2): drm/modes: Skip invalid cmdline mode drm/modes: Don't apply cmdline's rotation if it wasn't specified Gerd Hoffmann (1): drm/bochs: fix framebuffer setup. Hans de Goede (1): drm: panel-orientation-quirks: Add extra quirk table entry for GPD MicroPC james qian wang (Arm Technology China) (2): drm/komeda: Computing layer_split internally drm/komeda: Computing image enhancer internally MAINTAINERS| 4 +- drivers/gpu/drm/arm/display/komeda/komeda_crtc.c | 63 -- drivers/gpu/drm/arm/display/komeda/komeda_kms.h| 18 +-- .../gpu/drm/arm/display/komeda/komeda_pipeline.h | 3 +- .../drm/arm/display/komeda/komeda_pipeline_state.c | 15 ++- drivers/gpu/drm/arm/display/komeda/komeda_plane.c | 84 + .../drm/arm/display/komeda/komeda_wb_connector.c | 10 +- drivers/gpu/drm/bochs/bochs.h | 2 +- drivers/gpu/drm/bochs/bochs_hw.c | 14 ++- drivers/gpu/drm/bochs/bochs_kms.c | 3 +- drivers/gpu/drm/drm_client_modeset.c | 5 +- drivers/gpu/drm/drm_connector.c| 2 +- drivers/gpu/drm/drm_modes.c| 14 ++- drivers/gpu/drm/drm_panel_orientation_quirks.c | 12 ++ .../gpu/drm/selftests/test-drm_cmdline_parser.c| 136 - include/drm/drm_modes.h| 2 +- 16 files changed, 110 insertions(+), 277 deletions(-) -- Sean Paul, Software Engineer, Google / Chromium OS ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: Refuse modes with hdisplay==4096 on pre-HSW DP
== Series Details ==
Series: series starting with [1/2] drm/i915: Refuse modes with hdisplay==4096
on pre-HSW DP
URL : https://patchwork.freedesktop.org/series/63892/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6504 -> Patchwork_13688
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_13688 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_13688, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13688/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_13688:
### IGT changes ###
Possible regressions
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-icl-dsi: [PASS][1] -> [DMESG-WARN][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/fi-icl-dsi/igt@i915_pm_...@basic-pci-d3-state.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13688/fi-icl-dsi/igt@i915_pm_...@basic-pci-d3-state.html
Known issues
Here are the changes found in Patchwork_13688 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_execlists:
- fi-skl-gvtdvm: [PASS][3] -> [DMESG-FAIL][4] ([fdo#08])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13688/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
* igt@kms_chamelium@dp-crc-fast:
- fi-cml-u2: [PASS][5] -> [FAIL][6] ([fdo#110387])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13688/fi-cml-u2/igt@kms_chamel...@dp-crc-fast.html
* igt@kms_chamelium@dp-edid-read:
- fi-icl-u2: [PASS][7] -> [FAIL][8] ([fdo#109483] / [fdo#109635 ])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/fi-icl-u2/igt@kms_chamel...@dp-edid-read.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13688/fi-icl-u2/igt@kms_chamel...@dp-edid-read.html
Possible fixes
* igt@i915_selftest@live_contexts:
- fi-skl-iommu: [INCOMPLETE][9] ([fdo#111050]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/fi-skl-iommu/igt@i915_selftest@live_contexts.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13688/fi-skl-iommu/igt@i915_selftest@live_contexts.html
* igt@kms_chamelium@dp-edid-read:
- fi-cml-u2: [FAIL][11] ([fdo#109483]) -> [PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6504/fi-cml-u2/igt@kms_chamel...@dp-edid-read.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13688/fi-cml-u2/igt@kms_chamel...@dp-edid-read.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635
[fdo#110387]: https://bugs.freedesktop.org/show_bug.cgi?id=110387
[fdo#111050]: https://bugs.freedesktop.org/show_bug.cgi?id=111050
[fdo#08]: https://bugs.freedesktop.org/show_bug.cgi?id=08
Participating hosts (54 -> 47)
--
Additional (1): fi-pnv-d510
Missing(8): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan
fi-ctg-p8600 fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-
* Linux: CI_DRM_6504 -> Patchwork_13688
CI_DRM_6504: a23df173f63ed05ae452ab478a01131a89938654 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_5102: 6038ace76016d8892f4d13aef5301f71ca1a6e2d @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13688: 9d15f10da0053840cd206fd0a0c44673cae44520 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
9d15f10da005 drm/i915: Check some transcoder timing minimum limits
67e1394573e5 drm/i915: Refuse modes with hdisplay==4096 on pre-HSW DP
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13688/
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Move global activity tracking from GEM to GT
== Series Details == Series: drm/i915: Move global activity tracking from GEM to GT URL : https://patchwork.freedesktop.org/series/63884/ State : success == Summary == CI Bug Log - changes from CI_DRM_6503_full -> Patchwork_13686_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_13686_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_eio@unwedge-stress: - shard-snb: [PASS][1] -> [FAIL][2] ([fdo#109661]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6503/shard-snb6/igt@gem_...@unwedge-stress.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13686/shard-snb6/igt@gem_...@unwedge-stress.html * igt@i915_pm_rpm@i2c: - shard-hsw: [PASS][3] -> [FAIL][4] ([fdo#104097]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6503/shard-hsw4/igt@i915_pm_...@i2c.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13686/shard-hsw6/igt@i915_pm_...@i2c.html * igt@i915_suspend@fence-restore-tiled2untiled: - shard-apl: [PASS][5] -> [DMESG-WARN][6] ([fdo#108566]) +4 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6503/shard-apl1/igt@i915_susp...@fence-restore-tiled2untiled.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13686/shard-apl3/igt@i915_susp...@fence-restore-tiled2untiled.html * igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size: - shard-iclb: [PASS][7] -> [INCOMPLETE][8] ([fdo#107713]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6503/shard-iclb8/igt@kms_cursor_leg...@cursor-vs-flip-atomic-transitions-varying-size.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13686/shard-iclb7/igt@kms_cursor_leg...@cursor-vs-flip-atomic-transitions-varying-size.html * igt@kms_flip@modeset-vs-vblank-race-interruptible: - shard-glk: [PASS][9] -> [FAIL][10] ([fdo#103060]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6503/shard-glk4/igt@kms_f...@modeset-vs-vblank-race-interruptible.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13686/shard-glk4/igt@kms_f...@modeset-vs-vblank-race-interruptible.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt: - shard-iclb: [PASS][11] -> [FAIL][12] ([fdo#103167]) +4 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6503/shard-iclb1/igt@kms_frontbuffer_track...@fbc-1p-primscrn-spr-indfb-draw-blt.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13686/shard-iclb2/igt@kms_frontbuffer_track...@fbc-1p-primscrn-spr-indfb-draw-blt.html * igt@kms_plane@pixel-format-pipe-c-planes-source-clamping: - shard-iclb: [PASS][13] -> [INCOMPLETE][14] ([fdo#107713] / [fdo#110036 ]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6503/shard-iclb2/igt@kms_pl...@pixel-format-pipe-c-planes-source-clamping.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13686/shard-iclb3/igt@kms_pl...@pixel-format-pipe-c-planes-source-clamping.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][15] -> [FAIL][16] ([fdo#108145] / [fdo#110403]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6503/shard-skl9/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13686/shard-skl4/igt@kms_plane_alpha_bl...@pipe-c-coverage-7efc.html * igt@kms_plane_lowres@pipe-a-tiling-y: - shard-iclb: [PASS][17] -> [FAIL][18] ([fdo#103166]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6503/shard-iclb3/igt@kms_plane_low...@pipe-a-tiling-y.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13686/shard-iclb1/igt@kms_plane_low...@pipe-a-tiling-y.html * igt@kms_psr2_su@frontbuffer: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109642] / [fdo#111068]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6503/shard-iclb2/igt@kms_psr2...@frontbuffer.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13686/shard-iclb7/igt@kms_psr2...@frontbuffer.html * igt@kms_setmode@basic: - shard-kbl: [PASS][21] -> [FAIL][22] ([fdo#99912]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6503/shard-kbl2/igt@kms_setm...@basic.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13686/shard-kbl7/igt@kms_setm...@basic.html * igt@kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [PASS][23] -> [DMESG-WARN][24] ([fdo#108566]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6503/shard-kbl4/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13686/shard-kbl6/igt@kms_vbl...@pipe-a-ts-continuation-suspend.html Possible fixes *
[Intel-gfx] [PATCH 3/4] drm/i915: Flush all user surfaces prior to first use
Since userspace has the ability to bypass the CPU cache from within its
unprivileged command stream, we have to flush the CPU cache to memory
in order to overwrite the previous contents on creation.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: stablevger.kernel.org
---
drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 26 ++-
1 file changed, 7 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
index d2a1158868e7..f752b326d399 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
@@ -459,7 +459,6 @@ i915_gem_object_create_shmem(struct drm_i915_private *i915,
u64 size)
{
struct drm_i915_gem_object *obj;
struct address_space *mapping;
- unsigned int cache_level;
gfp_t mask;
int ret;
@@ -498,24 +497,13 @@ i915_gem_object_create_shmem(struct drm_i915_private
*i915, u64 size)
obj->write_domain = I915_GEM_DOMAIN_CPU;
obj->read_domains = I915_GEM_DOMAIN_CPU;
- if (HAS_LLC(i915))
- /* On some devices, we can have the GPU use the LLC (the CPU
-* cache) for about a 10% performance improvement
-* compared to uncached. Graphics requests other than
-* display scanout are coherent with the CPU in
-* accessing this cache. This means in this mode we
-* don't need to clflush on the CPU side, and on the
-* GPU side we only need to flush internal caches to
-* get data visible to the CPU.
-*
-* However, we maintain the display planes as UC, and so
-* need to rebind when first used as such.
-*/
- cache_level = I915_CACHE_LLC;
- else
- cache_level = I915_CACHE_NONE;
-
- i915_gem_object_set_cache_coherency(obj, cache_level);
+ /*
+* Note that userspace has control over cache-bypass
+* via its command stream, so even on LLC architectures
+* we have to flush out the CPU cache to memory to
+* clear previous contents.
+*/
+ i915_gem_object_set_cache_coherency(obj, I915_CACHE_NONE);
trace_i915_gem_object_create(obj);
--
2.22.0
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[Intel-gfx] [PATCH 2/4] drm/i915: Use maximum write flush for pwrite_gtt
As recently disovered by forcing big-core (!llc) machines to use the GTT
paths, we need our full GTT write flush before manipulating the GTT PTE
or else the writes may be directed to the wrong page.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Matthew Auld
Cc: Ville Syrjälä
Cc: sta...@vger.kernel.org
---
drivers/gpu/drm/i915/i915_gem.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index fed0bc421a55..c6ba350e6e4f 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -610,7 +610,8 @@ i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj,
unsigned int page_length = PAGE_SIZE - page_offset;
page_length = remain < page_length ? remain : page_length;
if (node.allocated) {
- wmb(); /* flush the write before we modify the GGTT */
+ /* flush the write before we modify the GGTT */
+ intel_gt_flush_ggtt_writes(ggtt->vm.gt);
ggtt->vm.insert_page(>vm,
i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT),
node.start, I915_CACHE_NONE, 0);
@@ -639,8 +640,8 @@ i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj,
i915_gem_object_unlock_fence(obj, fence);
out_unpin:
mutex_lock(>drm.struct_mutex);
+ intel_gt_flush_ggtt_writes(ggtt->vm.gt);
if (node.allocated) {
- wmb();
ggtt->vm.clear_range(>vm, node.start, node.size);
remove_mappable_node();
} else {
--
2.22.0
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[Intel-gfx] [PATCH 4/4] drm/i915: Flush stale cachelines on set-cache-level
Ensure that we flush any cache dirt out to main memory before the user changes the cache-level as they may elect to bypass the cache (even after declaring their access cache-coherent) via use of unprivileged MOCS. Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Cc: sta...@vger.kernel.org --- drivers/gpu/drm/i915/gem/i915_gem_domain.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c index 2e3ce2a69653..5d41e769a428 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c @@ -277,6 +277,11 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, list_for_each_entry(vma, >vma.list, obj_link) vma->node.color = cache_level; + + /* Flush any previous cache dirt in case of cache bypass */ + if (obj->cache_dirty & ~obj->cache_coherent) + i915_gem_clflush_object(obj, I915_CLFLUSH_SYNC); + i915_gem_object_set_cache_coherency(obj, cache_level); obj->cache_dirty = true; /* Always invalidate stale cachelines */ -- 2.22.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/4] drm/i915: Drop wmb() inside pread_gtt
Inside pread, we only ever read from the GTT so the serialising wmb()
instructions around the GGTT PTE updates are pointless.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index a207b90924e4..fed0bc421a55 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -395,11 +395,9 @@ i915_gem_gtt_pread(struct drm_i915_gem_object *obj,
unsigned page_length = PAGE_SIZE - page_offset;
page_length = remain < page_length ? remain : page_length;
if (node.allocated) {
- wmb();
ggtt->vm.insert_page(>vm,
i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT),
node.start, I915_CACHE_NONE, 0);
- wmb();
} else {
page_base += offset & PAGE_MASK;
}
@@ -419,7 +417,6 @@ i915_gem_gtt_pread(struct drm_i915_gem_object *obj,
out_unpin:
mutex_lock(>drm.struct_mutex);
if (node.allocated) {
- wmb();
ggtt->vm.clear_range(>vm, node.start, node.size);
remove_mappable_node();
} else {
--
2.22.0
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[Intel-gfx] [PATCH 09/12] drm/i915: Add PIPECONF YCbCr 4:4:4 programming for HSW
From: Ville Syrjälä
On HSW the pipe colorspace is configured via PIPECONF
(as opposed to PIPEMISC in BDW+). Let's configure+readout
that stuff correctly.
Enablling YCbCr 4:4:4 output will now be a simple matter of
setting crtc_state->output_format appropriately in the encoder
.compute_config().
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 13 -
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 1dd1aa29a649..bd3ff96c1618 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -9430,6 +9430,10 @@ static void haswell_set_pipeconf(const struct
intel_crtc_state *crtc_state)
else
val |= PIPECONF_PROGRESSIVE;
+ if (IS_HASWELL(dev_priv) &&
+ crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
+ val |= PIPECONF_OUTPUT_COLORSPACE_YUV_HSW;
+
I915_WRITE(PIPECONF(cpu_transcoder), val);
POSTING_READ(PIPECONF(cpu_transcoder));
}
@@ -10423,7 +10427,14 @@ static bool haswell_get_pipe_config(struct intel_crtc
*crtc,
intel_get_pipe_src_size(crtc, pipe_config);
- if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) {
+ if (IS_HASWELL(dev_priv)) {
+ u32 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
+
+ if (tmp & PIPECONF_OUTPUT_COLORSPACE_YUV_HSW)
+ pipe_config->output_format =
INTEL_OUTPUT_FORMAT_YCBCR444;
+ else
+ pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
+ } else {
pipe_config->output_format =
bdw_get_pipemisc_output_format(crtc);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 66f7f417231f..58471312b8b2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5712,6 +5712,7 @@ enum {
#define PIPECONF_CXSR_DOWNCLOCK (1 << 16)
#define PIPECONF_EDP_RR_MODE_SWITCH_VLV (1 << 14)
#define PIPECONF_COLOR_RANGE_SELECT (1 << 13)
+#define PIPECONF_OUTPUT_COLORSPACE_YUV_HSW (1 << 11) /* hsw only */
#define PIPECONF_BPC_MASK(0x7 << 5)
#define PIPECONF_8BPC(0 << 5)
#define PIPECONF_10BPC (1 << 5)
--
2.21.0
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[Intel-gfx] [PATCH 12/12] drm/i915: Add PIPECONF YCbCr 4:4:4 programming for ILK-IVB
From: Ville Syrjälä
On ILK-IVB the pipe colorspace is configured via PIPECONF
(as opposed to PIPEMISC in BDW+). Let's configure+readout
that stuff correctly.
Enablling YCbCr 4:4:4 output will now be a simple matter of
setting crtc_state->output_format appropriately in the encoder
.compute_config(). However, when we do that we must be
aware of the fact that YCbCr DP output doesn't seem to work
on ILK (resulting image is totally garbled), but on SNB+
it works fine. However HDMI YCbCr output does work correctly
even on ILK.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 21 +++-
drivers/gpu/drm/i915/i915_reg.h | 4
2 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index bd3ff96c1618..8e98715cd63b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -9406,9 +9406,19 @@ static void ironlake_set_pipeconf(const struct
intel_crtc_state *crtc_state)
else
val |= PIPECONF_PROGRESSIVE;
+ /*
+* This would end up with an odd purple hue over
+* the entire display. Make sure we don't do it.
+*/
+ WARN_ON(crtc_state->limited_color_range &&
+ crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
+
if (crtc_state->limited_color_range)
val |= PIPECONF_COLOR_RANGE_SELECT;
+ if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
+ val |= PIPECONF_OUTPUT_COLORSPACE_YUV709;
+
val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
I915_WRITE(PIPECONF(pipe), val);
@@ -9945,7 +9955,6 @@ static bool ironlake_get_pipe_config(struct intel_crtc
*crtc,
if (!wakeref)
return false;
- pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
pipe_config->shared_dpll = NULL;
@@ -9974,6 +9983,16 @@ static bool ironlake_get_pipe_config(struct intel_crtc
*crtc,
if (tmp & PIPECONF_COLOR_RANGE_SELECT)
pipe_config->limited_color_range = true;
+ switch (tmp & PIPECONF_OUTPUT_COLORSPACE_MASK) {
+ case PIPECONF_OUTPUT_COLORSPACE_YUV601:
+ case PIPECONF_OUTPUT_COLORSPACE_YUV709:
+ pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
+ break;
+ default:
+ pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
+ break;
+ }
+
pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK) >>
PIPECONF_GAMMA_MODE_SHIFT;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 33d535ae0944..3d33a1e03a45 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5712,6 +5712,10 @@ enum {
#define PIPECONF_CXSR_DOWNCLOCK (1 << 16)
#define PIPECONF_EDP_RR_MODE_SWITCH_VLV (1 << 14)
#define PIPECONF_COLOR_RANGE_SELECT (1 << 13)
+#define PIPECONF_OUTPUT_COLORSPACE_MASK (3 << 11) /* ilk-ivb */
+#define PIPECONF_OUTPUT_COLORSPACE_RGB (0 << 11) /* ilk-ivb */
+#define PIPECONF_OUTPUT_COLORSPACE_YUV601(1 << 11) /* ilk-ivb */
+#define PIPECONF_OUTPUT_COLORSPACE_YUV709(2 << 11) /* ilk-ivb */
#define PIPECONF_OUTPUT_COLORSPACE_YUV_HSW (1 << 11) /* hsw only */
#define PIPECONF_BPC_MASK(0x7 << 5)
#define PIPECONF_8BPC(0 << 5)
--
2.21.0
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[Intel-gfx] [PATCH 08/12] drm/i915: Simplify intel_get_crtc_ycbcr_config()
From: Ville Syrjälä
Make intel_get_crtc_ycbcr_config() simpler and rename it
to bdw_get_pipemisc_output_format() to better reflect what
it does.
Also toss in some comments to document that the 4:2:0 PIPECONF
bits are glk+ only. They are mbz on earlier platforms so reading
them unconditionally is safe however.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 71 +---
drivers/gpu/drm/i915/i915_reg.h | 4 +-
2 files changed, 34 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index ffdc350dc24a..1dd1aa29a649 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8713,47 +8713,24 @@ static void chv_crtc_clock_get(struct intel_crtc *crtc,
pipe_config->port_clock = chv_calc_dpll_params(refclk, );
}
-static void intel_get_crtc_ycbcr_config(struct intel_crtc *crtc,
- struct intel_crtc_state *pipe_config)
+static enum intel_output_format
+bdw_get_pipemisc_output_format(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- enum intel_output_format output = INTEL_OUTPUT_FORMAT_RGB;
-
- pipe_config->lspcon_downsampling = false;
-
- if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
- u32 tmp = I915_READ(PIPEMISC(crtc->pipe));
-
- if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) {
- bool ycbcr420_enabled = tmp & PIPEMISC_YUV420_ENABLE;
- bool blend = tmp & PIPEMISC_YUV420_MODE_FULL_BLEND;
-
- if (ycbcr420_enabled) {
- /* We support 4:2:0 in full blend mode only */
- if (!blend)
- output = INTEL_OUTPUT_FORMAT_INVALID;
- else if (!(IS_GEMINILAKE(dev_priv) ||
- INTEL_GEN(dev_priv) >= 10))
- output = INTEL_OUTPUT_FORMAT_INVALID;
- else
- output = INTEL_OUTPUT_FORMAT_YCBCR420;
- } else {
- /*
-* Currently there is no interface defined to
-* check user preference between RGB/YCBCR444
-* or YCBCR420. So the only possible case for
-* YCBCR444 usage is driving YCBCR420 output
-* with LSPCON, when pipe is configured for
-* YCBCR444 output and LSPCON takes care of
-* downsampling it.
-*/
- pipe_config->lspcon_downsampling = true;
- output = INTEL_OUTPUT_FORMAT_YCBCR444;
- }
- }
- }
+ u32 tmp;
+
+ tmp = I915_READ(PIPEMISC(crtc->pipe));
- pipe_config->output_format = output;
+ if (tmp & PIPEMISC_YUV420_ENABLE) {
+ /* We support 4:2:0 in full blend mode only */
+ WARN_ON((tmp & PIPEMISC_YUV420_MODE_FULL_BLEND) == 0);
+
+ return INTEL_OUTPUT_FORMAT_YCBCR420;
+ } else if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) {
+ return INTEL_OUTPUT_FORMAT_YCBCR444;
+ } else {
+ return INTEL_OUTPUT_FORMAT_RGB;
+ }
}
static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
@@ -10445,7 +10422,23 @@ static bool haswell_get_pipe_config(struct intel_crtc
*crtc,
}
intel_get_pipe_src_size(crtc, pipe_config);
- intel_get_crtc_ycbcr_config(crtc, pipe_config);
+
+ if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) {
+ pipe_config->output_format =
+ bdw_get_pipemisc_output_format(crtc);
+
+ /*
+* Currently there is no interface defined to
+* check user preference between RGB/YCBCR444
+* or YCBCR420. So the only possible case for
+* YCBCR444 usage is driving YCBCR420 output
+* with LSPCON, when pipe is configured for
+* YCBCR444 output and LSPCON takes care of
+* downsampling it.
+*/
+ pipe_config->lspcon_downsampling =
+ pipe_config->output_format ==
INTEL_OUTPUT_FORMAT_YCBCR444;
+ }
pipe_config->gamma_mode = I915_READ(GAMMA_MODE(crtc->pipe));
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 91bf714897e5..66f7f417231f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5803,8 +5803,8 @@ enum {
#define
[Intel-gfx] [PATCH 11/12] drm/i915: Set up ILK/SNB csc unit properly for YCbCr output
From: Ville Syrjälä
Prepare the pipe csc for YCbCr output on ilk/snb. The main difference
to IVB+ is the lack of explicit post offsets, and instead we must
configure the CSC info RGB->YUV mode (which takes care of offsetting
Cb/Cr properly) and enable the "black screen offset" bit to add the
required offset to Y.
And while at it throw some comments around the bit defines to
document which platforms have which bits.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_color.c | 25 +-
drivers/gpu/drm/i915/i915_reg.h| 10 -
2 files changed, 25 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 736c42720daf..a902f7809840 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1213,6 +1213,21 @@ static u32 ilk_gamma_mode(const struct intel_crtc_state
*crtc_state)
return GAMMA_MODE_MODE_10BIT;
}
+static u32 ilk_csc_mode(const struct intel_crtc_state *crtc_state)
+{
+ /*
+* CSC comes after the LUT in RGB->YCbCr mode.
+* RGB->YCbCr needs the limited range offsets added to
+* the output. RGB limited range output is handled by
+* the hw automagically elsewhere.
+*/
+ if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
+ return CSC_BLACK_SCREEN_OFFSET;
+
+ return CSC_MODE_YUV_TO_RGB |
+ CSC_POSITION_BEFORE_GAMMA;
+}
+
static int ilk_color_check(struct intel_crtc_state *crtc_state)
{
int ret;
@@ -1226,15 +1241,15 @@ static int ilk_color_check(struct intel_crtc_state
*crtc_state)
!crtc_state->c8_planes;
/*
-* We don't expose the ctm on ilk/snb currently,
-* nor do we enable YCbCr output. Also RGB limited
-* range output is handled by the hw automagically.
+* We don't expose the ctm on ilk/snb currently, also RGB
+* limited range output is handled by the hw automagically.
*/
- crtc_state->csc_enable = false;
+ crtc_state->csc_enable =
+ crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB;
crtc_state->gamma_mode = ilk_gamma_mode(crtc_state);
- crtc_state->csc_mode = 0;
+ crtc_state->csc_mode = ilk_csc_mode(crtc_state);
ret = intel_color_add_affected_planes(crtc_state);
if (ret)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 58471312b8b2..33d535ae0944 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10106,11 +10106,11 @@ enum skl_power_gate {
#define _PIPE_A_CSC_COEFF_BV 0x49024
#define _PIPE_A_CSC_MODE 0x49028
-#define ICL_CSC_ENABLE(1 << 31)
-#define ICL_OUTPUT_CSC_ENABLE (1 << 30)
-#define CSC_BLACK_SCREEN_OFFSET (1 << 2)
-#define CSC_POSITION_BEFORE_GAMMA (1 << 1)
-#define CSC_MODE_YUV_TO_RGB (1 << 0)
+#define ICL_CSC_ENABLE(1 << 31) /* icl+ */
+#define ICL_OUTPUT_CSC_ENABLE (1 << 30) /* icl+ */
+#define CSC_BLACK_SCREEN_OFFSET (1 << 2) /* ilk/snb */
+#define CSC_POSITION_BEFORE_GAMMA (1 << 1) /* pre-glk */
+#define CSC_MODE_YUV_TO_RGB (1 << 0) /* ilk/snb */
#define _PIPE_A_CSC_PREOFF_HI 0x49030
#define _PIPE_A_CSC_PREOFF_ME 0x49034
--
2.21.0
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[Intel-gfx] [PATCH 10/12] drm/i915: Document ILK+ pipe csc matrix better
From: Ville Syrjälä
Add comments to explain the ilk pipe csc operation a bit better.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_color.c | 26 +-
1 file changed, 21 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 23a84dd7989f..736c42720daf 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -42,6 +42,21 @@
#define LEGACY_LUT_LENGTH 256
+/*
+ * ILK+ csc matrix:
+ *
+ * |R/Cr| | c0 c1 c2 | ( |R/Cr| |preoff0| ) |postoff0|
+ * |G/Y | = | c3 c4 c5 | x ( |G/Y | + |preoff1| ) + |postoff1|
+ * |B/Cb| | c6 c7 c8 | ( |B/Cb| |preoff2| ) |postoff2|
+ *
+ * ILK/SNB don't have explicit post offsets, and instead
+ * CSC_MODE_YUV_TO_RGB and CSC_BLACK_SCREEN_OFFSET are used:
+ * CSC_MODE_YUV_TO_RGB=0 + CSC_BLACK_SCREEN_OFFSET=0 -> 1/2, 0, 1/2
+ * CSC_MODE_YUV_TO_RGB=0 + CSC_BLACK_SCREEN_OFFSET=1 -> 1/2, 1/16, 1/2
+ * CSC_MODE_YUV_TO_RGB=1 + CSC_BLACK_SCREEN_OFFSET=0 -> 0, 0, 0
+ * CSC_MODE_YUV_TO_RGB=1 + CSC_BLACK_SCREEN_OFFSET=1 -> 1/16, 1/16, 1/16
+ */
+
/*
* Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point
* format). This macro takes the coefficient we want transformed and the
@@ -59,37 +74,38 @@
#define ILK_CSC_POSTOFF_LIMITED_RANGE (16 * (1 << 12) / 255)
+/* Nop pre/post offsets */
static const u16 ilk_csc_off_zero[3] = {};
+/* Identity matrix */
static const u16 ilk_csc_coeff_identity[9] = {
ILK_CSC_COEFF_1_0, 0, 0,
0, ILK_CSC_COEFF_1_0, 0,
0, 0, ILK_CSC_COEFF_1_0,
};
+/* Limited range RGB post offsets */
static const u16 ilk_csc_postoff_limited_range[3] = {
ILK_CSC_POSTOFF_LIMITED_RANGE,
ILK_CSC_POSTOFF_LIMITED_RANGE,
ILK_CSC_POSTOFF_LIMITED_RANGE,
};
+/* Full range RGB -> limited range RGB matrix */
static const u16 ilk_csc_coeff_limited_range[9] = {
ILK_CSC_COEFF_LIMITED_RANGE, 0, 0,
0, ILK_CSC_COEFF_LIMITED_RANGE, 0,
0, 0, ILK_CSC_COEFF_LIMITED_RANGE,
};
-/*
- * These values are direct register values specified in the Bspec,
- * for RGB->YUV conversion matrix (colorspace BT709)
- */
+/* BT.709 full range RGB -> limited range YCbCr matrix */
static const u16 ilk_csc_coeff_rgb_to_ycbcr[9] = {
0x1e08, 0x9cc0, 0xb528,
0x2ba8, 0x09d8, 0x37e8,
0xbce8, 0x9ad8, 0x1e08,
};
-/* Post offset values for RGB->YCBCR conversion */
+/* Limited range YCbCr post offsets */
static const u16 ilk_csc_postoff_rgb_to_ycbcr[3] = {
0x0800, 0x0100, 0x0800,
};
--
2.21.0
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