[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Don't access non-existent PGTBL_ER register

[Patchwork]

== Series Details ==

Series: drm/i915: Don't access non-existent PGTBL_ER register
URL   : https://patchwork.freedesktop.org/series/86463/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_9704_full -> Patchwork_19546_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_19546_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_19546_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_19546_full:

### IGT changes ###

 Possible regressions 

  * igt@kms_frontbuffer_tracking@fbc-tiling-y:
- shard-iclb: [PASS][1] -> [FAIL][2] +1 similar issue
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9704/shard-iclb4/igt@kms_frontbuffer_track...@fbc-tiling-y.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19546/shard-iclb3/igt@kms_frontbuffer_track...@fbc-tiling-y.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@gem_ctx_persistence@many-contexts}:
- shard-iclb: [PASS][3] -> [INCOMPLETE][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9704/shard-iclb1/igt@gem_ctx_persiste...@many-contexts.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19546/shard-iclb7/igt@gem_ctx_persiste...@many-contexts.html

  * {igt@sysfs_clients@recycle}:
- shard-hsw:  [PASS][5] -> [FAIL][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9704/shard-hsw8/igt@sysfs_clie...@recycle.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19546/shard-hsw1/igt@sysfs_clie...@recycle.html

  
Known issues


  Here are the changes found in Patchwork_19546_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_persistence@close-replace-race:
- shard-glk:  [PASS][7] -> [TIMEOUT][8] ([i915#2918])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9704/shard-glk6/igt@gem_ctx_persiste...@close-replace-race.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19546/shard-glk6/igt@gem_ctx_persiste...@close-replace-race.html

  * igt@gem_exec_endless@dispatch@rcs0:
- shard-iclb: [PASS][9] -> [INCOMPLETE][10] ([i915#2502])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9704/shard-iclb4/igt@gem_exec_endless@dispa...@rcs0.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19546/shard-iclb3/igt@gem_exec_endless@dispa...@rcs0.html

  * igt@gem_exec_fair@basic-deadline:
- shard-apl:  NOTRUN -> [FAIL][11] ([i915#2846])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19546/shard-apl7/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-none@vecs0:
- shard-apl:  [PASS][12] -> [FAIL][13] ([i915#2842])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9704/shard-apl1/igt@gem_exec_fair@basic-n...@vecs0.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19546/shard-apl8/igt@gem_exec_fair@basic-n...@vecs0.html

  * igt@gem_exec_reloc@basic-many-active@vcs1:
- shard-iclb: NOTRUN -> [FAIL][14] ([i915#2389])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19546/shard-iclb2/igt@gem_exec_reloc@basic-many-act...@vcs1.html

  * igt@gem_exec_reloc@basic-wide-active@bcs0:
- shard-apl:  NOTRUN -> [FAIL][15] ([i915#2389]) +3 similar issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19546/shard-apl7/igt@gem_exec_reloc@basic-wide-act...@bcs0.html

  * igt@gem_exec_reloc@basic-wide-active@rcs0:
- shard-kbl:  NOTRUN -> [FAIL][16] ([i915#2389]) +4 similar issues
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19546/shard-kbl6/igt@gem_exec_reloc@basic-wide-act...@rcs0.html

  * igt@gem_exec_schedule@u-fairslice-all:
- shard-skl:  [PASS][17] -> [DMESG-WARN][18] ([i915#1610] / 
[i915#2803])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9704/shard-skl4/igt@gem_exec_sched...@u-fairslice-all.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19546/shard-skl8/igt@gem_exec_sched...@u-fairslice-all.html

  * igt@gem_exec_schedule@u-fairslice@rcs0:
- shard-apl:  [PASS][19] -> [DMESG-WARN][20] ([i915#1610])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9704/shard-apl2/igt@gem_exec_schedule@u-fairsl...@rcs0.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19546/shard-apl3/igt@gem_exec_schedule@u-fairsl...@rcs0.html
- shard-tglb: [PASS][21] -> [DMESG-WARN][22] ([i915#2803])
   [21]: 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Don't access non-existent PGTBL_ER register

[Patchwork]

== Series Details ==

Series: drm/i915: Don't access non-existent PGTBL_ER register
URL   : https://patchwork.freedesktop.org/series/86463/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9704 -> Patchwork_19546


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19546/index.html

Known issues


  Here are the changes found in Patchwork_19546 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@core_hotunplug@unbind-rebind:
- fi-kbl-7500u:   [PASS][1] -> [DMESG-WARN][2] ([i915#2605])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9704/fi-kbl-7500u/igt@core_hotunp...@unbind-rebind.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19546/fi-kbl-7500u/igt@core_hotunp...@unbind-rebind.html

  * igt@debugfs_test@read_all_entries:
- fi-tgl-y:   [PASS][3] -> [DMESG-WARN][4] ([i915#402]) +2 similar 
issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9704/fi-tgl-y/igt@debugfs_test@read_all_entries.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19546/fi-tgl-y/igt@debugfs_test@read_all_entries.html

  * igt@i915_pm_rpm@module-reload:
- fi-byt-j1900:   [PASS][5] -> [INCOMPLETE][6] ([i915#142] / 
[i915#2405])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9704/fi-byt-j1900/igt@i915_pm_...@module-reload.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19546/fi-byt-j1900/igt@i915_pm_...@module-reload.html

  * igt@runner@aborted:
- fi-byt-j1900:   NOTRUN -> [FAIL][7] ([i915#1814] / [i915#2505])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19546/fi-byt-j1900/igt@run...@aborted.html

  
 Possible fixes 

  * igt@i915_getparams_basic@basic-subslice-total:
- fi-tgl-y:   [DMESG-WARN][8] ([i915#402]) -> [PASS][9] +1 similar 
issue
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9704/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19546/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html

  
  [i915#142]: https://gitlab.freedesktop.org/drm/intel/issues/142
  [i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
  [i915#2405]: https://gitlab.freedesktop.org/drm/intel/issues/2405
  [i915#2505]: https://gitlab.freedesktop.org/drm/intel/issues/2505
  [i915#2605]: https://gitlab.freedesktop.org/drm/intel/issues/2605
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402


Participating hosts (44 -> 38)
--

  Missing(6): fi-jsl-1 fi-cml-u2 fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan 
fi-bdw-samus 


Build changes
-

  * Linux: CI_DRM_9704 -> Patchwork_19546

  CI-20190529: 20190529
  CI_DRM_9704: 3af64b0ad4ab498c2604002c8d0012ee49bc595b @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5979: fdc23507d022b68443121ec2c1a951af27c87240 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_19546: f4ea3a767967da99da57bb809113a5e16874a03c @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

f4ea3a767967 drm/i915: Don't access non-existent PGTBL_ER register

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19546/index.html
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[Intel-gfx] ✗ Fi.CI.IGT: failure for Final set of patches for ADLS enabling (rev3)

[Patchwork]

== Series Details ==

Series: Final set of patches for ADLS enabling (rev3)
URL   : https://patchwork.freedesktop.org/series/86322/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_9701_full -> Patchwork_19545_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_19545_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_19545_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_19545_full:

### IGT changes ###

 Warnings 

  * igt@kms_vblank@pipe-b-ts-continuation-suspend:
- shard-kbl:  [INCOMPLETE][1] ([i915#155]) -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9701/shard-kbl2/igt@kms_vbl...@pipe-b-ts-continuation-suspend.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19545/shard-kbl4/igt@kms_vbl...@pipe-b-ts-continuation-suspend.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@gem_ctx_persistence@many-contexts}:
- shard-tglb: [PASS][3] -> [FAIL][4] +1 similar issue
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9701/shard-tglb1/igt@gem_ctx_persiste...@many-contexts.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19545/shard-tglb5/igt@gem_ctx_persiste...@many-contexts.html

  * {igt@sysfs_clients@recycle}:
- shard-hsw:  [PASS][5] -> [FAIL][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9701/shard-hsw6/igt@sysfs_clie...@recycle.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19545/shard-hsw7/igt@sysfs_clie...@recycle.html

  

### Piglit changes ###

 Possible regressions 

  * spec@glsl-4.30@execution@built-in-functions@cs-op-eq-mat2x3-mat2x3 (NEW):
- pig-glk-j5005:  NOTRUN -> [INCOMPLETE][7] +3 similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19545/pig-glk-j5005/spec@glsl-4.30@execution@built-in-functi...@cs-op-eq-mat2x3-mat2x3.html

  
New tests
-

  New tests have been introduced between CI_DRM_9701_full and 
Patchwork_19545_full:

### New Piglit tests (4) ###

  * spec@glsl-4.30@execution@built-in-functions@cs-min-uvec2-uvec2:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s

  * spec@glsl-4.30@execution@built-in-functions@cs-op-assign-bitor-ivec3-ivec3:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s

  * spec@glsl-4.30@execution@built-in-functions@cs-op-eq-mat2x3-mat2x3:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s

  * spec@glsl-4.30@execution@built-in-functions@cs-sign-ivec3:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s

  

Known issues


  Here are the changes found in Patchwork_19545_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@drm_import_export@prime:
- shard-glk:  [PASS][8] -> [INCOMPLETE][9] ([i915#2055] / 
[i915#2944])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9701/shard-glk4/igt@drm_import_exp...@prime.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19545/shard-glk7/igt@drm_import_exp...@prime.html

  * igt@gem_ctx_persistence@legacy-engines-queued:
- shard-hsw:  NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#1099])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19545/shard-hsw1/igt@gem_ctx_persiste...@legacy-engines-queued.html

  * igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [PASS][11] -> [FAIL][12] ([i915#2842]) +2 similar 
issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9701/shard-tglb7/igt@gem_exec_fair@basic-f...@rcs0.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19545/shard-tglb8/igt@gem_exec_fair@basic-f...@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-glk:  [PASS][13] -> [FAIL][14] ([i915#2842])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9701/shard-glk9/igt@gem_exec_fair@basic-pace-s...@rcs0.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19545/shard-glk1/igt@gem_exec_fair@basic-pace-s...@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs0:
- shard-kbl:  [PASS][15] -> [SKIP][16] ([fdo#109271])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9701/shard-kbl7/igt@gem_exec_fair@basic-p...@vcs0.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19545/shard-kbl7/igt@gem_exec_fair@basic-p...@vcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
- shard-kbl:  [PASS][17] -> [FAIL][18] ([i915#2842])
   [17]: 

Re: [Intel-gfx] [PATCH] drm/i915: Don't access non-existent PGTBL_ER register

[Chris Wilson]

Quoting Matt Roper (2021-01-30 00:16:20)
> PGTBL_ER (0x2024) isn't documented in the bspec of any recent (SNB+)
> platform; it seems this register was removed ages ago and we probably
> shouldn't still be trying to clear it at init or read it during error
> state dump.

We do support decoding of PGTBL_ERR from the error state on gen2-gen4,
so that suggests we did have the definition at some point.

I would keep it in the error state and just read it on gen<6.

One day we will get per-platform lists of registers to snapshot for
errors.
-Chris
___
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[Intel-gfx] [PATCH] drm/i915: Don't access non-existent PGTBL_ER register

[Matt Roper]

PGTBL_ER (0x2024) isn't documented in the bspec of any recent (SNB+)
platform; it seems this register was removed ages ago and we probably
shouldn't still be trying to clear it at init or read it during error
state dump.

Since I don't have easy access to a gen4 or gen5 era bspec to confirm
exactly when it went away, I've left the initial clearing of the
register on those platforms to be safe, but removed it for everything
newer.  The error state's readout and printing of the register is
removed for all platforms, as is the GVT trap setup on BXT.

Bspec: 94, 34387
Signed-off-by: Matt Roper 
---
 drivers/gpu/drm/i915/gt/intel_gt.c| 2 +-
 drivers/gpu/drm/i915/gvt/handlers.c   | 1 -
 drivers/gpu/drm/i915/i915_gpu_error.c | 2 --
 drivers/gpu/drm/i915/i915_gpu_error.h | 1 -
 4 files changed, 1 insertion(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c 
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 35ff68ada4f1..57456a1af5e0 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -203,7 +203,7 @@ intel_gt_clear_error_registers(struct intel_gt *gt,
struct intel_uncore *uncore = gt->uncore;
u32 eir;
 
-   if (!IS_GEN(i915, 2))
+   if (IS_GEN_RANGE(i915, 3, 5))
clear_register(uncore, PGTBL_ER);
 
if (INTEL_GEN(i915) < 4)
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c 
b/drivers/gpu/drm/i915/gvt/handlers.c
index 6eeaeecb7f85..8db71d3b36ba 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -3189,7 +3189,6 @@ static int init_bxt_mmio_info(struct intel_gvt *gvt)
MMIO_D(ERROR_GEN6, D_BXT);
MMIO_D(DONE_REG, D_BXT);
MMIO_D(EIR, D_BXT);
-   MMIO_D(PGTBL_ER, D_BXT);
MMIO_D(_MMIO(0x4194), D_BXT);
MMIO_D(_MMIO(0x4294), D_BXT);
MMIO_D(_MMIO(0x4494), D_BXT);
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 0cb3686ed91d..c9eb076ad1c2 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -697,7 +697,6 @@ static void err_print_gt(struct drm_i915_error_state_buf *m,
err_printf(m, "IER: 0x%08x\n", gt->ier);
for (i = 0; i < gt->ngtier; i++)
err_printf(m, "GTIER[%d]: 0x%08x\n", i, gt->gtier[i]);
-   err_printf(m, "PGTBL_ER: 0x%08x\n", gt->pgtbl_er);
err_printf(m, "FORCEWAKE: 0x%08x\n", gt->forcewake);
err_printf(m, "DERRMR: 0x%08x\n", gt->derrmr);
 
@@ -1630,7 +1629,6 @@ static void gt_record_regs(struct intel_gt_coredump *gt)
gt->ier = intel_uncore_read(uncore, GEN2_IER);
}
gt->eir = intel_uncore_read(uncore, EIR);
-   gt->pgtbl_er = intel_uncore_read(uncore, PGTBL_ER);
 }
 
 static void gt_record_info(struct intel_gt_coredump *gt)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.h 
b/drivers/gpu/drm/i915/i915_gpu_error.h
index 1764fd254df3..05c601e9c97f 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.h
+++ b/drivers/gpu/drm/i915/i915_gpu_error.h
@@ -124,7 +124,6 @@ struct intel_gt_coredump {
 
/* Generic register state */
u32 eir;
-   u32 pgtbl_er;
u32 ier;
u32 gtier[6], ngtier;
u32 derrmr;
-- 
2.25.4

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[Intel-gfx] [PULL] drm-intel-next

[Rodrigo Vivi]

Hi Dave and Daniel,

On my last pull request I incorrectly stated that
Async flips were enabled for all ilk+ platforms, while it
was only on SKL. I'm sorry about that.

I hope there's still time to include a few changes including
the actual patches that make this statement true for 5.12.

Along with other fixes and clean-up as described below:

Here goes drm-intel-next-2021-01-29:
- WARN if plane src coords are too big (Ville)
- Prevent double YUV range correction on HDR planes (Andres)
- DP MST related Fixes (Sean, Imre)
- More clean-up around DRAM detection code (Jose)
- Actually async flips enable for all ilk+ platforms (Ville)

Sorry and Thanks,
Rodrigo.

The following changes since commit 784953a46589276b38d7e6dcb5ebf7e29db72ff1:

  drm/i915/display/vrr: Skip the VRR HW state readout on DSI transcoder 
(2021-01-26 16:34:53 -0800)

are available in the Git repository at:

  git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-next-2021-01-29

for you to fetch changes up to 3b7bbb3619d2cc92f04ba10ad27d3b616aabf175:

  drm/i915/dp: Prevent setting the LTTPR LT mode if no LTTPRs are detected 
(2021-01-29 22:00:07 +0200)


- WARN if plane src coords are too big (Ville)
- Prevent double YUV range correction on HDR planes (Andres)
- DP MST related Fixes (Sean, Imre)
- More clean-up around DRAM detection code (Jose)
- Actually async flips enable for all ilk+ platforms (Ville)


Andres Calderon Jaramillo (1):
  drm/i915/display: Prevent double YUV range correction on HDR planes

Imre Deak (3):
  drm/dp/mst: Export drm_dp_get_vc_payload_bw()
  drm/i915: Fix the MST PBN divider calculation
  drm/i915/dp: Prevent setting the LTTPR LT mode if no LTTPRs are detected

José Roberto de Souza (3):
  drm/i915: Nuke not needed members of dram_info
  drm/i915/gen11+: Only load DRAM information from pcode
  drm/i915: Rename is_16gb_dimm to wm_lv_0_adjust_needed

Sean Paul (1):
  drm/i915/hdcp: Disable the QSES check for HDCP 1.4 over MST

Ville Syrjälä (6):
  drm/i915: WARN if plane src coords are too big
  drm/i915: Limit plane stride to below TILEOFF.x limit
  drm/i915: Implement async flips for bdw
  drm/i915: Implement async flip for ivb/hsw
  drm/i915: Implement async flip for ilk/snb
  drm/i915: Implement async flips for vlv/chv

 drivers/gpu/drm/drm_dp_mst_topology.c  |  24 ++-
 drivers/gpu/drm/i915/display/i9xx_plane.c  | 213 -
 drivers/gpu/drm/i915/display/i9xx_plane.h  |   2 +-
 drivers/gpu/drm/i915/display/intel_bw.c|  80 +---
 drivers/gpu/drm/i915/display/intel_display.c   |  16 +-
 drivers/gpu/drm/i915/display/intel_dp_hdcp.c   |  12 +-
 .../gpu/drm/i915/display/intel_dp_link_training.c  |  36 ++--
 drivers/gpu/drm/i915/display/intel_dp_mst.c|   4 +-
 drivers/gpu/drm/i915/display/intel_sprite.c|  98 --
 drivers/gpu/drm/i915/i915_drv.c|   9 +-
 drivers/gpu/drm/i915/i915_drv.h|   6 +-
 drivers/gpu/drm/i915/i915_irq.c|  39 ++--
 drivers/gpu/drm/i915/i915_reg.h|   3 +
 drivers/gpu/drm/i915/intel_dram.c  | 136 +
 drivers/gpu/drm/i915/intel_pm.c|   2 +-
 include/drm/drm_dp_mst_helper.h|   1 +
 16 files changed, 434 insertions(+), 247 deletions(-)
___
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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Add missing -EDEADLK path in execbuffer ggtt pinning.

[Patchwork]

== Series Details ==

Series: drm/i915: Add missing -EDEADLK path in execbuffer ggtt pinning.
URL   : https://patchwork.freedesktop.org/series/86452/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_9700_full -> Patchwork_19543_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_19543_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_19543_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_19543_full:

### IGT changes ###

 Possible regressions 

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt:
- shard-glk:  [PASS][1] -> [DMESG-WARN][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9700/shard-glk3/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-msflip-blt.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19543/shard-glk4/igt@kms_frontbuffer_track...@fbc-1p-primscrn-shrfb-msflip-blt.html

  
Known issues


  Here are the changes found in Patchwork_19543_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_persistence@close-replace-race:
- shard-glk:  [PASS][3] -> [TIMEOUT][4] ([i915#2918])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9700/shard-glk9/igt@gem_ctx_persiste...@close-replace-race.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19543/shard-glk9/igt@gem_ctx_persiste...@close-replace-race.html

  * igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-glk:  NOTRUN -> [FAIL][5] ([i915#2842])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19543/shard-glk2/igt@gem_exec_fair@basic-none-r...@rcs0.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
- shard-apl:  [PASS][6] -> [SKIP][7] ([fdo#109271])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9700/shard-apl1/igt@gem_exec_fair@basic-none-sh...@rcs0.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19543/shard-apl8/igt@gem_exec_fair@basic-none-sh...@rcs0.html

  * igt@gem_exec_fair@basic-pace@bcs0:
- shard-tglb: [PASS][8] -> [FAIL][9] ([i915#2842])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9700/shard-tglb3/igt@gem_exec_fair@basic-p...@bcs0.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19543/shard-tglb1/igt@gem_exec_fair@basic-p...@bcs0.html
- shard-iclb: [PASS][10] -> [FAIL][11] ([i915#2842])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9700/shard-iclb7/igt@gem_exec_fair@basic-p...@bcs0.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19543/shard-iclb2/igt@gem_exec_fair@basic-p...@bcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][12] ([i915#2842])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19543/shard-iclb2/igt@gem_exec_fair@basic-p...@vcs1.html

  * igt@gem_exec_fair@basic-pace@vecs0:
- shard-kbl:  [PASS][13] -> [FAIL][14] ([i915#2842]) +1 similar 
issue
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9700/shard-kbl6/igt@gem_exec_fair@basic-p...@vecs0.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19543/shard-kbl4/igt@gem_exec_fair@basic-p...@vecs0.html

  * igt@gem_exec_reloc@basic-wide-active@vcs1:
- shard-iclb: NOTRUN -> [FAIL][15] ([i915#2389])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19543/shard-iclb4/igt@gem_exec_reloc@basic-wide-act...@vcs1.html

  * igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][16] -> [SKIP][17] ([i915#2190])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9700/shard-tglb5/igt@gem_huc_c...@huc-copy.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19543/shard-tglb6/igt@gem_huc_c...@huc-copy.html

  * igt@i915_pm_dc@dc6-psr:
- shard-iclb: [PASS][18] -> [FAIL][19] ([i915#454])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9700/shard-iclb5/igt@i915_pm...@dc6-psr.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19543/shard-iclb6/igt@i915_pm...@dc6-psr.html

  * igt@i915_pm_rpm@system-suspend-execbuf:
- shard-skl:  [PASS][20] -> [INCOMPLETE][21] ([i915#151])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9700/shard-skl3/igt@i915_pm_...@system-suspend-execbuf.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19543/shard-skl5/igt@i915_pm_...@system-suspend-execbuf.html

  * igt@kms_async_flips@alternate-sync-async-flip:
- shard-skl:  [PASS][22] -> [FAIL][23] ([i915#2521])
   [22]: 

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/dp: Prevent setting the LTTPR LT mode if no LTTPRs are detected

[Vudum, Lakshminarayana]

Re-reported.

-Original Message-
From: Imre Deak  
Sent: Friday, January 29, 2021 12:18 PM
To: intel-gfx@lists.freedesktop.org; Almahallawy, Khaled 

Cc: Vudum, Lakshminarayana 
Subject: Re: ✗ Fi.CI.IGT: failure for drm/i915/dp: Prevent setting the LTTPR LT 
mode if no LTTPRs are detected

On Tue, Jan 19, 2021 at 01:46:54AM +, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915/dp: Prevent setting the LTTPR LT mode if no LTTPRs are 
> detected
> URL   : https://patchwork.freedesktop.org/series/86007/
> State : failure

Thanks for the review pushed to -din.

The failures are unrelated see below.

> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_9636_full -> Patchwork_19399_full 
> 
> 
> Summary
> ---
> 
>   **FAILURE**
> 
>   Serious unknown changes coming with Patchwork_19399_full absolutely need to 
> be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the changes
>   introduced in Patchwork_19399_full, please notify your bug team to allow 
> them
>   to document this new failure mode, which will reduce false positives in CI.
> 
>   
> 
> Possible new issues
> ---
> 
>   Here are the unknown changes that may have been introduced in 
> Patchwork_19399_full:
> 
> ### IGT changes ###
> 
>  Possible regressions 
> 
>   * igt@gem_exec_reloc@basic-many-active@vcs1:
> - shard-iclb: NOTRUN -> [FAIL][1]
>[1]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19399/shard-iclb2/i
> gt@gem_exec_reloc@basic-many-act...@vcs1.html

This looks like
https://gitlab.freedesktop.org/drm/intel/-/issues/2389

> 
>   * igt@i915_pm_rps@reset:
> - shard-snb:  [PASS][2] -> [FAIL][3]
>[2]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9636/shard-snb4/igt@i915_pm_...@reset.html
>[3]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19399/shard-snb4/ig
> t@i915_pm_...@reset.html

There is no DP connected to this machine, so the change makes no difference 
here.

> 
>   
> Known issues
> 
> 
>   Here are the changes found in Patchwork_19399_full that come from known 
> issues:
> 
> ### IGT changes ###
> 
>  Issues hit 
> 
>   * igt@gem_ctx_persistence@engines-mixed:
> - shard-hsw:  NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#1099]) +2 
> similar issues
>[4]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19399/shard-hsw2/ig
> t@gem_ctx_persiste...@engines-mixed.html
> 
>   * igt@gem_exec_capture@pi@rcs0:
> - shard-skl:  [PASS][5] -> [INCOMPLETE][6] ([i915#2369] / 
> [i915#2502])
>[5]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9636/shard-skl2/igt@gem_exec_capture@p...@rcs0.html
>[6]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19399/shard-skl2/ig
> t@gem_exec_capture@p...@rcs0.html
> 
>   * igt@gem_exec_fair@basic-none-solo@rcs0:
> - shard-kbl:  [PASS][7] -> [FAIL][8] ([i915#2842])
>[7]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9636/shard-kbl6/igt@gem_exec_fair@basic-none-s...@rcs0.html
>[8]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19399/shard-kbl7/ig
> t@gem_exec_fair@basic-none-s...@rcs0.html
> 
>   * igt@gem_exec_reloc@basic-wide-active@vcs1:
> - shard-iclb: NOTRUN -> [FAIL][9] ([i915#2389])
>[9]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19399/shard-iclb4/i
> gt@gem_exec_reloc@basic-wide-act...@vcs1.html
> 
>   * igt@gem_render_copy@y-tiled-to-vebox-linear:
> - shard-hsw:  NOTRUN -> [SKIP][10] ([fdo#109271]) +158 similar 
> issues
>[10]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19399/shard-hsw2/ig
> t@gem_render_c...@y-tiled-to-vebox-linear.html
> 
>   * igt@gem_workarounds@suspend-resume-fd:
> - shard-kbl:  [PASS][11] -> [DMESG-WARN][12] ([i915#180])
>[11]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9636/shard-kbl3/igt@gem_workarou...@suspend-resume-fd.html
>[12]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19399/shard-kbl3/ig
> t@gem_workarou...@suspend-resume-fd.html
> 
>   * igt@kms_async_flips@alternate-sync-async-flip:
> - shard-skl:  [PASS][13] -> [FAIL][14] ([i915#2521])
>[13]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9636/shard-skl2/igt@kms_async_fl...@alternate-sync-async-flip.html
>[14]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19399/shard-skl2/ig
> t@kms_async_fl...@alternate-sync-async-flip.html
> 
>   * igt@kms_chamelium@hdmi-aspect-ratio:
> - shard-hsw:  NOTRUN -> [SKIP][15] ([fdo#109271] / [fdo#111827]) 
> +11 similar issues
>[15]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19399/shard-hsw2/ig
> t@kms_chamel...@hdmi-aspect-ratio.html
> 
>   * igt@kms_color_chamelium@pipe-a-ctm-green-to-red:
> - shard-skl:  NOTRUN -> [SKIP][16] ([fdo#109271] / [fdo#111827]) 
> +2 similar issues
>[16]: 
> 

Re: [Intel-gfx] [PATCH] drm/i915: Remove unreachable code

[Chris Wilson]

Quoting Vinicius Tinti (2021-01-29 18:15:19)
> By enabling -Wunreachable-code-aggressive on Clang the following code
> paths are unreachable.

That code exists as commentary and, especially for sdvo, library
functions that we may need in future.

The ivb-gt1 case => as we now set the gt level for ivb, should we not
enable the optimisation for ivb unaffected by the w/a? Just no one has
taken the time to see if it causes a regression.

For error state, the question remains whether we should revert to
uncompressed data if the compressed stream is larger than the original.
-Chris
___
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dp: Prevent setting the LTTPR LT mode if no LTTPRs are detected

[Patchwork]

== Series Details ==

Series: drm/i915/dp: Prevent setting the LTTPR LT mode if no LTTPRs are detected
URL   : https://patchwork.freedesktop.org/series/86007/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9636_full -> Patchwork_19399_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Known issues


  Here are the changes found in Patchwork_19399_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_persistence@engines-mixed:
- shard-hsw:  NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#1099]) +2 
similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19399/shard-hsw2/igt@gem_ctx_persiste...@engines-mixed.html

  * igt@gem_exec_capture@pi@rcs0:
- shard-skl:  [PASS][2] -> [INCOMPLETE][3] ([i915#2369] / 
[i915#2502])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9636/shard-skl2/igt@gem_exec_capture@p...@rcs0.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19399/shard-skl2/igt@gem_exec_capture@p...@rcs0.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-kbl:  [PASS][4] -> [FAIL][5] ([i915#2842]) +1 similar issue
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9636/shard-kbl6/igt@gem_exec_fair@basic-none-s...@rcs0.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19399/shard-kbl7/igt@gem_exec_fair@basic-none-s...@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs0:
- shard-glk:  [PASS][6] -> [FAIL][7] ([i915#2842])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9636/shard-glk9/igt@gem_exec_fair@basic-p...@vcs0.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19399/shard-glk2/igt@gem_exec_fair@basic-p...@vcs0.html

  * igt@gem_exec_fair@basic-pace@vecs0:
- shard-kbl:  [PASS][8] -> [SKIP][9] ([fdo#109271])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9636/shard-kbl4/igt@gem_exec_fair@basic-p...@vecs0.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19399/shard-kbl6/igt@gem_exec_fair@basic-p...@vecs0.html
- shard-tglb: [PASS][10] -> [FAIL][11] ([i915#2842]) +1 similar 
issue
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9636/shard-tglb2/igt@gem_exec_fair@basic-p...@vecs0.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19399/shard-tglb8/igt@gem_exec_fair@basic-p...@vecs0.html
- shard-iclb: [PASS][12] -> [FAIL][13] ([i915#2842])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9636/shard-iclb5/igt@gem_exec_fair@basic-p...@vecs0.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19399/shard-iclb7/igt@gem_exec_fair@basic-p...@vecs0.html

  * igt@gem_exec_reloc@basic-wide-active@vcs1:
- shard-iclb: NOTRUN -> [FAIL][14] ([i915#2389]) +1 similar issue
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19399/shard-iclb4/igt@gem_exec_reloc@basic-wide-act...@vcs1.html

  * igt@gem_render_copy@y-tiled-to-vebox-linear:
- shard-hsw:  NOTRUN -> [SKIP][15] ([fdo#109271]) +165 similar 
issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19399/shard-hsw2/igt@gem_render_c...@y-tiled-to-vebox-linear.html

  * igt@gem_workarounds@suspend-resume-fd:
- shard-kbl:  [PASS][16] -> [DMESG-WARN][17] ([i915#180]) +1 
similar issue
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9636/shard-kbl3/igt@gem_workarou...@suspend-resume-fd.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19399/shard-kbl3/igt@gem_workarou...@suspend-resume-fd.html

  * igt@i915_pm_rps@reset:
- shard-snb:  [PASS][18] -> [FAIL][19] ([i915#39])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9636/shard-snb4/igt@i915_pm_...@reset.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19399/shard-snb4/igt@i915_pm_...@reset.html

  * igt@kms_async_flips@alternate-sync-async-flip:
- shard-skl:  [PASS][20] -> [FAIL][21] ([i915#2521])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9636/shard-skl2/igt@kms_async_fl...@alternate-sync-async-flip.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19399/shard-skl2/igt@kms_async_fl...@alternate-sync-async-flip.html

  * igt@kms_chamelium@hdmi-aspect-ratio:
- shard-hsw:  NOTRUN -> [SKIP][22] ([fdo#109271] / [fdo#111827]) 
+11 similar issues
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19399/shard-hsw2/igt@kms_chamel...@hdmi-aspect-ratio.html

  * igt@kms_color_chamelium@pipe-a-ctm-green-to-red:
- shard-skl:  NOTRUN -> [SKIP][23] ([fdo#109271] / [fdo#111827]) +2 
similar issues
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19399/shard-skl8/igt@kms_color_chamel...@pipe-a-ctm-green-to-red.html

  * igt@kms_cursor_crc@pipe-b-cursor-64x64-sliding:
- shard-skl:  NOTRUN -> [FAIL][24] ([i915#54])
   [24]: 

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/dp: Prevent setting the LTTPR LT mode if no LTTPRs are detected

[Imre Deak]

On Tue, Jan 19, 2021 at 01:46:54AM +, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915/dp: Prevent setting the LTTPR LT mode if no LTTPRs are 
> detected
> URL   : https://patchwork.freedesktop.org/series/86007/
> State : failure

Thanks for the review pushed to -din.

The failures are unrelated see below.

> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_9636_full -> Patchwork_19399_full
> 
> 
> Summary
> ---
> 
>   **FAILURE**
> 
>   Serious unknown changes coming with Patchwork_19399_full absolutely need to 
> be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the changes
>   introduced in Patchwork_19399_full, please notify your bug team to allow 
> them
>   to document this new failure mode, which will reduce false positives in CI.
> 
>   
> 
> Possible new issues
> ---
> 
>   Here are the unknown changes that may have been introduced in 
> Patchwork_19399_full:
> 
> ### IGT changes ###
> 
>  Possible regressions 
> 
>   * igt@gem_exec_reloc@basic-many-active@vcs1:
> - shard-iclb: NOTRUN -> [FAIL][1]
>[1]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19399/shard-iclb2/igt@gem_exec_reloc@basic-many-act...@vcs1.html

This looks like
https://gitlab.freedesktop.org/drm/intel/-/issues/2389

> 
>   * igt@i915_pm_rps@reset:
> - shard-snb:  [PASS][2] -> [FAIL][3]
>[2]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9636/shard-snb4/igt@i915_pm_...@reset.html
>[3]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19399/shard-snb4/igt@i915_pm_...@reset.html

There is no DP connected to this machine, so the change makes no
difference here.

> 
>   
> Known issues
> 
> 
>   Here are the changes found in Patchwork_19399_full that come from known 
> issues:
> 
> ### IGT changes ###
> 
>  Issues hit 
> 
>   * igt@gem_ctx_persistence@engines-mixed:
> - shard-hsw:  NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#1099]) +2 
> similar issues
>[4]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19399/shard-hsw2/igt@gem_ctx_persiste...@engines-mixed.html
> 
>   * igt@gem_exec_capture@pi@rcs0:
> - shard-skl:  [PASS][5] -> [INCOMPLETE][6] ([i915#2369] / 
> [i915#2502])
>[5]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9636/shard-skl2/igt@gem_exec_capture@p...@rcs0.html
>[6]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19399/shard-skl2/igt@gem_exec_capture@p...@rcs0.html
> 
>   * igt@gem_exec_fair@basic-none-solo@rcs0:
> - shard-kbl:  [PASS][7] -> [FAIL][8] ([i915#2842])
>[7]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9636/shard-kbl6/igt@gem_exec_fair@basic-none-s...@rcs0.html
>[8]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19399/shard-kbl7/igt@gem_exec_fair@basic-none-s...@rcs0.html
> 
>   * igt@gem_exec_reloc@basic-wide-active@vcs1:
> - shard-iclb: NOTRUN -> [FAIL][9] ([i915#2389])
>[9]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19399/shard-iclb4/igt@gem_exec_reloc@basic-wide-act...@vcs1.html
> 
>   * igt@gem_render_copy@y-tiled-to-vebox-linear:
> - shard-hsw:  NOTRUN -> [SKIP][10] ([fdo#109271]) +158 similar 
> issues
>[10]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19399/shard-hsw2/igt@gem_render_c...@y-tiled-to-vebox-linear.html
> 
>   * igt@gem_workarounds@suspend-resume-fd:
> - shard-kbl:  [PASS][11] -> [DMESG-WARN][12] ([i915#180])
>[11]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9636/shard-kbl3/igt@gem_workarou...@suspend-resume-fd.html
>[12]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19399/shard-kbl3/igt@gem_workarou...@suspend-resume-fd.html
> 
>   * igt@kms_async_flips@alternate-sync-async-flip:
> - shard-skl:  [PASS][13] -> [FAIL][14] ([i915#2521])
>[13]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9636/shard-skl2/igt@kms_async_fl...@alternate-sync-async-flip.html
>[14]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19399/shard-skl2/igt@kms_async_fl...@alternate-sync-async-flip.html
> 
>   * igt@kms_chamelium@hdmi-aspect-ratio:
> - shard-hsw:  NOTRUN -> [SKIP][15] ([fdo#109271] / [fdo#111827]) 
> +11 similar issues
>[15]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19399/shard-hsw2/igt@kms_chamel...@hdmi-aspect-ratio.html
> 
>   * igt@kms_color_chamelium@pipe-a-ctm-green-to-red:
> - shard-skl:  NOTRUN -> [SKIP][16] ([fdo#109271] / [fdo#111827]) 
> +2 similar issues
>[16]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19399/shard-skl8/igt@kms_color_chamel...@pipe-a-ctm-green-to-red.html
> 
>   * igt@kms_cursor_crc@pipe-b-cursor-64x64-sliding:
> - shard-skl:  NOTRUN -> [FAIL][17] ([i915#54])
>[17]: 
> 

[Intel-gfx] ✓ Fi.CI.BAT: success for Final set of patches for ADLS enabling (rev3)

[Patchwork]

== Series Details ==

Series: Final set of patches for ADLS enabling (rev3)
URL   : https://patchwork.freedesktop.org/series/86322/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9701 -> Patchwork_19545


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19545/index.html

Known issues


  Here are the changes found in Patchwork_19545 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-byt-j1900:   NOTRUN -> [SKIP][1] ([fdo#109271]) +27 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19545/fi-byt-j1900/igt@gem_huc_c...@huc-copy.html

  * igt@gem_ringfill@basic-all:
- fi-tgl-y:   [PASS][2] -> [DMESG-WARN][3] ([i915#402])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9701/fi-tgl-y/igt@gem_ringf...@basic-all.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19545/fi-tgl-y/igt@gem_ringf...@basic-all.html

  * igt@kms_chamelium@hdmi-crc-fast:
- fi-byt-j1900:   NOTRUN -> [SKIP][4] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19545/fi-byt-j1900/igt@kms_chamel...@hdmi-crc-fast.html

  
 Possible fixes 

  * igt@gem_ctx_create@basic-files:
- fi-tgl-y:   [DMESG-WARN][5] ([i915#402]) -> [PASS][6] +1 similar 
issue
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9701/fi-tgl-y/igt@gem_ctx_cre...@basic-files.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19545/fi-tgl-y/igt@gem_ctx_cre...@basic-files.html

  * igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u:   [FAIL][7] ([i915#1161] / [i915#262]) -> [PASS][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9701/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19545/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html

  * igt@kms_chamelium@hdmi-crc-fast:
- fi-kbl-7500u:   [DMESG-WARN][9] ([i915#2868]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9701/fi-kbl-7500u/igt@kms_chamel...@hdmi-crc-fast.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19545/fi-kbl-7500u/igt@kms_chamel...@hdmi-crc-fast.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1161]: https://gitlab.freedesktop.org/drm/intel/issues/1161
  [i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262
  [i915#2868]: https://gitlab.freedesktop.org/drm/intel/issues/2868
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402


Participating hosts (43 -> 39)
--

  Additional (1): fi-byt-j1900 
  Missing(5): fi-jsl-1 fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-bdw-samus 


Build changes
-

  * Linux: CI_DRM_9701 -> Patchwork_19545

  CI-20190529: 20190529
  CI_DRM_9701: 1974b10a6bcd66b58fd5ed6990c6dc2495047d31 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5979: fdc23507d022b68443121ec2c1a951af27c87240 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_19545: 3900b84d73acf2a16d1b95f59ea6ccf02f71d216 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

3900b84d73ac drm/i915/adl_s: Add GT and CTX WAs for ADL-S
277d527984de drm/i915/adl_s: Add display WAs for ADL-S
fd086fb350b9 drm/i915/adl_s: Update memory bandwidth parameters
9825e76754aa drm/i915/adl_s: Load DMC
598223745a32 drm/i915/display: Add HAS_D12_PLANE_MINIMIZATION
d1a01bcc7045 drm/i915/adl_s: Re-use TGL GuC/HuC firmware
ad35bfcaf2e4 drm/i915/adl_s: Add power wells
20fe6c96d8ea drm/i915/adl_s: Update PHY_MISC programming

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19545/index.html
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Final set of patches for ADLS enabling (rev3)

[Patchwork]

== Series Details ==

Series: Final set of patches for ADLS enabling (rev3)
URL   : https://patchwork.freedesktop.org/series/86322/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1327:5: warning: context imbalance in 
'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gvt/mmio.c:295:23: warning: memcpy with byte count of 
279040
+drivers/gpu/drm/i915/i915_perf.c:1450:15: warning: memset with byte count of 
16777216
+drivers/gpu/drm/i915/i915_perf.c:1504:15: warning: memset with byte count of 
16777216
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' 
- different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' 
- different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' 
- different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - 
different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' 
- different lock contexts for basic block

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Final set of patches for ADLS enabling (rev3)

[Patchwork]

== Series Details ==

Series: Final set of patches for ADLS enabling (rev3)
URL   : https://patchwork.freedesktop.org/series/86322/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
20fe6c96d8ea drm/i915/adl_s: Update PHY_MISC programming
ad35bfcaf2e4 drm/i915/adl_s: Add power wells
d1a01bcc7045 drm/i915/adl_s: Re-use TGL GuC/HuC firmware
598223745a32 drm/i915/display: Add HAS_D12_PLANE_MINIMIZATION
-:45: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible 
side-effects?
#45: FILE: drivers/gpu/drm/i915/i915_drv.h:1786:
+#define HAS_D12_PLANE_MINIMIZATION(dev_priv) (IS_ROCKETLAKE(dev_priv) || \
+ IS_ALDERLAKE_S(dev_priv))

total: 0 errors, 0 warnings, 1 checks, 33 lines checked
9825e76754aa drm/i915/adl_s: Load DMC
fd086fb350b9 drm/i915/adl_s: Update memory bandwidth parameters
-:48: CHECK:LINE_SPACING: Please don't use multiple blank lines
#48: FILE: drivers/gpu/drm/i915/display/intel_bw.c:260:
 
+

total: 0 errors, 0 warnings, 1 checks, 23 lines checked
277d527984de drm/i915/adl_s: Add display WAs for ADL-S
3900b84d73ac drm/i915/adl_s: Add GT and CTX WAs for ADL-S


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Re: [Intel-gfx] [PATCH 7/8] drm/i915/adl_s: Add display WAs for ADL-S

[Souza, Jose]

On Fri, 2021-01-29 at 10:29 -0800, Aditya Swarup wrote:
> - Extend permanent driver WA Wa_1409767108, Wa_14010685332
>   and Wa_14011294188 to adl-s.
> - Extend permanent driver WA Wa_1606054188 to adl-s.
> - Add Wa_14011765242 for adl-s A0 stepping.

Reviewed-by: José Roberto de Souza 

> 
> Cc: Jani Nikula 
> Cc: Ville Syrjälä 
> Cc: Imre Deak 
> Cc: Matt Roper 
> Cc: Lucas De Marchi 
> Signed-off-by: Aditya Swarup 
> ---
>  drivers/gpu/drm/i915/display/intel_display_power.c | 7 ---
>  drivers/gpu/drm/i915/display/intel_sprite.c| 4 ++--
>  drivers/gpu/drm/i915/intel_device_info.c   | 6 +-
>  3 files changed, 11 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c 
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index cccfd45a67cf..e17b1ca356c3 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -5339,9 +5339,10 @@ static void tgl_bw_buddy_init(struct drm_i915_private 
> *dev_priv)
>   unsigned long abox_mask = INTEL_INFO(dev_priv)->abox_mask;
>   int config, i;
>  
> 
> 
> 
> - if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
> + if (IS_ALDERLAKE_S(dev_priv) ||
> + IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
>   IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_B0))
> - /* Wa_1409767108:tgl,dg1 */
> + /* Wa_1409767108:tgl,dg1,adl-s */
>   table = wa_1409767108_buddy_page_masks;
>   else
>   table = tgl_buddy_page_masks;
> @@ -5379,7 +5380,7 @@ static void icl_display_core_init(struct 
> drm_i915_private *dev_priv,
>  
> 
> 
> 
>   gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
>  
> 
> 
> 
> - /* Wa_14011294188:ehl,jsl,tgl,rkl */
> + /* Wa_14011294188:ehl,jsl,tgl,rkl,adl-s */
>   if (INTEL_PCH_TYPE(dev_priv) >= PCH_JSP &&
>   INTEL_PCH_TYPE(dev_priv) < PCH_DG1)
>   intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 0,
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c 
> b/drivers/gpu/drm/i915/display/intel_sprite.c
> index b1c7e9b010f4..402030251c64 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -2392,8 +2392,8 @@ static int skl_plane_check_fb(const struct 
> intel_crtc_state *crtc_state,
>   return -EINVAL;
>   }
>  
> 
> 
> 
> - /* Wa_1606054188:tgl */
> - if (IS_TIGERLAKE(dev_priv) &&
> + /* Wa_1606054188:tgl,adl-s */
> + if ((IS_ALDERLAKE_S(dev_priv) || IS_TIGERLAKE(dev_priv)) &&
>   plane_state->ckey.flags & I915_SET_COLORKEY_SOURCE &&
>   intel_format_is_p01x(fb->format->format)) {
>   drm_dbg_kms(_priv->drm,
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c 
> b/drivers/gpu/drm/i915/intel_device_info.c
> index 85d6883745d8..92ad3e7d1f6f 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -250,7 +250,11 @@ void intel_device_info_runtime_init(struct 
> drm_i915_private *dev_priv)
>   struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv);
>   enum pipe pipe;
>  
> 
> 
> 
> - if (INTEL_GEN(dev_priv) >= 10) {
> + /* Wa_14011765242: adl-s A0 */
> + if (IS_ADLS_DISP_STEPPING(dev_priv, STEP_A0, STEP_A0))
> + for_each_pipe(dev_priv, pipe)
> + runtime->num_scalers[pipe] = 0;
> + else if (INTEL_GEN(dev_priv) >= 10) {
>   for_each_pipe(dev_priv, pipe)
>   runtime->num_scalers[pipe] = 2;
>   } else if (IS_GEN(dev_priv, 9)) {

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[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gt: Ignore error capturing a closed context

[Patchwork]

== Series Details ==

Series: drm/i915/gt: Ignore error capturing a closed context
URL   : https://patchwork.freedesktop.org/series/86447/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_9699_full -> Patchwork_19541_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_19541_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_19541_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_19541_full:

### IGT changes ###

 Possible regressions 

  * igt@kms_cursor_crc@pipe-c-cursor-256x85-sliding:
- shard-skl:  [PASS][1] -> [DMESG-WARN][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9699/shard-skl10/igt@kms_cursor_...@pipe-c-cursor-256x85-sliding.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19541/shard-skl5/igt@kms_cursor_...@pipe-c-cursor-256x85-sliding.html

  
Known issues


  Here are the changes found in Patchwork_19541_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_fair@basic-deadline:
- shard-glk:  [PASS][3] -> [FAIL][4] ([i915#2846])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9699/shard-glk9/igt@gem_exec_f...@basic-deadline.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19541/shard-glk8/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-kbl:  [PASS][5] -> [FAIL][6] ([i915#2842]) +1 similar issue
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9699/shard-kbl2/igt@gem_exec_fair@basic-none-...@rcs0.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19541/shard-kbl2/igt@gem_exec_fair@basic-none-...@rcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][7] -> [FAIL][8] ([i915#2842]) +1 similar issue
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9699/shard-tglb3/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19541/shard-tglb1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
- shard-glk:  [PASS][9] -> [FAIL][10] ([i915#2842])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9699/shard-glk1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19541/shard-glk3/igt@gem_exec_fair@basic-pace-sh...@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][11] ([i915#2842]) +1 similar issue
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19541/shard-iclb1/igt@gem_exec_fair@basic-p...@vcs1.html

  * igt@gem_exec_schedule@u-fairslice-all:
- shard-tglb: [PASS][12] -> [DMESG-WARN][13] ([i915#2803]) +1 
similar issue
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9699/shard-tglb8/igt@gem_exec_sched...@u-fairslice-all.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19541/shard-tglb6/igt@gem_exec_sched...@u-fairslice-all.html

  * igt@gem_exec_schedule@u-fairslice@rcs0:
- shard-apl:  [PASS][14] -> [DMESG-WARN][15] ([i915#1610])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9699/shard-apl8/igt@gem_exec_schedule@u-fairsl...@rcs0.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19541/shard-apl7/igt@gem_exec_schedule@u-fairsl...@rcs0.html

  * igt@gem_userptr_blits@process-exit-mmap@gtt:
- shard-kbl:  NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#1699]) +3 
similar issues
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19541/shard-kbl1/igt@gem_userptr_blits@process-exit-m...@gtt.html

  * igt@kms_async_flips@alternate-sync-async-flip:
- shard-skl:  [PASS][17] -> [FAIL][18] ([i915#2521])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9699/shard-skl2/igt@kms_async_fl...@alternate-sync-async-flip.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19541/shard-skl9/igt@kms_async_fl...@alternate-sync-async-flip.html

  * igt@kms_big_joiner@basic:
- shard-kbl:  NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#2705])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19541/shard-kbl1/igt@kms_big_joi...@basic.html

  * igt@kms_chamelium@hdmi-mode-timings:
- shard-kbl:  NOTRUN -> [SKIP][20] ([fdo#109271] / [fdo#111827]) +3 
similar issues
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19541/shard-kbl1/igt@kms_chamel...@hdmi-mode-timings.html

  * igt@kms_color@pipe-d-ctm-0-5:
- shard-skl:  NOTRUN -> [SKIP][21] ([fdo#109271]) +51 similar issues
   [21]: 

Re: [Intel-gfx] [PATCH i-g-t 2/2] i915/sysfs_clients: Check that client ids are cyclic

[Tvrtko Ursulin]

On 29/01/2021 09:52, Chris Wilson wrote:

Quoting Tvrtko Ursulin (2021-01-29 09:18:50)

On 26/01/2021 13:05, Chris Wilson wrote:

The client id used is a cyclic allocator as that reduces the likelihood
of userspace seeing the same id used again (and so confusing the new
client as the old). Verify that each new client has an id greater than
the last.

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
---
   tests/i915/sysfs_clients.c | 129 +++--
   1 file changed, 108 insertions(+), 21 deletions(-)

diff --git a/tests/i915/sysfs_clients.c b/tests/i915/sysfs_clients.c
index a3a1f81e1..d2c1ebc5f 100644
--- a/tests/i915/sysfs_clients.c
+++ b/tests/i915/sysfs_clients.c
@@ -8,6 +8,7 @@
   #include 
   #include 
   #include 
+#include 
   #include 
   #include 
   #include 
@@ -47,6 +48,8 @@
   #define assert_within_epsilon(x, ref, tolerance) \
   __assert_within_epsilon(x, ref, tolerance / 100., tolerance / 100.)
   
+#define BUFSZ 280

+
   #define MI_BATCH_BUFFER_START (0x31 << 23)
   #define MI_BATCH_BUFFER_END (0xa << 23)
   #define MI_ARB_CHECK (0x5 << 23)
@@ -75,7 +78,7 @@ static void pidname(int i915, int clients)
   {
   struct dirent *de;
   int sv[2], rv[2];
- char buf[280];
+ char buf[BUFSZ];
   int me = -1;
   long count;
   pid_t pid;
@@ -180,7 +183,7 @@ static long count_clients(int clients)
   {
   struct dirent *de;
   long count = 0;
- char buf[280];
+ char buf[BUFSZ];
   DIR *dir;
   
   dir = fdopendir(dup(clients));

@@ -229,32 +232,113 @@ static void create(int i915, int clients)
   igt_assert_eq(count_clients(clients), 1);
   }
   
+static const char *find_client(int clients, pid_t pid, char *buf)

+{
+ DIR *dir = fdopendir(dup(clients));
+
+ /* Reading a dir as it changes does not appear to be stable, SEP */
+ for (int pass = 0; pass < 2; pass++) {
+ struct dirent *de;
+
+ rewinddir(dir);
+ while ((de = readdir(dir))) {
+ if (!isdigit(de->d_name[0]))
+ continue;
+
+ snprintf(buf, BUFSZ, "%s/pid", de->d_name);
+ igt_sysfs_read(clients, buf, buf, sizeof(buf));
+ if (atoi(buf) != pid)
+ continue;
+
+ strncpy(buf, de->d_name, BUFSZ);
+ goto out;
+ }
+ }
+ *buf = '\0';
+out:
+ closedir(dir);
+ return buf;
+}
+
   static int find_me(int clients, pid_t pid)
   {
- struct dirent *de;
- char buf[280];
- int me = -1;
- DIR *dir;
+ char buf[BUFSZ];
   
- dir = fdopendir(dup(clients));

- igt_assert(dir);
- rewinddir(dir);
+ return openat(clients,
+   find_client(clients, pid, buf),
+   O_DIRECTORY | O_RDONLY);
+}
   
- while ((de = readdir(dir))) {

- if (!isdigit(de->d_name[0]))
- continue;
+static int reopen_directory(int fd)
+{
+ char buf[BUFSZ];
+ int dir;
   
- snprintf(buf, sizeof(buf), "%s/pid", de->d_name);

- igt_sysfs_read(clients, buf, buf, sizeof(buf));
- if (atoi(buf) != pid)
- continue;
+ snprintf(buf, sizeof(buf), "/proc/self/fd/%d", fd);
+ dir = open(buf, O_RDONLY);


Maybe O_DIRECTORY if it is open_directory.


+ igt_assert_fd(dir);
   
- me = openat(clients, de->d_name, O_DIRECTORY | O_RDONLY);

- break;
+ return dir;
+}
+
+static unsigned int my_id(int clients, pid_t pid)
+{
+ char buf[BUFSZ];
+
+ return atoi(find_client(clients, pid, buf));
+}
+
+static unsigned int recycle_client(int i915, int clients)
+{
+ int device, client;
+
+ device = gem_reopen_driver(i915);
+ client = my_id(clients, getpid());
+ close(device);
+
+ return client;
+}
+
+static void recycle(int i915, int clients)
+{
+ const int ncpus = sysconf(_SC_NPROCESSORS_ONLN);
+
+ /*
+  * As we open and close clients, we do not expect to reuse old ids,
+  * i.e. we use a cyclic ida. This reduces the likelihood of userspace
+  * watchers becoming confused and mistaking the new client as a
+  * continuation of the old.
+  */
+ igt_require(my_id(clients, getpid()) < INT_MAX / 2);


Hm this is a bit dodgy - it will cause "permanent" skips if running the
test in a loop. Just for the client > last assert below? I guess it is
hard to handle wrap with forked clients.


It takes about a day to reach 2 billion ids on a fast machine. For CI, I
think we are safe.

We could do the (int)(A - B) > 0 to handle the wrap, that would be more
sensible.

[...]


Okay better than nothing.


But first we need to resolve the failure to find itself. :(


Forgot about that.. Start with one child for now?

Regards,

Tvrtko


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[Intel-gfx] [PATCH 6/8] drm/i915/adl_s: Update memory bandwidth parameters

[Aditya Swarup]

From: Tejas Upadhyay 

Just like RKL, the ADL_S platform also has different memory
characteristics from past platforms.  Update the values used
by our memory bandwidth calculations accordingly.

v2: Fix minor nitpick for shifting ADLS case above RKL(based on platform
order).(mdroper)

Bspec: 64631
Cc: Matt Roper 
Cc: Lucas De Marchi 
Cc: Jani Nikula 
Cc: Ville Syrjälä 
Cc: Imre Deak 
Signed-off-by: Tejas Upadhyay 
Signed-off-by: Aditya Swarup 
Reviewed-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/display/intel_bw.c | 11 ++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c 
b/drivers/gpu/drm/i915/display/intel_bw.c
index 4b5a30ac84bc..ec803861acb2 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -142,6 +142,12 @@ static const struct intel_sa_info rkl_sa_info = {
.displayrtids = 128,
 };
 
+static const struct intel_sa_info adls_sa_info = {
+   .deburst = 16,
+   .deprogbwlimit = 38, /* GB/s */
+   .displayrtids = 256,
+};
+
 static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct 
intel_sa_info *sa)
 {
struct intel_qgv_info qi = {};
@@ -251,7 +257,10 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv)
if (!HAS_DISPLAY(dev_priv))
return;
 
-   if (IS_ROCKETLAKE(dev_priv))
+
+   if (IS_ALDERLAKE_S(dev_priv))
+   icl_get_bw_info(dev_priv, _sa_info);
+   else if (IS_ROCKETLAKE(dev_priv))
icl_get_bw_info(dev_priv, _sa_info);
else if (IS_GEN(dev_priv, 12))
icl_get_bw_info(dev_priv, _sa_info);
-- 
2.27.0

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[Intel-gfx] [PATCH 7/8] drm/i915/adl_s: Add display WAs for ADL-S

[Aditya Swarup]

- Extend permanent driver WA Wa_1409767108, Wa_14010685332
  and Wa_14011294188 to adl-s.
- Extend permanent driver WA Wa_1606054188 to adl-s.
- Add Wa_14011765242 for adl-s A0 stepping.

Cc: Jani Nikula 
Cc: Ville Syrjälä 
Cc: Imre Deak 
Cc: Matt Roper 
Cc: Lucas De Marchi 
Signed-off-by: Aditya Swarup 
---
 drivers/gpu/drm/i915/display/intel_display_power.c | 7 ---
 drivers/gpu/drm/i915/display/intel_sprite.c| 4 ++--
 drivers/gpu/drm/i915/intel_device_info.c   | 6 +-
 3 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c 
b/drivers/gpu/drm/i915/display/intel_display_power.c
index cccfd45a67cf..e17b1ca356c3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5339,9 +5339,10 @@ static void tgl_bw_buddy_init(struct drm_i915_private 
*dev_priv)
unsigned long abox_mask = INTEL_INFO(dev_priv)->abox_mask;
int config, i;
 
-   if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
+   if (IS_ALDERLAKE_S(dev_priv) ||
+   IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_B0))
-   /* Wa_1409767108:tgl,dg1 */
+   /* Wa_1409767108:tgl,dg1,adl-s */
table = wa_1409767108_buddy_page_masks;
else
table = tgl_buddy_page_masks;
@@ -5379,7 +5380,7 @@ static void icl_display_core_init(struct drm_i915_private 
*dev_priv,
 
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 
-   /* Wa_14011294188:ehl,jsl,tgl,rkl */
+   /* Wa_14011294188:ehl,jsl,tgl,rkl,adl-s */
if (INTEL_PCH_TYPE(dev_priv) >= PCH_JSP &&
INTEL_PCH_TYPE(dev_priv) < PCH_DG1)
intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 0,
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c 
b/drivers/gpu/drm/i915/display/intel_sprite.c
index b1c7e9b010f4..402030251c64 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -2392,8 +2392,8 @@ static int skl_plane_check_fb(const struct 
intel_crtc_state *crtc_state,
return -EINVAL;
}
 
-   /* Wa_1606054188:tgl */
-   if (IS_TIGERLAKE(dev_priv) &&
+   /* Wa_1606054188:tgl,adl-s */
+   if ((IS_ALDERLAKE_S(dev_priv) || IS_TIGERLAKE(dev_priv)) &&
plane_state->ckey.flags & I915_SET_COLORKEY_SOURCE &&
intel_format_is_p01x(fb->format->format)) {
drm_dbg_kms(_priv->drm,
diff --git a/drivers/gpu/drm/i915/intel_device_info.c 
b/drivers/gpu/drm/i915/intel_device_info.c
index 85d6883745d8..92ad3e7d1f6f 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -250,7 +250,11 @@ void intel_device_info_runtime_init(struct 
drm_i915_private *dev_priv)
struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv);
enum pipe pipe;
 
-   if (INTEL_GEN(dev_priv) >= 10) {
+   /* Wa_14011765242: adl-s A0 */
+   if (IS_ADLS_DISP_STEPPING(dev_priv, STEP_A0, STEP_A0))
+   for_each_pipe(dev_priv, pipe)
+   runtime->num_scalers[pipe] = 0;
+   else if (INTEL_GEN(dev_priv) >= 10) {
for_each_pipe(dev_priv, pipe)
runtime->num_scalers[pipe] = 2;
} else if (IS_GEN(dev_priv, 9)) {
-- 
2.27.0

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[Intel-gfx] [PATCH 3/8] drm/i915/adl_s: Re-use TGL GuC/HuC firmware

[Aditya Swarup]

From: Matt Roper 

ADL-S, like RKL, uses the same internal device ID for the GuC and HuC as
TGL did, making them all firmware-compatible.  Let's re-use TGL's
firmware for ADL-S.

Bspec: 50668
Cc: John Harrison 
Cc: Lucas De Marchi 
Signed-off-by: Matt Roper 
Signed-off-by: Aditya Swarup 
Reviewed-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c 
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 67b06fde1225..984fa79e0fa7 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -44,9 +44,11 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw,
  * List of required GuC and HuC binaries per-platform.
  * Must be ordered based on platform + revid, from newer to older.
  *
- * Note that RKL uses the same firmware as TGL.
+ * Note that RKL and ADL-S have the same GuC/HuC device ID's and use the same
+ * firmware as TGL.
  */
 #define INTEL_UC_FIRMWARE_DEFS(fw_def, guc_def, huc_def) \
+   fw_def(ALDERLAKE_S, 0, guc_def(tgl, 49, 0, 1), huc_def(tgl,  7, 5, 0)) \
fw_def(ROCKETLAKE,  0, guc_def(tgl, 49, 0, 1), huc_def(tgl,  7, 5, 0)) \
fw_def(TIGERLAKE,   0, guc_def(tgl, 49, 0, 1), huc_def(tgl,  7, 5, 0)) \
fw_def(JASPERLAKE,  0, guc_def(ehl, 49, 0, 1), huc_def(ehl,  9, 0, 0)) \
-- 
2.27.0

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[Intel-gfx] [PATCH 5/8] drm/i915/adl_s: Load DMC

[Aditya Swarup]

From: Anusha Srivatsa 

Load DMC on ADL_S v2.01. This is the first offcial
release of DMC for ADL_S.

Cc: Jani Nikula 
Cc: Imre Deak 
Cc: Matt Roper 
Cc: Lucas De Marchi 
Cc: Aditya Swarup 
Signed-off-by: Anusha Srivatsa 
Signed-off-by: Aditya Swarup 
Reviewed-by: Aditya Swarup 
---
 drivers/gpu/drm/i915/display/intel_csr.c | 10 +-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_csr.c 
b/drivers/gpu/drm/i915/display/intel_csr.c
index 67dc64df78a5..db9f219c4b5a 100644
--- a/drivers/gpu/drm/i915/display/intel_csr.c
+++ b/drivers/gpu/drm/i915/display/intel_csr.c
@@ -40,6 +40,10 @@
 
 #define GEN12_CSR_MAX_FW_SIZE  ICL_CSR_MAX_FW_SIZE
 
+#define ADLS_CSR_PATH  "i915/adls_dmc_ver2_01.bin"
+#define ADLS_CSR_VERSION_REQUIRED  CSR_VERSION(2, 1)
+MODULE_FIRMWARE(ADLS_CSR_PATH);
+
 #define DG1_CSR_PATH   "i915/dg1_dmc_ver2_02.bin"
 #define DG1_CSR_VERSION_REQUIRED   CSR_VERSION(2, 2)
 MODULE_FIRMWARE(DG1_CSR_PATH);
@@ -689,7 +693,11 @@ void intel_csr_ucode_init(struct drm_i915_private 
*dev_priv)
 */
intel_csr_runtime_pm_get(dev_priv);
 
-   if (IS_DG1(dev_priv)) {
+   if (IS_ALDERLAKE_S(dev_priv)) {
+   csr->fw_path = ADLS_CSR_PATH;
+   csr->required_version = ADLS_CSR_VERSION_REQUIRED;
+   csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
+   } else if (IS_DG1(dev_priv)) {
csr->fw_path = DG1_CSR_PATH;
csr->required_version = DG1_CSR_VERSION_REQUIRED;
csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
-- 
2.27.0

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[Intel-gfx] [PATCH 4/8] drm/i915/display: Add HAS_D12_PLANE_MINIMIZATION

[Aditya Swarup]

From: José Roberto de Souza 

- As RKL and ADL-S only have 5 planes, primary and 4 sprites and
  the cursor plane, let's group the handling together under
  HAS_D12_PLANE_MINIMIZATION.
- Also use macro to select pipe irq fault error mask.

BSpec: 49251
Cc: Lucas De Marchi 
Cc: Jani Nikula 
Cc: Ville Syrjälä 
Cc: Imre Deak 
Cc: Matt Roper 
Signed-off-by: José Roberto de Souza 
Signed-off-by: Aditya Swarup 
Reviewed-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/display/intel_sprite.c | 2 +-
 drivers/gpu/drm/i915/i915_drv.h | 3 +++
 drivers/gpu/drm/i915/i915_irq.c | 2 +-
 drivers/gpu/drm/i915/intel_device_info.c| 2 +-
 4 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c 
b/drivers/gpu/drm/i915/display/intel_sprite.c
index 51cad1aefa5f..b1c7e9b010f4 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -382,7 +382,7 @@ int intel_plane_check_src_coordinates(struct 
intel_plane_state *plane_state)
 
 static u8 icl_nv12_y_plane_mask(struct drm_i915_private *i915)
 {
-   if (IS_ROCKETLAKE(i915))
+   if (HAS_D12_PLANE_MINIMIZATION(i915))
return BIT(PLANE_SPRITE2) | BIT(PLANE_SPRITE3);
else
return BIT(PLANE_SPRITE4) | BIT(PLANE_SPRITE5);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f684147290cb..18890d1ea57a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1783,6 +1783,9 @@ tgl_stepping_get(struct drm_i915_private *dev_priv)
 #define INTEL_DISPLAY_ENABLED(dev_priv) \
(drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), 
!(dev_priv)->params.disable_display)
 
+#define HAS_D12_PLANE_MINIMIZATION(dev_priv) (IS_ROCKETLAKE(dev_priv) || \
+ IS_ALDERLAKE_S(dev_priv))
+
 static inline bool run_as_guest(void)
 {
return !hypervisor_is_type(X86_HYPER_NATIVE);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 9665cd9742a6..352cd2260f55 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2289,7 +2289,7 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private 
*dev_priv)
 
 static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)
 {
-   if (IS_ROCKETLAKE(dev_priv))
+   if (HAS_D12_PLANE_MINIMIZATION(dev_priv))
return RKL_DE_PIPE_IRQ_FAULT_ERRORS;
else if (INTEL_GEN(dev_priv) >= 11)
return GEN11_DE_PIPE_IRQ_FAULT_ERRORS;
diff --git a/drivers/gpu/drm/i915/intel_device_info.c 
b/drivers/gpu/drm/i915/intel_device_info.c
index 7d98a718a051..85d6883745d8 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -261,7 +261,7 @@ void intel_device_info_runtime_init(struct drm_i915_private 
*dev_priv)
 
BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES);
 
-   if (IS_ROCKETLAKE(dev_priv))
+   if (HAS_D12_PLANE_MINIMIZATION(dev_priv))
for_each_pipe(dev_priv, pipe)
runtime->num_sprites[pipe] = 4;
else if (INTEL_GEN(dev_priv) >= 11)
-- 
2.27.0

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[Intel-gfx] [PATCH 1/8] drm/i915/adl_s: Update PHY_MISC programming

[Aditya Swarup]

From: Matt Roper 

ADL-S switches up which PHYs are considered a master to other PHYs;
PHY-C is no longer a master, but PHY-D is now.

Bspec: 49291
Cc: Jani Nikula 
Cc: Ville Syrjälä 
Cc: Imre Deak 
Cc: Lucas De Marchi 
Signed-off-by: Matt Roper 
Signed-off-by: Aditya Swarup 
Reviewed-by: Aditya Swarup 
---
 drivers/gpu/drm/i915/display/intel_combo_phy.c | 12 +---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c 
b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index dd45cbafcf42..c55813c6194a 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -187,10 +187,16 @@ static bool has_phy_misc(struct drm_i915_private *i915, 
enum phy phy)
 * Some platforms only expect PHY_MISC to be programmed for PHY-A and
 * PHY-B and may not even have instances of the register for the
 * other combo PHY's.
+*
+* ADL-S technically has three instances of PHY_MISC, but only requires
+* that we program it for PHY A.
 */
-   if (IS_JSL_EHL(i915) ||
-   IS_ROCKETLAKE(i915) ||
-   IS_DG1(i915))
+
+   if (IS_ALDERLAKE_S(i915))
+   return phy == PHY_A;
+   else if (IS_JSL_EHL(i915) ||
+IS_ROCKETLAKE(i915) ||
+IS_DG1(i915))
return phy < PHY_C;
 
return true;
-- 
2.27.0

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[Intel-gfx] [PATCH 8/8] drm/i915/adl_s: Add GT and CTX WAs for ADL-S

[Aditya Swarup]

- Extend Wa_1606931601 and Wa_1409804808 to ADL-S.
- Extend Wa_14010919138 and Wa_14010229206 to ADL-S (Madhumitha)
- Extend Wa_22010271021 to ADLS (cyokoyam)

v2:
- Extend Wa_1409804808 and remove unnecessary branching/redundant
  adls workaround placeholder functions.
- Split WAs properly based on previous platforms and applicable ADLS
  WA.

Cc: Jani Nikula 
Cc: Ville Syrjälä 
Cc: Imre Deak 
Cc: Matt Roper 
Cc: Lucas De Marchi 
Signed-off-by: Madhumitha Tolakanahalli Pradeep 

Signed-off-by: Aditya Swarup 
Reviewed-by: Matt Roper 
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 34 +
 1 file changed, 21 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 71d1c19c868b..3b4a7da60f0b 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -729,7 +729,8 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
 
if (IS_DG1(i915))
dg1_ctx_workarounds_init(engine, wal);
-   else if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915))
+   else if (IS_ALDERLAKE_S(i915) || IS_ROCKETLAKE(i915) ||
+IS_TIGERLAKE(i915))
tgl_ctx_workarounds_init(engine, wal);
else if (IS_GEN(i915, 12))
gen12_ctx_workarounds_init(engine, wal);
@@ -1639,45 +1640,45 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, 
struct i915_wa_list *wal)
GEN7_DISABLE_SAMPLER_PREFETCH);
}
 
-   if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
-   /* Wa_1606931601:tgl,rkl,dg1 */
+   if (IS_ALDERLAKE_S(i915) || IS_DG1(i915) ||
+   IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
+   /* Wa_1606931601:tgl,rkl,dg1,adl-s */
wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ);
 
/*
 * Wa_1407928979:tgl A*
 * Wa_18011464164:tgl[B0+],dg1[B0+]
 * Wa_22010931296:tgl[B0+],dg1[B0+]
-* Wa_14010919138:rkl, dg1
+* Wa_14010919138:rkl,dg1,adl-s
 */
wa_write_or(wal, GEN7_FF_THREAD_MODE,
GEN12_FF_TESSELATION_DOP_GATE_DISABLE);
 
/*
 * Wa_1606700617:tgl,dg1
-* Wa_22010271021:tgl,rkl,dg1
+* Wa_22010271021:tgl,rkl,dg1, adl-s
 */
wa_masked_en(wal,
 GEN9_CS_DEBUG_MODE1,
 FF_DOP_CLOCK_GATE_DISABLE);
-
-   /* Wa_1406941453:tgl,rkl,dg1 */
-   wa_masked_en(wal,
-GEN10_SAMPLER_MODE,
-ENABLE_SMALLPL);
}
 
-   if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
+   if (IS_ALDERLAKE_S(i915) || IS_DG1_REVID(i915, DG1_REVID_A0, 
DG1_REVID_A0) ||
IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
-   /* Wa_1409804808:tgl,rkl,dg1[a0] */
+   /* Wa_1409804808:tgl,rkl,dg1[a0],adl-s */
wa_masked_en(wal, GEN7_ROW_CHICKEN2,
 GEN12_PUSH_CONST_DEREF_HOLD_DIS);
 
/*
 * Wa_1409085225:tgl
-* Wa_14010229206:tgl,rkl,dg1[a0]
+* Wa_14010229206:tgl,rkl,dg1[a0],adl-s
 */
wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
+   }
+
 
+   if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
+   IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
/*
 * Wa_1607030317:tgl
 * Wa_1607186500:tgl
@@ -1694,6 +1695,13 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, 
struct i915_wa_list *wal)
 GEN8_RC_SEMA_IDLE_MSG_DISABLE);
}
 
+   if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
+   /* Wa_1406941453:tgl,rkl,dg1 */
+   wa_masked_en(wal,
+GEN10_SAMPLER_MODE,
+ENABLE_SMALLPL);
+   }
+
if (IS_GEN(i915, 11)) {
/* This is not an Wa. Enable for better image quality */
wa_masked_en(wal,
-- 
2.27.0

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[Intel-gfx] [PATCH 2/8] drm/i915/adl_s: Add power wells

[Aditya Swarup]

From: Lucas De Marchi 

TGL power wells can be re-used for ADL-S with the exception of the fake
power well for TC_COLD, just like DG-1.

BSpec: 53597
Bspec: 49231

Cc: Imre Deak 
Cc: Matt Roper 
Cc: Aditya Swarup 
Signed-off-by: Lucas De Marchi 
Signed-off-by: Aditya Swarup 
Reviewed-by: Matt Roper 
---
 drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c 
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 708f0b7e0990..cccfd45a67cf 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -4689,7 +4689,7 @@ int intel_power_domains_init(struct drm_i915_private 
*dev_priv)
 * The enabling order will be from lower to higher indexed wells,
 * the disabling order is reversed.
 */
-   if (IS_DG1(dev_priv)) {
+   if (IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv)) {
err = set_power_wells_mask(power_domains, tgl_power_wells,
   BIT_ULL(TGL_DISP_PW_TC_COLD_OFF));
} else if (IS_ROCKETLAKE(dev_priv)) {
-- 
2.27.0

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[Intel-gfx] [PATCH 0/8] Final set of patches for ADLS enabling

[Aditya Swarup]

These are the final set of patches required for enabling ADL-S. The
patches have been tested on platform and all display outputs are
working.

v2: Address minor nitpicks provided by mdroper.

Patch "drm/i915/adl_s: MCHBAR memory info registers are moved"
can be ignored as Jose's submission 
https://patchwork.freedesktop.org/series/86092/
allows us to fetch dram info from pcode.

Currently in his series, I didn't see removal of
skl_dram_get_channels_info(). So just to get clear results from CI, I
have included the MCHBAR patch in series.

v3:
- Drop MCHBAR patch and rebase on latest drm-tip that adds support for
  reading DRAM info through PCODE.
- Revert to STEP_A0 for Display WA as there is no STEP_A1 for ADLS.

Aditya Swarup (2):
  drm/i915/adl_s: Add display WAs for ADL-S
  drm/i915/adl_s: Add GT and CTX WAs for ADL-S

Anusha Srivatsa (1):
  drm/i915/adl_s: Load DMC

José Roberto de Souza (1):
  drm/i915/display: Add HAS_D12_PLANE_MINIMIZATION

Lucas De Marchi (1):
  drm/i915/adl_s: Add power wells

Matt Roper (2):
  drm/i915/adl_s: Update PHY_MISC programming
  drm/i915/adl_s: Re-use TGL GuC/HuC firmware

Tejas Upadhyay (1):
  drm/i915/adl_s: Update memory bandwidth parameters

 drivers/gpu/drm/i915/display/intel_bw.c   | 11 +-
 .../gpu/drm/i915/display/intel_combo_phy.c| 12 +--
 drivers/gpu/drm/i915/display/intel_csr.c  | 10 +-
 .../drm/i915/display/intel_display_power.c|  9 ++---
 drivers/gpu/drm/i915/display/intel_sprite.c   |  6 ++--
 drivers/gpu/drm/i915/gt/intel_workarounds.c   | 34 ---
 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c  |  4 ++-
 drivers/gpu/drm/i915/i915_drv.h   |  3 ++
 drivers/gpu/drm/i915/i915_irq.c   |  2 +-
 drivers/gpu/drm/i915/intel_device_info.c  |  8 +++--
 10 files changed, 70 insertions(+), 29 deletions(-)

-- 
2.27.0

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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gt: Restrict the GT clock override to just Icelake

[Patchwork]

== Series Details ==

Series: drm/i915/gt: Restrict the GT clock override to just Icelake
URL   : https://patchwork.freedesktop.org/series/86446/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9699_full -> Patchwork_19540_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Known issues


  Here are the changes found in Patchwork_19540_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_fair@basic-deadline:
- shard-glk:  [PASS][1] -> [FAIL][2] ([i915#2846])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9699/shard-glk9/igt@gem_exec_f...@basic-deadline.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19540/shard-glk1/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-none@vcs0:
- shard-apl:  [PASS][3] -> [FAIL][4] ([i915#2842]) +1 similar issue
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9699/shard-apl2/igt@gem_exec_fair@basic-n...@vcs0.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19540/shard-apl8/igt@gem_exec_fair@basic-n...@vcs0.html

  * igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][5] ([i915#2842])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19540/shard-iclb2/igt@gem_exec_fair@basic-n...@vcs1.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][6] -> [FAIL][7] ([i915#2842]) +1 similar issue
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9699/shard-tglb3/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19540/shard-tglb3/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
- shard-glk:  [PASS][8] -> [FAIL][9] ([i915#2842])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9699/shard-glk1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19540/shard-glk2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html

  * igt@gem_exec_fair@basic-pace@vecs0:
- shard-kbl:  [PASS][10] -> [FAIL][11] ([i915#2842]) +2 similar 
issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9699/shard-kbl4/igt@gem_exec_fair@basic-p...@vecs0.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19540/shard-kbl2/igt@gem_exec_fair@basic-p...@vecs0.html

  * igt@gem_exec_schedule@u-fairslice@vcs0:
- shard-glk:  [PASS][12] -> [DMESG-WARN][13] ([i915#1610] / 
[i915#2803])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9699/shard-glk4/igt@gem_exec_schedule@u-fairsl...@vcs0.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19540/shard-glk8/igt@gem_exec_schedule@u-fairsl...@vcs0.html
- shard-skl:  [PASS][14] -> [DMESG-WARN][15] ([i915#1610] / 
[i915#2803])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9699/shard-skl3/igt@gem_exec_schedule@u-fairsl...@vcs0.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19540/shard-skl9/igt@gem_exec_schedule@u-fairsl...@vcs0.html

  * igt@gem_userptr_blits@process-exit-mmap@gtt:
- shard-kbl:  NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#1699]) +3 
similar issues
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19540/shard-kbl7/igt@gem_userptr_blits@process-exit-m...@gtt.html

  * igt@kms_big_joiner@basic:
- shard-kbl:  NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#2705])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19540/shard-kbl7/igt@kms_big_joi...@basic.html

  * igt@kms_chamelium@hdmi-mode-timings:
- shard-kbl:  NOTRUN -> [SKIP][18] ([fdo#109271] / [fdo#111827]) +3 
similar issues
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19540/shard-kbl7/igt@kms_chamel...@hdmi-mode-timings.html

  * igt@kms_color@pipe-d-ctm-0-5:
- shard-skl:  NOTRUN -> [SKIP][19] ([fdo#109271]) +51 similar issues
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19540/shard-skl4/igt@kms_co...@pipe-d-ctm-0-5.html

  * igt@kms_color_chamelium@pipe-d-ctm-0-25:
- shard-skl:  NOTRUN -> [SKIP][20] ([fdo#109271] / [fdo#111827]) +1 
similar issue
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19540/shard-skl1/igt@kms_color_chamel...@pipe-d-ctm-0-25.html

  * igt@kms_cursor_crc@pipe-b-cursor-128x42-onscreen:
- shard-skl:  NOTRUN -> [FAIL][21] ([i915#54])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19540/shard-skl1/igt@kms_cursor_...@pipe-b-cursor-128x42-onscreen.html

  * igt@kms_cursor_crc@pipe-b-cursor-256x85-random:
- shard-skl:  [PASS][22] -> [FAIL][23] ([i915#54]) +4 similar issues
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9699/shard-skl5/igt@kms_cursor_...@pipe-b-cursor-256x85-random.html
   [23]: 

Re: [Intel-gfx] [PATCH 3/5] drm/i915: Power up combo PHY lanes for for HDMI as well

[Imre Deak]

On Fri, Jan 29, 2021 at 07:18:03PM +0200, Ville Syrjälä wrote:
> On Fri, Jan 29, 2021 at 07:06:33PM +0200, Imre Deak wrote:
> > On Thu, Jan 28, 2021 at 05:59:46PM +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä 
> > > 
> > > Currently we only explicitly power up the combo PHY lanes
> > > for DP. The spec says we should do it for HDMI as well.
> > > 
> > > Cc: sta...@vger.kernel.org
> > > Signed-off-by: Ville Syrjälä 
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++
> > >  1 file changed, 2 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
> > > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > index 88cc6e2fbe91..8fbeb8c24efb 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > @@ -4337,6 +4337,8 @@ static void intel_enable_ddi_hdmi(struct 
> > > intel_atomic_state *state,
> > >   intel_de_write(dev_priv, reg, val);
> > >   }
> > >  
> > > + intel_ddi_power_up_lanes(encoder, crtc_state);
> > > +
> > 
> > Not sure if it matters, but the spec says to apply WA #1143 just before
> > enabling DDI_BUF_CTL.
> 
> intel_ddi_power_up_lanes() is a nop for pre-icl, so we still do that.

Ok, missed this detail, it looks ok then:
Reviewed-by: Imre Deak 

> Also not sure what the final fate of that w/a will be since apparently
> it's not working as intended.
> 
> That said I was debating with myself what order to put these in, but
> in the end I chose this order because the w/a is related to the
> vswing programming, and so wanted to keep it next to the BUF_TRANS
> programming.
>
> > >   /* In HDMI/DVI mode, the port width, and swing/emphasis values
> > >* are ignored so nothing special needs to be done besides
> > >* enabling the port.
> > > -- 
> > > 2.26.2
> > > 
> > > ___
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Ville Syrjälä
> Intel
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Re: [Intel-gfx] [PATCH 4/5] drm/i915: Move HDMI vswing programming to the right place

[Ville Syrjälä]

On Fri, Jan 29, 2021 at 07:22:49PM +0200, Imre Deak wrote:
> On Thu, Jan 28, 2021 at 05:59:47PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä 
> > 
> > The documented programming sequence indicates the correct point
> > for the vswing programming is just before we enable the DDI.
> > Make it so.
> > 
> > Signed-off-by: Ville Syrjälä 
> > ---
> >  drivers/gpu/drm/i915/display/intel_ddi.c | 30 
> >  1 file changed, 15 insertions(+), 15 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 8fbeb8c24efb..efcdf5499903 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -3893,7 +3893,6 @@ static void intel_ddi_pre_enable_hdmi(struct 
> > intel_atomic_state *state,
> > struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> > struct intel_hdmi *intel_hdmi = _port->hdmi;
> > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > -   int level = intel_ddi_hdmi_level(encoder, crtc_state);
> >  
> > intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
> > intel_ddi_clk_select(encoder, crtc_state);
> > @@ -3904,20 +3903,6 @@ static void intel_ddi_pre_enable_hdmi(struct 
> > intel_atomic_state *state,
> >  
> > icl_program_mg_dp_mode(dig_port, crtc_state);
> >  
> > -   if (INTEL_GEN(dev_priv) >= 12)
> > -   tgl_ddi_vswing_sequence(encoder, crtc_state, level);
> > -   else if (INTEL_GEN(dev_priv) == 11)
> > -   icl_ddi_vswing_sequence(encoder, crtc_state, level);
> > -   else if (IS_CANNONLAKE(dev_priv))
> > -   cnl_ddi_vswing_sequence(encoder, crtc_state, level);
> > -   else if (IS_GEN9_LP(dev_priv))
> > -   bxt_ddi_vswing_sequence(encoder, crtc_state, level);
> > -   else
> > -   intel_prepare_hdmi_ddi_buffers(encoder, level);
> > -
> > -   if (IS_GEN9_BC(dev_priv))
> > -   skl_ddi_set_iboost(encoder, crtc_state, level);
> > -
> > intel_ddi_enable_pipe_clock(encoder, crtc_state);
> >  
> > dig_port->set_infoframes(encoder,
> > @@ -4293,6 +4278,7 @@ static void intel_enable_ddi_hdmi(struct 
> > intel_atomic_state *state,
> > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> > struct drm_connector *connector = conn_state->connector;
> > +   int level = intel_ddi_hdmi_level(encoder, crtc_state);
> > enum port port = encoder->port;
> >  
> > if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
> > @@ -4302,6 +4288,20 @@ static void intel_enable_ddi_hdmi(struct 
> > intel_atomic_state *state,
> > "[CONNECTOR:%d:%s] Failed to configure sink 
> > scrambling/TMDS bit clock ratio\n",
> > connector->base.id, connector->name);
> >  
> > +   if (INTEL_GEN(dev_priv) >= 12)
> > +   tgl_ddi_vswing_sequence(encoder, crtc_state, level);
> > +   else if (INTEL_GEN(dev_priv) == 11)
> > +   icl_ddi_vswing_sequence(encoder, crtc_state, level);
> > +   else if (IS_CANNONLAKE(dev_priv))
> > +   cnl_ddi_vswing_sequence(encoder, crtc_state, level);
> > +   else if (IS_GEN9_LP(dev_priv))
> > +   bxt_ddi_vswing_sequence(encoder, crtc_state, level);
> > +   else
> > +   intel_prepare_hdmi_ddi_buffers(encoder, level);
> 
> It's not specified where to do this on HSW, but I assume it matches BDW:

Should be fine. All we get on HSW is
"DDI_BUF_TRANS: ...
 Restriction : These registers must be programmed with valid values
 prior to enabling DDI_BUF_CTL."

> Reviewed-by: Imre Deak 
> 
> > +
> > +   if (IS_GEN9_BC(dev_priv))
> > +   skl_ddi_set_iboost(encoder, crtc_state, level);
> > +
> > /* Display WA #1143: skl,kbl,cfl */
> > if (IS_GEN9_BC(dev_priv)) {
> > /*
> > -- 
> > 2.26.2
> > 
> > ___
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> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH 8/9] drm/i915/adl_s: Add display WAs for ADL-S

[Souza, Jose]

On Wed, 2021-01-27 at 21:30 -0800, Aditya Swarup wrote:
> - Extend permanent driver WA Wa_1409767108, Wa_14010685332
>   and Wa_14011294188 to adl-s.
> - Extend permanent driver WA Wa_1606054188 to adl-s.
> - Add Wa_14011765242 for adl-s A0 stepping.
> 
> v2:
> - Extend Wa_14011765242 to STEP A1.(mdroper)
> 
> Cc: Jani Nikula 
> Cc: Ville Syrjälä 
> Cc: Imre Deak 
> Cc: Matt Roper 
> Cc: Lucas De Marchi 
> Signed-off-by: Aditya Swarup 
> ---
>  drivers/gpu/drm/i915/display/intel_display_power.c | 7 ---
>  drivers/gpu/drm/i915/display/intel_sprite.c| 4 ++--
>  drivers/gpu/drm/i915/i915_drv.h| 1 +
>  drivers/gpu/drm/i915/intel_device_info.c   | 6 +-
>  4 files changed, 12 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c 
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index cccfd45a67cf..e17b1ca356c3 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -5339,9 +5339,10 @@ static void tgl_bw_buddy_init(struct drm_i915_private 
> *dev_priv)
>   unsigned long abox_mask = INTEL_INFO(dev_priv)->abox_mask;
>   int config, i;
>  
> 
> 
> 
> - if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
> + if (IS_ALDERLAKE_S(dev_priv) ||
> + IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
>   IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_B0))
> - /* Wa_1409767108:tgl,dg1 */
> + /* Wa_1409767108:tgl,dg1,adl-s */
>   table = wa_1409767108_buddy_page_masks;
>   else
>   table = tgl_buddy_page_masks;
> @@ -5379,7 +5380,7 @@ static void icl_display_core_init(struct 
> drm_i915_private *dev_priv,
>  
> 
> 
> 
>   gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
>  
> 
> 
> 
> - /* Wa_14011294188:ehl,jsl,tgl,rkl */
> + /* Wa_14011294188:ehl,jsl,tgl,rkl,adl-s */
>   if (INTEL_PCH_TYPE(dev_priv) >= PCH_JSP &&
>   INTEL_PCH_TYPE(dev_priv) < PCH_DG1)
>   intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 0,
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c 
> b/drivers/gpu/drm/i915/display/intel_sprite.c
> index d216a863d818..ec931a08ff28 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -2373,8 +2373,8 @@ static int skl_plane_check_fb(const struct 
> intel_crtc_state *crtc_state,
>   return -EINVAL;
>   }
>  
> 
> 
> 
> - /* Wa_1606054188:tgl */
> - if (IS_TIGERLAKE(dev_priv) &&
> + /* Wa_1606054188:tgl,adl-s */
> + if ((IS_ALDERLAKE_S(dev_priv) || IS_TIGERLAKE(dev_priv)) &&
>   plane_state->ckey.flags & I915_SET_COLORKEY_SOURCE &&
>   intel_format_is_p01x(fb->format->format)) {
>   drm_dbg_kms(_priv->drm,
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 9713ab963122..a1fef2176ae0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1559,6 +1559,7 @@ extern const struct i915_rev_steppings kbl_revids[];
>  
> 
> 
> 
>  enum {
>   STEP_A0,
> + STEP_A1,
>   STEP_A2,
>   STEP_B0,
>   STEP_B1,
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c 
> b/drivers/gpu/drm/i915/intel_device_info.c
> index 85d6883745d8..06df1911cc7d 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -250,7 +250,11 @@ void intel_device_info_runtime_init(struct 
> drm_i915_private *dev_priv)
>   struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv);
>   enum pipe pipe;
>  
> 
> 
> 
> - if (INTEL_GEN(dev_priv) >= 10) {
> + /* Wa_14011765242: adl-s A0 */
> + if (IS_ADLS_DISP_STEPPING(dev_priv, STEP_A0, STEP_A1))

In my opinion "if (IS_ADLS_DISP_STEPPING(dev_priv, STEP_A0, STEP_A0))" is the 
right approach here, there no stepping with display A1 so just checking
STEP_A0 will be enough.

Also commented that in the previous version, maybe a third opinion to shine in?

Other than that it LGTM. 

> + for_each_pipe(dev_priv, pipe)
> + runtime->num_scalers[pipe] = 0;
> + else if (INTEL_GEN(dev_priv) >= 10) {
>   for_each_pipe(dev_priv, pipe)
>   runtime->num_scalers[pipe] = 2;
>   } else if (IS_GEN(dev_priv, 9)) {

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Re: [Intel-gfx] [PATCH 8/9] drm/i915/adl_s: Add display WAs for ADL-S

[Souza, Jose]

On Wed, 2021-01-27 at 21:43 -0800, Aditya Swarup wrote:
> On 1/26/21 9:22 PM, Matt Roper wrote:
> > On Tue, Jan 26, 2021 at 08:11:58PM -0800, Aditya Swarup wrote:
> > > - Extend permanent driver WA Wa_1409767108, Wa_14010685332
> > >   and Wa_14011294188 to adl-s.
> > > - Extend permanent driver WA Wa_1606054188 to adl-s.
> > > - Add Wa_14011765242 for adl-s A0 stepping.
> > > 
> > > Cc: Jani Nikula 
> > > Cc: Ville Syrjälä 
> > > Cc: Imre Deak 
> > > Cc: Matt Roper 
> > > Cc: Lucas De Marchi 
> > > Signed-off-by: Aditya Swarup 
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_display_power.c | 7 ---
> > >  drivers/gpu/drm/i915/display/intel_sprite.c| 4 ++--
> > >  drivers/gpu/drm/i915/intel_device_info.c   | 6 +-
> > >  3 files changed, 11 insertions(+), 6 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c 
> > > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > index cccfd45a67cf..e17b1ca356c3 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > @@ -5339,9 +5339,10 @@ static void tgl_bw_buddy_init(struct 
> > > drm_i915_private *dev_priv)
> > >   unsigned long abox_mask = INTEL_INFO(dev_priv)->abox_mask;
> > >   int config, i;
> > >  
> > > 
> > > 
> > > 
> > > - if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
> > > + if (IS_ALDERLAKE_S(dev_priv) ||
> > > + IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
> > >   IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_B0))
> > > - /* Wa_1409767108:tgl,dg1 */
> > > + /* Wa_1409767108:tgl,dg1,adl-s */
> > >   table = wa_1409767108_buddy_page_masks;
> > >   else
> > >   table = tgl_buddy_page_masks;
> > > @@ -5379,7 +5380,7 @@ static void icl_display_core_init(struct 
> > > drm_i915_private *dev_priv,
> > >  
> > > 
> > > 
> > > 
> > >   gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> > >  
> > > 
> > > 
> > > 
> > > - /* Wa_14011294188:ehl,jsl,tgl,rkl */
> > > + /* Wa_14011294188:ehl,jsl,tgl,rkl,adl-s */
> > >   if (INTEL_PCH_TYPE(dev_priv) >= PCH_JSP &&
> > >   INTEL_PCH_TYPE(dev_priv) < PCH_DG1)
> > >   intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 0,
> > > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c 
> > > b/drivers/gpu/drm/i915/display/intel_sprite.c
> > > index 68cea5ca251c..a7077babd31c 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> > > @@ -2418,8 +2418,8 @@ static int skl_plane_check_fb(const struct 
> > > intel_crtc_state *crtc_state,
> > >   return -EINVAL;
> > >   }
> > >  
> > > 
> > > 
> > > 
> > > - /* Wa_1606054188:tgl */
> > > - if (IS_TIGERLAKE(dev_priv) &&
> > > + /* Wa_1606054188:tgl,adl-s */
> > > + if ((IS_ALDERLAKE_S(dev_priv) || IS_TIGERLAKE(dev_priv)) &&
> > >   plane_state->ckey.flags & I915_SET_COLORKEY_SOURCE &&
> > >   intel_format_is_p01x(fb->format->format)) {
> > >   drm_dbg_kms(_priv->drm,
> > > diff --git a/drivers/gpu/drm/i915/intel_device_info.c 
> > > b/drivers/gpu/drm/i915/intel_device_info.c
> > > index 85d6883745d8..92ad3e7d1f6f 100644
> > > --- a/drivers/gpu/drm/i915/intel_device_info.c
> > > +++ b/drivers/gpu/drm/i915/intel_device_info.c
> > > @@ -250,7 +250,11 @@ void intel_device_info_runtime_init(struct 
> > > drm_i915_private *dev_priv)
> > >   struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv);
> > >   enum pipe pipe;
> > >  
> > > 
> > > 
> > > 
> > > - if (INTEL_GEN(dev_priv) >= 10) {
> > > + /* Wa_14011765242: adl-s A0 */
> > > + if (IS_ADLS_DISP_STEPPING(dev_priv, STEP_A0, STEP_A0))
> > 
> > I think this workaround is also needed on A1 stepping now and should
> > only be removed on A2.
> 
> There is no A1 stepping for ADLS. We directly have stepping A2 after A0. But 
> I have made the change
> that you have suggested in rev2.


In my opinion "if (IS_ADLS_DISP_STEPPING(dev_priv, STEP_A0, STEP_A0))" is the 
right approach here, there no stepping with display A1 so just checking
STEP_A0 will be enough.

> 
> Aditya
> 
> > 
> > 
> > Matt
> > 
> > > + for_each_pipe(dev_priv, pipe)
> > > + runtime->num_scalers[pipe] = 0;
> > > + else if (INTEL_GEN(dev_priv) >= 10) {
> > >   for_each_pipe(dev_priv, pipe)
> > >   runtime->num_scalers[pipe] = 2;
> > >   } else if (IS_GEN(dev_priv, 9)) {
> > > -- 
> > > 2.27.0
> > > 
> > 
> 
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Re: [Intel-gfx] [PATCH 5/5] drm/i915: Don't check tc_mode unless dealing with a TC PHY

[Imre Deak]

On Thu, Jan 28, 2021 at 05:59:48PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä 
> 
> We shouldn't really trust tc_mode on non-TC PHYs since we never
> initialize it explicitly. So let's check for the PHY type first.
> Fortunately TC_PORT_TBT_ALT happens to be zero so I don't think
> there's an actual bug here, just a possibility for a future one
> if someone rearranges the enum values.
> 
> Signed-off-by: Ville Syrjälä 

Reviewed-by: Imre Deak 

> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index efcdf5499903..5bc5033a2dea 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3463,10 +3463,12 @@ icl_program_mg_dp_mode(struct intel_digital_port 
> *dig_port,
>  {
>   struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
>   enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
> + enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
>   u32 ln0, ln1, pin_assignment;
>   u8 width;
>  
> - if (dig_port->tc_mode == TC_PORT_TBT_ALT)
> + if (!intel_phy_is_tc(dev_priv, phy) ||
> + dig_port->tc_mode == TC_PORT_TBT_ALT)
>   return;
>  
>   if (INTEL_GEN(dev_priv) >= 12) {
> -- 
> 2.26.2
> 
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Re: [Intel-gfx] [PATCH 4/5] drm/i915: Move HDMI vswing programming to the right place

[Imre Deak]

On Thu, Jan 28, 2021 at 05:59:47PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä 
> 
> The documented programming sequence indicates the correct point
> for the vswing programming is just before we enable the DDI.
> Make it so.
> 
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 30 
>  1 file changed, 15 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 8fbeb8c24efb..efcdf5499903 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3893,7 +3893,6 @@ static void intel_ddi_pre_enable_hdmi(struct 
> intel_atomic_state *state,
>   struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>   struct intel_hdmi *intel_hdmi = _port->hdmi;
>   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - int level = intel_ddi_hdmi_level(encoder, crtc_state);
>  
>   intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
>   intel_ddi_clk_select(encoder, crtc_state);
> @@ -3904,20 +3903,6 @@ static void intel_ddi_pre_enable_hdmi(struct 
> intel_atomic_state *state,
>  
>   icl_program_mg_dp_mode(dig_port, crtc_state);
>  
> - if (INTEL_GEN(dev_priv) >= 12)
> - tgl_ddi_vswing_sequence(encoder, crtc_state, level);
> - else if (INTEL_GEN(dev_priv) == 11)
> - icl_ddi_vswing_sequence(encoder, crtc_state, level);
> - else if (IS_CANNONLAKE(dev_priv))
> - cnl_ddi_vswing_sequence(encoder, crtc_state, level);
> - else if (IS_GEN9_LP(dev_priv))
> - bxt_ddi_vswing_sequence(encoder, crtc_state, level);
> - else
> - intel_prepare_hdmi_ddi_buffers(encoder, level);
> -
> - if (IS_GEN9_BC(dev_priv))
> - skl_ddi_set_iboost(encoder, crtc_state, level);
> -
>   intel_ddi_enable_pipe_clock(encoder, crtc_state);
>  
>   dig_port->set_infoframes(encoder,
> @@ -4293,6 +4278,7 @@ static void intel_enable_ddi_hdmi(struct 
> intel_atomic_state *state,
>   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>   struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>   struct drm_connector *connector = conn_state->connector;
> + int level = intel_ddi_hdmi_level(encoder, crtc_state);
>   enum port port = encoder->port;
>  
>   if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
> @@ -4302,6 +4288,20 @@ static void intel_enable_ddi_hdmi(struct 
> intel_atomic_state *state,
>   "[CONNECTOR:%d:%s] Failed to configure sink 
> scrambling/TMDS bit clock ratio\n",
>   connector->base.id, connector->name);
>  
> + if (INTEL_GEN(dev_priv) >= 12)
> + tgl_ddi_vswing_sequence(encoder, crtc_state, level);
> + else if (INTEL_GEN(dev_priv) == 11)
> + icl_ddi_vswing_sequence(encoder, crtc_state, level);
> + else if (IS_CANNONLAKE(dev_priv))
> + cnl_ddi_vswing_sequence(encoder, crtc_state, level);
> + else if (IS_GEN9_LP(dev_priv))
> + bxt_ddi_vswing_sequence(encoder, crtc_state, level);
> + else
> + intel_prepare_hdmi_ddi_buffers(encoder, level);

It's not specified where to do this on HSW, but I assume it matches BDW:
Reviewed-by: Imre Deak 

> +
> + if (IS_GEN9_BC(dev_priv))
> + skl_ddi_set_iboost(encoder, crtc_state, level);
> +
>   /* Display WA #1143: skl,kbl,cfl */
>   if (IS_GEN9_BC(dev_priv)) {
>   /*
> -- 
> 2.26.2
> 
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Re: [Intel-gfx] [PATCH 3/5] drm/i915: Power up combo PHY lanes for for HDMI as well

[Ville Syrjälä]

On Fri, Jan 29, 2021 at 07:06:33PM +0200, Imre Deak wrote:
> On Thu, Jan 28, 2021 at 05:59:46PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä 
> > 
> > Currently we only explicitly power up the combo PHY lanes
> > for DP. The spec says we should do it for HDMI as well.
> > 
> > Cc: sta...@vger.kernel.org
> > Signed-off-by: Ville Syrjälä 
> > ---
> >  drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++
> >  1 file changed, 2 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 88cc6e2fbe91..8fbeb8c24efb 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -4337,6 +4337,8 @@ static void intel_enable_ddi_hdmi(struct 
> > intel_atomic_state *state,
> > intel_de_write(dev_priv, reg, val);
> > }
> >  
> > +   intel_ddi_power_up_lanes(encoder, crtc_state);
> > +
> 
> Not sure if it matters, but the spec says to apply WA #1143 just before
> enabling DDI_BUF_CTL.

intel_ddi_power_up_lanes() is a nop for pre-icl, so we still do that.
Also not sure what the final fate of that w/a will be since apparently
it's not working as intended.

That said I was debating with myself what order to put these in, but
in the end I chose this order because the w/a is related to the
vswing programming, and so wanted to keep it next to the BUF_TRANS
programming.

> 
> 
> > /* In HDMI/DVI mode, the port width, and swing/emphasis values
> >  * are ignored so nothing special needs to be done besides
> >  * enabling the port.
> > -- 
> > 2.26.2
> > 
> > ___
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH 20/41] drm/i915: Replace priolist rbtree with a skiplist

[Matthew Brost]

On Fri, Jan 29, 2021 at 10:30:58AM +, Chris Wilson wrote:
> Quoting Matthew Brost (2021-01-28 22:56:04)
> > On Mon, Jan 25, 2021 at 02:01:15PM +, Chris Wilson wrote:
> > > Replace the priolist rbtree with a skiplist. The crucial difference is
> > > that walking and removing the first element of a skiplist is O(1), but
> > > O(lgN) for an rbtree, as we need to rebalance on remove. This is a
> > > hindrance for submission latency as it occurs between picking a request
> > > for the priolist and submitting it to hardware, as well effectively
> > > trippling the number of O(lgN) operations required under the irqoff lock.
> > > This is critical to reducing the latency jitter with multiple clients.
> > > 
> > > The downsides to skiplists are that lookup/insertion is only
> > > probablistically O(lgN) and there is a significant memory penalty to
> > > as each skip node is larger than the rbtree equivalent. Furthermore, we
> > > don't use dynamic arrays for the skiplist, so the allocation is fixed,
> > > and imposes an upper bound on the scalability wrt to the number of
> > > inflight requests.
> > > 
> > 
> > This is a fun data structure but IMO might be overkill to maintain this
> > code in the i915. The UMDs have effectively agreed to use only 3 levels,
> > is O(lgN) where N == 3 really a big deal? With GuC submission we will
> > statically map all user levels into 3 buckets. If we are doing that, do
> > we even need a complex data structure? i.e. Could use just use can
> > array of linked lists?
> 
> Because we need to scale the bst to handle a unqiue key per request with
> thousands of requests [this is not only about priorities]. And as you
> will see from the results, even with just a single priority in the system
> (so one entry in either the skiplist or rbtree), the skiplist is beating 
> the rbtree as measured by the lock hold time around insert/dequeue of
> requests. That surprised me.

Ok, seems reasonable. Skips list are pretty cool, wondering if at some
point we should make skip list code a bit more generic so it can
possibly be levered in other parts of the i915 / kernel.

Matt

> -Chris
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Re: [Intel-gfx] [PATCH 3/5] drm/i915: Power up combo PHY lanes for for HDMI as well

[Imre Deak]

On Thu, Jan 28, 2021 at 05:59:46PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä 
> 
> Currently we only explicitly power up the combo PHY lanes
> for DP. The spec says we should do it for HDMI as well.
> 
> Cc: sta...@vger.kernel.org
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 88cc6e2fbe91..8fbeb8c24efb 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4337,6 +4337,8 @@ static void intel_enable_ddi_hdmi(struct 
> intel_atomic_state *state,
>   intel_de_write(dev_priv, reg, val);
>   }
>  
> + intel_ddi_power_up_lanes(encoder, crtc_state);
> +

Not sure if it matters, but the spec says to apply WA #1143 just before
enabling DDI_BUF_CTL.


>   /* In HDMI/DVI mode, the port width, and swing/emphasis values
>* are ignored so nothing special needs to be done besides
>* enabling the port.
> -- 
> 2.26.2
> 
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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v14,1/2] drm/i915/display: Support PSR Multiple Instances

[Patchwork]

== Series Details ==

Series: series starting with [v14,1/2] drm/i915/display: Support PSR Multiple 
Instances
URL   : https://patchwork.freedesktop.org/series/86445/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9699_full -> Patchwork_19539_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Known issues


  Here are the changes found in Patchwork_19539_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_persistence@close-replace-race:
- shard-glk:  [PASS][1] -> [TIMEOUT][2] ([i915#2918])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9699/shard-glk6/igt@gem_ctx_persiste...@close-replace-race.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19539/shard-glk4/igt@gem_ctx_persiste...@close-replace-race.html

  * igt@gem_exec_fair@basic-deadline:
- shard-glk:  [PASS][3] -> [FAIL][4] ([i915#2846])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9699/shard-glk9/igt@gem_exec_f...@basic-deadline.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19539/shard-glk3/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][5] ([i915#2842])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19539/shard-iclb1/igt@gem_exec_fair@basic-n...@vcs1.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][6] -> [FAIL][7] ([i915#2842]) +1 similar issue
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9699/shard-tglb3/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19539/shard-tglb7/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
- shard-glk:  [PASS][8] -> [FAIL][9] ([i915#2842])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9699/shard-glk1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19539/shard-glk6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html

  * igt@gem_exec_fair@basic-pace@rcs0:
- shard-kbl:  [PASS][10] -> [FAIL][11] ([i915#2842])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9699/shard-kbl4/igt@gem_exec_fair@basic-p...@rcs0.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19539/shard-kbl7/igt@gem_exec_fair@basic-p...@rcs0.html

  * igt@gem_userptr_blits@process-exit-mmap@gtt:
- shard-kbl:  NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#1699]) +3 
similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19539/shard-kbl4/igt@gem_userptr_blits@process-exit-m...@gtt.html

  * igt@kms_big_joiner@basic:
- shard-kbl:  NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#2705])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19539/shard-kbl4/igt@kms_big_joi...@basic.html

  * igt@kms_chamelium@dp-crc-multiple:
- shard-skl:  NOTRUN -> [SKIP][14] ([fdo#109271] / [fdo#111827]) +5 
similar issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19539/shard-skl2/igt@kms_chamel...@dp-crc-multiple.html

  * igt@kms_chamelium@hdmi-mode-timings:
- shard-kbl:  NOTRUN -> [SKIP][15] ([fdo#109271] / [fdo#111827]) +3 
similar issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19539/shard-kbl4/igt@kms_chamel...@hdmi-mode-timings.html

  * igt@kms_color@pipe-d-ctm-0-5:
- shard-skl:  NOTRUN -> [SKIP][16] ([fdo#109271]) +85 similar issues
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19539/shard-skl8/igt@kms_co...@pipe-d-ctm-0-5.html

  * igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-skl:  [PASS][17] -> [INCOMPLETE][18] ([i915#2295] / 
[i915#300])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9699/shard-skl10/igt@kms_cursor_...@pipe-a-cursor-suspend.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19539/shard-skl7/igt@kms_cursor_...@pipe-a-cursor-suspend.html

  * igt@kms_cursor_crc@pipe-b-cursor-128x42-offscreen:
- shard-skl:  [PASS][19] -> [FAIL][20] ([i915#54]) +3 similar issues
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9699/shard-skl9/igt@kms_cursor_...@pipe-b-cursor-128x42-offscreen.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19539/shard-skl3/igt@kms_cursor_...@pipe-b-cursor-128x42-offscreen.html

  * igt@kms_cursor_crc@pipe-b-cursor-64x21-sliding:
- shard-skl:  NOTRUN -> [FAIL][21] ([i915#54])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19539/shard-skl2/igt@kms_cursor_...@pipe-b-cursor-64x21-sliding.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-varying-size:
- shard-apl:  NOTRUN -> [SKIP][22] ([fdo#109271]) +6 similar issues
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19539/shard-apl7/igt@kms_cursor_leg...@cursora-vs-flipb-varying-size.html

  * 

Re: [Intel-gfx] [PATCH 2/5] drm/i915: Extract intel_ddi_power_up_lanes()

[Imre Deak]

On Thu, Jan 28, 2021 at 05:59:45PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä 
> 
> Reduce the copypasta by pulling the combo PHY lane
> power up stuff into a helper. We'll have a third user soon.
> 
> Cc: sta...@vger.kernel.org
> Signed-off-by: Ville Syrjälä 

Reviewed-by: Imre Deak 

> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 35 +---
>  1 file changed, 19 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index c94650488dc1..88cc6e2fbe91 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3641,6 +3641,23 @@ static void intel_ddi_disable_fec_state(struct 
> intel_encoder *encoder,
>   intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
>  }
>  
> +static void intel_ddi_power_up_lanes(struct intel_encoder *encoder,
> +  const struct intel_crtc_state *crtc_state)
> +{
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> + enum phy phy = intel_port_to_phy(i915, encoder->port);
> +
> + if (intel_phy_is_combo(i915, phy)) {
> + bool lane_reversal =
> + dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
> +
> + intel_combo_phy_power_up_lanes(i915, phy, false,
> +crtc_state->lane_count,
> +lane_reversal);
> + }
> +}
> +
>  static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
> struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state,
> @@ -3732,14 +3749,7 @@ static void tgl_ddi_pre_enable_dp(struct 
> intel_atomic_state *state,
>* 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up
>* the used lanes of the DDI.
>*/
> - if (intel_phy_is_combo(dev_priv, phy)) {
> - bool lane_reversal =
> - dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
> -
> - intel_combo_phy_power_up_lanes(dev_priv, phy, false,
> -crtc_state->lane_count,
> -lane_reversal);
> - }
> + intel_ddi_power_up_lanes(encoder, crtc_state);
>  
>   /*
>* 7.g Configure and enable DDI_BUF_CTL
> @@ -3830,14 +3840,7 @@ static void hsw_ddi_pre_enable_dp(struct 
> intel_atomic_state *state,
>   else
>   intel_prepare_dp_ddi_buffers(encoder, crtc_state);
>  
> - if (intel_phy_is_combo(dev_priv, phy)) {
> - bool lane_reversal =
> - dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
> -
> - intel_combo_phy_power_up_lanes(dev_priv, phy, false,
> -crtc_state->lane_count,
> -lane_reversal);
> - }
> + intel_ddi_power_up_lanes(encoder, crtc_state);
>  
>   intel_ddi_init_dp_buf_reg(encoder, crtc_state);
>   if (!is_mst)
> -- 
> 2.26.2
> 
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Re: [Intel-gfx] [PATCH 1/5] drm/i915: Skip vswing programming for TBT

[Imre Deak]

On Thu, Jan 28, 2021 at 05:59:44PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä 
> 
> In thunderbolt mode the PHY is owned by the thunderbolt controller.
> We are not supposed to touch it. So skip the vswing programming
> as well (we already skipped the other steps not applicable to TBT).
> 
> Touching this stuff could supposedly interfere with the PHY
> programming done by the thunderbolt controller.
> 
> Cc: sta...@vger.kernel.org
> Signed-off-by: Ville Syrjälä 

Matches the spec:
Reviewed-by: Imre Deak 

> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 6 ++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 9506b8048530..c94650488dc1 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2827,6 +2827,9 @@ static void icl_mg_phy_ddi_vswing_sequence(struct 
> intel_encoder *encoder,
>   int n_entries, ln;
>   u32 val;
>  
> + if (enc_to_dig_port(encoder)->tc_mode == TC_PORT_TBT_ALT)
> + return;
> +
>   ddi_translations = icl_get_mg_buf_trans(encoder, crtc_state, 
> _entries);
>  
>   if (drm_WARN_ON_ONCE(_priv->drm, !ddi_translations))
> @@ -2962,6 +2965,9 @@ tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder 
> *encoder,
>   u32 val, dpcnt_mask, dpcnt_val;
>   int n_entries, ln;
>  
> + if (enc_to_dig_port(encoder)->tc_mode == TC_PORT_TBT_ALT)
> + return;
> +
>   ddi_translations = tgl_get_dkl_buf_trans(encoder, crtc_state, 
> _entries);
>  
>   if (drm_WARN_ON_ONCE(_priv->drm, !ddi_translations))
> -- 
> 2.26.2
> 
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[Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/2] drm/i915/display: Add a intel_pipe_is_enabled() helper

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/display: Add a 
intel_pipe_is_enabled() helper
URL   : https://patchwork.freedesktop.org/series/86454/
State : failure

== Summary ==

Applying: drm/i915/display: Add a intel_pipe_is_enabled() helper
Applying: drm/i915/display: Make vlv_find_free_pps() skip pipes which are in 
use for non DP purposes
error: sha1 information is lacking or useless 
(drivers/gpu/drm/i915/display/intel_dp.c).
error: could not build fake ancestor
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0002 drm/i915/display: Make vlv_find_free_pps() skip pipes 
which are in use for non DP purposes
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".


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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Add missing -EDEADLK path in execbuffer ggtt pinning.

[Patchwork]

== Series Details ==

Series: drm/i915: Add missing -EDEADLK path in execbuffer ggtt pinning.
URL   : https://patchwork.freedesktop.org/series/86452/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9700 -> Patchwork_19543


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19543/index.html

Known issues


  Here are the changes found in Patchwork_19543 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-byt-j1900:   NOTRUN -> [SKIP][1] ([fdo#109271]) +27 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19543/fi-byt-j1900/igt@gem_huc_c...@huc-copy.html

  * igt@gem_mmap_gtt@basic:
- fi-tgl-y:   [PASS][2] -> [DMESG-WARN][3] ([i915#402]) +1 similar 
issue
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9700/fi-tgl-y/igt@gem_mmap_...@basic.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19543/fi-tgl-y/igt@gem_mmap_...@basic.html

  * igt@kms_chamelium@hdmi-crc-fast:
- fi-byt-j1900:   NOTRUN -> [SKIP][4] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19543/fi-byt-j1900/igt@kms_chamel...@hdmi-crc-fast.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u:   [PASS][5] -> [DMESG-FAIL][6] ([i915#165])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9700/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19543/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html

  
 Possible fixes 

  * igt@debugfs_test@read_all_entries:
- fi-tgl-y:   [DMESG-WARN][7] ([i915#402]) -> [PASS][8] +2 similar 
issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9700/fi-tgl-y/igt@debugfs_test@read_all_entries.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19543/fi-tgl-y/igt@debugfs_test@read_all_entries.html

  * igt@i915_pm_rpm@module-reload:
- fi-kbl-guc: [FAIL][9] ([i915#2203] / [i915#579]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9700/fi-kbl-guc/igt@i915_pm_...@module-reload.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19543/fi-kbl-guc/igt@i915_pm_...@module-reload.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
  [i915#2203]: https://gitlab.freedesktop.org/drm/intel/issues/2203
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
  [i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579


Participating hosts (43 -> 39)
--

  Additional (1): fi-byt-j1900 
  Missing(5): fi-jsl-1 fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-bdw-samus 


Build changes
-

  * Linux: CI_DRM_9700 -> Patchwork_19543

  CI-20190529: 20190529
  CI_DRM_9700: b97c20a9180814dc69d5dbca6430a5e7c666 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5978: e1e5b3fea2baafdae0160940ecb8bf0242703840 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_19543: 772204b87113aee795162c5c6dc92145dfa40d0c @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

772204b87113 drm/i915: Add missing -EDEADLK path in execbuffer ggtt pinning.

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19543/index.html
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/debugfs: HDCP capability enc NULL check

[Patchwork]

== Series Details ==

Series: drm/i915/debugfs: HDCP capability enc NULL check
URL   : https://patchwork.freedesktop.org/series/86440/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9698_full -> Patchwork_19538_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Known issues


  Here are the changes found in Patchwork_19538_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_fair@basic-deadline:
- shard-kbl:  [PASS][1] -> [FAIL][2] ([i915#2846])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9698/shard-kbl6/igt@gem_exec_f...@basic-deadline.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19538/shard-kbl6/igt@gem_exec_f...@basic-deadline.html
- shard-glk:  [PASS][3] -> [FAIL][4] ([i915#2846])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9698/shard-glk9/igt@gem_exec_f...@basic-deadline.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19538/shard-glk6/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-iclb: NOTRUN -> [FAIL][5] ([i915#2842])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19538/shard-iclb2/igt@gem_exec_fair@basic-none-r...@rcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk:  [PASS][6] -> [FAIL][7] ([i915#2842])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9698/shard-glk2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19538/shard-glk1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html

  * igt@gem_exec_fair@basic-pace@rcs0:
- shard-kbl:  [PASS][8] -> [FAIL][9] ([i915#2842])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9698/shard-kbl7/igt@gem_exec_fair@basic-p...@rcs0.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19538/shard-kbl1/igt@gem_exec_fair@basic-p...@rcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][10] -> [FAIL][11] ([i915#2849])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9698/shard-iclb1/igt@gem_exec_fair@basic-throt...@rcs0.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19538/shard-iclb4/igt@gem_exec_fair@basic-throt...@rcs0.html

  * igt@gem_exec_params@rsvd2-dirt:
- shard-iclb: NOTRUN -> [SKIP][12] ([fdo#109283])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19538/shard-iclb2/igt@gem_exec_par...@rsvd2-dirt.html

  * igt@gem_exec_reloc@basic-many-active@rcs0:
- shard-iclb: NOTRUN -> [FAIL][13] ([i915#2389]) +3 similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19538/shard-iclb7/igt@gem_exec_reloc@basic-many-act...@rcs0.html

  * igt@gem_exec_schedule@u-fairslice@bcs0:
- shard-tglb: [PASS][14] -> [DMESG-WARN][15] ([i915#2803])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9698/shard-tglb6/igt@gem_exec_schedule@u-fairsl...@bcs0.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19538/shard-tglb8/igt@gem_exec_schedule@u-fairsl...@bcs0.html

  * igt@gem_exec_schedule@u-fairslice@rcs0:
- shard-skl:  [PASS][16] -> [DMESG-WARN][17] ([i915#1610] / 
[i915#2803])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9698/shard-skl7/igt@gem_exec_schedule@u-fairsl...@rcs0.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19538/shard-skl4/igt@gem_exec_schedule@u-fairsl...@rcs0.html

  * igt@gem_render_copy@linear-to-vebox-yf-tiled:
- shard-iclb: NOTRUN -> [SKIP][18] ([i915#768]) +1 similar issue
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19538/shard-iclb2/igt@gem_render_c...@linear-to-vebox-yf-tiled.html

  * igt@gem_softpin@evict-snoop:
- shard-iclb: NOTRUN -> [SKIP][19] ([fdo#109312])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19538/shard-iclb7/igt@gem_soft...@evict-snoop.html

  * igt@gem_userptr_blits@coherency-sync:
- shard-iclb: NOTRUN -> [SKIP][20] ([fdo#109290])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19538/shard-iclb2/igt@gem_userptr_bl...@coherency-sync.html

  * igt@gen9_exec_parse@allowed-all:
- shard-iclb: NOTRUN -> [SKIP][21] ([fdo#112306]) +2 similar issues
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19538/shard-iclb2/igt@gen9_exec_pa...@allowed-all.html

  * igt@i915_pm_dc@dc6-psr:
- shard-iclb: [PASS][22] -> [FAIL][23] ([i915#454])
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9698/shard-iclb2/igt@i915_pm...@dc6-psr.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19538/shard-iclb8/igt@i915_pm...@dc6-psr.html

  * igt@i915_pm_rpm@cursor:
- shard-tglb: [PASS][24] -> [INCOMPLETE][25] ([i915#2411])
   [24]: 

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v14,1/2] drm/i915/display: Support PSR Multiple Instances

[Patchwork]

== Series Details ==

Series: series starting with [v14,1/2] drm/i915/display: Support PSR Multiple 
Instances
URL   : https://patchwork.freedesktop.org/series/86433/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9698_full -> Patchwork_19537_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Known issues


  Here are the changes found in Patchwork_19537_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [PASS][1] -> [FAIL][2] ([i915#2842]) +2 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9698/shard-tglb5/igt@gem_exec_fair@basic-f...@rcs0.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19537/shard-tglb1/igt@gem_exec_fair@basic-f...@rcs0.html

  * igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-iclb: NOTRUN -> [FAIL][3] ([i915#2842])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19537/shard-iclb2/igt@gem_exec_fair@basic-none-r...@rcs0.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl:  [PASS][4] -> [FAIL][5] ([i915#2842]) +1 similar issue
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9698/shard-apl4/igt@gem_exec_fair@basic-none-s...@rcs0.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19537/shard-apl4/igt@gem_exec_fair@basic-none-s...@rcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk:  [PASS][6] -> [FAIL][7] ([i915#2842])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9698/shard-glk2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19537/shard-glk1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][8] -> [FAIL][9] ([i915#2849])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9698/shard-iclb1/igt@gem_exec_fair@basic-throt...@rcs0.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19537/shard-iclb5/igt@gem_exec_fair@basic-throt...@rcs0.html

  * igt@gem_exec_params@rsvd2-dirt:
- shard-iclb: NOTRUN -> [SKIP][10] ([fdo#109283])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19537/shard-iclb2/igt@gem_exec_par...@rsvd2-dirt.html

  * igt@gem_exec_reloc@basic-many-active@rcs0:
- shard-apl:  [PASS][11] -> [FAIL][12] ([i915#2389])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9698/shard-apl1/igt@gem_exec_reloc@basic-many-act...@rcs0.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19537/shard-apl4/igt@gem_exec_reloc@basic-many-act...@rcs0.html
- shard-iclb: NOTRUN -> [FAIL][13] ([i915#2389]) +3 similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19537/shard-iclb8/igt@gem_exec_reloc@basic-many-act...@rcs0.html

  * igt@gem_exec_schedule@u-fairslice@rcs0:
- shard-tglb: [PASS][14] -> [DMESG-WARN][15] ([i915#2803])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9698/shard-tglb6/igt@gem_exec_schedule@u-fairsl...@rcs0.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19537/shard-tglb2/igt@gem_exec_schedule@u-fairsl...@rcs0.html
- shard-skl:  [PASS][16] -> [DMESG-WARN][17] ([i915#1610] / 
[i915#2803])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9698/shard-skl7/igt@gem_exec_schedule@u-fairsl...@rcs0.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19537/shard-skl6/igt@gem_exec_schedule@u-fairsl...@rcs0.html

  * igt@gem_exec_whisper@basic-forked-all:
- shard-glk:  [PASS][18] -> [DMESG-WARN][19] ([i915#118] / 
[i915#95])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9698/shard-glk8/igt@gem_exec_whis...@basic-forked-all.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19537/shard-glk2/igt@gem_exec_whis...@basic-forked-all.html

  * igt@gem_render_copy@linear-to-vebox-yf-tiled:
- shard-iclb: NOTRUN -> [SKIP][20] ([i915#768]) +1 similar issue
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19537/shard-iclb2/igt@gem_render_c...@linear-to-vebox-yf-tiled.html

  * igt@gem_softpin@evict-snoop:
- shard-iclb: NOTRUN -> [SKIP][21] ([fdo#109312])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19537/shard-iclb8/igt@gem_soft...@evict-snoop.html

  * igt@gem_userptr_blits@coherency-sync:
- shard-iclb: NOTRUN -> [SKIP][22] ([fdo#109290])
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19537/shard-iclb2/igt@gem_userptr_bl...@coherency-sync.html

  * igt@gen9_exec_parse@allowed-all:
- shard-iclb: NOTRUN -> [SKIP][23] ([fdo#112306]) +2 similar issues
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19537/shard-iclb2/igt@gen9_exec_pa...@allowed-all.html

  * igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-iclb:   

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Remove obj->mm.lock! (rev14)

[Patchwork]

== Series Details ==

Series: drm/i915: Remove obj->mm.lock! (rev14)
URL   : https://patchwork.freedesktop.org/series/82337/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_9695_full -> Patchwork_19530_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_19530_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_19530_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_19530_full:

### IGT changes ###

 Possible regressions 

  * igt@gem_exec_reloc@basic-many-active@vecs0:
- shard-glk:  [PASS][1] -> [FAIL][2] +2 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9695/shard-glk8/igt@gem_exec_reloc@basic-many-act...@vecs0.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19530/shard-glk4/igt@gem_exec_reloc@basic-many-act...@vecs0.html
- shard-apl:  [PASS][3] -> [FAIL][4] +1 similar issue
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9695/shard-apl4/igt@gem_exec_reloc@basic-many-act...@vecs0.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19530/shard-apl1/igt@gem_exec_reloc@basic-many-act...@vecs0.html

  * igt@gem_userptr_blits@readonly-mmap-unsync:
- shard-tglb: NOTRUN -> [SKIP][5]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19530/shard-tglb1/igt@gem_userptr_bl...@readonly-mmap-unsync.html
- shard-iclb: NOTRUN -> [SKIP][6]
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19530/shard-iclb6/igt@gem_userptr_bl...@readonly-mmap-unsync.html

  * igt@gem_userptr_blits@unsync-unmap-cycles:
- shard-tglb: [PASS][7] -> [SKIP][8] +5 similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9695/shard-tglb5/igt@gem_userptr_bl...@unsync-unmap-cycles.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19530/shard-tglb7/igt@gem_userptr_bl...@unsync-unmap-cycles.html
- shard-iclb: [PASS][9] -> [SKIP][10] +5 similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9695/shard-iclb8/igt@gem_userptr_bl...@unsync-unmap-cycles.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19530/shard-iclb4/igt@gem_userptr_bl...@unsync-unmap-cycles.html

  * igt@gen9_exec_parse@bb-large:
- shard-kbl:  [PASS][11] -> [FAIL][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9695/shard-kbl2/igt@gen9_exec_pa...@bb-large.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19530/shard-kbl4/igt@gen9_exec_pa...@bb-large.html

  * igt@i915_module_load@reload-with-fault-injection:
- shard-glk:  [PASS][13] -> [INCOMPLETE][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9695/shard-glk1/igt@i915_module_l...@reload-with-fault-injection.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19530/shard-glk7/igt@i915_module_l...@reload-with-fault-injection.html

  * igt@i915_pm_backlight@fade_with_dpms:
- shard-iclb: [PASS][15] -> [DMESG-WARN][16]
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9695/shard-iclb4/igt@i915_pm_backlight@fade_with_dpms.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19530/shard-iclb8/igt@i915_pm_backlight@fade_with_dpms.html

  
 Warnings 

  * igt@gem_userptr_blits@coherency-unsync:
- shard-tglb: [SKIP][17] ([fdo#110542]) -> [SKIP][18]
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9695/shard-tglb3/igt@gem_userptr_bl...@coherency-unsync.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19530/shard-tglb8/igt@gem_userptr_bl...@coherency-unsync.html

  * igt@gem_userptr_blits@readonly-pwrite-unsync:
- shard-tglb: [SKIP][19] ([fdo#110426] / [i915#1704]) -> [SKIP][20] 
+1 similar issue
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9695/shard-tglb5/igt@gem_userptr_bl...@readonly-pwrite-unsync.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19530/shard-tglb7/igt@gem_userptr_bl...@readonly-pwrite-unsync.html
- shard-iclb: [SKIP][21] ([fdo#110426] / [i915#1704]) -> [SKIP][22] 
+1 similar issue
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9695/shard-iclb7/igt@gem_userptr_bl...@readonly-pwrite-unsync.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19530/shard-iclb5/igt@gem_userptr_bl...@readonly-pwrite-unsync.html

  * igt@gem_userptr_blits@vma-merge:
- shard-apl:  [INCOMPLETE][23] ([i915#2502] / [i915#2667]) -> 
[INCOMPLETE][24]
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9695/shard-apl3/igt@gem_userptr_bl...@vma-merge.html
   [24]: 

Re: [Intel-gfx] [PATCH] drm/i915/bios: tidy up child device debug logging

[Ville Syrjälä]

On Wed, Jan 27, 2021 at 10:45:34AM +0200, Jani Nikula wrote:
> Make the child device details easier to read by turning this:
> 
> [drm:parse_ddi_port [i915]] Port B VBT info: CRT:0 DVI:1 HDMI:1 DP:0 eDP:0 
> LSPCON:0 USB-Type-C:0 TBT:0 DSC:0
> [drm:parse_ddi_port [i915]] VBT HDMI level shift for port B: 8
> [drm:parse_ddi_port [i915]] VBT DP max link rate for port B: 81
> [drm:parse_ddi_port [i915]] Port C VBT info: CRT:0 DVI:1 HDMI:1 DP:1 eDP:0 
> LSPCON:0 USB-Type-C:0 TBT:0 DSC:0
> [drm:parse_ddi_port [i915]] VBT HDMI level shift for port C: 8
> [drm:parse_ddi_port [i915]] VBT (e)DP boost level for port C: 3
> [drm:parse_ddi_port [i915]] VBT HDMI boost level for port C: 1
> [drm:parse_ddi_port [i915]] VBT DP max link rate for port C: 81
> 
> into this:
> 
> [drm:parse_ddi_port [i915]] Port B VBT info: CRT:0 DVI:1 HDMI:1 DP:0 eDP:0 
> LSPCON:0 USB-Type-C:0 TBT:0 DSC:0
> [drm:parse_ddi_port [i915]] Port B VBT HDMI level shift: 8
> [drm:parse_ddi_port [i915]] Port B VBT DP max link rate: 81
> [drm:parse_ddi_port [i915]] Port C VBT info: CRT:0 DVI:1 HDMI:1 DP:1 eDP:0 
> LSPCON:0 USB-Type-C:0 TBT:0 DSC:0
> [drm:parse_ddi_port [i915]] Port C VBT HDMI level shift: 8
> [drm:parse_ddi_port [i915]] Port C VBT (e)DP boost level: 3
> [drm:parse_ddi_port [i915]] Port C VBT HDMI boost level: 1
> [drm:parse_ddi_port [i915]] Port C VBT DP max link rate: 81
> 
> Signed-off-by: Jani Nikula 

Reviewed-by: Ville Syrjälä 

> ---
>  drivers/gpu/drm/i915/display/intel_bios.c | 10 +-
>  1 file changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c 
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index 04337ac6f8c4..796d6be0ba5d 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -1829,7 +1829,7 @@ static void parse_ddi_port(struct drm_i915_private 
> *dev_priv,
>   /* The VBT HDMI level shift values match the table we have. */
>   u8 hdmi_level_shift = child->hdmi_level_shifter_value;
>   drm_dbg_kms(_priv->drm,
> - "VBT HDMI level shift for port %c: %d\n",
> + "Port %c VBT HDMI level shift: %d\n",
>   port_name(port),
>   hdmi_level_shift);
>   info->hdmi_level_shift = hdmi_level_shift;
> @@ -1856,7 +1856,7 @@ static void parse_ddi_port(struct drm_i915_private 
> *dev_priv,
>  
>   if (max_tmds_clock)
>   drm_dbg_kms(_priv->drm,
> - "VBT HDMI max TMDS clock for port %c: %d 
> kHz\n",
> + "Port %c VBT HDMI max TMDS clock: %d kHz\n",
>   port_name(port), max_tmds_clock);
>   info->max_tmds_clock = max_tmds_clock;
>   }
> @@ -1865,11 +1865,11 @@ static void parse_ddi_port(struct drm_i915_private 
> *dev_priv,
>   if (bdb_version >= 196 && child->iboost) {
>   info->dp_boost_level = translate_iboost(child->dp_iboost_level);
>   drm_dbg_kms(_priv->drm,
> - "VBT (e)DP boost level for port %c: %d\n",
> + "Port %c VBT (e)DP boost level: %d\n",
>   port_name(port), info->dp_boost_level);
>   info->hdmi_boost_level = 
> translate_iboost(child->hdmi_iboost_level);
>   drm_dbg_kms(_priv->drm,
> - "VBT HDMI boost level for port %c: %d\n",
> + "Port %c VBT HDMI boost level: %d\n",
>   port_name(port), info->hdmi_boost_level);
>   }
>  
> @@ -1891,7 +1891,7 @@ static void parse_ddi_port(struct drm_i915_private 
> *dev_priv,
>   break;
>   }
>   drm_dbg_kms(_priv->drm,
> - "VBT DP max link rate for port %c: %d\n",
> + "Port %c VBT DP max link rate: %d\n",
>   port_name(port), info->dp_max_link_rate);
>   }
>  
> -- 
> 2.20.1
> 
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH] drm/i915/gt: Ignore error capturing a closed context

[Mika Kuoppala]

Chris Wilson  writes:

> To capture a context after a gpu hang, we suspend the request and then
> resume its execution afterwards. If the context is already closed, we
> can assume that no one is interested in the result, but instead we are
> trying to terminate execution quickly as part of a forced-preemption.
> In which case, do not waste time in suspending the request, capturing
> the error, and just cancel it instead.
>
> Testcase: igt/gem_ctx_persistence/many-contexts
> Signed-off-by: Chris Wilson 

Reviewed-by: Mika Kuoppala 

> ---
>  .../drm/i915/gt/intel_execlists_submission.c   | 18 +-
>  1 file changed, 13 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c 
> b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index e20ab2eab3a8..2280d1bd2c77 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -2249,10 +2249,21 @@ static u32 active_ccid(struct intel_engine_cs *engine)
>  static void execlists_capture(struct intel_engine_cs *engine)
>  {
>   struct execlists_capture *cap;
> + struct i915_request *rq;
>  
>   if (!IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR))
>   return;
>  
> + rq = active_context(engine, active_ccid(engine));
> +
> + /*
> +  * If the context is closed, assume no one is listening for the
> +  * associated state; the user is already gone. We can save a lot of
> +  * time around forced-preemption by just cancelling the guilty request.
> +  */
> + if (!rq || intel_context_is_closed(rq->context))
> + return;
> +
>   /*
>* We need to _quickly_ capture the engine state before we reset.
>* We are inside an atomic section (softirq) here and we are delaying
> @@ -2262,11 +2273,8 @@ static void execlists_capture(struct intel_engine_cs 
> *engine)
>   if (!cap)
>   return;
>  
> - cap->rq = active_context(engine, active_ccid(engine));
> - if (cap->rq) {
> - cap->rq = active_request(cap->rq->context->timeline, cap->rq);
> - cap->rq = i915_request_get_rcu(cap->rq);
> - }
> + rq = active_request(rq->context->timeline, rq);
> + cap->rq = i915_request_get_rcu(rq);
>   if (!cap->rq)
>   goto err_free;
>  
> -- 
> 2.20.1
>
> ___
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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[Intel-gfx] ✗ Fi.CI.IGT: failure for disable the QSES check for HDCP2.2 over MST (rev2)

[Patchwork]

== Series Details ==

Series: disable the QSES check for HDCP2.2 over MST (rev2)
URL   : https://patchwork.freedesktop.org/series/86375/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_9697_full -> Patchwork_19536_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_19536_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_19536_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_19536_full:

### IGT changes ###

 Possible regressions 

  * igt@gem_exec_flush@basic-wb-ro-default:
- shard-skl:  [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9697/shard-skl6/igt@gem_exec_fl...@basic-wb-ro-default.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19536/shard-skl1/igt@gem_exec_fl...@basic-wb-ro-default.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@gem_ctx_persistence@many-contexts}:
- shard-tglb: [PASS][3] -> [FAIL][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9697/shard-tglb2/igt@gem_ctx_persiste...@many-contexts.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19536/shard-tglb6/igt@gem_ctx_persiste...@many-contexts.html

  * {igt@sysfs_clients@busy@vecs0}:
- shard-kbl:  [PASS][5] -> [FAIL][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9697/shard-kbl7/igt@sysfs_clients@b...@vecs0.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19536/shard-kbl7/igt@sysfs_clients@b...@vecs0.html

  
Known issues


  Here are the changes found in Patchwork_19536_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@feature_discovery@psr2:
- shard-iclb: [PASS][7] -> [SKIP][8] ([i915#658])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9697/shard-iclb2/igt@feature_discov...@psr2.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19536/shard-iclb1/igt@feature_discov...@psr2.html

  * igt@gem_ctx_isolation@preservation-s3@vecs0:
- shard-skl:  [PASS][9] -> [INCOMPLETE][10] ([i915#198])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9697/shard-skl8/igt@gem_ctx_isolation@preservation...@vecs0.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19536/shard-skl8/igt@gem_ctx_isolation@preservation...@vecs0.html

  * igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [PASS][11] -> [FAIL][12] ([i915#2842])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9697/shard-tglb7/igt@gem_exec_fair@basic-f...@rcs0.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19536/shard-tglb2/igt@gem_exec_fair@basic-f...@rcs0.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
- shard-apl:  [PASS][13] -> [SKIP][14] ([fdo#109271])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9697/shard-apl7/igt@gem_exec_fair@basic-none-sh...@rcs0.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19536/shard-apl1/igt@gem_exec_fair@basic-none-sh...@rcs0.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-kbl:  [PASS][15] -> [FAIL][16] ([i915#2842]) +3 similar 
issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9697/shard-kbl4/igt@gem_exec_fair@basic-none-s...@rcs0.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19536/shard-kbl2/igt@gem_exec_fair@basic-none-s...@rcs0.html

  * igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][17] ([i915#2842])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19536/shard-iclb2/igt@gem_exec_fair@basic-n...@vcs1.html

  * igt@gem_exec_reloc@basic-wide-active@vcs1:
- shard-iclb: NOTRUN -> [FAIL][18] ([i915#2389])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19536/shard-iclb1/igt@gem_exec_reloc@basic-wide-act...@vcs1.html

  * igt@gem_exec_schedule@u-fairslice@vcs0:
- shard-skl:  [PASS][19] -> [DMESG-WARN][20] ([i915#1610] / 
[i915#2803])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9697/shard-skl5/igt@gem_exec_schedule@u-fairsl...@vcs0.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19536/shard-skl3/igt@gem_exec_schedule@u-fairsl...@vcs0.html

  * igt@gem_mmap_wc@set-cache-level:
- shard-snb:  [PASS][21] -> [SKIP][22] ([fdo#109271])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9697/shard-snb2/igt@gem_mmap...@set-cache-level.html
   [22]: 

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gt: Only trust sseu subslice fuse if it is set

[Patchwork]

== Series Details ==

Series: drm/i915/gt: Only trust sseu subslice fuse if it is set
URL   : https://patchwork.freedesktop.org/series/86451/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_9699 -> Patchwork_19542


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_19542 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_19542, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19542/index.html

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_19542:

### IGT changes ###

 Possible regressions 

  * igt@i915_getparams_basic@basic-eu-total:
- fi-bxt-dsi: [PASS][1] -> [FAIL][2] +1 similar issue
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9699/fi-bxt-dsi/igt@i915_getparams_ba...@basic-eu-total.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19542/fi-bxt-dsi/igt@i915_getparams_ba...@basic-eu-total.html
- fi-apl-guc: [PASS][3] -> [FAIL][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9699/fi-apl-guc/igt@i915_getparams_ba...@basic-eu-total.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19542/fi-apl-guc/igt@i915_getparams_ba...@basic-eu-total.html

  * igt@i915_getparams_basic@basic-subslice-total:
- fi-glk-dsi: [PASS][5] -> [FAIL][6] +1 similar issue
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9699/fi-glk-dsi/igt@i915_getparams_ba...@basic-subslice-total.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19542/fi-glk-dsi/igt@i915_getparams_ba...@basic-subslice-total.html

  
Known issues


  Here are the changes found in Patchwork_19542 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@prime_self_import@basic-with_two_bos:
- fi-tgl-y:   [PASS][7] -> [DMESG-WARN][8] ([i915#402]) +2 similar 
issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9699/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19542/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s0:
- {fi-cml-drallion}:  [INCOMPLETE][9] ([i915#1614]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9699/fi-cml-drallion/igt@gem_exec_susp...@basic-s0.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19542/fi-cml-drallion/igt@gem_exec_susp...@basic-s0.html

  * igt@i915_getparams_basic@basic-subslice-total:
- fi-tgl-y:   [DMESG-WARN][11] ([i915#402]) -> [PASS][12] +1 
similar issue
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9699/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19542/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1614]: https://gitlab.freedesktop.org/drm/intel/issues/1614
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2331]: https://gitlab.freedesktop.org/drm/intel/issues/2331
  [i915#2546]: https://gitlab.freedesktop.org/drm/intel/issues/2546
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402


Participating hosts (45 -> 40)
--

  Missing(5): fi-jsl-1 fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-bdw-samus 


Build changes
-

  * Linux: CI_DRM_9699 -> Patchwork_19542

  CI-20190529: 20190529
  CI_DRM_9699: 227f6526730330c19bbf781bc59e684ccf373de8 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5978: e1e5b3fea2baafdae0160940ecb8bf0242703840 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_19542: b04632391b009f67d1d98596ec2434a693b2baf8 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

b04632391b00 drm/i915/gt: Only trust sseu subslice fuse if it is set

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19542/index.html
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Re: [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,1/3] drm/i915: Nuke not needed members of dram_info

[Souza, Jose]

On Fri, 2021-01-29 at 11:17 +, Patchwork wrote:
Patch Details
Series: series starting with [CI,1/3] drm/i915: Nuke not needed members of 
dram_info
URL:https://patchwork.freedesktop.org/series/86404/
State:  success
Details:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19531/index.html
CI Bug Log - changes from CI_DRM_9695_full -> Patchwork_19531_full
Summary

SUCCESS

No regressions found.

Pushed, thanks for the reviews Lucas.

Known issues

Here are the changes found in Patchwork_19531_full that come from known issues:

IGT changes
Issues hit

  *   igt@feature_discovery@psr2:

 *   shard-iclb: NOTRUN -> 
SKIP
 (i915#658) +1 similar 
issue
  *   igt@gem_ctx_persistence@close-replace-race:

 *   shard-kbl: 
PASS
 -> 
TIMEOUT
 (i915#2918)
  *   igt@gem_exec_capture@pi@rcs0:

 *   shard-skl: 
PASS
 -> 
INCOMPLETE
 (i915#2369 / 
i915#2502)
  *   igt@gem_exec_fair@basic-deadline:

 *   shard-glk: 
PASS
 -> 
FAIL
 (i915#2846)
  *   igt@gem_exec_fair@basic-pace@vcs1:

 *   shard-iclb: NOTRUN -> 
FAIL
 (i915#2842) +1 similar 
issue
  *   igt@gem_exec_fair@basic-throttle@rcs0:

 *   shard-glk: 
PASS
 -> 
FAIL
 (i915#2842)
  *   igt@gem_exec_whisper@basic-fds-forked:

 *   shard-glk: 
PASS
 -> 
DMESG-WARN
 (i915#118 / 
i915#95)
  *   igt@gem_readwrite@beyond-eob:

 *   shard-skl: 
PASS
 -> 
DMESG-WARN
 (i915#1982) +2 similar 
issues
  *   igt@gen9_exec_parse@bb-large:

 *   shard-apl: 
PASS
 -> 
TIMEOUT
 (i915#2502)
  *   igt@i915_pm_dc@dc6-psr:

 *   shard-iclb: NOTRUN -> 
FAIL
 (i915#454)
  *   igt@i915_pm_rpm@modeset-non-lpsp:

 *   shard-iclb: NOTRUN -> 
SKIP
 (fdo#110892)
  *   igt@kms_async_flips@test-time-stamp:

 *   shard-tglb: 
PASS
 -> 
FAIL
 (i915#2597)
  *   igt@kms_atomic_transition@plane-all-modeset-transition:

 *   shard-iclb: NOTRUN -> 
SKIP
 (i915#1769)
  *   igt@kms_big_fb@yf-tiled-8bpp-rotate-270:

 *   shard-iclb: 

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/gvt: Parse default state to update reg whitelist

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/gvt: Parse default state to update 
reg whitelist
URL   : https://patchwork.freedesktop.org/series/86425/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9696_full -> Patchwork_19535_full


Summary
---

  **WARNING**

  Minor unknown changes coming with Patchwork_19535_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_19535_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_19535_full:

### IGT changes ###

 Warnings 

  * igt@kms_color@pipe-c-legacy-gamma-reset:
- shard-kbl:  [FAIL][1] ([i915#2964]) -> [FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9696/shard-kbl4/igt@kms_co...@pipe-c-legacy-gamma-reset.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19535/shard-kbl1/igt@kms_co...@pipe-c-legacy-gamma-reset.html
- shard-apl:  [FAIL][3] ([i915#2964]) -> [FAIL][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9696/shard-apl3/igt@kms_co...@pipe-c-legacy-gamma-reset.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19535/shard-apl3/igt@kms_co...@pipe-c-legacy-gamma-reset.html
- shard-glk:  [FAIL][5] ([i915#2964]) -> [FAIL][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9696/shard-glk2/igt@kms_co...@pipe-c-legacy-gamma-reset.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19535/shard-glk7/igt@kms_co...@pipe-c-legacy-gamma-reset.html
- shard-skl:  [FAIL][7] ([i915#2964]) -> [FAIL][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9696/shard-skl4/igt@kms_co...@pipe-c-legacy-gamma-reset.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19535/shard-skl1/igt@kms_co...@pipe-c-legacy-gamma-reset.html

  
Known issues


  Here are the changes found in Patchwork_19535_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_persistence@close-replace-race:
- shard-glk:  [PASS][9] -> [TIMEOUT][10] ([i915#2918])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9696/shard-glk3/igt@gem_ctx_persiste...@close-replace-race.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19535/shard-glk3/igt@gem_ctx_persiste...@close-replace-race.html

  * igt@gem_exec_fair@basic-deadline:
- shard-glk:  [PASS][11] -> [FAIL][12] ([i915#2846])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9696/shard-glk2/igt@gem_exec_f...@basic-deadline.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19535/shard-glk2/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-none@rcs0:
- shard-kbl:  [PASS][13] -> [FAIL][14] ([i915#2842])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9696/shard-kbl1/igt@gem_exec_fair@basic-n...@rcs0.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19535/shard-kbl1/igt@gem_exec_fair@basic-n...@rcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][15] -> [FAIL][16] ([i915#2842])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9696/shard-tglb1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19535/shard-tglb1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
- shard-glk:  [PASS][17] -> [FAIL][18] ([i915#2842])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9696/shard-glk4/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19535/shard-glk9/igt@gem_exec_fair@basic-pace-sh...@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-kbl:  NOTRUN -> [FAIL][19] ([i915#2842])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19535/shard-kbl7/igt@gem_exec_fair@basic-pace-s...@rcs0.html

  * igt@gem_exec_fair@basic-pace@vecs0:
- shard-iclb: [PASS][20] -> [FAIL][21] ([i915#2842])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9696/shard-iclb5/igt@gem_exec_fair@basic-p...@vecs0.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19535/shard-iclb7/igt@gem_exec_fair@basic-p...@vecs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][22] -> [FAIL][23] ([i915#2849])
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9696/shard-iclb7/igt@gem_exec_fair@basic-throt...@rcs0.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19535/shard-iclb7/igt@gem_exec_fair@basic-throt...@rcs0.html

  * igt@gem_exec_reloc@basic-many-active@vcs1:
- shard-iclb: NOTRUN -> [FAIL][24] ([i915#2389])
   [24]: 

Re: [Intel-gfx] [PATCH] drm/i915: Add missing -EDEADLK path in execbuffer ggtt pinning.

[Maarten Lankhorst]

Op 29-01-2021 om 14:16 schreef Chris Wilson:
> Quoting Maarten Lankhorst (2021-01-29 13:11:37)
>> In reloc_iomap we swallow the -EDEADLK error, but this needs to
>> be returned for -EDEADLK handling. Add the missing check to
>> make bsw pass again.
> What lock? You already have the pages reserved, why are we not just using
> the earlier reservation.
> -Chris

We start taking locks on the vm ggtt objects, this is going to break with the 
object mm lock removal break. So easiest fix is to add missing -EDEADLK here.

Any pinning operation may fail with -EDEADLK, it's something we should always 
handle.

~Maarten

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Ignore error capturing a closed context

[Patchwork]

== Series Details ==

Series: drm/i915/gt: Ignore error capturing a closed context
URL   : https://patchwork.freedesktop.org/series/86447/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9699 -> Patchwork_19541


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19541/index.html

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_19541:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_flip@basic-flip-vs-modeset@a-edp1:
- {fi-cml-drallion}:  NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19541/fi-cml-drallion/igt@kms_flip@basic-flip-vs-mode...@a-edp1.html

  
Known issues


  Here are the changes found in Patchwork_19541 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@prime_self_import@basic-with_one_bo_two_files:
- fi-tgl-y:   [PASS][2] -> [DMESG-WARN][3] ([i915#402])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9699/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19541/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s0:
- {fi-cml-drallion}:  [INCOMPLETE][4] ([i915#1614]) -> [PASS][5]
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9699/fi-cml-drallion/igt@gem_exec_susp...@basic-s0.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19541/fi-cml-drallion/igt@gem_exec_susp...@basic-s0.html

  * igt@prime_vgem@basic-gtt:
- fi-tgl-y:   [DMESG-WARN][6] ([i915#402]) -> [PASS][7]
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9699/fi-tgl-y/igt@prime_v...@basic-gtt.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19541/fi-tgl-y/igt@prime_v...@basic-gtt.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1614]: https://gitlab.freedesktop.org/drm/intel/issues/1614
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402


Participating hosts (45 -> 40)
--

  Missing(5): fi-jsl-1 fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-bdw-samus 


Build changes
-

  * Linux: CI_DRM_9699 -> Patchwork_19541

  CI-20190529: 20190529
  CI_DRM_9699: 227f6526730330c19bbf781bc59e684ccf373de8 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5978: e1e5b3fea2baafdae0160940ecb8bf0242703840 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_19541: c7f7ce9089990f52885e8d1b8247351049e01a21 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

c7f7ce908999 drm/i915/gt: Ignore error capturing a closed context

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19541/index.html
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[Intel-gfx] [PATCH 1/2] drm/i915/display: Add a intel_pipe_is_enabled() helper

[Hans de Goede]

Factor the code to check if a pipe is currently enabled out of
assert_pipe() and put it in a new intel_pipe_is_enabled() helper,
so that it can be re-used without copy-pasting it.

Signed-off-by: Hans de Goede 
---
 drivers/gpu/drm/i915/display/intel_display.c | 20 ++--
 drivers/gpu/drm/i915/display/intel_display.h |  2 ++
 2 files changed, 16 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 24520f062ff9..f83caceb901b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1263,17 +1263,13 @@ void assert_panel_unlocked(struct drm_i915_private 
*dev_priv, enum pipe pipe)
 pipe_name(pipe));
 }
 
-void assert_pipe(struct drm_i915_private *dev_priv,
-enum transcoder cpu_transcoder, bool state)
+bool intel_pipe_is_enabled(struct drm_i915_private *dev_priv,
+  enum transcoder cpu_transcoder)
 {
bool cur_state;
enum intel_display_power_domain power_domain;
intel_wakeref_t wakeref;
 
-   /* we keep both pipes enabled on 830 */
-   if (IS_I830(dev_priv))
-   state = true;
-
power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
if (wakeref) {
@@ -1285,6 +1281,18 @@ void assert_pipe(struct drm_i915_private *dev_priv,
cur_state = false;
}
 
+   return cur_state;
+}
+
+void assert_pipe(struct drm_i915_private *dev_priv,
+enum transcoder cpu_transcoder, bool state)
+{
+   bool cur_state = intel_pipe_is_enabled(dev_priv, cpu_transcoder);
+
+   /* we keep both pipes enabled on 830 */
+   if (IS_I830(dev_priv))
+   state = true;
+
I915_STATE_WARN(cur_state != state,
"transcoder %s assertion failure (expected %s, current 
%s)\n",
transcoder_name(cpu_transcoder),
diff --git a/drivers/gpu/drm/i915/display/intel_display.h 
b/drivers/gpu/drm/i915/display/intel_display.h
index 5e0d42d82c11..be28d9570038 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -523,6 +523,8 @@ void intel_enable_pipe(const struct intel_crtc_state 
*new_crtc_state);
 void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state);
 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
+bool intel_pipe_is_enabled(struct drm_i915_private *dev_priv,
+  enum transcoder cpu_transcoder);
 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
-- 
2.29.2

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[Intel-gfx] [PATCH 2/2] drm/i915/display: Make vlv_find_free_pps() skip pipes which are in use for non DP purposes

[Hans de Goede]

As explained by a long comment block, on VLV intel_setup_outputs()
sometimes thinks there might be an eDP panel connected while there is none.
In this case intel_setup_outputs() will call intel_dp_init() to check.

In this scenario vlv_find_free_pps() ends up selecting pipe A for the pps,
even though this might be in use for non DP purposes. When this is the case
then the assert_pipe() in vlv_force_pll_on() will fail when called from
vlv_power_sequencer_kick().

This happens on a Voyo winpad A15, leading to the following WARN/backtrace:

[8.661531] [ cut here ]
[8.661590] transcoder A assertion failure (expected off, current on)
[8.661647] WARNING: CPU: 2 PID: 243 at 
drivers/gpu/drm/i915/display/intel_display.c:1288 assert_pipe+0x125/0xc20 [i915]
[8.661822] Modules linked in: i915(E+) mmc_block crct10dif_pclmul 
crc32_pclmul crc32c_intel ghash_clmulni_intel i2c_algo_bit drm_kms_helper cec 
drm drm_privacy_screen_helper video(E) sdhci_acpi sdhci i2c_hid 
pwm_lpss_platform pwm_lpss mmc_core i2c_dev fuse
[8.661944] CPU: 2 PID: 243 Comm: systemd-udevd Tainted: GE 
5.11.0-rc5+ #228
[8.661954] Hardware name: To be filled by O.E.M. To be filled by 
O.E.M./Aptio CRB, BIOS 5.6.5 11/20/2014
[8.661961] RIP: 0010:assert_pipe+0x125/0xc20 [i915]
[8.662050] Code: c7 c2 e5 39 4a c0 74 c9 48 c7 c6 53 3b 4a c0 83 fb 06 77 
0a 89 db 48 8b 34 dd 80 38 45 c0 48 c7 c7 c8 ff 47 c0 e8 13 6c 8f df <0f> 0b e9 
1d ff ff ff 89 db 48 8b 34 dd 80 38 45 c0 eb a0 48 c7 c2
[8.662058] RSP: 0018:a939c0557690 EFLAGS: 00010286
[8.662071] RAX: 0039 RBX:  RCX: 89c67bd19058
[8.662078] RDX: ffd8 RSI: 0027 RDI: 89c67bd19050
[8.662085] RBP: 89c64a3c R08: 0001 R09: 0001
[8.662091] R10: a939c05574c0 R11: a0961248 R12: 0009
[8.662098] R13:  R14: e000 R15: 89c64a3c
[8.662105] FS:  7fe824e42380() GS:89c67bd0() 
knlGS:
[8.662113] CS:  0010 DS:  ES:  CR0: 80050033
[8.662120] CR2: 7fffdc770558 CR3: 000106ab8000 CR4: 001006e0
[8.662127] Call Trace:
[8.662148]  assert_pipe+0xa9e/0xc20 [i915]
[8.662252]  vlv_force_pll_on+0xfb/0x1b0 [i915]
[8.662344]  intel_dp_sync_state+0xd92/0x2e70 [i915]
[8.662448]  intel_dp_sync_state+0x1908/0x2e70 [i915]
[8.662541]  intel_dp_sync_state+0x1a3e/0x2e70 [i915]
[8.662620]  ? recalibrate_cpu_khz+0x10/0x10
[8.662633]  ? ktime_get_with_offset+0xad/0x160
[8.662658]  intel_dp_sync_state+0x1f21/0x2e70 [i915]
[8.662788]  intel_dp_encoder_suspend+0x41f/0x14b0 [i915]
[8.662875]  ? drm_dp_dpcd_access+0x50/0xf0 [drm_kms_helper]
[8.662940]  ? __mutex_lock+0x7e/0x7a0
[8.662950]  ? drm_dp_dpcd_access+0x50/0xf0 [drm_kms_helper]
[8.662982]  ? drm_dp_dpcd_access+0x50/0xf0 [drm_kms_helper]
[8.663025]  intel_dp_encoder_suspend+0xdf3/0x14b0 [i915]
[8.663112]  ? find_held_lock+0x2b/0x80
[8.663132]  drm_dp_dpcd_access+0x62/0xf0 [drm_kms_helper]
[8.663181]  drm_dp_dpcd_read+0xb6/0xf0 [drm_kms_helper]
[8.663223]  drm_dp_read_dpcd_caps+0x20/0x110 [drm_kms_helper]
[8.663262]  intel_dp_init_connector+0x79e/0x1010 [i915]
[8.663366]  intel_dp_init+0x251/0x480 [i915]
[8.663453]  intel_modeset_init_nogem+0x1998/0x1b70 [i915]
[8.663540]  ? intel_pcode_init+0x3b6b/0x5d60 [i915]
[8.663625]  i915_driver_probe+0x5d5/0xcb0 [i915]
[8.663734]  ? drm_privacy_screen_get+0x163/0x1a0 [drm_privacy_screen_helper]
[8.663759]  i915_params_free+0x11a/0x200 [i915]
[8.663830]  ? __pm_runtime_resume+0x58/0x90
[8.663849]  local_pci_probe+0x42/0x80
[8.663869]  pci_device_probe+0xd9/0x190
[8.663892]  really_probe+0xf2/0x440
[8.663915]  driver_probe_device+0xe1/0x150
[8.663930]  device_driver_attach+0xa8/0xb0
[8.663948]  __driver_attach+0x8c/0x150
[8.663957]  ? device_driver_attach+0xb0/0xb0
[8.663966]  ? device_driver_attach+0xb0/0xb0
[8.663979]  bus_for_each_dev+0x67/0x90
[8.663998]  bus_add_driver+0x12e/0x1f0
[8.664015]  driver_register+0x8b/0xe0
[8.664025]  ? 0xc055a000
[8.664039]  init_module+0x62/0x7c [i915]
[8.664127]  do_one_initcall+0x5b/0x2d0
[8.664143]  ? rcu_read_lock_sched_held+0x3f/0x80
[8.664155]  ? kmem_cache_alloc_trace+0x292/0x2c0
[8.664178]  do_init_module+0x5c/0x260
[8.664194]  __do_sys_init_module+0x13d/0x1a0
[8.664247]  do_syscall_64+0x33/0x40
[8.664260]  entry_SYSCALL_64_after_hwframe+0x44/0xa9
[8.664272] RIP: 0033:0x7fe825d9a6be
[8.664284] Code: 48 8b 0d bd 27 0c 00 f7 d8 64 89 01 48 83 c8 ff c3 66 2e 
0f 1f 84 00 00 00 00 00 90 f3 0f 1e fa 49 89 ca b8 af 00 00 00 0f 05 <48> 3d 01 
f0 ff ff 73 01 c3 48 8b 0d 8a 27 0c 00 f7 d8 64 89 01 48
[8.664293] RSP: 002b:7fffdc778028 EFLAGS: 0246 ORIG_RAX: 
00af
[

Re: [Intel-gfx] [PATCH] drm/i915: Add missing -EDEADLK path in execbuffer ggtt pinning.

[Chris Wilson]

Quoting Maarten Lankhorst (2021-01-29 13:11:37)
> In reloc_iomap we swallow the -EDEADLK error, but this needs to
> be returned for -EDEADLK handling. Add the missing check to
> make bsw pass again.

What lock? You already have the pages reserved, why are we not just using
the earlier reservation.
-Chris
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[Intel-gfx] [PATCH] drm/i915: Add missing -EDEADLK path in execbuffer ggtt pinning.

[Maarten Lankhorst]

In reloc_iomap we swallow the -EDEADLK error, but this needs to
be returned for -EDEADLK handling. Add the missing check to
make bsw pass again.

Testcase: gem_exec_fence.basic-await

Signed-off-by: Maarten Lankhorst 
---
 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c 
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 97b0d1134b66..df4f124dc61f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -1209,6 +1209,8 @@ static void *reloc_iomap(struct drm_i915_gem_object *obj,
  PIN_MAPPABLE |
  PIN_NONBLOCK /* 
NOWARN */ |
  PIN_NOEVICT);
+   if (vma == ERR_PTR(-EDEADLK))
+   return vma;
if (IS_ERR(vma)) {
memset(>node, 0, sizeof(cache->node));
mutex_lock(>vm.mutex);
-- 
2.30.0

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[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v3,1/2] drm/i915/hdcp: update cp_irq_count_cached in intel_dp_hdcp2_read_msg()

[Patchwork]

== Series Details ==

Series: series starting with [v3,1/2] drm/i915/hdcp: update cp_irq_count_cached 
in intel_dp_hdcp2_read_msg()
URL   : https://patchwork.freedesktop.org/series/86424/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_9696_full -> Patchwork_19534_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_19534_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_19534_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_19534_full:

### IGT changes ###

 Possible regressions 

  * igt@gem_ctx_persistence@replace@bcs0:
- shard-glk:  [PASS][1] -> [FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9696/shard-glk4/igt@gem_ctx_persistence@repl...@bcs0.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19534/shard-glk9/igt@gem_ctx_persistence@repl...@bcs0.html

  
Known issues


  Here are the changes found in Patchwork_19534_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_persistence@close-replace-race:
- shard-glk:  [PASS][3] -> [TIMEOUT][4] ([i915#2918])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9696/shard-glk3/igt@gem_ctx_persiste...@close-replace-race.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19534/shard-glk9/igt@gem_ctx_persiste...@close-replace-race.html

  * igt@gem_exec_capture@pi@rcs0:
- shard-skl:  [PASS][5] -> [INCOMPLETE][6] ([i915#2369] / 
[i915#2502])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9696/shard-skl7/igt@gem_exec_capture@p...@rcs0.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19534/shard-skl3/igt@gem_exec_capture@p...@rcs0.html

  * igt@gem_exec_fair@basic-deadline:
- shard-glk:  [PASS][7] -> [FAIL][8] ([i915#2846])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9696/shard-glk2/igt@gem_exec_f...@basic-deadline.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19534/shard-glk2/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl:  [PASS][9] -> [FAIL][10] ([i915#2842]) +1 similar issue
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9696/shard-kbl1/igt@gem_exec_fair@basic-n...@vcs0.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19534/shard-kbl2/igt@gem_exec_fair@basic-n...@vcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][11] -> [FAIL][12] ([i915#2842])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9696/shard-tglb1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19534/shard-tglb1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
- shard-kbl:  [PASS][13] -> [SKIP][14] ([fdo#109271])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9696/shard-kbl6/igt@gem_exec_fair@basic-p...@vcs1.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19534/shard-kbl6/igt@gem_exec_fair@basic-p...@vcs1.html

  * igt@gem_exec_fair@basic-pace@vecs0:
- shard-iclb: [PASS][15] -> [FAIL][16] ([i915#2842])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9696/shard-iclb5/igt@gem_exec_fair@basic-p...@vecs0.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19534/shard-iclb3/igt@gem_exec_fair@basic-p...@vecs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][17] -> [FAIL][18] ([i915#2849])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9696/shard-iclb7/igt@gem_exec_fair@basic-throt...@rcs0.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19534/shard-iclb5/igt@gem_exec_fair@basic-throt...@rcs0.html

  * igt@gem_exec_reloc@basic-many-active@vcs1:
- shard-iclb: NOTRUN -> [FAIL][19] ([i915#2389])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19534/shard-iclb4/igt@gem_exec_reloc@basic-many-act...@vcs1.html

  * igt@gem_exec_whisper@basic-contexts-priority-all:
- shard-glk:  [PASS][20] -> [DMESG-WARN][21] ([i915#118] / 
[i915#95])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9696/shard-glk6/igt@gem_exec_whis...@basic-contexts-priority-all.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19534/shard-glk4/igt@gem_exec_whis...@basic-contexts-priority-all.html

  * igt@gem_vm_create@destroy-race:
- shard-tglb: [PASS][22] -> [INCOMPLETE][23] ([i915#2912])
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9696/shard-tglb2/igt@gem_vm_cre...@destroy-race.html
   [23]: 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Restrict the GT clock override to just Icelake

[Patchwork]

== Series Details ==

Series: drm/i915/gt: Restrict the GT clock override to just Icelake
URL   : https://patchwork.freedesktop.org/series/86446/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9699 -> Patchwork_19540


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19540/index.html

Known issues


  Here are the changes found in Patchwork_19540 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_suspend@basic-s3:
- fi-tgl-y:   [PASS][1] -> [DMESG-WARN][2] ([i915#2411] / 
[i915#402])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9699/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19540/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html

  * igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u:   [PASS][3] -> [FAIL][4] ([i915#1161] / [i915#262])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9699/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19540/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html

  * igt@prime_self_import@basic-with_two_bos:
- fi-tgl-y:   [PASS][5] -> [DMESG-WARN][6] ([i915#402]) +1 similar 
issue
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9699/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19540/fi-tgl-y/igt@prime_self_import@basic-with_two_bos.html

  
 Possible fixes 

  * igt@i915_getparams_basic@basic-subslice-total:
- fi-tgl-y:   [DMESG-WARN][7] ([i915#402]) -> [PASS][8] +1 similar 
issue
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9699/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19540/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html

  
  [i915#1161]: https://gitlab.freedesktop.org/drm/intel/issues/1161
  [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
  [i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402


Participating hosts (45 -> 40)
--

  Missing(5): fi-jsl-1 fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-bdw-samus 


Build changes
-

  * Linux: CI_DRM_9699 -> Patchwork_19540

  CI-20190529: 20190529
  CI_DRM_9699: 227f6526730330c19bbf781bc59e684ccf373de8 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5978: e1e5b3fea2baafdae0160940ecb8bf0242703840 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_19540: da19841af02bd42c6b6fd0c204d153f1b5265f0c @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

da19841af02b drm/i915/gt: Restrict the GT clock override to just Icelake

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19540/index.html
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[Intel-gfx] [PATCH] drm/i915/gt: Only trust sseu subslice fuse if it is set

[Chris Wilson]

Since userspace cannot run without any subslices, it seems remarkable
that any system would be configured with all fused off. Ignore the fuse
register if it says 0.

References: https://gitlab.freedesktop.org/drm/intel/-/issues/3022
Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/gt/intel_sseu.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c 
b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 0d9f74aec8fe..99c992db2ce7 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -341,9 +341,10 @@ static void gen9_sseu_info_init(struct intel_gt *gt)
 * The subslice disable field is global, i.e. it applies
 * to each of the enabled slices.
 */
-   subslice_mask = (1 << sseu->max_subslices) - 1;
-   subslice_mask &= ~((fuse2 & GEN9_F2_SS_DIS_MASK) >>
-  GEN9_F2_SS_DIS_SHIFT);
+   subslice_mask = (fuse2 & GEN9_F2_SS_DIS_MASK) >> GEN9_F2_SS_DIS_SHIFT;
+   if (!subslice_mask) /* Ignore the fuse if it says there is no HW */
+   subslice_mask = ~0u;
+   subslice_mask &= GENMASK(sseu->max_subslices - 1, 0);
 
/*
 * Iterate through enabled slices and subslices to
-- 
2.20.1

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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v14,1/2] drm/i915/display: Support PSR Multiple Instances

[Patchwork]

== Series Details ==

Series: series starting with [v14,1/2] drm/i915/display: Support PSR Multiple 
Instances
URL   : https://patchwork.freedesktop.org/series/86445/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9699 -> Patchwork_19539


Summary
---

  **WARNING**

  Minor unknown changes coming with Patchwork_19539 need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_19539, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19539/index.html

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_19539:

### IGT changes ###

 Warnings 

  * igt@kms_psr@primary_mmap_gtt:
- fi-icl-y:   [SKIP][1] ([fdo#110189]) -> [SKIP][2] +3 similar 
issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9699/fi-icl-y/igt@kms_psr@primary_mmap_gtt.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19539/fi-icl-y/igt@kms_psr@primary_mmap_gtt.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_flip@basic-flip-vs-dpms@b-edp1:
- {fi-cml-drallion}:  NOTRUN -> [INCOMPLETE][3]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19539/fi-cml-drallion/igt@kms_flip@basic-flip-vs-d...@b-edp1.html

  * igt@kms_psr@cursor_plane_move:
- {fi-rkl-11500t}:[SKIP][4] ([i915#1072]) -> [SKIP][5] +3 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9699/fi-rkl-11500t/igt@kms_psr@cursor_plane_move.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19539/fi-rkl-11500t/igt@kms_psr@cursor_plane_move.html

  * igt@kms_psr@primary_mmap_gtt:
- {fi-tgl-dsi}:   [SKIP][6] ([fdo#110189]) -> [SKIP][7] +3 similar 
issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9699/fi-tgl-dsi/igt@kms_psr@primary_mmap_gtt.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19539/fi-tgl-dsi/igt@kms_psr@primary_mmap_gtt.html

  * igt@kms_psr@sprite_plane_onoff:
- {fi-ehl-1}: [SKIP][8] ([i915#1072]) -> [SKIP][9] +3 similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9699/fi-ehl-1/igt@kms_psr@sprite_plane_onoff.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19539/fi-ehl-1/igt@kms_psr@sprite_plane_onoff.html

  
Known issues


  Here are the changes found in Patchwork_19539 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_suspend@basic-s3:
- fi-tgl-y:   [PASS][10] -> [DMESG-WARN][11] ([i915#2411] / 
[i915#402])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9699/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19539/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html

  * igt@gem_ringfill@basic-all:
- fi-tgl-y:   [PASS][12] -> [DMESG-WARN][13] ([i915#402]) +1 
similar issue
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9699/fi-tgl-y/igt@gem_ringf...@basic-all.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19539/fi-tgl-y/igt@gem_ringf...@basic-all.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s0:
- {fi-cml-drallion}:  [INCOMPLETE][14] ([i915#1614]) -> [PASS][15]
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9699/fi-cml-drallion/igt@gem_exec_susp...@basic-s0.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19539/fi-cml-drallion/igt@gem_exec_susp...@basic-s0.html

  * igt@i915_getparams_basic@basic-subslice-total:
- fi-tgl-y:   [DMESG-WARN][16] ([i915#402]) -> [PASS][17] +1 
similar issue
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9699/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19539/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html

  
 Warnings 

  * igt@kms_psr@primary_mmap_gtt:
- fi-hsw-4770:[SKIP][18] ([fdo#109271] / [i915#1072]) -> [SKIP][19] 
([fdo#109271]) +3 similar issues
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9699/fi-hsw-4770/igt@kms_psr@primary_mmap_gtt.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19539/fi-hsw-4770/igt@kms_psr@primary_mmap_gtt.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: 

Re: [Intel-gfx] [PATCH] drm/i915/gt: Ignore error capturing a closed context

[Chris Wilson]

Quoting Chris Wilson (2021-01-29 12:06:20)
> To capture a context after a gpu hang, we suspend the request and then
> resume its execution afterwards. If the context is already closed, we
> can assume that no one is interested in the result, but instead we are
> trying to terminate execution quickly as part of a forced-preemption.
> In which case, do not waste time in suspending the request, capturing
> the error, and just cancel it instead.

+ before throwing away the error state
-Chris
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[Intel-gfx] [PATCH] drm/i915/gt: Ignore error capturing a closed context

[Chris Wilson]

To capture a context after a gpu hang, we suspend the request and then
resume its execution afterwards. If the context is already closed, we
can assume that no one is interested in the result, but instead we are
trying to terminate execution quickly as part of a forced-preemption.
In which case, do not waste time in suspending the request, capturing
the error, and just cancel it instead.

Testcase: igt/gem_ctx_persistence/many-contexts
Signed-off-by: Chris Wilson 
---
 .../drm/i915/gt/intel_execlists_submission.c   | 18 +-
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c 
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index e20ab2eab3a8..2280d1bd2c77 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2249,10 +2249,21 @@ static u32 active_ccid(struct intel_engine_cs *engine)
 static void execlists_capture(struct intel_engine_cs *engine)
 {
struct execlists_capture *cap;
+   struct i915_request *rq;
 
if (!IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR))
return;
 
+   rq = active_context(engine, active_ccid(engine));
+
+   /*
+* If the context is closed, assume no one is listening for the
+* associated state; the user is already gone. We can save a lot of
+* time around forced-preemption by just cancelling the guilty request.
+*/
+   if (!rq || intel_context_is_closed(rq->context))
+   return;
+
/*
 * We need to _quickly_ capture the engine state before we reset.
 * We are inside an atomic section (softirq) here and we are delaying
@@ -2262,11 +2273,8 @@ static void execlists_capture(struct intel_engine_cs 
*engine)
if (!cap)
return;
 
-   cap->rq = active_context(engine, active_ccid(engine));
-   if (cap->rq) {
-   cap->rq = active_request(cap->rq->context->timeline, cap->rq);
-   cap->rq = i915_request_get_rcu(cap->rq);
-   }
+   rq = active_request(rq->context->timeline, rq);
+   cap->rq = i915_request_get_rcu(rq);
if (!cap->rq)
goto err_free;
 
-- 
2.20.1

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Re: [Intel-gfx] [PATCH 17/18] drm/i915/display13: Add rc_qp_table for rcparams calculation

[Jani Nikula]

On Fri, 29 Jan 2021, Chris Wilson  wrote:
> Quoting Jani Nikula (2021-01-29 11:12:02)
>> On Thu, 28 Jan 2021, Matt Roper  wrote:
>> > From: Vandita Kulkarni 
>> >
>> > Add the qp table for 444 formats, for 8bpc, 10bpc and 12bpc, as given by
>> > the VESA C model for DSC 1.1
>> >
>> > Cc: Manasi Navare 
>> > Signed-off-by: Vandita Kulkarni 
>> > Signed-off-by: Matt Roper 
>> > ---
>> >  .../gpu/drm/i915/display/intel_qp_tables.h| 294 ++
>> >  drivers/gpu/drm/i915/display/intel_vdsc.c |  22 +-
>> >  2 files changed, 315 insertions(+), 1 deletion(-)
>> >  create mode 100644 drivers/gpu/drm/i915/display/intel_qp_tables.h
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/intel_qp_tables.h 
>> > b/drivers/gpu/drm/i915/display/intel_qp_tables.h
>> > new file mode 100644
>> > index ..13694d5220d4
>> > --- /dev/null
>> > +++ b/drivers/gpu/drm/i915/display/intel_qp_tables.h
>> > @@ -0,0 +1,294 @@
>> > +/* SPDX-License-Identifier: MIT */
>> > +/*
>> > + * Copyright © 2019 Intel Corporation
>> > + */
>> > +
>> 
>> The include guard is missing.
>
> Should we even be putting large tables into a header?
>
> Would this be better as a .c?

Agreed.

BR,
Jani.

-- 
Jani Nikula, Intel Open Source Graphics Center
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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v14,1/2] drm/i915/display: Support PSR Multiple Instances

[Patchwork]

== Series Details ==

Series: series starting with [v14,1/2] drm/i915/display: Support PSR Multiple 
Instances
URL   : https://patchwork.freedesktop.org/series/86445/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1327:5: warning: context imbalance in 
'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gvt/mmio.c:295:23: warning: memcpy with byte count of 
279040
+drivers/gpu/drm/i915/i915_perf.c:1450:15: warning: memset with byte count of 
16777216
+drivers/gpu/drm/i915/i915_perf.c:1504:15: warning: memset with byte count of 
16777216
+drivers/gpu/drm/i915/intel_wakeref.c:137:19: warning: context imbalance in 
'wakeref_auto_timeout' - unexpected unlock
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' 
- different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' 
- different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' 
- different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - 
different lock contexts for basic 

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v14,1/2] drm/i915/display: Support PSR Multiple Instances

[Patchwork]

== Series Details ==

Series: series starting with [v14,1/2] drm/i915/display: Support PSR Multiple 
Instances
URL   : https://patchwork.freedesktop.org/series/86445/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
e7df7e13f87c drm/i915/display: Support PSR Multiple Instances
-:88: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in 
parentheses
#88: FILE: drivers/gpu/drm/i915/display/intel_display.h:420:
+#define for_each_intel_encoder_mask_can_psr(dev, intel_encoder, encoder_mask) \
+   list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, 
base.head) \
+   for_each_if(((encoder_mask) & 
drm_encoder_mask(&(intel_encoder)->base)) && \
+   intel_encoder_can_psr(intel_encoder))

-:88: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'intel_encoder' - possible 
side-effects?
#88: FILE: drivers/gpu/drm/i915/display/intel_display.h:420:
+#define for_each_intel_encoder_mask_can_psr(dev, intel_encoder, encoder_mask) \
+   list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, 
base.head) \
+   for_each_if(((encoder_mask) & 
drm_encoder_mask(&(intel_encoder)->base)) && \
+   intel_encoder_can_psr(intel_encoder))

-:97: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in 
parentheses
#97: FILE: drivers/gpu/drm/i915/display/intel_display.h:429:
+#define for_each_intel_encoder_can_psr(dev, intel_encoder) \
+   for_each_intel_encoder((dev), (intel_encoder)) \
+   for_each_if(intel_encoder_can_psr(intel_encoder))

-:97: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'intel_encoder' - possible 
side-effects?
#97: FILE: drivers/gpu/drm/i915/display/intel_display.h:429:
+#define for_each_intel_encoder_can_psr(dev, intel_encoder) \
+   for_each_intel_encoder((dev), (intel_encoder)) \
+   for_each_if(intel_encoder_can_psr(intel_encoder))

-:375: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'intel_dp' - possible 
side-effects?
#375: FILE: drivers/gpu/drm/i915/display/intel_display_types.h:1795:
+#define CAN_PSR(intel_dp)  (HAS_PSR(dp_to_i915(intel_dp)) && \
+(intel_dp)->psr.sink_support && \
+(intel_dp)->psr.source_support)

total: 2 errors, 0 warnings, 3 checks, 1730 lines checked
02d0fee29897 drm/i915/display: Support Multiple Transcoders' PSR status on 
debugfs


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Re: [Intel-gfx] [PATCH v7 13/63] drm/i915: Reject more ioctls for userptr

[Maarten Lankhorst]

Op 28-01-2021 om 17:47 schreef Jason Ekstrand:
> On Thu, Jan 28, 2021 at 10:26 AM Maarten Lankhorst
>  wrote:
>> There are a couple of ioctl's related to tiling and cache placement,
>> that make no sense for userptr, reject those:
>> - i915_gem_set_tiling_ioctl()
>> Tiling should always be linear for userptr. Changing placement will
>> fail with -ENXIO.
>> - i915_gem_set_caching_ioctl()
>> Userptr memory should always be cached. Changing caching mode will
>> fail with -ENXIO.
>> - i915_gem_set_domain_ioctl()
>> Changed to be equivalent to gem_wait, which is correct for the
>> cached linear userptr pointers. This is required because we
>> cannot grab a reference to the pages in the rework, but waiting
>> for idle will do the same.
>>
>> This plus the previous changes have been tested against beignet
>> by using its own unit tests, and intel-video-compute by using
>> piglit's opencl tests.
> Did you test against mesa at all?

I tested it and also looked at the code for manual inspection.

Unfortunately rechecking one more time, it seems I missed bo_alloc_internal in 
mesa. Fortunately it seems not to be capable of allocating userptr.

As far as I can tell, that means the changes to mesa are safe.

I tried to run parts of the vulkan cts as well, but it crashed after a while 
against my distro's vulkan package for non userptr related reasons.

~Maarten

>> Signed-off-by: Maarten Lankhorst 
>> Reviewed-by: Thomas Hellström 
>> Cc: Jason Ekstrand 
>>
>> -- Still needs an ack from relevant userspace that it won't break, but 
>> should be good.
>> ---
>>  drivers/gpu/drm/i915/display/intel_display.c |  2 +-
>>  drivers/gpu/drm/i915/gem/i915_gem_domain.c   | 12 ++--
>>  drivers/gpu/drm/i915/gem/i915_gem_object.h   |  6 ++
>>  drivers/gpu/drm/i915/gem/i915_gem_userptr.c  |  3 ++-
>>  4 files changed, 19 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
>> b/drivers/gpu/drm/i915/display/intel_display.c
>> index d013b0fab128..3e24db8b9ad6 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -14172,7 +14172,7 @@ static int 
>> intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
>> struct drm_i915_gem_object *obj = intel_fb_obj(fb);
>> struct drm_i915_private *i915 = to_i915(obj->base.dev);
>>
>> -   if (obj->userptr.mm) {
>> +   if (i915_gem_object_is_userptr(obj)) {
>> drm_dbg(>drm,
>> "attempting to use a userptr for a framebuffer, 
>> denied\n");
>> return -EINVAL;
>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c 
>> b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
>> index 36f54cedaaeb..3078e9a09f70 100644
>> --- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
>> @@ -335,7 +335,13 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, 
>> void *data,
>>  * not allowed to be changed by userspace.
>>  */
>> if (i915_gem_object_is_proxy(obj)) {
>> -   ret = -ENXIO;
>> +   /*
>> +* Silently allow cached for userptr; the vulkan driver
>> +* sets all objects to cached
>> +*/
>> +   if (!i915_gem_object_is_userptr(obj) ||
>> +   args->caching != I915_CACHING_CACHED)
> Thanks for looking out for this case.  I just double-checked and, yes,
> we set caching on userptr but we always set it to CACHED so this
> should take care of us, assuming it does what it looks like it does.
>
> Acked-by: Jason Ekstrand 
>
>> +   ret = -ENXIO;
>> goto out;
>> }
>>
>> @@ -533,7 +539,9 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void 
>> *data,
>>  * considered to be outside of any cache domain.
>>  */
>> if (i915_gem_object_is_proxy(obj)) {
>> -   err = -ENXIO;
>> +   /* silently allow userptr to complete */
>> +   if (!i915_gem_object_is_userptr(obj))
>> +   err = -ENXIO;
>> goto out;
>> }
>>
>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h 
>> b/drivers/gpu/drm/i915/gem/i915_gem_object.h
>> index e9a8ee96d64c..3f300a1d27ba 100644
>> --- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
>> @@ -574,6 +574,12 @@ void __i915_gem_object_flush_frontbuffer(struct 
>> drm_i915_gem_object *obj,
>>  void __i915_gem_object_invalidate_frontbuffer(struct drm_i915_gem_object 
>> *obj,
>>   enum fb_op_origin origin);
>>
>> +static inline bool
>> +i915_gem_object_is_userptr(struct drm_i915_gem_object *obj)
>> +{
>> +   return obj->userptr.mm;
>> +}
>> +
>>  static inline void
>>  i915_gem_object_flush_frontbuffer(struct drm_i915_gem_object *obj,
>>   

[Intel-gfx] [PATCH] drm/i915/gt: Restrict the GT clock override to just Icelake

[Chris Wilson]

It appears that Elkhart Lake uses the same clock for CTX_TIMESTAMP as
CS_TIMESTAMP, leaving Icelake as the odd one out.

Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/3024
Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c 
b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
index f8c79efb1a87..09b290fe0867 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
@@ -160,7 +160,7 @@ void intel_gt_init_clock_frequency(struct intel_gt *gt)
gt->clock_period_ns = intel_gt_clock_interval_to_ns(gt, 1);
 
/* Icelake appears to use another fixed frequency for CTX_TIMESTAMP */
-   if (IS_GEN(gt->i915, 11))
+   if (IS_ICELAKE(gt->i915))
gt->clock_period_ns = NSEC_PER_SEC / 1375;
 
GT_TRACE(gt,
-- 
2.20.1

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[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/5] drm/i915: Skip vswing programming for TBT (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [1/5] drm/i915: Skip vswing programming for TBT 
(rev2)
URL   : https://patchwork.freedesktop.org/series/86402/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9695_full -> Patchwork_19532_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Known issues


  Here are the changes found in Patchwork_19532_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@feature_discovery@psr2:
- shard-iclb: NOTRUN -> [SKIP][1] ([i915#658]) +1 similar issue
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19532/shard-iclb1/igt@feature_discov...@psr2.html

  * igt@gem_ctx_persistence@replace@rcs0:
- shard-skl:  [PASS][2] -> [FAIL][3] ([i915#2410])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9695/shard-skl6/igt@gem_ctx_persistence@repl...@rcs0.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19532/shard-skl7/igt@gem_ctx_persistence@repl...@rcs0.html

  * igt@gem_exec_fair@basic-deadline:
- shard-glk:  [PASS][4] -> [FAIL][5] ([i915#2846])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9695/shard-glk9/igt@gem_exec_f...@basic-deadline.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19532/shard-glk9/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-pace@vcs0:
- shard-kbl:  [PASS][6] -> [FAIL][7] ([i915#2842])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9695/shard-kbl1/igt@gem_exec_fair@basic-p...@vcs0.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19532/shard-kbl2/igt@gem_exec_fair@basic-p...@vcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][8] ([i915#2842])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19532/shard-iclb4/igt@gem_exec_fair@basic-p...@vcs1.html

  * igt@gem_exec_whisper@basic-contexts-priority-all:
- shard-glk:  [PASS][9] -> [DMESG-WARN][10] ([i915#118] / [i915#95])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9695/shard-glk2/igt@gem_exec_whis...@basic-contexts-priority-all.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19532/shard-glk1/igt@gem_exec_whis...@basic-contexts-priority-all.html

  * igt@i915_pm_rpm@modeset-non-lpsp:
- shard-iclb: NOTRUN -> [SKIP][11] ([fdo#110892])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19532/shard-iclb1/igt@i915_pm_...@modeset-non-lpsp.html

  * igt@i915_suspend@sysfs-reader:
- shard-kbl:  [PASS][12] -> [DMESG-WARN][13] ([i915#180])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9695/shard-kbl4/igt@i915_susp...@sysfs-reader.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19532/shard-kbl6/igt@i915_susp...@sysfs-reader.html

  * igt@kms_async_flips@alternate-sync-async-flip:
- shard-skl:  [PASS][14] -> [FAIL][15] ([i915#2521])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9695/shard-skl3/igt@kms_async_fl...@alternate-sync-async-flip.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19532/shard-skl4/igt@kms_async_fl...@alternate-sync-async-flip.html

  * igt@kms_atomic_transition@plane-all-modeset-transition:
- shard-iclb: NOTRUN -> [SKIP][16] ([i915#1769])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19532/shard-iclb1/igt@kms_atomic_transit...@plane-all-modeset-transition.html

  * igt@kms_big_fb@yf-tiled-8bpp-rotate-270:
- shard-iclb: NOTRUN -> [SKIP][17] ([fdo#110723]) +1 similar issue
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19532/shard-iclb1/igt@kms_big...@yf-tiled-8bpp-rotate-270.html

  * igt@kms_color@pipe-a-degamma:
- shard-iclb: NOTRUN -> [FAIL][18] ([i915#1149])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19532/shard-iclb1/igt@kms_co...@pipe-a-degamma.html

  * igt@kms_color_chamelium@pipe-b-gamma:
- shard-iclb: NOTRUN -> [SKIP][19] ([fdo#109284] / [fdo#111827])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19532/shard-iclb1/igt@kms_color_chamel...@pipe-b-gamma.html

  * igt@kms_cursor_crc@pipe-a-cursor-256x256-random:
- shard-kbl:  [PASS][20] -> [FAIL][21] ([i915#54])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9695/shard-kbl1/igt@kms_cursor_...@pipe-a-cursor-256x256-random.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19532/shard-kbl4/igt@kms_cursor_...@pipe-a-cursor-256x256-random.html
- shard-glk:  [PASS][22] -> [FAIL][23] ([i915#54])
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9695/shard-glk1/igt@kms_cursor_...@pipe-a-cursor-256x256-random.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19532/shard-glk2/igt@kms_cursor_...@pipe-a-cursor-256x256-random.html
- shard-apl:  [PASS][24] -> [FAIL][25] ([i915#54])
   

[Intel-gfx] [PATCH v14 2/2] drm/i915/display: Support Multiple Transcoders' PSR status on debugfs

[Gwan-gyeong Mun]

In order to support the PSR state of each transcoder, it adds
i915_psr_status to sub-directory of each transcoder.

v2: Change using of Symbolic permissions 'S_IRUGO' to using of octal
permissions '0444'
v5: Addressed JJani Nikula's review comments
 - Remove checking of Gen12 for i915_psr_status.
 - Add check of HAS_PSR()
 - Remove meaningless check routine.

Signed-off-by: Gwan-gyeong Mun 
Cc: José Roberto de Souza 
Cc: Jani Nikula 
Cc: Anshuman Gupta 
Reviewed-by: Anshuman Gupta 
---
 .../gpu/drm/i915/display/intel_display_debugfs.c | 16 
 1 file changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c 
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index b1bda1f5ef16..d6e4a9237bda 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -2211,6 +2211,16 @@ static int i915_hdcp_sink_capability_show(struct 
seq_file *m, void *data)
 }
 DEFINE_SHOW_ATTRIBUTE(i915_hdcp_sink_capability);
 
+static int i915_psr_status_show(struct seq_file *m, void *data)
+{
+   struct drm_connector *connector = m->private;
+   struct intel_dp *intel_dp =
+   intel_attached_dp(to_intel_connector(connector));
+
+   return intel_psr_status(m, intel_dp);
+}
+DEFINE_SHOW_ATTRIBUTE(i915_psr_status);
+
 #define LPSP_CAPABLE(COND) (COND ? seq_puts(m, "LPSP: capable\n") : \
seq_puts(m, "LPSP: incapable\n"))
 
@@ -2386,6 +2396,12 @@ int intel_connector_debugfs_add(struct drm_connector 
*connector)
connector, _psr_sink_status_fops);
}
 
+   if (HAS_PSR(dev_priv) &&
+   connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
+   debugfs_create_file("i915_psr_status", 0444, root,
+   connector, _psr_status_fops);
+   }
+
if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) {
-- 
2.30.0

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[Intel-gfx] [PATCH v14 1/2] drm/i915/display: Support PSR Multiple Instances

[Gwan-gyeong Mun]

It is a preliminary work for supporting multiple EDP PSR and
DP PanelReplay. And it refactors singleton PSR to Multi Transcoder
supportable PSR.
And this moves and renames the i915_psr structure of drm_i915_private's to
intel_dp's intel_psr structure.
It also causes changes in PSR interrupt handling routine for supporting
multiple transcoders. But it does not change the scenario and timing of
enabling and disabling PSR. And it not support multiple pipes with
a single transcoder PSR case yet.

v2: Fix indentation and add comments
v3: Remove Blank line
v4: Rebased
v5: Rebased and Addressed Anshuman's review comment.
- Move calling of intel_psr_init() to intel_dp_init_connector()
v6: Address Anshuman's review comments
   - Remove wrong comments and add comments for a limit of supporting of
 a single pipe PSR
v7: Update intel_psr_compute_config() for supporting multiple transcoder
PSR on BDW+
v8: Address Anshuman's review comments
   - Replace DRM_DEBUG_KMS with drm_dbg_kms() / DRM_WARN with drm_warn()
v9: Fix commit message
v10: Rebased
v11: Address Jose's review comment.
  - Reorder calling order of intel_psr2_program_trans_man_trk_ctl().
  - In order to reduce changes keep the old name for drm_i915_private.
  - Change restrictions of multiple instances of PSR.
v12: Address Jose's review comment.
  - Change the calling of intel_psr2_program_trans_man_trk_ctl() into
commit_pipe_config().
  - Change a checking order of CAN_PSR() and connector_status to original
on i915_psr_sink_status_show().
  - Drop unneeded intel_dp_update_pipe() function.
  - In order to wait a specific encoder which belong to crtc_state on
intel_psr_wait_for_idle(), add checking of encoder.
  - Add an whitespace to comments.
v13: Rebased and Address Jose's review comment.
  - Add and use for_each_intel_psr_enabled_encoder() macro.
  - In order to use correct frontbuffer_bit for each pipe,
fix intel_psr_invalidate() and intel_psr_flush().
  - Remove redundant or unneeded codes.
  - Update comments.
v14: Address Jose's review comment
  - Add and use for_each_intel_encoder_can_psr() macro and
for_each_intel_encoder_mask_can_psr() macro.
  - Add source_support member variable into intel_psr structure.
  - Update CAN_PSR() macro that checks source_support.
  - Move encoder's PSR availity check to psr_init() from
psr_compute_config().
  - Remove redundant or unneeded codes.

Signed-off-by: Gwan-gyeong Mun 
Cc: José Roberto de Souza 
Cc: Juha-Pekka Heikkila 
Cc: Anshuman Gupta 
Reviewed-by: Anshuman Gupta 
---
 drivers/gpu/drm/i915/display/intel_display.c  |   2 -
 drivers/gpu/drm/i915/display/intel_display.h  |   9 +
 .../drm/i915/display/intel_display_debugfs.c  |  95 ++-
 .../drm/i915/display/intel_display_types.h|  51 ++
 drivers/gpu/drm/i915/display/intel_dp.c   |  10 +-
 drivers/gpu/drm/i915/display/intel_psr.c  | 604 ++
 drivers/gpu/drm/i915/display/intel_psr.h  |  10 +-
 drivers/gpu/drm/i915/display/intel_sprite.c   |   6 +-
 drivers/gpu/drm/i915/i915_drv.h   |  38 --
 drivers/gpu/drm/i915/i915_irq.c   |  42 +-
 10 files changed, 491 insertions(+), 376 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index d013b0fab128..163a2c4eb313 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14141,8 +14141,6 @@ static void intel_setup_outputs(struct drm_i915_private 
*dev_priv)
intel_dvo_init(dev_priv);
}
 
-   intel_psr_init(dev_priv);
-
for_each_intel_encoder(_priv->drm, encoder) {
encoder->base.possible_crtcs =
intel_encoder_possible_crtcs(encoder);
diff --git a/drivers/gpu/drm/i915/display/intel_display.h 
b/drivers/gpu/drm/i915/display/intel_display.h
index 64ffa34544a7..c72e41b61349 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -417,10 +417,19 @@ enum phy_fia {
for_each_if((encoder_mask) &\
drm_encoder_mask(_encoder->base))
 
+#define for_each_intel_encoder_mask_can_psr(dev, intel_encoder, encoder_mask) \
+   list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, 
base.head) \
+   for_each_if(((encoder_mask) & 
drm_encoder_mask(&(intel_encoder)->base)) && \
+   intel_encoder_can_psr(intel_encoder))
+
 #define for_each_intel_dp(dev, intel_encoder)  \
for_each_intel_encoder(dev, intel_encoder)  \
for_each_if(intel_encoder_is_dp(intel_encoder))
 
+#define for_each_intel_encoder_can_psr(dev, intel_encoder) \
+   for_each_intel_encoder((dev), (intel_encoder)) \
+   for_each_if(intel_encoder_can_psr(intel_encoder))
+
 #define for_each_intel_connector_iter(intel_connector, iter) \
while 

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,1/3] drm/i915: Nuke not needed members of dram_info

[Patchwork]

== Series Details ==

Series: series starting with [CI,1/3] drm/i915: Nuke not needed members of 
dram_info
URL   : https://patchwork.freedesktop.org/series/86404/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9695_full -> Patchwork_19531_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Known issues


  Here are the changes found in Patchwork_19531_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@feature_discovery@psr2:
- shard-iclb: NOTRUN -> [SKIP][1] ([i915#658]) +1 similar issue
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19531/shard-iclb1/igt@feature_discov...@psr2.html

  * igt@gem_ctx_persistence@close-replace-race:
- shard-kbl:  [PASS][2] -> [TIMEOUT][3] ([i915#2918])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9695/shard-kbl2/igt@gem_ctx_persiste...@close-replace-race.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19531/shard-kbl7/igt@gem_ctx_persiste...@close-replace-race.html

  * igt@gem_exec_capture@pi@rcs0:
- shard-skl:  [PASS][4] -> [INCOMPLETE][5] ([i915#2369] / 
[i915#2502])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9695/shard-skl2/igt@gem_exec_capture@p...@rcs0.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19531/shard-skl3/igt@gem_exec_capture@p...@rcs0.html

  * igt@gem_exec_fair@basic-deadline:
- shard-glk:  [PASS][6] -> [FAIL][7] ([i915#2846])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9695/shard-glk9/igt@gem_exec_f...@basic-deadline.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19531/shard-glk6/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][8] ([i915#2842]) +1 similar issue
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19531/shard-iclb4/igt@gem_exec_fair@basic-p...@vcs1.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk:  [PASS][9] -> [FAIL][10] ([i915#2842])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9695/shard-glk3/igt@gem_exec_fair@basic-throt...@rcs0.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19531/shard-glk3/igt@gem_exec_fair@basic-throt...@rcs0.html

  * igt@gem_exec_whisper@basic-fds-forked:
- shard-glk:  [PASS][11] -> [DMESG-WARN][12] ([i915#118] / 
[i915#95])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9695/shard-glk8/igt@gem_exec_whis...@basic-fds-forked.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19531/shard-glk7/igt@gem_exec_whis...@basic-fds-forked.html

  * igt@gem_readwrite@beyond-eob:
- shard-skl:  [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) +2 
similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9695/shard-skl1/igt@gem_readwr...@beyond-eob.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19531/shard-skl8/igt@gem_readwr...@beyond-eob.html

  * igt@gen9_exec_parse@bb-large:
- shard-apl:  [PASS][15] -> [TIMEOUT][16] ([i915#2502])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9695/shard-apl3/igt@gen9_exec_pa...@bb-large.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19531/shard-apl2/igt@gen9_exec_pa...@bb-large.html

  * igt@i915_pm_dc@dc6-psr:
- shard-iclb: NOTRUN -> [FAIL][17] ([i915#454])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19531/shard-iclb1/igt@i915_pm...@dc6-psr.html

  * igt@i915_pm_rpm@modeset-non-lpsp:
- shard-iclb: NOTRUN -> [SKIP][18] ([fdo#110892])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19531/shard-iclb1/igt@i915_pm_...@modeset-non-lpsp.html

  * igt@kms_async_flips@test-time-stamp:
- shard-tglb: [PASS][19] -> [FAIL][20] ([i915#2597])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9695/shard-tglb1/igt@kms_async_fl...@test-time-stamp.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19531/shard-tglb3/igt@kms_async_fl...@test-time-stamp.html

  * igt@kms_atomic_transition@plane-all-modeset-transition:
- shard-iclb: NOTRUN -> [SKIP][21] ([i915#1769])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19531/shard-iclb1/igt@kms_atomic_transit...@plane-all-modeset-transition.html

  * igt@kms_big_fb@yf-tiled-8bpp-rotate-270:
- shard-iclb: NOTRUN -> [SKIP][22] ([fdo#110723]) +1 similar issue
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19531/shard-iclb1/igt@kms_big...@yf-tiled-8bpp-rotate-270.html

  * igt@kms_color@pipe-a-degamma:
- shard-iclb: NOTRUN -> [FAIL][23] ([i915#1149])
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19531/shard-iclb1/igt@kms_co...@pipe-a-degamma.html

  * igt@kms_color_chamelium@pipe-b-gamma:
- shard-iclb: NOTRUN -> [SKIP][24] ([fdo#109284] / [fdo#111827])
   [24]: 

Re: [Intel-gfx] [PATCH 17/18] drm/i915/display13: Add rc_qp_table for rcparams calculation

[Chris Wilson]

Quoting Jani Nikula (2021-01-29 11:12:02)
> On Thu, 28 Jan 2021, Matt Roper  wrote:
> > From: Vandita Kulkarni 
> >
> > Add the qp table for 444 formats, for 8bpc, 10bpc and 12bpc, as given by
> > the VESA C model for DSC 1.1
> >
> > Cc: Manasi Navare 
> > Signed-off-by: Vandita Kulkarni 
> > Signed-off-by: Matt Roper 
> > ---
> >  .../gpu/drm/i915/display/intel_qp_tables.h| 294 ++
> >  drivers/gpu/drm/i915/display/intel_vdsc.c |  22 +-
> >  2 files changed, 315 insertions(+), 1 deletion(-)
> >  create mode 100644 drivers/gpu/drm/i915/display/intel_qp_tables.h
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_qp_tables.h 
> > b/drivers/gpu/drm/i915/display/intel_qp_tables.h
> > new file mode 100644
> > index ..13694d5220d4
> > --- /dev/null
> > +++ b/drivers/gpu/drm/i915/display/intel_qp_tables.h
> > @@ -0,0 +1,294 @@
> > +/* SPDX-License-Identifier: MIT */
> > +/*
> > + * Copyright © 2019 Intel Corporation
> > + */
> > +
> 
> The include guard is missing.

Should we even be putting large tables into a header?

Would this be better as a .c?
-Chris
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Re: [Intel-gfx] [PATCH 17/18] drm/i915/display13: Add rc_qp_table for rcparams calculation

[Jani Nikula]

On Thu, 28 Jan 2021, Matt Roper  wrote:
> From: Vandita Kulkarni 
>
> Add the qp table for 444 formats, for 8bpc, 10bpc and 12bpc, as given by
> the VESA C model for DSC 1.1
>
> Cc: Manasi Navare 
> Signed-off-by: Vandita Kulkarni 
> Signed-off-by: Matt Roper 
> ---
>  .../gpu/drm/i915/display/intel_qp_tables.h| 294 ++
>  drivers/gpu/drm/i915/display/intel_vdsc.c |  22 +-
>  2 files changed, 315 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/gpu/drm/i915/display/intel_qp_tables.h
>
> diff --git a/drivers/gpu/drm/i915/display/intel_qp_tables.h 
> b/drivers/gpu/drm/i915/display/intel_qp_tables.h
> new file mode 100644
> index ..13694d5220d4
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_qp_tables.h
> @@ -0,0 +1,294 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2019 Intel Corporation
> + */
> +

The include guard is missing.

BR,
Jani.

> +#include 
> +
> +#define RC_RANGE_QP(min_max, bpp, row, col) \
> + rc_range_##min_max##qp444_##bpp##bpc[row][col]
> +
> +#ifndef DSC_NUM_BUF_RANGES
> +#define DSC_NUM_BUF_RANGES   15
> +#endif
> +
> +/* from BPP 6 to 24 in steps of 0.5 */
> +#define RC_RANGE_QP444_8BPC_MAX_NUM_BPP  37
> +
> +/* from BPP 6 to 30 in steps of 0.5 */
> +#define RC_RANGE_QP444_10BPC_MAX_NUM_BPP 49
> +
> +/* from BPP 6 to 36 in steps of 0.5 */
> +#define RC_RANGE_QP444_12BPC_MAX_NUM_BPP 61
> +
> +/*
> + * These qp tables are as per the C model
> + * and it has the rows pointing to bpps which increment
> + * in steps of 0.5
> + * We do not support fractional bpps as of today,
> + * hence we would skip the fractional bpps during
> + * our references for qp calclulations.
> + */
> +__maybe_unused
> +static const u8 
> rc_range_minqp444_8bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_8BPC_MAX_NUM_BPP] = 
> {
> + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
> +   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
> + { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
> +   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
> + { 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0,
> +   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
> + { 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,
> +   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
> + { 5, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1,
> +   1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
> + { 5, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1,
> +   1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 },
> + { 5, 5, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1,
> +   1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 },
> + { 5, 5, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2,
> +   2, 2, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0 },
> + { 5, 5, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2,
> +   2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0 },
> + { 6, 5, 5, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
> +   3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0 },
> + { 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3,
> +   3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 0 },
> + { 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4,
> +   4, 4, 4, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 0 },
> + { 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4,
> +   4, 4, 4, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 0 },
> + { 9, 9, 9, 9, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 5,
> +   5, 5, 5, 4, 4, 3, 3, 3, 3, 2, 2, 1, 1, 1 },
> + { 14, 14, 13, 13, 12, 12, 12, 12, 11, 11, 10, 10, 10, 10, 9, 9, 9, 8, 8,
> +   8, 7, 7, 7, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 3, 3, 3, 3 }
> +};
> +
> +__maybe_unused
> +static const u8 
> rc_range_maxqp444_8bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_8BPC_MAX_NUM_BPP] = 
> {
> + { 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 0, 0, 0, 0, 0, 0,
> +   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
> + { 6, 6, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1,
> +   1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0 },
> + { 8, 7, 7, 6, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 3, 2, 2, 1, 1, 1, 1, 1,
> +   1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0 },
> + { 8, 8, 7, 7, 6, 6, 6, 6, 6, 6, 6, 6, 5, 5, 5, 4, 3, 3, 2, 2, 2, 2, 2,
> +   2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0 },
> + { 9, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 5, 4, 4, 3, 2, 2, 2, 2, 2,
> +   2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 0 },
> + { 9, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 6, 5, 4, 4, 3, 3, 3, 3, 3,
> +   3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1 },
> + { 9, 9, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 5, 4, 4, 3, 3, 3, 3, 3,
> +   3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1 },
> + { 10, 10, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 8, 7, 7, 6, 5, 5, 

Re: [Intel-gfx] [PATCH 20/41] drm/i915: Replace priolist rbtree with a skiplist

[Chris Wilson]

Quoting Matthew Brost (2021-01-28 22:56:04)
> On Mon, Jan 25, 2021 at 02:01:15PM +, Chris Wilson wrote:
> > Replace the priolist rbtree with a skiplist. The crucial difference is
> > that walking and removing the first element of a skiplist is O(1), but
> > O(lgN) for an rbtree, as we need to rebalance on remove. This is a
> > hindrance for submission latency as it occurs between picking a request
> > for the priolist and submitting it to hardware, as well effectively
> > trippling the number of O(lgN) operations required under the irqoff lock.
> > This is critical to reducing the latency jitter with multiple clients.
> > 
> > The downsides to skiplists are that lookup/insertion is only
> > probablistically O(lgN) and there is a significant memory penalty to
> > as each skip node is larger than the rbtree equivalent. Furthermore, we
> > don't use dynamic arrays for the skiplist, so the allocation is fixed,
> > and imposes an upper bound on the scalability wrt to the number of
> > inflight requests.
> > 
> 
> This is a fun data structure but IMO might be overkill to maintain this
> code in the i915. The UMDs have effectively agreed to use only 3 levels,
> is O(lgN) where N == 3 really a big deal? With GuC submission we will
> statically map all user levels into 3 buckets. If we are doing that, do
> we even need a complex data structure? i.e. Could use just use can
> array of linked lists?

Because we need to scale the bst to handle a unqiue key per request with
thousands of requests [this is not only about priorities]. And as you
will see from the results, even with just a single priority in the system
(so one entry in either the skiplist or rbtree), the skiplist is beating 
the rbtree as measured by the lock hold time around insert/dequeue of
requests. That surprised me.
-Chris
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Re: [Intel-gfx] [PATCH 20/41] drm/i915: Replace priolist rbtree with a skiplist

[Chris Wilson]

Quoting Tvrtko Ursulin (2021-01-29 09:37:27)
> 
> On 28/01/2021 16:26, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2021-01-28 15:56:19)
> 
> >>> -static void assert_priolists(struct i915_sched_engine * const se)
> >>> -{
> >>> - struct rb_node *rb;
> >>> - long last_prio;
> >>> -
> >>> - if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
> >>> - return;
> >>> -
> >>> - GEM_BUG_ON(rb_first_cached(>queue) !=
> >>> -rb_first(>queue.rb_root));
> >>> -
> >>> - last_prio = INT_MAX;
> >>> - for (rb = rb_first_cached(>queue); rb; rb = rb_next(rb)) {
> >>> - const struct i915_priolist *p = to_priolist(rb);
> >>> -
> >>> - GEM_BUG_ON(p->priority > last_prio);
> >>> - last_prio = p->priority;
> >>> - }
> >>> + root->prng = next_pseudo_random32(root->prng);
> >>> + return  __ffs(root->prng) / 2;
> >>
> >> Where is the relationship to I915_PRIOLIST_HEIGHT? Feels root->prng %
> >> I915_PRIOLIST_HEIGHT would be more obvious here unless I am terribly
> >> mistaken. Or at least put a comment saying why the hack.
> > 
> > HEIGHT is the maximum possible for our struct. skiplists only want to
> > increment the height of the tree one step at a time. So we choose a level
> > with decreasing probability, and then limit that to the maximum height of
> > the current tree + 1, clamped to HEIGHT.
> > 
> > You might notice that unlike traditional skiplists, this uses a
> > probability of 0.25 for each additional level. A neat trick discovered by
> > Con Kolivas (I haven't found it mentioned elsewhere) as the cost of the
> > extra level (using P=.5) is the same as the extra chain length with
> > P=.25. So you can scale to higher number of requests by packing more
> > requests into each level.
> > 
> > So that is split between randomly choosing a level and then working out
> > the height of the node.
> 
> Choosing levels with decreasing probability by the virtue of using ffs 
> on a random number? Or because (BITS_PER_TYPE(u32) / 2) is greater than 
> I915_PRIOLIST_HEIGHT?

/*
 * Given a uniform distribution of random numbers over the u32, then
 * the probability each bit is unset is P=0.5. The probability of a
 * successive sequence of bits being unset is P(n) = 0.5^n [n > 0].
 *   P(level:1) = 0.5
 *   P(level:2) = 0.25
 *   P(level:3) = 0.125
 *   P(level:4) = 0.0625
 *   ...
 * So we can use ffs() on a good random number generator to pick our
 * level. We divide by two to reduce the probability of choosing a
 * level to .25, as the cost of descending a level is the same as
 * following an extra link in the chain at that level (so we can
 * pack more nodes into fewer levels without incurring extra cost,
 * and allow scaling to higher volumes of requests without expanding
 * the height of the skiplist).
 */

-Chris
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Re: [Intel-gfx] [PATCH 20/41] drm/i915: Replace priolist rbtree with a skiplist

[Tvrtko Ursulin]

On 25/01/2021 14:01, Chris Wilson wrote:

Replace the priolist rbtree with a skiplist. The crucial difference is
that walking and removing the first element of a skiplist is O(1), but
O(lgN) for an rbtree, as we need to rebalance on remove. This is a
hindrance for submission latency as it occurs between picking a request
for the priolist and submitting it to hardware, as well effectively
trippling the number of O(lgN) operations required under the irqoff lock.
This is critical to reducing the latency jitter with multiple clients.

The downsides to skiplists are that lookup/insertion is only
probablistically O(lgN) and there is a significant memory penalty to
as each skip node is larger than the rbtree equivalent. Furthermore, we
don't use dynamic arrays for the skiplist, so the allocation is fixed,
and imposes an upper bound on the scalability wrt to the number of
inflight requests.

Signed-off-by: Chris Wilson 
---
  .../drm/i915/gt/intel_execlists_submission.c  |  63 +++--
  .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  30 +--
  drivers/gpu/drm/i915/i915_priolist_types.h|  28 +-
  drivers/gpu/drm/i915/i915_scheduler.c | 244 ++
  drivers/gpu/drm/i915/i915_scheduler.h |  11 +-
  drivers/gpu/drm/i915/i915_scheduler_types.h   |   2 +-
  .../drm/i915/selftests/i915_mock_selftests.h  |   1 +
  .../gpu/drm/i915/selftests/i915_scheduler.c   |  53 +++-
  8 files changed, 316 insertions(+), 116 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c 
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 1103c8a00af1..129144dd86b0 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -244,11 +244,6 @@ static void ring_set_paused(const struct intel_engine_cs 
*engine, int state)
wmb();
  }
  
-static struct i915_priolist *to_priolist(struct rb_node *rb)

-{
-   return rb_entry(rb, struct i915_priolist, node);
-}
-
  static int rq_prio(const struct i915_request *rq)
  {
return READ_ONCE(rq->sched.attr.priority);
@@ -272,15 +267,31 @@ static int effective_prio(const struct i915_request *rq)
return prio;
  }
  
-static int queue_prio(const struct i915_sched_engine *se)

+static struct i915_request *first_request(struct i915_sched_engine *se)
  {
-   struct rb_node *rb;
+   struct i915_priolist *pl;
  
-	rb = rb_first_cached(>queue);

-   if (!rb)
+   for_each_priolist(pl, >queue) {
+   if (likely(!list_empty(>requests)))
+   return list_first_entry(>requests,
+   struct i915_request,
+   sched.link);
+
+   i915_priolist_advance(>queue, pl);


Why is a "peek" type call site doing tree modifications? Couldn't that 
be limited to places which add/remove?



+   }
+
+   return NULL;
+}
+
+static int queue_prio(struct i915_sched_engine *se)
+{
+   struct i915_request *rq;
+
+   rq = first_request(se);
+   if (!rq)
return INT_MIN;
  
-	return to_priolist(rb)->priority;

+   return rq_prio(rq);
  }
  
  static int virtual_prio(const struct intel_engine_execlists *el)

@@ -290,7 +301,7 @@ static int virtual_prio(const struct intel_engine_execlists 
*el)
return rb ? rb_entry(rb, struct ve_node, rb)->prio : INT_MIN;
  }
  
-static bool need_preempt(const struct intel_engine_cs *engine,

+static bool need_preempt(struct intel_engine_cs *engine,
 const struct i915_request *rq)
  {
int last_prio;
@@ -1136,6 +1147,7 @@ static void execlists_dequeue(struct intel_engine_cs 
*engine)
struct i915_request ** const last_port = port + execlists->port_mask;
struct i915_request *last, * const *active;
struct virtual_engine *ve;
+   struct i915_priolist *pl;
struct rb_node *rb;
bool submit = false;
  
@@ -1346,11 +1358,10 @@ static void execlists_dequeue(struct intel_engine_cs *engine)

break;
}
  
-	while ((rb = rb_first_cached(>active.queue))) {

-   struct i915_priolist *p = to_priolist(rb);
+   for_each_priolist(pl, >active.queue) {
struct i915_request *rq, *rn;
  
-		priolist_for_each_request_consume(rq, rn, p) {

+   priolist_for_each_request_safe(rq, rn, pl) {
bool merge = true;
  
  			/*

@@ -1425,8 +1436,7 @@ static void execlists_dequeue(struct intel_engine_cs 
*engine)
}
}
  
-		rb_erase_cached(>node, >active.queue);

-   i915_priolist_free(p);
+   i915_priolist_advance(>active.queue, pl);


There must be someone doing a list_del on this request in this block so 
I suppose it is hidden somewhere in the chain, must be 
__i915_request_submit. I guess it was the same with rbtree so I just 
wonder if there is a way to document 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/debugfs: HDCP capability enc NULL check

[Patchwork]

== Series Details ==

Series: drm/i915/debugfs: HDCP capability enc NULL check
URL   : https://patchwork.freedesktop.org/series/86440/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9698 -> Patchwork_19538


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19538/index.html

Known issues


  Here are the changes found in Patchwork_19538 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_basic@memory-alloc:
- fi-cml-u2:  NOTRUN -> [SKIP][1] ([fdo#109315]) +17 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19538/fi-cml-u2/igt@amdgpu/amd_ba...@memory-alloc.html

  * igt@gem_exec_fence@basic-busy@bcs0:
- fi-cml-u2:  NOTRUN -> [SKIP][2] ([i915#1208]) +1 similar issue
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19538/fi-cml-u2/igt@gem_exec_fence@basic-b...@bcs0.html

  * igt@gem_huc_copy@huc-copy:
- fi-cml-u2:  NOTRUN -> [SKIP][3] ([i915#2190])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19538/fi-cml-u2/igt@gem_huc_c...@huc-copy.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-cml-u2:  NOTRUN -> [SKIP][4] ([i915#1004]) +2 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19538/fi-cml-u2/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_chamelium@vga-edid-read:
- fi-cml-u2:  NOTRUN -> [SKIP][5] ([fdo#109309]) +1 similar issue
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19538/fi-cml-u2/igt@kms_chamel...@vga-edid-read.html

  * igt@kms_force_connector_basic@force-load-detect:
- fi-cml-u2:  NOTRUN -> [SKIP][6] ([fdo#109285])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19538/fi-cml-u2/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-cml-u2:  NOTRUN -> [SKIP][7] ([fdo#109278] / [i915#533])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19538/fi-cml-u2/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  * igt@prime_self_import@basic-with_one_bo_two_files:
- fi-tgl-y:   [PASS][8] -> [DMESG-WARN][9] ([i915#402]) +1 similar 
issue
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9698/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19538/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html

  
 Possible fixes 

  * igt@i915_getparams_basic@basic-subslice-total:
- fi-tgl-y:   [DMESG-WARN][10] ([i915#402]) -> [PASS][11] +1 
similar issue
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9698/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19538/fi-tgl-y/igt@i915_getparams_ba...@basic-subslice-total.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [i915#1004]: https://gitlab.freedesktop.org/drm/intel/issues/1004
  [i915#1208]: https://gitlab.freedesktop.org/drm/intel/issues/1208
  [i915#1614]: https://gitlab.freedesktop.org/drm/intel/issues/1614
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533


Participating hosts (43 -> 39)
--

  Additional (2): fi-cml-u2 fi-cml-drallion 
  Missing(6): fi-jsl-1 fi-ilk-m540 fi-hsw-4200u fi-byt-j1900 fi-bsw-cyan 
fi-bdw-samus 


Build changes
-

  * Linux: CI_DRM_9698 -> Patchwork_19538

  CI-20190529: 20190529
  CI_DRM_9698: 4917e86d5a4ca50e451247a3607e0f1eb81eedba @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5978: e1e5b3fea2baafdae0160940ecb8bf0242703840 @ 
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_19538: 830071064e9ecaa6b0a123e555b634e217d9135d @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

830071064e9e drm/i915/debugfs: HDCP capability enc NULL check

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19538/index.html
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Re: [Intel-gfx] [PATCH i-g-t 2/2] i915/sysfs_clients: Check that client ids are cyclic

[Chris Wilson]

Quoting Tvrtko Ursulin (2021-01-29 09:18:50)
> 
> 
> On 26/01/2021 13:05, Chris Wilson wrote:
> > The client id used is a cyclic allocator as that reduces the likelihood
> > of userspace seeing the same id used again (and so confusing the new
> > client as the old). Verify that each new client has an id greater than
> > the last.
> > 
> > Signed-off-by: Chris Wilson 
> > Cc: Tvrtko Ursulin 
> > ---
> >   tests/i915/sysfs_clients.c | 129 +++--
> >   1 file changed, 108 insertions(+), 21 deletions(-)
> > 
> > diff --git a/tests/i915/sysfs_clients.c b/tests/i915/sysfs_clients.c
> > index a3a1f81e1..d2c1ebc5f 100644
> > --- a/tests/i915/sysfs_clients.c
> > +++ b/tests/i915/sysfs_clients.c
> > @@ -8,6 +8,7 @@
> >   #include 
> >   #include 
> >   #include 
> > +#include 
> >   #include 
> >   #include 
> >   #include 
> > @@ -47,6 +48,8 @@
> >   #define assert_within_epsilon(x, ref, tolerance) \
> >   __assert_within_epsilon(x, ref, tolerance / 100., tolerance / 100.)
> >   
> > +#define BUFSZ 280
> > +
> >   #define MI_BATCH_BUFFER_START (0x31 << 23)
> >   #define MI_BATCH_BUFFER_END (0xa << 23)
> >   #define MI_ARB_CHECK (0x5 << 23)
> > @@ -75,7 +78,7 @@ static void pidname(int i915, int clients)
> >   {
> >   struct dirent *de;
> >   int sv[2], rv[2];
> > - char buf[280];
> > + char buf[BUFSZ];
> >   int me = -1;
> >   long count;
> >   pid_t pid;
> > @@ -180,7 +183,7 @@ static long count_clients(int clients)
> >   {
> >   struct dirent *de;
> >   long count = 0;
> > - char buf[280];
> > + char buf[BUFSZ];
> >   DIR *dir;
> >   
> >   dir = fdopendir(dup(clients));
> > @@ -229,32 +232,113 @@ static void create(int i915, int clients)
> >   igt_assert_eq(count_clients(clients), 1);
> >   }
> >   
> > +static const char *find_client(int clients, pid_t pid, char *buf)
> > +{
> > + DIR *dir = fdopendir(dup(clients));
> > +
> > + /* Reading a dir as it changes does not appear to be stable, SEP */
> > + for (int pass = 0; pass < 2; pass++) {
> > + struct dirent *de;
> > +
> > + rewinddir(dir);
> > + while ((de = readdir(dir))) {
> > + if (!isdigit(de->d_name[0]))
> > + continue;
> > +
> > + snprintf(buf, BUFSZ, "%s/pid", de->d_name);
> > + igt_sysfs_read(clients, buf, buf, sizeof(buf));
> > + if (atoi(buf) != pid)
> > + continue;
> > +
> > + strncpy(buf, de->d_name, BUFSZ);
> > + goto out;
> > + }
> > + }
> > + *buf = '\0';
> > +out:
> > + closedir(dir);
> > + return buf;
> > +}
> > +
> >   static int find_me(int clients, pid_t pid)
> >   {
> > - struct dirent *de;
> > - char buf[280];
> > - int me = -1;
> > - DIR *dir;
> > + char buf[BUFSZ];
> >   
> > - dir = fdopendir(dup(clients));
> > - igt_assert(dir);
> > - rewinddir(dir);
> > + return openat(clients,
> > +   find_client(clients, pid, buf),
> > +   O_DIRECTORY | O_RDONLY);
> > +}
> >   
> > - while ((de = readdir(dir))) {
> > - if (!isdigit(de->d_name[0]))
> > - continue;
> > +static int reopen_directory(int fd)
> > +{
> > + char buf[BUFSZ];
> > + int dir;
> >   
> > - snprintf(buf, sizeof(buf), "%s/pid", de->d_name);
> > - igt_sysfs_read(clients, buf, buf, sizeof(buf));
> > - if (atoi(buf) != pid)
> > - continue;
> > + snprintf(buf, sizeof(buf), "/proc/self/fd/%d", fd);
> > + dir = open(buf, O_RDONLY);
> 
> Maybe O_DIRECTORY if it is open_directory.
> 
> > + igt_assert_fd(dir);
> >   
> > - me = openat(clients, de->d_name, O_DIRECTORY | O_RDONLY);
> > - break;
> > + return dir;
> > +}
> > +
> > +static unsigned int my_id(int clients, pid_t pid)
> > +{
> > + char buf[BUFSZ];
> > +
> > + return atoi(find_client(clients, pid, buf));
> > +}
> > +
> > +static unsigned int recycle_client(int i915, int clients)
> > +{
> > + int device, client;
> > +
> > + device = gem_reopen_driver(i915);
> > + client = my_id(clients, getpid());
> > + close(device);
> > +
> > + return client;
> > +}
> > +
> > +static void recycle(int i915, int clients)
> > +{
> > + const int ncpus = sysconf(_SC_NPROCESSORS_ONLN);
> > +
> > + /*
> > +  * As we open and close clients, we do not expect to reuse old ids,
> > +  * i.e. we use a cyclic ida. This reduces the likelihood of userspace
> > +  * watchers becoming confused and mistaking the new client as a
> > +  * continuation of the old.
> > +  */
> > + igt_require(my_id(clients, getpid()) < INT_MAX / 2);
> 
> Hm this is a bit dodgy - it will cause "permanent" skips if running the 
> test in a loop. Just for the client > last assert below? 

Re: [Intel-gfx] [PATCH 20/41] drm/i915: Replace priolist rbtree with a skiplist

[Tvrtko Ursulin]

On 28/01/2021 16:26, Chris Wilson wrote:

Quoting Tvrtko Ursulin (2021-01-28 15:56:19)



-static void assert_priolists(struct i915_sched_engine * const se)
-{
- struct rb_node *rb;
- long last_prio;
-
- if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
- return;
-
- GEM_BUG_ON(rb_first_cached(>queue) !=
-rb_first(>queue.rb_root));
-
- last_prio = INT_MAX;
- for (rb = rb_first_cached(>queue); rb; rb = rb_next(rb)) {
- const struct i915_priolist *p = to_priolist(rb);
-
- GEM_BUG_ON(p->priority > last_prio);
- last_prio = p->priority;
- }
+ root->prng = next_pseudo_random32(root->prng);
+ return  __ffs(root->prng) / 2;


Where is the relationship to I915_PRIOLIST_HEIGHT? Feels root->prng %
I915_PRIOLIST_HEIGHT would be more obvious here unless I am terribly
mistaken. Or at least put a comment saying why the hack.


HEIGHT is the maximum possible for our struct. skiplists only want to
increment the height of the tree one step at a time. So we choose a level
with decreasing probability, and then limit that to the maximum height of
the current tree + 1, clamped to HEIGHT.

You might notice that unlike traditional skiplists, this uses a
probability of 0.25 for each additional level. A neat trick discovered by
Con Kolivas (I haven't found it mentioned elsewhere) as the cost of the
extra level (using P=.5) is the same as the extra chain length with
P=.25. So you can scale to higher number of requests by packing more
requests into each level.

So that is split between randomly choosing a level and then working out
the height of the node.


Choosing levels with decreasing probability by the virtue of using ffs 
on a random number? Or because (BITS_PER_TYPE(u32) / 2) is greater than 
I915_PRIOLIST_HEIGHT?


Regards,

Tvrtko
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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v14,1/2] drm/i915/display: Support PSR Multiple Instances

[Patchwork]

== Series Details ==

Series: series starting with [v14,1/2] drm/i915/display: Support PSR Multiple 
Instances
URL   : https://patchwork.freedesktop.org/series/86433/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9698 -> Patchwork_19537


Summary
---

  **WARNING**

  Minor unknown changes coming with Patchwork_19537 need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_19537, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19537/index.html

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_19537:

### IGT changes ###

 Warnings 

  * igt@kms_psr@primary_mmap_gtt:
- fi-icl-y:   [SKIP][1] ([fdo#110189]) -> [SKIP][2] +3 similar 
issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9698/fi-icl-y/igt@kms_psr@primary_mmap_gtt.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19537/fi-icl-y/igt@kms_psr@primary_mmap_gtt.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_psr@cursor_plane_move:
- {fi-rkl-11500t}:[SKIP][3] ([i915#1072]) -> [SKIP][4] +3 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9698/fi-rkl-11500t/igt@kms_psr@cursor_plane_move.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19537/fi-rkl-11500t/igt@kms_psr@cursor_plane_move.html

  * igt@kms_psr@primary_mmap_gtt:
- {fi-tgl-dsi}:   [SKIP][5] ([fdo#110189]) -> [SKIP][6] +3 similar 
issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9698/fi-tgl-dsi/igt@kms_psr@primary_mmap_gtt.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19537/fi-tgl-dsi/igt@kms_psr@primary_mmap_gtt.html

  * igt@kms_psr@sprite_plane_onoff:
- {fi-ehl-1}: [SKIP][7] ([i915#1072]) -> [SKIP][8] +3 similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9698/fi-ehl-1/igt@kms_psr@sprite_plane_onoff.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19537/fi-ehl-1/igt@kms_psr@sprite_plane_onoff.html

  
Known issues


  Here are the changes found in Patchwork_19537 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_basic@memory-alloc:
- fi-cml-u2:  NOTRUN -> [SKIP][9] ([fdo#109315]) +17 similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19537/fi-cml-u2/igt@amdgpu/amd_ba...@memory-alloc.html

  * igt@gem_exec_fence@basic-busy@bcs0:
- fi-cml-u2:  NOTRUN -> [SKIP][10] ([i915#1208]) +1 similar issue
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19537/fi-cml-u2/igt@gem_exec_fence@basic-b...@bcs0.html

  * igt@gem_exec_suspend@basic-s3:
- fi-tgl-y:   [PASS][11] -> [DMESG-WARN][12] ([i915#2411] / 
[i915#402])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9698/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19537/fi-tgl-y/igt@gem_exec_susp...@basic-s3.html

  * igt@gem_flink_basic@bad-flink:
- fi-tgl-y:   [PASS][13] -> [DMESG-WARN][14] ([i915#402])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9698/fi-tgl-y/igt@gem_flink_ba...@bad-flink.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19537/fi-tgl-y/igt@gem_flink_ba...@bad-flink.html

  * igt@gem_huc_copy@huc-copy:
- fi-cml-u2:  NOTRUN -> [SKIP][15] ([i915#2190])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19537/fi-cml-u2/igt@gem_huc_c...@huc-copy.html

  * igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u:   [PASS][16] -> [FAIL][17] ([i915#1161] / [i915#262])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9698/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19537/fi-kbl-7500u/igt@kms_chamel...@dp-crc-fast.html

  * igt@kms_chamelium@hdmi-hpd-fast:
- fi-cml-u2:  NOTRUN -> [SKIP][18] ([i915#1004]) +2 similar issues
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19537/fi-cml-u2/igt@kms_chamel...@hdmi-hpd-fast.html

  * igt@kms_chamelium@vga-edid-read:
- fi-cml-u2:  NOTRUN -> [SKIP][19] ([fdo#109309]) +1 similar issue
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19537/fi-cml-u2/igt@kms_chamel...@vga-edid-read.html

  * igt@kms_force_connector_basic@force-load-detect:
- fi-cml-u2:  NOTRUN -> [SKIP][20] ([fdo#109285])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19537/fi-cml-u2/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- 

Re: [Intel-gfx] [PATCH 20/41] drm/i915: Replace priolist rbtree with a skiplist

[Tvrtko Ursulin]

On 28/01/2021 22:44, Chris Wilson wrote:

Quoting Tvrtko Ursulin (2021-01-28 16:42:44)


On 28/01/2021 16:26, Chris Wilson wrote:

Quoting Tvrtko Ursulin (2021-01-28 15:56:19)

On 25/01/2021 14:01, Chris Wilson wrote:

diff --git a/drivers/gpu/drm/i915/i915_priolist_types.h 
b/drivers/gpu/drm/i915/i915_priolist_types.h
index bc2fa84f98a8..1200c3df6a4a 100644
--- a/drivers/gpu/drm/i915/i915_priolist_types.h
+++ b/drivers/gpu/drm/i915/i915_priolist_types.h
@@ -38,10 +38,36 @@ enum {
#define I915_PRIORITY_UNPREEMPTABLE INT_MAX
#define I915_PRIORITY_BARRIER (I915_PRIORITY_UNPREEMPTABLE - 1)

+#ifdef CONFIG_64BIT

+#define I915_PRIOLIST_HEIGHT 12
+#else
+#define I915_PRIOLIST_HEIGHT 11
+#endif


I did not get this. On one hand I could think pointers are larger on
64-bit so go for fewer levels, if size was a concern. But on the other
hand 32-bit is less important these days, definitely much less as a
performance platform. So going for less memory use => worse performance
on a less important platform, which typically could be more memory
constrained? Not sure I see it as that important either way to be
distinctive but a comment would satisfy me.


Just aligned to the cacheline. The struct is 128B on 64b and 64B on 32b.
On 64B, we will scale to around 16 million requests in flight and 4
million on 32b. Which should be enough.

If we shrunk 64b to a 64B node, we would only scale to 256 requests
which limit we definitely will exceed.


Ok thanks, pouring it into a comment is implied.




struct i915_priolist {
struct list_head requests;


What would be on this list? Request can only be on one at a time, so I
was thinking these nodes would have pointers to list of that priority,
rather than lists themselves. Assuming there can be multiple nodes of
the same priority in the 2d hierarcy. Possibly I don't understand the
layout.


A request is only on one list (queue, active, hold). But we may still
have more than one request at the same deadline, though that will likely
be limited to priority-inheritance and timeslice deferrals.

Since we would need pointer to the request, we could only reclaim a
single pointer here, which is not enough to warrant reducing the overall
node size. And while there is at least one user of request->sched.link,
the list maintenance will still be incurred. Using request->sched.link
remains a convenient interface.


Lost you.


/*
  * i915_priolist forms a skiplist. The skiplist is built in layers,
  * starting at the base [0] is a singly linked list of all i915_priolist.
  * Each higher layer contains a fraction of the i915_priolist from the
  * previous layer:
  *
  * S[0] 0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF S
  * E[1] >1>3>5>7>9>B>D>F>1>3>5>7>9>B>D>F>1>3>5>7>9>B>D>F>1>3>5>7>9>B>D>F E
  * N[2] -->3-->7-->B-->F-->3-->7-->B-->F-->3-->7-->B-->F-->3-->7-->B-->F N
  * T[3] --->7->F---7-->F-->7-->F-->7-->F 


Just align this first 7.

T

  * I[4] -->F-->F-->F-->F I
  * N[5] -->F-->F N
  * E[6] -->F---> E
  * L[7] ---> L
  *
  * To iterate through all active i915_priolist, we only need to follow
  * the chain in i915_priolist.next[0] (see for_each_priolist).
  *
  * To quickly find a specific key (or insert point), we can perform a binary
  * search by starting at the highest level and following the linked list
  * at that level until we either find the node, or have gone passed the key.
  * Then we descend a level, and start walking the list again starting from
  * the current position, until eventually we find our key, or we run out of


From the previous on the current level, not current I believe. So go 
previous before descending, right?


Very useful diagram, thank you.

Regards,

Tvrtko
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Re: [Intel-gfx] [PATCH i-g-t 2/2] i915/sysfs_clients: Check that client ids are cyclic

[Tvrtko Ursulin]

On 26/01/2021 13:05, Chris Wilson wrote:

The client id used is a cyclic allocator as that reduces the likelihood
of userspace seeing the same id used again (and so confusing the new
client as the old). Verify that each new client has an id greater than
the last.

Signed-off-by: Chris Wilson 
Cc: Tvrtko Ursulin 
---
  tests/i915/sysfs_clients.c | 129 +++--
  1 file changed, 108 insertions(+), 21 deletions(-)

diff --git a/tests/i915/sysfs_clients.c b/tests/i915/sysfs_clients.c
index a3a1f81e1..d2c1ebc5f 100644
--- a/tests/i915/sysfs_clients.c
+++ b/tests/i915/sysfs_clients.c
@@ -8,6 +8,7 @@
  #include 
  #include 
  #include 
+#include 
  #include 
  #include 
  #include 
@@ -47,6 +48,8 @@
  #define assert_within_epsilon(x, ref, tolerance) \
__assert_within_epsilon(x, ref, tolerance / 100., tolerance / 100.)
  
+#define BUFSZ 280

+
  #define MI_BATCH_BUFFER_START (0x31 << 23)
  #define MI_BATCH_BUFFER_END (0xa << 23)
  #define MI_ARB_CHECK (0x5 << 23)
@@ -75,7 +78,7 @@ static void pidname(int i915, int clients)
  {
struct dirent *de;
int sv[2], rv[2];
-   char buf[280];
+   char buf[BUFSZ];
int me = -1;
long count;
pid_t pid;
@@ -180,7 +183,7 @@ static long count_clients(int clients)
  {
struct dirent *de;
long count = 0;
-   char buf[280];
+   char buf[BUFSZ];
DIR *dir;
  
  	dir = fdopendir(dup(clients));

@@ -229,32 +232,113 @@ static void create(int i915, int clients)
igt_assert_eq(count_clients(clients), 1);
  }
  
+static const char *find_client(int clients, pid_t pid, char *buf)

+{
+   DIR *dir = fdopendir(dup(clients));
+
+   /* Reading a dir as it changes does not appear to be stable, SEP */
+   for (int pass = 0; pass < 2; pass++) {
+   struct dirent *de;
+
+   rewinddir(dir);
+   while ((de = readdir(dir))) {
+   if (!isdigit(de->d_name[0]))
+   continue;
+
+   snprintf(buf, BUFSZ, "%s/pid", de->d_name);
+   igt_sysfs_read(clients, buf, buf, sizeof(buf));
+   if (atoi(buf) != pid)
+   continue;
+
+   strncpy(buf, de->d_name, BUFSZ);
+   goto out;
+   }
+   }
+   *buf = '\0';
+out:
+   closedir(dir);
+   return buf;
+}
+
  static int find_me(int clients, pid_t pid)
  {
-   struct dirent *de;
-   char buf[280];
-   int me = -1;
-   DIR *dir;
+   char buf[BUFSZ];
  
-	dir = fdopendir(dup(clients));

-   igt_assert(dir);
-   rewinddir(dir);
+   return openat(clients,
+ find_client(clients, pid, buf),
+ O_DIRECTORY | O_RDONLY);
+}
  
-	while ((de = readdir(dir))) {

-   if (!isdigit(de->d_name[0]))
-   continue;
+static int reopen_directory(int fd)
+{
+   char buf[BUFSZ];
+   int dir;
  
-		snprintf(buf, sizeof(buf), "%s/pid", de->d_name);

-   igt_sysfs_read(clients, buf, buf, sizeof(buf));
-   if (atoi(buf) != pid)
-   continue;
+   snprintf(buf, sizeof(buf), "/proc/self/fd/%d", fd);
+   dir = open(buf, O_RDONLY);


Maybe O_DIRECTORY if it is open_directory.


+   igt_assert_fd(dir);
  
-		me = openat(clients, de->d_name, O_DIRECTORY | O_RDONLY);

-   break;
+   return dir;
+}
+
+static unsigned int my_id(int clients, pid_t pid)
+{
+   char buf[BUFSZ];
+
+   return atoi(find_client(clients, pid, buf));
+}
+
+static unsigned int recycle_client(int i915, int clients)
+{
+   int device, client;
+
+   device = gem_reopen_driver(i915);
+   client = my_id(clients, getpid());
+   close(device);
+
+   return client;
+}
+
+static void recycle(int i915, int clients)
+{
+   const int ncpus = sysconf(_SC_NPROCESSORS_ONLN);
+
+   /*
+* As we open and close clients, we do not expect to reuse old ids,
+* i.e. we use a cyclic ida. This reduces the likelihood of userspace
+* watchers becoming confused and mistaking the new client as a
+* continuation of the old.
+*/
+   igt_require(my_id(clients, getpid()) < INT_MAX / 2);


Hm this is a bit dodgy - it will cause "permanent" skips if running the 
test in a loop. Just for the client > last assert below? I guess it is 
hard to handle wrap with forked clients.



+   igt_assert(my_id(clients, getpid()));
+
+   igt_fork(child, 2 * ncpus) {
+   unsigned int client, last;
+
+   /* Reopen the directory fd for each client */
+   clients = reopen_directory(clients);
+
+   last = recycle_client(i915, clients);
+   igt_info("Child[%d] first client:%d\n", getpid(), last);
+   igt_until_timeout(5) {
+   client = recycle_client(i915, clients);

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v14,1/2] drm/i915/display: Support PSR Multiple Instances

[Patchwork]

== Series Details ==

Series: series starting with [v14,1/2] drm/i915/display: Support PSR Multiple 
Instances
URL   : https://patchwork.freedesktop.org/series/86433/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1327:5: warning: context imbalance in 
'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gvt/mmio.c:295:23: warning: memcpy with byte count of 
279040
+drivers/gpu/drm/i915/i915_perf.c:1450:15: warning: memset with byte count of 
16777216
+drivers/gpu/drm/i915/i915_perf.c:1504:15: warning: memset with byte count of 
16777216
+drivers/gpu/drm/i915/intel_wakeref.c:137:19: warning: context imbalance in 
'wakeref_auto_timeout' - unexpected unlock
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' 
- different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' 
- different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' 
- different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - 
different lock contexts for basic 

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v14,1/2] drm/i915/display: Support PSR Multiple Instances

[Patchwork]

== Series Details ==

Series: series starting with [v14,1/2] drm/i915/display: Support PSR Multiple 
Instances
URL   : https://patchwork.freedesktop.org/series/86433/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
2beed3acee30 drm/i915/display: Support PSR Multiple Instances
-:88: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in 
parentheses
#88: FILE: drivers/gpu/drm/i915/display/intel_display.h:420:
+#define for_each_intel_encoder_mask_can_psr(dev, intel_encoder, encoder_mask) \
+   list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, 
base.head) \
+   for_each_if(((encoder_mask) & 
drm_encoder_mask(&(intel_encoder)->base)) && \
+   intel_encoder_can_psr(intel_encoder))

-:88: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'intel_encoder' - possible 
side-effects?
#88: FILE: drivers/gpu/drm/i915/display/intel_display.h:420:
+#define for_each_intel_encoder_mask_can_psr(dev, intel_encoder, encoder_mask) \
+   list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, 
base.head) \
+   for_each_if(((encoder_mask) & 
drm_encoder_mask(&(intel_encoder)->base)) && \
+   intel_encoder_can_psr(intel_encoder))

-:97: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in 
parentheses
#97: FILE: drivers/gpu/drm/i915/display/intel_display.h:429:
+#define for_each_intel_encoder_can_psr(dev, intel_encoder) \
+   for_each_intel_encoder((dev), (intel_encoder)) \
+   for_each_if(intel_encoder_can_psr(intel_encoder))

-:97: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'intel_encoder' - possible 
side-effects?
#97: FILE: drivers/gpu/drm/i915/display/intel_display.h:429:
+#define for_each_intel_encoder_can_psr(dev, intel_encoder) \
+   for_each_intel_encoder((dev), (intel_encoder)) \
+   for_each_if(intel_encoder_can_psr(intel_encoder))

-:375: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'intel_dp' - possible 
side-effects?
#375: FILE: drivers/gpu/drm/i915/display/intel_display_types.h:1795:
+#define CAN_PSR(intel_dp)  (HAS_PSR(dp_to_i915(intel_dp)) && \
+(intel_dp)->psr.sink_support && \
+(intel_dp)->psr.source_support)

-:1188: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#1188: FILE: drivers/gpu/drm/i915/display/intel_psr.c:1230:
+   crtc_state->uapi.encoder_mask) {
+

-:1320: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1320: FILE: drivers/gpu/drm/i915/display/intel_psr.c:1523:
+   if (!intel_dp->psr.enabled ||
+(intel_dp->psr.enabled && intel_dp->psr.psr2_enabled)) {

total: 2 errors, 0 warnings, 5 checks, 1731 lines checked
84aa39bab08a drm/i915/display: Support Multiple Transcoders' PSR status on 
debugfs


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[Intel-gfx] [PATCH] drm/i915/debugfs: HDCP capability enc NULL check

[Anshuman Gupta]

DP-MST connector encoder initializes at modeset
Adding a connector->encoder NULL check in order to
avoid any NULL pointer dereference.
intel_hdcp_enable() already handle this but debugfs
can also invoke the intel_{hdcp,hdcp2_capable}.
Handling it gracefully.

Signed-off-by: Anshuman Gupta 
---
 drivers/gpu/drm/i915/display/intel_hdcp.c | 14 --
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c 
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index ae1371c36a32..58af323d189a 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -135,11 +135,16 @@ int intel_hdcp_read_valid_bksv(struct intel_digital_port 
*dig_port,
 /* Is HDCP1.4 capable on Platform and Sink */
 bool intel_hdcp_capable(struct intel_connector *connector)
 {
-   struct intel_digital_port *dig_port = 
intel_attached_dig_port(connector);
+   struct intel_digital_port *dig_port;
const struct intel_hdcp_shim *shim = connector->hdcp.shim;
bool capable = false;
u8 bksv[5];
 
+   if (!connector->encoder)
+   return -ENODEV;
+
+   dig_port = intel_attached_dig_port(connector);
+
if (!shim)
return capable;
 
@@ -156,11 +161,16 @@ bool intel_hdcp_capable(struct intel_connector *connector)
 /* Is HDCP2.2 capable on Platform and Sink */
 bool intel_hdcp2_capable(struct intel_connector *connector)
 {
-   struct intel_digital_port *dig_port = 
intel_attached_dig_port(connector);
+   struct intel_digital_port *dig_port;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct intel_hdcp *hdcp = >hdcp;
bool capable = false;
 
+   if (!connector->encoder)
+   return -ENODEV;
+
+   dig_port = intel_attached_dig_port(connector);
+
/* I915 support for HDCP2.2 */
if (!hdcp->hdcp2_supported)
return false;
-- 
2.26.2

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Re: [Intel-gfx] [PATCH 2/2] drm/i915/gvt: Purge dev_priv->gt

[Zhenyu Wang]

On 2021.01.29 00:49:33 +, Chris Wilson wrote:
> Use the right intel_gt stored as a backpointer in intel_vgpu.
> 
> Signed-off-by: Chris Wilson 
> ---

Reviewed-by: Zhenyu Wang 

I'll queue these two. Thanks!

>  drivers/gpu/drm/i915/gvt/execlist.c  | 8 +++-
>  drivers/gpu/drm/i915/gvt/scheduler.c | 3 +--
>  2 files changed, 4 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gvt/execlist.c 
> b/drivers/gpu/drm/i915/gvt/execlist.c
> index 158873f269b1..c8dcda6d4f0d 100644
> --- a/drivers/gpu/drm/i915/gvt/execlist.c
> +++ b/drivers/gpu/drm/i915/gvt/execlist.c
> @@ -522,12 +522,11 @@ static void init_vgpu_execlist(struct intel_vgpu *vgpu,
>  static void clean_execlist(struct intel_vgpu *vgpu,
>  intel_engine_mask_t engine_mask)
>  {
> - struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
> - struct intel_engine_cs *engine;
>   struct intel_vgpu_submission *s = >submission;
> + struct intel_engine_cs *engine;
>   intel_engine_mask_t tmp;
>  
> - for_each_engine_masked(engine, _priv->gt, engine_mask, tmp) {
> + for_each_engine_masked(engine, vgpu->gvt->gt, engine_mask, tmp) {
>   kfree(s->ring_scan_buffer[engine->id]);
>   s->ring_scan_buffer[engine->id] = NULL;
>   s->ring_scan_buffer_size[engine->id] = 0;
> @@ -537,11 +536,10 @@ static void clean_execlist(struct intel_vgpu *vgpu,
>  static void reset_execlist(struct intel_vgpu *vgpu,
>  intel_engine_mask_t engine_mask)
>  {
> - struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
>   struct intel_engine_cs *engine;
>   intel_engine_mask_t tmp;
>  
> - for_each_engine_masked(engine, _priv->gt, engine_mask, tmp)
> + for_each_engine_masked(engine, vgpu->gvt->gt, engine_mask, tmp)
>   init_vgpu_execlist(vgpu, engine);
>  }
>  
> diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c 
> b/drivers/gpu/drm/i915/gvt/scheduler.c
> index 43f31c2eab14..a55ae50dbbe1 100644
> --- a/drivers/gpu/drm/i915/gvt/scheduler.c
> +++ b/drivers/gpu/drm/i915/gvt/scheduler.c
> @@ -1015,13 +1015,12 @@ void intel_vgpu_clean_workloads(struct intel_vgpu 
> *vgpu,
>   intel_engine_mask_t engine_mask)
>  {
>   struct intel_vgpu_submission *s = >submission;
> - struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
>   struct intel_engine_cs *engine;
>   struct intel_vgpu_workload *pos, *n;
>   intel_engine_mask_t tmp;
>  
>   /* free the unsubmited workloads in the queues. */
> - for_each_engine_masked(engine, _priv->gt, engine_mask, tmp) {
> + for_each_engine_masked(engine, vgpu->gvt->gt, engine_mask, tmp) {
>   list_for_each_entry_safe(pos, n,
>   >workload_q_head[engine->id], list) {
>   list_del_init(>list);
> -- 
> 2.20.1
> 
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx


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