Re: [Intel-gfx] [PATCH V3 5/8] drm/i915/gt: Initialize unused MOCS entries with device specific values

[Siddiqui, Ayaz A]

> -Original Message-
> From: Roper, Matthew D 
> Sent: Thursday, September 2, 2021 5:15 AM
> To: Siddiqui, Ayaz A 
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH V3 5/8] drm/i915/gt: Initialize unused MOCS
> entries with device specific values
> 
> On Mon, Aug 30, 2021 at 09:52:37PM +0530, Ayaz A Siddiqui wrote:
> > Historically we've initialized all undefined/reserved entries in a
> > platform's MOCS table to the contents of table entry #1 (i.e.,
> > I915_MOCS_PTE).
> > Going forward, we can't assume that table entry #1 will always contain
> > suitable values to use for undefined/reserved table indices. We'll
> > allow a platform-specific table index to be selected at table
> > initialization time in these cases.
> >
> > This new mechanism to select L3 WB entry will be applicable for all
> > the Gen12+ platforms except TGL and RKL.
> >
> > Since TGL and RLK are already in production so their mocs settings are
> > intact to avoid ABI break.
> >
> > Signed-off-by: Ayaz A Siddiqui 
> > ---
> >  drivers/gpu/drm/i915/gt/intel_mocs.c | 41
> > +++-
> >  1 file changed, 22 insertions(+), 19 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c
> > b/drivers/gpu/drm/i915/gt/intel_mocs.c
> > index 82eafa8d22453..a97cc08e5a395 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> > @@ -25,6 +25,7 @@ struct drm_i915_mocs_table {
> > unsigned int n_entries;
> > const struct drm_i915_mocs_entry *table;
> > u8 uc_index;
> > +   u8 unused_entries_index;
> >  };
> >
> >  enum register_type {
> > @@ -113,18 +114,25 @@ struct drm_i915_aux_table {
> >   *
> >   * Entries not part of the following tables are undefined as far as
> >   * userspace is concerned and shouldn't be relied upon.  For Gen < 12
> > - * they will be initialized to PTE. Gen >= 12 onwards don't have a
> > setting for
> > - * PTE and will be initialized to an invalid value.
> > + * they will be initialized to PTE. Gen >= 12 don't have a setting
> > + for
> > + * PTE and those platforms except TGL/RKL will be initialized L3 WB
> > + to
> > + * catch accidental use of reserved and unused mocs indexes.
> >   *
> >   * The last few entries are reserved by the hardware. For ICL+ they
> >   * should be initialized according to bspec and never used, for older
> >   * platforms they should never be written to.
> >   *
> > - * NOTE: These tables are part of bspec and defined as part of
> > hardware
> > + * NOTE1: These tables are part of bspec and defined as part of
> > + hardware
> >   *   interface for ICL+. For older platforms, they are part of kernel
> >   *   ABI. It is expected that, for specific hardware platform, existing
> >   *   entries will remain constant and the table will only be updated by
> >   *   adding new entries, filling unused positions.
> > + *
> > + * NOTE2: For GEN >= 12 except TGL and RKL, reserved and unspecified
> MOCS
> > + *   indices have been set to L3 WB. These reserved entries should 
> > never
> > + *   be used, they may be changed to low performant variants with
> better
> > + *   coherency in the future if more entries are needed.
> > + *   For TGL/RKL, all the unspecified MOCS indexes are mapped to L3 UC.
> >   */
> >  #define GEN9_MOCS_ENTRIES \
> > MOCS_ENTRY(I915_MOCS_UNCACHED, \
> > @@ -307,17 +315,9 @@ static const struct drm_i915_mocs_entry
> > icl_mocs_table[] = {  };
> >
> >  static const struct drm_i915_mocs_entry dg1_mocs_table[] = {
> > -   /* Error */
> > -   MOCS_ENTRY(0, 0, L3_0_DIRECT),
> >
> > /* UC */
> > MOCS_ENTRY(1, 0, L3_1_UC),
> > -
> > -   /* Reserved */
> > -   MOCS_ENTRY(2, 0, L3_0_DIRECT),
> > -   MOCS_ENTRY(3, 0, L3_0_DIRECT),
> > -   MOCS_ENTRY(4, 0, L3_0_DIRECT),
> > -
> > /* WB - L3 */
> > MOCS_ENTRY(5, 0, L3_3_WB),
> > /* WB - L3 50% */
> > @@ -469,6 +469,7 @@ static unsigned int get_mocs_settings(const struct
> drm_i915_private *i915,
> > table->table = dg1_mocs_table;
> > table->n_entries = GEN9_NUM_MOCS_ENTRIES;
> > table->uc_index = 1;
> > +   table->unused_entries_index = 5;
> > } else if (GRAPHICS_VER(i915) >= 12) {
> > table->size  = ARRAY_SIZE(tgl_mocs_table);
> > table->table = tgl_mocs_table;
> 
> Should we add
> 
> table->unused_entries_index = 1;
> 
> to the rest of the platforms here since that's what we're doing in
> get_entry_l3cc() anyway?
> 
> Also I think we can rely on that to avoid the need to add a new MOCS table
> for ADL in the next patch; we can just use the same table but set a different
> unused_entries_index.  E.g.,
> 
> } else if (IS_TIGERLAKE(i915) || IS_ROCKETLAKE(i915)) {
> ...
> /* UC: Can't be changed now for ABI reasons */
> table->unused_entries_index = 1;
> } else if (GRAPHICS_VER(i915) >= 12) {
> ...
>   

[Intel-gfx] ✓ Fi.CI.IGT: success for Clean up GuC CI failures, simplify locking, and kernel DOC (rev8)

[Patchwork]

== Series Details ==

Series: Clean up GuC CI failures, simplify locking, and kernel DOC (rev8)
URL   : https://patchwork.freedesktop.org/series/93704/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10544_full -> Patchwork_20940_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_20940_full:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_cursor_legacy@pipe-d-forked-move:
- {shard-rkl}:NOTRUN -> [SKIP][1] +2 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20940/shard-rkl-1/igt@kms_cursor_leg...@pipe-d-forked-move.html

  
New tests
-

  New tests have been introduced between CI_DRM_10544_full and 
Patchwork_20940_full:

### New IGT tests (1) ###

  * igt@i915_selftest@live@guc:
- Statuses : 6 pass(s)
- Exec time: [0.51, 4.90] s

  

Known issues


  Here are the changes found in Patchwork_20940_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_persistence@process:
- shard-snb:  NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#1099]) +5 
similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20940/shard-snb2/igt@gem_ctx_persiste...@process.html

  * igt@gem_exec_fair@basic-deadline:
- shard-apl:  NOTRUN -> [FAIL][3] ([i915#2846])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20940/shard-apl8/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-kbl:  [PASS][4] -> [FAIL][5] ([i915#2842]) +4 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/shard-kbl6/igt@gem_exec_fair@basic-none-s...@rcs0.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20940/shard-kbl1/igt@gem_exec_fair@basic-none-s...@rcs0.html

  * igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][6] ([i915#2842])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20940/shard-iclb1/igt@gem_exec_fair@basic-n...@vcs1.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-iclb: [PASS][7] -> [FAIL][8] ([i915#2842])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/shard-iclb3/igt@gem_exec_fair@basic-pace-s...@rcs0.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20940/shard-iclb4/igt@gem_exec_fair@basic-pace-s...@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
- shard-tglb: [PASS][9] -> [FAIL][10] ([i915#2842]) +1 similar issue
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/shard-tglb5/igt@gem_exec_fair@basic-p...@vcs1.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20940/shard-tglb8/igt@gem_exec_fair@basic-p...@vcs1.html

  * igt@gem_exec_flush@basic-batch-kernel-default-cmd:
- shard-tglb: NOTRUN -> [SKIP][11] ([fdo#109313])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20940/shard-tglb6/igt@gem_exec_fl...@basic-batch-kernel-default-cmd.html

  * igt@gem_mmap_gtt@cpuset-big-copy-xy:
- shard-iclb: [PASS][12] -> [FAIL][13] ([i915#2428])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/shard-iclb1/igt@gem_mmap_...@cpuset-big-copy-xy.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20940/shard-iclb2/igt@gem_mmap_...@cpuset-big-copy-xy.html

  * igt@gem_pwrite@basic-exhaustion:
- shard-apl:  NOTRUN -> [WARN][14] ([i915#2658])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20940/shard-apl7/igt@gem_pwr...@basic-exhaustion.html

  * igt@gem_userptr_blits@dmabuf-sync:
- shard-apl:  NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#3323])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20940/shard-apl6/igt@gem_userptr_bl...@dmabuf-sync.html

  * igt@gem_userptr_blits@vma-merge:
- shard-tglb: NOTRUN -> [FAIL][16] ([i915#3318])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20940/shard-tglb1/igt@gem_userptr_bl...@vma-merge.html

  * igt@gem_workarounds@suspend-resume-fd:
- shard-kbl:  NOTRUN -> [DMESG-WARN][17] ([i915#180])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20940/shard-kbl7/igt@gem_workarou...@suspend-resume-fd.html

  * igt@gen9_exec_parse@bb-start-far:
- shard-iclb: NOTRUN -> [SKIP][18] ([i915#2856]) +1 similar issue
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20940/shard-iclb6/igt@gen9_exec_pa...@bb-start-far.html
- shard-tglb: NOTRUN -> [SKIP][19] ([i915#2856])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20940/shard-tglb6/igt@gen9_exec_pa...@bb-start-far.html

  * igt@i915_suspend@debugfs-reader:
- shard-kbl:  [PASS][20] ->

[Intel-gfx] ✓ Fi.CI.BAT: success for Clean up GuC CI failures, simplify locking, and kernel DOC (rev8)

[Patchwork]

== Series Details ==

Series: Clean up GuC CI failures, simplify locking, and kernel DOC (rev8)
URL   : https://patchwork.freedesktop.org/series/93704/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10544 -> Patchwork_20940


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20940/index.html

New tests
-

  New tests have been introduced between CI_DRM_10544 and Patchwork_20940:

### New IGT tests (1) ###

  * igt@i915_selftest@live@guc:
- Statuses : 33 pass(s)
- Exec time: [0.41, 3.59] s

  

Known issues


  Here are the changes found in Patchwork_20940 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-snb-2600:NOTRUN -> [SKIP][1] ([fdo#109271]) +37 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20940/fi-snb-2600/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_chamelium@hdmi-crc-fast:
- fi-snb-2600:NOTRUN -> [SKIP][2] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20940/fi-snb-2600/igt@kms_chamel...@hdmi-crc-fast.html

  
 Possible fixes 

  * igt@i915_pm_rpm@module-reload:
- fi-cfl-8109u:   [FAIL][3] ([i915#4054]) -> [PASS][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/fi-cfl-8109u/igt@i915_pm_...@module-reload.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20940/fi-cfl-8109u/igt@i915_pm_...@module-reload.html

  * igt@i915_selftest@live@execlists:
- fi-cfl-8109u:   [DMESG-WARN][5] ([i915#203]) -> [PASS][6] +4 similar 
issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/fi-cfl-8109u/igt@i915_selftest@l...@execlists.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20940/fi-cfl-8109u/igt@i915_selftest@l...@execlists.html

  
 Warnings 

  * igt@i915_pm_rpm@basic-pci-d3-state:
- fi-kbl-guc: [SKIP][7] ([fdo#109271]) -> [FAIL][8] ([i915#3049])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/fi-kbl-guc/igt@i915_pm_...@basic-pci-d3-state.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20940/fi-kbl-guc/igt@i915_pm_...@basic-pci-d3-state.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#203]: https://gitlab.freedesktop.org/drm/intel/issues/203
  [i915#3049]: https://gitlab.freedesktop.org/drm/intel/issues/3049
  [i915#4054]: https://gitlab.freedesktop.org/drm/intel/issues/4054


Participating hosts (42 -> 34)
--

  Additional (1): fi-snb-2600 
  Missing(9): fi-kbl-soraka fi-ilk-m540 bat-adls-5 bat-dg1-6 bat-dg1-5 
fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus bat-jsl-1 


Build changes
-

  * Linux: CI_DRM_10544 -> Patchwork_20940

  CI-20190529: 20190529
  CI_DRM_10544: 078e7300cf0130241e5d472d8e2f7eef4ef11b65 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6193: 080869f804cb86b25a38889e5ce9a870571cd8c4 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_20940: 03345c4aa1b77002fe893e80144ebf127ed83adc @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

03345c4aa1b7 drm/i915/guc: Add GuC kernel doc
7a1e8b049331 drm/i915/guc: Drop guc_active move everything into guc_state
2f2fb8824ce7 drm/i915/guc: Move fields protected by guc->contexts_lock into sub 
structure
6901d6d78c42 drm/i915/guc: Move GuC priority fields in context under guc_active
ec14694751cc drm/i915/guc: Drop pin count check trick between sched_disable and 
re-pin
2d753ce9f357 drm/i915/guc: Proper xarray usage for contexts_lookup
4c7f421d381a drm/i915/guc: Rework and simplify locking
064104f65f47 drm/i915/guc: Move guc_blocked fence to struct guc_state
efbc9c267ed2 drm/i915/guc: Release submit fence from an irq_work
f16ff82d9bef drm/i915/guc: Flush G2H work queue during reset
87be1fdc991f drm/i915: Allocate error capture in nowait context
76e31cf548b1 drm/i915/guc: Reset LRC descriptor if register returns -ENODEV
505c27859cd5 drm/i915/guc: Don't touch guc_state.sched_state without a lock
81160f40a055 drm/i915/guc: Take context ref when cancelling request
f65e8b30483f drm/i915/selftests: Add initial GuC selftest for scrubbing lost G2H
7fda30ff715f drm/i915/guc: Copy whole golden context, set engine state size of 
subset
27ee5f59d3e8 drm/i915/guc: Don't enable scheduling on a banned context, guc_id 
invalid, not registered
7890b2a82744 drm/i915/guc: Kick tasklet after queuing a request
469697335ccf Revert "drm/i915/gt: Propagate change in error status to children 
on unhold"
e3fe080cead5 drm/i915/guc: Workaround reset G2H is received after schedule done 
G2H
008bc855f8f5 drm/i915/guc: Process all G2H message at once in work queue
a83b1ac67822 drm/i915/guc

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Clean up GuC CI failures, simplify locking, and kernel DOC (rev8)

[Patchwork]

== Series Details ==

Series: Clean up GuC CI failures, simplify locking, and kernel DOC (rev8)
URL   : https://patchwork.freedesktop.org/series/93704/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+drivers/gpu/drm/i915/selftests/i915_syncmap.c:80:54: warning: dubious: x | !y

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Clean up GuC CI failures, simplify locking, and kernel DOC (rev8)

[Patchwork]

== Series Details ==

Series: Clean up GuC CI failures, simplify locking, and kernel DOC (rev8)
URL   : https://patchwork.freedesktop.org/series/93704/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
63fb5a2c9d8a drm/i915/guc: Fix blocked context accounting
58afa429a58a drm/i915/guc: Fix outstanding G2H accounting
94f527455e3b drm/i915/guc: Unwind context requests in reverse order
a83b1ac67822 drm/i915/guc: Don't drop ce->guc_active.lock when unwinding context
008bc855f8f5 drm/i915/guc: Process all G2H message at once in work queue
e3fe080cead5 drm/i915/guc: Workaround reset G2H is received after schedule done 
G2H
469697335ccf Revert "drm/i915/gt: Propagate change in error status to children 
on unhold"
-:8: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ 
chars of sha1> ("")' - ie: 'commit 3761baae908a ("Revert "drm/i915: 
Propagate errors on awaiting already signaled fences"")'
#8: 
errors from one client ending up in another.  In 3761baae908a (Revert

-:11: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ 
chars of sha1> ("")' - ie: 'commit 8e9f84cf5cac ("drm/i915/gt: 
Propagate change in error status to children on unhold")'
#11: 
added in 8e9f84cf5cac ("drm/i915/gt: Propagate change in error status

-:24: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description 
(prefer a maximum 75 chars per line)
#24: 
References: '3761baae908a ("Revert "drm/i915: Propagate errors on awaiting 
already signaled fences"")'

total: 2 errors, 1 warnings, 0 checks, 10 lines checked
7890b2a82744 drm/i915/guc: Kick tasklet after queuing a request
-:8: WARNING:TYPO_SPELLING: 'inteface' may be misspelled - perhaps 'interface'?
#8: 
Fixes: 3a4cdf1982f0 ("drm/i915/guc: Implement GuC context operations for new 
inteface")
 


total: 0 errors, 1 warnings, 0 checks, 7 lines checked
27ee5f59d3e8 drm/i915/guc: Don't enable scheduling on a banned context, guc_id 
invalid, not registered
7fda30ff715f drm/i915/guc: Copy whole golden context, set engine state size of 
subset
f65e8b30483f drm/i915/selftests: Add initial GuC selftest for scrubbing lost G2H
-:108: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#108: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 233 lines checked
81160f40a055 drm/i915/guc: Take context ref when cancelling request
505c27859cd5 drm/i915/guc: Don't touch guc_state.sched_state without a lock
76e31cf548b1 drm/i915/guc: Reset LRC descriptor if register returns -ENODEV
87be1fdc991f drm/i915: Allocate error capture in nowait context
f16ff82d9bef drm/i915/guc: Flush G2H work queue during reset
efbc9c267ed2 drm/i915/guc: Release submit fence from an irq_work
064104f65f47 drm/i915/guc: Move guc_blocked fence to struct guc_state
4c7f421d381a drm/i915/guc: Rework and simplify locking
2d753ce9f357 drm/i915/guc: Proper xarray usage for contexts_lookup
ec14694751cc drm/i915/guc: Drop pin count check trick between sched_disable and 
re-pin
6901d6d78c42 drm/i915/guc: Move GuC priority fields in context under guc_active
2f2fb8824ce7 drm/i915/guc: Move fields protected by guc->contexts_lock into sub 
structure
7a1e8b049331 drm/i915/guc: Drop guc_active move everything into guc_state
03345c4aa1b7 drm/i915/guc: Add GuC kernel doc
-:390: WARNING:REPEATED_WORD: Possible repeated word: 'range'
#390: FILE: drivers/gpu/drm/i915/i915_request.h:307:
+* GUC_PRIO_FINI) outside the GuC priority range range are used to

total: 0 errors, 1 warnings, 0 checks, 347 lines checked

[Intel-gfx] [PATCH v5 25/25] drm/i915/guc: Add GuC kernel doc

[Daniele Ceraolo Spurio]

From: Matthew Brost 

Add GuC kernel doc for all structures added thus far for GuC submission
and update the main GuC submission section with the new interface
details.

v2:
 - Drop guc_active.lock DOC
v3:
 - Fixup a few kernel doc comments (Daniele)
v4 (Daniele):
 - Implement doc suggestions from John
 - Add kerneldoc for all members of the GuC structure and pull the file
   in i915.rst

Signed-off-by: Matthew Brost 
Signed-off-by: Daniele Ceraolo Spurio 
Cc: John Harrison 
---
 Documentation/gpu/i915.rst|   2 +
 drivers/gpu/drm/i915/gt/intel_context_types.h |  43 +---
 drivers/gpu/drm/i915/gt/uc/intel_guc.h|  68 +---
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 100 ++
 drivers/gpu/drm/i915/i915_request.h   |  21 ++--
 5 files changed, 174 insertions(+), 60 deletions(-)

diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index 101dde3eb1ea..311e10400708 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -495,6 +495,8 @@ GuC
 .. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c
:doc: GuC
 
+.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.h
+
 GuC Firmware Layout
 ~~~
 
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h 
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index 5285d660eacf..930569a1a01f 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -156,40 +156,51 @@ struct intel_context {
u8 wa_bb_page; /* if set, page num reserved for context workarounds */
 
struct {
-   /** lock: protects everything in guc_state */
+   /** @lock: protects everything in guc_state */
spinlock_t lock;
/**
-* sched_state: scheduling state of this context using GuC
+* @sched_state: scheduling state of this context using GuC
 * submission
 */
u32 sched_state;
/*
-* fences: maintains of list of requests that have a submit
-* fence related to GuC submission
+* @fences: maintains a list of requests that are currently
+* being fenced until a GuC operation completes
 */
struct list_head fences;
-   /* GuC context blocked fence */
+   /**
+* @blocked: fence used to signal when the blocking of a
+* context's submissions is complete.
+*/
struct i915_sw_fence blocked;
-   /* GuC committed requests */
+   /** @number_committed_requests: number of committed requests */
int number_committed_requests;
-   /** requests: active requests on this context */
+   /** @requests: list of active requests on this context */
struct list_head requests;
-   /*
-* GuC priority management
-*/
+   /** @prio: the context's current guc priority */
u8 prio;
+   /**
+* @prio_count: a counter of the number requests in flight in
+* each priority bucket
+*/
u32 prio_count[GUC_CLIENT_PRIORITY_NUM];
} guc_state;
 
struct {
-   /* GuC LRC descriptor ID */
+   /**
+* @id: handle which is used to uniquely identify this context
+* with the GuC, protected by guc->contexts_lock
+*/
u16 id;
-
-   /* GuC LRC descriptor reference count */
+   /**
+* @ref: the number of references to the guc_id, when
+* transitioning in and out of zero protected by
+* guc->contexts_lock
+*/
atomic_t ref;
-
-   /*
-* GuC ID link - in list when unpinned but guc_id still valid 
in GuC
+   /**
+* @link: in guc->guc_id_list when the guc_id has no refs but is
+* still valid, protected by guc->contexts_lock
 */
struct list_head link;
} guc_id;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 2e27fe59786b..8427cd590087 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -22,74 +22,114 @@
 
 struct __guc_ads_blob;
 
-/*
- * Top level structure of GuC. It handles firmware loading and manages client
- * pool. intel_guc owns a intel_guc_client to replace the legacy ExecList
- * submission.
+/**
+ * struct intel_guc - Top level structure of GuC.
+ *
+ * It handles firmware loading and manages client pool. intel_guc owns an
+ * i915_sched_engine to replace the legacy ExecList submission.
  */
 struct intel_guc {
+   

[Intel-gfx] [PATCH v5 18/25] drm/i915/guc: Move guc_blocked fence to struct guc_state

[Daniele Ceraolo Spurio]

From: Matthew Brost 

Move guc_blocked fence to struct guc_state as the lock which protects
the fence lives there.

s/ce->guc_blocked/ce->guc_state.blocked/g

v2:
 (Daniele)
  - s/blocked_fence/blocked/g

Reviewed-by: Daniele Ceraolo Spurio 
Signed-off-by: Matthew Brost 
---
 drivers/gpu/drm/i915/gt/intel_context.c|  5 +++--
 drivers/gpu/drm/i915/gt/intel_context_types.h  |  5 ++---
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c  | 18 +-
 3 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_context.c 
b/drivers/gpu/drm/i915/gt/intel_context.c
index 745e84c72c90..3048267ddc7e 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -405,8 +405,9 @@ intel_context_init(struct intel_context *ce, struct 
intel_engine_cs *engine)
 * Initialize fence to be complete as this is expected to be complete
 * unless there is a pending schedule disable outstanding.
 */
-   i915_sw_fence_init(&ce->guc_blocked, sw_fence_dummy_notify);
-   i915_sw_fence_commit(&ce->guc_blocked);
+   i915_sw_fence_init(&ce->guc_state.blocked,
+  sw_fence_dummy_notify);
+   i915_sw_fence_commit(&ce->guc_state.blocked);
 
i915_active_init(&ce->active,
 __intel_context_active, __intel_context_retire, 0);
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h 
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index 3a73f3117873..5aecb9038b5b 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -167,6 +167,8 @@ struct intel_context {
 * fence related to GuC submission
 */
struct list_head fences;
+   /* GuC context blocked fence */
+   struct i915_sw_fence blocked;
} guc_state;
 
struct {
@@ -190,9 +192,6 @@ struct intel_context {
 */
struct list_head guc_id_link;
 
-   /* GuC context blocked fence */
-   struct i915_sw_fence guc_blocked;
-
/*
 * GuC priority management
 */
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 7c7cbd57d568..38068d5851e2 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1488,24 +1488,24 @@ static void guc_blocked_fence_complete(struct 
intel_context *ce)
 {
lockdep_assert_held(&ce->guc_state.lock);
 
-   if (!i915_sw_fence_done(&ce->guc_blocked))
-   i915_sw_fence_complete(&ce->guc_blocked);
+   if (!i915_sw_fence_done(&ce->guc_state.blocked))
+   i915_sw_fence_complete(&ce->guc_state.blocked);
 }
 
 static void guc_blocked_fence_reinit(struct intel_context *ce)
 {
lockdep_assert_held(&ce->guc_state.lock);
-   GEM_BUG_ON(!i915_sw_fence_done(&ce->guc_blocked));
+   GEM_BUG_ON(!i915_sw_fence_done(&ce->guc_state.blocked));
 
/*
 * This fence is always complete unless a pending schedule disable is
 * outstanding. We arm the fence here and complete it when we receive
 * the pending schedule disable complete message.
 */
-   i915_sw_fence_fini(&ce->guc_blocked);
-   i915_sw_fence_reinit(&ce->guc_blocked);
-   i915_sw_fence_await(&ce->guc_blocked);
-   i915_sw_fence_commit(&ce->guc_blocked);
+   i915_sw_fence_fini(&ce->guc_state.blocked);
+   i915_sw_fence_reinit(&ce->guc_state.blocked);
+   i915_sw_fence_await(&ce->guc_state.blocked);
+   i915_sw_fence_commit(&ce->guc_state.blocked);
 }
 
 static u16 prep_context_pending_disable(struct intel_context *ce)
@@ -1545,7 +1545,7 @@ static struct i915_sw_fence *guc_context_block(struct 
intel_context *ce)
if (enabled)
clr_context_enabled(ce);
spin_unlock_irqrestore(&ce->guc_state.lock, flags);
-   return &ce->guc_blocked;
+   return &ce->guc_state.blocked;
}
 
/*
@@ -1561,7 +1561,7 @@ static struct i915_sw_fence *guc_context_block(struct 
intel_context *ce)
with_intel_runtime_pm(runtime_pm, wakeref)
__guc_context_sched_disable(guc, ce, guc_id);
 
-   return &ce->guc_blocked;
+   return &ce->guc_state.blocked;
 }
 
 #define SCHED_STATE_MULTI_BLOCKED_MASK \
-- 
2.25.1

[Intel-gfx] [PATCH v5 24/25] drm/i915/guc: Drop guc_active move everything into guc_state

[Daniele Ceraolo Spurio]

From: Matthew Brost 

Now that we have locking hierarchy of sched_engine->lock ->
ce->guc_state everything from guc_active can be moved into guc_state and
protected the guc_state.lock.

Signed-off-by: Matthew Brost 
Reviewed-by: Daniele Ceraolo Spurio 
---
 drivers/gpu/drm/i915/gt/intel_context.c   | 10 +--
 drivers/gpu/drm/i915/gt/intel_context_types.h |  7 +-
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 88 +--
 drivers/gpu/drm/i915/i915_trace.h |  2 +-
 4 files changed, 49 insertions(+), 58 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_context.c 
b/drivers/gpu/drm/i915/gt/intel_context.c
index 485460a11331..ff637147b1a9 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -394,9 +394,7 @@ intel_context_init(struct intel_context *ce, struct 
intel_engine_cs *engine)
 
spin_lock_init(&ce->guc_state.lock);
INIT_LIST_HEAD(&ce->guc_state.fences);
-
-   spin_lock_init(&ce->guc_active.lock);
-   INIT_LIST_HEAD(&ce->guc_active.requests);
+   INIT_LIST_HEAD(&ce->guc_state.requests);
 
ce->guc_id.id = GUC_INVALID_LRC_ID;
INIT_LIST_HEAD(&ce->guc_id.link);
@@ -521,15 +519,15 @@ struct i915_request 
*intel_context_find_active_request(struct intel_context *ce)
 
GEM_BUG_ON(!intel_engine_uses_guc(ce->engine));
 
-   spin_lock_irqsave(&ce->guc_active.lock, flags);
-   list_for_each_entry_reverse(rq, &ce->guc_active.requests,
+   spin_lock_irqsave(&ce->guc_state.lock, flags);
+   list_for_each_entry_reverse(rq, &ce->guc_state.requests,
sched.link) {
if (i915_request_completed(rq))
break;
 
active = rq;
}
-   spin_unlock_irqrestore(&ce->guc_active.lock, flags);
+   spin_unlock_irqrestore(&ce->guc_state.lock, flags);
 
return active;
 }
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h 
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index 0b00d249c884..5285d660eacf 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -172,11 +172,6 @@ struct intel_context {
struct i915_sw_fence blocked;
/* GuC committed requests */
int number_committed_requests;
-   } guc_state;
-
-   struct {
-   /** lock: protects everything in guc_active */
-   spinlock_t lock;
/** requests: active requests on this context */
struct list_head requests;
/*
@@ -184,7 +179,7 @@ struct intel_context {
 */
u8 prio;
u32 prio_count[GUC_CLIENT_PRIORITY_NUM];
-   } guc_active;
+   } guc_state;
 
struct {
/* GuC LRC descriptor ID */
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 5a3435c041d1..6a894c3b7925 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -829,9 +829,9 @@ __unwind_incomplete_requests(struct intel_context *ce)
unsigned long flags;
 
spin_lock_irqsave(&sched_engine->lock, flags);
-   spin_lock(&ce->guc_active.lock);
+   spin_lock(&ce->guc_state.lock);
list_for_each_entry_safe_reverse(rq, rn,
-&ce->guc_active.requests,
+&ce->guc_state.requests,
 sched.link) {
if (i915_request_completed(rq))
continue;
@@ -850,7 +850,7 @@ __unwind_incomplete_requests(struct intel_context *ce)
list_add(&rq->sched.link, pl);
set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
}
-   spin_unlock(&ce->guc_active.lock);
+   spin_unlock(&ce->guc_state.lock);
spin_unlock_irqrestore(&sched_engine->lock, flags);
 }
 
@@ -945,10 +945,10 @@ static void guc_cancel_context_requests(struct 
intel_context *ce)
 
/* Mark all executing requests as skipped. */
spin_lock_irqsave(&sched_engine->lock, flags);
-   spin_lock(&ce->guc_active.lock);
-   list_for_each_entry(rq, &ce->guc_active.requests, sched.link)
+   spin_lock(&ce->guc_state.lock);
+   list_for_each_entry(rq, &ce->guc_state.requests, sched.link)
i915_request_put(i915_request_mark_eio(rq));
-   spin_unlock(&ce->guc_active.lock);
+   spin_unlock(&ce->guc_state.lock);
spin_unlock_irqrestore(&sched_engine->lock, flags);
 }
 
@@ -1399,7 +1399,7 @@ static int guc_lrc_desc_pin(struct intel_context *ce, 
bool loop)
desc->engine_submit_mask = adjust_engine_mask(engine->class,
  engine->mask);
desc->hw_context_desc = ce->lrc.lrca;
-   desc->priority = ce->guc_active.pr

[Intel-gfx] [PATCH v5 22/25] drm/i915/guc: Move GuC priority fields in context under guc_active

[Daniele Ceraolo Spurio]

From: Matthew Brost 

Move GuC management fields in context under guc_active struct as this is
where the lock that protects theses fields lives. Also only set guc_prio
field once during context init.

v2:
 (Daniele)
  - set CONTEXT_SET_INIT

Signed-off-by: Matthew Brost 
Reviewed-by: Daniele Ceraolo Spurio 
---
 drivers/gpu/drm/i915/gt/intel_context_types.h | 12 ++--
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 69 +++
 drivers/gpu/drm/i915/i915_trace.h |  2 +-
 3 files changed, 46 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h 
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index 3a5d98e908f4..b56960a781da 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -112,6 +112,7 @@ struct intel_context {
 #define CONTEXT_FORCE_SINGLE_SUBMISSION7
 #define CONTEXT_NOPREEMPT  8
 #define CONTEXT_LRCA_DIRTY 9
+#define CONTEXT_GUC_INIT   10
 
struct {
u64 timeout_us;
@@ -178,6 +179,11 @@ struct intel_context {
spinlock_t lock;
/** requests: active requests on this context */
struct list_head requests;
+   /*
+* GuC priority management
+*/
+   u8 prio;
+   u32 prio_count[GUC_CLIENT_PRIORITY_NUM];
} guc_active;
 
/* GuC LRC descriptor ID */
@@ -191,12 +197,6 @@ struct intel_context {
 */
struct list_head guc_id_link;
 
-   /*
-* GuC priority management
-*/
-   u8 guc_prio;
-   u32 guc_prio_count[GUC_CLIENT_PRIORITY_NUM];
-
 #ifdef CONFIG_DRM_I915_SELFTEST
/**
 * @drop_schedule_enable: Force drop of schedule enable G2H for selftest
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 440ddcaae627..7f8472ae3f19 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1368,8 +1368,6 @@ static void guc_context_policy_init(struct 
intel_engine_cs *engine,
desc->preemption_timeout = engine->props.preempt_timeout_ms * 1000;
 }
 
-static inline u8 map_i915_prio_to_guc_prio(int prio);
-
 static int guc_lrc_desc_pin(struct intel_context *ce, bool loop)
 {
struct intel_engine_cs *engine = ce->engine;
@@ -1377,8 +1375,6 @@ static int guc_lrc_desc_pin(struct intel_context *ce, 
bool loop)
struct intel_guc *guc = &engine->gt->uc.guc;
u32 desc_idx = ce->guc_id;
struct guc_lrc_desc *desc;
-   const struct i915_gem_context *ctx;
-   int prio = I915_CONTEXT_DEFAULT_PRIORITY;
bool context_registered;
intel_wakeref_t wakeref;
int ret = 0;
@@ -1395,12 +1391,6 @@ static int guc_lrc_desc_pin(struct intel_context *ce, 
bool loop)
 
context_registered = lrc_desc_registered(guc, desc_idx);
 
-   rcu_read_lock();
-   ctx = rcu_dereference(ce->gem_context);
-   if (ctx)
-   prio = ctx->sched.priority;
-   rcu_read_unlock();
-
reset_lrc_desc(guc, desc_idx);
set_lrc_desc_registered(guc, desc_idx, ce);
 
@@ -1409,8 +1399,7 @@ static int guc_lrc_desc_pin(struct intel_context *ce, 
bool loop)
desc->engine_submit_mask = adjust_engine_mask(engine->class,
  engine->mask);
desc->hw_context_desc = ce->lrc.lrca;
-   ce->guc_prio = map_i915_prio_to_guc_prio(prio);
-   desc->priority = ce->guc_prio;
+   desc->priority = ce->guc_active.prio;
desc->context_flags = CONTEXT_REGISTRATION_FLAG_KMD;
guc_context_policy_init(engine, desc);
 
@@ -1805,10 +1794,10 @@ static inline void guc_lrc_desc_unpin(struct 
intel_context *ce)
 
 static void __guc_context_destroy(struct intel_context *ce)
 {
-   GEM_BUG_ON(ce->guc_prio_count[GUC_CLIENT_PRIORITY_KMD_HIGH] ||
-  ce->guc_prio_count[GUC_CLIENT_PRIORITY_HIGH] ||
-  ce->guc_prio_count[GUC_CLIENT_PRIORITY_KMD_NORMAL] ||
-  ce->guc_prio_count[GUC_CLIENT_PRIORITY_NORMAL]);
+   GEM_BUG_ON(ce->guc_active.prio_count[GUC_CLIENT_PRIORITY_KMD_HIGH] ||
+  ce->guc_active.prio_count[GUC_CLIENT_PRIORITY_HIGH] ||
+  ce->guc_active.prio_count[GUC_CLIENT_PRIORITY_KMD_NORMAL] ||
+  ce->guc_active.prio_count[GUC_CLIENT_PRIORITY_NORMAL]);
GEM_BUG_ON(ce->guc_state.number_committed_requests);
 
lrc_fini(ce);
@@ -1918,14 +1907,17 @@ static void guc_context_set_prio(struct intel_guc *guc,
 
GEM_BUG_ON(prio < GUC_CLIENT_PRIORITY_KMD_HIGH ||
   prio > GUC_CLIENT_PRIORITY_NORMAL);
+   lockdep_assert_held(&ce->guc_active.lock);
 
-   if (ce->guc_prio == prio || submission_disabled(guc) ||
-   !context_registered(ce))
+   if (ce->guc_active.prio == pri

[Intel-gfx] [PATCH v5 23/25] drm/i915/guc: Move fields protected by guc->contexts_lock into sub structure

[Daniele Ceraolo Spurio]

From: Matthew Brost 

To make ownership of locking clear move fields (guc_id, guc_id_ref,
guc_id_link) to sub structure guc_id in intel_context.

Reviewed-by: Daniele Ceraolo Spurio 
Signed-off-by: Matthew Brost 
---
 drivers/gpu/drm/i915/gt/intel_context.c   |   4 +-
 drivers/gpu/drm/i915/gt/intel_context_types.h |  18 +--
 drivers/gpu/drm/i915/gt/selftest_hangcheck.c  |   6 +-
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 104 +-
 drivers/gpu/drm/i915/i915_trace.h |   4 +-
 5 files changed, 69 insertions(+), 67 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_context.c 
b/drivers/gpu/drm/i915/gt/intel_context.c
index 3048267ddc7e..485460a11331 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -398,8 +398,8 @@ intel_context_init(struct intel_context *ce, struct 
intel_engine_cs *engine)
spin_lock_init(&ce->guc_active.lock);
INIT_LIST_HEAD(&ce->guc_active.requests);
 
-   ce->guc_id = GUC_INVALID_LRC_ID;
-   INIT_LIST_HEAD(&ce->guc_id_link);
+   ce->guc_id.id = GUC_INVALID_LRC_ID;
+   INIT_LIST_HEAD(&ce->guc_id.link);
 
/*
 * Initialize fence to be complete as this is expected to be complete
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h 
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index b56960a781da..0b00d249c884 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -186,16 +186,18 @@ struct intel_context {
u32 prio_count[GUC_CLIENT_PRIORITY_NUM];
} guc_active;
 
-   /* GuC LRC descriptor ID */
-   u16 guc_id;
+   struct {
+   /* GuC LRC descriptor ID */
+   u16 id;
 
-   /* GuC LRC descriptor reference count */
-   atomic_t guc_id_ref;
+   /* GuC LRC descriptor reference count */
+   atomic_t ref;
 
-   /*
-* GuC ID link - in list when unpinned but guc_id still valid in GuC
-*/
-   struct list_head guc_id_link;
+   /*
+* GuC ID link - in list when unpinned but guc_id still valid 
in GuC
+*/
+   struct list_head link;
+   } guc_id;
 
 #ifdef CONFIG_DRM_I915_SELFTEST
/**
diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c 
b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
index 2c1ed32ca5ac..e9130fa39616 100644
--- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
@@ -789,7 +789,7 @@ static int __igt_reset_engine(struct intel_gt *gt, bool 
active)
if (err)
pr_err("[%s] Wait for request %lld:%lld 
[0x%04X] failed: %d!\n",
   engine->name, rq->fence.context,
-  rq->fence.seqno, 
rq->context->guc_id, err);
+  rq->fence.seqno, 
rq->context->guc_id.id, err);
}
 
 skip:
@@ -1098,7 +1098,7 @@ static int __igt_reset_engines(struct intel_gt *gt,
if (err)
pr_err("[%s] Wait for request %lld:%lld 
[0x%04X] failed: %d!\n",
   engine->name, rq->fence.context,
-  rq->fence.seqno, 
rq->context->guc_id, err);
+  rq->fence.seqno, 
rq->context->guc_id.id, err);
}
 
count++;
@@ -1108,7 +1108,7 @@ static int __igt_reset_engines(struct intel_gt *gt,
pr_err("i915_reset_engine(%s:%s): 
failed to reset request %lld:%lld [0x%04X]\n",
   engine->name, test_name,
   rq->fence.context,
-  rq->fence.seqno, 
rq->context->guc_id);
+  rq->fence.seqno, 
rq->context->guc_id.id);
i915_request_put(rq);
 
GEM_TRACE_DUMP();
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 7f8472ae3f19..5a3435c041d1 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -270,12 +270,12 @@ static inline void decr_context_committed_requests(struct 
intel_context *ce)
 
 static inline bool context_guc_id_invalid(struct intel_context *ce)
 {
-   return ce->guc_id == GUC_INVALID_LRC_ID;
+   return ce->guc_id.id == GUC_INVALID_LRC_ID;
 }
 
 static inline void set_context_guc_id_invalid(struct intel_context *ce)
 {
-   ce->guc_id = GUC_INVALID_LRC_ID;
+   ce->guc_id.id = GUC_INVALID_LRC_ID;
 }
 
 static inline 

[Intel-gfx] [PATCH v5 20/25] drm/i915/guc: Proper xarray usage for contexts_lookup

[Daniele Ceraolo Spurio]

From: Matthew Brost 

Lock the xarray and take ref to the context if needed.

v2:
 (Checkpatch)
  - Add new line after declaration
 (Daniel Vetter)
  - Correct put / get accounting in xa_for_loops
v3:
 (Checkpatch)
  - Extra new line

Reviewed-by: Daniele Ceraolo Spurio 
Signed-off-by: Matthew Brost 
---
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 102 +++---
 1 file changed, 87 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 3062406503d8..987aec197658 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -608,8 +608,18 @@ static void scrub_guc_desc_for_outstanding_g2h(struct 
intel_guc *guc)
unsigned long index, flags;
bool pending_disable, pending_enable, deregister, destroyed, banned;
 
+   xa_lock_irqsave(&guc->context_lookup, flags);
xa_for_each(&guc->context_lookup, index, ce) {
-   spin_lock_irqsave(&ce->guc_state.lock, flags);
+   /*
+* Corner case where the ref count on the object is zero but and
+* deregister G2H was lost. In this case we don't touch the ref
+* count and finish the destroy of the context.
+*/
+   bool do_put = kref_get_unless_zero(&ce->ref);
+
+   xa_unlock(&guc->context_lookup);
+
+   spin_lock(&ce->guc_state.lock);
 
/*
 * Once we are at this point submission_disabled() is guaranteed
@@ -625,7 +635,9 @@ static void scrub_guc_desc_for_outstanding_g2h(struct 
intel_guc *guc)
banned = context_banned(ce);
init_sched_state(ce);
 
-   spin_unlock_irqrestore(&ce->guc_state.lock, flags);
+   spin_unlock(&ce->guc_state.lock);
+
+   GEM_BUG_ON(!do_put && !destroyed);
 
if (pending_enable || destroyed || deregister) {
decr_outstanding_submission_g2h(guc);
@@ -648,13 +660,19 @@ static void scrub_guc_desc_for_outstanding_g2h(struct 
intel_guc *guc)
}
intel_context_sched_disable_unpin(ce);
decr_outstanding_submission_g2h(guc);
-   spin_lock_irqsave(&ce->guc_state.lock, flags);
+
+   spin_lock(&ce->guc_state.lock);
guc_blocked_fence_complete(ce);
-   spin_unlock_irqrestore(&ce->guc_state.lock, flags);
+   spin_unlock(&ce->guc_state.lock);
 
intel_context_put(ce);
}
+
+   if (do_put)
+   intel_context_put(ce);
+   xa_lock(&guc->context_lookup);
}
+   xa_unlock_irqrestore(&guc->context_lookup, flags);
 }
 
 static inline bool
@@ -873,16 +891,29 @@ void intel_guc_submission_reset(struct intel_guc *guc, 
bool stalled)
 {
struct intel_context *ce;
unsigned long index;
+   unsigned long flags;
 
if (unlikely(!guc_submission_initialized(guc))) {
/* Reset called during driver load? GuC not yet initialised! */
return;
}
 
-   xa_for_each(&guc->context_lookup, index, ce)
+   xa_lock_irqsave(&guc->context_lookup, flags);
+   xa_for_each(&guc->context_lookup, index, ce) {
+   if (!kref_get_unless_zero(&ce->ref))
+   continue;
+
+   xa_unlock(&guc->context_lookup);
+
if (intel_context_is_pinned(ce))
__guc_reset_context(ce, stalled);
 
+   intel_context_put(ce);
+
+   xa_lock(&guc->context_lookup);
+   }
+   xa_unlock_irqrestore(&guc->context_lookup, flags);
+
/* GuC is blown away, drop all references to contexts */
xa_destroy(&guc->context_lookup);
 }
@@ -957,11 +988,24 @@ void intel_guc_submission_cancel_requests(struct 
intel_guc *guc)
 {
struct intel_context *ce;
unsigned long index;
+   unsigned long flags;
+
+   xa_lock_irqsave(&guc->context_lookup, flags);
+   xa_for_each(&guc->context_lookup, index, ce) {
+   if (!kref_get_unless_zero(&ce->ref))
+   continue;
+
+   xa_unlock(&guc->context_lookup);
 
-   xa_for_each(&guc->context_lookup, index, ce)
if (intel_context_is_pinned(ce))
guc_cancel_context_requests(ce);
 
+   intel_context_put(ce);
+
+   xa_lock(&guc->context_lookup);
+   }
+   xa_unlock_irqrestore(&guc->context_lookup, flags);
+
guc_cancel_sched_engine_requests(guc->sched_engine);
 
/* GuC is blown away, drop all references to contexts */
@@ -2849,21 +2893,28 @@ void intel_guc_find_hung_context(struct intel_engine_cs 
*engine)
struct intel_context *ce;
struct i915_

[Intel-gfx] [PATCH v5 19/25] drm/i915/guc: Rework and simplify locking

[Daniele Ceraolo Spurio]

From: Matthew Brost 

Rework and simplify the locking with GuC subission. Drop
sched_state_no_lock and move all fields under the guc_state.sched_state
and protect all these fields with guc_state.lock . This requires
changing the locking hierarchy from guc_state.lock -> sched_engine.lock
to sched_engine.lock -> guc_state.lock.

v2:
 (Daniele)
  - Don't check fields outside of lock during sched disable, check less
fields within lock as some of the outside are no longer needed

Reviewed-by: Daniele Ceraolo Spurio 
Signed-off-by: Matthew Brost 
---
 drivers/gpu/drm/i915/gt/intel_context_types.h |   5 +-
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 200 --
 drivers/gpu/drm/i915/i915_trace.h |   6 +-
 3 files changed, 89 insertions(+), 122 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h 
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index 5aecb9038b5b..d2f798ef678c 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -161,7 +161,7 @@ struct intel_context {
 * sched_state: scheduling state of this context using GuC
 * submission
 */
-   u16 sched_state;
+   u32 sched_state;
/*
 * fences: maintains of list of requests that have a submit
 * fence related to GuC submission
@@ -178,9 +178,6 @@ struct intel_context {
struct list_head requests;
} guc_active;
 
-   /* GuC scheduling state flags that do not require a lock. */
-   atomic_t guc_sched_state_no_lock;
-
/* GuC LRC descriptor ID */
u16 guc_id;
 
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 38068d5851e2..3062406503d8 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -72,87 +72,24 @@ guc_create_virtual(struct intel_engine_cs **siblings, 
unsigned int count);
 
 #define GUC_REQUEST_SIZE 64 /* bytes */
 
-/*
- * Below is a set of functions which control the GuC scheduling state which do
- * not require a lock as all state transitions are mutually exclusive. i.e. It
- * is not possible for the context pinning code and submission, for the same
- * context, to be executing simultaneously. We still need an atomic as it is
- * possible for some of the bits to changing at the same time though.
- */
-#define SCHED_STATE_NO_LOCK_ENABLEDBIT(0)
-#define SCHED_STATE_NO_LOCK_PENDING_ENABLE BIT(1)
-#define SCHED_STATE_NO_LOCK_REGISTERED BIT(2)
-static inline bool context_enabled(struct intel_context *ce)
-{
-   return (atomic_read(&ce->guc_sched_state_no_lock) &
-   SCHED_STATE_NO_LOCK_ENABLED);
-}
-
-static inline void set_context_enabled(struct intel_context *ce)
-{
-   atomic_or(SCHED_STATE_NO_LOCK_ENABLED, &ce->guc_sched_state_no_lock);
-}
-
-static inline void clr_context_enabled(struct intel_context *ce)
-{
-   atomic_and((u32)~SCHED_STATE_NO_LOCK_ENABLED,
-  &ce->guc_sched_state_no_lock);
-}
-
-static inline bool context_pending_enable(struct intel_context *ce)
-{
-   return (atomic_read(&ce->guc_sched_state_no_lock) &
-   SCHED_STATE_NO_LOCK_PENDING_ENABLE);
-}
-
-static inline void set_context_pending_enable(struct intel_context *ce)
-{
-   atomic_or(SCHED_STATE_NO_LOCK_PENDING_ENABLE,
- &ce->guc_sched_state_no_lock);
-}
-
-static inline void clr_context_pending_enable(struct intel_context *ce)
-{
-   atomic_and((u32)~SCHED_STATE_NO_LOCK_PENDING_ENABLE,
-  &ce->guc_sched_state_no_lock);
-}
-
-static inline bool context_registered(struct intel_context *ce)
-{
-   return (atomic_read(&ce->guc_sched_state_no_lock) &
-   SCHED_STATE_NO_LOCK_REGISTERED);
-}
-
-static inline void set_context_registered(struct intel_context *ce)
-{
-   atomic_or(SCHED_STATE_NO_LOCK_REGISTERED,
- &ce->guc_sched_state_no_lock);
-}
-
-static inline void clr_context_registered(struct intel_context *ce)
-{
-   atomic_and((u32)~SCHED_STATE_NO_LOCK_REGISTERED,
-  &ce->guc_sched_state_no_lock);
-}
-
 /*
  * Below is a set of functions which control the GuC scheduling state which
- * require a lock, aside from the special case where the functions are called
- * from guc_lrc_desc_pin(). In that case it isn't possible for any other code
- * path to be executing on the context.
+ * require a lock.
  */
 #define SCHED_STATE_WAIT_FOR_DEREGISTER_TO_REGISTERBIT(0)
 #define SCHED_STATE_DESTROYED  BIT(1)
 #define SCHED_STATE_PENDING_DISABLEBIT(2)
 #define SCHED_STATE_BANNED BIT(3)
-#define SCHED_STATE_BLOCKED_SHIFT  4
+#define SCHED_STATE_ENABLEDBIT(4)
+#defin

[Intel-gfx] [PATCH v5 21/25] drm/i915/guc: Drop pin count check trick between sched_disable and re-pin

[Daniele Ceraolo Spurio]

From: Matthew Brost 

Drop pin count check trick between a sched_disable and re-pin, now rely
on the lock and counter of the number of committed requests to determine
if scheduling should be disabled on the context.

Reviewed-by: Daniele Ceraolo Spurio 
Signed-off-by: Matthew Brost 
---
 drivers/gpu/drm/i915/gt/intel_context_types.h |  2 +
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 53 +++
 2 files changed, 34 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h 
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index d2f798ef678c..3a5d98e908f4 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -169,6 +169,8 @@ struct intel_context {
struct list_head fences;
/* GuC context blocked fence */
struct i915_sw_fence blocked;
+   /* GuC committed requests */
+   int number_committed_requests;
} guc_state;
 
struct {
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 987aec197658..440ddcaae627 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -249,6 +249,25 @@ static inline void decr_context_blocked(struct 
intel_context *ce)
ce->guc_state.sched_state -= SCHED_STATE_BLOCKED;
 }
 
+static inline bool context_has_committed_requests(struct intel_context *ce)
+{
+   return !!ce->guc_state.number_committed_requests;
+}
+
+static inline void incr_context_committed_requests(struct intel_context *ce)
+{
+   lockdep_assert_held(&ce->guc_state.lock);
+   ++ce->guc_state.number_committed_requests;
+   GEM_BUG_ON(ce->guc_state.number_committed_requests < 0);
+}
+
+static inline void decr_context_committed_requests(struct intel_context *ce)
+{
+   lockdep_assert_held(&ce->guc_state.lock);
+   --ce->guc_state.number_committed_requests;
+   GEM_BUG_ON(ce->guc_state.number_committed_requests < 0);
+}
+
 static inline bool context_guc_id_invalid(struct intel_context *ce)
 {
return ce->guc_id == GUC_INVALID_LRC_ID;
@@ -1749,24 +1768,18 @@ static void guc_context_sched_disable(struct 
intel_context *ce)
spin_lock_irqsave(&ce->guc_state.lock, flags);
 
/*
-* We have to check if the context has been disabled by another thread.
-* We also have to check if the context has been pinned again as another
-* pin operation is allowed to pass this function. Checking the pin
-* count, within ce->guc_state.lock, synchronizes this function with
-* guc_request_alloc ensuring a request doesn't slip through the
-* 'context_pending_disable' fence. Checking within the spin lock (can't
-* sleep) ensures another process doesn't pin this context and generate
-* a request before we set the 'context_pending_disable' flag here.
+* We have to check if the context has been disabled by another thread,
+* check if submssion has been disabled to seal a race with reset and
+* finally check if any more requests have been committed to the
+* context ensursing that a request doesn't slip through the
+* 'context_pending_disable' fence.
 */
-   if (unlikely(!context_enabled(ce) || submission_disabled(guc))) {
+   if (unlikely(!context_enabled(ce) || submission_disabled(guc) ||
+context_has_committed_requests(ce))) {
clr_context_enabled(ce);
spin_unlock_irqrestore(&ce->guc_state.lock, flags);
goto unpin;
}
-   if (unlikely(atomic_add_unless(&ce->pin_count, -2, 2))) {
-   spin_unlock_irqrestore(&ce->guc_state.lock, flags);
-   return;
-   }
guc_id = prep_context_pending_disable(ce);
 
spin_unlock_irqrestore(&ce->guc_state.lock, flags);
@@ -1796,6 +1809,7 @@ static void __guc_context_destroy(struct intel_context 
*ce)
   ce->guc_prio_count[GUC_CLIENT_PRIORITY_HIGH] ||
   ce->guc_prio_count[GUC_CLIENT_PRIORITY_KMD_NORMAL] ||
   ce->guc_prio_count[GUC_CLIENT_PRIORITY_NORMAL]);
+   GEM_BUG_ON(ce->guc_state.number_committed_requests);
 
lrc_fini(ce);
intel_context_fini(ce);
@@ -2026,6 +2040,10 @@ static void remove_from_context(struct i915_request *rq)
 
spin_unlock_irq(&ce->guc_active.lock);
 
+   spin_lock_irq(&ce->guc_state.lock);
+   decr_context_committed_requests(ce);
+   spin_unlock_irq(&ce->guc_state.lock);
+
atomic_dec(&ce->guc_id_ref);
i915_request_notify_execute_cb_imm(rq);
 }
@@ -2176,15 +2194,7 @@ static int guc_request_alloc(struct i915_request *rq)
 * schedule enable or context registration if either G2H is pending
 * respectfully. Once a G2H returns, the fence is released that is
 * blocking

[Intel-gfx] [PATCH v5 12/25] drm/i915/guc: Take context ref when cancelling request

[Daniele Ceraolo Spurio]

From: Matthew Brost 

A context can get destroyed after cancelling a request, if a context or
GT reset occurs, so take a reference to context when cancelling a
request.

Fixes: 62eaf0ae217d ("drm/i915/guc: Support request cancellation")
Signed-off-by: Matthew Brost 
Reviewed-by: Daniele Ceraolo Spurio 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 5970c54a2e72..e036a171ff17 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1624,8 +1624,10 @@ static void guc_context_cancel_request(struct 
intel_context *ce,
   struct i915_request *rq)
 {
if (i915_sw_fence_signaled(&rq->submit)) {
-   struct i915_sw_fence *fence = guc_context_block(ce);
+   struct i915_sw_fence *fence;
 
+   intel_context_get(ce);
+   fence = guc_context_block(ce);
i915_sw_fence_wait(fence);
if (!i915_request_completed(rq)) {
__i915_request_skip(rq);
@@ -1640,6 +1642,7 @@ static void guc_context_cancel_request(struct 
intel_context *ce,
flush_work(&ce_to_guc(ce)->ct.requests.worker);
 
guc_context_unblock(ce);
+   intel_context_put(ce);
}
 }
 
-- 
2.25.1

[Intel-gfx] [PATCH v5 17/25] drm/i915/guc: Release submit fence from an irq_work

[Daniele Ceraolo Spurio]

From: Matthew Brost 

A subsequent patch will flip the locking hierarchy from
ce->guc_state.lock -> sched_engine->lock to sched_engine->lock ->
ce->guc_state.lock. As such we need to release the submit fence for a
request from an IRQ to break a lock inversion - i.e. the fence must be
release went holding ce->guc_state.lock and the releasing of the can
acquire sched_engine->lock.

v2:
 (Daniele)
  - Delete request from list before calling irq_work_queue

Reviewed-by: Daniele Ceraolo Spurio 
Signed-off-by: Matthew Brost 
---
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 22 ---
 drivers/gpu/drm/i915/i915_request.h   |  5 +
 2 files changed, 24 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 8509e827a8d0..7c7cbd57d568 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -2035,17 +2035,32 @@ static const struct intel_context_ops guc_context_ops = 
{
.create_virtual = guc_create_virtual,
 };
 
+static void submit_work_cb(struct irq_work *wrk)
+{
+   struct i915_request *rq = container_of(wrk, typeof(*rq), submit_work);
+
+   might_lock(&rq->engine->sched_engine->lock);
+   i915_sw_fence_complete(&rq->submit);
+}
+
 static void __guc_signal_context_fence(struct intel_context *ce)
 {
-   struct i915_request *rq;
+   struct i915_request *rq, *rn;
 
lockdep_assert_held(&ce->guc_state.lock);
 
if (!list_empty(&ce->guc_state.fences))
trace_intel_context_fence_release(ce);
 
-   list_for_each_entry(rq, &ce->guc_state.fences, guc_fence_link)
-   i915_sw_fence_complete(&rq->submit);
+   /*
+* Use an IRQ to ensure locking order of sched_engine->lock ->
+* ce->guc_state.lock is preserved.
+*/
+   list_for_each_entry_safe(rq, rn, &ce->guc_state.fences,
+guc_fence_link) {
+   list_del(&rq->guc_fence_link);
+   irq_work_queue(&rq->submit_work);
+   }
 
INIT_LIST_HEAD(&ce->guc_state.fences);
 }
@@ -2155,6 +2170,7 @@ static int guc_request_alloc(struct i915_request *rq)
spin_lock_irqsave(&ce->guc_state.lock, flags);
if (context_wait_for_deregister_to_register(ce) ||
context_pending_disable(ce)) {
+   init_irq_work(&rq->submit_work, submit_work_cb);
i915_sw_fence_await(&rq->submit);
 
list_add_tail(&rq->guc_fence_link, &ce->guc_state.fences);
diff --git a/drivers/gpu/drm/i915/i915_request.h 
b/drivers/gpu/drm/i915/i915_request.h
index 1bc1349ba3c2..d818cfbfc41d 100644
--- a/drivers/gpu/drm/i915/i915_request.h
+++ b/drivers/gpu/drm/i915/i915_request.h
@@ -218,6 +218,11 @@ struct i915_request {
};
struct llist_head execute_cb;
struct i915_sw_fence semaphore;
+   /**
+* @submit_work: complete submit fence from an IRQ if needed for
+* locking hierarchy reasons.
+*/
+   struct irq_work submit_work;
 
/*
 * A list of everyone we wait upon, and everyone who waits upon us.
-- 
2.25.1

[Intel-gfx] [PATCH v5 16/25] drm/i915/guc: Flush G2H work queue during reset

[Daniele Ceraolo Spurio]

From: Matthew Brost 

It isn't safe to scrub for missing G2H or continue with the reset until
all G2H processing is complete. Flush the G2H work queue during reset to
ensure it is done running. No need to call the IRQ handler directly
either as the scrubbing code can deal with any missing G2H.

Fixes: eb5e7da736f3 ("drm/i915/guc: Reset implementation for new GuC interface")
Signed-off-by: Matthew Brost 
Reviewed-by: Daniele Ceraolo Spurio 
---
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c  | 18 ++
 1 file changed, 2 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index dcd7a09f8559..8509e827a8d0 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -716,8 +716,6 @@ static void guc_flush_submissions(struct intel_guc *guc)
 
 void intel_guc_submission_reset_prepare(struct intel_guc *guc)
 {
-   int i;
-
if (unlikely(!guc_submission_initialized(guc))) {
/* Reset called during driver load? GuC not yet initialised! */
return;
@@ -733,20 +731,8 @@ void intel_guc_submission_reset_prepare(struct intel_guc 
*guc)
 
guc_flush_submissions(guc);
 
-   /*
-* Handle any outstanding G2Hs before reset. Call IRQ handler directly
-* each pass as interrupt have been disabled. We always scrub for
-* outstanding G2H as it is possible for outstanding_submission_g2h to
-* be incremented after the context state update.
-*/
-   for (i = 0; i < 4 && atomic_read(&guc->outstanding_submission_g2h); 
++i) {
-   intel_guc_to_host_event_handler(guc);
-#define wait_for_reset(guc, wait_var) \
-   intel_guc_wait_for_pending_msg(guc, wait_var, false, (HZ / 20))
-   do {
-   wait_for_reset(guc, &guc->outstanding_submission_g2h);
-   } while (!list_empty(&guc->ct.requests.incoming));
-   }
+   flush_work(&guc->ct.requests.worker);
+
scrub_guc_desc_for_outstanding_g2h(guc);
 }
 
-- 
2.25.1

[Intel-gfx] [PATCH v5 13/25] drm/i915/guc: Don't touch guc_state.sched_state without a lock

[Daniele Ceraolo Spurio]

From: Matthew Brost 

Before we did some clever tricks to not use the a lock when touching
guc_state.sched_state in certain cases. Don't do that, enforce the use
of the lock.

v2:
 (kernel test robo )
  - Add __maybe_unused to sched_state_is_init()

v3: rebase after the unused code path removal has been moved to an
earlier patch.

Signed-off-by: Matthew Brost 
Reported-by: kernel test robot 
Reviewed-by: Daniele Ceraolo Spurio 
---
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 22 ++-
 1 file changed, 17 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index e036a171ff17..ca73128d7b4d 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -151,11 +151,23 @@ static inline void clr_context_registered(struct 
intel_context *ce)
 
 static inline void init_sched_state(struct intel_context *ce)
 {
-   /* Only should be called from guc_lrc_desc_pin() */
+   lockdep_assert_held(&ce->guc_state.lock);
atomic_set(&ce->guc_sched_state_no_lock, 0);
ce->guc_state.sched_state &= SCHED_STATE_BLOCKED_MASK;
 }
 
+__maybe_unused
+static bool sched_state_is_init(struct intel_context *ce)
+{
+   /*
+* XXX: Kernel contexts can have SCHED_STATE_NO_LOCK_REGISTERED after
+* suspend.
+*/
+   return !(atomic_read(&ce->guc_sched_state_no_lock) &
+~SCHED_STATE_NO_LOCK_REGISTERED) &&
+   !(ce->guc_state.sched_state &= ~SCHED_STATE_BLOCKED_MASK);
+}
+
 static inline bool
 context_wait_for_deregister_to_register(struct intel_context *ce)
 {
@@ -166,7 +178,7 @@ context_wait_for_deregister_to_register(struct 
intel_context *ce)
 static inline void
 set_context_wait_for_deregister_to_register(struct intel_context *ce)
 {
-   /* Only should be called from guc_lrc_desc_pin() without lock */
+   lockdep_assert_held(&ce->guc_state.lock);
ce->guc_state.sched_state |=
SCHED_STATE_WAIT_FOR_DEREGISTER_TO_REGISTER;
 }
@@ -607,9 +619,7 @@ static void scrub_guc_desc_for_outstanding_g2h(struct 
intel_guc *guc)
bool pending_disable, pending_enable, deregister, destroyed, banned;
 
xa_for_each(&guc->context_lookup, index, ce) {
-   /* Flush context */
spin_lock_irqsave(&ce->guc_state.lock, flags);
-   spin_unlock_irqrestore(&ce->guc_state.lock, flags);
 
/*
 * Once we are at this point submission_disabled() is guaranteed
@@ -625,6 +635,8 @@ static void scrub_guc_desc_for_outstanding_g2h(struct 
intel_guc *guc)
banned = context_banned(ce);
init_sched_state(ce);
 
+   spin_unlock_irqrestore(&ce->guc_state.lock, flags);
+
if (pending_enable || destroyed || deregister) {
decr_outstanding_submission_g2h(guc);
if (deregister)
@@ -1324,6 +1336,7 @@ static int guc_lrc_desc_pin(struct intel_context *ce, 
bool loop)
int ret = 0;
 
GEM_BUG_ON(!engine->mask);
+   GEM_BUG_ON(!sched_state_is_init(ce));
 
/*
 * Ensure LRC + CT vmas are is same region as write barrier is done
@@ -1352,7 +1365,6 @@ static int guc_lrc_desc_pin(struct intel_context *ce, 
bool loop)
desc->priority = ce->guc_prio;
desc->context_flags = CONTEXT_REGISTRATION_FLAG_KMD;
guc_context_policy_init(engine, desc);
-   init_sched_state(ce);
 
/*
 * The context_lookup xarray is used to determine if the hardware
-- 
2.25.1

[Intel-gfx] [PATCH v5 15/25] drm/i915: Allocate error capture in nowait context

[Daniele Ceraolo Spurio]

From: Matthew Brost 

Error captures can now be done in a work queue processing G2H messages.
These messages need to be completely done being processed in the reset
path, to avoid races in the missing G2H cleanup, which create a
dependency on memory allocations and dma fences (i915_requests).
Requests depend on resets, thus now we have a circular dependency. To
work around this, allocate the error capture in a nowait context.

v2:
 (Daniel Vetter)
  - Use GFP_NOWAIT instead GFP_ATOMIC

Fixes: dc0dad365c5e ("Fix for error capture after full GPU reset with GuC")
Fixes: 573ba126aef3 ("Capture error state on context reset")
Signed-off-by: Matthew Brost 
---
 drivers/gpu/drm/i915/i915_gpu_error.c | 39 +--
 1 file changed, 19 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
b/drivers/gpu/drm/i915/i915_gpu_error.c
index b9f66dbd46bb..8696ead02118 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -49,8 +49,7 @@
 #include "i915_memcpy.h"
 #include "i915_scatterlist.h"
 
-#define ALLOW_FAIL (GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN)
-#define ATOMIC_MAYFAIL (GFP_ATOMIC | __GFP_NOWARN)
+#define ATOMIC_MAYFAIL (GFP_NOWAIT | __GFP_NOWARN)
 
 static void __sg_set_buf(struct scatterlist *sg,
 void *addr, unsigned int len, loff_t it)
@@ -79,7 +78,7 @@ static bool __i915_error_grow(struct drm_i915_error_state_buf 
*e, size_t len)
if (e->cur == e->end) {
struct scatterlist *sgl;
 
-   sgl = (typeof(sgl))__get_free_page(ALLOW_FAIL);
+   sgl = (typeof(sgl))__get_free_page(ATOMIC_MAYFAIL);
if (!sgl) {
e->err = -ENOMEM;
return false;
@@ -99,10 +98,10 @@ static bool __i915_error_grow(struct 
drm_i915_error_state_buf *e, size_t len)
}
 
e->size = ALIGN(len + 1, SZ_64K);
-   e->buf = kmalloc(e->size, ALLOW_FAIL);
+   e->buf = kmalloc(e->size, ATOMIC_MAYFAIL);
if (!e->buf) {
e->size = PAGE_ALIGN(len + 1);
-   e->buf = kmalloc(e->size, GFP_KERNEL);
+   e->buf = kmalloc(e->size, ATOMIC_MAYFAIL);
}
if (!e->buf) {
e->err = -ENOMEM;
@@ -243,12 +242,12 @@ static bool compress_init(struct i915_vma_compress *c)
 {
struct z_stream_s *zstream = &c->zstream;
 
-   if (pool_init(&c->pool, ALLOW_FAIL))
+   if (pool_init(&c->pool, ATOMIC_MAYFAIL))
return false;
 
zstream->workspace =
kmalloc(zlib_deflate_workspacesize(MAX_WBITS, MAX_MEM_LEVEL),
-   ALLOW_FAIL);
+   ATOMIC_MAYFAIL);
if (!zstream->workspace) {
pool_fini(&c->pool);
return false;
@@ -256,7 +255,7 @@ static bool compress_init(struct i915_vma_compress *c)
 
c->tmp = NULL;
if (i915_has_memcpy_from_wc())
-   c->tmp = pool_alloc(&c->pool, ALLOW_FAIL);
+   c->tmp = pool_alloc(&c->pool, ATOMIC_MAYFAIL);
 
return true;
 }
@@ -280,7 +279,7 @@ static void *compress_next_page(struct i915_vma_compress *c,
if (dst->page_count >= dst->num_pages)
return ERR_PTR(-ENOSPC);
 
-   page = pool_alloc(&c->pool, ALLOW_FAIL);
+   page = pool_alloc(&c->pool, ATOMIC_MAYFAIL);
if (!page)
return ERR_PTR(-ENOMEM);
 
@@ -376,7 +375,7 @@ struct i915_vma_compress {
 
 static bool compress_init(struct i915_vma_compress *c)
 {
-   return pool_init(&c->pool, ALLOW_FAIL) == 0;
+   return pool_init(&c->pool, ATOMIC_MAYFAIL) == 0;
 }
 
 static bool compress_start(struct i915_vma_compress *c)
@@ -391,7 +390,7 @@ static int compress_page(struct i915_vma_compress *c,
 {
void *ptr;
 
-   ptr = pool_alloc(&c->pool, ALLOW_FAIL);
+   ptr = pool_alloc(&c->pool, ATOMIC_MAYFAIL);
if (!ptr)
return -ENOMEM;
 
@@ -1026,7 +1025,7 @@ i915_vma_coredump_create(const struct intel_gt *gt,
 
num_pages = min_t(u64, vma->size, vma->obj->base.size) >> PAGE_SHIFT;
num_pages = DIV_ROUND_UP(10 * num_pages, 8); /* worstcase zlib growth */
-   dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), ALLOW_FAIL);
+   dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), ATOMIC_MAYFAIL);
if (!dst)
return NULL;
 
@@ -1462,7 +1461,7 @@ capture_engine(struct intel_engine_cs *engine,
struct i915_request *rq = NULL;
unsigned long flags;
 
-   ee = intel_engine_coredump_alloc(engine, GFP_KERNEL);
+   ee = intel_engine_coredump_alloc(engine, ATOMIC_MAYFAIL);
if (!ee)
return NULL;
 
@@ -1510,7 +1509,7 @@ gt_record_engines(struct intel_gt_coredump *gt,
struct intel_engine_coredump *ee;
 
/* Refill our page pool before entering atomic section */
-   pool_refill(&compress->pool, ALLOW_FAIL);
+

[Intel-gfx] [PATCH v5 14/25] drm/i915/guc: Reset LRC descriptor if register returns -ENODEV

[Daniele Ceraolo Spurio]

From: Matthew Brost 

Reset LRC descriptor if a context register returns -ENODEV as this means
we are mid-reset.

Fixes: eb5e7da736f3 ("drm/i915/guc: Reset implementation for new GuC interface")
Signed-off-by: Matthew Brost 
Reviewed-by: Daniele Ceraolo Spurio 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index ca73128d7b4d..dcd7a09f8559 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1405,10 +1405,12 @@ static int guc_lrc_desc_pin(struct intel_context *ce, 
bool loop)
} else {
with_intel_runtime_pm(runtime_pm, wakeref)
ret = register_context(ce, loop);
-   if (unlikely(ret == -EBUSY))
+   if (unlikely(ret == -EBUSY)) {
+   reset_lrc_desc(guc, desc_idx);
+   } else if (unlikely(ret == -ENODEV)) {
reset_lrc_desc(guc, desc_idx);
-   else if (unlikely(ret == -ENODEV))
ret = 0;/* Will get registered later */
+   }
}
 
return ret;
-- 
2.25.1

[Intel-gfx] [PATCH v5 11/25] drm/i915/selftests: Add initial GuC selftest for scrubbing lost G2H

[Daniele Ceraolo Spurio]

From: Matthew Brost 

While debugging an issue with full GT resets I went down a rabbit hole
thinking the scrubbing of lost G2H wasn't working correctly. This proved
to be incorrect as this was working just fine but this chase inspired me
to write a selftest to prove that this works. This simple selftest
injects errors dropping various G2H and then issues a full GT reset
proving that the scrubbing of these G2H doesn't blow up.

v2:
 (Daniel Vetter)
  - Use ifdef instead of macros for selftests
v3:
 (Checkpatch)
  - A space after 'switch' statement
v4:
 (Daniele)
  - A comment saying GT won't idle if G2H are lost

Reviewed-by: Daniele Ceraolo Spurio 
Signed-off-by: Matthew Brost 
---
 drivers/gpu/drm/i915/gt/intel_context_types.h |  18 +++
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  25 
 drivers/gpu/drm/i915/gt/uc/selftest_guc.c | 127 ++
 .../drm/i915/selftests/i915_live_selftests.h  |   1 +
 .../i915/selftests/intel_scheduler_helpers.c  |  12 ++
 .../i915/selftests/intel_scheduler_helpers.h  |   2 +
 6 files changed, 185 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/gt/uc/selftest_guc.c

diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h 
b/drivers/gpu/drm/i915/gt/intel_context_types.h
index e54351a170e2..3a73f3117873 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -198,6 +198,24 @@ struct intel_context {
 */
u8 guc_prio;
u32 guc_prio_count[GUC_CLIENT_PRIORITY_NUM];
+
+#ifdef CONFIG_DRM_I915_SELFTEST
+   /**
+* @drop_schedule_enable: Force drop of schedule enable G2H for selftest
+*/
+   bool drop_schedule_enable;
+
+   /**
+* @drop_schedule_disable: Force drop of schedule disable G2H for
+* selftest
+*/
+   bool drop_schedule_disable;
+
+   /**
+* @drop_deregister: Force drop of deregister G2H for selftest
+*/
+   bool drop_deregister;
+#endif
 };
 
 #endif /* __INTEL_CONTEXT_TYPES__ */
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index f5bee833ee7d..5970c54a2e72 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -2639,6 +2639,13 @@ int intel_guc_deregister_done_process_msg(struct 
intel_guc *guc,
 
trace_intel_context_deregister_done(ce);
 
+#ifdef CONFIG_DRM_I915_SELFTEST
+   if (unlikely(ce->drop_deregister)) {
+   ce->drop_deregister = false;
+   return 0;
+   }
+#endif
+
if (context_wait_for_deregister_to_register(ce)) {
struct intel_runtime_pm *runtime_pm =
&ce->engine->gt->i915->runtime_pm;
@@ -2693,10 +2700,24 @@ int intel_guc_sched_done_process_msg(struct intel_guc 
*guc,
trace_intel_context_sched_done(ce);
 
if (context_pending_enable(ce)) {
+#ifdef CONFIG_DRM_I915_SELFTEST
+   if (unlikely(ce->drop_schedule_enable)) {
+   ce->drop_schedule_enable = false;
+   return 0;
+   }
+#endif
+
clr_context_pending_enable(ce);
} else if (context_pending_disable(ce)) {
bool banned;
 
+#ifdef CONFIG_DRM_I915_SELFTEST
+   if (unlikely(ce->drop_schedule_disable)) {
+   ce->drop_schedule_disable = false;
+   return 0;
+   }
+#endif
+
/*
 * Unpin must be done before __guc_signal_context_fence,
 * otherwise a race exists between the requests getting
@@ -3073,3 +3094,7 @@ bool intel_guc_virtual_engine_has_heartbeat(const struct 
intel_engine_cs *ve)
 
return false;
 }
+
+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+#include "selftest_guc.c"
+#endif
diff --git a/drivers/gpu/drm/i915/gt/uc/selftest_guc.c 
b/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
new file mode 100644
index ..fb0e4a7bd8ca
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright �� 2021 Intel Corporation
+ */
+
+#include "selftests/intel_scheduler_helpers.h"
+
+static struct i915_request *nop_user_request(struct intel_context *ce,
+struct i915_request *from)
+{
+   struct i915_request *rq;
+   int ret;
+
+   rq = intel_context_create_request(ce);
+   if (IS_ERR(rq))
+   return rq;
+
+   if (from) {
+   ret = i915_sw_fence_await_dma_fence(&rq->submit,
+   &from->fence, 0,
+   I915_FENCE_GFP);
+   if (ret < 0) {
+   i915_request_put(rq);
+   return ERR_PTR(ret);
+   }
+   }
+
+   i915_request_get(rq);
+   i915_request_add(rq);
+
+   ret

[Intel-gfx] [PATCH v5 09/25] drm/i915/guc: Don't enable scheduling on a banned context, guc_id invalid, not registered

[Daniele Ceraolo Spurio]

From: Matthew Brost 

When unblocking a context, do not enable scheduling if the context is
banned, guc_id invalid, or not registered.

v2:
 (Daniele)
  - Add helper for unblock

Fixes: 62eaf0ae217d ("drm/i915/guc: Support request cancellation")
Signed-off-by: Matthew Brost 
Reviewed-by: Daniele Ceraolo Spurio 
Cc: 
---
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 22 ---
 1 file changed, 19 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index bd401a5be87c..f5bee833ee7d 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -148,6 +148,7 @@ static inline void clr_context_registered(struct 
intel_context *ce)
 #define SCHED_STATE_BLOCKED_SHIFT  4
 #define SCHED_STATE_BLOCKEDBIT(SCHED_STATE_BLOCKED_SHIFT)
 #define SCHED_STATE_BLOCKED_MASK   (0xfff << SCHED_STATE_BLOCKED_SHIFT)
+
 static inline void init_sched_state(struct intel_context *ce)
 {
/* Only should be called from guc_lrc_desc_pin() */
@@ -1563,6 +1564,23 @@ static struct i915_sw_fence *guc_context_block(struct 
intel_context *ce)
return &ce->guc_blocked;
 }
 
+#define SCHED_STATE_MULTI_BLOCKED_MASK \
+   (SCHED_STATE_BLOCKED_MASK & ~SCHED_STATE_BLOCKED)
+#define SCHED_STATE_NO_UNBLOCK \
+   (SCHED_STATE_MULTI_BLOCKED_MASK | \
+SCHED_STATE_PENDING_DISABLE | \
+SCHED_STATE_BANNED)
+
+static bool context_cant_unblock(struct intel_context *ce)
+{
+   lockdep_assert_held(&ce->guc_state.lock);
+
+   return (ce->guc_state.sched_state & SCHED_STATE_NO_UNBLOCK) ||
+   context_guc_id_invalid(ce) ||
+   !lrc_desc_registered(ce_to_guc(ce), ce->guc_id) ||
+   !intel_context_is_pinned(ce);
+}
+
 static void guc_context_unblock(struct intel_context *ce)
 {
struct intel_guc *guc = ce_to_guc(ce);
@@ -1577,9 +1595,7 @@ static void guc_context_unblock(struct intel_context *ce)
spin_lock_irqsave(&ce->guc_state.lock, flags);
 
if (unlikely(submission_disabled(guc) ||
-!intel_context_is_pinned(ce) ||
-context_pending_disable(ce) ||
-context_blocked(ce) > 1)) {
+context_cant_unblock(ce))) {
enable = false;
} else {
enable = true;
-- 
2.25.1

[Intel-gfx] [PATCH v5 08/25] drm/i915/guc: Kick tasklet after queuing a request

[Daniele Ceraolo Spurio]

From: Matthew Brost 

Kick tasklet after queuing a request so it submitted in a timely manner.

Fixes: 3a4cdf1982f0 ("drm/i915/guc: Implement GuC context operations for new 
inteface")
Signed-off-by: Matthew Brost 
Reviewed-by: Daniele Ceraolo Spurio 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index f9e3725b94c1..bd401a5be87c 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1049,6 +1049,7 @@ static inline void queue_request(struct i915_sched_engine 
*sched_engine,
list_add_tail(&rq->sched.link,
  i915_sched_lookup_priolist(sched_engine, prio));
set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
+   tasklet_hi_schedule(&sched_engine->tasklet);
 }
 
 static int guc_bypass_tasklet_submit(struct intel_guc *guc,
-- 
2.25.1

[Intel-gfx] [PATCH v5 10/25] drm/i915/guc: Copy whole golden context, set engine state size of subset

[Daniele Ceraolo Spurio]

From: Matthew Brost 

When the GuC does a media reset, it copies a golden context state back
into the corrupted context's state. The address of the golden context
and the size of the engine state restore are passed in via the GuC ADS.
The i915 had a bug where it passed in the whole size of the golden
context, not the size of the engine state to restore resulting in a
memory corruption.

Also copy the entire golden context on init rather than just the engine
state that is restored.

v2 (Daniele): use defines to avoid duplicated const variables (John).

Fixes: 481d458caede ("drm/i915/guc: Add golden context to GuC ADS")
Signed-off-by: Matthew Brost 
Signed-off-by: Daniele Ceraolo Spurio 
Cc: John Harrison 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 26 ++
 1 file changed, 17 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index 6926919bcac6..2c6ea64af7ec 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -349,6 +349,8 @@ static void fill_engine_enable_masks(struct intel_gt *gt,
info->engine_enabled_masks[GUC_VIDEOENHANCE_CLASS] = VEBOX_MASK(gt);
 }
 
+#define LR_HW_CONTEXT_SIZE (80 * sizeof(u32))
+#define LRC_SKIP_SIZE (LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SIZE)
 static int guc_prep_golden_context(struct intel_guc *guc,
   struct __guc_ads_blob *blob)
 {
@@ -396,7 +398,18 @@ static int guc_prep_golden_context(struct intel_guc *guc,
if (!blob)
continue;
 
-   blob->ads.eng_state_size[guc_class] = real_size;
+   /*
+* This interface is slightly confusing. We need to pass the
+* base address of the full golden context and the size of just
+* the engine state, which is the section of the context image
+* that starts after the execlists context. This is required to
+* allow the GuC to restore just the engine state when a
+* watchdog reset occurs.
+* We calculate the engine state size by removing the size of
+* what comes before it in the context image (which is identical
+* on all engines).
+*/
+   blob->ads.eng_state_size[guc_class] = real_size - LRC_SKIP_SIZE;
blob->ads.golden_context_lrca[guc_class] = addr_ggtt;
addr_ggtt += alloc_size;
}
@@ -436,11 +449,6 @@ static void guc_init_golden_context(struct intel_guc *guc)
u8 engine_class, guc_class;
u8 *ptr;
 
-   /* Skip execlist and PPGTT registers + HWSP */
-   const u32 lr_hw_context_size = 80 * sizeof(u32);
-   const u32 skip_size = LRC_PPHWSP_SZ * PAGE_SIZE +
-   lr_hw_context_size;
-
if (!intel_uc_uses_guc_submission(>->uc))
return;
 
@@ -476,12 +484,12 @@ static void guc_init_golden_context(struct intel_guc *guc)
continue;
}
 
-   GEM_BUG_ON(blob->ads.eng_state_size[guc_class] != real_size);
+   GEM_BUG_ON(blob->ads.eng_state_size[guc_class] !=
+  real_size - LRC_SKIP_SIZE);
GEM_BUG_ON(blob->ads.golden_context_lrca[guc_class] != 
addr_ggtt);
addr_ggtt += alloc_size;
 
-   shmem_read(engine->default_state, skip_size, ptr + skip_size,
-  real_size - skip_size);
+   shmem_read(engine->default_state, 0, ptr, real_size);
ptr += alloc_size;
}
 
-- 
2.25.1

[Intel-gfx] [PATCH v5 07/25] Revert "drm/i915/gt: Propagate change in error status to children on unhold"

[Daniele Ceraolo Spurio]

From: Matthew Brost 

Propagating errors to dependent fences is broken and can lead to
errors from one client ending up in another.  In 3761baae908a (Revert
"drm/i915: Propagate errors on awaiting already signaled fences"), we
attempted to get rid of fence error propagation but missed the case
added in 8e9f84cf5cac ("drm/i915/gt: Propagate change in error status
to children on unhold").  Revert that one too.  This error was found
by an up-and-coming selftest which triggers a reset during request
cancellation and verifies that subsequent requests complete
successfully.

v2:
 (Daniel Vetter)
  - Use revert
v3:
 (Jason)
  - Update commit message

References: '3761baae908a ("Revert "drm/i915: Propagate errors on awaiting 
already signaled fences"")'
Signed-off-by: Matthew Brost 
Reviewed-by: Daniel Vetter 
---
 drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 4 
 1 file changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c 
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index de5f9c86b9a4..cafb0608ffb4 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2140,10 +2140,6 @@ static void __execlists_unhold(struct i915_request *rq)
if (p->flags & I915_DEPENDENCY_WEAK)
continue;
 
-   /* Propagate any change in error status */
-   if (rq->fence.error)
-   i915_request_set_error_once(w, rq->fence.error);
-
if (w->engine != rq->engine)
continue;
 
-- 
2.25.1

[Intel-gfx] [PATCH v5 04/25] drm/i915/guc: Don't drop ce->guc_active.lock when unwinding context

[Daniele Ceraolo Spurio]

From: Matthew Brost 

Don't drop ce->guc_active.lock when unwinding a context after reset.
At one point we had to drop this because of a lock inversion but that is
no longer the case. It is much safer to hold the lock so let's do that.

Fixes: eb5e7da736f3 ("drm/i915/guc: Reset implementation for new GuC interface")
Reviewed-by: Daniele Ceraolo Spurio 
Signed-off-by: Matthew Brost 
Cc: 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 4 
 1 file changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 0c1e6b465fba..31bbfe5479ae 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -813,8 +813,6 @@ __unwind_incomplete_requests(struct intel_context *ce)
continue;
 
list_del_init(&rq->sched.link);
-   spin_unlock(&ce->guc_active.lock);
-
__i915_request_unsubmit(rq);
 
/* Push the request back into the queue for later resubmission. 
*/
@@ -827,8 +825,6 @@ __unwind_incomplete_requests(struct intel_context *ce)
 
list_add(&rq->sched.link, pl);
set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
-
-   spin_lock(&ce->guc_active.lock);
}
spin_unlock(&ce->guc_active.lock);
spin_unlock_irqrestore(&sched_engine->lock, flags);
-- 
2.25.1

[Intel-gfx] [PATCH v5 06/25] drm/i915/guc: Workaround reset G2H is received after schedule done G2H

[Daniele Ceraolo Spurio]

From: Matthew Brost 

If the context is reset as a result of the request cancellation the
context reset G2H is received after schedule disable done G2H which is
the wrong order. The schedule disable done G2H release the waiting
request cancellation code which resubmits the context. This races
with the context reset G2H which also wants to resubmit the context but
in this case it really should be a NOP as request cancellation code owns
the resubmit. Use some clever tricks of checking the context state to
seal this race until the GuC firmware is fixed.

v2:
 (Checkpatch)
  - Fix typos
v3:
 (Daniele)
  - State that is a bug in the GuC firmware

Fixes: 62eaf0ae217d ("drm/i915/guc: Support request cancellation")
Signed-off-by: Matthew Brost 
Cc: 
Reviewed-by: Daniele Ceraolo Spurio 
---
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 41 ---
 1 file changed, 35 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 31bbfe5479ae..f9e3725b94c1 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -833,17 +833,33 @@ __unwind_incomplete_requests(struct intel_context *ce)
 static void __guc_reset_context(struct intel_context *ce, bool stalled)
 {
struct i915_request *rq;
+   unsigned long flags;
u32 head;
+   bool skip = false;
 
intel_context_get(ce);
 
/*
-* GuC will implicitly mark the context as non-schedulable
-* when it sends the reset notification. Make sure our state
-* reflects this change. The context will be marked enabled
-* on resubmission.
+* GuC will implicitly mark the context as non-schedulable when it sends
+* the reset notification. Make sure our state reflects this change. The
+* context will be marked enabled on resubmission.
+*
+* XXX: If the context is reset as a result of the request cancellation
+* this G2H is received after the schedule disable complete G2H which is
+* wrong as this creates a race between the request cancellation code
+* re-submitting the context and this G2H handler. This is a bug in the
+* GuC but can be worked around in the meantime but converting this to a
+* NOP if a pending enable is in flight as this indicates that a request
+* cancellation has occurred.
 */
-   clr_context_enabled(ce);
+   spin_lock_irqsave(&ce->guc_state.lock, flags);
+   if (likely(!context_pending_enable(ce)))
+   clr_context_enabled(ce);
+   else
+   skip = true;
+   spin_unlock_irqrestore(&ce->guc_state.lock, flags);
+   if (unlikely(skip))
+   goto out_put;
 
rq = intel_context_find_active_request(ce);
if (!rq) {
@@ -862,6 +878,7 @@ static void __guc_reset_context(struct intel_context *ce, 
bool stalled)
 out_replay:
guc_reset_state(ce, head, stalled);
__unwind_incomplete_requests(ce);
+out_put:
intel_context_put(ce);
 }
 
@@ -1598,6 +1615,13 @@ static void guc_context_cancel_request(struct 
intel_context *ce,
guc_reset_state(ce, intel_ring_wrap(ce->ring, rq->head),
true);
}
+
+   /*
+* XXX: Racey if context is reset, see comment in
+* __guc_reset_context().
+*/
+   flush_work(&ce_to_guc(ce)->ct.requests.worker);
+
guc_context_unblock(ce);
}
 }
@@ -2712,7 +2736,12 @@ static void guc_handle_context_reset(struct intel_guc 
*guc,
 {
trace_intel_context_reset(ce);
 
-   if (likely(!intel_context_is_banned(ce))) {
+   /*
+* XXX: Racey if request cancellation has occurred, see comment in
+* __guc_reset_context().
+*/
+   if (likely(!intel_context_is_banned(ce) &&
+  !context_blocked(ce))) {
capture_error_state(guc, ce);
guc_context_replay(ce);
}
-- 
2.25.1

[Intel-gfx] [PATCH v5 05/25] drm/i915/guc: Process all G2H message at once in work queue

[Daniele Ceraolo Spurio]

From: Matthew Brost 

Rather than processing 1 G2H at a time and re-queuing the work queue if
more messages exist, process all the G2H in a single pass of the work
queue.

Signed-off-by: Matthew Brost 
Reviewed-by: Daniele Ceraolo Spurio 
Cc: Daniel Vetter 
Cc: Michal Wajdeczko 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
index 22b4733b55e2..20c710a74498 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
@@ -1042,9 +1042,9 @@ static void ct_incoming_request_worker_func(struct 
work_struct *w)
container_of(w, struct intel_guc_ct, requests.worker);
bool done;
 
-   done = ct_process_incoming_requests(ct);
-   if (!done)
-   queue_work(system_unbound_wq, &ct->requests.worker);
+   do {
+   done = ct_process_incoming_requests(ct);
+   } while (!done);
 }
 
 static int ct_handle_event(struct intel_guc_ct *ct, struct ct_incoming_msg 
*request)
-- 
2.25.1

[Intel-gfx] [PATCH v5 03/25] drm/i915/guc: Unwind context requests in reverse order

[Daniele Ceraolo Spurio]

From: Matthew Brost 

When unwinding requests on a reset context, if other requests in the
context are in the priority list the requests could be resubmitted out
of seqno order. Traverse the list of active requests in reverse and
append to the head of the priority list to fix this.

Fixes: eb5e7da736f3 ("drm/i915/guc: Reset implementation for new GuC interface")
Signed-off-by: Matthew Brost 
Reviewed-by: Daniele Ceraolo Spurio 
Cc: 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index aff5dd247a88..0c1e6b465fba 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -806,9 +806,9 @@ __unwind_incomplete_requests(struct intel_context *ce)
 
spin_lock_irqsave(&sched_engine->lock, flags);
spin_lock(&ce->guc_active.lock);
-   list_for_each_entry_safe(rq, rn,
-&ce->guc_active.requests,
-sched.link) {
+   list_for_each_entry_safe_reverse(rq, rn,
+&ce->guc_active.requests,
+sched.link) {
if (i915_request_completed(rq))
continue;
 
@@ -825,7 +825,7 @@ __unwind_incomplete_requests(struct intel_context *ce)
}
GEM_BUG_ON(i915_sched_engine_is_empty(sched_engine));
 
-   list_add_tail(&rq->sched.link, pl);
+   list_add(&rq->sched.link, pl);
set_bit(I915_FENCE_FLAG_PQUEUE, &rq->fence.flags);
 
spin_lock(&ce->guc_active.lock);
-- 
2.25.1

[Intel-gfx] [PATCH v5 02/25] drm/i915/guc: Fix outstanding G2H accounting

[Daniele Ceraolo Spurio]

From: Matthew Brost 

A small race that could result in incorrect accounting of the number
of outstanding G2H. Basically prior to this patch we did not increment
the number of outstanding G2H if we encoutered a GT reset while sending
a H2G. This was incorrect as the context state had already been updated
to anticipate a G2H response thus the counter should be incremented.

As part of this change we remove a legacy (now unused) path that was the
last caller requiring a G2H response that was not guaranteed to loop.
This allows us to simplify the accounting as we don't need to handle the
case where the send fails due to the channel being busy.

Also always use helper when decrementing this value.

v2 (Daniele): update GEM_BUG_ON check, pull in dead code removal from
later patch, remove loop param from context_deregister.

Fixes: f4eb1f3fe946 ("drm/i915/guc: Ensure G2H response has space in buffer")
Signed-off-by: Matthew Brost 
Signed-off-by: Daniele Ceraolo Spurio 
Cc: 
---
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 79 +--
 1 file changed, 37 insertions(+), 42 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 69faa39da178..aff5dd247a88 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -352,20 +352,29 @@ static inline void set_lrc_desc_registered(struct 
intel_guc *guc, u32 id,
xa_unlock_irqrestore(&guc->context_lookup, flags);
 }
 
+static void decr_outstanding_submission_g2h(struct intel_guc *guc)
+{
+   if (atomic_dec_and_test(&guc->outstanding_submission_g2h))
+   wake_up_all(&guc->ct.wq);
+}
+
 static int guc_submission_send_busy_loop(struct intel_guc *guc,
 const u32 *action,
 u32 len,
 u32 g2h_len_dw,
 bool loop)
 {
-   int err;
-
-   err = intel_guc_send_busy_loop(guc, action, len, g2h_len_dw, loop);
+   /*
+* We always loop when a send requires a reply (i.e. g2h_len_dw > 0),
+* so we don't handle the case where we don't get a reply because we
+* aborted the send due to the channel being busy.
+*/
+   GEM_BUG_ON(g2h_len_dw && !loop);
 
-   if (!err && g2h_len_dw)
+   if (g2h_len_dw)
atomic_inc(&guc->outstanding_submission_g2h);
 
-   return err;
+   return intel_guc_send_busy_loop(guc, action, len, g2h_len_dw, loop);
 }
 
 int intel_guc_wait_for_pending_msg(struct intel_guc *guc,
@@ -616,7 +625,7 @@ static void scrub_guc_desc_for_outstanding_g2h(struct 
intel_guc *guc)
init_sched_state(ce);
 
if (pending_enable || destroyed || deregister) {
-   atomic_dec(&guc->outstanding_submission_g2h);
+   decr_outstanding_submission_g2h(guc);
if (deregister)
guc_signal_context_fence(ce);
if (destroyed) {
@@ -635,7 +644,7 @@ static void scrub_guc_desc_for_outstanding_g2h(struct 
intel_guc *guc)
intel_engine_signal_breadcrumbs(ce->engine);
}
intel_context_sched_disable_unpin(ce);
-   atomic_dec(&guc->outstanding_submission_g2h);
+   decr_outstanding_submission_g2h(guc);
spin_lock_irqsave(&ce->guc_state.lock, flags);
guc_blocked_fence_complete(ce);
spin_unlock_irqrestore(&ce->guc_state.lock, flags);
@@ -1233,8 +1242,7 @@ static int register_context(struct intel_context *ce, 
bool loop)
 }
 
 static int __guc_action_deregister_context(struct intel_guc *guc,
-  u32 guc_id,
-  bool loop)
+  u32 guc_id)
 {
u32 action[] = {
INTEL_GUC_ACTION_DEREGISTER_CONTEXT,
@@ -1243,16 +1251,16 @@ static int __guc_action_deregister_context(struct 
intel_guc *guc,
 
return guc_submission_send_busy_loop(guc, action, ARRAY_SIZE(action),
 G2H_LEN_DW_DEREGISTER_CONTEXT,
-loop);
+true);
 }
 
-static int deregister_context(struct intel_context *ce, u32 guc_id, bool loop)
+static int deregister_context(struct intel_context *ce, u32 guc_id)
 {
struct intel_guc *guc = ce_to_guc(ce);
 
trace_intel_context_deregister(ce);
 
-   return __guc_action_deregister_context(guc, guc_id, loop);
+   return __guc_action_deregister_context(guc, guc_id);
 }
 
 static intel_engine_mask_t adjust_engine_mask(u8 class, intel_engine_mask_t 
mask)
@@ -1340,26 +1348,23 @@ static int guc_lrc_

[Intel-gfx] [PATCH v5 01/25] drm/i915/guc: Fix blocked context accounting

[Daniele Ceraolo Spurio]

From: Matthew Brost 

Prior to this patch the blocked context counter was cleared on
init_sched_state (used during registering a context & resets) which is
incorrect. This state needs to be persistent or the counter can read the
incorrect value resulting in scheduling never getting enabled again.

Fixes: 62eaf0ae217d ("drm/i915/guc: Support request cancellation")
Signed-off-by: Matthew Brost 
Reviewed-by: Daniel Vetter 
Cc: 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 87d8dc8f51b9..69faa39da178 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -152,7 +152,7 @@ static inline void init_sched_state(struct intel_context 
*ce)
 {
/* Only should be called from guc_lrc_desc_pin() */
atomic_set(&ce->guc_sched_state_no_lock, 0);
-   ce->guc_state.sched_state = 0;
+   ce->guc_state.sched_state &= SCHED_STATE_BLOCKED_MASK;
 }
 
 static inline bool
-- 
2.25.1

[Intel-gfx] [PATCH v5 00/25] Clean up GuC CI failures, simplify locking, and kernel DOC

[Daniele Ceraolo Spurio]

Daniel Vetter pointed out that locking in the GuC submission code was
overly complicated, let's clean this up a bit before introducing more
features in the GuC submission backend.

Also fix some CI failures, port fixes from our internal tree, and add a
few more selftests for coverage.

Lastly, add some kernel DOC explaining how the GuC submission backend
works.

v2: Fix logic error in 'Workaround reset G2H is received after schedule
done G2H', don't propagate errors to dependent fences in execlists
submissiom, resolve checkpatch issues, resend to correct lists
v3: Fix issue kicking tasklet, drop guc_active, fix ref counting in
xarray, add guc_id sub structure, drop inline fuctions, and various
other cleanup suggested by Daniel
v4: Address Daniele's feedback, rebase to tip, resend for CI
v5 [Daniele taking over while Matt is out]: drop patches 8 and 27 for
now (not critical, Matt will update and resend when he's back), address
review comments, improve kerneldoc. Also move all code related to busy
loop to patch 2 so we have a standalone fix.

Signed-off-by: Matthew Brost 
Signed-off-by: Daniele Ceraolo Spurio  #v5

Matthew Brost (25):
  drm/i915/guc: Fix blocked context accounting
  drm/i915/guc: Fix outstanding G2H accounting
  drm/i915/guc: Unwind context requests in reverse order
  drm/i915/guc: Don't drop ce->guc_active.lock when unwinding context
  drm/i915/guc: Process all G2H message at once in work queue
  drm/i915/guc: Workaround reset G2H is received after schedule done G2H
  Revert "drm/i915/gt: Propagate change in error status to children on
unhold"
  drm/i915/guc: Kick tasklet after queuing a request
  drm/i915/guc: Don't enable scheduling on a banned context, guc_id
invalid, not registered
  drm/i915/guc: Copy whole golden context, set engine state size of
subset
  drm/i915/selftests: Add initial GuC selftest for scrubbing lost G2H
  drm/i915/guc: Take context ref when cancelling request
  drm/i915/guc: Don't touch guc_state.sched_state without a lock
  drm/i915/guc: Reset LRC descriptor if register returns -ENODEV
  drm/i915: Allocate error capture in nowait context
  drm/i915/guc: Flush G2H work queue during reset
  drm/i915/guc: Release submit fence from an irq_work
  drm/i915/guc: Move guc_blocked fence to struct guc_state
  drm/i915/guc: Rework and simplify locking
  drm/i915/guc: Proper xarray usage for contexts_lookup
  drm/i915/guc: Drop pin count check trick between sched_disable and
re-pin
  drm/i915/guc: Move GuC priority fields in context under guc_active
  drm/i915/guc: Move fields protected by guc->contexts_lock into sub
structure
  drm/i915/guc: Drop guc_active move everything into guc_state
  drm/i915/guc: Add GuC kernel doc

 Documentation/gpu/i915.rst|   2 +
 drivers/gpu/drm/i915/gt/intel_context.c   |  19 +-
 drivers/gpu/drm/i915/gt/intel_context_types.h |  80 +-
 .../drm/i915/gt/intel_execlists_submission.c  |   4 -
 drivers/gpu/drm/i915/gt/selftest_hangcheck.c  |   6 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc.h|  68 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c|  26 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c |   6 +-
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 921 +++---
 drivers/gpu/drm/i915/gt/uc/selftest_guc.c | 127 +++
 drivers/gpu/drm/i915/i915_gpu_error.c |  39 +-
 drivers/gpu/drm/i915/i915_request.h   |  26 +-
 drivers/gpu/drm/i915/i915_trace.h |  12 +-
 .../drm/i915/selftests/i915_live_selftests.h  |   1 +
 .../i915/selftests/intel_scheduler_helpers.c  |  12 +
 .../i915/selftests/intel_scheduler_helpers.h  |   2 +
 16 files changed, 884 insertions(+), 467 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/gt/uc/selftest_guc.c

-- 
2.25.1

Re: [Intel-gfx] [PATCH V3 8/8] drm/i915/selftest: Remove Renderer class check for l3cc table read

[Matt Roper]

On Mon, Aug 30, 2021 at 09:52:40PM +0530, Ayaz A Siddiqui wrote:
> Some platform like XEHPSVD does not have Renderer engines. since
> read_l3cc_table() is guarded by renderer class due to that check
> of L3CC table was not being performed on those platforms.
> 
> Signed-off-by: Ayaz A Siddiqui 
> ---
>  drivers/gpu/drm/i915/gt/selftest_mocs.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c 
> b/drivers/gpu/drm/i915/gt/selftest_mocs.c
> index 2b0207dfbf21c..05f5c57f82699 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c
> @@ -281,7 +281,7 @@ static int check_mocs_engine(struct live_mocs *arg,
>   offset = i915_ggtt_offset(vma);
>   if (!err)
>   err = read_mocs_table(rq, arg->mocs, &offset);
> - if (!err && ce->engine->class == RENDER_CLASS)
> + if (!err)

This is going to make us read & verify the same values several times
(once per engine) which doesn't seem to provide much benefit.  But I
guess we do the same thing for global MOCS and nobody seems to care
about the duplicated effort there either.

I guess it doesn't really matter.

Reviewed-by: Matt Roper 


Matt

>   err = read_l3cc_table(rq, arg->l3cc, &offset);
>   if (!err)
>   err = read_aux_regs(rq, aux, &offset);
> @@ -296,7 +296,7 @@ static int check_mocs_engine(struct live_mocs *arg,
>   vaddr = arg->vaddr;
>   if (!err)
>   err = check_mocs_table(ce->engine, arg->mocs, &vaddr);
> - if (!err && ce->engine->class == RENDER_CLASS)
> + if (!err)
>   err = check_l3cc_table(ce->engine, arg->l3cc, &vaddr);
>   if (!err)
>   err = check_aux_regs(ce->engine, aux, &vaddr);
> -- 
> 2.26.2
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795

Re: [Intel-gfx] [PATCH V3 7/8] drm/i915/gt: Initialize L3CC table in mocs init

[Matt Roper]

On Mon, Aug 30, 2021 at 09:52:39PM +0530, Ayaz A Siddiqui wrote:
> From: Sreedhar Telukuntla 
> 
> Initialize the L3CC table as part of mocs initalization to program
> LNCFCMOCSx registers, so that the mocs settings are available for
> selection for subsequent memory transactions in driver load path.
> 
> Signed-off-by: Sreedhar Telukuntla 
> Signed-off-by: Ayaz A Siddiqui 
> ---
>  drivers/gpu/drm/i915/gt/intel_mocs.c | 13 ++---
>  1 file changed, 10 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c 
> b/drivers/gpu/drm/i915/gt/intel_mocs.c
> index 577a78dfedf99..405374f1d8ed2 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> @@ -717,10 +717,9 @@ static u32 l3cc_combine(u16 low, u16 high)
>0; \
>i++)
>  
> -static void init_l3cc_table(struct intel_engine_cs *engine,
> +static void init_l3cc_table(struct intel_uncore *uncore,
>   const struct drm_i915_mocs_table *table)
>  {
> - struct intel_uncore *uncore = engine->uncore;
>   unsigned int i;
>   u32 l3cc;
>  
> @@ -746,7 +745,7 @@ void intel_mocs_init_engine(struct intel_engine_cs 
> *engine)
>   init_mocs_table(engine, &table);
>  
>   if (flags & HAS_RENDER_L3CC && engine->class == RENDER_CLASS)
> - init_l3cc_table(engine, &table);
> + init_l3cc_table(engine->uncore, &table);

Can you clarify in the commit message why we still need to re-call this
in intel_mocs_init_engine() if we've already done it in
intel_mocs_init()?  I'm assuming it's because we lose these register
values on engine resets, so in the execlist path we need to make sure
they get re-applied after the reset?


Matt

>  
>   aux = build_aux_regs(engine, &table);
>   apply_aux_regs_engine(engine, aux);
> @@ -776,6 +775,14 @@ void intel_mocs_init(struct intel_gt *gt)
>   if (flags & HAS_GLOBAL_MOCS)
>   __init_mocs_table(gt->uncore, &table, global_mocs_offset());
>   set_mocs_index(gt, &table);
> +
> + /*
> +  * Initialize the L3CC table as part of mocs initalization to make
> +  * sure the LNCFCMOCSx registers are programmed for the subsequent
> +  * memory transactions including guc transactions
> +  */
> + if (flags & HAS_RENDER_L3CC)
> + init_l3cc_table(gt->uncore, &table);
>  }
>  
>  #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
> -- 
> 2.26.2
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795

Re: [Intel-gfx] [PATCH V3 6/8] drm/i95/adl: Define MOCS table for Alderlake

[Matt Roper]

On Mon, Aug 30, 2021 at 09:52:38PM +0530, Ayaz A Siddiqui wrote:
> In order to program unused and reserved mocs entries to L3_WB,
> we need to create a separate mocs table for alderlake.

As noted on the previous patch, I don't think we need a separate table
if we just make sure we initialize unused_entries_index differently for
TGL/RKL vs other gen12 platforms (entry 2 vs entry 1).

> 
> This patch will also covers wa_1608975824.
> 
> Cc: Chris P Wilson 
> Cc: Lucas De Marchi 
> 
> Reviewed-by: Matt Roper 
> Signed-off-by: Ayaz A Siddiqui 
> ---
>  drivers/gpu/drm/i915/gt/intel_mocs.c | 41 +++-
>  1 file changed, 40 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c 
> b/drivers/gpu/drm/i915/gt/intel_mocs.c
> index a97cc08e5a395..577a78dfedf99 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> @@ -339,6 +339,39 @@ static const struct drm_i915_mocs_entry dg1_mocs_table[] 
> = {
>   MOCS_ENTRY(63, 0, L3_1_UC),
>  };
>  
> +static const struct drm_i915_mocs_entry adl_mocs_table[] = {
> + /* wa_1608975824 */
> + MOCS_ENTRY(0,
> +LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
> +L3_3_WB),

Even if we want to keep the separate table for some reason, I believe
this is the same as entry 2, right (which is defined inside
GEN11_MOCS_ENTRIES)?  So if we just omit it, it will be handled just
like any other undefined entry.


Matt

> +
> + GEN11_MOCS_ENTRIES,
> + /* Implicitly enable L1 - HDC:L1 + L3 + LLC */
> + MOCS_ENTRY(48,
> +LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
> +L3_3_WB),
> + /* Implicitly enable L1 - HDC:L1 + L3 */
> + MOCS_ENTRY(49,
> +LE_1_UC | LE_TC_1_LLC,
> +L3_3_WB),
> + /* Implicitly enable L1 - HDC:L1 + LLC */
> + MOCS_ENTRY(50,
> +LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
> +L3_1_UC),
> + /* Implicitly enable L1 - HDC:L1 */
> + MOCS_ENTRY(51,
> +LE_1_UC | LE_TC_1_LLC,
> +L3_1_UC),
> + /* HW Special Case (CCS) */
> + MOCS_ENTRY(60,
> +LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
> +L3_1_UC),
> + /* HW Special Case (Displayable) */
> + MOCS_ENTRY(61,
> +LE_1_UC | LE_TC_1_LLC,
> +L3_3_WB),
> +};
> +
>  enum {
>   HAS_GLOBAL_MOCS = BIT(0),
>   HAS_ENGINE_MOCS = BIT(1),
> @@ -464,7 +497,13 @@ static unsigned int get_mocs_settings(const struct 
> drm_i915_private *i915,
>  
>   memset(table, 0, sizeof(struct drm_i915_mocs_table));
>  
> - if (IS_DG1(i915)) {
> + if (IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) {
> + table->size = ARRAY_SIZE(adl_mocs_table);
> + table->table = adl_mocs_table;
> + table->n_entries = GEN9_NUM_MOCS_ENTRIES;
> + table->uc_index = 3;
> + table->unused_entries_index = 2;
> + } else if (IS_DG1(i915)) {
>   table->size = ARRAY_SIZE(dg1_mocs_table);
>   table->table = dg1_mocs_table;
>   table->n_entries = GEN9_NUM_MOCS_ENTRIES;
> -- 
> 2.26.2
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795

Re: [Intel-gfx] [PATCH V3 5/8] drm/i915/gt: Initialize unused MOCS entries with device specific values

[Matt Roper]

On Mon, Aug 30, 2021 at 09:52:37PM +0530, Ayaz A Siddiqui wrote:
> Historically we've initialized all undefined/reserved entries in
> a platform's MOCS table to the contents of table entry #1 (i.e.,
> I915_MOCS_PTE).
> Going forward, we can't assume that table entry #1 will always
> contain suitable values to use for undefined/reserved table
> indices. We'll allow a platform-specific table index to be
> selected at table initialization time in these cases.
> 
> This new mechanism to select L3 WB entry will be applicable for
> all the Gen12+ platforms except TGL and RKL.
> 
> Since TGL and RLK are already in production so their mocs settings
> are intact to avoid ABI break.
> 
> Signed-off-by: Ayaz A Siddiqui 
> ---
>  drivers/gpu/drm/i915/gt/intel_mocs.c | 41 +++-
>  1 file changed, 22 insertions(+), 19 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c 
> b/drivers/gpu/drm/i915/gt/intel_mocs.c
> index 82eafa8d22453..a97cc08e5a395 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> @@ -25,6 +25,7 @@ struct drm_i915_mocs_table {
>   unsigned int n_entries;
>   const struct drm_i915_mocs_entry *table;
>   u8 uc_index;
> + u8 unused_entries_index;
>  };
>  
>  enum register_type {
> @@ -113,18 +114,25 @@ struct drm_i915_aux_table {
>   *
>   * Entries not part of the following tables are undefined as far as
>   * userspace is concerned and shouldn't be relied upon.  For Gen < 12
> - * they will be initialized to PTE. Gen >= 12 onwards don't have a setting 
> for
> - * PTE and will be initialized to an invalid value.
> + * they will be initialized to PTE. Gen >= 12 don't have a setting for
> + * PTE and those platforms except TGL/RKL will be initialized L3 WB to
> + * catch accidental use of reserved and unused mocs indexes.
>   *
>   * The last few entries are reserved by the hardware. For ICL+ they
>   * should be initialized according to bspec and never used, for older
>   * platforms they should never be written to.
>   *
> - * NOTE: These tables are part of bspec and defined as part of hardware
> + * NOTE1: These tables are part of bspec and defined as part of hardware
>   *   interface for ICL+. For older platforms, they are part of kernel
>   *   ABI. It is expected that, for specific hardware platform, existing
>   *   entries will remain constant and the table will only be updated by
>   *   adding new entries, filling unused positions.
> + *
> + * NOTE2: For GEN >= 12 except TGL and RKL, reserved and unspecified MOCS
> + *   indices have been set to L3 WB. These reserved entries should never
> + *   be used, they may be changed to low performant variants with better
> + *   coherency in the future if more entries are needed.
> + *   For TGL/RKL, all the unspecified MOCS indexes are mapped to L3 UC.
>   */
>  #define GEN9_MOCS_ENTRIES \
>   MOCS_ENTRY(I915_MOCS_UNCACHED, \
> @@ -307,17 +315,9 @@ static const struct drm_i915_mocs_entry icl_mocs_table[] 
> = {
>  };
>  
>  static const struct drm_i915_mocs_entry dg1_mocs_table[] = {
> - /* Error */
> - MOCS_ENTRY(0, 0, L3_0_DIRECT),
>  
>   /* UC */
>   MOCS_ENTRY(1, 0, L3_1_UC),
> -
> - /* Reserved */
> - MOCS_ENTRY(2, 0, L3_0_DIRECT),
> - MOCS_ENTRY(3, 0, L3_0_DIRECT),
> - MOCS_ENTRY(4, 0, L3_0_DIRECT),
> -
>   /* WB - L3 */
>   MOCS_ENTRY(5, 0, L3_3_WB),
>   /* WB - L3 50% */
> @@ -469,6 +469,7 @@ static unsigned int get_mocs_settings(const struct 
> drm_i915_private *i915,
>   table->table = dg1_mocs_table;
>   table->n_entries = GEN9_NUM_MOCS_ENTRIES;
>   table->uc_index = 1;
> + table->unused_entries_index = 5;
>   } else if (GRAPHICS_VER(i915) >= 12) {
>   table->size  = ARRAY_SIZE(tgl_mocs_table);
>   table->table = tgl_mocs_table;

Should we add

table->unused_entries_index = 1;

to the rest of the platforms here since that's what we're doing in
get_entry_l3cc() anyway?

Also I think we can rely on that to avoid the need to add a new MOCS
table for ADL in the next patch; we can just use the same table but set
a different unused_entries_index.  E.g.,

} else if (IS_TIGERLAKE(i915) || IS_ROCKETLAKE(i915)) {
...
/* UC: Can't be changed now for ABI reasons */
table->unused_entries_index = 1;
} else if (GRAPHICS_VER(i915) >= 12) {
...
/* L3 */
table->unused_entries_index = 2;
} else if (GRAPHICS_VER(i915) == 11) {
...
table->unused_entries_index = 1;
...


> @@ -600,16 +601,17 @@ int apply_mocs_aux_regs_ctx(struct i915_request *rq)
>  }
>  
>  /*
> - * Get control_value from MOCS entry taking into account when it's not used:
> - * I915_MOCS_PTE's value is returned in this case.
> + * Get control_value from MOCS entry taking into 

Re: [Intel-gfx] [PATCH V3 4/8] drm/i915/gt: Set BLIT_CCTL reg to un-cached

[Matt Roper]

On Mon, Aug 30, 2021 at 09:52:36PM +0530, Ayaz A Siddiqui wrote:
> From: Apoorva Singh 
> 
> Blitter commands which do not have MOCS fields rely on
> cacheability of BlitterCacheControlRegister which was mapped
> to index 0 by default.Once we changed the MOCS value of
> index 0 to L3 WB, tests like gem_linear_blits started failing
> due to a change in cacheability from UC to WB.
> 
> Program and place the BlitterCacheControlRegister in
> build_aux_regs().
> 
> Signed-off-by: Apoorva Singh 
> Signed-off-by: Ayaz A Siddiqui 
> ---
>  drivers/gpu/drm/i915/gt/intel_mocs.c | 13 +
>  drivers/gpu/drm/i915/i915_reg.h  |  7 +++
>  2 files changed, 20 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c 
> b/drivers/gpu/drm/i915/gt/intel_mocs.c
> index 403bd48362b19..82eafa8d22453 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> @@ -386,6 +386,17 @@ add_aux_reg(struct drm_i915_aux_table *aux,
>   return x;
>  }
>  
> +static struct drm_i915_aux_table *
> +add_blit_cctl_override(struct drm_i915_aux_table *aux, u8 idx)
> +{
> + return add_aux_reg(aux,
> +REG_ENGINE_CONTEXT,
> +"BLIT_CCTL",
> +BLIT_CCTL(0),
> +BLIT_CCTL_MOCS(idx, idx),
> +0);
> +}
> +
>  static struct drm_i915_aux_table *
>  add_cmd_cctl_override(struct drm_i915_aux_table *aux, u8 idx)
>  {
> @@ -412,6 +423,8 @@ build_aux_regs(const struct intel_engine_cs *engine,
>* a entry in drm_i915_aux_table link list.
>*/
>   aux = add_cmd_cctl_override(aux, mocs->uc_index);
> + if (engine->class == COPY_ENGINE_CLASS)
> + aux = add_blit_cctl_override(aux, mocs->uc_index);
>   }
>   return aux;
>  }
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index df7a4550fb50f..207e0ada179b2 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2567,6 +2567,13 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, (write) << 
> 1) | \
> REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, (read) << 1))
>  
> +#define BLIT_CCTL(base)  _MMIO((base) + 0x204)
> +#define   BLIT_CCTL_DST_MOCS_MASKREG_GENMASK(14, 8)
> +#define   BLIT_CCTL_SRC_MOCS_MASKREG_GENMASK(6, 0)
> +#define   BLIT_CCTL_DST_MOCS_SHIFT   8
> +#define   BLIT_CCTL_MOCS(dst, src)   
> \
> + dst) << 1) << BLIT_CCTL_DST_MOCS_SHIFT) | ((src) << 1))

It would be preferable to write this as

#define   BLIT_CCTL_MOCS(dst, src) (\
REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, (dst << 1)) | \
REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, (src << 1)) \
)

You can drop BLIT_CCTL_DST_MOCS_SHIFT too then.


In general the changes in this patch and patch #3 look okay, but they
may need to be reworked slightly if we change the general design of the
aux table framework based on the review feedback there.


Matt

> +
>  #define RING_RESET_CTL(base) _MMIO((base) + 0xd0)
>  #define   RESET_CTL_CAT_ERROR   REG_BIT(2)
>  #define   RESET_CTL_READY_TO_RESET REG_BIT(1)
> -- 
> 2.26.2
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795

[Intel-gfx] ✗ Fi.CI.IGT: failure for Fix in max source calculation for dp/edp (rev3)

[Patchwork]

== Series Details ==

Series: Fix in max source calculation for dp/edp (rev3)
URL   : https://patchwork.freedesktop.org/series/93622/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_10544_full -> Patchwork_20939_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_20939_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_20939_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_20939_full:

### IGT changes ###

 Possible regressions 

  * igt@gem_exec_schedule@pi-common@rcs0:
- shard-skl:  [PASS][1] -> [FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/shard-skl8/igt@gem_exec_schedule@pi-com...@rcs0.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20939/shard-skl5/igt@gem_exec_schedule@pi-com...@rcs0.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs:
- {shard-rkl}:[SKIP][3] ([i915#1845]) -> [SKIP][4] +6 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/shard-rkl-2/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20939/shard-rkl-6/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs.html

  * igt@kms_cursor_crc@pipe-c-cursor-32x10-onscreen:
- {shard-rkl}:[SKIP][5] ([fdo#112022]) -> [SKIP][6] +3 similar 
issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/shard-rkl-1/igt@kms_cursor_...@pipe-c-cursor-32x10-onscreen.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20939/shard-rkl-6/igt@kms_cursor_...@pipe-c-cursor-32x10-onscreen.html

  
Known issues


  Here are the changes found in Patchwork_20939_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_isolation@preservation-s3@vcs0:
- shard-kbl:  [PASS][7] -> [DMESG-WARN][8] ([i915#180]) +4 similar 
issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/shard-kbl6/igt@gem_ctx_isolation@preservation...@vcs0.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20939/shard-kbl7/igt@gem_ctx_isolation@preservation...@vcs0.html

  * igt@gem_ctx_persistence@legacy-engines-persistence:
- shard-snb:  NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#1099]) +2 
similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20939/shard-snb2/igt@gem_ctx_persiste...@legacy-engines-persistence.html

  * igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][10] -> [TIMEOUT][11] ([i915#2369] / 
[i915#3063] / [i915#3648])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/shard-tglb1/igt@gem_...@unwedge-stress.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20939/shard-tglb2/igt@gem_...@unwedge-stress.html

  * igt@gem_exec_fair@basic-deadline:
- shard-apl:  NOTRUN -> [FAIL][12] ([i915#2846])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20939/shard-apl6/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
- shard-tglb: [PASS][13] -> [FAIL][14] ([i915#2842]) +2 similar 
issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/shard-tglb8/igt@gem_exec_fair@basic-none-sh...@rcs0.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20939/shard-tglb1/igt@gem_exec_fair@basic-none-sh...@rcs0.html
- shard-apl:  [PASS][15] -> [SKIP][16] ([fdo#109271])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/shard-apl7/igt@gem_exec_fair@basic-none-sh...@rcs0.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20939/shard-apl1/igt@gem_exec_fair@basic-none-sh...@rcs0.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-kbl:  [PASS][17] -> [FAIL][18] ([i915#2842])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/shard-kbl6/igt@gem_exec_fair@basic-none-s...@rcs0.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20939/shard-kbl7/igt@gem_exec_fair@basic-none-s...@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-iclb: [PASS][19] -> [FAIL][20] ([i915#2842])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/shard-iclb3/igt@gem_exec_fair@basic-pace-s...@rcs0.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20939/shard-iclb3/igt@gem_exec_fair@basic-pace-s...@rcs0.html

  * igt@gem_exec_flush@basic-batch-kernel-default-cmd:
- shard-tglb: NOTRUN -> [

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/bios: remove vbt ddi_port_info caching (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/bios: remove vbt ddi_port_info caching (rev2)
URL   : https://patchwork.freedesktop.org/series/93957/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10544_full -> Patchwork_20938_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_20938_full:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_pm_rps@reset:
- {shard-rkl}:[PASS][1] -> [FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/shard-rkl-5/igt@i915_pm_...@reset.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20938/shard-rkl-6/igt@i915_pm_...@reset.html

  * igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_rc_ccs_cc:
- {shard-rkl}:[SKIP][3] ([i915#1845]) -> [SKIP][4] +16 similar 
issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/shard-rkl-5/igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20938/shard-rkl-6/igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_cursor_crc@pipe-c-cursor-32x10-offscreen:
- {shard-rkl}:[SKIP][5] ([fdo#112022]) -> [SKIP][6] +8 similar 
issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/shard-rkl-2/igt@kms_cursor_...@pipe-c-cursor-32x10-offscreen.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20938/shard-rkl-6/igt@kms_cursor_...@pipe-c-cursor-32x10-offscreen.html

  
Known issues


  Here are the changes found in Patchwork_20938_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_create@create-clear:
- shard-skl:  [PASS][7] -> [FAIL][8] ([i915#1888] / [i915#3160])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/shard-skl4/igt@gem_cre...@create-clear.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20938/shard-skl7/igt@gem_cre...@create-clear.html

  * igt@gem_ctx_persistence@process:
- shard-snb:  NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#1099]) +5 
similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20938/shard-snb2/igt@gem_ctx_persiste...@process.html

  * igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][10] -> [TIMEOUT][11] ([i915#2369] / 
[i915#3063] / [i915#3648])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/shard-tglb1/igt@gem_...@unwedge-stress.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20938/shard-tglb3/igt@gem_...@unwedge-stress.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-kbl:  [PASS][12] -> [FAIL][13] ([i915#2842]) +1 similar 
issue
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/shard-kbl6/igt@gem_exec_fair@basic-none-s...@rcs0.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20938/shard-kbl3/igt@gem_exec_fair@basic-none-s...@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-iclb: [PASS][14] -> [FAIL][15] ([i915#2842])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/shard-iclb3/igt@gem_exec_fair@basic-pace-s...@rcs0.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20938/shard-iclb1/igt@gem_exec_fair@basic-pace-s...@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
- shard-tglb: [PASS][16] -> [FAIL][17] ([i915#2842]) +1 similar 
issue
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/shard-tglb5/igt@gem_exec_fair@basic-p...@vcs1.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20938/shard-tglb5/igt@gem_exec_fair@basic-p...@vcs1.html

  * igt@gem_exec_fair@basic-pace@vecs0:
- shard-kbl:  [PASS][18] -> [SKIP][19] ([fdo#109271])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/shard-kbl6/igt@gem_exec_fair@basic-p...@vecs0.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20938/shard-kbl6/igt@gem_exec_fair@basic-p...@vecs0.html

  * igt@gem_exec_flush@basic-batch-kernel-default-cmd:
- shard-tglb: NOTRUN -> [SKIP][20] ([fdo#109313])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20938/shard-tglb3/igt@gem_exec_fl...@basic-batch-kernel-default-cmd.html

  * igt@gem_mmap_gtt@cpuset-big-copy-odd:
- shard-iclb: [PASS][21] -> [FAIL][22] ([i915#2428])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/shard-iclb3/igt@gem_mmap_...@cpuset-big-copy-odd.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20938/shard-iclb1/igt@gem_mmap_...@cpuset-big-copy-odd.html

  * igt@gem_pwrite@basic-exhaustion:
- shard-apl:  NOTRUN -> [WARN][23] ([i915#2658])
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/

Re: [Intel-gfx] [PATCH V3 2/8] drm/i915/gt: Add support of mocs auxiliary registers programming

[Matt Roper]

On Mon, Aug 30, 2021 at 09:52:34PM +0530, Ayaz A Siddiqui wrote:
> From: Srinivasan Shanmugam 
> 
> Few registers need to be programmed with
> appropriate MOCS indexes for proper functioning.
> As of now, there are two categories of registers that
> need to be programmed, these are engine power domains
> register and engine state context register.

Minor nitpick:  MOCS-related registers are the initial user of this
framework, but isn't the longer-term goal to move other types of
registers over to this as well (e.g., some of the "fake" workarounds we
have today for uapi compatibility)?  I'd avoid mentioning MOCS
specifically in this patch since this is just a general
register-initializing framework.

> 
> A framework is being added to handle programming and
> verification of those registers.
> 
> To add a register in the future we just need to add it
> in build_aux_regs(), the rest will be taken care of by
> the framework.
> 
> V2: (Ayaz)
>  Added CMD_CCTL in guc_mmio_regset_init(), so that this
>  register can restored after engine reset.
> 
> V3: (Ayaz)
>  1. Changed implementation to have a framework only.
>  2. Added register type for proper application.
>  3. Removed CMD_CCTL programming.
> 
> Cc: Chris Wilson 
> Cc: Matt Roper 
> Signed-off-by: Srinivasan Shanmugam 
> Signed-off-by: Ayaz A Siddiqui 
> ---
>  drivers/gpu/drm/i915/gt/intel_gt.c |   5 +
>  drivers/gpu/drm/i915/gt/intel_mocs.c   | 184 +
>  drivers/gpu/drm/i915/gt/intel_mocs.h   |   5 +
>  drivers/gpu/drm/i915/gt/selftest_mocs.c|  49 ++
>  drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c |  17 +-
>  drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h |  15 ++
>  6 files changed, 263 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c 
> b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 62d40c9866427..ccb257d5282f4 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -21,6 +21,7 @@
>  #include "intel_uncore.h"
>  #include "intel_pm.h"
>  #include "shmem_utils.h"
> +#include "intel_mocs.h"
>  
>  void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
>  {
> @@ -530,6 +531,10 @@ static int __engines_record_defaults(struct intel_gt *gt)
>   if (err)
>   goto err_rq;
>  
> + err  = apply_mocs_aux_regs_ctx(rq);
> + if (err)
> + goto err_rq;
> +
>   err = intel_renderstate_emit(&so, rq);
>   if (err)
>   goto err_rq;
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c 
> b/drivers/gpu/drm/i915/gt/intel_mocs.c
> index 10cc508c1a4f6..c52640523c218 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c

The main framework here probably shouldn't be in intel_mocs if we want
to make this generic and usable for multiple purposes.  It would be best
to have most of this infrastructure in its own file.  Then other parts
of the code (e.g., mocs) can call the new functions here to add their
own sets of registers to the aux table.

> @@ -10,6 +10,8 @@
>  #include "intel_lrc_reg.h"
>  #include "intel_mocs.h"
>  #include "intel_ring.h"
> +#include "intel_gpu_commands.h"
> +#include "uc/intel_guc_ads.h"
>  
>  /* structures required */
>  struct drm_i915_mocs_entry {
> @@ -25,6 +27,28 @@ struct drm_i915_mocs_table {
>   u8 uc_index;
>  };
>  
> +enum register_type {
> + /*
> +  * REG_GT: General register - Need to  be re-plied after GT/GPU reset
> +  * REG_ENGINE: Domain register - needs to be re-applied after
> +  * engine reset
> +  * REG_ENGINE_CONTEXT: Engine state context register - need to stored
> +  * as part of Golden context.
> +  */
> + REG_GT = 0,
> + REG_ENGINE,
> + REG_ENGINE_CONTEXT
> +};
> +
> +struct drm_i915_aux_table {
> + enum register_type type;
> + const char *name;
> + i915_reg_t offset;
> + u32 value;
> + u32 readmask;
> + struct drm_i915_aux_table *next;
> +};
> +
>  /* Defines for the tables (XXX_MOCS_0 - XXX_MOCS_63) */
>  #define _LE_CACHEABILITY(value)  ((value) << 0)
>  #define _LE_TGT_CACHE(value) ((value) << 2)
> @@ -336,6 +360,78 @@ static bool has_mocs(const struct drm_i915_private *i915)
>   return !IS_DGFX(i915);
>  }
>  
> +static struct drm_i915_aux_table *
> +add_aux_reg(struct drm_i915_aux_table *aux,
> + enum register_type type,
> + const char *name,
> + i915_reg_t offset,
> + u32 value,
> + u32 read)
> +{
> + struct drm_i915_aux_table *x;
> +
> + x = kmalloc(sizeof(*x), GFP_ATOMIC);
> + if (!x) {
> + DRM_ERROR("Failed to allocate aux reg '%s'\n", name);
> + return aux;
> + }
> +
> + x->type = type;
> + x->name = name;
> + x->offset = offset;
> + x->value = value;
> + x->readmask = read;
> +
> + x->next = aux;
> + return x;
> +}

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Flush buffer pools on driver remove (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Flush buffer pools on driver remove (rev2)
URL   : https://patchwork.freedesktop.org/series/91177/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_10544_full -> Patchwork_20937_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_20937_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_20937_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_20937_full:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_rc_ccs_cc:
- {shard-rkl}:[SKIP][1] ([i915#1845]) -> [SKIP][2] +12 similar 
issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/shard-rkl-5/igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20937/shard-rkl-6/igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_cursor_crc@pipe-c-cursor-32x10-offscreen:
- {shard-rkl}:[SKIP][3] ([fdo#112022]) -> [SKIP][4] +5 similar 
issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/shard-rkl-2/igt@kms_cursor_...@pipe-c-cursor-32x10-offscreen.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20937/shard-rkl-6/igt@kms_cursor_...@pipe-c-cursor-32x10-offscreen.html

  

### Piglit changes ###

 Possible regressions 

  * 
spec@arb_gpu_shader_fp64@execution@conversion@vert-conversion-explicit-dmat3x2-mat3x2
 (NEW):
- pig-glk-j5005:  NOTRUN -> [INCOMPLETE][5] +3 similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20937/pig-glk-j5005/spec@arb_gpu_shader_fp64@execution@convers...@vert-conversion-explicit-dmat3x2-mat3x2.html

  
New tests
-

  New tests have been introduced between CI_DRM_10544_full and 
Patchwork_20937_full:

### New Piglit tests (4) ###

  * 
spec@arb_gpu_shader_fp64@execution@conversion@frag-conversion-explicit-dvec3-ivec3:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s

  * 
spec@arb_gpu_shader_fp64@execution@conversion@frag-conversion-explicit-dvec3-vec3:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s

  * 
spec@arb_gpu_shader_fp64@execution@conversion@geom-conversion-implicit-vec3-dvec3:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s

  * 
spec@arb_gpu_shader_fp64@execution@conversion@vert-conversion-explicit-dmat3x2-mat3x2:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s

  

Known issues


  Here are the changes found in Patchwork_20937_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_isolation@preservation-s3@vcs0:
- shard-kbl:  [PASS][6] -> [DMESG-WARN][7] ([i915#180]) +3 similar 
issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/shard-kbl6/igt@gem_ctx_isolation@preservation...@vcs0.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20937/shard-kbl6/igt@gem_ctx_isolation@preservation...@vcs0.html

  * igt@gem_ctx_persistence@legacy-engines-persistence:
- shard-snb:  NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#1099]) +2 
similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20937/shard-snb5/igt@gem_ctx_persiste...@legacy-engines-persistence.html

  * igt@gem_ctx_shared@q-smoketest-all:
- shard-glk:  [PASS][9] -> [DMESG-WARN][10] ([i915#118] / [i915#95])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/shard-glk2/igt@gem_ctx_sha...@q-smoketest-all.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20937/shard-glk7/igt@gem_ctx_sha...@q-smoketest-all.html

  * igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][11] -> [TIMEOUT][12] ([i915#2369] / 
[i915#3063] / [i915#3648])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/shard-tglb1/igt@gem_...@unwedge-stress.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20937/shard-tglb2/igt@gem_...@unwedge-stress.html
- shard-iclb: [PASS][13] -> [TIMEOUT][14] ([i915#2369] / 
[i915#2481] / [i915#3070])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/shard-iclb8/igt@gem_...@unwedge-stress.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20937/shard-iclb8/igt@gem_...@unwedge-stress.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-kbl:  [PASS][15] -> [FAIL][16] ([i915#2842]) +1 similar 
issue
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/shard-kbl6/igt@gem_exec_fair@basic-none-s...@rcs0.h

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Mark GPU wedging on driver unregister unrecoverable

[Patchwork]

== Series Details ==

Series: drm/i915: Mark GPU wedging on driver unregister unrecoverable
URL   : https://patchwork.freedesktop.org/series/94247/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10544_full -> Patchwork_20936_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_20936_full:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
- {shard-rkl}:[SKIP][1] ([i915#1845]) -> [SKIP][2] +9 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/shard-rkl-2/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20936/shard-rkl-6/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_cursor_crc@pipe-c-cursor-64x21-sliding:
- {shard-rkl}:[SKIP][3] ([fdo#112022]) -> [SKIP][4] +7 similar 
issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/shard-rkl-5/igt@kms_cursor_...@pipe-c-cursor-64x21-sliding.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20936/shard-rkl-6/igt@kms_cursor_...@pipe-c-cursor-64x21-sliding.html

  
Known issues


  Here are the changes found in Patchwork_20936_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_persistence@legacy-engines-persistence:
- shard-snb:  NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#1099]) +2 
similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20936/shard-snb6/igt@gem_ctx_persiste...@legacy-engines-persistence.html

  * igt@gem_eio@in-flight-contexts-1us:
- shard-tglb: [PASS][6] -> [TIMEOUT][7] ([i915#3063])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/shard-tglb1/igt@gem_...@in-flight-contexts-1us.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20936/shard-tglb1/igt@gem_...@in-flight-contexts-1us.html

  * igt@gem_eio@unwedge-stress:
- shard-skl:  [PASS][8] -> [TIMEOUT][9] ([i915#2369] / [i915#3063])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/shard-skl6/igt@gem_...@unwedge-stress.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20936/shard-skl1/igt@gem_...@unwedge-stress.html

  * igt@gem_exec_fair@basic-deadline:
- shard-apl:  NOTRUN -> [FAIL][10] ([i915#2846])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20936/shard-apl3/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-kbl:  [PASS][11] -> [FAIL][12] ([i915#2842]) +4 similar 
issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/shard-kbl6/igt@gem_exec_fair@basic-none-s...@rcs0.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20936/shard-kbl6/igt@gem_exec_fair@basic-none-s...@rcs0.html

  * igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][13] ([i915#2842])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20936/shard-iclb1/igt@gem_exec_fair@basic-n...@vcs1.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-iclb: [PASS][14] -> [FAIL][15] ([i915#2842])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/shard-iclb3/igt@gem_exec_fair@basic-pace-s...@rcs0.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20936/shard-iclb3/igt@gem_exec_fair@basic-pace-s...@rcs0.html

  * igt@gem_exec_fair@basic-pace@rcs0:
- shard-tglb: [PASS][16] -> [SKIP][17] ([i915#2848])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/shard-tglb5/igt@gem_exec_fair@basic-p...@rcs0.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20936/shard-tglb3/igt@gem_exec_fair@basic-p...@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
- shard-tglb: [PASS][18] -> [FAIL][19] ([i915#2842])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/shard-tglb5/igt@gem_exec_fair@basic-p...@vcs1.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20936/shard-tglb3/igt@gem_exec_fair@basic-p...@vcs1.html

  * igt@gem_userptr_blits@dmabuf-sync:
- shard-kbl:  NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#3323])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20936/shard-kbl3/igt@gem_userptr_bl...@dmabuf-sync.html

  * igt@gem_userptr_blits@vma-merge:
- shard-tglb: NOTRUN -> [FAIL][21] ([i915#3318])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20936/shard-tglb6/igt@gem_userptr_bl...@vma-merge.html

  * igt@gem_workarounds@suspend-resume:
- shard-apl:  NOTRUN -> [DMESG-WARN][22] ([i915#180]) +1 simi

[Intel-gfx] ✓ Fi.CI.BAT: success for Fix in max source calculation for dp/edp (rev3)

[Patchwork]

== Series Details ==

Series: Fix in max source calculation for dp/edp (rev3)
URL   : https://patchwork.freedesktop.org/series/93622/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10544 -> Patchwork_20939


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20939/index.html

Known issues


  Here are the changes found in Patchwork_20939 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@hangcheck:
- fi-snb-2600:NOTRUN -> [INCOMPLETE][1] ([i915#3921])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20939/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-snb-2600:NOTRUN -> [SKIP][2] ([fdo#109271]) +19 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20939/fi-snb-2600/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_chamelium@hdmi-crc-fast:
- fi-snb-2600:NOTRUN -> [SKIP][3] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20939/fi-snb-2600/igt@kms_chamel...@hdmi-crc-fast.html

  
 Possible fixes 

  * igt@i915_pm_rpm@module-reload:
- fi-cfl-8109u:   [FAIL][4] ([i915#4054]) -> [PASS][5]
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/fi-cfl-8109u/igt@i915_pm_...@module-reload.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20939/fi-cfl-8109u/igt@i915_pm_...@module-reload.html

  * igt@i915_selftest@live@execlists:
- fi-cfl-8109u:   [DMESG-WARN][6] ([i915#203]) -> [PASS][7] +4 similar 
issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/fi-cfl-8109u/igt@i915_selftest@l...@execlists.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20939/fi-cfl-8109u/igt@i915_selftest@l...@execlists.html

  * igt@i915_selftest@live@hangcheck:
- {fi-hsw-gt1}:   [DMESG-WARN][8] ([i915#3303]) -> [PASS][9]
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/fi-hsw-gt1/igt@i915_selftest@l...@hangcheck.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20939/fi-hsw-gt1/igt@i915_selftest@l...@hangcheck.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#203]: https://gitlab.freedesktop.org/drm/intel/issues/203
  [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
  [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
  [i915#4054]: https://gitlab.freedesktop.org/drm/intel/issues/4054


Participating hosts (42 -> 35)
--

  Additional (1): fi-snb-2600 
  Missing(8): fi-ilk-m540 bat-adls-5 bat-dg1-6 bat-dg1-5 fi-bsw-cyan 
fi-ctg-p8600 fi-bdw-samus bat-jsl-1 


Build changes
-

  * Linux: CI_DRM_10544 -> Patchwork_20939

  CI-20190529: 20190529
  CI_DRM_10544: 078e7300cf0130241e5d472d8e2f7eef4ef11b65 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6193: 080869f804cb86b25a38889e5ce9a870571cd8c4 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_20939: f455afb651e880e535f1b829f9b1e3c3462ecef9 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

f455afb651e8 drm/i915/dp: fix for ADL_P/S dp/edp max source rates
6b114d620e48 drm/i915/dp: fix DG1 and RKL max source rates
e80b66d2ec61 drm/i915/dp: fix EHL/JSL max source rates calculation
a188ad5865dd drm/i915/dp: fix TGL and ICL max source rates
974b164e0d66 drm/i915/dp: Fix eDP max rate for display 11+

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20939/index.html

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Fix in max source calculation for dp/edp (rev3)

[Patchwork]

== Series Details ==

Series: Fix in max source calculation for dp/edp (rev3)
URL   : https://patchwork.freedesktop.org/series/93622/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
974b164e0d66 drm/i915/dp: Fix eDP max rate for display 11+
-:20: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ 
chars of sha1> ("")' - ie: 'commit d3913019602e ("Revert 
"drm/i915/dp: Correctly advertise HBR3 for GEN11+"")'
#20: 
due to issues in CI in commit d3913019602e ("Revert "drm/i915/dp:

total: 1 errors, 0 warnings, 0 checks, 53 lines checked
a188ad5865dd drm/i915/dp: fix TGL and ICL max source rates
e80b66d2ec61 drm/i915/dp: fix EHL/JSL max source rates calculation
6b114d620e48 drm/i915/dp: fix DG1 and RKL max source rates
f455afb651e8 drm/i915/dp: fix for ADL_P/S dp/edp max source rates

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/dp: fix DG2 max source rate check (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/dp: fix DG2 max source rate check (rev2)
URL   : https://patchwork.freedesktop.org/series/94241/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_10544_full -> Patchwork_20935_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_20935_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_20935_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_20935_full:

### IGT changes ###

 Possible regressions 

  * igt@i915_module_load@reload-with-fault-injection:
- shard-tglb: [PASS][1] -> [TIMEOUT][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/shard-tglb8/igt@i915_module_l...@reload-with-fault-injection.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20935/shard-tglb3/igt@i915_module_l...@reload-with-fault-injection.html

  * igt@kms_cursor_edge_walk@pipe-b-128x128-right-edge:
- shard-tglb: [PASS][3] -> [SKIP][4] +8 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/shard-tglb8/igt@kms_cursor_edge_w...@pipe-b-128x128-right-edge.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20935/shard-tglb3/igt@kms_cursor_edge_w...@pipe-b-128x128-right-edge.html

  * igt@kms_cursor_legacy@short-flip-before-cursor-atomic-transitions:
- shard-tglb: [PASS][5] -> [FAIL][6] +17 similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/shard-tglb8/igt@kms_cursor_leg...@short-flip-before-cursor-atomic-transitions.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20935/shard-tglb3/igt@kms_cursor_leg...@short-flip-before-cursor-atomic-transitions.html

  * igt@kms_lease@lessee_list:
- shard-tglb: [PASS][7] -> [WARN][8] +2 similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/shard-tglb8/igt@kms_lease@lessee_list.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20935/shard-tglb3/igt@kms_lease@lessee_list.html

  
 Warnings 

  * igt@kms_big_fb@linear-64bpp-rotate-90:
- shard-tglb: [SKIP][9] ([fdo#111614]) -> [SKIP][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/shard-tglb8/igt@kms_big...@linear-64bpp-rotate-90.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20935/shard-tglb3/igt@kms_big...@linear-64bpp-rotate-90.html

  * igt@kms_ccs@pipe-c-missing-ccs-buffer-yf_tiled_ccs:
- shard-tglb: [SKIP][11] ([i915#3689]) -> [SKIP][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/shard-tglb8/igt@kms_ccs@pipe-c-missing-ccs-buffer-yf_tiled_ccs.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20935/shard-tglb3/igt@kms_ccs@pipe-c-missing-ccs-buffer-yf_tiled_ccs.html

  * igt@kms_color_chamelium@pipe-d-ctm-max:
- shard-tglb: [SKIP][13] ([fdo#109284] / [fdo#111827]) -> 
[SKIP][14] +1 similar issue
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/shard-tglb8/igt@kms_color_chamel...@pipe-d-ctm-max.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20935/shard-tglb3/igt@kms_color_chamel...@pipe-d-ctm-max.html

  * igt@kms_cursor_crc@pipe-b-cursor-512x512-offscreen:
- shard-tglb: [SKIP][15] ([fdo#109279] / [i915#3359]) -> [SKIP][16]
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/shard-tglb8/igt@kms_cursor_...@pipe-b-cursor-512x512-offscreen.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20935/shard-tglb3/igt@kms_cursor_...@pipe-b-cursor-512x512-offscreen.html

  * igt@kms_cursor_crc@pipe-b-cursor-max-size-offscreen:
- shard-tglb: [SKIP][17] ([i915#3359]) -> [SKIP][18] +1 similar 
issue
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/shard-tglb8/igt@kms_cursor_...@pipe-b-cursor-max-size-offscreen.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20935/shard-tglb3/igt@kms_cursor_...@pipe-b-cursor-max-size-offscreen.html

  * igt@kms_cursor_crc@pipe-d-cursor-32x32-sliding:
- shard-tglb: [SKIP][19] ([i915#3319]) -> [SKIP][20]
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/shard-tglb8/igt@kms_cursor_...@pipe-d-cursor-32x32-sliding.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20935/shard-tglb3/igt@kms_cursor_...@pipe-d-cursor-32x32-sliding.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-3:
- shard-tglb: [SKIP][21] ([i915#2920]) -> [FAIL][22]
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/shard-tglb8/igt@kms_psr2...@primary-plane-update-sf-dmg-area-3.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchw

Re: [Intel-gfx] [PATCH] drm/i915/dp: fix DG2 max source rate check

[Navare, Manasi]

On Wed, Sep 01, 2021 at 02:28:15PM +0300, Jani Nikula wrote:
> Accidentally dropped the else in a rebase fail, causing the DG2 max rate
> to be overwritten later in the if ladder.
> 
> Fixes: e752d1f9c14a ("drm/i915/dg2: add DG2 UHBR source rates")
> Cc: Manasi Navare 
> Cc: Ville Syrjälä 
> Signed-off-by: Jani Nikula 

Yes makes sense and fix looks good

Reviewed-by: Manasi Navare 

Manasi

> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 4f2fd33529ca..81b7097c6ff1 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -345,7 +345,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
>   size = ARRAY_SIZE(icl_rates);
>   if (IS_DG2(dev_priv))
>   max_rate = dg2_max_source_rate(intel_dp);
> - if (IS_JSL_EHL(dev_priv))
> + else if (IS_JSL_EHL(dev_priv))
>   max_rate = ehl_max_source_rate(intel_dp);
>   else
>   max_rate = icl_max_source_rate(intel_dp);
> -- 
> 2.30.2
> 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/bios: remove vbt ddi_port_info caching (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/bios: remove vbt ddi_port_info caching (rev2)
URL   : https://patchwork.freedesktop.org/series/93957/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10544 -> Patchwork_20938


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20938/index.html

Known issues


  Here are the changes found in Patchwork_20938 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_suspend@basic-s0:
- fi-tgl-1115g4:  [PASS][1] -> [FAIL][2] ([i915#1888])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s0.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20938/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s0.html

  * igt@i915_selftest@live@workarounds:
- fi-rkl-guc: [PASS][3] -> [DMESG-FAIL][4] ([i915#3928])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/fi-rkl-guc/igt@i915_selftest@l...@workarounds.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20938/fi-rkl-guc/igt@i915_selftest@l...@workarounds.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-snb-2600:NOTRUN -> [SKIP][5] ([fdo#109271]) +37 similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20938/fi-snb-2600/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_chamelium@hdmi-crc-fast:
- fi-snb-2600:NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20938/fi-snb-2600/igt@kms_chamel...@hdmi-crc-fast.html

  * igt@runner@aborted:
- fi-rkl-guc: NOTRUN -> [FAIL][7] ([i915#3928])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20938/fi-rkl-guc/igt@run...@aborted.html

  
 Possible fixes 

  * igt@i915_pm_rpm@module-reload:
- fi-cfl-8109u:   [FAIL][8] ([i915#4054]) -> [PASS][9]
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/fi-cfl-8109u/igt@i915_pm_...@module-reload.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20938/fi-cfl-8109u/igt@i915_pm_...@module-reload.html

  * igt@i915_selftest@live@execlists:
- fi-cfl-8109u:   [DMESG-WARN][10] ([i915#203]) -> [PASS][11] +4 
similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/fi-cfl-8109u/igt@i915_selftest@l...@execlists.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20938/fi-cfl-8109u/igt@i915_selftest@l...@execlists.html

  * igt@i915_selftest@live@hangcheck:
- {fi-hsw-gt1}:   [DMESG-WARN][12] ([i915#3303]) -> [PASS][13]
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/fi-hsw-gt1/igt@i915_selftest@l...@hangcheck.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20938/fi-hsw-gt1/igt@i915_selftest@l...@hangcheck.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
  [i915#203]: https://gitlab.freedesktop.org/drm/intel/issues/203
  [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
  [i915#3928]: https://gitlab.freedesktop.org/drm/intel/issues/3928
  [i915#4054]: https://gitlab.freedesktop.org/drm/intel/issues/4054


Participating hosts (42 -> 35)
--

  Additional (1): fi-snb-2600 
  Missing(8): fi-ilk-m540 bat-adls-5 bat-dg1-6 bat-dg1-5 fi-bsw-cyan 
fi-ctg-p8600 fi-bdw-samus bat-jsl-1 


Build changes
-

  * Linux: CI_DRM_10544 -> Patchwork_20938

  CI-20190529: 20190529
  CI_DRM_10544: 078e7300cf0130241e5d472d8e2f7eef4ef11b65 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6193: 080869f804cb86b25a38889e5ce9a870571cd8c4 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_20938: 2898c8f26498730dd4cc1afb133442abbf483c12 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

2898c8f26498 drm/i915/bios: get rid of vbt ddi_port_info
efaf221f51b3 drm/i915/bios: use ddc pin directly from child data
76b2336849d2 drm/i915/bios: move ddc pin mapping code next to ddc pin sanitize
8f42bba04387 drm/i915/bios: use alternate aux channel directly from child data
58c59f8ec842 drm/i915/bios: use dp max link rate directly from child data
69a7a6ba4efa drm/i915/bios: use max tmds clock directly from child data
631c5797e268 drm/i915/bios: use hdmi level shift directly from child data

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20938/index.html

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/bios: remove vbt ddi_port_info caching (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/bios: remove vbt ddi_port_info caching (rev2)
URL   : https://patchwork.freedesktop.org/series/93957/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
631c5797e268 drm/i915/bios: use hdmi level shift directly from child data
-:71: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#71: FILE: drivers/gpu/drm/i915/display/intel_bios.c:2961:
+   const struct intel_bios_encoder_data *devdata = 
i915->vbt.ddi_port_info[encoder->port].devdata;

total: 0 errors, 1 warnings, 0 checks, 66 lines checked
69a7a6ba4efa drm/i915/bios: use max tmds clock directly from child data
-:92: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#92: FILE: drivers/gpu/drm/i915/display/intel_bios.c:2952:
+   const struct intel_bios_encoder_data *devdata = 
i915->vbt.ddi_port_info[encoder->port].devdata;

total: 0 errors, 1 warnings, 0 checks, 85 lines checked
58c59f8ec842 drm/i915/bios: use dp max link rate directly from child data
-:70: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#70: FILE: drivers/gpu/drm/i915/display/intel_bios.c:2990:
+   const struct intel_bios_encoder_data *devdata = 
i915->vbt.ddi_port_info[encoder->port].devdata;

total: 0 errors, 1 warnings, 0 checks, 63 lines checked
8f42bba04387 drm/i915/bios: use alternate aux channel directly from child data
76b2336849d2 drm/i915/bios: move ddc pin mapping code next to ddc pin sanitize
efaf221f51b3 drm/i915/bios: use ddc pin directly from child data
-:109: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#109: FILE: drivers/gpu/drm/i915/display/intel_bios.c:2999:
+   const struct intel_bios_encoder_data *devdata = 
i915->vbt.ddi_port_info[encoder->port].devdata;

total: 0 errors, 1 warnings, 0 checks, 99 lines checked
2898c8f26498 drm/i915/bios: get rid of vbt ddi_port_info

Re: [Intel-gfx] [PATCH V3 1/8] drm/i915/gt: Add support of mocs propagation

[Matt Roper]

On Mon, Aug 30, 2021 at 09:52:33PM +0530, Ayaz A Siddiqui wrote:
> Now there are lots of Command and registers that require mocs index
> programming.
> So propagating mocs_index from mocs to gt so that it can be
> used directly without having platform-specific checks.
> 
> Cc: CQ Tang
> Signed-off-by: Ayaz A Siddiqui 
> ---
>  drivers/gpu/drm/i915/gt/intel_gt_types.h |  4 
>  drivers/gpu/drm/i915/gt/intel_mocs.c | 10 ++
>  2 files changed, 14 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h 
> b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> index a81e21bf1bd1a..88601a2d2c229 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> @@ -192,6 +192,10 @@ struct intel_gt {
>  
>   unsigned long mslice_mask;
>   } info;
> +
> + struct i915_mocs_index_gt {

Do we actually plan to use the name 'i915_mocs_index_gt' anywhere else
in the code?  If not, an anonymous struct is probably fine.

> + u8 uc_index;
> + } mocs;
>  };
>  
>  enum intel_gt_scratch_field {
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c 
> b/drivers/gpu/drm/i915/gt/intel_mocs.c
> index 582c4423b95d6..10cc508c1a4f6 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> @@ -22,6 +22,7 @@ struct drm_i915_mocs_table {
>   unsigned int size;
>   unsigned int n_entries;
>   const struct drm_i915_mocs_entry *table;
> + u8 uc_index;
>  };
>  
>  /* Defines for the tables (XXX_MOCS_0 - XXX_MOCS_63) */
> @@ -340,6 +341,8 @@ static unsigned int get_mocs_settings(const struct 
> drm_i915_private *i915,
>  {
>   unsigned int flags;
>  
> + memset(table, 0, sizeof(struct drm_i915_mocs_table));
> +
>   if (IS_DG1(i915)) {
>   table->size = ARRAY_SIZE(dg1_mocs_table);
>   table->table = dg1_mocs_table;
> @@ -504,6 +507,12 @@ static u32 global_mocs_offset(void)
>   return i915_mmio_reg_offset(GEN12_GLOBAL_MOCS(0));
>  }
>  
> +static void set_mocs_index(struct intel_gt *gt,
> +struct drm_i915_mocs_table *table)
> +{
> + gt->mocs.uc_index = table->uc_index;
> +}
> +
>  void intel_mocs_init(struct intel_gt *gt)
>  {
>   struct drm_i915_mocs_table table;
> @@ -515,6 +524,7 @@ void intel_mocs_init(struct intel_gt *gt)
>   flags = get_mocs_settings(gt->i915, &table);
>   if (flags & HAS_GLOBAL_MOCS)
>   __init_mocs_table(gt->uncore, &table, global_mocs_offset());
> + set_mocs_index(gt, &table);

We could probably just inline the 

gt->mocs.uc_index = table->uc_index;

rather than creating a separate function; it doesn't look like
set_mocs_index() gets used anywhere else.

Aside from the two minor cleanups,

Reviewed-by: Matt Roper 

>  }
>  
>  #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
> -- 
> 2.26.2
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Flush buffer pools on driver remove (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Flush buffer pools on driver remove (rev2)
URL   : https://patchwork.freedesktop.org/series/91177/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10544 -> Patchwork_20937


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20937/index.html

Known issues


  Here are the changes found in Patchwork_20937 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_suspend@basic-s3:
- fi-tgl-1115g4:  [PASS][1] -> [FAIL][2] ([i915#1888])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20937/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html

  * igt@i915_selftest@live@hangcheck:
- fi-snb-2600:NOTRUN -> [INCOMPLETE][3] ([i915#3921])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20937/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-snb-2600:NOTRUN -> [SKIP][4] ([fdo#109271]) +19 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20937/fi-snb-2600/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_chamelium@hdmi-crc-fast:
- fi-snb-2600:NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20937/fi-snb-2600/igt@kms_chamel...@hdmi-crc-fast.html

  
 Possible fixes 

  * igt@i915_pm_rpm@module-reload:
- fi-cfl-8109u:   [FAIL][6] ([i915#4054]) -> [PASS][7]
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/fi-cfl-8109u/igt@i915_pm_...@module-reload.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20937/fi-cfl-8109u/igt@i915_pm_...@module-reload.html

  * igt@i915_selftest@live@execlists:
- fi-cfl-8109u:   [DMESG-WARN][8] ([i915#203]) -> [PASS][9] +4 similar 
issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/fi-cfl-8109u/igt@i915_selftest@l...@execlists.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20937/fi-cfl-8109u/igt@i915_selftest@l...@execlists.html

  * igt@i915_selftest@live@hangcheck:
- {fi-hsw-gt1}:   [DMESG-WARN][10] ([i915#3303]) -> [PASS][11]
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/fi-hsw-gt1/igt@i915_selftest@l...@hangcheck.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20937/fi-hsw-gt1/igt@i915_selftest@l...@hangcheck.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
  [i915#203]: https://gitlab.freedesktop.org/drm/intel/issues/203
  [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
  [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
  [i915#4054]: https://gitlab.freedesktop.org/drm/intel/issues/4054


Participating hosts (42 -> 35)
--

  Additional (1): fi-snb-2600 
  Missing(8): fi-ilk-m540 bat-adls-5 bat-dg1-6 bat-dg1-5 fi-bsw-cyan 
fi-ctg-p8600 fi-bdw-samus bat-jsl-1 


Build changes
-

  * Linux: CI_DRM_10544 -> Patchwork_20937

  CI-20190529: 20190529
  CI_DRM_10544: 078e7300cf0130241e5d472d8e2f7eef4ef11b65 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6193: 080869f804cb86b25a38889e5ce9a870571cd8c4 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_20937: 8abf6a31e1e712ba212a5e252c1019bf373bf0cc @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

8abf6a31e1e7 drm/i915: Flush buffer pools on driver remove

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20937/index.html

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Mark GPU wedging on driver unregister unrecoverable

[Patchwork]

== Series Details ==

Series: drm/i915: Mark GPU wedging on driver unregister unrecoverable
URL   : https://patchwork.freedesktop.org/series/94247/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10544 -> Patchwork_20936


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20936/index.html

Known issues


  Here are the changes found in Patchwork_20936 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_prime@amd-to-i915:
- fi-kbl-soraka:  NOTRUN -> [SKIP][1] ([fdo#109271])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20936/fi-kbl-soraka/igt@amdgpu/amd_pr...@amd-to-i915.html

  * igt@gem_exec_suspend@basic-s3:
- fi-tgl-1115g4:  [PASS][2] -> [FAIL][3] ([i915#1888])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20936/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html

  * igt@i915_selftest@live@gt_lrc:
- fi-rkl-guc: [PASS][4] -> [DMESG-WARN][5] ([i915#3958])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/fi-rkl-guc/igt@i915_selftest@live@gt_lrc.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20936/fi-rkl-guc/igt@i915_selftest@live@gt_lrc.html

  * igt@i915_selftest@live@hangcheck:
- fi-snb-2600:NOTRUN -> [INCOMPLETE][6] ([i915#3921])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20936/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-snb-2600:NOTRUN -> [SKIP][7] ([fdo#109271]) +19 similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20936/fi-snb-2600/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_chamelium@hdmi-crc-fast:
- fi-snb-2600:NOTRUN -> [SKIP][8] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20936/fi-snb-2600/igt@kms_chamel...@hdmi-crc-fast.html

  
 Possible fixes 

  * igt@i915_pm_rpm@module-reload:
- fi-cfl-8109u:   [FAIL][9] ([i915#4054]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/fi-cfl-8109u/igt@i915_pm_...@module-reload.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20936/fi-cfl-8109u/igt@i915_pm_...@module-reload.html

  * igt@i915_selftest@live@execlists:
- fi-cfl-8109u:   [DMESG-WARN][11] ([i915#203]) -> [PASS][12] +4 
similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/fi-cfl-8109u/igt@i915_selftest@l...@execlists.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20936/fi-cfl-8109u/igt@i915_selftest@l...@execlists.html

  * igt@i915_selftest@live@hangcheck:
- {fi-hsw-gt1}:   [DMESG-WARN][13] ([i915#3303]) -> [PASS][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/fi-hsw-gt1/igt@i915_selftest@l...@hangcheck.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20936/fi-hsw-gt1/igt@i915_selftest@l...@hangcheck.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
  [i915#203]: https://gitlab.freedesktop.org/drm/intel/issues/203
  [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
  [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
  [i915#3958]: https://gitlab.freedesktop.org/drm/intel/issues/3958
  [i915#4054]: https://gitlab.freedesktop.org/drm/intel/issues/4054


Participating hosts (42 -> 34)
--

  Additional (1): fi-snb-2600 
  Missing(9): fi-ilk-m540 bat-adls-5 bat-dg1-6 bat-dg1-5 fi-bsw-cyan 
fi-ctg-p8600 fi-bdw-samus bat-jsl-1 fi-kbl-r 


Build changes
-

  * Linux: CI_DRM_10544 -> Patchwork_20936

  CI-20190529: 20190529
  CI_DRM_10544: 078e7300cf0130241e5d472d8e2f7eef4ef11b65 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6193: 080869f804cb86b25a38889e5ce9a870571cd8c4 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_20936: c999ceb5aa6ddd5fe1f8b393bbf6b4041c894351 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

c999ceb5aa6d drm/i915: Mark GPU wedging on driver unregister unrecoverable

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20936/index.html

Re: [Intel-gfx] [PATCH 5/5] drm/i915/debugfs: pass intel_connector to intel_connector_debugfs_add()

[Jani Nikula]

On Wed, 01 Sep 2021, Rodrigo Vivi  wrote:
> On Mon, Aug 30, 2021 at 03:53:44PM +0300, Jani Nikula wrote:
>> Prefer the intel_ types. No functional changes.
>> 
>> Signed-off-by: Jani Nikula 
>> ---
>>  drivers/gpu/drm/i915/display/intel_connector.c   | 2 +-
>>  drivers/gpu/drm/i915/display/intel_display_debugfs.c | 3 ++-
>>  drivers/gpu/drm/i915/display/intel_display_debugfs.h | 4 ++--
>>  3 files changed, 5 insertions(+), 4 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_connector.c 
>> b/drivers/gpu/drm/i915/display/intel_connector.c
>> index 4f49d782eca2..c65f95a9a1ec 100644
>> --- a/drivers/gpu/drm/i915/display/intel_connector.c
>> +++ b/drivers/gpu/drm/i915/display/intel_connector.c
>> @@ -124,7 +124,7 @@ int intel_connector_register(struct drm_connector 
>> *connector)
>
> oh, actually this is drm_connector
>
>>  goto err_backlight;
>>  }
>>  
>> -intel_connector_debugfs_add(connector);
>> +intel_connector_debugfs_add(intel_connector);
>
> so this fails...

Hence the v2 :)

>
>>  
>>  return 0;
>>  
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c 
>> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> index 845e2dc76f87..82043a71e91f 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> @@ -2444,8 +2444,9 @@ static const struct file_operations i915_dsc_bpp_fops 
>> = {
>>   * Cleanup will be done by drm_connector_unregister() through a call to
>>   * drm_debugfs_connector_remove().
>>   */
>> -void intel_connector_debugfs_add(struct drm_connector *connector)
>> +void intel_connector_debugfs_add(struct intel_connector *intel_connector)
>>  {
>> +struct drm_connector *connector = &intel_connector->base;
>>  struct dentry *root = connector->debugfs_entry;
>>  struct drm_i915_private *dev_priv = to_i915(connector->dev);
>>  
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.h 
>> b/drivers/gpu/drm/i915/display/intel_display_debugfs.h
>> index c72e35ecba1f..9b89b707ffe6 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.h
>> @@ -6,9 +6,9 @@
>>  #ifndef __INTEL_DISPLAY_DEBUGFS_H__
>>  #define __INTEL_DISPLAY_DEBUGFS_H__
>>  
>> -struct drm_connector;
>>  struct drm_crtc;
>>  struct drm_i915_private;
>> +struct intel_connector;
>>  
>>  #ifdef CONFIG_DEBUG_FS
>>  void intel_display_debugfs_register(struct drm_i915_private *i915);
>> @@ -16,7 +16,7 @@ void intel_connector_debugfs_add(struct drm_connector 
>> *connector);
>>  void intel_crtc_debugfs_add(struct drm_crtc *crtc);
>>  #else
>>  static inline void intel_display_debugfs_register(struct drm_i915_private 
>> *i915) {}
>> -static inline void intel_connector_debugfs_add(struct drm_connector 
>> *connector) {}
>> +static inline void intel_connector_debugfs_add(struct intel_connector 
>> *connector) {}
>>  static inline void intel_crtc_debugfs_add(struct drm_crtc *crtc) {}
>>  #endif
>>  
>> -- 
>> 2.20.1
>> 

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 4/5] drm/i915/display: stop returning errors from debugfs registration

[Jani Nikula]

On Wed, 01 Sep 2021, Rodrigo Vivi  wrote:
> On Mon, Aug 30, 2021 at 03:53:43PM +0300, Jani Nikula wrote:
>> Failures to register debugfs should be ignored anyway, so stop
>> propagating errors altogether for clarity and simplicity. No functional
>> changes.
>
> not even a drm_debug if that fails?

*shrug* the only error we were returning anyway was if debugfs hadn't
been added at the drm level.

BR,
Jani.

>
>> 
>> Signed-off-by: Jani Nikula 
>> ---
>>  .../drm/i915/display/intel_display_debugfs.c  | 19 +--
>>  .../drm/i915/display/intel_display_debugfs.h  |  8 
>>  2 files changed, 9 insertions(+), 18 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c 
>> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> index c1cd5d005e08..845e2dc76f87 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> @@ -2443,17 +2443,15 @@ static const struct file_operations 
>> i915_dsc_bpp_fops = {
>>   *
>>   * Cleanup will be done by drm_connector_unregister() through a call to
>>   * drm_debugfs_connector_remove().
>> - *
>> - * Returns 0 on success, negative error codes on error.
>>   */
>> -int intel_connector_debugfs_add(struct drm_connector *connector)
>> +void intel_connector_debugfs_add(struct drm_connector *connector)
>>  {
>>  struct dentry *root = connector->debugfs_entry;
>>  struct drm_i915_private *dev_priv = to_i915(connector->dev);
>>  
>>  /* The connector must have been registered beforehands. */
>>  if (!root)
>> -return -ENODEV;
>> +return;
>>  
>>  if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
>>  debugfs_create_file("i915_panel_timings", S_IRUGO, root,
>> @@ -2493,23 +2491,16 @@ int intel_connector_debugfs_add(struct drm_connector 
>> *connector)
>>  connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
>>  debugfs_create_file("i915_lpsp_capability", 0444, root,
>>  connector, &i915_lpsp_capability_fops);
>> -
>> -return 0;
>>  }
>>  
>>  /**
>>   * intel_crtc_debugfs_add - add i915 specific crtc debugfs files
>>   * @crtc: pointer to a drm_crtc
>>   *
>> - * Returns 0 on success, negative error codes on error.
>> - *
>>   * Failure to add debugfs entries should generally be ignored.
>>   */
>> -int intel_crtc_debugfs_add(struct drm_crtc *crtc)
>> +void intel_crtc_debugfs_add(struct drm_crtc *crtc)
>>  {
>> -if (!crtc->debugfs_entry)
>> -return -ENODEV;
>> -
>> -crtc_updates_add(crtc);
>> -return 0;
>> +if (crtc->debugfs_entry)
>> +crtc_updates_add(crtc);
>>  }
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.h 
>> b/drivers/gpu/drm/i915/display/intel_display_debugfs.h
>> index 557901f3eb90..c72e35ecba1f 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.h
>> @@ -12,12 +12,12 @@ struct drm_i915_private;
>>  
>>  #ifdef CONFIG_DEBUG_FS
>>  void intel_display_debugfs_register(struct drm_i915_private *i915);
>> -int intel_connector_debugfs_add(struct drm_connector *connector);
>> -int intel_crtc_debugfs_add(struct drm_crtc *crtc);
>> +void intel_connector_debugfs_add(struct drm_connector *connector);
>> +void intel_crtc_debugfs_add(struct drm_crtc *crtc);
>>  #else
>>  static inline void intel_display_debugfs_register(struct drm_i915_private 
>> *i915) {}
>> -static inline int intel_connector_debugfs_add(struct drm_connector 
>> *connector) { return 0; }
>> -static inline int intel_crtc_debugfs_add(struct drm_crtc *crtc) { return 0; 
>> }
>> +static inline void intel_connector_debugfs_add(struct drm_connector 
>> *connector) {}
>> +static inline void intel_crtc_debugfs_add(struct drm_crtc *crtc) {}
>>  #endif
>>  
>>  #endif /* __INTEL_DISPLAY_DEBUGFS_H__ */
>> -- 
>> 2.20.1
>> 

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] [RFC PATCH] drm/i915/gt: fix duplicated inclusion

[kernel test robot]

Generated by: scripts/checkincludes.pl

Reported-by: kernel test robot 
Signed-off-by: kernel test robot 
---
 intel_gt.c |1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c 
b/drivers/gpu/drm/i915/gt/intel_gt.c
index ccb257d5282f4..4643fbf753455 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -14,7 +14,6 @@
 #include "intel_gt_pm.h"
 #include "intel_gt_requests.h"
 #include "intel_migrate.h"
-#include "intel_mocs.h"
 #include "intel_rc6.h"
 #include "intel_renderstate.h"
 #include "intel_rps.h"

Re: [Intel-gfx] [PATCH V3 2/8] drm/i915/gt: Add support of mocs auxiliary registers programming

[kernel test robot]

Hi Ayaz,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-tip/drm-tip next-20210901]
[cannot apply to v5.14]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:
https://github.com/0day-ci/linux/commits/Ayaz-A-Siddiqui/drm-i915-gt-Initialize-unused-MOCS-entries-to-L3_WB/20210831-002827
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot 


includecheck warnings: (new ones prefixed by >>)
>> drivers/gpu/drm/i915/gt/intel_gt.c: intel_mocs.h is included more than once.

Please review and possibly fold the followup patch.

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dp: fix DG2 max source rate check (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/dp: fix DG2 max source rate check (rev2)
URL   : https://patchwork.freedesktop.org/series/94241/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10544 -> Patchwork_20935


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20935/index.html

Known issues


  Here are the changes found in Patchwork_20935 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_pm_rpm@module-reload:
- fi-kbl-r:   [PASS][1] -> [INCOMPLETE][2] ([i915#151] / [i915#92])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/fi-kbl-r/igt@i915_pm_...@module-reload.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20935/fi-kbl-r/igt@i915_pm_...@module-reload.html

  * igt@i915_selftest@live@hangcheck:
- fi-snb-2600:NOTRUN -> [INCOMPLETE][3] ([i915#3921])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20935/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-snb-2600:NOTRUN -> [SKIP][4] ([fdo#109271]) +19 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20935/fi-snb-2600/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_chamelium@hdmi-crc-fast:
- fi-snb-2600:NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20935/fi-snb-2600/igt@kms_chamel...@hdmi-crc-fast.html

  * igt@runner@aborted:
- fi-kbl-r:   NOTRUN -> [FAIL][6] ([fdo#109271] / [i915#1814] / 
[i915#2722] / [i915#3363])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20935/fi-kbl-r/igt@run...@aborted.html

  
 Possible fixes 

  * igt@i915_pm_rpm@module-reload:
- fi-cfl-8109u:   [FAIL][7] ([i915#4054]) -> [PASS][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/fi-cfl-8109u/igt@i915_pm_...@module-reload.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20935/fi-cfl-8109u/igt@i915_pm_...@module-reload.html

  * igt@i915_selftest@live@execlists:
- fi-cfl-8109u:   [DMESG-WARN][9] ([i915#203]) -> [PASS][10] +4 similar 
issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/fi-cfl-8109u/igt@i915_selftest@l...@execlists.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20935/fi-cfl-8109u/igt@i915_selftest@l...@execlists.html

  * igt@i915_selftest@live@hangcheck:
- {fi-hsw-gt1}:   [DMESG-WARN][11] ([i915#3303]) -> [PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/fi-hsw-gt1/igt@i915_selftest@l...@hangcheck.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20935/fi-hsw-gt1/igt@i915_selftest@l...@hangcheck.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151
  [i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
  [i915#203]: https://gitlab.freedesktop.org/drm/intel/issues/203
  [i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
  [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
  [i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
  [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
  [i915#4054]: https://gitlab.freedesktop.org/drm/intel/issues/4054
  [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92


Participating hosts (42 -> 35)
--

  Additional (1): fi-snb-2600 
  Missing(8): fi-ilk-m540 bat-adls-5 bat-dg1-6 bat-dg1-5 fi-bsw-cyan 
fi-ctg-p8600 fi-bdw-samus bat-jsl-1 


Build changes
-

  * Linux: CI_DRM_10544 -> Patchwork_20935

  CI-20190529: 20190529
  CI_DRM_10544: 078e7300cf0130241e5d472d8e2f7eef4ef11b65 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6193: 080869f804cb86b25a38889e5ce9a870571cd8c4 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_20935: ce8d5066428956eb44a13ab0a9613cba79485c64 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

ce8d50664289 drm/i915/dp: fix DG2 max source rate check

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20935/index.html

[Intel-gfx] [PATCH 5/5] drm/i915/dp: fix for ADL_P/S dp/edp max source rates

[Animesh Manna]

Added HBR3 support for ADL_P and ADL_S platform.

Bspec: 53597, 53720, 49185, 55409

Cc: Jani Nikula 
Cc: Imre Deak 
Signed-off-by: Animesh Manna 
Reviewed-by: Imre Deak 
---
 drivers/gpu/drm/i915/display/intel_dp.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 3fe1158706d5..d28bd8c4a8a5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -372,7 +372,8 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
size = ARRAY_SIZE(icl_rates);
if (IS_DG2(dev_priv))
max_rate = dg2_max_source_rate(intel_dp);
-   else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
+   else if (IS_ALDERLAKE_P(dev_priv) || IS_ALDERLAKE_S(dev_priv) ||
+IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
max_rate = dg1_max_source_rate(intel_dp);
else if (IS_JSL_EHL(dev_priv))
max_rate = ehl_max_source_rate(intel_dp);
-- 
2.29.0

[Intel-gfx] [PATCH 4/5] drm/i915/dp: fix DG1 and RKL max source rates

[Animesh Manna]

From: Jani Nikula 

Combo phy is limited to 5.4 GHz on low-voltage SKUs, but both eDP and DP
can do 8.1 GHz on combo phy.

Bspec: 49182, 49205, 49202

Cc: Imre Deak 
Signed-off-by: Jani Nikula 
Signed-off-by: Animesh Manna 
Reviewed-by: Imre Deak 
---
 drivers/gpu/drm/i915/display/intel_dp.c | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 5aabd8ec1015..3fe1158706d5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -325,6 +325,18 @@ static int ehl_max_source_rate(struct intel_dp *intel_dp)
return 81;
 }
 
+static int dg1_max_source_rate(struct intel_dp *intel_dp)
+{
+   struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+   struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+   enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
+
+   if (intel_phy_is_combo(i915, phy) && is_low_voltage_sku(i915, phy))
+   return 54;
+
+   return 81;
+}
+
 static void
 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 {
@@ -360,6 +372,8 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
size = ARRAY_SIZE(icl_rates);
if (IS_DG2(dev_priv))
max_rate = dg2_max_source_rate(intel_dp);
+   else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
+   max_rate = dg1_max_source_rate(intel_dp);
else if (IS_JSL_EHL(dev_priv))
max_rate = ehl_max_source_rate(intel_dp);
else
-- 
2.29.0

[Intel-gfx] [PATCH 3/5] drm/i915/dp: fix EHL/JSL max source rates calculation

[Animesh Manna]

Only higher voltage sku can support HBR3 so a condition
check added in max source rate calculation for ehl/jsl.

Bspec: 32247, 20598

Cc: Jani Nikula 
Cc: Imre Deak 
Signed-off-by: Animesh Manna 
Reviewed-by: Imre Deak 
---
 drivers/gpu/drm/i915/display/intel_dp.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index d7486017b7f6..5aabd8ec1015 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -315,7 +315,11 @@ static int icl_max_source_rate(struct intel_dp *intel_dp)
 
 static int ehl_max_source_rate(struct intel_dp *intel_dp)
 {
-   if (intel_dp_is_edp(intel_dp))
+   struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+   struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
+   enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
+
+   if (intel_dp_is_edp(intel_dp) || is_low_voltage_sku(dev_priv, phy))
return 54;
 
return 81;
@@ -356,7 +360,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
size = ARRAY_SIZE(icl_rates);
if (IS_DG2(dev_priv))
max_rate = dg2_max_source_rate(intel_dp);
-   if (IS_JSL_EHL(dev_priv))
+   else if (IS_JSL_EHL(dev_priv))
max_rate = ehl_max_source_rate(intel_dp);
else
max_rate = icl_max_source_rate(intel_dp);
-- 
2.29.0

[Intel-gfx] [PATCH 2/5] drm/i915/dp: fix TGL and ICL max source rates

[Animesh Manna]

From: Jani Nikula 

Combo phy is limited to 5.4 GHz on low-voltage SKUs. Combo phy DP is
limited to 5.4 GHz, while combo phy eDP can do 8.1 GHz.

Bspec: 20584, 20598, 49180, 49201

Cc: Imre Deak 
Signed-off-by: Jani Nikula 
Signed-off-by: Animesh Manna 
Reviewed-by: Imre Deak 
---
 drivers/gpu/drm/i915/display/intel_dp.c | 11 ++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 7e823c02c1e9..d7486017b7f6 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -291,6 +291,15 @@ static int dg2_max_source_rate(struct intel_dp *intel_dp)
return intel_dp_is_edp(intel_dp) ? 81 : 135;
 }
 
+static bool is_low_voltage_sku(struct drm_i915_private *i915, enum phy phy)
+{
+   u32 voltage;
+
+   voltage = intel_de_read(i915, ICL_PORT_COMP_DW3(phy)) & 
VOLTAGE_INFO_MASK;
+
+   return voltage == VOLTAGE_INFO_0_85V;
+}
+
 static int icl_max_source_rate(struct intel_dp *intel_dp)
 {
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
@@ -298,7 +307,7 @@ static int icl_max_source_rate(struct intel_dp *intel_dp)
enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
 
if (intel_phy_is_combo(dev_priv, phy) &&
-   !intel_dp_is_edp(intel_dp))
+   (is_low_voltage_sku(dev_priv, phy) || !intel_dp_is_edp(intel_dp)))
return 54;
 
return 81;
-- 
2.29.0

[Intel-gfx] [PATCH 1/5] drm/i915/dp: Fix eDP max rate for display 11+

[Animesh Manna]

From: Matt Atwood 

intel_dp_set_source_rates() calls intel_dp_is_edp(), which is unsafe to
use before intel_encoder->type is set. This causes incorrect max source
rate to be used for display 11+. On EHL and JSL, HBR3 is used instead of
HBR2, and on the other affected platforms, HBR2 is used instead of HBR3.

Move intel_dp_set_source_rates() to after intel_encoder->type is
set. Add comment to intel_dp_is_edp() describing unsafe usages. Cleanup
intel_dp_init_connector() while at it.

Note: The same change was originally added as commit 680c45c767f6
("drm/i915/dp: Correctly advertise HBR3 for GEN11+"), but later reverted
due to issues in CI in commit d3913019602e ("Revert "drm/i915/dp:
Correctly advertise HBR3 for GEN11+"").

Cc: Uma Shankar 
Cc: Imre Deak 
Cc: Ville Syrjälä 
Signed-off-by: Matt Atwood 
Signed-off-by: José Roberto de Souza 
Signed-off-by: Jani Nikula 
Signed-off-by: Animesh Manna 
Reviewed-by: Imre Deak 
---
 drivers/gpu/drm/i915/display/intel_dp.c | 28 ++---
 1 file changed, 11 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 4f2fd33529ca..7e823c02c1e9 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -102,6 +102,8 @@ static const u8 valid_dsc_slicecount[] = {1, 2, 4};
  *
  * If a CPU or PCH DP output is attached to an eDP panel, this function
  * will return true, and false otherwise.
+ *
+ * This function is not safe to use prior to encoder type being set.
  */
 bool intel_dp_is_edp(struct intel_dp *intel_dp)
 {
@@ -4899,8 +4901,6 @@ intel_dp_init_connector(struct intel_digital_port 
*dig_port,
 intel_encoder->base.name))
return false;
 
-   intel_dp_set_source_rates(intel_dp);
-
intel_dp->reset_link_params = true;
intel_dp->pps.pps_pipe = INVALID_PIPE;
intel_dp->pps.active_pipe = INVALID_PIPE;
@@ -4916,28 +4916,22 @@ intel_dp_init_connector(struct intel_digital_port 
*dig_port,
 */
drm_WARN_ON(dev, intel_phy_is_tc(dev_priv, phy));
type = DRM_MODE_CONNECTOR_eDP;
+   intel_encoder->type = INTEL_OUTPUT_EDP;
+
+   /* eDP only on port B and/or C on vlv/chv */
+   if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) ||
+ IS_CHERRYVIEW(dev_priv)) &&
+   port != PORT_B && port != PORT_C))
+   return false;
} else {
type = DRM_MODE_CONNECTOR_DisplayPort;
}
 
+   intel_dp_set_source_rates(intel_dp);
+
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);
 
-   /*
-* For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
-* for DP the encoder type can be set by the caller to
-* INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
-*/
-   if (type == DRM_MODE_CONNECTOR_eDP)
-   intel_encoder->type = INTEL_OUTPUT_EDP;
-
-   /* eDP only on port B and/or C on vlv/chv */
-   if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) ||
- IS_CHERRYVIEW(dev_priv)) &&
-   intel_dp_is_edp(intel_dp) &&
-   port != PORT_B && port != PORT_C))
-   return false;
-
drm_dbg_kms(&dev_priv->drm,
"Adding %s connector on [ENCODER:%d:%s]\n",
type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
-- 
2.29.0

[Intel-gfx] [PATCH 0/5] Fix in max source calculation for dp/edp

[Animesh Manna]

HBR3 support for display gen11+ platform is depends upon some
conditions which are mentioned below.

ICL:
- eDP (only on DDI-A): Up to HBR3 for higher Vccio.
- DP:
- (DDI-B, combo phy): upto HBR2.
- (DDI-C to DDI-F): upto HBR3
 
RKLC:
- eDP/DP: Up to HBR3? Vccio dependent? (missing bspec pages)
 
JSL/EHL:
- eDP (DDI-A): Up to HBR2.
- DP (DDI-B to DDI-D): Up to HBR3 for higher Vccio _and_ retimers.
 
TGL:
- eDP (DDI-A to DDI-C): Up to HBR3 for higher Vccio.
- DP:
- (DDI-A to DDI-C, combo phy): Up to HBR2.
- (DDI-TC1 to DDI-TC6): Up to HBR3
 
DG1/ADL_S:
- eDP (all DDI is part of combo phy): Up to HBR3 for higher Vccio.
- DP (all DDI is part of combo phy): Up to HBR3 for higher Vccio _and_ retimers.
 
ADL_P/D13:
- eDP (DDI-A to DDI-B): Up to HBR3 for higher Vccio.
- DP:
- (DDI-A to DDI-E): Up to HBR3 for higher Vccio.
- (DDI-TC1 to DDI-TC4): Up to HBR3 for higher Vccio.

Some condition added during max rate calculation in this patch series
based on above conditions.

Animesh Manna (2):
  drm/i915/dp: fix EHL/JSL max source rates calculation
  drm/i915/dp: fix for ADL_P/S dp/edp max source rates

Jani Nikula (2):
  drm/i915/dp: fix TGL and ICL max source rates
  drm/i915/dp: fix DG1 and RKL max source rates

Matt Atwood (1):
  drm/i915/dp: Fix eDP max rate for display 11+

 drivers/gpu/drm/i915/display/intel_dp.c | 62 +
 1 file changed, 42 insertions(+), 20 deletions(-)

-- 
2.29.0

Re: [Intel-gfx] [PATCH 4/5] drm/i915/display: stop returning errors from debugfs registration

[Rodrigo Vivi]

On Mon, Aug 30, 2021 at 03:53:43PM +0300, Jani Nikula wrote:
> Failures to register debugfs should be ignored anyway, so stop
> propagating errors altogether for clarity and simplicity. No functional
> changes.

not even a drm_debug if that fails?

> 
> Signed-off-by: Jani Nikula 
> ---
>  .../drm/i915/display/intel_display_debugfs.c  | 19 +--
>  .../drm/i915/display/intel_display_debugfs.h  |  8 
>  2 files changed, 9 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c 
> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index c1cd5d005e08..845e2dc76f87 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -2443,17 +2443,15 @@ static const struct file_operations i915_dsc_bpp_fops 
> = {
>   *
>   * Cleanup will be done by drm_connector_unregister() through a call to
>   * drm_debugfs_connector_remove().
> - *
> - * Returns 0 on success, negative error codes on error.
>   */
> -int intel_connector_debugfs_add(struct drm_connector *connector)
> +void intel_connector_debugfs_add(struct drm_connector *connector)
>  {
>   struct dentry *root = connector->debugfs_entry;
>   struct drm_i915_private *dev_priv = to_i915(connector->dev);
>  
>   /* The connector must have been registered beforehands. */
>   if (!root)
> - return -ENODEV;
> + return;
>  
>   if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
>   debugfs_create_file("i915_panel_timings", S_IRUGO, root,
> @@ -2493,23 +2491,16 @@ int intel_connector_debugfs_add(struct drm_connector 
> *connector)
>   connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
>   debugfs_create_file("i915_lpsp_capability", 0444, root,
>   connector, &i915_lpsp_capability_fops);
> -
> - return 0;
>  }
>  
>  /**
>   * intel_crtc_debugfs_add - add i915 specific crtc debugfs files
>   * @crtc: pointer to a drm_crtc
>   *
> - * Returns 0 on success, negative error codes on error.
> - *
>   * Failure to add debugfs entries should generally be ignored.
>   */
> -int intel_crtc_debugfs_add(struct drm_crtc *crtc)
> +void intel_crtc_debugfs_add(struct drm_crtc *crtc)
>  {
> - if (!crtc->debugfs_entry)
> - return -ENODEV;
> -
> - crtc_updates_add(crtc);
> - return 0;
> + if (crtc->debugfs_entry)
> + crtc_updates_add(crtc);
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.h 
> b/drivers/gpu/drm/i915/display/intel_display_debugfs.h
> index 557901f3eb90..c72e35ecba1f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.h
> @@ -12,12 +12,12 @@ struct drm_i915_private;
>  
>  #ifdef CONFIG_DEBUG_FS
>  void intel_display_debugfs_register(struct drm_i915_private *i915);
> -int intel_connector_debugfs_add(struct drm_connector *connector);
> -int intel_crtc_debugfs_add(struct drm_crtc *crtc);
> +void intel_connector_debugfs_add(struct drm_connector *connector);
> +void intel_crtc_debugfs_add(struct drm_crtc *crtc);
>  #else
>  static inline void intel_display_debugfs_register(struct drm_i915_private 
> *i915) {}
> -static inline int intel_connector_debugfs_add(struct drm_connector 
> *connector) { return 0; }
> -static inline int intel_crtc_debugfs_add(struct drm_crtc *crtc) { return 0; }
> +static inline void intel_connector_debugfs_add(struct drm_connector 
> *connector) {}
> +static inline void intel_crtc_debugfs_add(struct drm_crtc *crtc) {}
>  #endif
>  
>  #endif /* __INTEL_DISPLAY_DEBUGFS_H__ */
> -- 
> 2.20.1
> 

Re: [Intel-gfx] [PATCH 3/5] drm/i915/debugfs: register LPSP capability on all platforms

[Rodrigo Vivi]

On Mon, Aug 30, 2021 at 03:53:42PM +0300, Jani Nikula wrote:
> The debugfs file shows it's not capable, don't duplicate the info.

okay, but the file is useless if not supported right?!
I believe the goal here was even avoid the file creation...

But either way:
If this is not breaking IGT:
Reviewed-by: Rodrigo Vivi 


> 
> Signed-off-by: Jani Nikula 
> ---
>  .../gpu/drm/i915/display/intel_display_debugfs.c| 13 +
>  1 file changed, 5 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c 
> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index a6dcb95cfc1f..c1cd5d005e08 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -2486,14 +2486,11 @@ int intel_connector_debugfs_add(struct drm_connector 
> *connector)
>   connector, &i915_dsc_bpp_fops);
>   }
>  
> - /* Legacy panels doesn't lpsp on any platform */
> - if ((DISPLAY_VER(dev_priv) >= 9 || IS_HASWELL(dev_priv) ||
> -  IS_BROADWELL(dev_priv)) &&
> -  (connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
> -  connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
> -  connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
> -  connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
> -  connector->connector_type == DRM_MODE_CONNECTOR_HDMIB))
> + if (connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
> + connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
> + connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
> + connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
> + connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
>   debugfs_create_file("i915_lpsp_capability", 0444, root,
>   connector, &i915_lpsp_capability_fops);
>  
> -- 
> 2.20.1
> 

Re: [Intel-gfx] [PATCH 2/5] drm/i915/debugfs: clean up LPSP capable

[Rodrigo Vivi]

On Mon, Aug 30, 2021 at 03:53:41PM +0300, Jani Nikula wrote:
> Clean up the LPSP capability printout. No functional changes.
> 
> Signed-off-by: Jani Nikula 

Reviewed-by: Rodrigo Vivi 

> ---
>  .../drm/i915/display/intel_display_debugfs.c  | 44 +++
>  1 file changed, 17 insertions(+), 27 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c 
> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index d2a14a9c6857..a6dcb95cfc1f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -2225,14 +2225,12 @@ static int i915_psr_status_show(struct seq_file *m, 
> void *data)
>  }
>  DEFINE_SHOW_ATTRIBUTE(i915_psr_status);
>  
> -#define LPSP_CAPABLE(COND) (COND ? seq_puts(m, "LPSP: capable\n") : \
> - seq_puts(m, "LPSP: incapable\n"))
> -
>  static int i915_lpsp_capability_show(struct seq_file *m, void *data)
>  {
>   struct drm_connector *connector = m->private;
>   struct drm_i915_private *i915 = to_i915(connector->dev);
>   struct intel_encoder *encoder;
> + bool lpsp_capable = false;
>  
>   encoder = intel_attached_encoder(to_intel_connector(connector));
>   if (!encoder)
> @@ -2241,35 +2239,27 @@ static int i915_lpsp_capability_show(struct seq_file 
> *m, void *data)
>   if (connector->status != connector_status_connected)
>   return -ENODEV;
>  
> - if (DISPLAY_VER(i915) >= 13) {
> - LPSP_CAPABLE(encoder->port <= PORT_B);
> - return 0;
> - }
> -
> - switch (DISPLAY_VER(i915)) {
> - case 12:
> + if (DISPLAY_VER(i915) >= 13)
> + lpsp_capable = encoder->port <= PORT_B;
> + else if (DISPLAY_VER(i915) >= 12)
>   /*
>* Actually TGL can drive LPSP on port till DDI_C
>* but there is no physical connected DDI_C on TGL sku's,
>* even driver is not initilizing DDI_C port for gen12.
>*/
> - LPSP_CAPABLE(encoder->port <= PORT_B);
> - break;
> - case 11:
> - LPSP_CAPABLE(connector->connector_type == 
> DRM_MODE_CONNECTOR_DSI ||
> -  connector->connector_type == 
> DRM_MODE_CONNECTOR_eDP);
> - break;
> - case 10:
> - case 9:
> - LPSP_CAPABLE(encoder->port == PORT_A &&
> -  (connector->connector_type == 
> DRM_MODE_CONNECTOR_DSI ||
> -  connector->connector_type == 
> DRM_MODE_CONNECTOR_eDP  ||
> -  connector->connector_type == 
> DRM_MODE_CONNECTOR_DisplayPort));
> - break;
> - default:
> - if (IS_HASWELL(i915) || IS_BROADWELL(i915))
> - LPSP_CAPABLE(connector->connector_type == 
> DRM_MODE_CONNECTOR_eDP);
> - }
> + lpsp_capable = encoder->port <= PORT_B;
> + else if (DISPLAY_VER(i915) == 11)
> + lpsp_capable = (connector->connector_type == 
> DRM_MODE_CONNECTOR_DSI ||
> + connector->connector_type == 
> DRM_MODE_CONNECTOR_eDP);
> + else if (IS_DISPLAY_VER(i915, 9, 10))
> + lpsp_capable = (encoder->port == PORT_A &&
> + (connector->connector_type == 
> DRM_MODE_CONNECTOR_DSI ||
> +  connector->connector_type == 
> DRM_MODE_CONNECTOR_eDP ||
> +  connector->connector_type == 
> DRM_MODE_CONNECTOR_DisplayPort));
> + else if (IS_HASWELL(i915) || IS_BROADWELL(i915))
> + lpsp_capable = connector->connector_type == 
> DRM_MODE_CONNECTOR_eDP;
> +
> + seq_printf(m, "LPSP: %s\n", lpsp_capable ? "capable" : "incapable");
>  
>   return 0;
>  }
> -- 
> 2.20.1
> 

Re: [Intel-gfx] [PATCH 1/5] drm/i915/debugfs: clean up LPSP status

[Rodrigo Vivi]

On Mon, Aug 30, 2021 at 03:53:40PM +0300, Jani Nikula wrote:
> Clean up the LPSP status printout. No functional changes.
> 
> Signed-off-by: Jani Nikula 

Reviewed-by: Rodrigo Vivi 

> ---
>  .../drm/i915/display/intel_display_debugfs.c  | 37 ++-
>  1 file changed, 11 insertions(+), 26 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c 
> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 8fdacb252bb1..d2a14a9c6857 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -1323,9 +1323,6 @@ static int i915_drrs_status(struct seq_file *m, void 
> *unused)
>   return 0;
>  }
>  
> -#define LPSP_STATUS(COND) (COND ? seq_puts(m, "LPSP: enabled\n") : \
> - seq_puts(m, "LPSP: disabled\n"))
> -
>  static bool
>  intel_lpsp_power_well_enabled(struct drm_i915_private *i915,
> enum i915_power_well_id power_well_id)
> @@ -1344,32 +1341,20 @@ intel_lpsp_power_well_enabled(struct drm_i915_private 
> *i915,
>  static int i915_lpsp_status(struct seq_file *m, void *unused)
>  {
>   struct drm_i915_private *i915 = node_to_i915(m->private);
> -
> - if (DISPLAY_VER(i915) >= 13) {
> - LPSP_STATUS(!intel_lpsp_power_well_enabled(i915,
> -SKL_DISP_PW_2));
> + bool lpsp_enabled = false;
> +
> + if (DISPLAY_VER(i915) >= 13 || IS_DISPLAY_VER(i915, 9, 10)) {
> + lpsp_enabled = !intel_lpsp_power_well_enabled(i915, 
> SKL_DISP_PW_2);
> + } else if (IS_DISPLAY_VER(i915, 11, 12)) {
> + lpsp_enabled = !intel_lpsp_power_well_enabled(i915, 
> ICL_DISP_PW_3);
> + } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
> + lpsp_enabled = !intel_lpsp_power_well_enabled(i915, 
> HSW_DISP_PW_GLOBAL);
> + } else {
> + seq_puts(m, "LPSP: not supported\n");
>   return 0;
>   }
>  
> - switch (DISPLAY_VER(i915)) {
> - case 12:
> - case 11:
> - LPSP_STATUS(!intel_lpsp_power_well_enabled(i915, 
> ICL_DISP_PW_3));
> - break;
> - case 10:
> - case 9:
> - LPSP_STATUS(!intel_lpsp_power_well_enabled(i915, 
> SKL_DISP_PW_2));
> - break;
> - default:
> - /*
> -  * Apart from HASWELL/BROADWELL other legacy platform doesn't
> -  * support lpsp.
> -  */
> - if (IS_HASWELL(i915) || IS_BROADWELL(i915))
> - LPSP_STATUS(!intel_lpsp_power_well_enabled(i915, 
> HSW_DISP_PW_GLOBAL));
> - else
> - seq_puts(m, "LPSP: not supported\n");
> - }
> + seq_printf(m, "LPSP: %s\n", enableddisabled(lpsp_enabled));
>  
>   return 0;
>  }
> -- 
> 2.20.1
> 

Re: [Intel-gfx] [PATCH 2/7] drm/i915/guc: put all guc objects in lmem when available

[Matthew Auld]

On Wed, 1 Sept 2021 at 03:21,  wrote:
>
> From: Daniele Ceraolo Spurio 
>
> The firmware binary has to be loaded from lmem and the recommendation is
> to put all other objects in there as well. Note that we don't fall back
> to system memory if the allocation in lmem fails because all objects are
> allocated during driver load and if we have issues with lmem at that point
> something is seriously wrong with the system, so no point in trying to
> handle it.
>
> Cc: Matthew Auld 
> Cc: Abdiel Janulgue 
> Cc: Michal Wajdeczko 
> Cc: Vinay Belgaumkar 
> Cc: Radoslaw Szwichtenberg 
> Signed-off-by: Daniele Ceraolo Spurio 
> Signed-off-by: Matthew Brost 
> ---
>  drivers/gpu/drm/i915/gem/i915_gem_lmem.c  | 26 
>  drivers/gpu/drm/i915/gem/i915_gem_lmem.h  |  4 ++
>  drivers/gpu/drm/i915/gt/uc/intel_guc.c|  9 ++-
>  drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 13 ++--
>  drivers/gpu/drm/i915/gt/uc/intel_huc.c| 14 -
>  drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c  | 75 +--
>  6 files changed, 128 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c 
> b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
> index eb345305dc52..034226c5d4d0 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
> @@ -103,6 +103,32 @@ __i915_gem_object_create_lmem_with_ps(struct 
> drm_i915_private *i915,
>  size, page_size, flags);
>  }
>
> +struct drm_i915_gem_object *
> +i915_gem_object_create_lmem_from_data(struct drm_i915_private *i915,
> + const void *data, size_t size)
> +{
> +   struct drm_i915_gem_object *obj;
> +   void *map;
> +
> +   obj = i915_gem_object_create_lmem(i915,
> + round_up(size, PAGE_SIZE),
> + I915_BO_ALLOC_CONTIGUOUS);

Maybe push the ALLOC_CONTIG into the caller and expose the flags
instead, assuming it's still needed for something GuC related?
pin_map() at least no longer has that constraint.

Re: [Intel-gfx] [PATCH 5/5] drm/i915/debugfs: pass intel_connector to intel_connector_debugfs_add()

[Rodrigo Vivi]

On Mon, Aug 30, 2021 at 03:53:44PM +0300, Jani Nikula wrote:
> Prefer the intel_ types. No functional changes.
> 
> Signed-off-by: Jani Nikula 
> ---
>  drivers/gpu/drm/i915/display/intel_connector.c   | 2 +-
>  drivers/gpu/drm/i915/display/intel_display_debugfs.c | 3 ++-
>  drivers/gpu/drm/i915/display/intel_display_debugfs.h | 4 ++--
>  3 files changed, 5 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_connector.c 
> b/drivers/gpu/drm/i915/display/intel_connector.c
> index 4f49d782eca2..c65f95a9a1ec 100644
> --- a/drivers/gpu/drm/i915/display/intel_connector.c
> +++ b/drivers/gpu/drm/i915/display/intel_connector.c
> @@ -124,7 +124,7 @@ int intel_connector_register(struct drm_connector 
> *connector)

oh, actually this is drm_connector

>   goto err_backlight;
>   }
>  
> - intel_connector_debugfs_add(connector);
> + intel_connector_debugfs_add(intel_connector);

so this fails...

>  
>   return 0;
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c 
> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 845e2dc76f87..82043a71e91f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -2444,8 +2444,9 @@ static const struct file_operations i915_dsc_bpp_fops = 
> {
>   * Cleanup will be done by drm_connector_unregister() through a call to
>   * drm_debugfs_connector_remove().
>   */
> -void intel_connector_debugfs_add(struct drm_connector *connector)
> +void intel_connector_debugfs_add(struct intel_connector *intel_connector)
>  {
> + struct drm_connector *connector = &intel_connector->base;
>   struct dentry *root = connector->debugfs_entry;
>   struct drm_i915_private *dev_priv = to_i915(connector->dev);
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.h 
> b/drivers/gpu/drm/i915/display/intel_display_debugfs.h
> index c72e35ecba1f..9b89b707ffe6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.h
> @@ -6,9 +6,9 @@
>  #ifndef __INTEL_DISPLAY_DEBUGFS_H__
>  #define __INTEL_DISPLAY_DEBUGFS_H__
>  
> -struct drm_connector;
>  struct drm_crtc;
>  struct drm_i915_private;
> +struct intel_connector;
>  
>  #ifdef CONFIG_DEBUG_FS
>  void intel_display_debugfs_register(struct drm_i915_private *i915);
> @@ -16,7 +16,7 @@ void intel_connector_debugfs_add(struct drm_connector 
> *connector);
>  void intel_crtc_debugfs_add(struct drm_crtc *crtc);
>  #else
>  static inline void intel_display_debugfs_register(struct drm_i915_private 
> *i915) {}
> -static inline void intel_connector_debugfs_add(struct drm_connector 
> *connector) {}
> +static inline void intel_connector_debugfs_add(struct intel_connector 
> *connector) {}
>  static inline void intel_crtc_debugfs_add(struct drm_crtc *crtc) {}
>  #endif
>  
> -- 
> 2.20.1
> 

[Intel-gfx] [PATCH v2 7/7] drm/i915/bios: get rid of vbt ddi_port_info

[Jani Nikula]

We can finally remove the extra caching in ddi_port_info. Good riddance.

v2: Rebased

Cc: José Roberto de Souza 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_bios.c | 63 +--
 drivers/gpu/drm/i915/i915_drv.h   |  7 +--
 2 files changed, 25 insertions(+), 45 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c 
b/drivers/gpu/drm/i915/display/intel_bios.c
index 0c16a848a6e4..052f27c0fb0c 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1580,16 +1580,16 @@ static u8 map_ddc_pin(struct drm_i915_private *i915, u8 
vbt_pin)
 
 static enum port get_port_by_ddc_pin(struct drm_i915_private *i915, u8 ddc_pin)
 {
-   const struct ddi_vbt_port_info *info;
+   const struct intel_bios_encoder_data *devdata;
enum port port;
 
if (!ddc_pin)
return PORT_NONE;
 
for_each_port(port) {
-   info = &i915->vbt.ddi_port_info[port];
+   devdata = i915->vbt.ports[port];
 
-   if (info->devdata && ddc_pin == info->devdata->child.ddc_pin)
+   if (devdata && ddc_pin == devdata->child.ddc_pin)
return port;
}
 
@@ -1600,7 +1600,6 @@ static void sanitize_ddc_pin(struct 
intel_bios_encoder_data *devdata,
 enum port port)
 {
struct drm_i915_private *i915 = devdata->i915;
-   struct ddi_vbt_port_info *info;
struct child_device_config *child;
u8 mapped_ddc_pin;
enum port p;
@@ -1637,8 +1636,7 @@ static void sanitize_ddc_pin(struct 
intel_bios_encoder_data *devdata,
 * there are real machines (eg. Asrock B250M-HDV) where VBT has both
 * port A and port E with the same AUX ch and we must pick port E :(
 */
-   info = &i915->vbt.ddi_port_info[p];
-   child = &info->devdata->child;
+   child = &i915->vbt.ports[p]->child;
 
child->device_type &= ~DEVICE_TYPE_TMDS_DVI_SIGNALING;
child->device_type |= DEVICE_TYPE_NOT_HDMI_OUTPUT;
@@ -1648,16 +1646,16 @@ static void sanitize_ddc_pin(struct 
intel_bios_encoder_data *devdata,
 
 static enum port get_port_by_aux_ch(struct drm_i915_private *i915, u8 aux_ch)
 {
-   const struct ddi_vbt_port_info *info;
+   const struct intel_bios_encoder_data *devdata;
enum port port;
 
if (!aux_ch)
return PORT_NONE;
 
for_each_port(port) {
-   info = &i915->vbt.ddi_port_info[port];
+   devdata = i915->vbt.ports[port];
 
-   if (info->devdata && aux_ch == info->devdata->child.aux_channel)
+   if (devdata && aux_ch == devdata->child.aux_channel)
return port;
}
 
@@ -1668,7 +1666,6 @@ static void sanitize_aux_ch(struct 
intel_bios_encoder_data *devdata,
enum port port)
 {
struct drm_i915_private *i915 = devdata->i915;
-   struct ddi_vbt_port_info *info;
struct child_device_config *child;
enum port p;
 
@@ -1691,8 +1688,7 @@ static void sanitize_aux_ch(struct 
intel_bios_encoder_data *devdata,
 * there are real machines (eg. Asrock B250M-HDV) where VBT has both
 * port A and port E with the same AUX ch and we must pick port E :(
 */
-   info = &i915->vbt.ddi_port_info[p];
-   child = &info->devdata->child;
+   child = &i915->vbt.ports[p]->child;
 
child->device_type &= ~DEVICE_TYPE_DISPLAYPORT_OUTPUT;
child->aux_channel = 0;
@@ -1938,7 +1934,6 @@ static void parse_ddi_port(struct drm_i915_private *i915,
   struct intel_bios_encoder_data *devdata)
 {
const struct child_device_config *child = &devdata->child;
-   struct ddi_vbt_port_info *info;
bool is_dvi, is_hdmi, is_dp, is_edp, is_crt, supports_typec_usb, 
supports_tbt;
int dp_boost_level, dp_max_link_rate, hdmi_boost_level, 
hdmi_level_shift, max_tmds_clock;
enum port port;
@@ -1954,9 +1949,7 @@ static void parse_ddi_port(struct drm_i915_private *i915,
return;
}
 
-   info = &i915->vbt.ddi_port_info[port];
-
-   if (info->devdata) {
+   if (i915->vbt.ports[port]) {
drm_dbg_kms(&i915->drm,
"More than one child device for port %c in VBT, 
using the first.\n",
port_name(port));
@@ -2019,7 +2012,7 @@ static void parse_ddi_port(struct drm_i915_private *i915,
"Port %c VBT DP max link rate: %d\n",
port_name(port), dp_max_link_rate);
 
-   info->devdata = devdata;
+   i915->vbt.ports[port] = devdata;
 }
 
 static void parse_ddi_ports(struct drm_i915_private *i915)
@@ -2557,12 +2550,8 @@ bool intel_bios_is_port_present(struct drm_i915_private 
*i915, enum port port)
[PORT_F] = { DVO_PORT_DPF, DVO_PORT_HDMIF, },
};
 
-   if (HAS_DDI(

[Intel-gfx] [PATCH v2 5/7] drm/i915/bios: move ddc pin mapping code next to ddc pin sanitize

[Jani Nikula]

Move code around to avoid a forward declaration in the future.

Cc: José Roberto de Souza 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_bios.c | 154 +++---
 1 file changed, 77 insertions(+), 77 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c 
b/drivers/gpu/drm/i915/display/intel_bios.c
index 69d7da66f168..b4113506b3b8 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1501,6 +1501,83 @@ static u8 translate_iboost(u8 val)
return mapping[val];
 }
 
+static const u8 cnp_ddc_pin_map[] = {
+   [0] = 0, /* N/A */
+   [DDC_BUS_DDI_B] = GMBUS_PIN_1_BXT,
+   [DDC_BUS_DDI_C] = GMBUS_PIN_2_BXT,
+   [DDC_BUS_DDI_D] = GMBUS_PIN_4_CNP, /* sic */
+   [DDC_BUS_DDI_F] = GMBUS_PIN_3_BXT, /* sic */
+};
+
+static const u8 icp_ddc_pin_map[] = {
+   [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT,
+   [ICL_DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT,
+   [TGL_DDC_BUS_DDI_C] = GMBUS_PIN_3_BXT,
+   [ICL_DDC_BUS_PORT_1] = GMBUS_PIN_9_TC1_ICP,
+   [ICL_DDC_BUS_PORT_2] = GMBUS_PIN_10_TC2_ICP,
+   [ICL_DDC_BUS_PORT_3] = GMBUS_PIN_11_TC3_ICP,
+   [ICL_DDC_BUS_PORT_4] = GMBUS_PIN_12_TC4_ICP,
+   [TGL_DDC_BUS_PORT_5] = GMBUS_PIN_13_TC5_TGP,
+   [TGL_DDC_BUS_PORT_6] = GMBUS_PIN_14_TC6_TGP,
+};
+
+static const u8 rkl_pch_tgp_ddc_pin_map[] = {
+   [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT,
+   [ICL_DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT,
+   [RKL_DDC_BUS_DDI_D] = GMBUS_PIN_9_TC1_ICP,
+   [RKL_DDC_BUS_DDI_E] = GMBUS_PIN_10_TC2_ICP,
+};
+
+static const u8 adls_ddc_pin_map[] = {
+   [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT,
+   [ADLS_DDC_BUS_PORT_TC1] = GMBUS_PIN_9_TC1_ICP,
+   [ADLS_DDC_BUS_PORT_TC2] = GMBUS_PIN_10_TC2_ICP,
+   [ADLS_DDC_BUS_PORT_TC3] = GMBUS_PIN_11_TC3_ICP,
+   [ADLS_DDC_BUS_PORT_TC4] = GMBUS_PIN_12_TC4_ICP,
+};
+
+static const u8 gen9bc_tgp_ddc_pin_map[] = {
+   [DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT,
+   [DDC_BUS_DDI_C] = GMBUS_PIN_9_TC1_ICP,
+   [DDC_BUS_DDI_D] = GMBUS_PIN_10_TC2_ICP,
+};
+
+static u8 map_ddc_pin(struct drm_i915_private *i915, u8 vbt_pin)
+{
+   const u8 *ddc_pin_map;
+   int n_entries;
+
+   if (IS_ALDERLAKE_S(i915)) {
+   ddc_pin_map = adls_ddc_pin_map;
+   n_entries = ARRAY_SIZE(adls_ddc_pin_map);
+   } else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) {
+   return vbt_pin;
+   } else if (IS_ROCKETLAKE(i915) && INTEL_PCH_TYPE(i915) == PCH_TGP) {
+   ddc_pin_map = rkl_pch_tgp_ddc_pin_map;
+   n_entries = ARRAY_SIZE(rkl_pch_tgp_ddc_pin_map);
+   } else if (HAS_PCH_TGP(i915) && DISPLAY_VER(i915) == 9) {
+   ddc_pin_map = gen9bc_tgp_ddc_pin_map;
+   n_entries = ARRAY_SIZE(gen9bc_tgp_ddc_pin_map);
+   } else if (INTEL_PCH_TYPE(i915) >= PCH_ICP) {
+   ddc_pin_map = icp_ddc_pin_map;
+   n_entries = ARRAY_SIZE(icp_ddc_pin_map);
+   } else if (HAS_PCH_CNP(i915)) {
+   ddc_pin_map = cnp_ddc_pin_map;
+   n_entries = ARRAY_SIZE(cnp_ddc_pin_map);
+   } else {
+   /* Assuming direct map */
+   return vbt_pin;
+   }
+
+   if (vbt_pin < n_entries && ddc_pin_map[vbt_pin] != 0)
+   return ddc_pin_map[vbt_pin];
+
+   drm_dbg_kms(&i915->drm,
+   "Ignoring alternate pin: VBT claims DDC pin %d, which is 
not valid for this platform\n",
+   vbt_pin);
+   return 0;
+}
+
 static enum port get_port_by_ddc_pin(struct drm_i915_private *i915, u8 ddc_pin)
 {
const struct ddi_vbt_port_info *info;
@@ -1606,83 +1683,6 @@ static void sanitize_aux_ch(struct 
intel_bios_encoder_data *devdata,
child->aux_channel = 0;
 }
 
-static const u8 cnp_ddc_pin_map[] = {
-   [0] = 0, /* N/A */
-   [DDC_BUS_DDI_B] = GMBUS_PIN_1_BXT,
-   [DDC_BUS_DDI_C] = GMBUS_PIN_2_BXT,
-   [DDC_BUS_DDI_D] = GMBUS_PIN_4_CNP, /* sic */
-   [DDC_BUS_DDI_F] = GMBUS_PIN_3_BXT, /* sic */
-};
-
-static const u8 icp_ddc_pin_map[] = {
-   [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT,
-   [ICL_DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT,
-   [TGL_DDC_BUS_DDI_C] = GMBUS_PIN_3_BXT,
-   [ICL_DDC_BUS_PORT_1] = GMBUS_PIN_9_TC1_ICP,
-   [ICL_DDC_BUS_PORT_2] = GMBUS_PIN_10_TC2_ICP,
-   [ICL_DDC_BUS_PORT_3] = GMBUS_PIN_11_TC3_ICP,
-   [ICL_DDC_BUS_PORT_4] = GMBUS_PIN_12_TC4_ICP,
-   [TGL_DDC_BUS_PORT_5] = GMBUS_PIN_13_TC5_TGP,
-   [TGL_DDC_BUS_PORT_6] = GMBUS_PIN_14_TC6_TGP,
-};
-
-static const u8 rkl_pch_tgp_ddc_pin_map[] = {
-   [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT,
-   [ICL_DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT,
-   [RKL_DDC_BUS_DDI_D] = GMBUS_PIN_9_TC1_ICP,
-   [RKL_DDC_BUS_DDI_E] = GMBUS_PIN_10_TC2_ICP,
-};
-
-static const u8 adls_ddc_pin_map[] = {
-   [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT,
-   [ADLS_DDC_BUS_PORT_TC1] = GMBUS_PIN_9_TC1_ICP,
-   [ADLS_DDC_BUS_PORT_TC2] = GMBUS

[Intel-gfx] [PATCH v2 6/7] drm/i915/bios: use ddc pin directly from child data

[Jani Nikula]

Avoid extra caching of the data. This is slightly more subtle than one
would think. For one thing, we explicitly ignore 0 value in child device
ddc pin; this is specified as N/A and does not warrant a warning. For
another, we start looking for ddc pin collisions in sanitize using
unmapped pin numbering.

v2: Check !devdata in intel_bios_alternate_ddc_pin()

Cc: José Roberto de Souza 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_bios.c | 49 +--
 drivers/gpu/drm/i915/i915_drv.h   |  2 -
 2 files changed, 28 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c 
b/drivers/gpu/drm/i915/display/intel_bios.c
index b4113506b3b8..0c16a848a6e4 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1589,28 +1589,43 @@ static enum port get_port_by_ddc_pin(struct 
drm_i915_private *i915, u8 ddc_pin)
for_each_port(port) {
info = &i915->vbt.ddi_port_info[port];
 
-   if (info->devdata && ddc_pin == info->alternate_ddc_pin)
+   if (info->devdata && ddc_pin == info->devdata->child.ddc_pin)
return port;
}
 
return PORT_NONE;
 }
 
-static void sanitize_ddc_pin(struct drm_i915_private *i915,
+static void sanitize_ddc_pin(struct intel_bios_encoder_data *devdata,
 enum port port)
 {
-   struct ddi_vbt_port_info *info = &i915->vbt.ddi_port_info[port];
+   struct drm_i915_private *i915 = devdata->i915;
+   struct ddi_vbt_port_info *info;
struct child_device_config *child;
+   u8 mapped_ddc_pin;
enum port p;
 
-   p = get_port_by_ddc_pin(i915, info->alternate_ddc_pin);
+   if (!devdata->child.ddc_pin)
+   return;
+
+   mapped_ddc_pin = map_ddc_pin(i915, devdata->child.ddc_pin);
+   if (!intel_gmbus_is_valid_pin(i915, mapped_ddc_pin)) {
+   drm_dbg_kms(&i915->drm,
+   "Port %c has invalid DDC pin %d, "
+   "sticking to defaults\n",
+   port_name(port), mapped_ddc_pin);
+   devdata->child.ddc_pin = 0;
+   return;
+   }
+
+   p = get_port_by_ddc_pin(i915, devdata->child.ddc_pin);
if (p == PORT_NONE)
return;
 
drm_dbg_kms(&i915->drm,
"port %c trying to use the same DDC pin (0x%x) as port %c, "
"disabling port %c DVI/HDMI support\n",
-   port_name(port), info->alternate_ddc_pin,
+   port_name(port), mapped_ddc_pin,
port_name(p), port_name(p));
 
/*
@@ -1628,7 +1643,7 @@ static void sanitize_ddc_pin(struct drm_i915_private 
*i915,
child->device_type &= ~DEVICE_TYPE_TMDS_DVI_SIGNALING;
child->device_type |= DEVICE_TYPE_NOT_HDMI_OUTPUT;
 
-   info->alternate_ddc_pin = 0;
+   child->ddc_pin = 0;
 }
 
 static enum port get_port_by_aux_ch(struct drm_i915_private *i915, u8 aux_ch)
@@ -1966,20 +1981,8 @@ static void parse_ddi_port(struct drm_i915_private *i915,
supports_typec_usb, supports_tbt,
devdata->dsc != NULL);
 
-   if (is_dvi) {
-   u8 ddc_pin;
-
-   ddc_pin = map_ddc_pin(i915, child->ddc_pin);
-   if (intel_gmbus_is_valid_pin(i915, ddc_pin)) {
-   info->alternate_ddc_pin = ddc_pin;
-   sanitize_ddc_pin(i915, port);
-   } else {
-   drm_dbg_kms(&i915->drm,
-   "Port %c has invalid DDC pin %d, "
-   "sticking to defaults\n",
-   port_name(port), ddc_pin);
-   }
-   }
+   if (is_dvi)
+   sanitize_ddc_pin(devdata, port);
 
if (is_dp)
sanitize_aux_ch(devdata, port);
@@ -2993,8 +2996,12 @@ int intel_bios_dp_max_link_rate(struct intel_encoder 
*encoder)
 int intel_bios_alternate_ddc_pin(struct intel_encoder *encoder)
 {
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+   const struct intel_bios_encoder_data *devdata = 
i915->vbt.ddi_port_info[encoder->port].devdata;
+
+   if (!devdata || !devdata->child.ddc_pin)
+   return 0;
 
-   return i915->vbt.ddi_port_info[encoder->port].alternate_ddc_pin;
+   return map_ddc_pin(i915, devdata->child.ddc_pin);
 }
 
 bool intel_bios_encoder_supports_typec_usb(const struct 
intel_bios_encoder_data *devdata)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 032d59119407..744181cbe21c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -638,8 +638,6 @@ i915_fence_timeout(const struct drm_i915_private *i915)
 struct ddi_vbt_port_info {
/* Non-NULL if port present. */
struct intel_bios_encoder_data *devdata

[Intel-gfx] [PATCH v2 4/7] drm/i915/bios: use alternate aux channel directly from child data

[Jani Nikula]

Avoid extra caching of the data.

v2: Check for !info->devdata in intel_bios_port_aux_ch() (Ankit)

Cc: José Roberto de Souza 
Cc: Ankit Nautiyal 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_bios.c | 26 +++
 drivers/gpu/drm/i915/i915_drv.h   |  1 -
 2 files changed, 12 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c 
b/drivers/gpu/drm/i915/display/intel_bios.c
index 10b2beddc121..69d7da66f168 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1565,28 +1565,29 @@ static enum port get_port_by_aux_ch(struct 
drm_i915_private *i915, u8 aux_ch)
for_each_port(port) {
info = &i915->vbt.ddi_port_info[port];
 
-   if (info->devdata && aux_ch == info->alternate_aux_channel)
+   if (info->devdata && aux_ch == info->devdata->child.aux_channel)
return port;
}
 
return PORT_NONE;
 }
 
-static void sanitize_aux_ch(struct drm_i915_private *i915,
+static void sanitize_aux_ch(struct intel_bios_encoder_data *devdata,
enum port port)
 {
-   struct ddi_vbt_port_info *info = &i915->vbt.ddi_port_info[port];
+   struct drm_i915_private *i915 = devdata->i915;
+   struct ddi_vbt_port_info *info;
struct child_device_config *child;
enum port p;
 
-   p = get_port_by_aux_ch(i915, info->alternate_aux_channel);
+   p = get_port_by_aux_ch(i915, devdata->child.aux_channel);
if (p == PORT_NONE)
return;
 
drm_dbg_kms(&i915->drm,
"port %c trying to use the same AUX CH (0x%x) as port %c, "
"disabling port %c DP support\n",
-   port_name(port), info->alternate_aux_channel,
+   port_name(port), devdata->child.aux_channel,
port_name(p), port_name(p));
 
/*
@@ -1602,7 +1603,7 @@ static void sanitize_aux_ch(struct drm_i915_private *i915,
child = &info->devdata->child;
 
child->device_type &= ~DEVICE_TYPE_DISPLAYPORT_OUTPUT;
-   info->alternate_aux_channel = 0;
+   child->aux_channel = 0;
 }
 
 static const u8 cnp_ddc_pin_map[] = {
@@ -1980,11 +1981,8 @@ static void parse_ddi_port(struct drm_i915_private *i915,
}
}
 
-   if (is_dp) {
-   info->alternate_aux_channel = child->aux_channel;
-
-   sanitize_aux_ch(i915, port);
-   }
+   if (is_dp)
+   sanitize_aux_ch(devdata, port);
 
hdmi_level_shift = _intel_bios_hdmi_level_shift(devdata);
if (hdmi_level_shift >= 0) {
@@ -2863,7 +2861,7 @@ enum aux_ch intel_bios_port_aux_ch(struct 
drm_i915_private *i915,
&i915->vbt.ddi_port_info[port];
enum aux_ch aux_ch;
 
-   if (!info->alternate_aux_channel) {
+   if (!info->devdata || !info->devdata->child.aux_channel) {
aux_ch = (enum aux_ch)port;
 
drm_dbg_kms(&i915->drm,
@@ -2879,7 +2877,7 @@ enum aux_ch intel_bios_port_aux_ch(struct 
drm_i915_private *i915,
 * ADL-S VBT uses PHY based mapping. Combo PHYs A,B,C,D,E
 * map to DDI A,TC1,TC2,TC3,TC4 respectively.
 */
-   switch (info->alternate_aux_channel) {
+   switch (info->devdata->child.aux_channel) {
case DP_AUX_A:
aux_ch = AUX_CH_A;
break;
@@ -2940,7 +2938,7 @@ enum aux_ch intel_bios_port_aux_ch(struct 
drm_i915_private *i915,
aux_ch = AUX_CH_I;
break;
default:
-   MISSING_CASE(info->alternate_aux_channel);
+   MISSING_CASE(info->devdata->child.aux_channel);
aux_ch = AUX_CH_A;
break;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 586b5368d4fc..032d59119407 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -639,7 +639,6 @@ struct ddi_vbt_port_info {
/* Non-NULL if port present. */
struct intel_bios_encoder_data *devdata;
 
-   u8 alternate_aux_channel;
u8 alternate_ddc_pin;
 };
 
-- 
2.30.2

[Intel-gfx] [PATCH v2 3/7] drm/i915/bios: use dp max link rate directly from child data

[Jani Nikula]

Avoid extra caching of the data.

Cc: José Roberto de Souza 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_bios.c | 28 ++-
 drivers/gpu/drm/i915/i915_drv.h   |  2 --
 2 files changed, 17 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c 
b/drivers/gpu/drm/i915/display/intel_bios.c
index 253a528ba61a..10b2beddc121 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1815,6 +1815,17 @@ static int parse_bdb_216_dp_max_link_rate(const int 
vbt_max_link_rate)
}
 }
 
+static int _intel_bios_dp_max_link_rate(const struct intel_bios_encoder_data 
*devdata)
+{
+   if (!devdata || devdata->i915->vbt.version < 216)
+   return 0;
+
+   if (devdata->i915->vbt.version >= 230)
+   return 
parse_bdb_230_dp_max_link_rate(devdata->child.dp_max_link_rate);
+   else
+   return 
parse_bdb_216_dp_max_link_rate(devdata->child.dp_max_link_rate);
+}
+
 static void sanitize_device_type(struct intel_bios_encoder_data *devdata,
 enum port port)
 {
@@ -1913,7 +1924,7 @@ static void parse_ddi_port(struct drm_i915_private *i915,
const struct child_device_config *child = &devdata->child;
struct ddi_vbt_port_info *info;
bool is_dvi, is_hdmi, is_dp, is_edp, is_crt, supports_typec_usb, 
supports_tbt;
-   int dp_boost_level, hdmi_boost_level, hdmi_level_shift, max_tmds_clock;
+   int dp_boost_level, dp_max_link_rate, hdmi_boost_level, 
hdmi_level_shift, max_tmds_clock;
enum port port;
 
port = dvo_port_to_port(i915, child->dvo_port);
@@ -2001,17 +2012,11 @@ static void parse_ddi_port(struct drm_i915_private 
*i915,
"Port %c VBT HDMI boost level: %d\n",
port_name(port), hdmi_boost_level);
 
-   /* DP max link rate for GLK+ */
-   if (i915->vbt.version >= 216) {
-   if (i915->vbt.version >= 230)
-   info->dp_max_link_rate = 
parse_bdb_230_dp_max_link_rate(child->dp_max_link_rate);
-   else
-   info->dp_max_link_rate = 
parse_bdb_216_dp_max_link_rate(child->dp_max_link_rate);
-
+   dp_max_link_rate = _intel_bios_dp_max_link_rate(devdata);
+   if (dp_max_link_rate)
drm_dbg_kms(&i915->drm,
"Port %c VBT DP max link rate: %d\n",
-   port_name(port), info->dp_max_link_rate);
-   }
+   port_name(port), dp_max_link_rate);
 
info->devdata = devdata;
 }
@@ -2982,8 +2987,9 @@ int intel_bios_encoder_hdmi_boost_level(const struct 
intel_bios_encoder_data *de
 int intel_bios_dp_max_link_rate(struct intel_encoder *encoder)
 {
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+   const struct intel_bios_encoder_data *devdata = 
i915->vbt.ddi_port_info[encoder->port].devdata;
 
-   return i915->vbt.ddi_port_info[encoder->port].dp_max_link_rate;
+   return _intel_bios_dp_max_link_rate(devdata);
 }
 
 int intel_bios_alternate_ddc_pin(struct intel_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8b4a31265978..586b5368d4fc 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -641,8 +641,6 @@ struct ddi_vbt_port_info {
 
u8 alternate_aux_channel;
u8 alternate_ddc_pin;
-
-   int dp_max_link_rate;   /* 0 for not limited by VBT */
 };
 
 enum psr_lines_to_wait {
-- 
2.30.2

[Intel-gfx] [PATCH v2 2/7] drm/i915/bios: use max tmds clock directly from child data

[Jani Nikula]

Avoid extra caching of the data.

Cc: José Roberto de Souza 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_bios.c | 52 +++
 drivers/gpu/drm/i915/i915_drv.h   |  2 -
 2 files changed, 26 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c 
b/drivers/gpu/drm/i915/display/intel_bios.c
index afb5fcd9dd0c..253a528ba61a 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1876,6 +1876,24 @@ static int _intel_bios_hdmi_level_shift(const struct 
intel_bios_encoder_data *de
return devdata->child.hdmi_level_shifter_value;
 }
 
+static int _intel_bios_max_tmds_clock(const struct intel_bios_encoder_data 
*devdata)
+{
+   if (!devdata || devdata->i915->vbt.version < 204)
+   return 0;
+
+   switch (devdata->child.hdmi_max_data_rate) {
+   default:
+   MISSING_CASE(devdata->child.hdmi_max_data_rate);
+   fallthrough;
+   case HDMI_MAX_DATA_RATE_PLATFORM:
+   return 0;
+   case HDMI_MAX_DATA_RATE_297:
+   return 297000;
+   case HDMI_MAX_DATA_RATE_165:
+   return 165000;
+   }
+}
+
 static bool is_port_valid(struct drm_i915_private *i915, enum port port)
 {
/*
@@ -1895,7 +1913,7 @@ static void parse_ddi_port(struct drm_i915_private *i915,
const struct child_device_config *child = &devdata->child;
struct ddi_vbt_port_info *info;
bool is_dvi, is_hdmi, is_dp, is_edp, is_crt, supports_typec_usb, 
supports_tbt;
-   int dp_boost_level, hdmi_boost_level, hdmi_level_shift;
+   int dp_boost_level, hdmi_boost_level, hdmi_level_shift, max_tmds_clock;
enum port port;
 
port = dvo_port_to_port(i915, child->dvo_port);
@@ -1964,30 +1982,11 @@ static void parse_ddi_port(struct drm_i915_private 
*i915,
port_name(port), hdmi_level_shift);
}
 
-   if (i915->vbt.version >= 204) {
-   int max_tmds_clock;
-
-   switch (child->hdmi_max_data_rate) {
-   default:
-   MISSING_CASE(child->hdmi_max_data_rate);
-   fallthrough;
-   case HDMI_MAX_DATA_RATE_PLATFORM:
-   max_tmds_clock = 0;
-   break;
-   case HDMI_MAX_DATA_RATE_297:
-   max_tmds_clock = 297000;
-   break;
-   case HDMI_MAX_DATA_RATE_165:
-   max_tmds_clock = 165000;
-   break;
-   }
-
-   if (max_tmds_clock)
-   drm_dbg_kms(&i915->drm,
-   "Port %c VBT HDMI max TMDS clock: %d kHz\n",
-   port_name(port), max_tmds_clock);
-   info->max_tmds_clock = max_tmds_clock;
-   }
+   max_tmds_clock = _intel_bios_max_tmds_clock(devdata);
+   if (max_tmds_clock)
+   drm_dbg_kms(&i915->drm,
+   "Port %c VBT HDMI max TMDS clock: %d kHz\n",
+   port_name(port), max_tmds_clock);
 
/* I_boost config for SKL and above */
dp_boost_level = intel_bios_encoder_dp_boost_level(devdata);
@@ -2950,8 +2949,9 @@ enum aux_ch intel_bios_port_aux_ch(struct 
drm_i915_private *i915,
 int intel_bios_max_tmds_clock(struct intel_encoder *encoder)
 {
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+   const struct intel_bios_encoder_data *devdata = 
i915->vbt.ddi_port_info[encoder->port].devdata;
 
-   return i915->vbt.ddi_port_info[encoder->port].max_tmds_clock;
+   return _intel_bios_max_tmds_clock(devdata);
 }
 
 /* This is an index in the HDMI/DVI DDI buffer translation table, or -1 */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 67a9f07550d4..8b4a31265978 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -639,8 +639,6 @@ struct ddi_vbt_port_info {
/* Non-NULL if port present. */
struct intel_bios_encoder_data *devdata;
 
-   int max_tmds_clock;
-
u8 alternate_aux_channel;
u8 alternate_ddc_pin;
 
-- 
2.30.2

[Intel-gfx] [PATCH v2 1/7] drm/i915/bios: use hdmi level shift directly from child data

[Jani Nikula]

Avoid extra caching of the data.

Cc: José Roberto de Souza 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_bios.c | 26 +--
 drivers/gpu/drm/i915/i915_drv.h   |  4 
 2 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c 
b/drivers/gpu/drm/i915/display/intel_bios.c
index e86e6ed2d3bf..afb5fcd9dd0c 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1868,6 +1868,14 @@ intel_bios_encoder_supports_edp(const struct 
intel_bios_encoder_data *devdata)
devdata->child.device_type & DEVICE_TYPE_INTERNAL_CONNECTOR;
 }
 
+static int _intel_bios_hdmi_level_shift(const struct intel_bios_encoder_data 
*devdata)
+{
+   if (!devdata || devdata->i915->vbt.version < 158)
+   return -1;
+
+   return devdata->child.hdmi_level_shifter_value;
+}
+
 static bool is_port_valid(struct drm_i915_private *i915, enum port port)
 {
/*
@@ -1887,7 +1895,7 @@ static void parse_ddi_port(struct drm_i915_private *i915,
const struct child_device_config *child = &devdata->child;
struct ddi_vbt_port_info *info;
bool is_dvi, is_hdmi, is_dp, is_edp, is_crt, supports_typec_usb, 
supports_tbt;
-   int dp_boost_level, hdmi_boost_level;
+   int dp_boost_level, hdmi_boost_level, hdmi_level_shift;
enum port port;
 
port = dvo_port_to_port(i915, child->dvo_port);
@@ -1949,15 +1957,11 @@ static void parse_ddi_port(struct drm_i915_private 
*i915,
sanitize_aux_ch(i915, port);
}
 
-   if (i915->vbt.version >= 158) {
-   /* The VBT HDMI level shift values match the table we have. */
-   u8 hdmi_level_shift = child->hdmi_level_shifter_value;
+   hdmi_level_shift = _intel_bios_hdmi_level_shift(devdata);
+   if (hdmi_level_shift >= 0) {
drm_dbg_kms(&i915->drm,
"Port %c VBT HDMI level shift: %d\n",
-   port_name(port),
-   hdmi_level_shift);
-   info->hdmi_level_shift = hdmi_level_shift;
-   info->hdmi_level_shift_set = true;
+   port_name(port), hdmi_level_shift);
}
 
if (i915->vbt.version >= 204) {
@@ -2950,13 +2954,13 @@ int intel_bios_max_tmds_clock(struct intel_encoder 
*encoder)
return i915->vbt.ddi_port_info[encoder->port].max_tmds_clock;
 }
 
+/* This is an index in the HDMI/DVI DDI buffer translation table, or -1 */
 int intel_bios_hdmi_level_shift(struct intel_encoder *encoder)
 {
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
-   const struct ddi_vbt_port_info *info =
-   &i915->vbt.ddi_port_info[encoder->port];
+   const struct intel_bios_encoder_data *devdata = 
i915->vbt.ddi_port_info[encoder->port].devdata;
 
-   return info->hdmi_level_shift_set ? info->hdmi_level_shift : -1;
+   return _intel_bios_hdmi_level_shift(devdata);
 }
 
 int intel_bios_encoder_dp_boost_level(const struct intel_bios_encoder_data 
*devdata)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index be2392bbcecc..67a9f07550d4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -641,10 +641,6 @@ struct ddi_vbt_port_info {
 
int max_tmds_clock;
 
-   /* This is an index in the HDMI/DVI DDI buffer translation table. */
-   u8 hdmi_level_shift;
-   u8 hdmi_level_shift_set:1;
-
u8 alternate_aux_channel;
u8 alternate_ddc_pin;
 
-- 
2.30.2

[Intel-gfx] [PATCH v2 0/7] drm/i915/bios: remove vbt ddi_port_info caching

[Jani Nikula]

v2 of https://patchwork.freedesktop.org/series/93957/ with the CI issues
fixed (fingers crossed!).

BR,
Jani.

Jani Nikula (7):
  drm/i915/bios: use hdmi level shift directly from child data
  drm/i915/bios: use max tmds clock directly from child data
  drm/i915/bios: use dp max link rate directly from child data
  drm/i915/bios: use alternate aux channel directly from child data
  drm/i915/bios: move ddc pin mapping code next to ddc pin sanitize
  drm/i915/bios: use ddc pin directly from child data
  drm/i915/bios: get rid of vbt ddi_port_info

 drivers/gpu/drm/i915/display/intel_bios.c | 372 +++---
 drivers/gpu/drm/i915/i915_drv.h   |  18 +-
 2 files changed, 187 insertions(+), 203 deletions(-)

-- 
2.30.2

Re: [Intel-gfx] [PATCH 5/5] drm/i915/debugfs: pass intel_connector to intel_connector_debugfs_add()

[Rodrigo Vivi]

On Mon, Aug 30, 2021 at 03:53:44PM +0300, Jani Nikula wrote:
> Prefer the intel_ types. No functional changes.
> 
> Signed-off-by: Jani Nikula 

Reviewed-by: Rodrigo Vivi 

> ---
>  drivers/gpu/drm/i915/display/intel_connector.c   | 2 +-
>  drivers/gpu/drm/i915/display/intel_display_debugfs.c | 3 ++-
>  drivers/gpu/drm/i915/display/intel_display_debugfs.h | 4 ++--
>  3 files changed, 5 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_connector.c 
> b/drivers/gpu/drm/i915/display/intel_connector.c
> index 4f49d782eca2..c65f95a9a1ec 100644
> --- a/drivers/gpu/drm/i915/display/intel_connector.c
> +++ b/drivers/gpu/drm/i915/display/intel_connector.c
> @@ -124,7 +124,7 @@ int intel_connector_register(struct drm_connector 
> *connector)
>   goto err_backlight;
>   }
>  
> - intel_connector_debugfs_add(connector);
> + intel_connector_debugfs_add(intel_connector);
>  
>   return 0;
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c 
> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 845e2dc76f87..82043a71e91f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -2444,8 +2444,9 @@ static const struct file_operations i915_dsc_bpp_fops = 
> {
>   * Cleanup will be done by drm_connector_unregister() through a call to
>   * drm_debugfs_connector_remove().
>   */
> -void intel_connector_debugfs_add(struct drm_connector *connector)
> +void intel_connector_debugfs_add(struct intel_connector *intel_connector)
>  {
> + struct drm_connector *connector = &intel_connector->base;
>   struct dentry *root = connector->debugfs_entry;
>   struct drm_i915_private *dev_priv = to_i915(connector->dev);
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.h 
> b/drivers/gpu/drm/i915/display/intel_display_debugfs.h
> index c72e35ecba1f..9b89b707ffe6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.h
> @@ -6,9 +6,9 @@
>  #ifndef __INTEL_DISPLAY_DEBUGFS_H__
>  #define __INTEL_DISPLAY_DEBUGFS_H__
>  
> -struct drm_connector;
>  struct drm_crtc;
>  struct drm_i915_private;
> +struct intel_connector;
>  
>  #ifdef CONFIG_DEBUG_FS
>  void intel_display_debugfs_register(struct drm_i915_private *i915);
> @@ -16,7 +16,7 @@ void intel_connector_debugfs_add(struct drm_connector 
> *connector);
>  void intel_crtc_debugfs_add(struct drm_crtc *crtc);
>  #else
>  static inline void intel_display_debugfs_register(struct drm_i915_private 
> *i915) {}
> -static inline void intel_connector_debugfs_add(struct drm_connector 
> *connector) {}
> +static inline void intel_connector_debugfs_add(struct intel_connector 
> *connector) {}
>  static inline void intel_crtc_debugfs_add(struct drm_crtc *crtc) {}
>  #endif
>  
> -- 
> 2.20.1
> 

Re: [Intel-gfx] [PATCH v7 13/17] drm/i915/pxp: Add plane decryption support

[Rodrigo Vivi]

On Fri, Aug 27, 2021 at 06:27:34PM -0700, Daniele Ceraolo Spurio wrote:
> From: Anshuman Gupta 
> 
> Add support to enable/disable PLANE_SURF Decryption Request bit.
> It requires only to enable plane decryption support when following
> condition met.
> 1. PXP session is enabled.
> 2. Buffer object is protected.
> 
> v2:
> - Used gen fb obj user_flags instead gem_object_metadata. [Krishna]
> 
> v3:
> - intel_pxp_gem_object_status() API changes.
> 
> v4: use intel_pxp_is_active (Daniele)
> 
> v5: rebase and use the new protected object status checker (Daniele)
> 
> v6: used plane state for plane_decryption to handle async flip
> as suggested by Ville.
> 
> v7: check pxp session while plane decrypt state computation. [Ville]
> removed pointless code. [Ville]
> 
> v8 (Daniele): update PXP check
> 
> v9: move decrypt check after icl_check_nv12_planes() when overlays
> have fb set (Juston)
> 
> v10 (Daniele): update PXP check again to match rework in earlier patches and
> don't consider protection valid if the object has not been used in an
> execbuf beforehand.

Reviewed-by: Rodrigo Vivi 

> 
> Cc: Bommu Krishnaiah 
> Cc: Huang Sean Z 
> Cc: Gaurav Kumar 
> Cc: Ville Syrjälä 
> Signed-off-by: Anshuman Gupta 
> Signed-off-by: Daniele Ceraolo Spurio 
> Signed-off-by: Juston Li 
> Reviewed-by: Rodrigo Vivi  #v8
> Reviewed-by: Uma Shankar  #v9
> ---
>  drivers/gpu/drm/i915/display/intel_display.c  | 26 +++
>  .../drm/i915/display/intel_display_types.h|  3 +++
>  .../drm/i915/display/skl_universal_plane.c| 15 ---
>  .../gpu/drm/i915/gem/i915_gem_execbuffer.c|  2 +-
>  drivers/gpu/drm/i915/i915_reg.h   |  1 +
>  drivers/gpu/drm/i915/pxp/intel_pxp.c  |  9 ---
>  drivers/gpu/drm/i915/pxp/intel_pxp.h  |  7 +++--
>  7 files changed, 54 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> b/drivers/gpu/drm/i915/display/intel_display.c
> index fe5ad599c218..f04d98fcea46 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -70,6 +70,8 @@
>  #include "gt/intel_rps.h"
>  #include "gt/gen8_ppgtt.h"
>  
> +#include "pxp/intel_pxp.h"
> +
>  #include "g4x_dp.h"
>  #include "g4x_hdmi.h"
>  #include "i915_drv.h"
> @@ -9148,13 +9150,23 @@ static int intel_bigjoiner_add_affected_planes(struct 
> intel_atomic_state *state)
>   return 0;
>  }
>  
> +static bool bo_has_valid_encryption(struct drm_i915_gem_object *obj)
> +{
> + struct drm_i915_private *i915 = to_i915(obj->base.dev);
> +
> + return intel_pxp_key_check(&i915->gt.pxp, obj, false) == 0;
> +}
> +
>  static int intel_atomic_check_planes(struct intel_atomic_state *state)
>  {
>   struct drm_i915_private *dev_priv = to_i915(state->base.dev);
>   struct intel_crtc_state *old_crtc_state, *new_crtc_state;
>   struct intel_plane_state *plane_state;
>   struct intel_plane *plane;
> + struct intel_plane_state *new_plane_state;
> + struct intel_plane_state *old_plane_state;
>   struct intel_crtc *crtc;
> + const struct drm_framebuffer *fb;
>   int i, ret;
>  
>   ret = icl_add_linked_planes(state);
> @@ -9202,6 +9214,16 @@ static int intel_atomic_check_planes(struct 
> intel_atomic_state *state)
>   return ret;
>   }
>  
> + for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
> + new_plane_state = intel_atomic_get_new_plane_state(state, 
> plane);
> + old_plane_state = intel_atomic_get_old_plane_state(state, 
> plane);
> + fb = new_plane_state->hw.fb;
> + if (fb)
> + new_plane_state->decrypt = 
> bo_has_valid_encryption(intel_fb_obj(fb));
> + else
> + new_plane_state->decrypt = old_plane_state->decrypt;
> + }
> +
>   return 0;
>  }
>  
> @@ -9488,6 +9510,10 @@ static int intel_atomic_check_async(struct 
> intel_atomic_state *state)
>   drm_dbg_kms(&i915->drm, "Color range cannot be changed 
> in async flip\n");
>   return -EINVAL;
>   }
> +
> + /* plane decryption is allow to change only in synchronous 
> flips */
> + if (old_plane_state->decrypt != new_plane_state->decrypt)
> + return -EINVAL;
>   }
>  
>   return 0;
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h 
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index c7bcf9183447..6d4ea1d5bf7b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -629,6 +629,9 @@ struct intel_plane_state {
>  
>   struct intel_fb_view view;
>  
> + /* Plane pxp decryption state */
> + bool decrypt;
> +
>   /* plane control register */
>   u32 ctl;
>  
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c 
> b/drivers/gpu/drm/i915/di

Re: [Intel-gfx] [PATCH v7 14/17] drm/i915/pxp: black pixels on pxp disabled

[Rodrigo Vivi]

On Fri, Aug 27, 2021 at 06:27:35PM -0700, Daniele Ceraolo Spurio wrote:
> From: Anshuman Gupta 
> 
> When protected sufaces has flipped and pxp session is disabled,
> display black pixels by using plane color CTM correction.
> 
> v2:
> - Display black pixels in async flip too.
> 
> v3:
> - Removed the black pixels logic for async flip. [Ville]
> - Used plane state to force black pixels. [Ville]
> 
> v4 (Daniele): update pxp_is_borked check.
> 
> v5: rebase on top of v9 plane decryption moving the decrypt check
> (Juston)
> 
> Cc: Ville Syrjälä 
> Cc: Gaurav Kumar 
> Cc: Shankar Uma 
> Signed-off-by: Anshuman Gupta 
> Signed-off-by: Daniele Ceraolo Spurio 
> Signed-off-by: Juston Li 
> Reviewed-by: Rodrigo Vivi  #v4

The end result looks identical to me, so my rv-b remains valid.

> Reviewed-by: Uma Shankar 
> ---
>  drivers/gpu/drm/i915/display/intel_display.c  | 12 -
>  .../drm/i915/display/intel_display_types.h|  3 ++
>  .../drm/i915/display/skl_universal_plane.c| 36 ++-
>  drivers/gpu/drm/i915/i915_reg.h   | 46 +++
>  4 files changed, 94 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> b/drivers/gpu/drm/i915/display/intel_display.c
> index f04d98fcea46..146c87440cc6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -9157,6 +9157,11 @@ static bool bo_has_valid_encryption(struct 
> drm_i915_gem_object *obj)
>   return intel_pxp_key_check(&i915->gt.pxp, obj, false) == 0;
>  }
>  
> +static bool pxp_is_borked(struct drm_i915_gem_object *obj)
> +{
> + return i915_gem_object_is_protected(obj) && 
> !bo_has_valid_encryption(obj);
> +}
> +
>  static int intel_atomic_check_planes(struct intel_atomic_state *state)
>  {
>   struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> @@ -9218,10 +9223,13 @@ static int intel_atomic_check_planes(struct 
> intel_atomic_state *state)
>   new_plane_state = intel_atomic_get_new_plane_state(state, 
> plane);
>   old_plane_state = intel_atomic_get_old_plane_state(state, 
> plane);
>   fb = new_plane_state->hw.fb;
> - if (fb)
> + if (fb) {
>   new_plane_state->decrypt = 
> bo_has_valid_encryption(intel_fb_obj(fb));
> - else
> + new_plane_state->force_black = 
> pxp_is_borked(intel_fb_obj(fb));
> + } else {
>   new_plane_state->decrypt = old_plane_state->decrypt;
> + new_plane_state->force_black = 
> old_plane_state->force_black;
> + }
>   }
>  
>   return 0;
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h 
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 6d4ea1d5bf7b..05d2e6676387 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -632,6 +632,9 @@ struct intel_plane_state {
>   /* Plane pxp decryption state */
>   bool decrypt;
>  
> + /* Plane state to display black pixels when pxp is borked */
> + bool force_black;
> +
>   /* plane control register */
>   u32 ctl;
>  
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c 
> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 55e3f093b951..c4adcb3e12b3 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -1002,6 +1002,33 @@ static u32 skl_surf_address(const struct 
> intel_plane_state *plane_state,
>   }
>  }
>  
> +static void intel_load_plane_csc_black(struct intel_plane *intel_plane)
> +{
> + struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
> + enum pipe pipe = intel_plane->pipe;
> + enum plane_id plane = intel_plane->id;
> + u16 postoff = 0;
> +
> + drm_dbg_kms(&dev_priv->drm, "plane color CTM to black  %s:%d\n",
> + intel_plane->base.name, plane);
> + intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 0), 0);
> + intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 1), 0);
> +
> + intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 2), 0);
> + intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 3), 0);
> +
> + intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 4), 0);
> + intel_de_write_fw(dev_priv, PLANE_CSC_COEFF(pipe, plane, 5), 0);
> +
> + intel_de_write_fw(dev_priv, PLANE_CSC_PREOFF(pipe, plane, 0), 0);
> + intel_de_write_fw(dev_priv, PLANE_CSC_PREOFF(pipe, plane, 1), 0);
> + intel_de_write_fw(dev_priv, PLANE_CSC_PREOFF(pipe, plane, 2), 0);
> +
> + intel_de_write_fw(dev_priv, PLANE_CSC_POSTOFF(pipe, plane, 0), postoff);
> + intel_de_write_fw(dev_priv, PLANE_CSC_POSTOFF(pipe, plane, 1), postoff);
> + intel_de_write_fw(dev_priv, PLANE_CSC_POSTOFF(pipe, plane, 2), postoff);
> +}
> +
>  static 

Re: [Intel-gfx] [PATCH v7 10/17] drm/i915/pxp: interfaces for using protected objects

[Rodrigo Vivi]

On Tue, Aug 31, 2021 at 03:01:51PM -0700, Daniele Ceraolo Spurio wrote:
> 
> 
> > > +}
> > > +
> > > +void intel_pxp_invalidate(struct intel_pxp *pxp)
> > > +{
> > > + struct drm_i915_private *i915 = pxp_to_gt(pxp)->i915;
> > > + struct i915_gem_context *ctx, *cn;
> > > +
> > > + /* ban all contexts marked as protected */
> > > + spin_lock_irq(&i915->gem.contexts.lock);
> > > + list_for_each_entry_safe(ctx, cn, &i915->gem.contexts.list, link) {
> > > + struct i915_gem_engines_iter it;
> > > + struct intel_context *ce;
> > > +
> > > + if (!kref_get_unless_zero(&ctx->ref))
> > > + continue;
> > > +
> > > + if (likely(!i915_gem_context_uses_protected_content(ctx))) {
> > > + i915_gem_context_put(ctx);
> > > + continue;
> > > + }
> > > +
> > > + spin_unlock_irq(&i915->gem.contexts.lock);
> > > +
> > > + /*
> > > +  * By the time we get here, the HW keys are already long gone,
> > > +  * so any batch using them that's already on the engines is very
> > > +  * likely a lost cause (and it has probably already hung the
> > > +  * engine). Therefore, we skip attempting to pull the running
> > > +  * context out of the HW and we prioritize bringing the session
> > > +  * back as soon as possible.
> > > +  * For each context we ban we increase the ctx->guilty_count, so
> > > +  * that userspace can see that all the intel contexts have been
> > > +  * banned (on a non-recoverable gem context, guilty intel
> > > +  * contexts are banned immediately on reset, so we report the
> > > +  * same way here).
> > hmm... but guilty specifically means that they indeed caused the GPU hang.
> > does the umd really need this indication? any other way of doing this?
> 
> The request from Daniel was to re-use the existing interface and AFAICT the
> guilty_count is the only one we have for this. The alternative would be to
> add a new flag (like I had in the previous version of this patch), but that
> was shot down already. Lionel can probably comment more on the UMD
> requirements for this since it was a request from the mesa side.

Daniel and Lionel, could you please comment here?
Are we really expanding the guilty from the hang meaning?
Is it really better than creating the new flag?

> 
> 
> > > +  */
> > > + for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it)
> > > + if (!intel_context_ban(ce, NULL))
> > > + atomic_inc(&ctx->guilty_count);
> > > + i915_gem_context_unlock_engines(ctx);
> > > +
> > > + /*
> > > +  * The context has been killed, no need to keep the wakeref.
> > > +  * This is safe from races because the only other place this
> > > +  * is touched is context_close and we're holding a ctx ref
> > > +  */
> > The comments make sense, but maybe we should avoid the optimization here,
> > but maybe we should avoid the optimization and just keep it locked?
> 
> The lock released above the comment and the one taken after the pm_put are
> different ones, so even if we don't release the wakeref here we still need
> to do the same locking steps. Or did you mean something different with
> keeping it locked?

oh, please ignore me here. I thought it was the same locking...

> 
> Thanks,
> Daniele
> 
> > 
> > > + if (ctx->pxp_wakeref) {
> > > + intel_runtime_pm_put(&i915->runtime_pm,
> > > +  ctx->pxp_wakeref);
> > > + ctx->pxp_wakeref = 0;
> > > + }
> > > +
> > > + spin_lock_irq(&i915->gem.contexts.lock);
> > > + list_safe_reset_next(ctx, cn, link);
> > > + i915_gem_context_put(ctx);
> > > + }
> > > + spin_unlock_irq(&i915->gem.contexts.lock);
> > > +}
> > > +
> > > diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h 
> > > b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> > > index 8f1e86caa53f..f942bdd2af0c 100644
> > > --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
> > > +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> > > @@ -9,6 +9,8 @@
> > >   #include "gt/intel_gt_types.h"
> > >   #include "intel_pxp_types.h"
> > > +struct drm_i915_gem_object;
> > > +
> > >   static inline struct intel_gt *pxp_to_gt(const struct intel_pxp *pxp)
> > >   {
> > >   return container_of(pxp, struct intel_gt, pxp);
> > > @@ -33,6 +35,10 @@ void intel_pxp_fini_hw(struct intel_pxp *pxp);
> > >   void intel_pxp_mark_termination_in_progress(struct intel_pxp *pxp);
> > >   int intel_pxp_wait_for_arb_start(struct intel_pxp *pxp);
> > > +
> > > +int intel_pxp_key_check(struct intel_pxp *pxp, struct 
> > > drm_i915_gem_object *obj);
> > > +
> > > +void intel_pxp_invalidate(struct intel_pxp *pxp);
> > >   #else
> > >   static inline void intel_pxp_init(struct intel_pxp *pxp)
> > >   {
> > > @@ -46,6 +52,12 @@ static inline int intel_pxp_wait_for_arb_start(s

Re: [Intel-gfx] [PATCH 5/5] drm/i915/dsi: Read/write proper brightness value via MIPI DCS command

[Jani Nikula]

On Wed, 01 Sep 2021, Lee Shawn C  wrote:
> Driver has to swap the endian before send brightness level value
> to tcon.
>
> v2: Use __be16 instead of u16 to fix sparse warning.
> v3: Send one or two bytes brightness value depend on the precision.
>
> Reported-by: kernel test robot 
> Cc: Ville Syrjala 
> Cc: Jani Nikula 
> Cc: Vandita Kulkarni 
> Cc: Cooper Chiou 
> Cc: William Tseng 
> Signed-off-by: Lee Shawn C 
> ---
>  .../drm/i915/display/intel_dsi_dcs_backlight.c| 15 +--
>  1 file changed, 9 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c 
> b/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c
> index 21ab9e1acb57..722411b5cb21 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c
> @@ -47,33 +47,36 @@ static u32 dcs_get_backlight(struct intel_connector 
> *connector, enum pipe unused
>  {
>   struct intel_encoder *encoder = intel_attached_encoder(connector);
>   struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> + struct intel_panel *panel = &connector->panel;
>   struct mipi_dsi_device *dsi_device;
> - u8 data = 0;
> + u8 data[2] = {0, 0};

u8 data[2] = {};

>   enum port port;

size_t len = panel->backlight.max > U8_MAX ? 2 : 1;

>  
>   /* FIXME: Need to take care of 16 bit brightness level */
>   for_each_dsi_port(port, intel_dsi->dcs_backlight_ports) {
>   dsi_device = intel_dsi->dsi_hosts[port]->device;
>   mipi_dsi_dcs_read(dsi_device, MIPI_DCS_GET_DISPLAY_BRIGHTNESS,
> -   &data, sizeof(data));
> +   &data,
> +   (panel->backlight.max >> 8) ? sizeof(data) : 
> 1);
>   break;
>   }
>  
> - return data;
> + return ((data[1] << 8) | data[0]);

Unnecessary braces around the whole thing.

>  }
>  
>  static void dcs_set_backlight(const struct drm_connector_state *conn_state, 
> u32 level)
>  {
>   struct intel_dsi *intel_dsi = 
> enc_to_intel_dsi(to_intel_encoder(conn_state->best_encoder));
> + struct intel_panel *panel = 
> &to_intel_connector(conn_state->connector)->panel;
>   struct mipi_dsi_device *dsi_device;
> - u8 data = level;
> + __be16 data = cpu_to_be16(level);

I think it's confusing to use __be16 in set and u8 data[2] in get. Let's
just use u8 data[2] in both. Especially because this one will always
write 0 for len == 1 as it's big-endian data!

You may have to do something like to keep it clear:

size_t len = panel->backlight.max > U8_MAX ? 2 : 1;

if (len == 1) {
data[0] = level;
} else {
data[0] = level >> 8;
data[1] = level;
}

>   enum port port;
>  
> - /* FIXME: Need to take care of 16 bit brightness level */
>   for_each_dsi_port(port, intel_dsi->dcs_backlight_ports) {
>   dsi_device = intel_dsi->dsi_hosts[port]->device;
>   mipi_dsi_dcs_write(dsi_device, MIPI_DCS_SET_DISPLAY_BRIGHTNESS,
> -&data, sizeof(data));
> +&data,
> +(panel->backlight.max >> 8) ? sizeof(data) : 
> 1);
>   }
>  }

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] [PATCH] drm/i915: Flush buffer pools on driver remove

[Janusz Krzysztofik]

In preparation for clean driver release, attempts to drain work queues
and release freed objects are taken at driver remove time.  However, GT
buffer pools are now not flushed before the driver release phase.
Since unused objects may stay there for up to one second, some may
survive until driver release is attempted.  That can potentially
explain sporadic then hardly reproducible issues observed at driver
release time, like non-zero shrink counter or outstanding address space
areas.

Flush buffer pools on GT remove as a fix.  On driver release, don't push
the pools again, just assert that the flush was called and nothing added
more in between.

Signed-off-by: Janusz Krzysztofik 
Cc: Chris Wilson 
---
 drivers/gpu/drm/i915/gt/intel_gt.c | 2 ++
 drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.c | 2 --
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c 
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 62d40c986642..8f322a4ecd87 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -737,6 +737,8 @@ void intel_gt_driver_remove(struct intel_gt *gt)
intel_uc_driver_remove(>->uc);
 
intel_engines_release(gt);
+
+   intel_gt_flush_buffer_pool(gt);
 }
 
 void intel_gt_driver_unregister(struct intel_gt *gt)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.c 
b/drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.c
index aa0a59c5b614..acc49c56a9f3 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.c
@@ -245,8 +245,6 @@ void intel_gt_fini_buffer_pool(struct intel_gt *gt)
struct intel_gt_buffer_pool *pool = >->buffer_pool;
int n;
 
-   intel_gt_flush_buffer_pool(gt);
-
for (n = 0; n < ARRAY_SIZE(pool->cache_list); n++)
GEM_BUG_ON(!list_empty(&pool->cache_list[n]));
 }
-- 
2.25.1

[Intel-gfx] [PATCH] drm/i915: Mark GPU wedging on driver unregister unrecoverable

[Janusz Krzysztofik]

GPU wedged flag now set on driver unregister to prevent from further
using the GPU can be then cleared unintentionally when calling
__intel_gt_unset_wedged() still before the flag is finally marked
unrecoverable.  We need to have it marked unrecoverable earlier.
Implement that by replacing a call to intel_gt_set_wedged() in
intel_gt_driver_unregister() with intel_gt_set_wedged_on_fini().

With the above in place, intel_gt_set_wedged_on_fini() is now called
twice on driver remove, second time from __intel_gt_disable().  This
seems harmless, while dropping intel_gt_set_wedged_on_fini() from
__intel_gt_disable() proved to break some driver probe error unwind
paths as well as mock selftest exit path.

Signed-off-by: Janusz Krzysztofik 
Cc: Michał Winiarski 
---
 drivers/gpu/drm/i915/gt/intel_gt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c 
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 62d40c986642..173b53cb2b47 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -750,7 +750,7 @@ void intel_gt_driver_unregister(struct intel_gt *gt)
 * all in-flight requests so that we can quickly unbind the active
 * resources.
 */
-   intel_gt_set_wedged(gt);
+   intel_gt_set_wedged_on_fini(gt);
 
/* Scrub all HW state upon release */
with_intel_runtime_pm(gt->uncore->rpm, wakeref)
-- 
2.25.1

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dp: fix DG2 max source rate check

[Patchwork]

== Series Details ==

Series: drm/i915/dp: fix DG2 max source rate check
URL   : https://patchwork.freedesktop.org/series/94241/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_10544 -> Patchwork_20934


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_20934 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_20934, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20934/index.html

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_20934:

### IGT changes ###

 Possible regressions 

  * igt@kms_busy@basic:
- fi-rkl-11600:   NOTRUN -> [SKIP][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20934/fi-rkl-11600/igt@kms_b...@basic.html

  
Known issues


  Here are the changes found in Patchwork_20934 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_suspend@basic-s0:
- fi-cfl-8109u:   [PASS][2] -> [DMESG-WARN][3] ([i915#203] / [i915#262] 
/ [i915#295]) +1 similar issue
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/fi-cfl-8109u/igt@gem_exec_susp...@basic-s0.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20934/fi-cfl-8109u/igt@gem_exec_susp...@basic-s0.html

  * igt@i915_selftest@live@execlists:
- fi-bsw-nick:[PASS][4] -> [INCOMPLETE][5] ([i915#2940])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20934/fi-bsw-nick/igt@i915_selftest@l...@execlists.html

  * igt@i915_selftest@live@hangcheck:
- fi-snb-2600:NOTRUN -> [INCOMPLETE][6] ([i915#3921])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20934/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-snb-2600:NOTRUN -> [SKIP][7] ([fdo#109271]) +19 similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20934/fi-snb-2600/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_chamelium@hdmi-crc-fast:
- fi-snb-2600:NOTRUN -> [SKIP][8] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20934/fi-snb-2600/igt@kms_chamel...@hdmi-crc-fast.html

  * igt@runner@aborted:
- fi-bsw-nick:NOTRUN -> [FAIL][9] ([fdo#109271] / [i915#1436] / 
[i915#2722] / [i915#3428])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20934/fi-bsw-nick/igt@run...@aborted.html

  
 Possible fixes 

  * igt@i915_pm_rpm@module-reload:
- fi-cfl-8109u:   [FAIL][10] ([i915#4054]) -> [PASS][11]
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/fi-cfl-8109u/igt@i915_pm_...@module-reload.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20934/fi-cfl-8109u/igt@i915_pm_...@module-reload.html

  * igt@i915_selftest@live@execlists:
- fi-cfl-8109u:   [DMESG-WARN][12] ([i915#203]) -> [PASS][13] +4 
similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/fi-cfl-8109u/igt@i915_selftest@l...@execlists.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20934/fi-cfl-8109u/igt@i915_selftest@l...@execlists.html

  * igt@i915_selftest@live@hangcheck:
- {fi-hsw-gt1}:   [DMESG-WARN][14] ([i915#3303]) -> [PASS][15]
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10544/fi-hsw-gt1/igt@i915_selftest@l...@hangcheck.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20934/fi-hsw-gt1/igt@i915_selftest@l...@hangcheck.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#203]: https://gitlab.freedesktop.org/drm/intel/issues/203
  [i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262
  [i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
  [i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
  [i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295
  [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
  [i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428
  [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
  [i915#4054]: https://gitlab.freedesktop.org/drm/intel/issues/4054


Participating hosts (42 -> 35)
--

  Additional (1): f

Re: [Intel-gfx] [PATCH V4] drm/i915/gen11: Disable cursor clock gating in HDR mode

[Ville Syrjälä]

On Tue, Jun 22, 2021 at 03:04:24PM +0530, Tejas Upadhyay wrote:
> Display underrun in HDR mode when cursor is enabled.
> RTL fix will be implemented CLKGATE_DIS_PSL_A bit 28-46520h.
> As per W/A 1604331009, Disable cursor clock gating in HDR mode.
> 
> Bspec : 33451
> 
> Changes since V3:
>   - Disable WA when not in HDR mode or cursor plane not active - Ville
>   - Extract required args from crtc_state - Ville
>   - Create HDR mode API using bdw_set_pipemisc ref - Ville
>   - Tested with HDR video as well full setmode, WA applies and disables
> Changes since V2:
> - Made it general gen11 WA
> - Removed WA needed check
> - Added cursor plane active check
> - Once WA enable, software will not disable
> Changes since V1:
> - Modified way CLKGATE_DIS_PSL bit 28 was modified
> 
> Cc: Souza Jose 
> Signed-off-by: Tejas Upadhyay 
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 27 
>  drivers/gpu/drm/i915/i915_reg.h  |  5 
>  2 files changed, 32 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 6be1b31af07b..e1ea03b918df 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -358,6 +358,13 @@ static void intel_update_czclk(struct drm_i915_private 
> *dev_priv)
>   dev_priv->czclk_freq);
>  }
>  
> +static bool
> +is_hdr_mode(const struct intel_crtc_state *crtc_state)
> +{
> + return (crtc_state->active_planes & ~(icl_hdr_plane_mask() |
> + BIT(PLANE_CURSOR))) == 0;
> +}

Please use this in bdw_set_pipemisc() as well. This could be
a separate prep patch actually.

> +
>  /* WA Display #0827: Gen9:all */
>  static void
>  skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable)
> @@ -383,6 +390,23 @@ icl_wa_scalerclkgating(struct drm_i915_private 
> *dev_priv, enum pipe pipe,
>  intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & 
> ~DPFR_GATING_DIS);
>  }
>  
> +/* Wa_1604331009:icl,jsl,ehl */
> + static void
> +icl_wa_cursorclkgating(const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +
> + if (is_hdr_mode(crtc_state) &&
> + crtc_state->active_planes & BIT(PLANE_CURSOR) &&
> + IS_GEN(dev_priv, 11))
> + intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(crtc->pipe),
> +  CURSOR_GATING_DIS, CURSOR_GATING_DIS);
> + else
> + intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(crtc->pipe),
> +  CURSOR_GATING_DIS, 0);
> +}
> +
>  static bool
>  is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state)
>  {
> @@ -2939,6 +2963,9 @@ static void intel_pre_plane_update(struct 
> intel_atomic_state *state,
>   needs_scalerclk_wa(new_crtc_state))
>   icl_wa_scalerclkgating(dev_priv, pipe, true);
>  
> + /* Wa_1604331009:icl,jsl,ehl */
> + icl_wa_cursorclkgating(new_crtc_state);

This looks a bit wrong. We shouldn't turn the clock gating back on
until after HDR mode has been disabled.

So please model this after skl_wa_827() and icl_wa_scalerclkgating()
so that a) the ordering is correct, and b) the code between all three
w/as looks consistent.

> +
>   /*
>* Vblank time updates from the shadow to live plane control register
>* are blocked if the memory self-refresh mode is active at that
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c857fafb8a30..703d708c773e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4235,6 +4235,11 @@ enum {
>  #define INF_UNIT_LEVEL_CLKGATE   _MMIO(0x9560)
>  #define   CGPSF_CLKGATE_DIS  (1 << 3)
>  
> +/*
> + * GEN11 clock gating regs
> + */
> +#define   CURSOR_GATING_DISBIT(28)

This looks misplaced. It should be next to the other bits of whatever
register this is. Also pls use REG_BIT() instead of BIT().

> +
>  /*
>   * Display engine regs
>   */
> -- 
> 2.31.1
> 
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gem: Fix the mman selftest (rev2)

[Kattamanchi, JaswanthX]

Hi Thomas,

Re reported

Patch : https://patchwork.freedesktop.org/series/94062/

Regards,
Jaswanth Kattamanchi

From: Thomas Hellström 
Sent: Wednesday, September 1, 2021 3:04 PM
To: intel-gfx@lists.freedesktop.org; Vudum, Lakshminarayana 
; Kattamanchi, JaswanthX 

Subject: Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gem: Fix the mman 
selftest (rev2)


+ jaswanthx.kattaman...@intel.com
On 9/1/21 10:33 AM, Thomas Hellström wrote:


On 8/31/21 8:51 PM, Patchwork wrote:
Patch Details
Series:
drm/i915/gem: Fix the mman selftest (rev2)
URL:
https://patchwork.freedesktop.org/series/94062/
State:
failure
Details:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20928/index.html
CI Bug Log - changes from CI_DRM_10539_full -> Patchwork_20928_full
Summary

FAILURE

Serious unknown changes coming with Patchwork_20928_full absolutely need to be
verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20928_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.

Possible new issues

Here are the unknown changes that may have been introduced in 
Patchwork_20928_full:

IGT changes
Possible regressions

  *   igt@sysfs_heartbeat_interval@mixed@vcs0:

 *   shard-skl: 
PASS
 -> 
WARN


Lakshmi, this failure is unrelated.

Thanks,

Thomas

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gem: Fix the mman selftest (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/gem: Fix the mman selftest (rev2)
URL   : https://patchwork.freedesktop.org/series/94062/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10539_full -> Patchwork_20928_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_20928_full:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_pm_rps@reset:
- {shard-rkl}:NOTRUN -> [FAIL][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20928/shard-rkl-2/igt@i915_pm_...@reset.html

  * igt@kms_cursor_crc@pipe-c-cursor-max-size-random:
- {shard-rkl}:[SKIP][2] ([fdo#112022]) -> [SKIP][3] +39 similar 
issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10539/shard-rkl-5/igt@kms_cursor_...@pipe-c-cursor-max-size-random.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20928/shard-rkl-1/igt@kms_cursor_...@pipe-c-cursor-max-size-random.html

  * igt@kms_cursor_legacy@pipe-c-forked-bo:
- {shard-rkl}:[PASS][4] -> [SKIP][5] +3 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10539/shard-rkl-1/igt@kms_cursor_leg...@pipe-c-forked-bo.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20928/shard-rkl-1/igt@kms_cursor_leg...@pipe-c-forked-bo.html

  * igt@kms_cursor_legacy@pipe-d-torture-bo:
- {shard-rkl}:[SKIP][6] ([i915#533]) -> [SKIP][7] +3 similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10539/shard-rkl-5/igt@kms_cursor_leg...@pipe-d-torture-bo.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20928/shard-rkl-1/igt@kms_cursor_leg...@pipe-d-torture-bo.html

  * igt@kms_pipe_crc_basic@read-crc-pipe-c:
- {shard-rkl}:[SKIP][8] ([i915#1849]) -> [SKIP][9] +19 similar 
issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10539/shard-rkl-1/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20928/shard-rkl-5/igt@kms_pipe_crc_ba...@read-crc-pipe-c.html

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
- {shard-rkl}:NOTRUN -> [SKIP][10] +4 similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20928/shard-rkl-2/igt@kms_plane_alpha_bl...@pipe-c-constant-alpha-max.html

  * igt@kms_plane_multiple@atomic-pipe-c-tiling-none:
- {shard-rkl}:[SKIP][11] ([i915#3558]) -> [SKIP][12] +1 similar 
issue
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10539/shard-rkl-1/igt@kms_plane_multi...@atomic-pipe-c-tiling-none.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20928/shard-rkl-1/igt@kms_plane_multi...@atomic-pipe-c-tiling-none.html

  * igt@kms_plane_multiple@atomic-pipe-c-tiling-yf:
- {shard-rkl}:[SKIP][13] ([i915#1849] / [i915#3558]) -> [SKIP][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10539/shard-rkl-2/igt@kms_plane_multi...@atomic-pipe-c-tiling-yf.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20928/shard-rkl-5/igt@kms_plane_multi...@atomic-pipe-c-tiling-yf.html

  * igt@kms_tv_load_detect@load-detect:
- {shard-rkl}:[SKIP][15] ([fdo#109309]) -> [INCOMPLETE][16]
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10539/shard-rkl-1/igt@kms_tv_load_det...@load-detect.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20928/shard-rkl-5/igt@kms_tv_load_det...@load-detect.html

  
Known issues


  Here are the changes found in Patchwork_20928_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_create@create-massive:
- shard-snb:  NOTRUN -> [DMESG-WARN][17] ([i915#3002]) +1 similar 
issue
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20928/shard-snb6/igt@gem_cre...@create-massive.html
- shard-kbl:  NOTRUN -> [DMESG-WARN][18] ([i915#3002])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20928/shard-kbl3/igt@gem_cre...@create-massive.html

  * igt@gem_ctx_isolation@preservation-s3@rcs0:
- shard-apl:  [PASS][19] -> [DMESG-WARN][20] ([i915#180])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10539/shard-apl2/igt@gem_ctx_isolation@preservation...@rcs0.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20928/shard-apl2/igt@gem_ctx_isolation@preservation...@rcs0.html

  * igt@gem_ctx_isolation@preservation-s3@vcs0:
- shard-kbl:  NOTRUN -> [DMESG-WARN][21] ([i915#180]) +3 similar 
issues
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20928/shard-kbl7/igt@gem_ctx_isolation@preservation...@vcs0.html

  * igt@gem_ctx_persistence@legacy-engines-hostile-preempt:
- shard-snb:  NOTRUN -> [SK

Re: [Intel-gfx] [PATCH v3 1/2] drm/i915/opregion: add support for mailbox #5 EDID

[Anisse Astier]

Hi,

On Tue, Aug 31, 2021 at 11:30 AM Jani Nikula  wrote:
>
> On Tue, 17 Aug 2021, Anisse Astier  wrote:
> > The ACPI OpRegion Mailbox #5 ASLE extension may contain an EDID to be
> > used for the embedded display. Add support for using it via by adding
> > the EDID to the list of available modes on the connector, and use it for
> > eDP when available.
> >
> > If a panel's EDID is broken, there may be an override EDID set in the
> > ACPI OpRegion mailbox #5. Use it if available.
> >
> > Fixes the GPD Win Max laptop display, which seems to only use this
> > mechanism to provide a proper EDID for its eDP screen. It would have
> > been better to provide the EDID through the ACPI _DDC method instead, to
> > have a more generic solution, but it seems the designers of this system
> > did not consider it, and shipped the firmware without it.
>
> The question is whether the opregion EDID should be used for override or
> fallback. The patch at hand is kind of neither, it just unconditionally
> adds the modes from the opregion EDID to the connector. For your
> display, they apparently end up also being the only mode(s), with one of
> them being used as the fixed mode. (Otherwise the orientation quirk
> wouldn't work.)

Yes, I agree it should be a fallback, at least for this hardware.

>
> What does drm_get_edid() return for you? Maybe we should do something
> like this instead:
>
> mutex_lock(&dev->mode_config.mutex);
> edid = drm_get_edid(connector, &intel_dp->aux.ddc);
> +   if (!edid)
> +   edid = intel_opregion_get_edid(intel_connector);
> if (edid) {
> if (drm_add_edid_modes(connector, edid)) {
> drm_connector_update_edid_property(connector, edid);

Yes, I just tried this, it works well since drm_get_edid() does not
return an EDID.

>
> This way we'll actually use all the other bits in the EDID, not just the
> modes. And if it needs to become override rather than fallback, the
> solution is:
>
> mutex_lock(&dev->mode_config.mutex);
> -   edid = drm_get_edid(connector, &intel_dp->aux.ddc);
> +   edid = intel_opregion_get_edid(intel_connector);
> +   if (!edid)
> +   edid = drm_get_edid(connector, &intel_dp->aux.ddc);
> if (edid) {
> if (drm_add_edid_modes(connector, edid)) {
> drm_connector_update_edid_property(connector, edid);
>
> In any case, I think it's just plain wrong to use both the display and
> opregion EDIDs at the same time. It's probably all around safer to start
> with fallback.

It will be in the next iteration.

>
> Please find some further comments inline.
>
> > Based on original patch series by: Jani Nikula 
> > https://patchwork.kernel.org/project/intel-gfx/patch/20200828061941.17051-1-jani.nik...@intel.com/
> >
> > Changes since Jani Nikula's series:
> >  - EDID is copied and validated with drm_edid_is_valid
> >  - Mode is now added via drm_add_edid_modes instead of using override
> >mechanism
> >  - squashed the two patches
> >
> > Cc: Jani Nikula 
> > Cc: Uma Shankar 
> > Cc: Ville Syrjälä 
> > Signed-off-by: Anisse Astier 
> > ---
> >  drivers/gpu/drm/i915/display/intel_dp.c   |  3 +
> >  drivers/gpu/drm/i915/display/intel_opregion.c | 69 ++-
> >  drivers/gpu/drm/i915/display/intel_opregion.h |  8 +++
> >  3 files changed, 79 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 75d4ebc66941..f9254c0df1a2 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -5183,6 +5183,9 @@ static bool intel_edp_init_connector(struct intel_dp 
> > *intel_dp,
> >   goto out_vdd_off;
> >   }
> >
> > + /* Set up override EDID, if any, from ACPI OpRegion */
> > + intel_opregion_edid_probe(intel_connector);
> > +
> >   mutex_lock(&dev->mode_config.mutex);
> >   edid = drm_get_edid(connector, &intel_dp->aux.ddc);
> >   if (edid) {
> > diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c 
> > b/drivers/gpu/drm/i915/display/intel_opregion.c
> > index 3855fba70980..b1b87ed758ba 100644
> > --- a/drivers/gpu/drm/i915/display/intel_opregion.c
> > +++ b/drivers/gpu/drm/i915/display/intel_opregion.c
> > @@ -196,6 +196,8 @@ struct opregion_asle_ext {
> >  #define ASLE_IUER_WINDOWS_BTN(1 << 1)
> >  #define ASLE_IUER_POWER_BTN  (1 << 0)
> >
> > +#define ASLE_PHED_EDID_VALID_MASK0x3
> > +
> >  /* Software System Control Interrupt (SWSCI) */
> >  #define SWSCI_SCIC_INDICATOR (1 << 0)
> >  #define SWSCI_SCIC_MAIN_FUNCTION_SHIFT   1
> > @@ -909,8 +911,10 @@ int intel_opregion_setup(struct drm_i915_private 
> > *dev_priv)
> >   opregion->asle->ardy = ASLE_ARDY_NOT_READY;
> >   }
> >
> > - if (mboxes & MBOX_ASLE_EXT)
> > + if (mboxes & MBOX_ASLE_EXT) {
> >   drm_dbg(&dev_priv->drm

[Intel-gfx] ✓ Fi.CI.IGT: success for DSI driver improvement

[Patchwork]

== Series Details ==

Series: DSI driver improvement
URL   : https://patchwork.freedesktop.org/series/94237/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10542_full -> Patchwork_20933_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Known issues


  Here are the changes found in Patchwork_20933_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_ctx_persistence@legacy-engines-mixed-process:
- shard-snb:  NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#1099]) +3 
similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20933/shard-snb2/igt@gem_ctx_persiste...@legacy-engines-mixed-process.html

  * igt@gem_eio@unwedge-stress:
- shard-snb:  NOTRUN -> [FAIL][2] ([i915#3354])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20933/shard-snb2/igt@gem_...@unwedge-stress.html

  * igt@gem_exec_capture@pi@rcs0:
- shard-skl:  [PASS][3] -> [INCOMPLETE][4] ([i915#2369])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10542/shard-skl5/igt@gem_exec_capture@p...@rcs0.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20933/shard-skl7/igt@gem_exec_capture@p...@rcs0.html

  * igt@gem_exec_fair@basic-deadline:
- shard-kbl:  [PASS][5] -> [FAIL][6] ([i915#2846])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10542/shard-kbl7/igt@gem_exec_f...@basic-deadline.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20933/shard-kbl6/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
- shard-apl:  [PASS][7] -> [SKIP][8] ([fdo#109271])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10542/shard-apl6/igt@gem_exec_fair@basic-none-sh...@rcs0.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20933/shard-apl3/igt@gem_exec_fair@basic-none-sh...@rcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk:  [PASS][9] -> [FAIL][10] ([i915#2842])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10542/shard-glk2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20933/shard-glk9/igt@gem_exec_fair@basic-pace-sh...@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs0:
- shard-kbl:  [PASS][11] -> [FAIL][12] ([i915#2842])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10542/shard-kbl6/igt@gem_exec_fair@basic-p...@vcs0.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20933/shard-kbl1/igt@gem_exec_fair@basic-p...@vcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][13] -> [FAIL][14] ([i915#2849])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10542/shard-iclb6/igt@gem_exec_fair@basic-throt...@rcs0.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20933/shard-iclb8/igt@gem_exec_fair@basic-throt...@rcs0.html

  * igt@gem_exec_flush@basic-batch-kernel-default-cmd:
- shard-tglb: NOTRUN -> [SKIP][15] ([fdo#109313])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20933/shard-tglb3/igt@gem_exec_fl...@basic-batch-kernel-default-cmd.html

  * igt@gem_pread@exhaustion:
- shard-snb:  NOTRUN -> [WARN][16] ([i915#2658])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20933/shard-snb7/igt@gem_pr...@exhaustion.html

  * igt@gem_userptr_blits@input-checking:
- shard-apl:  NOTRUN -> [DMESG-WARN][17] ([i915#3002])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20933/shard-apl7/igt@gem_userptr_bl...@input-checking.html
- shard-snb:  NOTRUN -> [DMESG-WARN][18] ([i915#3002])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20933/shard-snb7/igt@gem_userptr_bl...@input-checking.html

  * igt@gem_userptr_blits@vma-merge:
- shard-snb:  NOTRUN -> [FAIL][19] ([i915#2724])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20933/shard-snb7/igt@gem_userptr_bl...@vma-merge.html

  * igt@gen9_exec_parse@bb-start-far:
- shard-iclb: NOTRUN -> [SKIP][20] ([i915#2856])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20933/shard-iclb4/igt@gen9_exec_pa...@bb-start-far.html
- shard-tglb: NOTRUN -> [SKIP][21] ([i915#2856])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20933/shard-tglb3/igt@gen9_exec_pa...@bb-start-far.html

  * igt@i915_pm_rpm@modeset-non-lpsp:
- shard-tglb: NOTRUN -> [SKIP][22] ([fdo#111644] / [i915#1397] / 
[i915#2411])
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20933/shard-tglb2/igt@i915_pm_...@modeset-non-lpsp.html

  * igt@i915_suspend@sysfs-reader:
- shard-skl:  [PASS][23] -> [INCOMPLETE][24] ([i915#198]) +1 
similar issue
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10542/shard-skl10/igt@i915_susp...@sysfs-reader.html
   [24]: 
https://intel-gfx

Re: [Intel-gfx] [PATCH] drm/i915/dp: fix DG2 max source rate check

[Imre Deak]

On Wed, Sep 01, 2021 at 02:28:15PM +0300, Jani Nikula wrote:
> Accidentally dropped the else in a rebase fail, causing the DG2 max rate
> to be overwritten later in the if ladder.
> 
> Fixes: e752d1f9c14a ("drm/i915/dg2: add DG2 UHBR source rates")
> Cc: Manasi Navare 
> Cc: Ville Syrjälä 
> Signed-off-by: Jani Nikula 

Reviewed-by: Imre Deak 

> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 4f2fd33529ca..81b7097c6ff1 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -345,7 +345,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
>   size = ARRAY_SIZE(icl_rates);
>   if (IS_DG2(dev_priv))
>   max_rate = dg2_max_source_rate(intel_dp);
> - if (IS_JSL_EHL(dev_priv))
> + else if (IS_JSL_EHL(dev_priv))
>   max_rate = ehl_max_source_rate(intel_dp);
>   else
>   max_rate = icl_max_source_rate(intel_dp);
> -- 
> 2.30.2
> 

[Intel-gfx] [PATCH] drm/i915/dp: fix DG2 max source rate check

[Jani Nikula]

Accidentally dropped the else in a rebase fail, causing the DG2 max rate
to be overwritten later in the if ladder.

Fixes: e752d1f9c14a ("drm/i915/dg2: add DG2 UHBR source rates")
Cc: Manasi Navare 
Cc: Ville Syrjälä 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 4f2fd33529ca..81b7097c6ff1 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -345,7 +345,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
size = ARRAY_SIZE(icl_rates);
if (IS_DG2(dev_priv))
max_rate = dg2_max_source_rate(intel_dp);
-   if (IS_JSL_EHL(dev_priv))
+   else if (IS_JSL_EHL(dev_priv))
max_rate = ehl_max_source_rate(intel_dp);
else
max_rate = icl_max_source_rate(intel_dp);
-- 
2.30.2

Re: [Intel-gfx] [PATCH 0/5] Fix in max source calculation for dp/edp

[Jani Nikula]

On Thu, 12 Aug 2021, Animesh Manna  wrote:
> HBR3 support for display gen11+ platform is depends upon some
> conditions which are mentioned below.

The series no longer applies, please rebase and resend.

BR,
Jani.

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 7/8] drm/i915/gem: Correct the locking and pin pattern for dma-buf (v8)

[Intel]

Hi, Jason,

A quick question below:

On 7/23/21 7:21 PM, Jason Ekstrand wrote:

From: Thomas Hellström 

If our exported dma-bufs are imported by another instance of our driver,
that instance will typically have the imported dma-bufs locked during
dma_buf_map_attachment(). But the exporter also locks the same reservation
object in the map_dma_buf() callback, which leads to recursive locking.

So taking the lock inside _pin_pages_unlocked() is incorrect.

Additionally, the current pinning code path is contrary to the defined
way that pinning should occur.

Remove the explicit pin/unpin from the map/umap functions and move them
to the attach/detach allowing correct locking to occur, and to match
the static dma-buf drm_prime pattern.

Add a live selftest to exercise both dynamic and non-dynamic
exports.

v2:
- Extend the selftest with a fake dynamic importer.
- Provide real pin and unpin callbacks to not abuse the interface.
v3: (ruhl)
- Remove the dynamic export support and move the pinning into the
   attach/detach path.
v4: (ruhl)
- Put pages does not need to assert on the dma-resv
v5: (jason)
- Lock around dma_buf_unmap_attachment() when emulating a dynamic
   importer in the subtests.
- Use pin_pages_unlocked
v6: (jason)
- Use dma_buf_attach instead of dma_buf_attach_dynamic in the selftests


Why did we drop the dynamic importer from the selftests? Shouldn't we 
try to ensure compatibility with dynamic importers?


/Thomas

[Intel-gfx] ✓ Fi.CI.BAT: success for DSI driver improvement

[Patchwork]

== Series Details ==

Series: DSI driver improvement
URL   : https://patchwork.freedesktop.org/series/94237/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10542 -> Patchwork_20933


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20933/index.html

Known issues


  Here are the changes found in Patchwork_20933 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@amdgpu/amd_basic@cs-gfx:
- fi-kbl-soraka:  NOTRUN -> [SKIP][1] ([fdo#109271]) +16 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20933/fi-kbl-soraka/igt@amdgpu/amd_ba...@cs-gfx.html

  * igt@amdgpu/amd_basic@query-info:
- fi-tgl-1115g4:  NOTRUN -> [SKIP][2] ([fdo#109315])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20933/fi-tgl-1115g4/igt@amdgpu/amd_ba...@query-info.html

  * igt@amdgpu/amd_cs_nop@nop-gfx0:
- fi-tgl-1115g4:  NOTRUN -> [SKIP][3] ([fdo#109315] / [i915#2575]) +16 
similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20933/fi-tgl-1115g4/igt@amdgpu/amd_cs_...@nop-gfx0.html

  * igt@gem_huc_copy@huc-copy:
- fi-tgl-1115g4:  NOTRUN -> [SKIP][4] ([i915#2190])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20933/fi-tgl-1115g4/igt@gem_huc_c...@huc-copy.html

  * igt@i915_pm_backlight@basic-brightness:
- fi-tgl-1115g4:  NOTRUN -> [SKIP][5] ([i915#1155])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20933/fi-tgl-1115g4/igt@i915_pm_backli...@basic-brightness.html

  * igt@kms_chamelium@common-hpd-after-suspend:
- fi-tgl-1115g4:  NOTRUN -> [SKIP][6] ([fdo#111827]) +8 similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20933/fi-tgl-1115g4/igt@kms_chamel...@common-hpd-after-suspend.html

  * igt@kms_force_connector_basic@force-load-detect:
- fi-tgl-1115g4:  NOTRUN -> [SKIP][7] ([fdo#109285])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20933/fi-tgl-1115g4/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_psr@primary_mmap_gtt:
- fi-tgl-1115g4:  NOTRUN -> [SKIP][8] ([i915#1072]) +3 similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20933/fi-tgl-1115g4/igt@kms_psr@primary_mmap_gtt.html

  * igt@prime_vgem@basic-userptr:
- fi-tgl-1115g4:  NOTRUN -> [SKIP][9] ([i915#3301])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20933/fi-tgl-1115g4/igt@prime_v...@basic-userptr.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
  [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
  [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303


Participating hosts (42 -> 35)
--

  Additional (1): fi-tgl-1115g4 
  Missing(8): fi-ilk-m540 bat-adls-5 bat-dg1-6 bat-dg1-5 fi-bsw-cyan 
fi-ctg-p8600 fi-bdw-samus bat-jsl-1 


Build changes
-

  * Linux: CI_DRM_10542 -> Patchwork_20933

  CI-20190529: 20190529
  CI_DRM_10542: 1f267035b78adb2a1b211809bc52f6009f024669 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6193: 080869f804cb86b25a38889e5ce9a870571cd8c4 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_20933: 55fa495029cf15db7a7f1c61b984d96278d1d7d7 @ 
git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

55fa495029cf drm/i915/dsi: Read/write proper brightness value via MIPI DCS 
command
acabf38d37d0 drm/i915/dsi: Retrieve max brightness level from VBT
1d4c2235dac3 drm/i915: Get proper min cdclk if vDSC enabled
0668b3ff4d4e drm/i915/dsi: refine send MIPI DCS command sequence
446bf065040f drm/i915/dsi: wait for header and payload credit available

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20933/index.html

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for DSI driver improvement

[Patchwork]

== Series Details ==

Series: DSI driver improvement
URL   : https://patchwork.freedesktop.org/series/94237/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gem/i915_gem_context.c:1374:34:expected struct 
i915_address_space *vm
+drivers/gpu/drm/i915/gem/i915_gem_context.c:1374:34:got struct 
i915_address_space [noderef] __rcu *vm
+drivers/gpu/drm/i915/gem/i915_gem_context.c:1374:34: warning: incorrect type 
in argument 1 (different address spaces)
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25:expected struct 
i915_address_space [noderef] __rcu *vm
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25:got struct 
i915_address_space *
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:43:25: warning: incorrect 
type in assignment (different address spaces)
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34:expected struct 
i915_address_space *vm
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34:got struct 
i915_address_space [noderef] __rcu *vm
+drivers/gpu/drm/i915/gem/selftests/mock_context.c:60:34: warning: incorrect 
type in argument 1 (different address spaces)
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy 
expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1392:5: warning: context imbalance in 
'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/i915_perf.c:1442:15: warning: memset with byte count of 
16777216
+drivers/gpu/drm/i915/i915_perf.c:1496:15: warning: memset with byte count of 
16777216
+./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative 
(-262080)
+./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative 
(-262080)
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 
'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' 
- different lock 

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for DSI driver improvement

[Patchwork]

== Series Details ==

Series: DSI driver improvement
URL   : https://patchwork.freedesktop.org/series/94237/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
446bf065040f drm/i915/dsi: wait for header and payload credit available
0668b3ff4d4e drm/i915/dsi: refine send MIPI DCS command sequence
1d4c2235dac3 drm/i915: Get proper min cdclk if vDSC enabled
acabf38d37d0 drm/i915/dsi: Retrieve max brightness level from VBT
-:52: WARNING:LINE_CONTINUATIONS: Avoid unnecessary line continuations
#52: FILE: drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c:154:
+   panel->backlight.max = 
(dev_priv->vbt.backlight.brightness_precision_bits > 8) \

total: 0 errors, 1 warnings, 0 checks, 32 lines checked
55fa495029cf drm/i915/dsi: Read/write proper brightness value via MIPI DCS 
command

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gem: Fix the mman selftest (rev2)

[Thomas Hellström]

+ jaswanthx.kattaman...@intel.com

On 9/1/21 10:33 AM, Thomas Hellström wrote:



On 8/31/21 8:51 PM, Patchwork wrote:

Project List - Patchwork *Patch Details*
*Series:*   drm/i915/gem: Fix the mman selftest (rev2)
*URL:* 	https://patchwork.freedesktop.org/series/94062/ 


*State:*failure
*Details:* 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20928/index.html 




  CI Bug Log - changes from CI_DRM_10539_full -> Patchwork_20928_full


Summary

*FAILURE*

Serious unknown changes coming with Patchwork_20928_full absolutely 
need to be

verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20928_full, please notify your bug team to 
allow them
to document this new failure mode, which will reduce false positives 
in CI.



Possible new issues

Here are the unknown changes that may have been introduced in 
Patchwork_20928_full:



  IGT changes


Possible regressions

  * igt@sysfs_heartbeat_interval@mixed@vcs0:
  o shard-skl: PASS


-> WARN





Lakshmi, this failure is unrelated.

Thanks,

Thomas

[Intel-gfx] [PATCH 5/5] drm/i915/dsi: Read/write proper brightness value via MIPI DCS command

[Lee Shawn C]

Driver has to swap the endian before send brightness level value
to tcon.

v2: Use __be16 instead of u16 to fix sparse warning.
v3: Send one or two bytes brightness value depend on the precision.

Reported-by: kernel test robot 
Cc: Ville Syrjala 
Cc: Jani Nikula 
Cc: Vandita Kulkarni 
Cc: Cooper Chiou 
Cc: William Tseng 
Signed-off-by: Lee Shawn C 
---
 .../drm/i915/display/intel_dsi_dcs_backlight.c| 15 +--
 1 file changed, 9 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c 
b/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c
index 21ab9e1acb57..722411b5cb21 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c
@@ -47,33 +47,36 @@ static u32 dcs_get_backlight(struct intel_connector 
*connector, enum pipe unused
 {
struct intel_encoder *encoder = intel_attached_encoder(connector);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
+   struct intel_panel *panel = &connector->panel;
struct mipi_dsi_device *dsi_device;
-   u8 data = 0;
+   u8 data[2] = {0, 0};
enum port port;
 
/* FIXME: Need to take care of 16 bit brightness level */
for_each_dsi_port(port, intel_dsi->dcs_backlight_ports) {
dsi_device = intel_dsi->dsi_hosts[port]->device;
mipi_dsi_dcs_read(dsi_device, MIPI_DCS_GET_DISPLAY_BRIGHTNESS,
- &data, sizeof(data));
+ &data,
+ (panel->backlight.max >> 8) ? sizeof(data) : 
1);
break;
}
 
-   return data;
+   return ((data[1] << 8) | data[0]);
 }
 
 static void dcs_set_backlight(const struct drm_connector_state *conn_state, 
u32 level)
 {
struct intel_dsi *intel_dsi = 
enc_to_intel_dsi(to_intel_encoder(conn_state->best_encoder));
+   struct intel_panel *panel = 
&to_intel_connector(conn_state->connector)->panel;
struct mipi_dsi_device *dsi_device;
-   u8 data = level;
+   __be16 data = cpu_to_be16(level);
enum port port;
 
-   /* FIXME: Need to take care of 16 bit brightness level */
for_each_dsi_port(port, intel_dsi->dcs_backlight_ports) {
dsi_device = intel_dsi->dsi_hosts[port]->device;
mipi_dsi_dcs_write(dsi_device, MIPI_DCS_SET_DISPLAY_BRIGHTNESS,
-  &data, sizeof(data));
+  &data,
+  (panel->backlight.max >> 8) ? sizeof(data) : 
1);
}
 }
 
-- 
2.17.1

[Intel-gfx] [PATCH 4/5] drm/i915/dsi: Retrieve max brightness level from VBT

[Lee Shawn C]

So far, DCS backlight driver hardcode (0xFF) for max brightness level.
MIPI DCS spec allow max 0x for set_display_brightness (51h) command.
And VBT brightness precision bits can support 8 ~ 16 bits.

We should set correct precision bits in VBT that meet panel's request.
Driver can refer to this setting then configure max brightness level
in DCS backlight driver properly.

v2: modify variable name brightness_precision_bits instead of
max_brightness_level.

Cc: Ville Syrjala 
Cc: Jani Nikula 
Cc: Vandita Kulkarni 
Cc: Cooper Chiou 
Cc: William Tseng 
Signed-off-by: Lee Shawn C 
---
 drivers/gpu/drm/i915/display/intel_bios.c  | 3 +++
 drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c | 8 ++--
 drivers/gpu/drm/i915/i915_drv.h| 1 +
 3 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c 
b/drivers/gpu/drm/i915/display/intel_bios.c
index e86e6ed2d3bf..ccaf0a3100f7 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -483,6 +483,9 @@ parse_lfp_backlight(struct drm_i915_private *i915,
level = 255;
}
i915->vbt.backlight.min_brightness = min_level;
+
+   i915->vbt.backlight.brightness_precision_bits =
+   backlight_data->brightness_precision_bits[panel_type];
} else {
level = backlight_data->level[panel_type];
i915->vbt.backlight.min_brightness = entry->min_brightness;
diff --git a/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c 
b/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c
index 584c14c4cbd0..21ab9e1acb57 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c
@@ -147,10 +147,14 @@ static void dcs_enable_backlight(const struct 
intel_crtc_state *crtc_state,
 static int dcs_setup_backlight(struct intel_connector *connector,
   enum pipe unused)
 {
+   struct drm_device *dev = connector->base.dev;
+   struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_panel *panel = &connector->panel;
 
-   panel->backlight.max = PANEL_PWM_MAX_VALUE;
-   panel->backlight.level = PANEL_PWM_MAX_VALUE;
+   panel->backlight.max = 
(dev_priv->vbt.backlight.brightness_precision_bits > 8) \
+  ? (1 << 
dev_priv->vbt.backlight.brightness_precision_bits) - 1 \
+  : PANEL_PWM_MAX_VALUE;
+   panel->backlight.level = panel->backlight.max;
 
return 0;
 }
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 005b1cec7007..1b42e39a7cd4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -706,6 +706,7 @@ struct intel_vbt_data {
 
struct {
u16 pwm_freq_hz;
+   u16 brightness_precision_bits;
bool present;
bool active_low_pwm;
u8 min_brightness;  /* min_brightness/255 of max */
-- 
2.17.1

[Intel-gfx] [PATCH 3/5] drm/i915: Get proper min cdclk if vDSC enabled

[Lee Shawn C]

VDSC engine can process only 1 pixel per Cd clock. In case
VDSC is used and max slice count == 1, max supported pixel
clock should be 100% of CD clock. Then do min_cdclk and
pixel clock comparison to get proper min cdclk.

v2:
- Check for dsc enable and slice count ==1 then allow to
  double confirm min cdclk value.

Cc: Ville Syrjala 
Cc: Jani Nikula 
Cc: Vandita Kulkarni 
Cc: Cooper Chiou 
Cc: William Tseng 
Signed-off-by: Lee Shawn C 
Reviewed-by: Vandita Kulkarni 
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 34fa4130d5c4..9aec17b33819 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2139,6 +2139,16 @@ int intel_crtc_compute_min_cdclk(const struct 
intel_crtc_state *crtc_state)
/* Account for additional needs from the planes */
min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk);
 
+   /*
+* VDSC engine can process only 1 pixel per Cd clock.
+* In case VDSC is used and max slice count == 1,
+* max supported pixel clock should be 100% of CD clock.
+* Then do min_cdclk and pixel clock comparison to get cdclk.
+*/
+   if (crtc_state->dsc.compression_enable &&
+   crtc_state->dsc.slice_count == 1)
+   min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate);
+
/*
 * HACK. Currently for TGL platforms we calculate
 * min_cdclk initially based on pixel_rate divided
-- 
2.17.1

[Intel-gfx] [PATCH 2/5] drm/i915/dsi: refine send MIPI DCS command sequence

[Lee Shawn C]

According to chapter "Sending Commands to the Panel" in bspec #29738
and #49188. If driver try to send DCS long pakcet, we have to program
TX payload register at first. And configure TX header HW register later.
DSC long packet would not be sent properly if we don't follow this
sequence.

Cc: Ville Syrjala 
Cc: Jani Nikula 
Cc: Vandita Kulkarni 
Cc: Cooper Chiou 
Cc: William Tseng 
Signed-off-by: Lee Shawn C 
Reviewed-by: Vandita Kulkarni 
---
 drivers/gpu/drm/i915/display/icl_dsi.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c 
b/drivers/gpu/drm/i915/display/icl_dsi.c
index 1780830d9909..60413bbf565f 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1807,11 +1807,6 @@ static ssize_t gen11_dsi_host_transfer(struct 
mipi_dsi_host *host,
if (msg->flags & MIPI_DSI_MSG_USE_LPM)
enable_lpdt = true;
 
-   /* send packet header */
-   ret  = dsi_send_pkt_hdr(intel_dsi_host, dsi_pkt, enable_lpdt);
-   if (ret < 0)
-   return ret;
-
/* only long packet contains payload */
if (mipi_dsi_packet_format_is_long(msg->type)) {
ret = dsi_send_pkt_payld(intel_dsi_host, dsi_pkt);
@@ -1819,6 +1814,11 @@ static ssize_t gen11_dsi_host_transfer(struct 
mipi_dsi_host *host,
return ret;
}
 
+   /* send packet header */
+   ret  = dsi_send_pkt_hdr(intel_dsi_host, dsi_pkt, enable_lpdt);
+   if (ret < 0)
+   return ret;
+
//TODO: add payload receive code if needed
 
ret = sizeof(dsi_pkt.header) + dsi_pkt.payload_length;
-- 
2.17.1