[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: replace X86_FEATURE_PAT with pat_enabled()
== Series Details == Series: drm/i915: replace X86_FEATURE_PAT with pat_enabled() URL : https://patchwork.freedesktop.org/series/97482/ State : success == Summary == CI Bug Log - changes from CI_DRM_10952_full -> Patchwork_21723_full Summary --- **SUCCESS** No regressions found. Participating hosts (9 -> 9) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_21723_full that come from known issues: ### CI changes ### Possible fixes * boot: - shard-apl: ([PASS][1], [PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [FAIL][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25]) ([i915#4386]) -> ([PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10952/shard-apl3/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10952/shard-apl4/boot.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10952/shard-apl8/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10952/shard-apl8/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10952/shard-apl1/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10952/shard-apl8/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10952/shard-apl7/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10952/shard-apl1/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10952/shard-apl1/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10952/shard-apl2/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10952/shard-apl2/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10952/shard-apl2/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10952/shard-apl2/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10952/shard-apl3/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10952/shard-apl7/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10952/shard-apl7/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10952/shard-apl6/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10952/shard-apl3/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10952/shard-apl6/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10952/shard-apl6/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10952/shard-apl6/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10952/shard-apl6/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10952/shard-apl4/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10952/shard-apl4/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10952/shard-apl3/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21723/shard-apl1/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21723/shard-apl1/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21723/shard-apl1/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21723/shard-apl1/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21723/shard-apl2/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21723/shard-apl2/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21723/shard-apl2/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21723/shard-apl2/boot.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21723/shard-apl3/boot.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21723/shard-apl3/boot.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21723/shard-apl3/boot.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21723/shard-apl4/boot.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21723/shard-apl4/boot.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21723/shard-apl4/boot.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21723/shard-apl6/boot.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21723/shard-apl6/boot.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21723/shard-apl6/boot.html [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21723/shard-apl6/boot.html [44]:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix error pointer dereference in i915_gem_do_execbuffer() (rev4)
== Series Details == Series: drm/i915: Fix error pointer dereference in i915_gem_do_execbuffer() (rev4) URL : https://patchwork.freedesktop.org/series/96969/ State : success == Summary == CI Bug Log - changes from CI_DRM_10953 -> Patchwork_21725 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21725/index.html Participating hosts (38 -> 32) -- Additional (1): fi-bdw-gvtdvm Missing(7): fi-tgl-dsi bat-dg1-6 bat-dg1-5 fi-bsw-cyan bat-adlp-6 bat-jsl-2 bat-jsl-1 Known issues Here are the changes found in Patchwork_21725 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@read_all_entries: - fi-kbl-soraka: [PASS][1] -> [DMESG-WARN][2] ([i915#1982] / [i915#262]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/fi-kbl-soraka/igt@debugfs_test@read_all_entries.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21725/fi-kbl-soraka/igt@debugfs_test@read_all_entries.html * igt@fbdev@write: - fi-bdw-gvtdvm: NOTRUN -> [SKIP][3] ([fdo#109271]) +5 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21725/fi-bdw-gvtdvm/igt@fb...@write.html * igt@gem_exec_suspend@basic-s0: - fi-bdw-gvtdvm: NOTRUN -> [INCOMPLETE][4] ([i915#146] / [i915#2539]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21725/fi-bdw-gvtdvm/igt@gem_exec_susp...@basic-s0.html * igt@gem_huc_copy@huc-copy: - fi-skl-6600u: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#2190]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21725/fi-skl-6600u/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@verify-random: - fi-skl-6600u: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#4613]) +3 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21725/fi-skl-6600u/igt@gem_lmem_swapp...@verify-random.html * igt@i915_selftest@live@gt_pm: - fi-tgl-1115g4: [PASS][7] -> [DMESG-FAIL][8] ([i915#3987]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/fi-tgl-1115g4/igt@i915_selftest@live@gt_pm.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21725/fi-tgl-1115g4/igt@i915_selftest@live@gt_pm.html * igt@kms_chamelium@vga-edid-read: - fi-skl-6600u: NOTRUN -> [SKIP][9] ([fdo#109271] / [fdo#111827]) +8 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21725/fi-skl-6600u/igt@kms_chamel...@vga-edid-read.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-skl-6600u: NOTRUN -> [SKIP][10] ([fdo#109271]) +2 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21725/fi-skl-6600u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-skl-6600u: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#533]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21725/fi-skl-6600u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html * igt@kms_psr@primary_page_flip: - fi-skl-6600u: NOTRUN -> [INCOMPLETE][12] ([i915#198]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21725/fi-skl-6600u/igt@kms_psr@primary_page_flip.html Possible fixes * igt@gem_exec_suspend@basic-s0: - fi-tgl-1115g4: [FAIL][13] ([i915#1888]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21725/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s0.html * igt@gem_exec_suspend@basic-s3: - fi-skl-6600u: [INCOMPLETE][15] ([i915#4547]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/fi-skl-6600u/igt@gem_exec_susp...@basic-s3.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21725/fi-skl-6600u/igt@gem_exec_susp...@basic-s3.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#2539]: https://gitlab.freedesktop.org/drm/intel/issues/2539 [i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262 [i915#3987]: https://gitlab.freedesktop.org/drm/intel/issues/3987 [i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533 Build changes
Re: [Intel-gfx] [v3 0/3] Introduce Raptor Lake S
> -Original Message- > From: Jani Nikula > Sent: Wednesday, December 1, 2021 5:52 PM > To: Srivatsa, Anusha ; intel- > g...@lists.freedesktop.org > Subject: Re: [Intel-gfx] [v3 0/3] Introduce Raptor Lake S > > On Wed, 01 Dec 2021, Anusha Srivatsa wrote: > > Raptor Lake S(RPL-S) is a version 12 > > Display, Media and Render. For all i915 purposes it is the same as > > Alder Lake S (ADL-S). > > > > The series introduces it as a subplatform of ADL-S. The one difference > > is the GuC submission which is default on RPL-S but was not the case > > with ADL-S. > > Acked-by: Jani Nikula > > on the series, did not check the pci ids in spec. Thanks for the ack. Anusha > > > > Anusha Srivatsa (3): > > drm/i915/rpl-s: Add PCI IDS for Raptor Lake S > > drm/i915/rpl-s: Add PCH Support for Raptor Lake S > > drm/i915/rpl-s: Enable guc submission by default > > > > arch/x86/kernel/early-quirks.c | 1 + > > drivers/gpu/drm/i915/gt/uc/intel_uc.c| 2 +- > > drivers/gpu/drm/i915/i915_drv.h | 2 ++ > > drivers/gpu/drm/i915/i915_pci.c | 1 + > > drivers/gpu/drm/i915/intel_device_info.c | 7 +++ > > drivers/gpu/drm/i915/intel_device_info.h | 3 +++ > > drivers/gpu/drm/i915/intel_pch.c | 1 + > > drivers/gpu/drm/i915/intel_pch.h | 1 + > > include/drm/i915_pciids.h| 9 + > > 9 files changed, 26 insertions(+), 1 deletion(-) > > -- > Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] ✓ Fi.CI.BAT: success for static analysis failure
== Series Details == Series: static analysis failure URL : https://patchwork.freedesktop.org/series/97486/ State : success == Summary == CI Bug Log - changes from CI_DRM_10953 -> Patchwork_21724 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21724/index.html Participating hosts (38 -> 34) -- Additional (3): fi-bdw-gvtdvm fi-icl-u2 fi-pnv-d510 Missing(7): fi-tgl-dsi bat-dg1-6 bat-dg1-5 fi-bsw-cyan bat-adlp-6 bat-jsl-2 bat-jsl-1 Known issues Here are the changes found in Patchwork_21724 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_cs_nop@fork-gfx0: - fi-icl-u2: NOTRUN -> [SKIP][1] ([fdo#109315]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21724/fi-icl-u2/igt@amdgpu/amd_cs_...@fork-gfx0.html * igt@fbdev@write: - fi-bdw-gvtdvm: NOTRUN -> [SKIP][2] ([fdo#109271]) +5 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21724/fi-bdw-gvtdvm/igt@fb...@write.html * igt@gem_exec_suspend@basic-s0: - fi-bdw-gvtdvm: NOTRUN -> [INCOMPLETE][3] ([i915#146] / [i915#2539]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21724/fi-bdw-gvtdvm/igt@gem_exec_susp...@basic-s0.html * igt@gem_huc_copy@huc-copy: - fi-skl-6600u: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21724/fi-skl-6600u/igt@gem_huc_c...@huc-copy.html - fi-icl-u2: NOTRUN -> [SKIP][5] ([i915#2190]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21724/fi-icl-u2/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@parallel-random-engines: - fi-icl-u2: NOTRUN -> [SKIP][6] ([i915#4613]) +3 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21724/fi-icl-u2/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_lmem_swapping@verify-random: - fi-skl-6600u: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#4613]) +3 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21724/fi-skl-6600u/igt@gem_lmem_swapp...@verify-random.html * igt@i915_selftest@live@gt_engines: - fi-rkl-guc: [PASS][8] -> [INCOMPLETE][9] ([i915#4432]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10953/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21724/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html * igt@i915_selftest@live@objects: - fi-icl-u2: NOTRUN -> [DMESG-WARN][10] ([i915#2867]) +3 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21724/fi-icl-u2/igt@i915_selftest@l...@objects.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-icl-u2: NOTRUN -> [SKIP][11] ([fdo#111827]) +8 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21724/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html * igt@kms_chamelium@vga-edid-read: - fi-skl-6600u: NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +8 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21724/fi-skl-6600u/igt@kms_chamel...@vga-edid-read.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-icl-u2: NOTRUN -> [SKIP][13] ([fdo#109278]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21724/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html - fi-skl-6600u: NOTRUN -> [SKIP][14] ([fdo#109271]) +2 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21724/fi-skl-6600u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html * igt@kms_force_connector_basic@force-load-detect: - fi-icl-u2: NOTRUN -> [SKIP][15] ([fdo#109285]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21724/fi-icl-u2/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-skl-6600u: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#533]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21724/fi-skl-6600u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html * igt@kms_psr@primary_page_flip: - fi-skl-6600u: NOTRUN -> [FAIL][17] ([i915#4547]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21724/fi-skl-6600u/igt@kms_psr@primary_page_flip.html * igt@prime_vgem@basic-userptr: - fi-pnv-d510:NOTRUN -> [SKIP][18] ([fdo#109271]) +57 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21724/fi-pnv-d510/igt@prime_v...@basic-userptr.html - fi-icl-u2: NOTRUN -> [SKIP][19] ([i915#3301]) [19]:
[Intel-gfx] [PATCH] drm/i915: Fix error pointer dereference in i915_gem_do_execbuffer()
From: Dan Carpenter
Originally "out_fence" was set using out_fence = sync_file_create() but
which returns NULL, but now it is set with out_fence = eb_requests_create()
which returns error pointers. The error path needs to be modified to
avoid an Oops in the "goto err_request;" path.
Fixes: 544460c33821 ("drm/i915: Multi-BB execbuf")
Signed-off-by: Dan Carpenter
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 9f7c6ecadb90..6db588b9a30e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -3288,6 +3288,7 @@ i915_gem_do_execbuffer(struct drm_device *dev,
out_fence = eb_requests_create(, in_fence, out_fence_fd);
if (IS_ERR(out_fence)) {
err = PTR_ERR(out_fence);
+ out_fence = NULL;
if (eb.requests[0])
goto err_request;
else
--
2.33.1
Re: [Intel-gfx] [PATCH v4 1/6] drm: move the buddy allocator from i915 into common drm
Hi Arunpravin, Thank you for the patch! Yet something to improve: [auto build test ERROR on drm-intel/for-linux-next] [also build test ERROR on v5.16-rc3] [cannot apply to drm/drm-next drm-tip/drm-tip next-20211201] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Arunpravin/drm-move-the-buddy-allocator-from-i915-into-common-drm/20211202-004327 base: git://anongit.freedesktop.org/drm-intel for-linux-next config: i386-allyesconfig (https://download.01.org/0day-ci/archive/20211202/202112021239.jptbrhi2-...@intel.com/config) compiler: gcc-9 (Debian 9.3.0-22) 9.3.0 reproduce (this is a W=1 build): # https://github.com/0day-ci/linux/commit/afbc900c0399e8c6220abd729932e877e81f37c8 git remote add linux-review https://github.com/0day-ci/linux git fetch --no-tags linux-review Arunpravin/drm-move-the-buddy-allocator-from-i915-into-common-drm/20211202-004327 git checkout afbc900c0399e8c6220abd729932e877e81f37c8 # save the config file to linux build tree mkdir build_dir make W=1 O=build_dir ARCH=i386 SHELL=/bin/bash If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot All errors (new ones prefixed by >>): In file included from drivers/gpu/drm/i915/intel_memory_region.c:242: >> drivers/gpu/drm/i915/selftests/intel_memory_region.c:23:10: fatal error: >> i915_buddy.h: No such file or directory 23 | #include "i915_buddy.h" | ^~ compilation terminated. vim +23 drivers/gpu/drm/i915/selftests/intel_memory_region.c 232a6ebae41919 Matthew Auld 2019-10-08 14 340be48f2c5a3c Matthew Auld 2019-10-25 15 #include "gem/i915_gem_context.h" b908be543e4441 Matthew Auld 2019-10-25 16 #include "gem/i915_gem_lmem.h" 232a6ebae41919 Matthew Auld 2019-10-08 17 #include "gem/i915_gem_region.h" 340be48f2c5a3c Matthew Auld 2019-10-25 18 #include "gem/selftests/igt_gem_utils.h" 232a6ebae41919 Matthew Auld 2019-10-08 19 #include "gem/selftests/mock_context.h" 99919be74aa375 Thomas Hellström 2021-06-17 20 #include "gt/intel_engine_pm.h" 6804da20bb549e Chris Wilson 2019-10-27 21 #include "gt/intel_engine_user.h" b908be543e4441 Matthew Auld 2019-10-25 22 #include "gt/intel_gt.h" d53ec322dc7de3 Matthew Auld 2021-06-16 @23 #include "i915_buddy.h" 99919be74aa375 Thomas Hellström 2021-06-17 24 #include "gt/intel_migrate.h" ba12993c522801 Matthew Auld 2020-01-29 25 #include "i915_memcpy.h" d53ec322dc7de3 Matthew Auld 2021-06-16 26 #include "i915_ttm_buddy_manager.h" 01377a0d7e6648 Abdiel Janulgue 2019-10-25 27 #include "selftests/igt_flush_test.h" 2f0b97ca021186 Matthew Auld 2019-10-08 28 #include "selftests/i915_random.h" 232a6ebae41919 Matthew Auld 2019-10-08 29 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org
[Intel-gfx] [PATCH 1/1] static analysis failure
fix for null ptr dereferences.
Signed-off-by: Pallavi Mishra
---
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 3 +++
drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 4 +++-
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 218a9b3037c7..997fe73c205b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -906,6 +906,8 @@ vm_access_ttm(struct vm_area_struct *area, unsigned long
addr,
struct drm_i915_gem_object *obj =
i915_ttm_to_gem(area->vm_private_data);
+ GEM_BUG_ON(!obj);
+
if (i915_gem_object_is_readonly(obj) && write)
return -EACCES;
@@ -966,6 +968,7 @@ static const struct drm_i915_gem_object_ops
i915_gem_ttm_obj_ops = {
void i915_ttm_bo_destroy(struct ttm_buffer_object *bo)
{
struct drm_i915_gem_object *obj = i915_ttm_to_gem(bo);
+ GEM_BUG_ON(!obj);
i915_gem_object_release_memory_region(obj);
mutex_destroy(>ttm.get_io_page.lock);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
index 80df9f592407..12ba05d44d0f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
@@ -369,8 +369,10 @@ void i915_ttm_adjust_gem_after_move(struct
drm_i915_gem_object *obj)
int i915_ttm_move_notify(struct ttm_buffer_object *bo)
{
struct drm_i915_gem_object *obj = i915_ttm_to_gem(bo);
+
int ret;
+ GEM_BUG_ON(!obj);
ret = i915_gem_object_unbind(obj, I915_GEM_OBJECT_UNBIND_ACTIVE);
if (ret)
return ret;
@@ -506,7 +508,7 @@ static void i915_ttm_memcpy_init(struct i915_ttm_memcpy_arg
*arg,
dst_reg = i915_ttm_region(bo->bdev, dst_mem->mem_type);
src_reg = i915_ttm_region(bo->bdev, bo->resource->mem_type);
- GEM_BUG_ON(!dst_reg || !src_reg);
+ GEM_BUG_ON(!dst_reg || !src_reg || !obj);
arg->dst_iter = !i915_ttm_cpu_maps_iomem(dst_mem) ?
ttm_kmap_iter_tt_init(>_dst_iter.tt, dst_ttm) :
--
2.25.1
[Intel-gfx] [PATCH 0/1] static analysis failure
fix for null ptr dereferences Pallavi Mishra (1): static analysis failure drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 3 +++ drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 4 +++- 2 files changed, 6 insertions(+), 1 deletion(-) -- 2.25.1
[Intel-gfx] ✓ Fi.CI.IGT: success for Bump DMC to v2.14 on ADL-P (rev2)
== Series Details == Series: Bump DMC to v2.14 on ADL-P (rev2) URL : https://patchwork.freedesktop.org/series/97477/ State : success == Summary == CI Bug Log - changes from CI_DRM_10951_full -> Patchwork_21722_full Summary --- **SUCCESS** No regressions found. Participating hosts (10 -> 9) -- Missing(1): shard-rkl Known issues Here are the changes found in Patchwork_21722_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_capture@pi@rcs0: - shard-skl: [PASS][1] -> [INCOMPLETE][2] ([i915#4547]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10951/shard-skl4/igt@gem_exec_capture@p...@rcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21722/shard-skl10/igt@gem_exec_capture@p...@rcs0.html * igt@gem_exec_fair@basic-deadline: - shard-kbl: NOTRUN -> [FAIL][3] ([i915#2846]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21722/shard-kbl3/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-pace@bcs0: - shard-tglb: [PASS][4] -> [FAIL][5] ([i915#2842]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10951/shard-tglb3/igt@gem_exec_fair@basic-p...@bcs0.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21722/shard-tglb3/igt@gem_exec_fair@basic-p...@bcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-iclb: NOTRUN -> [FAIL][6] ([i915#2842]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21722/shard-iclb2/igt@gem_exec_fair@basic-p...@vcs1.html * igt@gem_lmem_swapping@heavy-verify-multi: - shard-glk: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#4613]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21722/shard-glk4/igt@gem_lmem_swapp...@heavy-verify-multi.html * igt@gem_lmem_swapping@heavy-verify-random: - shard-kbl: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#4613]) +1 similar issue [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21722/shard-kbl3/igt@gem_lmem_swapp...@heavy-verify-random.html * igt@gem_lmem_swapping@parallel-multi: - shard-apl: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#4613]) +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21722/shard-apl4/igt@gem_lmem_swapp...@parallel-multi.html * igt@gem_lmem_swapping@random: - shard-tglb: NOTRUN -> [SKIP][10] ([i915#4613]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21722/shard-tglb6/igt@gem_lmem_swapp...@random.html - shard-skl: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#4613]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21722/shard-skl1/igt@gem_lmem_swapp...@random.html - shard-iclb: NOTRUN -> [SKIP][12] ([i915#4613]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21722/shard-iclb8/igt@gem_lmem_swapp...@random.html * igt@gem_pwrite@basic-exhaustion: - shard-kbl: NOTRUN -> [WARN][13] ([i915#2658]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21722/shard-kbl2/igt@gem_pwr...@basic-exhaustion.html - shard-apl: NOTRUN -> [WARN][14] ([i915#2658]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21722/shard-apl6/igt@gem_pwr...@basic-exhaustion.html * igt@gem_userptr_blits@input-checking: - shard-skl: NOTRUN -> [DMESG-WARN][15] ([i915#3002]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21722/shard-skl7/igt@gem_userptr_bl...@input-checking.html * igt@gen7_exec_parse@oacontrol-tracking: - shard-iclb: NOTRUN -> [SKIP][16] ([fdo#109289]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21722/shard-iclb8/igt@gen7_exec_pa...@oacontrol-tracking.html * igt@gen9_exec_parse@allowed-single: - shard-skl: [PASS][17] -> [DMESG-WARN][18] ([i915#1436] / [i915#716]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10951/shard-skl10/igt@gen9_exec_pa...@allowed-single.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21722/shard-skl4/igt@gen9_exec_pa...@allowed-single.html * igt@kms_async_flips@crc: - shard-skl: NOTRUN -> [FAIL][19] ([i915#4272]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21722/shard-skl6/igt@kms_async_fl...@crc.html * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip: - shard-apl: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#3777]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21722/shard-apl6/igt@kms_big...@x-tiled-max-hw-stride-32bpp-rotate-180-hflip.html - shard-skl: NOTRUN -> [SKIP][21] ([fdo#109271] / [i915#3777]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21722/shard-skl7/igt@kms_big...@x-tiled-max-hw-stride-32bpp-rotate-180-hflip.html *
Re: [Intel-gfx] [PATCH] drm/i915: Add PLANE_CUS_CTL restriction in max_width
> -Original Message-
> From: Ville Syrjälä
> Sent: Wednesday, December 1, 2021 8:33 PM
> To: Srinivas, Vidya
> Cc: intel-gfx@lists.freedesktop.org; Yashashvi, Shantam
>
> Subject: Re: [PATCH] drm/i915: Add PLANE_CUS_CTL restriction in max_width
>
> On Wed, Dec 01, 2021 at 09:17:27AM +0530, Vidya Srinivas wrote:
> > PLANE_CUS_CTL has a restriction of 4096 width even though PLANE_SIZE
> > and scaler size registers supports max 5120.
> > Take care of this restriction in max_width.
> >
> > Without this patch, when 5k content is sent on HDR plane with NV12
> > content, FIFO underrun is seen and screen blanks out.
> >
> > v2: Addressed review comments from Ville. Added separate functions for
> > max_width - for HDR and SDR
> >
> > v3: Addressed review comments from Ville. Changed names of HDR and
> SDR
> > max_width functions to icl_hdr_plane_max_width and
> > icl_sdr_plane_max_width
> >
> > v4: Fixed paranthesis alignment. No code change
> >
> > Reviewed-by: Ville Syrjälä
> > Signed-off-by: Vidya Srinivas
> > Signed-off-by: Yashashvi Shantam
>
> Hmm. What's this extra sob doing here?
Hello Ville, sincere apologies. When I run checkpatch.pl I see no warnings on
my host.
However patchwork keeps reporting paranthesis alignment warning.
I tried to push it multiple times after running checkpatch.pl on my host.
Really sorry about that.
Regards
Vidya
>
> > ---
> > .../drm/i915/display/skl_universal_plane.c| 21 +++
> > 1 file changed, 17 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > index 28890876bdeb..e717eb58b105 100644
> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > @@ -420,9 +420,19 @@ static int icl_plane_min_width(const struct
> drm_framebuffer *fb,
> > }
> > }
> >
> > -static int icl_plane_max_width(const struct drm_framebuffer *fb,
> > - int color_plane,
> > - unsigned int rotation)
> > +static int icl_hdr_plane_max_width(const struct drm_framebuffer *fb,
> > + int color_plane,
> > + unsigned int rotation)
> > +{
> > + if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
> > + return 4096;
> > + else
> > + return 5120;
> > +}
> > +
> > +static int icl_sdr_plane_max_width(const struct drm_framebuffer *fb,
> > + int color_plane,
> > + unsigned int rotation)
> > {
> > return 5120;
> > }
> > @@ -2108,7 +2118,10 @@ skl_universal_plane_create(struct
> > drm_i915_private *dev_priv,
> >
> > if (DISPLAY_VER(dev_priv) >= 11) {
> > plane->min_width = icl_plane_min_width;
> > - plane->max_width = icl_plane_max_width;
> > + if (icl_is_hdr_plane(dev_priv, plane_id))
> > + plane->max_width = icl_hdr_plane_max_width;
> > + else
> > + plane->max_width = icl_sdr_plane_max_width;
> > plane->max_height = icl_plane_max_height;
> > plane->min_cdclk = icl_plane_min_cdclk;
> > } else if (DISPLAY_VER(dev_priv) >= 10) {
> > --
> > 2.33.0
>
> --
> Ville Syrjälä
> Intel
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Plane register cleanup
== Series Details ==
Series: drm/i915: Plane register cleanup
URL : https://patchwork.freedesktop.org/series/97467/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10950_full -> Patchwork_21718_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (10 -> 10)
--
No changes in participating hosts
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_21718_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@kms_psr2_su@page_flip-xrgb}:
- shard-iclb: [FAIL][1] -> [SKIP][2] +1 similar issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-iclb2/igt@kms_psr2_su@page_flip-xrgb.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-iclb5/igt@kms_psr2_su@page_flip-xrgb.html
Known issues
Here are the changes found in Patchwork_21718_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@feature_discovery@psr2:
- shard-iclb: [PASS][3] -> [SKIP][4] ([i915#658])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-iclb2/igt@feature_discov...@psr2.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-iclb4/igt@feature_discov...@psr2.html
* igt@gem_eio@in-flight-suspend:
- shard-skl: [PASS][5] -> [INCOMPLETE][6] ([i915#198]) +1 similar
issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-skl6/igt@gem_...@in-flight-suspend.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-skl1/igt@gem_...@in-flight-suspend.html
* igt@gem_exec_capture@pi@bcs0:
- shard-skl: [PASS][7] -> [INCOMPLETE][8] ([i915#4547])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-skl4/igt@gem_exec_capture@p...@bcs0.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-skl10/igt@gem_exec_capture@p...@bcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl: [PASS][9] -> [FAIL][10] ([i915#2842]) +1 similar issue
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-kbl2/igt@gem_exec_fair@basic-n...@vcs0.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-kbl3/igt@gem_exec_fair@basic-n...@vcs0.html
* igt@gem_exec_fair@basic-pace@bcs0:
- shard-tglb: [PASS][11] -> [FAIL][12] ([i915#2842])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-tglb8/igt@gem_exec_fair@basic-p...@bcs0.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-tglb2/igt@gem_exec_fair@basic-p...@bcs0.html
* igt@gem_lmem_swapping@parallel-random-engines:
- shard-apl: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#4613]) +1
similar issue
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-apl4/igt@gem_lmem_swapp...@parallel-random-engines.html
- shard-kbl: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613]) +1
similar issue
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-kbl7/igt@gem_lmem_swapp...@parallel-random-engines.html
* igt@gem_lmem_swapping@random:
- shard-tglb: NOTRUN -> [SKIP][15] ([i915#4613])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-tglb5/igt@gem_lmem_swapp...@random.html
- shard-iclb: NOTRUN -> [SKIP][16] ([i915#4613])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-iclb2/igt@gem_lmem_swapp...@random.html
* igt@gem_lmem_swapping@verify-random:
- shard-skl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613]) +3
similar issues
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-skl1/igt@gem_lmem_swapp...@verify-random.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-glk: [PASS][18] -> [FAIL][19] ([i915#644])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/shard-glk9/igt@gem_pp...@flink-and-close-vma-leak.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-glk6/igt@gem_pp...@flink-and-close-vma-leak.html
* igt@gem_pxp@regular-baseline-src-copy-readible:
- shard-kbl: NOTRUN -> [SKIP][20] ([fdo#109271]) +148 similar
issues
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-kbl7/igt@gem_...@regular-baseline-src-copy-readible.html
* igt@gem_userptr_blits@input-checking:
- shard-skl: NOTRUN -> [DMESG-WARN][21] ([i915#3002])
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/shard-skl6/igt@gem_userptr_bl...@input-checking.html
* igt@gem_userptr_blits@vma-merge:
- shard-apl: NOTRUN -> [FAIL][22] ([i915#3318])
[22]:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: replace X86_FEATURE_PAT with pat_enabled()
== Series Details == Series: drm/i915: replace X86_FEATURE_PAT with pat_enabled() URL : https://patchwork.freedesktop.org/series/97482/ State : success == Summary == CI Bug Log - changes from CI_DRM_10952 -> Patchwork_21723 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21723/index.html Participating hosts (39 -> 34) -- Additional (2): fi-kbl-soraka fi-icl-u2 Missing(7): bat-dg1-6 bat-dg1-5 fi-bsw-cyan bat-adlp-6 bat-adlp-4 bat-jsl-2 bat-jsl-1 Known issues Here are the changes found in Patchwork_21723 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@cs-gfx: - fi-rkl-guc: NOTRUN -> [SKIP][1] ([fdo#109315]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21723/fi-rkl-guc/igt@amdgpu/amd_ba...@cs-gfx.html * igt@amdgpu/amd_basic@semaphore: - fi-bdw-5557u: NOTRUN -> [SKIP][2] ([fdo#109271]) +31 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21723/fi-bdw-5557u/igt@amdgpu/amd_ba...@semaphore.html * igt@amdgpu/amd_cs_nop@fork-gfx0: - fi-icl-u2: NOTRUN -> [SKIP][3] ([fdo#109315]) +17 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21723/fi-icl-u2/igt@amdgpu/amd_cs_...@fork-gfx0.html * igt@amdgpu/amd_cs_nop@sync-gfx0: - fi-bsw-n3050: NOTRUN -> [SKIP][4] ([fdo#109271]) +17 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21723/fi-bsw-n3050/igt@amdgpu/amd_cs_...@sync-gfx0.html * igt@gem_exec_fence@basic-busy@bcs0: - fi-kbl-soraka: NOTRUN -> [SKIP][5] ([fdo#109271]) +8 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21723/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html * igt@gem_huc_copy@huc-copy: - fi-kbl-soraka: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#2190]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21723/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html - fi-icl-u2: NOTRUN -> [SKIP][7] ([i915#2190]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21723/fi-icl-u2/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-kbl-soraka: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#4613]) +3 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21723/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html * igt@gem_lmem_swapping@parallel-random-engines: - fi-icl-u2: NOTRUN -> [SKIP][9] ([i915#4613]) +3 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21723/fi-icl-u2/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@i915_selftest@live@execlists: - fi-bsw-kefka: [PASS][10] -> [INCOMPLETE][11] ([i915#2940]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10952/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21723/fi-bsw-kefka/igt@i915_selftest@l...@execlists.html * igt@i915_selftest@live@gt_pm: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][12] ([i915#1886] / [i915#2291]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21723/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-kbl-soraka: NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827]) +8 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21723/fi-kbl-soraka/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_chamelium@dp-crc-fast: - fi-bdw-5557u: NOTRUN -> [SKIP][14] ([fdo#109271] / [fdo#111827]) +8 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21723/fi-bdw-5557u/igt@kms_chamel...@dp-crc-fast.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-icl-u2: NOTRUN -> [SKIP][15] ([fdo#111827]) +8 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21723/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-icl-u2: NOTRUN -> [SKIP][16] ([fdo#109278]) +2 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21723/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html * igt@kms_force_connector_basic@force-load-detect: - fi-icl-u2: NOTRUN -> [SKIP][17] ([fdo#109285]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21723/fi-icl-u2/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-kbl-soraka: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#533]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21723/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html * igt@prime_vgem@basic-userptr: -
Re: [Intel-gfx] [PATCH] drm/i915/selftest: Disable IRQ for timestamp calculation
On Tue, 30 Nov 2021 05:20:05 -0800, Anshuman Gupta wrote:
>
> gt_pm selftest calculates engine ticks cycles and wall time
> cycles by delta of respective engine elapsed TIMESTAMP and ktime
> for period of 1000us.
> It compares the engine ticks cycles with wall time cycles.
>
> Disable local cpu interrupt so that interrupt handler does not
> switch out the thread during measure_clocks() and prevent
> miscalculation of engine tick cycles.
Reviewed-by: Ashutosh Dixit
> v2:
> - nuke preempt_{disable,enable}, as disable_local_irq()
> disable the preemption. (Chris)
>
> Cc: Chris P Wilson
> Cc: Badal Nilawar
> Cc: Ashutosh Dixit
> Signed-off-by: Anshuman Gupta
> ---
> drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
> b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
> index b9441217ca3d..55c5cdb99f45 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
> @@ -43,7 +43,7 @@ static void measure_clocks(struct intel_engine_cs *engine,
> int i;
>
> for (i = 0; i < 5; i++) {
> - preempt_disable();
> + local_irq_disable();
> cycles[i] = -ENGINE_READ_FW(engine, RING_TIMESTAMP);
> dt[i] = ktime_get();
>
> @@ -51,7 +51,7 @@ static void measure_clocks(struct intel_engine_cs *engine,
>
> dt[i] = ktime_sub(ktime_get(), dt[i]);
> cycles[i] += ENGINE_READ_FW(engine, RING_TIMESTAMP);
> - preempt_enable();
> + local_irq_enable();
> }
>
> /* Use the median of both cycle/dt; close enough */
> --
> 2.26.2
>
Re: [Intel-gfx] [PATCH] drm/i915/display/tgl: Implement Wa_14013120569
@Jani @Manasi
Bump.
On Mon, 2021-11-08 at 15:52 -0800, Navare, Manasi wrote:
> On Mon, Nov 01, 2021 at 12:25:21PM +0200, Jani Nikula wrote:
> > On Mon, 28 Jun 2021, Madhumitha Tolakanahalli Pradeep
> > wrote:
> > > PCH display HPD IRQ is not detected with default filter value.
> > > So, PP_CONTROL is manually reprogrammed.
> >
> > Returning to this workaround.
> >
> > You're not supposed to enable the workaround when there's eDP
> > connected. This is also crucial in avoiding issues with eDP PPS.
> >
> > The workaround is specific to Tiger Lake PCH, so you need to check
> > against the PCH, not the GPU.
> >
> > Also see comments inline.
> >
> > >
> > > Signed-off-by: Madhumitha Tolakanahalli Pradeep
> > >
> > > ---
> > > .../gpu/drm/i915/display/intel_display_power.c | 8
> > > drivers/gpu/drm/i915/display/intel_hotplug.c | 16
> > >
> > > 2 files changed, 24 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > index 285380079aab..e44323cc76f5 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > @@ -6385,8 +6385,16 @@ static void
> > > intel_power_domains_verify_state(struct drm_i915_private *i915)
> > >
> > > void intel_display_power_suspend_late(struct drm_i915_private
> > > *i915)
> > > {
> > > + struct drm_i915_private *dev_priv = i915;
> > > + u32 val;
> > > if (DISPLAY_VER(i915) >= 11 || IS_GEMINILAKE(i915) ||
> > > IS_BROXTON(i915)) {
> > > + val = intel_de_read(dev_priv, PP_CONTROL(0));
> > > + /* Wa_14013120569:tgl */
> > > + if (IS_TIGERLAKE(i915)) {
> > > + val &= ~PANEL_POWER_ON;
> > > + intel_de_write(dev_priv, PP_CONTROL(0),
> > > val);
> > > + }
> >
> > As José said, how do you enable the workaround after resume if
> > external
> > displays are still connected?
> >
> > > bxt_enable_dc9(i915);
> > > /* Tweaked Wa_14010685332:icp,jsp,mcc */
> > > if (INTEL_PCH_TYPE(i915) >= PCH_ICP &&
> > > INTEL_PCH_TYPE(i915) <= PCH_MCC)
> > > diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c
> > > b/drivers/gpu/drm/i915/display/intel_hotplug.c
> > > index 47c85ac97c87..8e3f84100daf 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_hotplug.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
> > > @@ -26,6 +26,7 @@
> > > #include "i915_drv.h"
> > > #include "intel_display_types.h"
> > > #include "intel_hotplug.h"
> > > +#include "intel_de.h"
> > >
> > > /**
> > > * DOC: Hotplug
> > > @@ -266,7 +267,9 @@ intel_encoder_hotplug(struct intel_encoder
> > > *encoder,
> > > struct intel_connector *connector)
> > > {
> > > struct drm_device *dev = connector->base.dev;
> > > + struct drm_i915_private *dev_priv = to_i915(dev);
> > > enum drm_connector_status old_status;
> > > + u32 val;
> > > u64 old_epoch_counter;
> > > bool ret = false;
> > >
> > > @@ -288,6 +291,19 @@ intel_encoder_hotplug(struct intel_encoder
> > > *encoder,
> > >
> > > drm_get_connector_status_name(connector->base.status),
> > > old_epoch_counter,
> > > connector->base.epoch_counter);
> > > +
> > > + /* Wa_14013120569:tgl */
> > > + if (IS_TIGERLAKE(dev_priv)) {
> > > + val = intel_de_read(dev_priv,
> > > PP_CONTROL(0));
> > > + if (connector->base.status ==
> > > connector_status_connected) {
> > > + val |= PANEL_POWER_ON;
> > > + intel_de_write(dev_priv,
> > > PP_CONTROL(0), val);
> > > + }
> > > + else if (connector->base.status ==
> > > connector_status_disconnected) {
> > > + val &= ~PANEL_POWER_ON;
> > > + intel_de_write(dev_priv,
> > > PP_CONTROL(0), val);
> > > + }
> > > + }
> >
> > First off, usually if you have a clean, generic, high level
> > function,
> > it's a hint you shouldn't stick low level register access there.
> >
> > If you plug in two external displays and then unplug one of them,
> > you
> > end up disabling the workaround, while it's supposed to remain
> > enabled
> > if there's an external display connected. This is likely the most
> > annoying part about the workaround.
> >
> > This does not seem like a trivial workaround to implement.
> >
>
> Yes I agree, not a trivial W/A to implement. I think few main things
> to figure out:
> - Right place to enable/disable the W/A at connect/disconnect and for
> the connectors already connected on boot - Probably in
>
[Intel-gfx] i915 Updates: ADL-P DMC v2.14
Hi Ben, Josh, Kyle, Kindly add the below i915 changes to linux-firmware: The following changes since commit b0e898fbaf377c99a36aac6fdeb7250003648ca4: linux-firmware: Update firmware file for Intel Bluetooth 9462 (2021- 11-23 12:31:45 -0500) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-firmware adlp_dmc_v2.14_update for you to fetch changes up to 2a2aa410c2eaebe5807d1fd321e42b8f53288d91: i915: Add DMC firmware v2.14 for ADL-P (2021-12-01 16:50:30 -0800) Madhumitha Tolakanahalli Pradeep (1): i915: Add DMC firmware v2.14 for ADL-P WHENCE| 3 +++ i915/adlp_dmc_ver2_14.bin | Bin 0 -> 77300 bytes 2 files changed, 3 insertions(+) create mode 100644 i915/adlp_dmc_ver2_14.bin Thanks! - Madhumitha
Re: [Intel-gfx] [PATCH v4 1/6] drm: move the buddy allocator from i915 into common drm
Hi Arunpravin, Thank you for the patch! Yet something to improve: [auto build test ERROR on drm-intel/for-linux-next] [also build test ERROR on v5.16-rc3] [cannot apply to drm/drm-next drm-tip/drm-tip next-20211201] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Arunpravin/drm-move-the-buddy-allocator-from-i915-into-common-drm/20211202-004327 base: git://anongit.freedesktop.org/drm-intel for-linux-next config: x86_64-randconfig-a012-20211130 (https://download.01.org/0day-ci/archive/20211202/202112020812.si0y9psy-...@intel.com/config) compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project 4b553297ef3ee4dc2119d5429adf3072e90fac38) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://github.com/0day-ci/linux/commit/afbc900c0399e8c6220abd729932e877e81f37c8 git remote add linux-review https://github.com/0day-ci/linux git fetch --no-tags linux-review Arunpravin/drm-move-the-buddy-allocator-from-i915-into-common-drm/20211202-004327 git checkout afbc900c0399e8c6220abd729932e877e81f37c8 # save the config file to linux build tree mkdir build_dir COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=x86_64 SHELL=/bin/bash drivers/gpu/ If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot All errors (new ones prefixed by >>): In file included from drivers/gpu/drm/i915/intel_memory_region.c:242: >> drivers/gpu/drm/i915/selftests/intel_memory_region.c:23:10: fatal error: >> 'i915_buddy.h' file not found #include "i915_buddy.h" ^~ 1 error generated. vim +23 drivers/gpu/drm/i915/selftests/intel_memory_region.c 232a6ebae419193 Matthew Auld 2019-10-08 14 340be48f2c5a3c0 Matthew Auld 2019-10-25 15 #include "gem/i915_gem_context.h" b908be543e44414 Matthew Auld 2019-10-25 16 #include "gem/i915_gem_lmem.h" 232a6ebae419193 Matthew Auld 2019-10-08 17 #include "gem/i915_gem_region.h" 340be48f2c5a3c0 Matthew Auld 2019-10-25 18 #include "gem/selftests/igt_gem_utils.h" 232a6ebae419193 Matthew Auld 2019-10-08 19 #include "gem/selftests/mock_context.h" 99919be74aa3753 Thomas Hellström 2021-06-17 20 #include "gt/intel_engine_pm.h" 6804da20bb549e3 Chris Wilson 2019-10-27 21 #include "gt/intel_engine_user.h" b908be543e44414 Matthew Auld 2019-10-25 22 #include "gt/intel_gt.h" d53ec322dc7de32 Matthew Auld 2021-06-16 @23 #include "i915_buddy.h" 99919be74aa3753 Thomas Hellström 2021-06-17 24 #include "gt/intel_migrate.h" ba12993c5228015 Matthew Auld 2020-01-29 25 #include "i915_memcpy.h" d53ec322dc7de32 Matthew Auld 2021-06-16 26 #include "i915_ttm_buddy_manager.h" 01377a0d7e6648b Abdiel Janulgue 2019-10-25 27 #include "selftests/igt_flush_test.h" 2f0b97ca0211863 Matthew Auld 2019-10-08 28 #include "selftests/i915_random.h" 232a6ebae419193 Matthew Auld 2019-10-08 29 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org
Re: [Intel-gfx] [v2 1/1] drm/i915/dmc: Update DMC to v2.14 on ADL-P
On Wed, Dec 01, 2021 at 02:24:04PM -0800, Madhumitha Tolakanahalli Pradeep wrote: Changes since v2.12: - Release notes for v2.13: 1. Fix for simple flip queue with DC6v - Release notes for v2.14: 1. Fix for flip queue roll over cases with DC6v 2. Enhancement for residency 3. Workaround for 3Dlut restore issue v2: Commit message update (Imre) Signed-off-by: Madhumitha Tolakanahalli Pradeep Reviewed-by: Lucas De Marchi thanks Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_dmc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c index 2dc9d632969d..8617cd1ec9b2 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc.c +++ b/drivers/gpu/drm/i915/display/intel_dmc.c @@ -45,8 +45,8 @@ #define GEN12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE -#define ADLP_DMC_PATH DMC_PATH(adlp, 2, 12) -#define ADLP_DMC_VERSION_REQUIRED DMC_VERSION(2, 12) +#define ADLP_DMC_PATH DMC_PATH(adlp, 2, 14) +#define ADLP_DMC_VERSION_REQUIRED DMC_VERSION(2, 14) MODULE_FIRMWARE(ADLP_DMC_PATH); #define ADLS_DMC_PATH DMC_PATH(adls, 2, 01) -- 2.33.1
[Intel-gfx] linux-next: manual merge of the drm-intel-gt tree with the drm-intel tree
Hi all,
Today's linux-next merge of the drm-intel-gt tree got a conflict in:
drivers/gpu/drm/i915/display/intel_fbc.c
between commit:
d06188234427 ("drm/i915/fbc: s/dev_priv/i915/")
from the drm-intel tree and commit:
cca084692394 ("drm/i915: Use per device iommu check")
from the drm-intel-gt tree.
I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging. You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.
--
Cheers,
Stephen Rothwell
diff --cc drivers/gpu/drm/i915/display/intel_fbc.c
index d0c34bc3af6c,c40444206425..
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@@ -1674,12 -1536,12 +1674,12 @@@ static int intel_sanitize_fbc_option(st
return 0;
}
-static bool need_fbc_vtd_wa(struct drm_i915_private *dev_priv)
+static bool need_fbc_vtd_wa(struct drm_i915_private *i915)
{
/* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */
- if (intel_vtd_active() &&
- if (intel_vtd_active(dev_priv) &&
- (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))) {
- drm_info(_priv->drm,
++ if (intel_vtd_active(i915) &&
+ (IS_SKYLAKE(i915) || IS_BROXTON(i915))) {
+ drm_info(>drm,
"Disabling framebuffer compression (FBC) to prevent
screen flicker with VT-d enabled\n");
return true;
}
pgpb9MpNN13wZ.pgp
Description: OpenPGP digital signature
[Intel-gfx] [PATCH] drm/i915: replace X86_FEATURE_PAT with pat_enabled()
PAT can be disabled on boot with "nopat" in the command line. Replace one x86-ism with another, which is slightly more correct to prepare for supporting other architectures. Cc: Matt Roper Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/gem/i915_gem_mman.c | 8 drivers/gpu/drm/i915/gem/i915_gem_pages.c | 3 +-- 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c index 65fc6ff5f59d..c0c509e5c0ae 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c @@ -72,7 +72,7 @@ i915_gem_mmap_ioctl(struct drm_device *dev, void *data, if (args->flags & ~(I915_MMAP_WC)) return -EINVAL; - if (args->flags & I915_MMAP_WC && !boot_cpu_has(X86_FEATURE_PAT)) + if (args->flags & I915_MMAP_WC && !pat_enabled()) return -ENODEV; obj = i915_gem_object_lookup(file, args->handle); @@ -736,7 +736,7 @@ i915_gem_dumb_mmap_offset(struct drm_file *file, if (HAS_LMEM(to_i915(dev))) mmap_type = I915_MMAP_TYPE_FIXED; - else if (boot_cpu_has(X86_FEATURE_PAT)) + else if (pat_enabled()) mmap_type = I915_MMAP_TYPE_WC; else if (!i915_ggtt_has_aperture(_i915(dev)->ggtt)) return -ENODEV; @@ -792,7 +792,7 @@ i915_gem_mmap_offset_ioctl(struct drm_device *dev, void *data, break; case I915_MMAP_OFFSET_WC: - if (!boot_cpu_has(X86_FEATURE_PAT)) + if (!pat_enabled()) return -ENODEV; type = I915_MMAP_TYPE_WC; break; @@ -802,7 +802,7 @@ i915_gem_mmap_offset_ioctl(struct drm_device *dev, void *data, break; case I915_MMAP_OFFSET_UC: - if (!boot_cpu_has(X86_FEATURE_PAT)) + if (!pat_enabled()) return -ENODEV; type = I915_MMAP_TYPE_UC; break; diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c b/drivers/gpu/drm/i915/gem/i915_gem_pages.c index 49c6e55c68ce..89b70f5cde7a 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c @@ -424,8 +424,7 @@ void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj, goto err_unpin; } - if (GEM_WARN_ON(type == I915_MAP_WC && - !static_cpu_has(X86_FEATURE_PAT))) + if (GEM_WARN_ON(type == I915_MAP_WC && !pat_enabled())) ptr = ERR_PTR(-ENODEV); else if (i915_gem_object_has_struct_page(obj)) ptr = i915_gem_object_map_page(obj, type); -- 2.33.1
[Intel-gfx] ✓ Fi.CI.BAT: success for Bump DMC to v2.14 on ADL-P (rev2)
== Series Details == Series: Bump DMC to v2.14 on ADL-P (rev2) URL : https://patchwork.freedesktop.org/series/97477/ State : success == Summary == CI Bug Log - changes from CI_DRM_10951 -> Patchwork_21722 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21722/index.html Participating hosts (39 -> 33) -- Additional (2): fi-kbl-soraka fi-icl-u2 Missing(8): fi-rkl-11600 bat-dg1-6 bat-dg1-5 fi-bsw-cyan bat-adlp-6 fi-pnv-d510 bat-jsl-2 bat-jsl-1 Known issues Here are the changes found in Patchwork_21722 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_cs_nop@fork-gfx0: - fi-icl-u2: NOTRUN -> [SKIP][1] ([fdo#109315]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21722/fi-icl-u2/igt@amdgpu/amd_cs_...@fork-gfx0.html * igt@gem_exec_fence@basic-busy@bcs0: - fi-kbl-soraka: NOTRUN -> [SKIP][2] ([fdo#109271]) +8 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21722/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html * igt@gem_exec_suspend@basic-s3: - fi-bdw-5557u: [PASS][3] -> [INCOMPLETE][4] ([i915#146]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10951/fi-bdw-5557u/igt@gem_exec_susp...@basic-s3.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21722/fi-bdw-5557u/igt@gem_exec_susp...@basic-s3.html * igt@gem_flink_basic@bad-flink: - fi-skl-6600u: [PASS][5] -> [INCOMPLETE][6] ([i915#198]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10951/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21722/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html * igt@gem_huc_copy@huc-copy: - fi-kbl-soraka: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#2190]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21722/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html - fi-icl-u2: NOTRUN -> [SKIP][8] ([i915#2190]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21722/fi-icl-u2/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-kbl-soraka: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#4613]) +3 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21722/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html * igt@gem_lmem_swapping@parallel-random-engines: - fi-icl-u2: NOTRUN -> [SKIP][10] ([i915#4613]) +3 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21722/fi-icl-u2/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@i915_selftest@live@gt_pm: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][11] ([i915#1886] / [i915#2291]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21722/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-kbl-soraka: NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +8 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21722/fi-kbl-soraka/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-icl-u2: NOTRUN -> [SKIP][13] ([fdo#111827]) +8 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21722/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-icl-u2: NOTRUN -> [SKIP][14] ([fdo#109278]) +2 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21722/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html * igt@kms_force_connector_basic@force-load-detect: - fi-icl-u2: NOTRUN -> [SKIP][15] ([fdo#109285]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21722/fi-icl-u2/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-kbl-soraka: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#533]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21722/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html * igt@prime_vgem@basic-userptr: - fi-icl-u2: NOTRUN -> [SKIP][17] ([i915#3301]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21722/fi-icl-u2/igt@prime_v...@basic-userptr.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146 [i915#1886]:
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Re-use i915 macros for checking PTEs (rev9)
== Series Details == Series: drm/i915: Re-use i915 macros for checking PTEs (rev9) URL : https://patchwork.freedesktop.org/series/97090/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10951 -> Patchwork_21721 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_21721 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21721, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21721/index.html Participating hosts (39 -> 34) -- Additional (2): fi-kbl-soraka fi-icl-u2 Missing(7): bat-dg1-6 bat-dg1-5 fi-bsw-cyan bat-adlp-6 fi-pnv-d510 bat-jsl-2 bat-jsl-1 Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_21721: ### IGT changes ### Possible regressions * igt@i915_selftest@live@gem_contexts: - fi-skl-6600u: NOTRUN -> [DMESG-FAIL][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21721/fi-skl-6600u/igt@i915_selftest@live@gem_contexts.html - fi-bsw-kefka: [PASS][2] -> [DMESG-FAIL][3] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10951/fi-bsw-kefka/igt@i915_selftest@live@gem_contexts.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21721/fi-bsw-kefka/igt@i915_selftest@live@gem_contexts.html - fi-glk-dsi: [PASS][4] -> [DMESG-FAIL][5] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10951/fi-glk-dsi/igt@i915_selftest@live@gem_contexts.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21721/fi-glk-dsi/igt@i915_selftest@live@gem_contexts.html - fi-skl-6700k2: [PASS][6] -> [DMESG-FAIL][7] [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10951/fi-skl-6700k2/igt@i915_selftest@live@gem_contexts.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21721/fi-skl-6700k2/igt@i915_selftest@live@gem_contexts.html - fi-cfl-8700k: [PASS][8] -> [DMESG-FAIL][9] [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10951/fi-cfl-8700k/igt@i915_selftest@live@gem_contexts.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21721/fi-cfl-8700k/igt@i915_selftest@live@gem_contexts.html - fi-bsw-n3050: [PASS][10] -> [DMESG-FAIL][11] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10951/fi-bsw-n3050/igt@i915_selftest@live@gem_contexts.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21721/fi-bsw-n3050/igt@i915_selftest@live@gem_contexts.html - fi-kbl-7567u: [PASS][12] -> [DMESG-FAIL][13] [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10951/fi-kbl-7567u/igt@i915_selftest@live@gem_contexts.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21721/fi-kbl-7567u/igt@i915_selftest@live@gem_contexts.html - fi-cfl-guc: [PASS][14] -> [DMESG-FAIL][15] [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10951/fi-cfl-guc/igt@i915_selftest@live@gem_contexts.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21721/fi-cfl-guc/igt@i915_selftest@live@gem_contexts.html - fi-bxt-dsi: [PASS][16] -> [DMESG-FAIL][17] [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10951/fi-bxt-dsi/igt@i915_selftest@live@gem_contexts.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21721/fi-bxt-dsi/igt@i915_selftest@live@gem_contexts.html - fi-kbl-7500u: [PASS][18] -> [DMESG-FAIL][19] [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10951/fi-kbl-7500u/igt@i915_selftest@live@gem_contexts.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21721/fi-kbl-7500u/igt@i915_selftest@live@gem_contexts.html Known issues Here are the changes found in Patchwork_21721 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_cs_nop@fork-gfx0: - fi-icl-u2: NOTRUN -> [SKIP][20] ([fdo#109315]) +17 similar issues [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21721/fi-icl-u2/igt@amdgpu/amd_cs_...@fork-gfx0.html * igt@amdgpu/amd_cs_nop@sync-fork-gfx0: - fi-skl-6600u: NOTRUN -> [SKIP][21] ([fdo#109271]) +18 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21721/fi-skl-6600u/igt@amdgpu/amd_cs_...@sync-fork-gfx0.html * igt@gem_exec_fence@basic-busy@bcs0: - fi-kbl-soraka: NOTRUN -> [SKIP][22] ([fdo#109271]) +8 similar issues [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21721/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html * igt@gem_exec_suspend@basic-s3: - fi-bdw-5557u: [PASS][23] -> [INCOMPLETE][24] ([i915#146]) [23]:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Re-use i915 macros for checking PTEs (rev9)
== Series Details == Series: drm/i915: Re-use i915 macros for checking PTEs (rev9) URL : https://patchwork.freedesktop.org/series/97090/ State : warning == Summary == $ dim checkpatch origin/drm-tip 3809a1d72d34 drm/i915: Re-use i915 macros for checking PTEs -:6: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #6: Certain gen8 ppgtt/gtt functions are using _PAGE_RW and _PAGE_PRESENT to check total: 0 errors, 1 warnings, 0 checks, 72 lines checked
[Intel-gfx] [v2 0/1] Bump DMC to v2.14 on ADL-P
Adding PR for CI to pick the firmware, The following changes since commit f5d519563ac9d2d1f382a817aae5ec5473811ac8: linux-firmware: Update AMD cpu microcode (2021-11-15 12:49:19 -0500) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-firmware adlp_dmc_v2.14 for you to fetch changes up to dd81b8ccf199693e382596eb785cffde9db217c6: i915: Add DMC firmware v2.14 for ADL-P (2021-11-17 17:49:57 -0800) Madhumitha Tolakanahalli Pradeep (1): drm/i915/dmc: Update DMC to v2.14 on ADL-P drivers/gpu/drm/i915/display/intel_dmc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.33.1
[Intel-gfx] [v2 1/1] drm/i915/dmc: Update DMC to v2.14 on ADL-P
Changes since v2.12: - Release notes for v2.13: 1. Fix for simple flip queue with DC6v - Release notes for v2.14: 1. Fix for flip queue roll over cases with DC6v 2. Enhancement for residency 3. Workaround for 3Dlut restore issue v2: Commit message update (Imre) Signed-off-by: Madhumitha Tolakanahalli Pradeep --- drivers/gpu/drm/i915/display/intel_dmc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c index 2dc9d632969d..8617cd1ec9b2 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc.c +++ b/drivers/gpu/drm/i915/display/intel_dmc.c @@ -45,8 +45,8 @@ #define GEN12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE -#define ADLP_DMC_PATH DMC_PATH(adlp, 2, 12) -#define ADLP_DMC_VERSION_REQUIRED DMC_VERSION(2, 12) +#define ADLP_DMC_PATH DMC_PATH(adlp, 2, 14) +#define ADLP_DMC_VERSION_REQUIRED DMC_VERSION(2, 14) MODULE_FIRMWARE(ADLP_DMC_PATH); #define ADLS_DMC_PATH DMC_PATH(adls, 2, 01) -- 2.33.1
[Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [v4,1/6] drm: move the buddy allocator from i915 into common drm
== Series Details == Series: series starting with [v4,1/6] drm: move the buddy allocator from i915 into common drm URL : https://patchwork.freedesktop.org/series/97476/ State : failure == Summary == Applying: drm: move the buddy allocator from i915 into common drm Using index info to reconstruct a base tree... M drivers/gpu/drm/Kconfig M drivers/gpu/drm/Makefile M drivers/gpu/drm/i915/Makefile M drivers/gpu/drm/i915/i915_module.c M drivers/gpu/drm/i915/i915_scatterlist.c Falling back to patching base and 3-way merge... Auto-merging drivers/gpu/drm/i915/i915_scatterlist.c CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/i915_scatterlist.c Auto-merging drivers/gpu/drm/i915/i915_module.c Removing drivers/gpu/drm/i915/i915_buddy.h Removing drivers/gpu/drm/i915/i915_buddy.c Auto-merging drivers/gpu/drm/i915/Makefile Auto-merging drivers/gpu/drm/Makefile CONFLICT (content): Merge conflict in drivers/gpu/drm/Makefile Auto-merging drivers/gpu/drm/Kconfig error: Failed to merge in the changes. hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0001 drm: move the buddy allocator from i915 into common drm When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Re-use i915 macros for checking PTEs (rev8)
== Series Details == Series: drm/i915: Re-use i915 macros for checking PTEs (rev8) URL : https://patchwork.freedesktop.org/series/97090/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10951 -> Patchwork_21719 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_21719 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21719, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21719/index.html Participating hosts (39 -> 33) -- Additional (1): fi-icl-u2 Missing(7): bat-dg1-6 bat-dg1-5 fi-bsw-cyan bat-adlp-6 fi-pnv-d510 bat-jsl-2 bat-jsl-1 Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_21719: ### IGT changes ### Possible regressions * igt@i915_selftest@live@gem_contexts: - fi-skl-6600u: NOTRUN -> [DMESG-FAIL][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21719/fi-skl-6600u/igt@i915_selftest@live@gem_contexts.html - fi-bsw-kefka: [PASS][2] -> [DMESG-FAIL][3] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10951/fi-bsw-kefka/igt@i915_selftest@live@gem_contexts.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21719/fi-bsw-kefka/igt@i915_selftest@live@gem_contexts.html - fi-glk-dsi: [PASS][4] -> [DMESG-FAIL][5] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10951/fi-glk-dsi/igt@i915_selftest@live@gem_contexts.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21719/fi-glk-dsi/igt@i915_selftest@live@gem_contexts.html - fi-skl-6700k2: [PASS][6] -> [DMESG-FAIL][7] [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10951/fi-skl-6700k2/igt@i915_selftest@live@gem_contexts.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21719/fi-skl-6700k2/igt@i915_selftest@live@gem_contexts.html - fi-cfl-8700k: [PASS][8] -> [DMESG-FAIL][9] [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10951/fi-cfl-8700k/igt@i915_selftest@live@gem_contexts.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21719/fi-cfl-8700k/igt@i915_selftest@live@gem_contexts.html - fi-bsw-n3050: [PASS][10] -> [DMESG-FAIL][11] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10951/fi-bsw-n3050/igt@i915_selftest@live@gem_contexts.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21719/fi-bsw-n3050/igt@i915_selftest@live@gem_contexts.html - fi-kbl-7567u: [PASS][12] -> [DMESG-FAIL][13] [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10951/fi-kbl-7567u/igt@i915_selftest@live@gem_contexts.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21719/fi-kbl-7567u/igt@i915_selftest@live@gem_contexts.html - fi-cfl-guc: [PASS][14] -> [DMESG-FAIL][15] [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10951/fi-cfl-guc/igt@i915_selftest@live@gem_contexts.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21719/fi-cfl-guc/igt@i915_selftest@live@gem_contexts.html - fi-bxt-dsi: [PASS][16] -> [DMESG-FAIL][17] [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10951/fi-bxt-dsi/igt@i915_selftest@live@gem_contexts.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21719/fi-bxt-dsi/igt@i915_selftest@live@gem_contexts.html - fi-bdw-5557u: [PASS][18] -> [DMESG-FAIL][19] [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10951/fi-bdw-5557u/igt@i915_selftest@live@gem_contexts.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21719/fi-bdw-5557u/igt@i915_selftest@live@gem_contexts.html - fi-kbl-7500u: [PASS][20] -> [DMESG-FAIL][21] [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10951/fi-kbl-7500u/igt@i915_selftest@live@gem_contexts.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21719/fi-kbl-7500u/igt@i915_selftest@live@gem_contexts.html Known issues Here are the changes found in Patchwork_21719 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_cs_nop@fork-gfx0: - fi-icl-u2: NOTRUN -> [SKIP][22] ([fdo#109315]) +17 similar issues [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21719/fi-icl-u2/igt@amdgpu/amd_cs_...@fork-gfx0.html * igt@amdgpu/amd_cs_nop@sync-fork-gfx0: - fi-skl-6600u: NOTRUN -> [SKIP][23] ([fdo#109271]) +18 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21719/fi-skl-6600u/igt@amdgpu/amd_cs_...@sync-fork-gfx0.html * igt@gem_huc_copy@huc-copy: - fi-icl-u2: NOTRUN -> [SKIP][24] ([i915#2190]) [24]:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Re-use i915 macros for checking PTEs (rev8)
== Series Details == Series: drm/i915: Re-use i915 macros for checking PTEs (rev8) URL : https://patchwork.freedesktop.org/series/97090/ State : warning == Summary == $ dim checkpatch origin/drm-tip 6a888e8bac16 drm/i915: Re-use i915 macros for checking PTEs -:6: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #6: Certain gen8 ppgtt/gtt functions are using _PAGE_RW and _PAGE_PRESENT to check total: 0 errors, 1 warnings, 0 checks, 72 lines checked
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: break intel_display_types.h dependency on i915_drv.h (rev2)
== Series Details == Series: drm/i915: break intel_display_types.h dependency on i915_drv.h (rev2) URL : https://patchwork.freedesktop.org/series/97173/ State : success == Summary == CI Bug Log - changes from CI_DRM_10949_full -> Patchwork_21716_full Summary --- **SUCCESS** No regressions found. Participating hosts (10 -> 11) -- Additional (1): shard-rkl Known issues Here are the changes found in Patchwork_21716_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@preservation-s3@vcs0: - shard-kbl: [PASS][1] -> [DMESG-WARN][2] ([i915#180]) +5 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10949/shard-kbl4/igt@gem_ctx_isolation@preservation...@vcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21716/shard-kbl7/igt@gem_ctx_isolation@preservation...@vcs0.html * igt@gem_exec_capture@pi@vcs0: - shard-skl: [PASS][3] -> [INCOMPLETE][4] ([i915#4547]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10949/shard-skl6/igt@gem_exec_capture@p...@vcs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21716/shard-skl4/igt@gem_exec_capture@p...@vcs0.html * igt@gem_exec_endless@dispatch@rcs0: - shard-tglb: [PASS][5] -> [INCOMPLETE][6] ([i915#3778]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10949/shard-tglb6/igt@gem_exec_endless@dispa...@rcs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21716/shard-tglb6/igt@gem_exec_endless@dispa...@rcs0.html * igt@gem_exec_fair@basic-deadline: - shard-skl: NOTRUN -> [FAIL][7] ([i915#2846]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21716/shard-skl1/igt@gem_exec_f...@basic-deadline.html - shard-glk: [PASS][8] -> [FAIL][9] ([i915#2846]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10949/shard-glk4/igt@gem_exec_f...@basic-deadline.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21716/shard-glk6/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-tglb: [PASS][10] -> [FAIL][11] ([i915#2842]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10949/shard-tglb1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21716/shard-tglb2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-iclb: [PASS][12] -> [FAIL][13] ([i915#2842]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10949/shard-iclb3/igt@gem_exec_fair@basic-pace-s...@rcs0.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21716/shard-iclb6/igt@gem_exec_fair@basic-pace-s...@rcs0.html * igt@gem_lmem_swapping@heavy-verify-random: - shard-skl: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613]) +1 similar issue [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21716/shard-skl9/igt@gem_lmem_swapp...@heavy-verify-random.html - shard-apl: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4613]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21716/shard-apl2/igt@gem_lmem_swapp...@heavy-verify-random.html * igt@gen9_exec_parse@allowed-single: - shard-skl: NOTRUN -> [DMESG-WARN][16] ([i915#1436] / [i915#716]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21716/shard-skl1/igt@gen9_exec_pa...@allowed-single.html * igt@i915_suspend@fence-restore-tiled2untiled: - shard-kbl: NOTRUN -> [DMESG-WARN][17] ([i915#180]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21716/shard-kbl7/igt@i915_susp...@fence-restore-tiled2untiled.html * igt@kms_async_flips@alternate-sync-async-flip: - shard-skl: [PASS][18] -> [FAIL][19] ([i915#2521]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10949/shard-skl6/igt@kms_async_fl...@alternate-sync-async-flip.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21716/shard-skl4/igt@kms_async_fl...@alternate-sync-async-flip.html * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip: - shard-kbl: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#3777]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21716/shard-kbl2/igt@kms_big...@x-tiled-max-hw-stride-32bpp-rotate-0-hflip.html * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip: - shard-skl: NOTRUN -> [FAIL][21] ([i915#3743]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21716/shard-skl1/igt@kms_big...@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip: - shard-apl: NOTRUN -> [SKIP][22] ([fdo#109271] / [i915#3777]) [22]:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Plane register cleanup
== Series Details == Series: drm/i915: Plane register cleanup URL : https://patchwork.freedesktop.org/series/97467/ State : success == Summary == CI Bug Log - changes from CI_DRM_10950 -> Patchwork_21718 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/index.html Participating hosts (40 -> 33) -- Additional (1): fi-icl-u2 Missing(8): bat-dg1-6 bat-dg1-5 fi-bsw-cyan bat-adlp-6 bat-adlp-4 fi-pnv-d510 bat-jsl-2 bat-jsl-1 Known issues Here are the changes found in Patchwork_21718 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@cs-gfx: - fi-rkl-guc: NOTRUN -> [SKIP][1] ([fdo#109315]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/fi-rkl-guc/igt@amdgpu/amd_ba...@cs-gfx.html * igt@amdgpu/amd_cs_nop@fork-gfx0: - fi-icl-u2: NOTRUN -> [SKIP][2] ([fdo#109315]) +17 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/fi-icl-u2/igt@amdgpu/amd_cs_...@fork-gfx0.html * igt@gem_huc_copy@huc-copy: - fi-icl-u2: NOTRUN -> [SKIP][3] ([i915#2190]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/fi-icl-u2/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@parallel-random-engines: - fi-icl-u2: NOTRUN -> [SKIP][4] ([i915#4613]) +3 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/fi-icl-u2/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@i915_selftest@live@execlists: - fi-bsw-n3050: [PASS][5] -> [INCOMPLETE][6] ([i915#2940]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html * igt@i915_selftest@live@gt_pm: - fi-tgl-1115g4: [PASS][7] -> [DMESG-FAIL][8] ([i915#3987]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/fi-tgl-1115g4/igt@i915_selftest@live@gt_pm.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/fi-tgl-1115g4/igt@i915_selftest@live@gt_pm.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-icl-u2: NOTRUN -> [SKIP][9] ([fdo#111827]) +8 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-icl-u2: NOTRUN -> [SKIP][10] ([fdo#109278]) +2 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html * igt@kms_force_connector_basic@force-load-detect: - fi-icl-u2: NOTRUN -> [SKIP][11] ([fdo#109285]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/fi-icl-u2/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_psr@primary_page_flip: - fi-skl-6600u: [PASS][12] -> [FAIL][13] ([i915#4547]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/fi-skl-6600u/igt@kms_psr@primary_page_flip.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/fi-skl-6600u/igt@kms_psr@primary_page_flip.html * igt@prime_vgem@basic-userptr: - fi-icl-u2: NOTRUN -> [SKIP][14] ([i915#3301]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/fi-icl-u2/igt@prime_v...@basic-userptr.html * igt@runner@aborted: - fi-skl-6600u: NOTRUN -> [FAIL][15] ([i915#3363] / [i915#4312]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/fi-skl-6600u/igt@run...@aborted.html - fi-bsw-n3050: NOTRUN -> [FAIL][16] ([fdo#109271] / [i915#1436] / [i915#3428] / [i915#4312]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/fi-bsw-n3050/igt@run...@aborted.html Possible fixes * igt@i915_selftest@live@gt_engines: - fi-rkl-guc: [INCOMPLETE][17] ([i915#4432]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html * igt@i915_selftest@live@gt_heartbeat: - fi-bdw-5557u: [DMESG-FAIL][19] ([i915#541]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/fi-bdw-5557u/igt@i915_selftest@live@gt_heartbeat.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21718/fi-bdw-5557u/igt@i915_selftest@live@gt_heartbeat.html * igt@kms_frontbuffer_tracking@basic: - fi-cml-u2: [DMESG-WARN][21] ([i915#4269]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html [22]:
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] Revert "drm/i915: Implement Wa_1508744258" (rev2)
== Series Details == Series: series starting with [1/2] Revert "drm/i915: Implement Wa_1508744258" (rev2) URL : https://patchwork.freedesktop.org/series/97105/ State : success == Summary == CI Bug Log - changes from CI_DRM_10949_full -> Patchwork_21715_full Summary --- **WARNING** Minor unknown changes coming with Patchwork_21715_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21715_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (10 -> 11) -- Additional (1): shard-rkl Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_21715_full: ### IGT changes ### Warnings * igt@kms_chamelium@vga-hpd-without-ddc: - shard-skl: [SKIP][1] ([fdo#109271] / [fdo#111827]) -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10949/shard-skl10/igt@kms_chamel...@vga-hpd-without-ddc.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21715/shard-skl6/igt@kms_chamel...@vga-hpd-without-ddc.html Known issues Here are the changes found in Patchwork_21715_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_eio@in-flight-contexts-1us: - shard-snb: [PASS][3] -> [FAIL][4] ([i915#4409]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10949/shard-snb5/igt@gem_...@in-flight-contexts-1us.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21715/shard-snb6/igt@gem_...@in-flight-contexts-1us.html * igt@gem_exec_capture@pi@vcs0: - shard-skl: [PASS][5] -> [INCOMPLETE][6] ([i915#4547]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10949/shard-skl6/igt@gem_exec_capture@p...@vcs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21715/shard-skl1/igt@gem_exec_capture@p...@vcs0.html * igt@gem_exec_fair@basic-deadline: - shard-kbl: [PASS][7] -> [FAIL][8] ([i915#2846]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10949/shard-kbl2/igt@gem_exec_f...@basic-deadline.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21715/shard-kbl4/igt@gem_exec_f...@basic-deadline.html - shard-skl: NOTRUN -> [FAIL][9] ([i915#2846]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21715/shard-skl10/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-none@vecs0: - shard-kbl: [PASS][10] -> [FAIL][11] ([i915#2842]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10949/shard-kbl7/igt@gem_exec_fair@basic-n...@vecs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21715/shard-kbl2/igt@gem_exec_fair@basic-n...@vecs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-tglb: [PASS][12] -> [FAIL][13] ([i915#2842]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10949/shard-tglb1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21715/shard-tglb5/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-iclb: [PASS][14] -> [FAIL][15] ([i915#2842]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10949/shard-iclb3/igt@gem_exec_fair@basic-pace-s...@rcs0.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21715/shard-iclb3/igt@gem_exec_fair@basic-pace-s...@rcs0.html * igt@gem_lmem_swapping@heavy-verify-random: - shard-apl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4613]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21715/shard-apl2/igt@gem_lmem_swapp...@heavy-verify-random.html * igt@gem_lmem_swapping@parallel-random-verify: - shard-skl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21715/shard-skl1/igt@gem_lmem_swapp...@parallel-random-verify.html * igt@gen9_exec_parse@allowed-single: - shard-skl: NOTRUN -> [DMESG-WARN][18] ([i915#1436] / [i915#716]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21715/shard-skl10/igt@gen9_exec_pa...@allowed-single.html * igt@i915_selftest@live@execlists: - shard-skl: [PASS][19] -> [INCOMPLETE][20] ([i915#198]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10949/shard-skl4/igt@i915_selftest@l...@execlists.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21715/shard-skl4/igt@i915_selftest@l...@execlists.html * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip: - shard-kbl: NOTRUN -> [SKIP][21] ([fdo#109271] / [i915#3777]) [21]:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Plane register cleanup
== Series Details == Series: drm/i915: Plane register cleanup URL : https://patchwork.freedesktop.org/series/97467/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plane register cleanup
== Series Details == Series: drm/i915: Plane register cleanup URL : https://patchwork.freedesktop.org/series/97467/ State : warning == Summary == $ dim checkpatch origin/drm-tip 2a489c8cf0ae drm/i915: Get rid of the 64bit PLANE_CC_VAL mmio -:69: WARNING:LONG_LINE: line length of 102 exceeds 100 columns #69: FILE: drivers/gpu/drm/i915/i915_reg.h:7368: +#define _PLANE_CC_VAL_1(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B) + (dw) * 4) -:70: WARNING:LONG_LINE: line length of 102 exceeds 100 columns #70: FILE: drivers/gpu/drm/i915/i915_reg.h:7369: +#define _PLANE_CC_VAL_2(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B) + (dw) * 4) -:71: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects? #71: FILE: drivers/gpu/drm/i915/i915_reg.h:7370: +#define PLANE_CC_VAL(pipe, plane, dw) \ + _MMIO_PLANE((plane), _PLANE_CC_VAL_1((pipe), (dw)), _PLANE_CC_VAL_2((pipe), (dw))) -:71: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dw' - possible side-effects? #71: FILE: drivers/gpu/drm/i915/i915_reg.h:7370: +#define PLANE_CC_VAL(pipe, plane, dw) \ + _MMIO_PLANE((plane), _PLANE_CC_VAL_1((pipe), (dw)), _PLANE_CC_VAL_2((pipe), (dw))) total: 0 errors, 2 warnings, 2 checks, 41 lines checked cace02264ed4 drm/i915: Rename plane YUV order bits fd4e986084c5 drm/i915: Get rid of the "sizes are 0 based" stuff fb774f7bdbf7 drm/i915: Sipmplify PLANE_STRIDE masking 0ae6611ab3f7 drm/i915: Rename PLANE_CUS_CTL Y plane bits f2f7a1963976 drm/i915: Use REG_BIT() & co. for universal plane bits 08836e799b35 drm/i915: Clean up pre-skl primary plane registers b7bd2fa19c5d drm/i915: Clean up ivb+ sprite plane registers -:114: WARNING:LONG_LINE_COMMENT: line length of 106 exceeds 100 columns #114: FILE: drivers/gpu/drm/i915/i915_reg.h:7058: +#define SPRITE_FORMAT_XR_BGR101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 5) /* Extended range */ total: 0 errors, 1 warnings, 0 checks, 150 lines checked b2a43d32eb81 drm/i915: Clean up vlv/chv sprite plane registers e86cd1d175b5 drm/i915: Clean up g4x+ sprite plane registers f5a56e525f98 drm/i915: Clean up cursor registers -:144: WARNING:LONG_LINE_COMMENT: line length of 103 exceeds 100 columns #144: FILE: drivers/gpu/drm/i915/i915_reg.h:6767: +#define CURSOR_STRIDE(stride)REG_FIELD_PREP(CURSOR_STRIDE_MASK, ffs(stride) - 9) /* 256,512,1k,2k */ total: 0 errors, 1 warnings, 0 checks, 182 lines checked 0008f4a39e22 drm/i915: Extract skl_plane_aux_dist() 79283225eb38 drm/i915: Declutter color key register stuff 7f07412a683b drm/i915: Nuke pointless middle men for skl+ plane programming
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Re-use i915 macros for checking PTEs (rev7)
== Series Details == Series: drm/i915: Re-use i915 macros for checking PTEs (rev7) URL : https://patchwork.freedesktop.org/series/97090/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10950 -> Patchwork_21717 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_21717 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_21717, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21717/index.html Participating hosts (40 -> 32) -- Additional (1): fi-kbl-soraka Missing(9): bat-dg1-6 bat-dg1-5 fi-bsw-cyan fi-apl-guc bat-adlp-6 bat-adlp-4 fi-pnv-d510 bat-jsl-2 bat-jsl-1 Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_21717: ### IGT changes ### Possible regressions * igt@i915_selftest@live@gem_contexts: - fi-bsw-kefka: [PASS][1] -> [DMESG-FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/fi-bsw-kefka/igt@i915_selftest@live@gem_contexts.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21717/fi-bsw-kefka/igt@i915_selftest@live@gem_contexts.html - fi-glk-dsi: [PASS][3] -> [DMESG-FAIL][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/fi-glk-dsi/igt@i915_selftest@live@gem_contexts.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21717/fi-glk-dsi/igt@i915_selftest@live@gem_contexts.html - fi-skl-6700k2: [PASS][5] -> [DMESG-FAIL][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/fi-skl-6700k2/igt@i915_selftest@live@gem_contexts.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21717/fi-skl-6700k2/igt@i915_selftest@live@gem_contexts.html - fi-cfl-8700k: [PASS][7] -> [DMESG-FAIL][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/fi-cfl-8700k/igt@i915_selftest@live@gem_contexts.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21717/fi-cfl-8700k/igt@i915_selftest@live@gem_contexts.html - fi-bsw-n3050: [PASS][9] -> [DMESG-FAIL][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/fi-bsw-n3050/igt@i915_selftest@live@gem_contexts.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21717/fi-bsw-n3050/igt@i915_selftest@live@gem_contexts.html - fi-kbl-7567u: [PASS][11] -> [DMESG-FAIL][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/fi-kbl-7567u/igt@i915_selftest@live@gem_contexts.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21717/fi-kbl-7567u/igt@i915_selftest@live@gem_contexts.html - fi-cfl-guc: [PASS][13] -> [DMESG-FAIL][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/fi-cfl-guc/igt@i915_selftest@live@gem_contexts.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21717/fi-cfl-guc/igt@i915_selftest@live@gem_contexts.html - fi-bxt-dsi: [PASS][15] -> [DMESG-FAIL][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/fi-bxt-dsi/igt@i915_selftest@live@gem_contexts.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21717/fi-bxt-dsi/igt@i915_selftest@live@gem_contexts.html - fi-bdw-5557u: [PASS][17] -> [DMESG-FAIL][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/fi-bdw-5557u/igt@i915_selftest@live@gem_contexts.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21717/fi-bdw-5557u/igt@i915_selftest@live@gem_contexts.html - fi-kbl-7500u: [PASS][19] -> [DMESG-FAIL][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/fi-kbl-7500u/igt@i915_selftest@live@gem_contexts.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21717/fi-kbl-7500u/igt@i915_selftest@live@gem_contexts.html Known issues Here are the changes found in Patchwork_21717 that come from known issues: ### CI changes ### Issues hit * boot: - fi-kbl-soraka: NOTRUN -> [FAIL][21] ([i915#4337]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21717/fi-kbl-soraka/boot.html ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@cs-gfx: - fi-rkl-guc: NOTRUN -> [SKIP][22] ([fdo#109315]) +17 similar issues [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21717/fi-rkl-guc/igt@amdgpu/amd_ba...@cs-gfx.html * igt@kms_psr@primary_page_flip: - fi-skl-6600u: [PASS][23] -> [INCOMPLETE][24] ([i915#198]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10950/fi-skl-6600u/igt@kms_psr@primary_page_flip.html [24]:
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Re-use i915 macros for checking PTEs (rev7)
== Series Details == Series: drm/i915: Re-use i915 macros for checking PTEs (rev7) URL : https://patchwork.freedesktop.org/series/97090/ State : warning == Summary == $ dim checkpatch origin/drm-tip 68b441f63a8e drm/i915: Re-use i915 macros for checking PTEs -:6: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #6: Certain gen8 ppgtt/gtt functions are using _PAGE_RW and _PAGE_PRESENT to check total: 0 errors, 1 warnings, 0 checks, 72 lines checked
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/adl_p: Add adl-p ddc pin mapping (rev2)
== Series Details == Series: drm/i915/adl_p: Add adl-p ddc pin mapping (rev2) URL : https://patchwork.freedesktop.org/series/97009/ State : success == Summary == CI Bug Log - changes from CI_DRM_10949_full -> Patchwork_21714_full Summary --- **SUCCESS** No regressions found. Participating hosts (10 -> 11) -- Additional (1): shard-rkl Known issues Here are the changes found in Patchwork_21714_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_eio@unwedge-stress: - shard-iclb: [PASS][1] -> [TIMEOUT][2] ([i915#2481] / [i915#3070]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10949/shard-iclb7/igt@gem_...@unwedge-stress.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21714/shard-iclb8/igt@gem_...@unwedge-stress.html * igt@gem_exec_capture@pi@vcs0: - shard-skl: [PASS][3] -> [INCOMPLETE][4] ([i915#4547]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10949/shard-skl6/igt@gem_exec_capture@p...@vcs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21714/shard-skl8/igt@gem_exec_capture@p...@vcs0.html * igt@gem_exec_fair@basic-deadline: - shard-kbl: [PASS][5] -> [FAIL][6] ([i915#2846]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10949/shard-kbl2/igt@gem_exec_f...@basic-deadline.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21714/shard-kbl6/igt@gem_exec_f...@basic-deadline.html - shard-skl: NOTRUN -> [FAIL][7] ([i915#2846]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21714/shard-skl10/igt@gem_exec_f...@basic-deadline.html - shard-glk: [PASS][8] -> [FAIL][9] ([i915#2846]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10949/shard-glk4/igt@gem_exec_f...@basic-deadline.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21714/shard-glk8/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-iclb: [PASS][10] -> [FAIL][11] ([i915#2842]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10949/shard-iclb3/igt@gem_exec_fair@basic-none-sh...@rcs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21714/shard-iclb3/igt@gem_exec_fair@basic-none-sh...@rcs0.html - shard-apl: [PASS][12] -> [SKIP][13] ([fdo#109271]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10949/shard-apl6/igt@gem_exec_fair@basic-none-sh...@rcs0.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21714/shard-apl2/igt@gem_exec_fair@basic-none-sh...@rcs0.html * igt@gem_exec_whisper@basic-contexts-forked: - shard-glk: [PASS][14] -> [DMESG-WARN][15] ([i915#118]) +1 similar issue [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10949/shard-glk1/igt@gem_exec_whis...@basic-contexts-forked.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21714/shard-glk9/igt@gem_exec_whis...@basic-contexts-forked.html * igt@gem_lmem_swapping@heavy-random: - shard-skl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4613]) +1 similar issue [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21714/shard-skl10/igt@gem_lmem_swapp...@heavy-random.html * igt@gem_lmem_swapping@heavy-verify-random: - shard-apl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21714/shard-apl3/igt@gem_lmem_swapp...@heavy-verify-random.html * igt@i915_suspend@fence-restore-tiled2untiled: - shard-kbl: NOTRUN -> [DMESG-WARN][18] ([i915#180]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21714/shard-kbl1/igt@i915_susp...@fence-restore-tiled2untiled.html * igt@kms_async_flips@alternate-sync-async-flip: - shard-skl: [PASS][19] -> [FAIL][20] ([i915#2521]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10949/shard-skl6/igt@kms_async_fl...@alternate-sync-async-flip.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21714/shard-skl6/igt@kms_async_fl...@alternate-sync-async-flip.html * igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-180: - shard-snb: [PASS][21] -> [SKIP][22] ([fdo#109271]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10949/shard-snb6/igt@kms_big...@linear-max-hw-stride-32bpp-rotate-180.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21714/shard-snb7/igt@kms_big...@linear-max-hw-stride-32bpp-rotate-180.html * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip: - shard-skl: NOTRUN -> [FAIL][23] ([i915#3743]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21714/shard-skl10/igt@kms_big...@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip:
Re: [Intel-gfx] [PATCH 14/14] drm/i915: Nuke pointless middle men for skl+ plane programming
On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> There is no real point in having this two stage
> skl_program_plane*() vs. skl_plane_update*() wrapper stuff.
> All we need to do is determine the correct color plane and
> we're done.
Reviewed-by: José Roberto de Souza
>
> Signed-off-by: Ville Syrjälä
> ---
> .../drm/i915/display/skl_universal_plane.c| 53 ++-
> 1 file changed, 17 insertions(+), 36 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 92270679a99c..de2708ac1802 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -1053,15 +1053,24 @@ static void icl_plane_csc_load_black(struct
> intel_plane *plane)
> intel_de_write_fw(i915, PLANE_CSC_POSTOFF(pipe, plane_id, 2), 0);
> }
>
> +static int skl_plane_color_plane(const struct intel_plane_state *plane_state)
> +{
> + /* Program the UV plane on planar master */
> + if (plane_state->planar_linked_plane && !plane_state->planar_slave)
> + return 1;
> + else
> + return 0;
> +}
> +
> static void
> -skl_program_plane_noarm(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state,
> - const struct intel_plane_state *plane_state,
> - int color_plane)
> +skl_plane_update_noarm(struct intel_plane *plane,
> +const struct intel_crtc_state *crtc_state,
> +const struct intel_plane_state *plane_state)
> {
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum plane_id plane_id = plane->id;
> enum pipe pipe = plane->pipe;
> + int color_plane = skl_plane_color_plane(plane_state);
> u32 stride = skl_plane_stride(plane_state, color_plane);
> const struct drm_framebuffer *fb = plane_state->hw.fb;
> int crtc_x = plane_state->uapi.dst.x1;
> @@ -1114,14 +1123,14 @@ skl_program_plane_noarm(struct intel_plane *plane,
> }
>
> static void
> -skl_program_plane_arm(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state,
> - const struct intel_plane_state *plane_state,
> - int color_plane)
> +skl_plane_update_arm(struct intel_plane *plane,
> + const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state)
> {
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum plane_id plane_id = plane->id;
> enum pipe pipe = plane->pipe;
> + int color_plane = skl_plane_color_plane(plane_state);
> u32 x = plane_state->view.color_plane[color_plane].x;
> u32 y = plane_state->view.color_plane[color_plane].y;
> u32 plane_color_ctl = 0;
> @@ -1202,34 +1211,6 @@ skl_plane_async_flip(struct intel_plane *plane,
> spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
> }
>
> -static void
> -skl_plane_update_noarm(struct intel_plane *plane,
> -const struct intel_crtc_state *crtc_state,
> -const struct intel_plane_state *plane_state)
> -{
> - int color_plane = 0;
> -
> - if (plane_state->planar_linked_plane && !plane_state->planar_slave)
> - /* Program the UV plane on planar master */
> - color_plane = 1;
> -
> - skl_program_plane_noarm(plane, crtc_state, plane_state, color_plane);
> -}
> -
> -static void
> -skl_plane_update_arm(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state,
> - const struct intel_plane_state *plane_state)
> -{
> - int color_plane = 0;
> -
> - if (plane_state->planar_linked_plane && !plane_state->planar_slave)
> - /* Program the UV plane on planar master */
> - color_plane = 1;
> -
> - skl_program_plane_arm(plane, crtc_state, plane_state, color_plane);
> -}
> -
> static bool intel_format_is_p01x(u32 format)
> {
> switch (format) {
Re: [Intel-gfx] [PATCH 13/14] drm/i915: Declutter color key register stuff
On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Add a few small helpers to calculate the color key register
> values. Cleans up skl_program_plane_arm() a bit.
Reviewed-by: José Roberto de Souza
>
> Signed-off-by: Ville Syrjälä
> ---
> .../drm/i915/display/skl_universal_plane.c| 45 +--
> 1 file changed, 32 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index c7de643d16dd..92270679a99c 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -1001,6 +1001,34 @@ static u32 skl_plane_aux_dist(const struct
> intel_plane_state *plane_state,
> return aux_dist;
> }
>
> +static u32 skl_plane_keyval(const struct intel_plane_state *plane_state)
> +{
> + const struct drm_intel_sprite_colorkey *key = _state->ckey;
> +
> + return key->min_value;
> +}
> +
> +static u32 skl_plane_keymax(const struct intel_plane_state *plane_state)
> +{
> + const struct drm_intel_sprite_colorkey *key = _state->ckey;
> + u8 alpha = plane_state->hw.alpha >> 8;
> +
> + return (key->max_value & 0xff) | PLANE_KEYMAX_ALPHA(alpha);
> +}
> +
> +static u32 skl_plane_keymsk(const struct intel_plane_state *plane_state)
> +{
> + const struct drm_intel_sprite_colorkey *key = _state->ckey;
> + u8 alpha = plane_state->hw.alpha >> 8;
> + u32 keymsk;
> +
> + keymsk = key->channel_mask & 0x7ff;
> + if (alpha < 0xff)
> + keymsk |= PLANE_KEYMSK_ALPHA_ENABLE;
> +
> + return keymsk;
> +}
> +
> static void icl_plane_csc_load_black(struct intel_plane *plane)
> {
> struct drm_i915_private *i915 = to_i915(plane->base.dev);
> @@ -1094,11 +1122,9 @@ skl_program_plane_arm(struct intel_plane *plane,
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> enum plane_id plane_id = plane->id;
> enum pipe pipe = plane->pipe;
> - const struct drm_intel_sprite_colorkey *key = _state->ckey;
> u32 x = plane_state->view.color_plane[color_plane].x;
> u32 y = plane_state->view.color_plane[color_plane].y;
> - u32 keymsk, keymax, plane_color_ctl = 0;
> - u8 alpha = plane_state->hw.alpha >> 8;
> + u32 plane_color_ctl = 0;
> u32 plane_ctl = plane_state->ctl;
> unsigned long irqflags;
>
> @@ -1108,18 +1134,11 @@ skl_program_plane_arm(struct intel_plane *plane,
> plane_color_ctl = plane_state->color_ctl |
> glk_plane_color_ctl_crtc(crtc_state);
>
> - keymax = (key->max_value & 0xff) | PLANE_KEYMAX_ALPHA(alpha);
> -
> - keymsk = key->channel_mask & 0x7ff;
> - if (alpha < 0xff)
> - keymsk |= PLANE_KEYMSK_ALPHA_ENABLE;
> -
> spin_lock_irqsave(_priv->uncore.lock, irqflags);
>
> - intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id),
> - key->min_value);
> - intel_de_write_fw(dev_priv, PLANE_KEYMSK(pipe, plane_id), keymsk);
> - intel_de_write_fw(dev_priv, PLANE_KEYMAX(pipe, plane_id), keymax);
> + intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id),
> skl_plane_keyval(plane_state));
> + intel_de_write_fw(dev_priv, PLANE_KEYMSK(pipe, plane_id),
> skl_plane_keymsk(plane_state));
> + intel_de_write_fw(dev_priv, PLANE_KEYMAX(pipe, plane_id),
> skl_plane_keymax(plane_state));
>
> intel_de_write_fw(dev_priv, PLANE_OFFSET(pipe, plane_id),
> PLANE_OFFSET_Y(y) | PLANE_OFFSET_X(x));
Re: [Intel-gfx] [PATCH 12/14] drm/i915: Extract skl_plane_aux_dist()
On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Extract the PLANE_AUX_DIST stuff into a small helper to
> dclutter skl_program_plane_arm() a bit.
Reviewed-by: José Roberto de Souza
>
> Signed-off-by: Ville Syrjälä
> ---
> .../drm/i915/display/skl_universal_plane.c| 35 ---
> 1 file changed, 23 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 79998eb67280..c7de643d16dd 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -981,6 +981,26 @@ static u32 skl_plane_surf(const struct intel_plane_state
> *plane_state,
> return plane_surf;
> }
>
> +static u32 skl_plane_aux_dist(const struct intel_plane_state *plane_state,
> + int color_plane)
> +{
> + struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
> + const struct drm_framebuffer *fb = plane_state->hw.fb;
> + int aux_plane = skl_main_to_aux_plane(fb, color_plane);
> + u32 aux_dist;
> +
> + if (!aux_plane)
> + return 0;
> +
> + aux_dist = skl_surf_address(plane_state, aux_plane) -
> + skl_surf_address(plane_state, color_plane);
> +
> + if (DISPLAY_VER(i915) < 12)
> + aux_dist |= PLANE_AUX_STRIDE(skl_plane_stride(plane_state,
> aux_plane));
> +
> + return aux_dist;
> +}
> +
> static void icl_plane_csc_load_black(struct intel_plane *plane)
> {
> struct drm_i915_private *i915 = to_i915(plane->base.dev);
> @@ -1075,11 +1095,9 @@ skl_program_plane_arm(struct intel_plane *plane,
> enum plane_id plane_id = plane->id;
> enum pipe pipe = plane->pipe;
> const struct drm_intel_sprite_colorkey *key = _state->ckey;
> - const struct drm_framebuffer *fb = plane_state->hw.fb;
> - int aux_plane = skl_main_to_aux_plane(fb, color_plane);
> u32 x = plane_state->view.color_plane[color_plane].x;
> u32 y = plane_state->view.color_plane[color_plane].y;
> - u32 keymsk, keymax, aux_dist = 0, plane_color_ctl = 0;
> + u32 keymsk, keymax, plane_color_ctl = 0;
> u8 alpha = plane_state->hw.alpha >> 8;
> u32 plane_ctl = plane_state->ctl;
> unsigned long irqflags;
> @@ -1096,14 +1114,6 @@ skl_program_plane_arm(struct intel_plane *plane,
> if (alpha < 0xff)
> keymsk |= PLANE_KEYMSK_ALPHA_ENABLE;
>
> - if (aux_plane) {
> - aux_dist = skl_surf_address(plane_state, aux_plane) -
> - skl_surf_address(plane_state, color_plane);
> -
> - if (DISPLAY_VER(dev_priv) < 12)
> - aux_dist |=
> PLANE_AUX_STRIDE(skl_plane_stride(plane_state, aux_plane));
> - }
> -
> spin_lock_irqsave(_priv->uncore.lock, irqflags);
>
> intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id),
> @@ -1114,7 +1124,8 @@ skl_program_plane_arm(struct intel_plane *plane,
> intel_de_write_fw(dev_priv, PLANE_OFFSET(pipe, plane_id),
> PLANE_OFFSET_Y(y) | PLANE_OFFSET_X(x));
>
> - intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id), aux_dist);
> + intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id),
> + skl_plane_aux_dist(plane_state, color_plane));
>
> if (DISPLAY_VER(dev_priv) < 11)
> intel_de_write_fw(dev_priv, PLANE_AUX_OFFSET(pipe, plane_id),
Re: [Intel-gfx] [PATCH 06/14] drm/i915: Use REG_BIT() & co. for universal plane bits
On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Polish the skl+ universal plane register defines by
> using REG_BIT() & co.
>
> The defines are also currently spread around in some
> semi-random fashion. Collect them up into one place.
>
> Signed-off-by: Ville Syrjälä
> ---
> .../drm/i915/display/skl_universal_plane.c| 36 ++--
> drivers/gpu/drm/i915/gvt/reg.h| 1 -
> drivers/gpu/drm/i915/i915_reg.h | 197 ++
> drivers/gpu/drm/i915/intel_pm.c | 12 +-
> 4 files changed, 135 insertions(+), 111 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 984bb35ecf06..79998eb67280 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -1037,11 +1037,12 @@ skl_program_plane_noarm(struct intel_plane *plane,
> if (plane_state->force_black)
> icl_plane_csc_load_black(plane);
>
> - intel_de_write_fw(dev_priv, PLANE_STRIDE(pipe, plane_id), stride);
> + intel_de_write_fw(dev_priv, PLANE_STRIDE(pipe, plane_id),
> + PLANE_STRIDE_(stride));
> intel_de_write_fw(dev_priv, PLANE_POS(pipe, plane_id),
> - (crtc_y << 16) | crtc_x);
> + PLANE_POS_Y(crtc_y) | PLANE_POS_X(crtc_x));
> intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id),
> - ((src_h - 1) << 16) | (src_w - 1));
> + PLANE_HEIGHT(src_h - 1) | PLANE_WIDTH(src_w - 1));
>
> if (intel_fb_is_rc_ccs_cc_modifier(fb->modifier)) {
> intel_de_write_fw(dev_priv, PLANE_CC_VAL(pipe, plane_id, 0),
> @@ -1100,7 +1101,7 @@ skl_program_plane_arm(struct intel_plane *plane,
> skl_surf_address(plane_state, color_plane);
>
> if (DISPLAY_VER(dev_priv) < 12)
> - aux_dist |= skl_plane_stride(plane_state, aux_plane);
> + aux_dist |=
> PLANE_AUX_STRIDE(skl_plane_stride(plane_state, aux_plane));
> }
>
> spin_lock_irqsave(_priv->uncore.lock, irqflags);
> @@ -,14 +1112,14 @@ skl_program_plane_arm(struct intel_plane *plane,
> intel_de_write_fw(dev_priv, PLANE_KEYMAX(pipe, plane_id), keymax);
>
> intel_de_write_fw(dev_priv, PLANE_OFFSET(pipe, plane_id),
> - (y << 16) | x);
> + PLANE_OFFSET_Y(y) | PLANE_OFFSET_X(x));
>
> intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id), aux_dist);
>
> if (DISPLAY_VER(dev_priv) < 11)
> intel_de_write_fw(dev_priv, PLANE_AUX_OFFSET(pipe, plane_id),
> - (plane_state->view.color_plane[1].y << 16) |
> -plane_state->view.color_plane[1].x);
> +
> PLANE_OFFSET_Y(plane_state->view.color_plane[1].y) |
> +
> PLANE_OFFSET_X(plane_state->view.color_plane[1].x));
>
> if (DISPLAY_VER(dev_priv) >= 10)
> intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id),
> plane_color_ctl);
> @@ -2262,16 +2263,17 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
> val = intel_de_read(dev_priv, PLANE_CTL(pipe, plane_id));
>
> if (DISPLAY_VER(dev_priv) >= 11)
> - pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK;
> + pixel_format = val & PLANE_CTL_FORMAT_MASK_ICL;
Most of our platform bits definition follows _.
Other than that the idea looks good to me.
> else
> - pixel_format = val & PLANE_CTL_FORMAT_MASK;
> + pixel_format = val & PLANE_CTL_FORMAT_MASK_SKL;
>
> if (DISPLAY_VER(dev_priv) >= 10) {
> - alpha = intel_de_read(dev_priv,
> - PLANE_COLOR_CTL(pipe, plane_id));
> - alpha &= PLANE_COLOR_ALPHA_MASK;
> + u32 color_ctl;
> +
> + color_ctl = intel_de_read(dev_priv, PLANE_COLOR_CTL(pipe,
> plane_id));
> + alpha = REG_FIELD_GET(PLANE_COLOR_ALPHA_MASK, color_ctl);
> } else {
> - alpha = val & PLANE_CTL_ALPHA_MASK;
> + alpha = REG_FIELD_GET(PLANE_CTL_ALPHA_MASK, val);
> }
>
> fourcc = skl_format_to_fourcc(pixel_format,
> @@ -2335,19 +2337,19 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
> if (drm_rotation_90_or_270(plane_config->rotation))
> goto error;
>
> - base = intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) & 0xf000;
> + base = intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) &
> PLANE_SURF_ADDR_MASK;
> plane_config->base = base;
>
> offset = intel_de_read(dev_priv, PLANE_OFFSET(pipe, plane_id));
>
> val = intel_de_read(dev_priv, PLANE_SIZE(pipe, plane_id));
> - fb->height = ((val >> 16) & 0x) + 1;
> -
Re: [Intel-gfx] [PATCH 03/14] drm/i915: Get rid of the "sizes are 0 based" stuff
On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Replace the "sizes are 0 based" stuff with just straight
> up -1 where needed. Less confusing all around.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_sprite.c | 26 ---
> .../drm/i915/display/skl_universal_plane.c| 6 +
> 2 files changed, 6 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
> b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 1b99a9501a45..2067a7bca4a8 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -431,10 +431,6 @@ vlv_sprite_update_noarm(struct intel_plane *plane,
> u32 crtc_h = drm_rect_height(_state->uapi.dst);
> unsigned long irqflags;
>
> - /* Sizes are 0 based */
In my opinion at least this comment should stay, helps understand why the -1.
> - crtc_w--;
> - crtc_h--;
> -
> spin_lock_irqsave(_priv->uncore.lock, irqflags);
>
> intel_de_write_fw(dev_priv, SPSTRIDE(pipe, plane_id),
> @@ -442,7 +438,7 @@ vlv_sprite_update_noarm(struct intel_plane *plane,
> intel_de_write_fw(dev_priv, SPPOS(pipe, plane_id),
> (crtc_y << 16) | crtc_x);
> intel_de_write_fw(dev_priv, SPSIZE(pipe, plane_id),
> - (crtc_h << 16) | crtc_w);
> + ((crtc_h - 1) << 16) | (crtc_w - 1));
>
> spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
> }
> @@ -866,21 +862,15 @@ ivb_sprite_update_noarm(struct intel_plane *plane,
> u32 sprscale = 0;
> unsigned long irqflags;
>
> - /* Sizes are 0 based */
> - src_w--;
> - src_h--;
> - crtc_w--;
> - crtc_h--;
> -
> if (crtc_w != src_w || crtc_h != src_h)
> - sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
> + sprscale = SPRITE_SCALE_ENABLE | ((src_w - 1) << 16) | (src_h -
> 1);
>
> spin_lock_irqsave(_priv->uncore.lock, irqflags);
>
> intel_de_write_fw(dev_priv, SPRSTRIDE(pipe),
> plane_state->view.color_plane[0].mapping_stride);
> intel_de_write_fw(dev_priv, SPRPOS(pipe), (crtc_y << 16) | crtc_x);
> - intel_de_write_fw(dev_priv, SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
> + intel_de_write_fw(dev_priv, SPRSIZE(pipe), ((crtc_h - 1) << 16) |
> (crtc_w - 1));
> if (IS_IVYBRIDGE(dev_priv))
> intel_de_write_fw(dev_priv, SPRSCALE(pipe), sprscale);
>
> @@ -1208,21 +1198,15 @@ g4x_sprite_update_noarm(struct intel_plane *plane,
> u32 dvsscale = 0;
> unsigned long irqflags;
>
> - /* Sizes are 0 based */
> - src_w--;
> - src_h--;
> - crtc_w--;
> - crtc_h--;
> -
> if (crtc_w != src_w || crtc_h != src_h)
> - dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
> + dvsscale = DVS_SCALE_ENABLE | ((src_w - 1) << 16) | (src_h - 1);
>
> spin_lock_irqsave(_priv->uncore.lock, irqflags);
>
> intel_de_write_fw(dev_priv, DVSSTRIDE(pipe),
> plane_state->view.color_plane[0].mapping_stride);
> intel_de_write_fw(dev_priv, DVSPOS(pipe), (crtc_y << 16) | crtc_x);
> - intel_de_write_fw(dev_priv, DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
> + intel_de_write_fw(dev_priv, DVSSIZE(pipe), ((crtc_h - 1) << 16) |
> (crtc_w - 1));
> intel_de_write_fw(dev_priv, DVSSCALE(pipe), dvsscale);
>
> spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 9ff24a0e79b4..09948922016b 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -1022,10 +1022,6 @@ skl_program_plane_noarm(struct intel_plane *plane,
> u32 src_h = drm_rect_height(_state->uapi.src) >> 16;
> unsigned long irqflags;
>
> - /* Sizes are 0 based */
> - src_w--;
> - src_h--;
> -
> /* The scaler will handle the output position */
> if (plane_state->scaler_id >= 0) {
> crtc_x = 0;
> @@ -1045,7 +1041,7 @@ skl_program_plane_noarm(struct intel_plane *plane,
> intel_de_write_fw(dev_priv, PLANE_POS(pipe, plane_id),
> (crtc_y << 16) | crtc_x);
> intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id),
> - (src_h << 16) | src_w);
> + ((src_h - 1) << 16) | (src_w - 1));
>
> if (intel_fb_is_rc_ccs_cc_modifier(fb->modifier)) {
> intel_de_write_fw(dev_priv, PLANE_CC_VAL(pipe, plane_id, 0),
Re: [Intel-gfx] [PATCH 05/14] drm/i915: Rename PLANE_CUS_CTL Y plane bits
On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Rename the PLANE_CUS_CTL Y plane selection bits to actually
> say "Y plane".
>
Reviewed-by: José Roberto de Souza
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 8
> drivers/gpu/drm/i915/i915_reg.h | 8
> 2 files changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index badf035efaeb..726c1552c9bf 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5159,13 +5159,13 @@ static int icl_check_nv12_planes(struct
> intel_crtc_state *crtc_state)
>
> if (icl_is_hdr_plane(dev_priv, plane->id)) {
> if (linked->id == PLANE_SPRITE5)
> - plane_state->cus_ctl |= PLANE_CUS_PLANE_7;
> + plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL;
> else if (linked->id == PLANE_SPRITE4)
> - plane_state->cus_ctl |= PLANE_CUS_PLANE_6;
> + plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL;
> else if (linked->id == PLANE_SPRITE3)
> - plane_state->cus_ctl |= PLANE_CUS_PLANE_5_RKL;
> + plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL;
> else if (linked->id == PLANE_SPRITE2)
> - plane_state->cus_ctl |= PLANE_CUS_PLANE_4_RKL;
> + plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL;
> else
> MISSING_CASE(linked->id);
> }
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 6066b1e2763c..4b2bc17d0235 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7328,10 +7328,10 @@ enum {
> #define _PLANE_CUS_CTL_1_A 0x701c8
> #define _PLANE_CUS_CTL_2_A 0x702c8
> #define PLANE_CUS_ENABLE(1 << 31)
> -#define PLANE_CUS_PLANE_4_RKL (0 << 30)
> -#define PLANE_CUS_PLANE_5_RKL (1 << 30)
> -#define PLANE_CUS_PLANE_6 (0 << 30)
> -#define PLANE_CUS_PLANE_7 (1 << 30)
> +#define PLANE_CUS_Y_PLANE_4_RKL (0 << 30)
> +#define PLANE_CUS_Y_PLANE_5_RKL (1 << 30)
> +#define PLANE_CUS_Y_PLANE_6_ICL (0 << 30)
> +#define PLANE_CUS_Y_PLANE_7_ICL (1 << 30)
> #define PLANE_CUS_HPHASE_SIGN_NEGATIVE (1 << 19)
> #define PLANE_CUS_HPHASE_0 (0 << 16)
> #define PLANE_CUS_HPHASE_0_25 (1 << 16)
Re: [Intel-gfx] [PATCH 01/14] drm/i915: Get rid of the 64bit PLANE_CC_VAL mmio
On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Let's just stick to 32bit mmio accesses so we can get rid
> of the bare "uncore" reg access in display code. The register
> are defined as 32bit in the spec anyway.
>
> We could define a 64bit "de" variant I suppose, but doesn't
> really make much sense just for this one case, and when we
> start to use the DSB for this stuff we'd also need another
> 64bit variant for that. Just easier to do 32bit always.
>
> While at it we can reorder stuff a bit so that we write the
> registers in order of increasing offset (more or less).
Reviewed-by: José Roberto de Souza
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/skl_universal_plane.c | 11 +++
> drivers/gpu/drm/i915/i915_reg.h| 12 ++--
> 2 files changed, 13 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 28890876bdeb..845b99844ec6 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -1047,6 +1047,13 @@ skl_program_plane_noarm(struct intel_plane *plane,
> intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id),
> (src_h << 16) | src_w);
>
> + if (intel_fb_is_rc_ccs_cc_modifier(fb->modifier)) {
> + intel_de_write_fw(dev_priv, PLANE_CC_VAL(pipe, plane_id, 0),
> + lower_32_bits(plane_state->ccval));
> + intel_de_write_fw(dev_priv, PLANE_CC_VAL(pipe, plane_id, 1),
> + upper_32_bits(plane_state->ccval));
> + }
> +
> if (icl_is_hdr_plane(dev_priv, plane_id))
> intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id),
> plane_state->cus_ctl);
> @@ -1054,10 +1061,6 @@ skl_program_plane_noarm(struct intel_plane *plane,
> if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
> icl_program_input_csc(plane, crtc_state, plane_state);
>
> - if (intel_fb_is_rc_ccs_cc_modifier(fb->modifier))
> - intel_uncore_write64_fw(_priv->uncore,
> - PLANE_CC_VAL(pipe, plane_id),
> plane_state->ccval);
> -
> skl_write_plane_wm(plane, crtc_state);
>
> intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state,
> color_plane);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3450818802c2..3c0471f20e53 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7363,12 +7363,12 @@ enum {
> #define _PLANE_NV12_BUF_CFG_1_A 0x70278
> #define _PLANE_NV12_BUF_CFG_2_A 0x70378
>
> -#define _PLANE_CC_VAL_1_B0x711b4
> -#define _PLANE_CC_VAL_2_B0x712b4
> -#define _PLANE_CC_VAL_1(pipe)_PIPE(pipe, _PLANE_CC_VAL_1_A,
> _PLANE_CC_VAL_1_B)
> -#define _PLANE_CC_VAL_2(pipe)_PIPE(pipe, _PLANE_CC_VAL_2_A,
> _PLANE_CC_VAL_2_B)
> -#define PLANE_CC_VAL(pipe, plane)\
> - _MMIO_PLANE(plane, _PLANE_CC_VAL_1(pipe), _PLANE_CC_VAL_2(pipe))
> +#define _PLANE_CC_VAL_1_B0x711b4
> +#define _PLANE_CC_VAL_2_B0x712b4
> +#define _PLANE_CC_VAL_1(pipe, dw)(_PIPE(pipe, _PLANE_CC_VAL_1_A,
> _PLANE_CC_VAL_1_B) + (dw) * 4)
> +#define _PLANE_CC_VAL_2(pipe, dw)(_PIPE(pipe, _PLANE_CC_VAL_2_A,
> _PLANE_CC_VAL_2_B) + (dw) * 4)
> +#define PLANE_CC_VAL(pipe, plane, dw) \
> + _MMIO_PLANE((plane), _PLANE_CC_VAL_1((pipe), (dw)),
> _PLANE_CC_VAL_2((pipe), (dw)))
>
> /* Input CSC Register Definitions */
> #define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0
Re: [Intel-gfx] [PATCH 02/14] drm/i915: Rename plane YUV order bits
On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Rename the YUV byte order bits to be a bit more consistent.
Why rename bits not used? Would be better already nuke it.
Anyways up to you.
Reviewed-by: José Roberto de Souza
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/skl_universal_plane.c | 8
> drivers/gpu/drm/i915/i915_reg.h| 14 +++---
> 2 files changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 845b99844ec6..9ff24a0e79b4 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -672,13 +672,13 @@ static u32 skl_plane_ctl_format(u32 pixel_format)
> case DRM_FORMAT_XYUV:
> return PLANE_CTL_FORMAT_XYUV;
> case DRM_FORMAT_YUYV:
> - return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
> + return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_YUYV;
> case DRM_FORMAT_YVYU:
> - return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
> + return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_YVYU;
> case DRM_FORMAT_UYVY:
> - return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
> + return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_UYVY;
> case DRM_FORMAT_VYUY:
> - return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
> + return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_VYUY;
> case DRM_FORMAT_NV12:
> return PLANE_CTL_FORMAT_NV12;
> case DRM_FORMAT_P010:
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3c0471f20e53..02d8db03c0bf 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6966,7 +6966,7 @@ enum {
> #define DVS_SOURCE_KEY (1 << 22)
> #define DVS_RGB_ORDER_XBGR (1 << 20)
> #define DVS_YUV_FORMAT_BT709 (1 << 18)
> -#define DVS_YUV_BYTE_ORDER_MASK (3 << 16)
> +#define DVS_YUV_ORDER_MASK (3 << 16)
> #define DVS_YUV_ORDER_YUYV (0 << 16)
> #define DVS_YUV_ORDER_UYVY (1 << 16)
> #define DVS_YUV_ORDER_YVYU (2 << 16)
> @@ -7045,7 +7045,7 @@ enum {
> #define SPRITE_RGB_ORDER_RGBX (1 << 20) /* only for 888 and
> 161616 */
> #define SPRITE_YUV_TO_RGB_CSC_DISABLE (1 << 19)
> #define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709 (1 << 18) /* 0 is BT601 */
> -#define SPRITE_YUV_BYTE_ORDER_MASK (3 << 16)
> +#define SPRITE_YUV_ORDER_MASK (3 << 16)
> #define SPRITE_YUV_ORDER_YUYV (0 << 16)
> #define SPRITE_YUV_ORDER_UYVY (1 << 16)
> #define SPRITE_YUV_ORDER_YVYU (2 << 16)
> @@ -7130,7 +7130,7 @@ enum {
> #define SP_ALPHA_PREMULTIPLY (1 << 23) /* CHV pipe B */
> #define SP_SOURCE_KEY (1 << 22)
> #define SP_YUV_FORMAT_BT709(1 << 18)
> -#define SP_YUV_BYTE_ORDER_MASK (3 << 16)
> +#define SP_YUV_ORDER_MASK (3 << 16)
> #define SP_YUV_ORDER_YUYV (0 << 16)
> #define SP_YUV_ORDER_UYVY (1 << 16)
> #define SP_YUV_ORDER_YVYU (2 << 16)
> @@ -7271,10 +7271,10 @@ enum {
> #define PLANE_CTL_YUV420_Y_PLANE (1 << 19)
> #define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 (1 << 18)
> #define PLANE_CTL_YUV422_ORDER_MASK(0x3 << 16)
> -#define PLANE_CTL_YUV422_YUYV (0 << 16)
> -#define PLANE_CTL_YUV422_UYVY (1 << 16)
> -#define PLANE_CTL_YUV422_YVYU (2 << 16)
> -#define PLANE_CTL_YUV422_VYUY (3 << 16)
> +#define PLANE_CTL_YUV422_ORDER_YUYV(0 << 16)
> +#define PLANE_CTL_YUV422_ORDER_UYVY(1 << 16)
> +#define PLANE_CTL_YUV422_ORDER_YVYU(2 << 16)
> +#define PLANE_CTL_YUV422_ORDER_VYUY(3 << 16)
> #define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE (1 << 15)
> #define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14)
> #define PLANE_CTL_CLEAR_COLOR_DISABLE (1 << 13) /* TGL+ */
[Intel-gfx] [PATCH 09/14] drm/i915: Clean up vlv/chv sprite plane registers
From: Ville Syrjälä
Use REG_BIT() & co. to polish the vlv/chv sprite plane registers.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_sprite.c | 9 +-
drivers/gpu/drm/i915/i915_reg.h | 103
2 files changed, 70 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index 70083d04a9fd..eb9ce96c030f 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -313,7 +313,7 @@ static u32 vlv_sprite_ctl_crtc(const struct
intel_crtc_state *crtc_state)
u32 sprctl = 0;
if (crtc_state->gamma_enable)
- sprctl |= SP_GAMMA_ENABLE;
+ sprctl |= SP_PIPE_GAMMA_ENABLE;
return sprctl;
}
@@ -436,9 +436,9 @@ vlv_sprite_update_noarm(struct intel_plane *plane,
intel_de_write_fw(dev_priv, SPSTRIDE(pipe, plane_id),
plane_state->view.color_plane[0].mapping_stride);
intel_de_write_fw(dev_priv, SPPOS(pipe, plane_id),
- (crtc_y << 16) | crtc_x);
+ SP_POS_Y(crtc_y) | SP_POS_X(crtc_x));
intel_de_write_fw(dev_priv, SPSIZE(pipe, plane_id),
- ((crtc_h - 1) << 16) | (crtc_w - 1));
+ SP_HEIGHT(crtc_h - 1) | SP_WIDTH(crtc_w - 1));
spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
}
@@ -479,7 +479,8 @@ vlv_sprite_update_arm(struct intel_plane *plane,
intel_de_write_fw(dev_priv, SPCONSTALPHA(pipe, plane_id), 0);
intel_de_write_fw(dev_priv, SPLINOFF(pipe, plane_id), linear_offset);
- intel_de_write_fw(dev_priv, SPTILEOFF(pipe, plane_id), (y << 16) | x);
+ intel_de_write_fw(dev_priv, SPTILEOFF(pipe, plane_id),
+ SP_OFFSET_Y(y) | SP_OFFSET_X(x));
/*
* The control register self-arms if the plane was previously
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0bd47a929f5d..4d61e7f2ee7c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7146,48 +7146,67 @@ enum {
#define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
#define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
-#define SP_ENABLE(1 << 31)
-#define SP_GAMMA_ENABLE (1 << 30)
-#define SP_PIXFORMAT_MASK(0xf << 26)
-#define SP_FORMAT_YUV422 (0x0 << 26)
-#define SP_FORMAT_8BPP (0x2 << 26)
-#define SP_FORMAT_BGR565 (0x5 << 26)
-#define SP_FORMAT_BGRX (0x6 << 26)
-#define SP_FORMAT_BGRA (0x7 << 26)
-#define SP_FORMAT_RGBX1010102(0x8 << 26)
-#define SP_FORMAT_RGBA1010102(0x9 << 26)
-#define SP_FORMAT_BGRX1010102(0xa << 26) /* CHV pipe B */
-#define SP_FORMAT_BGRA1010102(0xb << 26) /* CHV pipe B */
-#define SP_FORMAT_RGBX (0xe << 26)
-#define SP_FORMAT_RGBA (0xf << 26)
-#define SP_ALPHA_PREMULTIPLY (1 << 23) /* CHV pipe B */
-#define SP_SOURCE_KEY(1 << 22)
-#define SP_YUV_FORMAT_BT709 (1 << 18)
-#define SP_YUV_ORDER_MASK(3 << 16)
-#define SP_YUV_ORDER_YUYV(0 << 16)
-#define SP_YUV_ORDER_UYVY(1 << 16)
-#define SP_YUV_ORDER_YVYU(2 << 16)
-#define SP_YUV_ORDER_VYUY(3 << 16)
-#define SP_ROTATE_180(1 << 15)
-#define SP_TILED (1 << 10)
-#define SP_MIRROR(1 << 8) /* CHV pipe B */
+#define SP_ENABLEREG_BIT(31)
+#define SP_PIPE_GAMMA_ENABLE REG_BIT(30)
+#define SP_FORMAT_MASK REG_GENMASK(29, 26)
+#define SP_FORMAT_YUV422 REG_FIELD_PREP(SP_FORMAT_MASK, 0)
+#define SP_FORMAT_8BPP REG_FIELD_PREP(SP_FORMAT_MASK, 2)
+#define SP_FORMAT_BGR565 REG_FIELD_PREP(SP_FORMAT_MASK, 5)
+#define SP_FORMAT_BGRX REG_FIELD_PREP(SP_FORMAT_MASK, 6)
+#define SP_FORMAT_BGRA REG_FIELD_PREP(SP_FORMAT_MASK, 7)
+#define SP_FORMAT_RGBX1010102REG_FIELD_PREP(SP_FORMAT_MASK,
8)
+#define SP_FORMAT_RGBA1010102REG_FIELD_PREP(SP_FORMAT_MASK,
9)
+#define SP_FORMAT_BGRX1010102REG_FIELD_PREP(SP_FORMAT_MASK,
10) /* CHV pipe B */
+#define SP_FORMAT_BGRA1010102REG_FIELD_PREP(SP_FORMAT_MASK,
11) /* CHV pipe B */
+#define SP_FORMAT_RGBX REG_FIELD_PREP(SP_FORMAT_MASK, 14)
+#define SP_FORMAT_RGBA REG_FIELD_PREP(SP_FORMAT_MASK, 15)
+#define SP_ALPHA_PREMULTIPLY REG_BIT(23) /* CHV pipe B */
+#define SP_SOURCE_KEYREG_BIT(22)
+#define SP_YUV_FORMAT_BT709 REG_BIT(18)
+#define SP_YUV_ORDER_MASK
Re: [Intel-gfx] [PATCH v2 10/10] drm/i915/display: stop including i915_drv.h from intel_display_types.h
On Wed, Dec 01, 2021 at 03:57:12PM +0200, Jani Nikula wrote:
> Break the dependency on i915_drv.h.
>
> Signed-off-by: Jani Nikula
Looks reasonable.
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_display_types.h| 9 -
> drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c | 1 +
> drivers/gpu/drm/i915/display/intel_dp_link_training.c | 2 +-
> drivers/gpu/drm/i915/display/intel_dsi.c | 2 ++
> drivers/gpu/drm/i915/display/intel_fb.c | 1 +
> drivers/gpu/drm/i915/display/intel_fb_pin.c | 10 +-
> drivers/gpu/drm/i915/display/intel_plane_initial.c| 5 +++--
> drivers/gpu/drm/i915/display/intel_quirks.c | 1 +
> 8 files changed, 22 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index f6e76b4d377d..974af6c01cca 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -36,6 +36,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -46,13 +47,19 @@
> #include
> #include
>
> -#include "i915_drv.h"
> +#include "i915_vma.h"
> +#include "i915_vma_types.h"
> +#include "intel_bios.h"
> +#include "intel_display.h"
> +#include "intel_display_power.h"
> +#include "intel_dpll_mgr.h"
> #include "intel_pm_types.h"
>
> struct drm_printer;
> struct __intel_global_objs_state;
> struct intel_ddi_buf_trans;
> struct intel_fbc;
> +struct intel_connector;
>
> /*
> * Display related stuff
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> index 62c112daacf2..97cf3cac0105 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> @@ -34,6 +34,7 @@
> * for some reason.
> */
>
> +#include "i915_drv.h"
> #include "intel_backlight.h"
> #include "intel_display_types.h"
> #include "intel_dp.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index e264467de8ed..9451f336f28f 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -21,11 +21,11 @@
> * IN THE SOFTWARE.
> */
>
> +#include "i915_drv.h"
> #include "intel_display_types.h"
> #include "intel_dp.h"
> #include "intel_dp_link_training.h"
>
> -
> static void intel_dp_reset_lttpr_common_caps(struct intel_dp *intel_dp)
> {
> memset(intel_dp->lttpr_common_caps, 0,
> sizeof(intel_dp->lttpr_common_caps));
> diff --git a/drivers/gpu/drm/i915/display/intel_dsi.c
> b/drivers/gpu/drm/i915/display/intel_dsi.c
> index 6b0301ba046e..a50422e03a7e 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsi.c
> @@ -4,6 +4,8 @@
> */
>
> #include
> +
> +#include "i915_drv.h"
> #include "intel_dsi.h"
> #include "intel_panel.h"
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
> b/drivers/gpu/drm/i915/display/intel_fb.c
> index 99769132c35b..23cfe2e5ce2a 100644
> --- a/drivers/gpu/drm/i915/display/intel_fb.c
> +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> @@ -6,6 +6,7 @@
> #include
> #include
>
> +#include "i915_drv.h"
> #include "intel_display.h"
> #include "intel_display_types.h"
> #include "intel_dpt.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c
> b/drivers/gpu/drm/i915/display/intel_fb_pin.c
> index 3b20f69e0240..31c15e5fca95 100644
> --- a/drivers/gpu/drm/i915/display/intel_fb_pin.c
> +++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c
> @@ -7,13 +7,13 @@
> * DOC: display pinning helpers
> */
>
> -#include "intel_display_types.h"
> -#include "intel_fb_pin.h"
> -#include "intel_fb.h"
> +#include "gem/i915_gem_object.h"
>
> +#include "i915_drv.h"
> +#include "intel_display_types.h"
> #include "intel_dpt.h"
> -
> -#include "gem/i915_gem_object.h"
> +#include "intel_fb.h"
> +#include "intel_fb_pin.h"
>
> static struct i915_vma *
> intel_pin_fb_obj_dpt(struct drm_framebuffer *fb,
> diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c
> b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> index dcd698a02da2..01ce1d72297f 100644
> --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
> +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> @@ -3,11 +3,12 @@
> * Copyright © 2021 Intel Corporation
> */
>
> -#include "intel_display_types.h"
> -#include "intel_plane_initial.h"
> +#include "i915_drv.h"
> #include "intel_atomic_plane.h"
> #include "intel_display.h"
> +#include "intel_display_types.h"
> #include "intel_fb.h"
> +#include "intel_plane_initial.h"
>
> static bool
> intel_reuse_initial_plane_obj(struct drm_i915_private *i915,
> diff --git
Re: [Intel-gfx] [PATCH] drm/i915: Add PLANE_CUS_CTL restriction in max_width
On Wed, Dec 01, 2021 at 09:17:27AM +0530, Vidya Srinivas wrote:
> PLANE_CUS_CTL has a restriction of 4096 width even though
> PLANE_SIZE and scaler size registers supports max 5120.
> Take care of this restriction in max_width.
>
> Without this patch, when 5k content is sent on HDR plane
> with NV12 content, FIFO underrun is seen and screen blanks
> out.
>
> v2: Addressed review comments from Ville. Added separate
> functions for max_width - for HDR and SDR
>
> v3: Addressed review comments from Ville. Changed names of
> HDR and SDR max_width functions to icl_hdr_plane_max_width
> and icl_sdr_plane_max_width
>
> v4: Fixed paranthesis alignment. No code change
>
> Reviewed-by: Ville Syrjälä
> Signed-off-by: Vidya Srinivas
> Signed-off-by: Yashashvi Shantam
Hmm. What's this extra sob doing here?
> ---
> .../drm/i915/display/skl_universal_plane.c| 21 +++
> 1 file changed, 17 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 28890876bdeb..e717eb58b105 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -420,9 +420,19 @@ static int icl_plane_min_width(const struct
> drm_framebuffer *fb,
> }
> }
>
> -static int icl_plane_max_width(const struct drm_framebuffer *fb,
> -int color_plane,
> -unsigned int rotation)
> +static int icl_hdr_plane_max_width(const struct drm_framebuffer *fb,
> + int color_plane,
> + unsigned int rotation)
> +{
> + if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
> + return 4096;
> + else
> + return 5120;
> +}
> +
> +static int icl_sdr_plane_max_width(const struct drm_framebuffer *fb,
> + int color_plane,
> + unsigned int rotation)
> {
> return 5120;
> }
> @@ -2108,7 +2118,10 @@ skl_universal_plane_create(struct drm_i915_private
> *dev_priv,
>
> if (DISPLAY_VER(dev_priv) >= 11) {
> plane->min_width = icl_plane_min_width;
> - plane->max_width = icl_plane_max_width;
> + if (icl_is_hdr_plane(dev_priv, plane_id))
> + plane->max_width = icl_hdr_plane_max_width;
> + else
> + plane->max_width = icl_sdr_plane_max_width;
> plane->max_height = icl_plane_max_height;
> plane->min_cdclk = icl_plane_min_cdclk;
> } else if (DISPLAY_VER(dev_priv) >= 10) {
> --
> 2.33.0
--
Ville Syrjälä
Intel
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Add workaround numbers to GEN7_COMMON_SLICE_CHICKEN1 whitelisting
On Fri, Nov 19, 2021 at 06:09:31AM -0800, José Roberto de Souza wrote: > Those two workarounds needs to be implemented in UMD, KMD only needs > to whitelist the registers, so here only adding the workaround number > to facilitate future workaroud table checks. > > Signed-off-by: José Roberto de Souza Reviewed-by: Matt Atwood > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 +- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c > b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index cd2935b9e7c81..c3211325c2d3e 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -1869,7 +1869,11 @@ static void tgl_whitelist_build(struct intel_engine_cs > *engine) > RING_FORCE_TO_NONPRIV_ACCESS_RD | > RING_FORCE_TO_NONPRIV_RANGE_4); > > - /* Wa_1808121037:tgl */ > + /* > + * Wa_1808121037:tgl > + * Wa_14012131227:dg1 > + * Wa_1508744258:tgl,rkl,dg1,adl-s,adl-p > + */ > whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1); > > /* Wa_1806527549:tgl */ > -- > 2.33.1 >
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Skip remap_io_mapping() for non-x86 platforms (rev4)
== Series Details == Series: drm/i915: Skip remap_io_mapping() for non-x86 platforms (rev4) URL : https://patchwork.freedesktop.org/series/96855/ State : success == Summary == CI Bug Log - changes from CI_DRM_10949_full -> Patchwork_21713_full Summary --- **SUCCESS** No regressions found. Participating hosts (10 -> 11) -- Additional (1): shard-rkl Known issues Here are the changes found in Patchwork_21713_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_basic@create-fd-close: - shard-skl: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10949/shard-skl9/igt@gem_ba...@create-fd-close.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21713/shard-skl7/igt@gem_ba...@create-fd-close.html * igt@gem_ctx_isolation@preservation-s3@rcs0: - shard-apl: [PASS][3] -> [DMESG-WARN][4] ([i915#180]) +2 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10949/shard-apl8/igt@gem_ctx_isolation@preservation...@rcs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21713/shard-apl6/igt@gem_ctx_isolation@preservation...@rcs0.html * igt@gem_ctx_isolation@preservation-s3@vcs0: - shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([i915#180]) +8 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10949/shard-kbl4/igt@gem_ctx_isolation@preservation...@vcs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21713/shard-kbl6/igt@gem_ctx_isolation@preservation...@vcs0.html * igt@gem_exec_capture@pi@vcs0: - shard-skl: [PASS][7] -> [INCOMPLETE][8] ([i915#4547]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10949/shard-skl6/igt@gem_exec_capture@p...@vcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21713/shard-skl1/igt@gem_exec_capture@p...@vcs0.html * igt@gem_exec_fair@basic-deadline: - shard-skl: NOTRUN -> [FAIL][9] ([i915#2846]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21713/shard-skl6/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-none@vcs1: - shard-iclb: NOTRUN -> [FAIL][10] ([i915#2842]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21713/shard-iclb4/igt@gem_exec_fair@basic-n...@vcs1.html * igt@gem_exec_fair@basic-none@vecs0: - shard-apl: [PASS][11] -> [FAIL][12] ([i915#2842]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10949/shard-apl1/igt@gem_exec_fair@basic-n...@vecs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21713/shard-apl4/igt@gem_exec_fair@basic-n...@vecs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: [PASS][13] -> [FAIL][14] ([i915#2842]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10949/shard-glk1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21713/shard-glk9/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-iclb: [PASS][15] -> [FAIL][16] ([i915#2842]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10949/shard-iclb3/igt@gem_exec_fair@basic-pace-s...@rcs0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21713/shard-iclb8/igt@gem_exec_fair@basic-pace-s...@rcs0.html * igt@gem_lmem_swapping@heavy-verify-random: - shard-skl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613]) +2 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21713/shard-skl1/igt@gem_lmem_swapp...@heavy-verify-random.html - shard-apl: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#4613]) +1 similar issue [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21713/shard-apl4/igt@gem_lmem_swapp...@heavy-verify-random.html * igt@i915_suspend@debugfs-reader: - shard-skl: [PASS][19] -> [INCOMPLETE][20] ([i915#198]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10949/shard-skl8/igt@i915_susp...@debugfs-reader.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21713/shard-skl7/igt@i915_susp...@debugfs-reader.html * igt@i915_suspend@fence-restore-tiled2untiled: - shard-kbl: NOTRUN -> [DMESG-WARN][21] ([i915#180]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21713/shard-kbl1/igt@i915_susp...@fence-restore-tiled2untiled.html * igt@kms_async_flips@alternate-sync-async-flip: - shard-skl: [PASS][22] -> [FAIL][23] ([i915#2521]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10949/shard-skl6/igt@kms_async_fl...@alternate-sync-async-flip.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21713/shard-skl8/igt@kms_async_fl...@alternate-sync-async-flip.html *
[Intel-gfx] ✓ Fi.CI.IGT: success for Introduce Raptor Lake S (rev4)
== Series Details == Series: Introduce Raptor Lake S (rev4) URL : https://patchwork.freedesktop.org/series/96869/ State : success == Summary == CI Bug Log - changes from CI_DRM_10949_full -> Patchwork_21712_full Summary --- **SUCCESS** No regressions found. Participating hosts (10 -> 11) -- Additional (1): shard-rkl Known issues Here are the changes found in Patchwork_21712_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@preservation-s3@bcs0: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([i915#180]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10949/shard-apl8/igt@gem_ctx_isolation@preservation...@bcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21712/shard-apl4/igt@gem_ctx_isolation@preservation...@bcs0.html * igt@gem_exec_capture@pi@rcs0: - shard-skl: [PASS][3] -> [INCOMPLETE][4] ([i915#4547]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10949/shard-skl6/igt@gem_exec_capture@p...@rcs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21712/shard-skl4/igt@gem_exec_capture@p...@rcs0.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-apl: [PASS][5] -> [SKIP][6] ([fdo#109271]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10949/shard-apl6/igt@gem_exec_fair@basic-none-sh...@rcs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21712/shard-apl2/igt@gem_exec_fair@basic-none-sh...@rcs0.html * igt@gem_exec_fair@basic-none@vcs0: - shard-kbl: [PASS][7] -> [FAIL][8] ([i915#2842]) +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10949/shard-kbl7/igt@gem_exec_fair@basic-n...@vcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21712/shard-kbl7/igt@gem_exec_fair@basic-n...@vcs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-tglb: [PASS][9] -> [FAIL][10] ([i915#2842]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10949/shard-tglb1/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21712/shard-tglb2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-iclb: [PASS][11] -> [FAIL][12] ([i915#2842]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10949/shard-iclb3/igt@gem_exec_fair@basic-pace-s...@rcs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21712/shard-iclb5/igt@gem_exec_fair@basic-pace-s...@rcs0.html * igt@gem_lmem_swapping@heavy-verify-random: - shard-apl: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#4613]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21712/shard-apl2/igt@gem_lmem_swapp...@heavy-verify-random.html * igt@gem_lmem_swapping@parallel-random-verify: - shard-skl: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21712/shard-skl8/igt@gem_lmem_swapp...@parallel-random-verify.html * igt@i915_suspend@fence-restore-tiled2untiled: - shard-kbl: NOTRUN -> [DMESG-WARN][15] ([i915#180]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21712/shard-kbl6/igt@i915_susp...@fence-restore-tiled2untiled.html * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip: - shard-apl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#3777]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21712/shard-apl2/igt@kms_big...@x-tiled-max-hw-stride-64bpp-rotate-180-hflip.html * igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs: - shard-apl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#3886]) +2 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21712/shard-apl2/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_mc_ccs: - shard-skl: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#3886]) +2 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21712/shard-skl8/igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_mc_ccs: - shard-kbl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#3886]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21712/shard-kbl1/igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-d-bad-aux-stride-y_tiled_ccs: - shard-tglb: NOTRUN -> [SKIP][20] ([i915#3689]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21712/shard-tglb5/igt@kms_ccs@pipe-d-bad-aux-stride-y_tiled_ccs.html * igt@kms_cdclk@mode-transition: - shard-apl: NOTRUN -> [SKIP][21] ([fdo#109271]) +41
[Intel-gfx] [PATCH 12/14] drm/i915: Extract skl_plane_aux_dist()
From: Ville Syrjälä
Extract the PLANE_AUX_DIST stuff into a small helper to
dclutter skl_program_plane_arm() a bit.
Signed-off-by: Ville Syrjälä
---
.../drm/i915/display/skl_universal_plane.c| 35 ---
1 file changed, 23 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 79998eb67280..c7de643d16dd 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -981,6 +981,26 @@ static u32 skl_plane_surf(const struct intel_plane_state
*plane_state,
return plane_surf;
}
+static u32 skl_plane_aux_dist(const struct intel_plane_state *plane_state,
+ int color_plane)
+{
+ struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
+ int aux_plane = skl_main_to_aux_plane(fb, color_plane);
+ u32 aux_dist;
+
+ if (!aux_plane)
+ return 0;
+
+ aux_dist = skl_surf_address(plane_state, aux_plane) -
+ skl_surf_address(plane_state, color_plane);
+
+ if (DISPLAY_VER(i915) < 12)
+ aux_dist |= PLANE_AUX_STRIDE(skl_plane_stride(plane_state,
aux_plane));
+
+ return aux_dist;
+}
+
static void icl_plane_csc_load_black(struct intel_plane *plane)
{
struct drm_i915_private *i915 = to_i915(plane->base.dev);
@@ -1075,11 +1095,9 @@ skl_program_plane_arm(struct intel_plane *plane,
enum plane_id plane_id = plane->id;
enum pipe pipe = plane->pipe;
const struct drm_intel_sprite_colorkey *key = _state->ckey;
- const struct drm_framebuffer *fb = plane_state->hw.fb;
- int aux_plane = skl_main_to_aux_plane(fb, color_plane);
u32 x = plane_state->view.color_plane[color_plane].x;
u32 y = plane_state->view.color_plane[color_plane].y;
- u32 keymsk, keymax, aux_dist = 0, plane_color_ctl = 0;
+ u32 keymsk, keymax, plane_color_ctl = 0;
u8 alpha = plane_state->hw.alpha >> 8;
u32 plane_ctl = plane_state->ctl;
unsigned long irqflags;
@@ -1096,14 +1114,6 @@ skl_program_plane_arm(struct intel_plane *plane,
if (alpha < 0xff)
keymsk |= PLANE_KEYMSK_ALPHA_ENABLE;
- if (aux_plane) {
- aux_dist = skl_surf_address(plane_state, aux_plane) -
- skl_surf_address(plane_state, color_plane);
-
- if (DISPLAY_VER(dev_priv) < 12)
- aux_dist |=
PLANE_AUX_STRIDE(skl_plane_stride(plane_state, aux_plane));
- }
-
spin_lock_irqsave(_priv->uncore.lock, irqflags);
intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id),
@@ -1114,7 +1124,8 @@ skl_program_plane_arm(struct intel_plane *plane,
intel_de_write_fw(dev_priv, PLANE_OFFSET(pipe, plane_id),
PLANE_OFFSET_Y(y) | PLANE_OFFSET_X(x));
- intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id), aux_dist);
+ intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id),
+ skl_plane_aux_dist(plane_state, color_plane));
if (DISPLAY_VER(dev_priv) < 11)
intel_de_write_fw(dev_priv, PLANE_AUX_OFFSET(pipe, plane_id),
--
2.32.0
[Intel-gfx] [PATCH 05/14] drm/i915: Rename PLANE_CUS_CTL Y plane bits
From: Ville Syrjälä
Rename the PLANE_CUS_CTL Y plane selection bits to actually
say "Y plane".
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 8
drivers/gpu/drm/i915/i915_reg.h | 8
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index badf035efaeb..726c1552c9bf 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5159,13 +5159,13 @@ static int icl_check_nv12_planes(struct
intel_crtc_state *crtc_state)
if (icl_is_hdr_plane(dev_priv, plane->id)) {
if (linked->id == PLANE_SPRITE5)
- plane_state->cus_ctl |= PLANE_CUS_PLANE_7;
+ plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL;
else if (linked->id == PLANE_SPRITE4)
- plane_state->cus_ctl |= PLANE_CUS_PLANE_6;
+ plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL;
else if (linked->id == PLANE_SPRITE3)
- plane_state->cus_ctl |= PLANE_CUS_PLANE_5_RKL;
+ plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL;
else if (linked->id == PLANE_SPRITE2)
- plane_state->cus_ctl |= PLANE_CUS_PLANE_4_RKL;
+ plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL;
else
MISSING_CASE(linked->id);
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6066b1e2763c..4b2bc17d0235 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7328,10 +7328,10 @@ enum {
#define _PLANE_CUS_CTL_1_A 0x701c8
#define _PLANE_CUS_CTL_2_A 0x702c8
#define PLANE_CUS_ENABLE (1 << 31)
-#define PLANE_CUS_PLANE_4_RKL (0 << 30)
-#define PLANE_CUS_PLANE_5_RKL (1 << 30)
-#define PLANE_CUS_PLANE_6 (0 << 30)
-#define PLANE_CUS_PLANE_7 (1 << 30)
+#define PLANE_CUS_Y_PLANE_4_RKL (0 << 30)
+#define PLANE_CUS_Y_PLANE_5_RKL (1 << 30)
+#define PLANE_CUS_Y_PLANE_6_ICL (0 << 30)
+#define PLANE_CUS_Y_PLANE_7_ICL (1 << 30)
#define PLANE_CUS_HPHASE_SIGN_NEGATIVE(1 << 19)
#define PLANE_CUS_HPHASE_0(0 << 16)
#define PLANE_CUS_HPHASE_0_25 (1 << 16)
--
2.32.0
[Intel-gfx] [PATCH 02/14] drm/i915: Rename plane YUV order bits
From: Ville Syrjälä
Rename the YUV byte order bits to be a bit more consistent.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/skl_universal_plane.c | 8
drivers/gpu/drm/i915/i915_reg.h| 14 +++---
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 845b99844ec6..9ff24a0e79b4 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -672,13 +672,13 @@ static u32 skl_plane_ctl_format(u32 pixel_format)
case DRM_FORMAT_XYUV:
return PLANE_CTL_FORMAT_XYUV;
case DRM_FORMAT_YUYV:
- return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
+ return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_YUYV;
case DRM_FORMAT_YVYU:
- return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
+ return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_YVYU;
case DRM_FORMAT_UYVY:
- return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
+ return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_UYVY;
case DRM_FORMAT_VYUY:
- return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
+ return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_VYUY;
case DRM_FORMAT_NV12:
return PLANE_CTL_FORMAT_NV12;
case DRM_FORMAT_P010:
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3c0471f20e53..02d8db03c0bf 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6966,7 +6966,7 @@ enum {
#define DVS_SOURCE_KEY (1 << 22)
#define DVS_RGB_ORDER_XBGR (1 << 20)
#define DVS_YUV_FORMAT_BT709 (1 << 18)
-#define DVS_YUV_BYTE_ORDER_MASK (3 << 16)
+#define DVS_YUV_ORDER_MASK (3 << 16)
#define DVS_YUV_ORDER_YUYV (0 << 16)
#define DVS_YUV_ORDER_UYVY (1 << 16)
#define DVS_YUV_ORDER_YVYU (2 << 16)
@@ -7045,7 +7045,7 @@ enum {
#define SPRITE_RGB_ORDER_RGBX(1 << 20) /* only for 888 and
161616 */
#define SPRITE_YUV_TO_RGB_CSC_DISABLE(1 << 19)
#define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709 (1 << 18) /* 0 is BT601 */
-#define SPRITE_YUV_BYTE_ORDER_MASK (3 << 16)
+#define SPRITE_YUV_ORDER_MASK(3 << 16)
#define SPRITE_YUV_ORDER_YUYV(0 << 16)
#define SPRITE_YUV_ORDER_UYVY(1 << 16)
#define SPRITE_YUV_ORDER_YVYU(2 << 16)
@@ -7130,7 +7130,7 @@ enum {
#define SP_ALPHA_PREMULTIPLY (1 << 23) /* CHV pipe B */
#define SP_SOURCE_KEY(1 << 22)
#define SP_YUV_FORMAT_BT709 (1 << 18)
-#define SP_YUV_BYTE_ORDER_MASK (3 << 16)
+#define SP_YUV_ORDER_MASK(3 << 16)
#define SP_YUV_ORDER_YUYV(0 << 16)
#define SP_YUV_ORDER_UYVY(1 << 16)
#define SP_YUV_ORDER_YVYU(2 << 16)
@@ -7271,10 +7271,10 @@ enum {
#define PLANE_CTL_YUV420_Y_PLANE (1 << 19)
#define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709(1 << 18)
#define PLANE_CTL_YUV422_ORDER_MASK (0x3 << 16)
-#define PLANE_CTL_YUV422_YUYV(0 << 16)
-#define PLANE_CTL_YUV422_UYVY(1 << 16)
-#define PLANE_CTL_YUV422_YVYU(2 << 16)
-#define PLANE_CTL_YUV422_VYUY(3 << 16)
+#define PLANE_CTL_YUV422_ORDER_YUYV (0 << 16)
+#define PLANE_CTL_YUV422_ORDER_UYVY (1 << 16)
+#define PLANE_CTL_YUV422_ORDER_YVYU (2 << 16)
+#define PLANE_CTL_YUV422_ORDER_VYUY (3 << 16)
#define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE(1 << 15)
#define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14)
#define PLANE_CTL_CLEAR_COLOR_DISABLE(1 << 13) /* TGL+ */
--
2.32.0
[Intel-gfx] [PATCH 14/14] drm/i915: Nuke pointless middle men for skl+ plane programming
From: Ville Syrjälä
There is no real point in having this two stage
skl_program_plane*() vs. skl_plane_update*() wrapper stuff.
All we need to do is determine the correct color plane and
we're done.
Signed-off-by: Ville Syrjälä
---
.../drm/i915/display/skl_universal_plane.c| 53 ++-
1 file changed, 17 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 92270679a99c..de2708ac1802 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1053,15 +1053,24 @@ static void icl_plane_csc_load_black(struct intel_plane
*plane)
intel_de_write_fw(i915, PLANE_CSC_POSTOFF(pipe, plane_id, 2), 0);
}
+static int skl_plane_color_plane(const struct intel_plane_state *plane_state)
+{
+ /* Program the UV plane on planar master */
+ if (plane_state->planar_linked_plane && !plane_state->planar_slave)
+ return 1;
+ else
+ return 0;
+}
+
static void
-skl_program_plane_noarm(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state,
- const struct intel_plane_state *plane_state,
- int color_plane)
+skl_plane_update_noarm(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum plane_id plane_id = plane->id;
enum pipe pipe = plane->pipe;
+ int color_plane = skl_plane_color_plane(plane_state);
u32 stride = skl_plane_stride(plane_state, color_plane);
const struct drm_framebuffer *fb = plane_state->hw.fb;
int crtc_x = plane_state->uapi.dst.x1;
@@ -1114,14 +1123,14 @@ skl_program_plane_noarm(struct intel_plane *plane,
}
static void
-skl_program_plane_arm(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state,
- const struct intel_plane_state *plane_state,
- int color_plane)
+skl_plane_update_arm(struct intel_plane *plane,
+const struct intel_crtc_state *crtc_state,
+const struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum plane_id plane_id = plane->id;
enum pipe pipe = plane->pipe;
+ int color_plane = skl_plane_color_plane(plane_state);
u32 x = plane_state->view.color_plane[color_plane].x;
u32 y = plane_state->view.color_plane[color_plane].y;
u32 plane_color_ctl = 0;
@@ -1202,34 +1211,6 @@ skl_plane_async_flip(struct intel_plane *plane,
spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
}
-static void
-skl_plane_update_noarm(struct intel_plane *plane,
- const struct intel_crtc_state *crtc_state,
- const struct intel_plane_state *plane_state)
-{
- int color_plane = 0;
-
- if (plane_state->planar_linked_plane && !plane_state->planar_slave)
- /* Program the UV plane on planar master */
- color_plane = 1;
-
- skl_program_plane_noarm(plane, crtc_state, plane_state, color_plane);
-}
-
-static void
-skl_plane_update_arm(struct intel_plane *plane,
-const struct intel_crtc_state *crtc_state,
-const struct intel_plane_state *plane_state)
-{
- int color_plane = 0;
-
- if (plane_state->planar_linked_plane && !plane_state->planar_slave)
- /* Program the UV plane on planar master */
- color_plane = 1;
-
- skl_program_plane_arm(plane, crtc_state, plane_state, color_plane);
-}
-
static bool intel_format_is_p01x(u32 format)
{
switch (format) {
--
2.32.0
[Intel-gfx] [PATCH 13/14] drm/i915: Declutter color key register stuff
From: Ville Syrjälä
Add a few small helpers to calculate the color key register
values. Cleans up skl_program_plane_arm() a bit.
Signed-off-by: Ville Syrjälä
---
.../drm/i915/display/skl_universal_plane.c| 45 +--
1 file changed, 32 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index c7de643d16dd..92270679a99c 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1001,6 +1001,34 @@ static u32 skl_plane_aux_dist(const struct
intel_plane_state *plane_state,
return aux_dist;
}
+static u32 skl_plane_keyval(const struct intel_plane_state *plane_state)
+{
+ const struct drm_intel_sprite_colorkey *key = _state->ckey;
+
+ return key->min_value;
+}
+
+static u32 skl_plane_keymax(const struct intel_plane_state *plane_state)
+{
+ const struct drm_intel_sprite_colorkey *key = _state->ckey;
+ u8 alpha = plane_state->hw.alpha >> 8;
+
+ return (key->max_value & 0xff) | PLANE_KEYMAX_ALPHA(alpha);
+}
+
+static u32 skl_plane_keymsk(const struct intel_plane_state *plane_state)
+{
+ const struct drm_intel_sprite_colorkey *key = _state->ckey;
+ u8 alpha = plane_state->hw.alpha >> 8;
+ u32 keymsk;
+
+ keymsk = key->channel_mask & 0x7ff;
+ if (alpha < 0xff)
+ keymsk |= PLANE_KEYMSK_ALPHA_ENABLE;
+
+ return keymsk;
+}
+
static void icl_plane_csc_load_black(struct intel_plane *plane)
{
struct drm_i915_private *i915 = to_i915(plane->base.dev);
@@ -1094,11 +1122,9 @@ skl_program_plane_arm(struct intel_plane *plane,
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum plane_id plane_id = plane->id;
enum pipe pipe = plane->pipe;
- const struct drm_intel_sprite_colorkey *key = _state->ckey;
u32 x = plane_state->view.color_plane[color_plane].x;
u32 y = plane_state->view.color_plane[color_plane].y;
- u32 keymsk, keymax, plane_color_ctl = 0;
- u8 alpha = plane_state->hw.alpha >> 8;
+ u32 plane_color_ctl = 0;
u32 plane_ctl = plane_state->ctl;
unsigned long irqflags;
@@ -1108,18 +1134,11 @@ skl_program_plane_arm(struct intel_plane *plane,
plane_color_ctl = plane_state->color_ctl |
glk_plane_color_ctl_crtc(crtc_state);
- keymax = (key->max_value & 0xff) | PLANE_KEYMAX_ALPHA(alpha);
-
- keymsk = key->channel_mask & 0x7ff;
- if (alpha < 0xff)
- keymsk |= PLANE_KEYMSK_ALPHA_ENABLE;
-
spin_lock_irqsave(_priv->uncore.lock, irqflags);
- intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id),
- key->min_value);
- intel_de_write_fw(dev_priv, PLANE_KEYMSK(pipe, plane_id), keymsk);
- intel_de_write_fw(dev_priv, PLANE_KEYMAX(pipe, plane_id), keymax);
+ intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id),
skl_plane_keyval(plane_state));
+ intel_de_write_fw(dev_priv, PLANE_KEYMSK(pipe, plane_id),
skl_plane_keymsk(plane_state));
+ intel_de_write_fw(dev_priv, PLANE_KEYMAX(pipe, plane_id),
skl_plane_keymax(plane_state));
intel_de_write_fw(dev_priv, PLANE_OFFSET(pipe, plane_id),
PLANE_OFFSET_Y(y) | PLANE_OFFSET_X(x));
--
2.32.0
[Intel-gfx] [PATCH 11/14] drm/i915: Clean up cursor registers
From: Ville Syrjälä
Use REG_BIT() & co. to polish the cursor plane registers.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cursor.c | 25 ---
drivers/gpu/drm/i915/display/intel_display.c | 4 +-
drivers/gpu/drm/i915/i915_reg.h | 71 +++-
3 files changed, 53 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c
b/drivers/gpu/drm/i915/display/intel_cursor.c
index 16d34685d83f..2ade8fdd9bdd 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -51,16 +51,16 @@ static u32 intel_cursor_position(const struct
intel_plane_state *plane_state)
u32 pos = 0;
if (x < 0) {
- pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
+ pos |= CURSOR_POS_X_SIGN;
x = -x;
}
- pos |= x << CURSOR_X_SHIFT;
+ pos |= CURSOR_POS_X(x);
if (y < 0) {
- pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
+ pos |= CURSOR_POS_Y_SIGN;
y = -y;
}
- pos |= y << CURSOR_Y_SHIFT;
+ pos |= CURSOR_POS_Y(y);
return pos;
}
@@ -180,7 +180,7 @@ static u32 i845_cursor_ctl_crtc(const struct
intel_crtc_state *crtc_state)
u32 cntl = 0;
if (crtc_state->gamma_enable)
- cntl |= CURSOR_GAMMA_ENABLE;
+ cntl |= CURSOR_PIPE_GAMMA_ENABLE;
return cntl;
}
@@ -264,7 +264,7 @@ static void i845_cursor_update_arm(struct intel_plane
*plane,
cntl = plane_state->ctl |
i845_cursor_ctl_crtc(crtc_state);
- size = (height << 12) | width;
+ size = CURSOR_HEIGHT(height) | CURSOR_WIDTH(width);
base = intel_cursor_base(plane_state);
pos = intel_cursor_position(plane_state);
@@ -280,7 +280,7 @@ static void i845_cursor_update_arm(struct intel_plane
*plane,
plane->cursor.cntl != cntl) {
intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), 0);
intel_de_write_fw(dev_priv, CURBASE(PIPE_A), base);
- intel_de_write_fw(dev_priv, CURSIZE, size);
+ intel_de_write_fw(dev_priv, CURSIZE(PIPE_A), size);
intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), cntl);
@@ -340,13 +340,13 @@ static u32 i9xx_cursor_ctl_crtc(const struct
intel_crtc_state *crtc_state)
return cntl;
if (crtc_state->gamma_enable)
- cntl = MCURSOR_GAMMA_ENABLE;
+ cntl = MCURSOR_PIPE_GAMMA_ENABLE;
if (crtc_state->csc_enable)
cntl |= MCURSOR_PIPE_CSC_ENABLE;
if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
- cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);
+ cntl |= MCURSOR_PIPE_SEL(crtc->pipe);
return cntl;
}
@@ -502,7 +502,7 @@ static void i9xx_cursor_update_arm(struct intel_plane
*plane,
i9xx_cursor_ctl_crtc(crtc_state);
if (width != height)
- fbc_ctl = CUR_FBC_CTL_EN | (height - 1);
+ fbc_ctl = CUR_FBC_EN | CUR_FBC_HEIGHT(height - 1);
base = intel_cursor_base(plane_state);
pos = intel_cursor_position(plane_state);
@@ -586,13 +586,12 @@ static bool i9xx_cursor_get_hw_state(struct intel_plane
*plane,
val = intel_de_read(dev_priv, CURCNTR(plane->pipe));
- ret = val & MCURSOR_MODE;
+ ret = val & MCURSOR_MODE_MASK;
if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))
*pipe = plane->pipe;
else
- *pipe = (val & MCURSOR_PIPE_SELECT_MASK) >>
- MCURSOR_PIPE_SELECT_SHIFT;
+ *pipe = REG_FIELD_GET(MCURSOR_PIPE_SEL_MASK, val);
intel_display_power_put(dev_priv, power_domain, wakeref);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 00a2c9915780..34c1463e2ef9 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -10041,9 +10041,9 @@ void i830_disable_pipe(struct drm_i915_private
*dev_priv, enum pipe pipe)
drm_WARN_ON(_priv->drm,
intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DSP_ENABLE);
drm_WARN_ON(_priv->drm,
- intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE);
+ intel_de_read(dev_priv, CURCNTR(PIPE_A)) &
MCURSOR_MODE_MASK);
drm_WARN_ON(_priv->drm,
- intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE);
+ intel_de_read(dev_priv, CURCNTR(PIPE_B)) &
MCURSOR_MODE_MASK);
intel_de_write(dev_priv, PIPECONF(pipe), 0);
intel_de_posting_read(dev_priv, PIPECONF(pipe));
diff --git a/drivers/gpu/drm/i915/i915_reg.h
[Intel-gfx] [PATCH 10/14] drm/i915: Clean up g4x+ sprite plane registers
From: Ville Syrjälä
Use REG_BIT() & co. to polish the g4x+ sprite plane registers.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_sprite.c | 12 ++--
drivers/gpu/drm/i915/i915_reg.h | 73 +
2 files changed, 53 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index eb9ce96c030f..6f2a560700ce 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -1054,7 +1054,7 @@ static u32 g4x_sprite_ctl_crtc(const struct
intel_crtc_state *crtc_state)
u32 dvscntr = 0;
if (crtc_state->gamma_enable)
- dvscntr |= DVS_GAMMA_ENABLE;
+ dvscntr |= DVS_PIPE_GAMMA_ENABLE;
if (crtc_state->csc_enable)
dvscntr |= DVS_PIPE_CSC_ENABLE;
@@ -1206,14 +1206,18 @@ g4x_sprite_update_noarm(struct intel_plane *plane,
unsigned long irqflags;
if (crtc_w != src_w || crtc_h != src_h)
- dvsscale = DVS_SCALE_ENABLE | ((src_w - 1) << 16) | (src_h - 1);
+ dvsscale = DVS_SCALE_ENABLE |
+ DVS_SRC_WIDTH(src_w - 1) |
+ DVS_SRC_HEIGHT(src_h - 1);
spin_lock_irqsave(_priv->uncore.lock, irqflags);
intel_de_write_fw(dev_priv, DVSSTRIDE(pipe),
plane_state->view.color_plane[0].mapping_stride);
- intel_de_write_fw(dev_priv, DVSPOS(pipe), (crtc_y << 16) | crtc_x);
- intel_de_write_fw(dev_priv, DVSSIZE(pipe), ((crtc_h - 1) << 16) |
(crtc_w - 1));
+ intel_de_write_fw(dev_priv, DVSPOS(pipe),
+ DVS_POS_Y(crtc_y) | DVS_POS_X(crtc_x));
+ intel_de_write_fw(dev_priv, DVSSIZE(pipe),
+ DVS_HEIGHT(crtc_h - 1) | DVS_WIDTH(crtc_w - 1));
intel_de_write_fw(dev_priv, DVSSCALE(pipe), dvsscale);
spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4d61e7f2ee7c..d215cad95fe8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6970,46 +6970,63 @@ enum {
/* Sprite A control */
#define _DVSACNTR 0x72180
-#define DVS_ENABLE (1 << 31)
-#define DVS_GAMMA_ENABLE (1 << 30)
-#define DVS_YUV_RANGE_CORRECTION_DISABLE (1 << 27)
-#define DVS_PIXFORMAT_MASK (3 << 25)
-#define DVS_FORMAT_YUV422(0 << 25)
-#define DVS_FORMAT_RGBX101010(1 << 25)
-#define DVS_FORMAT_RGBX888 (2 << 25)
-#define DVS_FORMAT_RGBX161616(3 << 25)
-#define DVS_PIPE_CSC_ENABLE (1 << 24)
-#define DVS_SOURCE_KEY (1 << 22)
-#define DVS_RGB_ORDER_XBGR (1 << 20)
-#define DVS_YUV_FORMAT_BT709 (1 << 18)
-#define DVS_YUV_ORDER_MASK (3 << 16)
-#define DVS_YUV_ORDER_YUYV (0 << 16)
-#define DVS_YUV_ORDER_UYVY (1 << 16)
-#define DVS_YUV_ORDER_YVYU (2 << 16)
-#define DVS_YUV_ORDER_VYUY (3 << 16)
-#define DVS_ROTATE_180 (1 << 15)
-#define DVS_DEST_KEY (1 << 2)
-#define DVS_TRICKLE_FEED_DISABLE (1 << 14)
-#define DVS_TILED(1 << 10)
+#define DVS_ENABLE REG_BIT(31)
+#define DVS_PIPE_GAMMA_ENABLEREG_BIT(30)
+#define DVS_YUV_RANGE_CORRECTION_DISABLE REG_BIT(27)
+#define DVS_FORMAT_MASK REG_GENMASK(26, 25)
+#define DVS_FORMAT_YUV422REG_FIELD_PREP(DVS_FORMAT_MASK, 0)
+#define DVS_FORMAT_RGBX101010REG_FIELD_PREP(DVS_FORMAT_MASK,
1)
+#define DVS_FORMAT_RGBX888 REG_FIELD_PREP(DVS_FORMAT_MASK, 2)
+#define DVS_FORMAT_RGBX161616REG_FIELD_PREP(DVS_FORMAT_MASK,
3)
+#define DVS_PIPE_CSC_ENABLE REG_BIT(24)
+#define DVS_SOURCE_KEY REG_BIT(22)
+#define DVS_RGB_ORDER_XBGR REG_BIT(20)
+#define DVS_YUV_FORMAT_BT709 REG_BIT(18)
+#define DVS_YUV_ORDER_MASK REG_GENMASK(17, 16)
+#define DVS_YUV_ORDER_YUYV REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 0)
+#define DVS_YUV_ORDER_UYVY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 1)
+#define DVS_YUV_ORDER_YVYU REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 2)
+#define DVS_YUV_ORDER_VYUY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 3)
+#define DVS_ROTATE_180 REG_BIT(15)
+#define DVS_DEST_KEY REG_BIT(2)
+#define DVS_TRICKLE_FEED_DISABLE REG_BIT(14)
+#define DVS_TILEDREG_BIT(10)
#define _DVSALINOFF0x72184
#define _DVSASTRIDE0x72188
#define _DVSAPOS 0x7218c
+#define DVS_POS_Y_MASK REG_GENMASK(31, 16)
+#define DVS_POS_Y(y) REG_FIELD_PREP(DVS_POS_Y_MASK, (y))
+#define DVS_POS_X_MASK REG_GENMASK(15, 0)
+#define DVS_POS_X(x) REG_FIELD_PREP(DVS_POS_X_MASK, (x))
#define _DVSASIZE 0x72190
+#define
[Intel-gfx] [PATCH 03/14] drm/i915: Get rid of the "sizes are 0 based" stuff
From: Ville Syrjälä
Replace the "sizes are 0 based" stuff with just straight
up -1 where needed. Less confusing all around.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_sprite.c | 26 ---
.../drm/i915/display/skl_universal_plane.c| 6 +
2 files changed, 6 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index 1b99a9501a45..2067a7bca4a8 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -431,10 +431,6 @@ vlv_sprite_update_noarm(struct intel_plane *plane,
u32 crtc_h = drm_rect_height(_state->uapi.dst);
unsigned long irqflags;
- /* Sizes are 0 based */
- crtc_w--;
- crtc_h--;
-
spin_lock_irqsave(_priv->uncore.lock, irqflags);
intel_de_write_fw(dev_priv, SPSTRIDE(pipe, plane_id),
@@ -442,7 +438,7 @@ vlv_sprite_update_noarm(struct intel_plane *plane,
intel_de_write_fw(dev_priv, SPPOS(pipe, plane_id),
(crtc_y << 16) | crtc_x);
intel_de_write_fw(dev_priv, SPSIZE(pipe, plane_id),
- (crtc_h << 16) | crtc_w);
+ ((crtc_h - 1) << 16) | (crtc_w - 1));
spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
}
@@ -866,21 +862,15 @@ ivb_sprite_update_noarm(struct intel_plane *plane,
u32 sprscale = 0;
unsigned long irqflags;
- /* Sizes are 0 based */
- src_w--;
- src_h--;
- crtc_w--;
- crtc_h--;
-
if (crtc_w != src_w || crtc_h != src_h)
- sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
+ sprscale = SPRITE_SCALE_ENABLE | ((src_w - 1) << 16) | (src_h -
1);
spin_lock_irqsave(_priv->uncore.lock, irqflags);
intel_de_write_fw(dev_priv, SPRSTRIDE(pipe),
plane_state->view.color_plane[0].mapping_stride);
intel_de_write_fw(dev_priv, SPRPOS(pipe), (crtc_y << 16) | crtc_x);
- intel_de_write_fw(dev_priv, SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
+ intel_de_write_fw(dev_priv, SPRSIZE(pipe), ((crtc_h - 1) << 16) |
(crtc_w - 1));
if (IS_IVYBRIDGE(dev_priv))
intel_de_write_fw(dev_priv, SPRSCALE(pipe), sprscale);
@@ -1208,21 +1198,15 @@ g4x_sprite_update_noarm(struct intel_plane *plane,
u32 dvsscale = 0;
unsigned long irqflags;
- /* Sizes are 0 based */
- src_w--;
- src_h--;
- crtc_w--;
- crtc_h--;
-
if (crtc_w != src_w || crtc_h != src_h)
- dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
+ dvsscale = DVS_SCALE_ENABLE | ((src_w - 1) << 16) | (src_h - 1);
spin_lock_irqsave(_priv->uncore.lock, irqflags);
intel_de_write_fw(dev_priv, DVSSTRIDE(pipe),
plane_state->view.color_plane[0].mapping_stride);
intel_de_write_fw(dev_priv, DVSPOS(pipe), (crtc_y << 16) | crtc_x);
- intel_de_write_fw(dev_priv, DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
+ intel_de_write_fw(dev_priv, DVSSIZE(pipe), ((crtc_h - 1) << 16) |
(crtc_w - 1));
intel_de_write_fw(dev_priv, DVSSCALE(pipe), dvsscale);
spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 9ff24a0e79b4..09948922016b 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1022,10 +1022,6 @@ skl_program_plane_noarm(struct intel_plane *plane,
u32 src_h = drm_rect_height(_state->uapi.src) >> 16;
unsigned long irqflags;
- /* Sizes are 0 based */
- src_w--;
- src_h--;
-
/* The scaler will handle the output position */
if (plane_state->scaler_id >= 0) {
crtc_x = 0;
@@ -1045,7 +1041,7 @@ skl_program_plane_noarm(struct intel_plane *plane,
intel_de_write_fw(dev_priv, PLANE_POS(pipe, plane_id),
(crtc_y << 16) | crtc_x);
intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id),
- (src_h << 16) | src_w);
+ ((src_h - 1) << 16) | (src_w - 1));
if (intel_fb_is_rc_ccs_cc_modifier(fb->modifier)) {
intel_de_write_fw(dev_priv, PLANE_CC_VAL(pipe, plane_id, 0),
--
2.32.0
[Intel-gfx] [PATCH 08/14] drm/i915: Clean up ivb+ sprite plane registers
From: Ville Syrjälä
Use REG_BIT() & co. to polish the ivb+ sprite plane registers.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_sprite.c | 20 +++--
drivers/gpu/drm/i915/i915_reg.h | 81 +
2 files changed, 62 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index 2067a7bca4a8..70083d04a9fd 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -700,7 +700,7 @@ static u32 ivb_sprite_ctl_crtc(const struct
intel_crtc_state *crtc_state)
u32 sprctl = 0;
if (crtc_state->gamma_enable)
- sprctl |= SPRITE_GAMMA_ENABLE;
+ sprctl |= SPRITE_PIPE_GAMMA_ENABLE;
if (crtc_state->csc_enable)
sprctl |= SPRITE_PIPE_CSC_ENABLE;
@@ -770,7 +770,7 @@ static u32 ivb_sprite_ctl(const struct intel_crtc_state
*crtc_state,
}
if (!ivb_need_sprite_gamma(plane_state))
- sprctl |= SPRITE_INT_GAMMA_DISABLE;
+ sprctl |= SPRITE_PLANE_GAMMA_DISABLE;
if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
sprctl |= SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709;
@@ -863,14 +863,18 @@ ivb_sprite_update_noarm(struct intel_plane *plane,
unsigned long irqflags;
if (crtc_w != src_w || crtc_h != src_h)
- sprscale = SPRITE_SCALE_ENABLE | ((src_w - 1) << 16) | (src_h -
1);
+ sprscale = SPRITE_SCALE_ENABLE |
+ SPRITE_SRC_WIDTH(src_w - 1) |
+ SPRITE_SRC_HEIGHT(src_h - 1);
spin_lock_irqsave(_priv->uncore.lock, irqflags);
intel_de_write_fw(dev_priv, SPRSTRIDE(pipe),
plane_state->view.color_plane[0].mapping_stride);
- intel_de_write_fw(dev_priv, SPRPOS(pipe), (crtc_y << 16) | crtc_x);
- intel_de_write_fw(dev_priv, SPRSIZE(pipe), ((crtc_h - 1) << 16) |
(crtc_w - 1));
+ intel_de_write_fw(dev_priv, SPRPOS(pipe),
+ SPRITE_POS_Y(crtc_y) | SPRITE_POS_X(crtc_x));
+ intel_de_write_fw(dev_priv, SPRSIZE(pipe),
+ SPRITE_HEIGHT(crtc_h - 1) | SPRITE_WIDTH(crtc_w - 1));
if (IS_IVYBRIDGE(dev_priv))
intel_de_write_fw(dev_priv, SPRSCALE(pipe), sprscale);
@@ -907,10 +911,12 @@ ivb_sprite_update_arm(struct intel_plane *plane,
/* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
* register */
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
- intel_de_write_fw(dev_priv, SPROFFSET(pipe), (y << 16) | x);
+ intel_de_write_fw(dev_priv, SPROFFSET(pipe),
+ SPRITE_OFFSET_Y(y) | SPRITE_OFFSET_X(x));
} else {
intel_de_write_fw(dev_priv, SPRLINOFF(pipe), linear_offset);
- intel_de_write_fw(dev_priv, SPRTILEOFF(pipe), (y << 16) | x);
+ intel_de_write_fw(dev_priv, SPRTILEOFF(pipe),
+ SPRITE_OFFSET_Y(y) | SPRITE_OFFSET_X(x));
}
/*
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8678cbab1d33..0bd47a929f5d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7046,50 +7046,67 @@ enum {
#define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK,
_DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */
#define _SPRA_CTL 0x70280
-#define SPRITE_ENABLE(1 << 31)
-#define SPRITE_GAMMA_ENABLE (1 << 30)
-#define SPRITE_YUV_RANGE_CORRECTION_DISABLE (1 << 28)
-#define SPRITE_PIXFORMAT_MASK(7 << 25)
-#define SPRITE_FORMAT_YUV422 (0 << 25)
-#define SPRITE_FORMAT_RGBX101010 (1 << 25)
-#define SPRITE_FORMAT_RGBX888(2 << 25)
-#define SPRITE_FORMAT_RGBX161616 (3 << 25)
-#define SPRITE_FORMAT_YUV444 (4 << 25)
-#define SPRITE_FORMAT_XR_BGR101010 (5 << 25) /* Extended range */
-#define SPRITE_PIPE_CSC_ENABLE (1 << 24)
-#define SPRITE_SOURCE_KEY(1 << 22)
-#define SPRITE_RGB_ORDER_RGBX(1 << 20) /* only for 888 and
161616 */
-#define SPRITE_YUV_TO_RGB_CSC_DISABLE(1 << 19)
-#define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709 (1 << 18) /* 0 is BT601 */
-#define SPRITE_YUV_ORDER_MASK(3 << 16)
-#define SPRITE_YUV_ORDER_YUYV(0 << 16)
-#define SPRITE_YUV_ORDER_UYVY(1 << 16)
-#define SPRITE_YUV_ORDER_YVYU(2 << 16)
-#define SPRITE_YUV_ORDER_VYUY(3 << 16)
-#define SPRITE_ROTATE_180(1 << 15)
-#define SPRITE_TRICKLE_FEED_DISABLE (1 << 14)
-#define SPRITE_INT_GAMMA_DISABLE (1 << 13)
-#define SPRITE_TILED (1 << 10)
-#define SPRITE_DEST_KEY (1 << 2)
+#define SPRITE_ENABLE
[Intel-gfx] [PATCH 04/14] drm/i915: Sipmplify PLANE_STRIDE masking
From: Ville Syrjälä
There's no need to have separate masks for the stride bitfield
in PLANE_STRIDE for different platforms. All the extra bits
are hardcoded to zero anyway.
Also the masks we're using now don't even match the actual hardware
since the bitfield was only 10 bits on skl/derivatives, only getting
bumped to 11 bits on glk.
So let's just use a 12 bit mask for everything.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/skl_universal_plane.c | 5 +
drivers/gpu/drm/i915/i915_reg.h| 3 +--
2 files changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 09948922016b..984bb35ecf06 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -2347,10 +2347,7 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
val = intel_de_read(dev_priv, PLANE_STRIDE(pipe, plane_id));
stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0);
- if (DISPLAY_VER(dev_priv) >= 13)
- fb->pitches[0] = (val & PLANE_STRIDE_MASK_XELPD) * stride_mult;
- else
- fb->pitches[0] = (val & PLANE_STRIDE_MASK) * stride_mult;
+ fb->pitches[0] = (val & PLANE_STRIDE_MASK) * stride_mult;
aligned_height = intel_fb_align_height(fb, 0, fb->height);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 02d8db03c0bf..6066b1e2763c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7440,8 +7440,7 @@ enum {
_PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
#define PLANE_STRIDE(pipe, plane) \
_MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
-#define PLANE_STRIDE_MASK REG_GENMASK(10, 0)
-#define PLANE_STRIDE_MASK_XELPDREG_GENMASK(11, 0)
+#define PLANE_STRIDE_MASK REG_GENMASK(11, 0)
#define _PLANE_POS_1_B 0x7118c
#define _PLANE_POS_2_B 0x7128c
--
2.32.0
[Intel-gfx] [PATCH 07/14] drm/i915: Clean up pre-skl primary plane registers
From: Ville Syrjälä
Use REG_BIT() & co. for the pre-skl primary plane registers.
Also give everything a consistent namespace.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/i9xx_plane.c| 99 +
drivers/gpu/drm/i915/display/intel_display.c | 13 +--
drivers/gpu/drm/i915/i915_reg.h | 108 +++
drivers/gpu/drm/i915/intel_pm.c | 2 +-
4 files changed, 117 insertions(+), 105 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 2194f74101ae..00cc8b4bd6bc 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -145,51 +145,51 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state
*crtc_state,
unsigned int rotation = plane_state->hw.rotation;
u32 dspcntr;
- dspcntr = DISPLAY_PLANE_ENABLE;
+ dspcntr = DSP_ENABLE;
if (IS_G4X(dev_priv) || IS_IRONLAKE(dev_priv) ||
IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv))
- dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
+ dspcntr |= DSP_TRICKLE_FEED_DISABLE;
switch (fb->format->format) {
case DRM_FORMAT_C8:
- dspcntr |= DISPPLANE_8BPP;
+ dspcntr |= DSP_FORMAT_8BPP;
break;
case DRM_FORMAT_XRGB1555:
- dspcntr |= DISPPLANE_BGRX555;
+ dspcntr |= DSP_FORMAT_BGRX555;
break;
case DRM_FORMAT_ARGB1555:
- dspcntr |= DISPPLANE_BGRA555;
+ dspcntr |= DSP_FORMAT_BGRA555;
break;
case DRM_FORMAT_RGB565:
- dspcntr |= DISPPLANE_BGRX565;
+ dspcntr |= DSP_FORMAT_BGRX565;
break;
case DRM_FORMAT_XRGB:
- dspcntr |= DISPPLANE_BGRX888;
+ dspcntr |= DSP_FORMAT_BGRX888;
break;
case DRM_FORMAT_XBGR:
- dspcntr |= DISPPLANE_RGBX888;
+ dspcntr |= DSP_FORMAT_RGBX888;
break;
case DRM_FORMAT_ARGB:
- dspcntr |= DISPPLANE_BGRA888;
+ dspcntr |= DSP_FORMAT_BGRA888;
break;
case DRM_FORMAT_ABGR:
- dspcntr |= DISPPLANE_RGBA888;
+ dspcntr |= DSP_FORMAT_RGBA888;
break;
case DRM_FORMAT_XRGB2101010:
- dspcntr |= DISPPLANE_BGRX101010;
+ dspcntr |= DSP_FORMAT_BGRX101010;
break;
case DRM_FORMAT_XBGR2101010:
- dspcntr |= DISPPLANE_RGBX101010;
+ dspcntr |= DSP_FORMAT_RGBX101010;
break;
case DRM_FORMAT_ARGB2101010:
- dspcntr |= DISPPLANE_BGRA101010;
+ dspcntr |= DSP_FORMAT_BGRA101010;
break;
case DRM_FORMAT_ABGR2101010:
- dspcntr |= DISPPLANE_RGBA101010;
+ dspcntr |= DSP_FORMAT_RGBA101010;
break;
case DRM_FORMAT_XBGR16161616F:
- dspcntr |= DISPPLANE_RGBX161616;
+ dspcntr |= DSP_FORMAT_RGBX161616;
break;
default:
MISSING_CASE(fb->format->format);
@@ -198,13 +198,13 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state
*crtc_state,
if (DISPLAY_VER(dev_priv) >= 4 &&
fb->modifier == I915_FORMAT_MOD_X_TILED)
- dspcntr |= DISPPLANE_TILED;
+ dspcntr |= DSP_TILED;
if (rotation & DRM_MODE_ROTATE_180)
- dspcntr |= DISPPLANE_ROTATE_180;
+ dspcntr |= DSP_ROTATE_180;
if (rotation & DRM_MODE_REFLECT_X)
- dspcntr |= DISPPLANE_MIRROR;
+ dspcntr |= DSP_MIRROR;
return dspcntr;
}
@@ -344,13 +344,13 @@ static u32 i9xx_plane_ctl_crtc(const struct
intel_crtc_state *crtc_state)
u32 dspcntr = 0;
if (crtc_state->gamma_enable)
- dspcntr |= DISPPLANE_GAMMA_ENABLE;
+ dspcntr |= DSP_PIPE_GAMMA_ENABLE;
if (crtc_state->csc_enable)
- dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
+ dspcntr |= DSP_PIPE_CSC_ENABLE;
if (DISPLAY_VER(dev_priv) < 5)
- dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
+ dspcntr |= DSP_PIPE_SEL(crtc->pipe);
return dspcntr;
}
@@ -427,9 +427,9 @@ static void i9xx_plane_update_noarm(struct intel_plane
*plane,
* program whatever is there.
*/
intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane),
- (crtc_y << 16) | crtc_x);
+ DSP_POS_Y(crtc_y) | DSP_POS_X(crtc_x));
intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane),
- ((crtc_h - 1) << 16) | (crtc_w - 1));
+ DSP_HEIGHT(crtc_h - 1) | DSP_POS_X(crtc_w -
1));
[Intel-gfx] [PATCH 06/14] drm/i915: Use REG_BIT() & co. for universal plane bits
From: Ville Syrjälä
Polish the skl+ universal plane register defines by
using REG_BIT() & co.
The defines are also currently spread around in some
semi-random fashion. Collect them up into one place.
Signed-off-by: Ville Syrjälä
---
.../drm/i915/display/skl_universal_plane.c| 36 ++--
drivers/gpu/drm/i915/gvt/reg.h| 1 -
drivers/gpu/drm/i915/i915_reg.h | 197 ++
drivers/gpu/drm/i915/intel_pm.c | 12 +-
4 files changed, 135 insertions(+), 111 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 984bb35ecf06..79998eb67280 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1037,11 +1037,12 @@ skl_program_plane_noarm(struct intel_plane *plane,
if (plane_state->force_black)
icl_plane_csc_load_black(plane);
- intel_de_write_fw(dev_priv, PLANE_STRIDE(pipe, plane_id), stride);
+ intel_de_write_fw(dev_priv, PLANE_STRIDE(pipe, plane_id),
+ PLANE_STRIDE_(stride));
intel_de_write_fw(dev_priv, PLANE_POS(pipe, plane_id),
- (crtc_y << 16) | crtc_x);
+ PLANE_POS_Y(crtc_y) | PLANE_POS_X(crtc_x));
intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id),
- ((src_h - 1) << 16) | (src_w - 1));
+ PLANE_HEIGHT(src_h - 1) | PLANE_WIDTH(src_w - 1));
if (intel_fb_is_rc_ccs_cc_modifier(fb->modifier)) {
intel_de_write_fw(dev_priv, PLANE_CC_VAL(pipe, plane_id, 0),
@@ -1100,7 +1101,7 @@ skl_program_plane_arm(struct intel_plane *plane,
skl_surf_address(plane_state, color_plane);
if (DISPLAY_VER(dev_priv) < 12)
- aux_dist |= skl_plane_stride(plane_state, aux_plane);
+ aux_dist |=
PLANE_AUX_STRIDE(skl_plane_stride(plane_state, aux_plane));
}
spin_lock_irqsave(_priv->uncore.lock, irqflags);
@@ -,14 +1112,14 @@ skl_program_plane_arm(struct intel_plane *plane,
intel_de_write_fw(dev_priv, PLANE_KEYMAX(pipe, plane_id), keymax);
intel_de_write_fw(dev_priv, PLANE_OFFSET(pipe, plane_id),
- (y << 16) | x);
+ PLANE_OFFSET_Y(y) | PLANE_OFFSET_X(x));
intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id), aux_dist);
if (DISPLAY_VER(dev_priv) < 11)
intel_de_write_fw(dev_priv, PLANE_AUX_OFFSET(pipe, plane_id),
- (plane_state->view.color_plane[1].y << 16) |
- plane_state->view.color_plane[1].x);
+
PLANE_OFFSET_Y(plane_state->view.color_plane[1].y) |
+
PLANE_OFFSET_X(plane_state->view.color_plane[1].x));
if (DISPLAY_VER(dev_priv) >= 10)
intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id),
plane_color_ctl);
@@ -2262,16 +2263,17 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
val = intel_de_read(dev_priv, PLANE_CTL(pipe, plane_id));
if (DISPLAY_VER(dev_priv) >= 11)
- pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK;
+ pixel_format = val & PLANE_CTL_FORMAT_MASK_ICL;
else
- pixel_format = val & PLANE_CTL_FORMAT_MASK;
+ pixel_format = val & PLANE_CTL_FORMAT_MASK_SKL;
if (DISPLAY_VER(dev_priv) >= 10) {
- alpha = intel_de_read(dev_priv,
- PLANE_COLOR_CTL(pipe, plane_id));
- alpha &= PLANE_COLOR_ALPHA_MASK;
+ u32 color_ctl;
+
+ color_ctl = intel_de_read(dev_priv, PLANE_COLOR_CTL(pipe,
plane_id));
+ alpha = REG_FIELD_GET(PLANE_COLOR_ALPHA_MASK, color_ctl);
} else {
- alpha = val & PLANE_CTL_ALPHA_MASK;
+ alpha = REG_FIELD_GET(PLANE_CTL_ALPHA_MASK, val);
}
fourcc = skl_format_to_fourcc(pixel_format,
@@ -2335,19 +2337,19 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
if (drm_rotation_90_or_270(plane_config->rotation))
goto error;
- base = intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) & 0xf000;
+ base = intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) &
PLANE_SURF_ADDR_MASK;
plane_config->base = base;
offset = intel_de_read(dev_priv, PLANE_OFFSET(pipe, plane_id));
val = intel_de_read(dev_priv, PLANE_SIZE(pipe, plane_id));
- fb->height = ((val >> 16) & 0x) + 1;
- fb->width = ((val >> 0) & 0x) + 1;
+ fb->height = REG_FIELD_GET(PLANE_HEIGHT_MASK, val) + 1;
+ fb->width = REG_FIELD_GET(PLANE_WIDTH_MASK, val) + 1;
val = intel_de_read(dev_priv, PLANE_STRIDE(pipe, plane_id));
[Intel-gfx] [PATCH 01/14] drm/i915: Get rid of the 64bit PLANE_CC_VAL mmio
From: Ville Syrjälä
Let's just stick to 32bit mmio accesses so we can get rid
of the bare "uncore" reg access in display code. The register
are defined as 32bit in the spec anyway.
We could define a 64bit "de" variant I suppose, but doesn't
really make much sense just for this one case, and when we
start to use the DSB for this stuff we'd also need another
64bit variant for that. Just easier to do 32bit always.
While at it we can reorder stuff a bit so that we write the
registers in order of increasing offset (more or less).
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/skl_universal_plane.c | 11 +++
drivers/gpu/drm/i915/i915_reg.h| 12 ++--
2 files changed, 13 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 28890876bdeb..845b99844ec6 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1047,6 +1047,13 @@ skl_program_plane_noarm(struct intel_plane *plane,
intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id),
(src_h << 16) | src_w);
+ if (intel_fb_is_rc_ccs_cc_modifier(fb->modifier)) {
+ intel_de_write_fw(dev_priv, PLANE_CC_VAL(pipe, plane_id, 0),
+ lower_32_bits(plane_state->ccval));
+ intel_de_write_fw(dev_priv, PLANE_CC_VAL(pipe, plane_id, 1),
+ upper_32_bits(plane_state->ccval));
+ }
+
if (icl_is_hdr_plane(dev_priv, plane_id))
intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id),
plane_state->cus_ctl);
@@ -1054,10 +1061,6 @@ skl_program_plane_noarm(struct intel_plane *plane,
if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
icl_program_input_csc(plane, crtc_state, plane_state);
- if (intel_fb_is_rc_ccs_cc_modifier(fb->modifier))
- intel_uncore_write64_fw(_priv->uncore,
- PLANE_CC_VAL(pipe, plane_id),
plane_state->ccval);
-
skl_write_plane_wm(plane, crtc_state);
intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state,
color_plane);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3450818802c2..3c0471f20e53 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7363,12 +7363,12 @@ enum {
#define _PLANE_NV12_BUF_CFG_1_A0x70278
#define _PLANE_NV12_BUF_CFG_2_A0x70378
-#define _PLANE_CC_VAL_1_B 0x711b4
-#define _PLANE_CC_VAL_2_B 0x712b4
-#define _PLANE_CC_VAL_1(pipe) _PIPE(pipe, _PLANE_CC_VAL_1_A,
_PLANE_CC_VAL_1_B)
-#define _PLANE_CC_VAL_2(pipe) _PIPE(pipe, _PLANE_CC_VAL_2_A,
_PLANE_CC_VAL_2_B)
-#define PLANE_CC_VAL(pipe, plane) \
- _MMIO_PLANE(plane, _PLANE_CC_VAL_1(pipe), _PLANE_CC_VAL_2(pipe))
+#define _PLANE_CC_VAL_1_B 0x711b4
+#define _PLANE_CC_VAL_2_B 0x712b4
+#define _PLANE_CC_VAL_1(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_1_A,
_PLANE_CC_VAL_1_B) + (dw) * 4)
+#define _PLANE_CC_VAL_2(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_2_A,
_PLANE_CC_VAL_2_B) + (dw) * 4)
+#define PLANE_CC_VAL(pipe, plane, dw) \
+ _MMIO_PLANE((plane), _PLANE_CC_VAL_1((pipe), (dw)),
_PLANE_CC_VAL_2((pipe), (dw)))
/* Input CSC Register Definitions */
#define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0
--
2.32.0
[Intel-gfx] [PATCH 00/14] drm/i915: Plane register cleanup
From: Ville Syrjälä Bunch of cleanup around plane registers, and a bit of reshuffling in the skl+ universal plane code. Ville Syrjälä (14): drm/i915: Get rid of the 64bit PLANE_CC_VAL mmio drm/i915: Rename plane YUV order bits drm/i915: Get rid of the "sizes are 0 based" stuff drm/i915: Sipmplify PLANE_STRIDE masking drm/i915: Rename PLANE_CUS_CTL Y plane bits drm/i915: Use REG_BIT() & co. for universal plane bits drm/i915: Clean up pre-skl primary plane registers drm/i915: Clean up ivb+ sprite plane registers drm/i915: Clean up vlv/chv sprite plane registers drm/i915: Clean up g4x+ sprite plane registers drm/i915: Clean up cursor registers drm/i915: Extract skl_plane_aux_dist() drm/i915: Declutter color key register stuff drm/i915: Nuke pointless middle men for skl+ plane programming drivers/gpu/drm/i915/display/i9xx_plane.c | 99 ++- drivers/gpu/drm/i915/display/intel_cursor.c | 25 +- drivers/gpu/drm/i915/display/intel_display.c | 25 +- drivers/gpu/drm/i915/display/intel_sprite.c | 57 +- .../drm/i915/display/skl_universal_plane.c| 191 +++--- drivers/gpu/drm/i915/gvt/reg.h| 1 - drivers/gpu/drm/i915/i915_reg.h | 646 ++ drivers/gpu/drm/i915/intel_pm.c | 14 +- 8 files changed, 581 insertions(+), 477 deletions(-) -- 2.32.0
Re: [Intel-gfx] [PATCH v2 09/10] drm/i915/display: convert dp_to_i915() to a macro
On Wed, Dec 01, 2021 at 03:57:11PM +0200, Jani Nikula wrote:
> Avoid looking into the guts of struct drm_i915_private in
> headers. Again, converting an inline function to a macro is less than
> ideal, but avoids having to pull in i915_drv.h just for the to_i915()
> part.
Ugly, but gets the job done.
Reviewed-by: Ville Syrjälä
>
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_display_types.h | 6 +-
> 1 file changed, 1 insertion(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 14b4c3bb6030..f6e76b4d377d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1883,11 +1883,7 @@ dp_to_lspcon(struct intel_dp *intel_dp)
> return _to_dig_port(intel_dp)->lspcon;
> }
>
> -static inline struct drm_i915_private *
> -dp_to_i915(struct intel_dp *intel_dp)
> -{
> - return to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
> -}
> +#define dp_to_i915(__intel_dp)
> to_i915(dp_to_dig_port(__intel_dp)->base.base.dev)
>
> #define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \
> (intel_dp)->psr.source_support)
> --
> 2.30.2
--
Ville Syrjälä
Intel
Re: [Intel-gfx] [PATCH v2 08/10] drm/i915: move enum hpd_pin to intel_display.h
On Wed, Dec 01, 2021 at 03:57:10PM +0200, Jani Nikula wrote:
> It's not the ideal location, but a better alternative than
> i915_drv.h. The goal is to break the intel_display_types.h to i915_drv.h
> dependency.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_display.h | 24
> drivers/gpu/drm/i915/i915_drv.h | 24
> 2 files changed, 24 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h
> b/drivers/gpu/drm/i915/display/intel_display.h
> index 38c15ec30ee7..8d8725b45d99 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -346,6 +346,30 @@ enum phy_fia {
> FIA3,
> };
>
> +enum hpd_pin {
> + HPD_NONE = 0,
> + HPD_TV = HPD_NONE, /* TV is known to be unreliable */
> + HPD_CRT,
> + HPD_SDVO_B,
> + HPD_SDVO_C,
> + HPD_PORT_A,
> + HPD_PORT_B,
> + HPD_PORT_C,
> + HPD_PORT_D,
> + HPD_PORT_E,
> + HPD_PORT_TC1,
> + HPD_PORT_TC2,
> + HPD_PORT_TC3,
> + HPD_PORT_TC4,
> + HPD_PORT_TC5,
> + HPD_PORT_TC6,
> +
> + HPD_NUM_PINS
> +};
> +
> +#define for_each_hpd_pin(__pin) \
> + for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
> +
> #define for_each_pipe(__dev_priv, __p) \
> for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \
> for_each_if(INTEL_INFO(__dev_priv)->pipe_mask & BIT(__p))
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index e2ccc0696df7..27677bb18a6b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -117,30 +117,6 @@
>
> struct drm_i915_gem_object;
>
> -enum hpd_pin {
> - HPD_NONE = 0,
> - HPD_TV = HPD_NONE, /* TV is known to be unreliable */
> - HPD_CRT,
> - HPD_SDVO_B,
> - HPD_SDVO_C,
> - HPD_PORT_A,
> - HPD_PORT_B,
> - HPD_PORT_C,
> - HPD_PORT_D,
> - HPD_PORT_E,
> - HPD_PORT_TC1,
> - HPD_PORT_TC2,
> - HPD_PORT_TC3,
> - HPD_PORT_TC4,
> - HPD_PORT_TC5,
> - HPD_PORT_TC6,
> -
> - HPD_NUM_PINS
> -};
> -
> -#define for_each_hpd_pin(__pin) \
> - for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
> -
> /* Threshold == 5 for long IRQs, 50 for short */
> #define HPD_STORM_DEFAULT_THRESHOLD 50
>
> --
> 2.30.2
--
Ville Syrjälä
Intel
Re: [Intel-gfx] [PATCH v2 07/10] drm/i915: split out intel_pm_types.h
On Wed, Dec 01, 2021 at 03:57:09PM +0200, Jani Nikula wrote:
> This is far from ideal, but it reduces the i915_drv.h dependency from
> intel_display_types.h. Maybe in the future we'll need a better split.
Yeah, looks pretty temporary until we move the wm code into some
actually sensible place.
Reviewed-by: Ville Syrjälä
>
> Signed-off-by: Jani Nikula
> ---
> .../drm/i915/display/intel_display_types.h| 1 +
> drivers/gpu/drm/i915/i915_drv.h | 64 +---
> drivers/gpu/drm/i915/intel_pm_types.h | 76 +++
> 3 files changed, 78 insertions(+), 63 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/intel_pm_types.h
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 5f077e8cea33..14b4c3bb6030 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -47,6 +47,7 @@
> #include
>
> #include "i915_drv.h"
> +#include "intel_pm_types.h"
>
> struct drm_printer;
> struct __intel_global_objs_state;
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 1bfadd9127fc..e2ccc0696df7 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -89,6 +89,7 @@
> #include "intel_device_info.h"
> #include "intel_memory_region.h"
> #include "intel_pch.h"
> +#include "intel_pm_types.h"
> #include "intel_runtime_pm.h"
> #include "intel_step.h"
> #include "intel_uncore.h"
> @@ -730,69 +731,6 @@ struct intel_vbt_data {
> struct sdvo_device_mapping sdvo_mappings[2];
> };
>
> -enum intel_ddb_partitioning {
> - INTEL_DDB_PART_1_2,
> - INTEL_DDB_PART_5_6, /* IVB+ */
> -};
> -
> -struct ilk_wm_values {
> - u32 wm_pipe[3];
> - u32 wm_lp[3];
> - u32 wm_lp_spr[3];
> - bool enable_fbc_wm;
> - enum intel_ddb_partitioning partitioning;
> -};
> -
> -struct g4x_pipe_wm {
> - u16 plane[I915_MAX_PLANES];
> - u16 fbc;
> -};
> -
> -struct g4x_sr_wm {
> - u16 plane;
> - u16 cursor;
> - u16 fbc;
> -};
> -
> -struct vlv_wm_ddl_values {
> - u8 plane[I915_MAX_PLANES];
> -};
> -
> -struct vlv_wm_values {
> - struct g4x_pipe_wm pipe[3];
> - struct g4x_sr_wm sr;
> - struct vlv_wm_ddl_values ddl[3];
> - u8 level;
> - bool cxsr;
> -};
> -
> -struct g4x_wm_values {
> - struct g4x_pipe_wm pipe[2];
> - struct g4x_sr_wm sr;
> - struct g4x_sr_wm hpll;
> - bool cxsr;
> - bool hpll_en;
> - bool fbc_en;
> -};
> -
> -struct skl_ddb_entry {
> - u16 start, end; /* in number of blocks, 'end' is exclusive */
> -};
> -
> -static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry)
> -{
> - return entry->end - entry->start;
> -}
> -
> -static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
> -const struct skl_ddb_entry *e2)
> -{
> - if (e1->start == e2->start && e1->end == e2->end)
> - return true;
> -
> - return false;
> -}
> -
> struct i915_frontbuffer_tracking {
> spinlock_t lock;
>
> diff --git a/drivers/gpu/drm/i915/intel_pm_types.h
> b/drivers/gpu/drm/i915/intel_pm_types.h
> new file mode 100644
> index ..211632f58751
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_pm_types.h
> @@ -0,0 +1,76 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2021 Intel Corporation
> + */
> +
> +#ifndef __INTEL_PM_TYPES_H__
> +#define __INTEL_PM_TYPES_H__
> +
> +#include
> +
> +#include "display/intel_display.h"
> +
> +enum intel_ddb_partitioning {
> + INTEL_DDB_PART_1_2,
> + INTEL_DDB_PART_5_6, /* IVB+ */
> +};
> +
> +struct ilk_wm_values {
> + u32 wm_pipe[3];
> + u32 wm_lp[3];
> + u32 wm_lp_spr[3];
> + bool enable_fbc_wm;
> + enum intel_ddb_partitioning partitioning;
> +};
> +
> +struct g4x_pipe_wm {
> + u16 plane[I915_MAX_PLANES];
> + u16 fbc;
> +};
> +
> +struct g4x_sr_wm {
> + u16 plane;
> + u16 cursor;
> + u16 fbc;
> +};
> +
> +struct vlv_wm_ddl_values {
> + u8 plane[I915_MAX_PLANES];
> +};
> +
> +struct vlv_wm_values {
> + struct g4x_pipe_wm pipe[3];
> + struct g4x_sr_wm sr;
> + struct vlv_wm_ddl_values ddl[3];
> + u8 level;
> + bool cxsr;
> +};
> +
> +struct g4x_wm_values {
> + struct g4x_pipe_wm pipe[2];
> + struct g4x_sr_wm sr;
> + struct g4x_sr_wm hpll;
> + bool cxsr;
> + bool hpll_en;
> + bool fbc_en;
> +};
> +
> +struct skl_ddb_entry {
> + u16 start, end; /* in number of blocks, 'end' is exclusive */
> +};
> +
> +static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry)
> +{
> + return entry->end - entry->start;
> +}
> +
> +static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
> +const struct skl_ddb_entry *e2)
> +{
> + if (e1->start == e2->start && e1->end == e2->end)
> +
Re: [Intel-gfx] [PATCH v2 05/10] drm/i915/crtc: un-inline some crtc functions and move to intel_crtc.[ch]
On Wed, Dec 01, 2021 at 03:57:07PM +0200, Jani Nikula wrote:
> Move a number of crtc/pipe related functions to intel_crtc.[ch], and
> un-inline to avoid looking into struct drm_i915_private guts in header
> files.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_crtc.c | 42 ++
> drivers/gpu/drm/i915/display/intel_crtc.h | 10 +
> .../drm/i915/display/intel_display_types.h| 44 ---
> 3 files changed, 52 insertions(+), 44 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c
> b/drivers/gpu/drm/i915/display/intel_crtc.c
> index 243d5cc29734..43554b591904 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> @@ -36,6 +36,48 @@ static void assert_vblank_disabled(struct drm_crtc *crtc)
> drm_crtc_vblank_put(crtc);
> }
>
> +bool intel_pipe_valid(struct drm_i915_private *i915, enum pipe pipe)
> +{
> + return (pipe >= 0 &&
> + pipe < ARRAY_SIZE(i915->pipe_to_crtc_mapping) &&
> + INTEL_INFO(i915)->pipe_mask & BIT(pipe) &&
> + i915->pipe_to_crtc_mapping[pipe]);
> +}
> +
> +struct intel_crtc *intel_get_first_crtc(struct drm_i915_private *i915)
> +{
> + return to_intel_crtc(drm_crtc_from_index(>drm, 0));
> +}
> +
> +struct intel_crtc *intel_crtc_for_pipe(struct drm_i915_private *i915,
> +enum pipe pipe)
> +{
> + /* pipe_to_crtc_mapping may have hole on any of 3 display pipe system */
> + drm_WARN_ON(>drm,
> + !(INTEL_INFO(i915)->pipe_mask & BIT(pipe)));
> + return i915->pipe_to_crtc_mapping[pipe];
> +}
> +
> +struct intel_crtc *intel_crtc_for_plane(struct drm_i915_private *i915,
> + enum i9xx_plane_id plane)
> +{
> + return i915->plane_to_crtc_mapping[plane];
> +}
> +
> +void intel_crtc_wait_for_next_vblank(struct intel_crtc *crtc)
> +{
> + drm_crtc_wait_one_vblank(>base);
> +}
> +
> +void intel_wait_for_vblank_if_active(struct drm_i915_private *i915,
> + enum pipe pipe)
> +{
> + struct intel_crtc *crtc = intel_crtc_for_pipe(i915, pipe);
> +
> + if (crtc->active)
> + intel_crtc_wait_for_next_vblank(crtc);
> +}
> +
> u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
> {
> struct drm_device *dev = crtc->base.dev;
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc.h
> b/drivers/gpu/drm/i915/display/intel_crtc.h
> index a0039fdb1eb0..23110e91ecd6 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc.h
> +++ b/drivers/gpu/drm/i915/display/intel_crtc.h
> @@ -8,6 +8,7 @@
>
> #include
>
> +enum i9xx_plane_id;
> enum pipe;
> struct drm_display_mode;
> struct drm_i915_private;
> @@ -28,5 +29,14 @@ void intel_crtc_vblank_off(const struct intel_crtc_state
> *crtc_state);
> void intel_pipe_update_start(struct intel_crtc_state *new_crtc_state);
> void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state);
> void intel_wait_for_vblank_workers(struct intel_atomic_state *state);
> +bool intel_pipe_valid(struct drm_i915_private *i915, enum pipe pipe);
> +struct intel_crtc *intel_get_first_crtc(struct drm_i915_private *i915);
> +struct intel_crtc *intel_crtc_for_pipe(struct drm_i915_private *i915,
> +enum pipe pipe);
> +struct intel_crtc *intel_crtc_for_plane(struct drm_i915_private *i915,
> + enum i9xx_plane_id plane);
> +void intel_wait_for_vblank_if_active(struct drm_i915_private *i915,
> + enum pipe pipe);
> +void intel_crtc_wait_for_next_vblank(struct intel_crtc *crtc);
>
> #endif
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index a48dfd1474dd..eeaaa101a7b6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1773,35 +1773,6 @@ vlv_pipe_to_channel(enum pipe pipe)
> }
> }
>
> -static inline bool intel_pipe_valid(struct drm_i915_private *i915, enum pipe
> pipe)
> -{
> - return (pipe >= 0 &&
> - pipe < ARRAY_SIZE(i915->pipe_to_crtc_mapping) &&
> - INTEL_INFO(i915)->pipe_mask & BIT(pipe) &&
> - i915->pipe_to_crtc_mapping[pipe]);
> -}
> -
> -static inline struct intel_crtc *
> -intel_get_first_crtc(struct drm_i915_private *dev_priv)
> -{
> - return to_intel_crtc(drm_crtc_from_index(_priv->drm, 0));
> -}
> -
> -static inline struct intel_crtc *
> -intel_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
> -{
> - /* pipe_to_crtc_mapping may have hole on any of 3 display pipe system */
> - drm_WARN_ON(_priv->drm,
> - !(INTEL_INFO(dev_priv)->pipe_mask & BIT(pipe)));
> - return dev_priv->pipe_to_crtc_mapping[pipe];
> -}
> -
> -static inline
Re: [Intel-gfx] [PATCH v2 06/10] drm/i915/fb: move intel_fb_uses_dpt to intel_fb.c and un-inline
On Wed, Dec 01, 2021 at 03:57:08PM +0200, Jani Nikula wrote:
> Move fb functions where they belong, and un-inline to avoid looking into
> struct drm_i915_private guts in header files.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_display_types.h | 10 --
> drivers/gpu/drm/i915/display/intel_fb.c| 10 ++
> drivers/gpu/drm/i915/display/intel_fb.h| 2 ++
> 3 files changed, 12 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index eeaaa101a7b6..5f077e8cea33 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1990,16 +1990,6 @@ intel_crtc_needs_modeset(const struct intel_crtc_state
> *crtc_state)
> return drm_atomic_crtc_needs_modeset(_state->uapi);
> }
>
> -static inline bool intel_modifier_uses_dpt(struct drm_i915_private *i915,
> u64 modifier)
> -{
> - return DISPLAY_VER(i915) >= 13 && modifier != DRM_FORMAT_MOD_LINEAR;
> -}
> -
> -static inline bool intel_fb_uses_dpt(const struct drm_framebuffer *fb)
> -{
> - return fb && intel_modifier_uses_dpt(to_i915(fb->dev), fb->modifier);
> -}
> -
> static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state
> *plane_state)
> {
> return i915_ggtt_offset(plane_state->ggtt_vma);
> diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
> b/drivers/gpu/drm/i915/display/intel_fb.c
> index c4a743d0913f..99769132c35b 100644
> --- a/drivers/gpu/drm/i915/display/intel_fb.c
> +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> @@ -658,6 +658,16 @@ static unsigned int intel_fb_modifier_to_tiling(u64
> fb_modifier)
> }
> }
>
> +static bool intel_modifier_uses_dpt(struct drm_i915_private *i915, u64
> modifier)
> +{
> + return DISPLAY_VER(i915) >= 13 && modifier != DRM_FORMAT_MOD_LINEAR;
> +}
> +
> +bool intel_fb_uses_dpt(const struct drm_framebuffer *fb)
> +{
> + return fb && intel_modifier_uses_dpt(to_i915(fb->dev), fb->modifier);
> +}
> +
> unsigned int intel_cursor_alignment(const struct drm_i915_private *i915)
> {
> if (IS_I830(i915))
> diff --git a/drivers/gpu/drm/i915/display/intel_fb.h
> b/drivers/gpu/drm/i915/display/intel_fb.h
> index b54997175d6d..ba9df8986c1e 100644
> --- a/drivers/gpu/drm/i915/display/intel_fb.h
> +++ b/drivers/gpu/drm/i915/display/intel_fb.h
> @@ -90,4 +90,6 @@ intel_user_framebuffer_create(struct drm_device *dev,
> struct drm_file *filp,
> const struct drm_mode_fb_cmd2 *user_mode_cmd);
>
> +bool intel_fb_uses_dpt(const struct drm_framebuffer *fb);
> +
> #endif /* __INTEL_FB_H__ */
> --
> 2.30.2
--
Ville Syrjälä
Intel
Re: [Intel-gfx] [PATCH v2 04/10] drm/i915/display: remove intel_wait_for_vblank()
On Wed, Dec 01, 2021 at 03:57:06PM +0200, Jani Nikula wrote:
> There are only three call sites remaining for
> intel_wait_for_vblank(). Remove the function, and open code it to avoid
> new users from showing up.
>
> v2:
> - Use intel_crtc_wait_for_next_vblank() (Ville)
>
> Signed-off-by: Jani Nikula
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
> drivers/gpu/drm/i915/display/intel_crt.c | 2 +-
> drivers/gpu/drm/i915/display/intel_display.c | 8 ++--
> drivers/gpu/drm/i915/display/intel_display_types.h | 8
> 4 files changed, 8 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 5a475aa52079..986fb9ba750e 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1690,7 +1690,7 @@ static void bxt_set_cdclk(struct drm_i915_private
> *dev_priv,
> intel_de_write(dev_priv, CDCLK_CTL, val);
>
> if (pipe != INVALID_PIPE)
> - intel_wait_for_vblank(dev_priv, pipe);
> + intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv,
> pipe));
>
> if (DISPLAY_VER(dev_priv) >= 11) {
> ret = sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
> diff --git a/drivers/gpu/drm/i915/display/intel_crt.c
> b/drivers/gpu/drm/i915/display/intel_crt.c
> index 42533e6457b5..6a3893c8ff22 100644
> --- a/drivers/gpu/drm/i915/display/intel_crt.c
> +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> @@ -721,7 +721,7 @@ intel_crt_load_detect(struct intel_crt *crt, u32 pipe)
> intel_uncore_posting_read(uncore, pipeconf_reg);
> /* Wait for next Vblank to substitue
>* border color for Color info */
> - intel_wait_for_vblank(dev_priv, pipe);
> + intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv,
> pipe));
> st00 = intel_uncore_read8(uncore, _VGA_MSR_WRITE);
> status = ((st00 & (1 << 4)) != 0) ?
> connector_status_connected :
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 624a7d719531..09f088e6272b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2101,8 +2101,12 @@ static void hsw_crtc_enable(struct intel_atomic_state
> *state,
>* to change the workaround. */
> hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe;
> if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
> - intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
> - intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
> + struct intel_crtc *wa_crtc;
> +
> + wa_crtc = intel_crtc_for_pipe(dev_priv, hsw_workaround_pipe);
> +
> + intel_crtc_wait_for_next_vblank(wa_crtc);
> + intel_crtc_wait_for_next_vblank(wa_crtc);
> }
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 036f9be3045d..a48dfd1474dd 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -2025,14 +2025,6 @@ intel_crtc_wait_for_next_vblank(struct intel_crtc
> *crtc)
> drm_crtc_wait_one_vblank(>base);
> }
>
> -static inline void
> -intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
> -{
> - struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe);
> -
> - intel_crtc_wait_for_next_vblank(crtc);
> -}
> -
> static inline void
> intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, enum pipe
> pipe)
> {
> --
> 2.30.2
--
Ville Syrjälä
Intel
Re: [Intel-gfx] [PATCH v2 03/10] drm/i915/crtc: rename intel_get_crtc_for_plane() to intel_crtc_for_plane()
On Wed, Dec 01, 2021 at 03:57:05PM +0200, Jani Nikula wrote:
> The "get" in the name implies reference counting, remove it. This also
> makes the function conform to naming style.
>
> Suggested-by: Ville Syrjälä
> Signed-off-by: Jani Nikula
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_display_types.h | 2 +-
> drivers/gpu/drm/i915/intel_pm.c| 4 ++--
> 2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 8009bcfa1a38..036f9be3045d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1797,7 +1797,7 @@ intel_crtc_for_pipe(struct drm_i915_private *dev_priv,
> enum pipe pipe)
> }
>
> static inline struct intel_crtc *
> -intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum
> i9xx_plane_id plane)
> +intel_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id
> plane)
> {
> return dev_priv->plane_to_crtc_mapping[plane];
> }
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index fadcd8af5452..ed760627aa6f 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2357,7 +2357,7 @@ static void i9xx_update_wm(struct drm_i915_private
> *dev_priv)
> fifo_size = i830_get_fifo_size(dev_priv, PLANE_A);
> else
> fifo_size = i9xx_get_fifo_size(dev_priv, PLANE_A);
> - crtc = intel_get_crtc_for_plane(dev_priv, PLANE_A);
> + crtc = intel_crtc_for_plane(dev_priv, PLANE_A);
> if (intel_crtc_active(crtc)) {
> const struct drm_display_mode *pipe_mode =
> >config->hw.pipe_mode;
> @@ -2387,7 +2387,7 @@ static void i9xx_update_wm(struct drm_i915_private
> *dev_priv)
> fifo_size = i830_get_fifo_size(dev_priv, PLANE_B);
> else
> fifo_size = i9xx_get_fifo_size(dev_priv, PLANE_B);
> - crtc = intel_get_crtc_for_plane(dev_priv, PLANE_B);
> + crtc = intel_crtc_for_plane(dev_priv, PLANE_B);
> if (intel_crtc_active(crtc)) {
> const struct drm_display_mode *pipe_mode =
> >config->hw.pipe_mode;
> --
> 2.30.2
--
Ville Syrjälä
Intel
Re: [Intel-gfx] [PATCH v2 01/10] drm/i915/display: add intel_crtc_wait_for_next_vblank() and use it
On Wed, Dec 01, 2021 at 03:57:03PM +0200, Jani Nikula wrote:
> intel_wait_for_vblank() goes through a pipe to crtc lookup, while in
> most cases we already have the crtc available. Avoid the extra lookups
> by adding an intel_crtc based helper.
>
> v2:
> - Add intel_crtc_wait_for_next_vblank() helper (Ville)
>
> Signed-off-by: Jani Nikula
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_crt.c | 4 +--
> drivers/gpu/drm/i915/display/intel_display.c | 32 +--
> .../drm/i915/display/intel_display_types.h| 12 +--
> drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
> drivers/gpu/drm/i915/display/intel_sdvo.c | 2 +-
> drivers/gpu/drm/i915/display/intel_tv.c | 7 ++--
> 6 files changed, 32 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crt.c
> b/drivers/gpu/drm/i915/display/intel_crt.c
> index f0f28572dfdc..42533e6457b5 100644
> --- a/drivers/gpu/drm/i915/display/intel_crt.c
> +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> @@ -321,8 +321,8 @@ static void hsw_enable_crt(struct intel_atomic_state
> *state,
>
> intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON);
>
> - intel_wait_for_vblank(dev_priv, pipe);
> - intel_wait_for_vblank(dev_priv, pipe);
> + intel_crtc_wait_for_next_vblank(crtc);
> + intel_crtc_wait_for_next_vblank(crtc);
> intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
> intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 4b065a281d69..503074dc5690 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -775,7 +775,7 @@ void intel_plane_disable_noatomic(struct intel_crtc *crtc,
>*/
> if (HAS_GMCH(dev_priv) &&
> intel_set_memory_cxsr(dev_priv, false))
> - intel_wait_for_vblank(dev_priv, crtc->pipe);
> + intel_crtc_wait_for_next_vblank(crtc);
>
> /*
>* Gen2 reports pipe underruns whenever all planes are disabled.
> @@ -785,7 +785,7 @@ void intel_plane_disable_noatomic(struct intel_crtc *crtc,
> intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe,
> false);
>
> intel_plane_disable_arm(plane, crtc_state);
> - intel_wait_for_vblank(dev_priv, crtc->pipe);
> + intel_crtc_wait_for_next_vblank(crtc);
> }
>
> unsigned int
> @@ -1011,7 +1011,7 @@ bool intel_has_pending_fb_unpin(struct drm_i915_private
> *dev_priv)
> if (cleanup_done)
> continue;
>
> - drm_crtc_wait_one_vblank(crtc);
> + intel_crtc_wait_for_next_vblank(to_intel_crtc(crtc));
>
> return true;
> }
> @@ -1158,7 +1158,7 @@ void hsw_disable_ips(const struct intel_crtc_state
> *crtc_state)
> }
>
> /* We need to wait for a vblank before we can disable the plane. */
> - intel_wait_for_vblank(dev_priv, crtc->pipe);
> + intel_crtc_wait_for_next_vblank(crtc);
> }
>
> static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc)
> @@ -1389,7 +1389,6 @@ static void intel_crtc_disable_flip_done(struct
> intel_atomic_state *state,
> static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state
> *state,
>struct intel_crtc *crtc)
> {
> - struct drm_i915_private *i915 = to_i915(state->base.dev);
> const struct intel_crtc_state *old_crtc_state =
> intel_atomic_get_old_crtc_state(state, crtc);
> const struct intel_crtc_state *new_crtc_state =
> @@ -1415,7 +1414,7 @@ static void intel_crtc_async_flip_disable_wa(struct
> intel_atomic_state *state,
> }
>
> if (need_vbl_wait)
> - intel_wait_for_vblank(i915, crtc->pipe);
> + intel_crtc_wait_for_next_vblank(crtc);
> }
>
> static void intel_pre_plane_update(struct intel_atomic_state *state,
> @@ -1434,7 +1433,7 @@ static void intel_pre_plane_update(struct
> intel_atomic_state *state,
> hsw_disable_ips(old_crtc_state);
>
> if (intel_fbc_pre_update(state, crtc))
> - intel_wait_for_vblank(dev_priv, pipe);
> + intel_crtc_wait_for_next_vblank(crtc);
>
> if (!needs_async_flip_vtd_wa(old_crtc_state) &&
> needs_async_flip_vtd_wa(new_crtc_state))
> @@ -1466,7 +1465,7 @@ static void intel_pre_plane_update(struct
> intel_atomic_state *state,
>*/
> if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
> new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv,
> false))
> - intel_wait_for_vblank(dev_priv, pipe);
> + intel_crtc_wait_for_next_vblank(crtc);
>
> /*
>* IVB workaround: must disable low power watermarks for at least
> @@ -1477,7 +1476,7 @@ static void
Re: [Intel-gfx] [PATCH v2 02/10] drm/i915/crtc: rename intel_get_crtc_for_pipe() to intel_crtc_for_pipe()
On Wed, Dec 01, 2021 at 03:57:04PM +0200, Jani Nikula wrote:
> The "get" in the name implies reference counting, remove it. This also
> makes the function conform to naming style.
>
> Suggested-by: Ville Syrjälä
> Signed-off-by: Jani Nikula
Reviewed-by: Ville Syrjälä
> ---
> .../gpu/drm/i915/display/intel_atomic_plane.c| 2 +-
> drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
> drivers/gpu/drm/i915/display/intel_display.c | 16
> .../gpu/drm/i915/display/intel_display_types.h | 6 +++---
> drivers/gpu/drm/i915/display/intel_dpll.c| 2 +-
> drivers/gpu/drm/i915/display/intel_fdi.c | 4 ++--
> .../gpu/drm/i915/display/intel_fifo_underrun.c | 10 +-
> drivers/gpu/drm/i915/display/intel_sprite.c | 4 ++--
> drivers/gpu/drm/i915/display/intel_vdsc.c| 2 +-
> drivers/gpu/drm/i915/i915_irq.c | 6 +++---
> drivers/gpu/drm/i915/i915_trace.h| 4 ++--
> drivers/gpu/drm/i915/intel_pm.c | 8
> 12 files changed, 33 insertions(+), 33 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index e3a0bfb7be84..27b8f99dd099 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -395,7 +395,7 @@ int intel_plane_atomic_check(struct intel_atomic_state
> *state,
> const struct intel_plane_state *old_plane_state =
> intel_atomic_get_old_plane_state(state, plane);
> const struct intel_plane_state *new_master_plane_state;
> - struct intel_crtc *crtc = intel_get_crtc_for_pipe(i915, plane->pipe);
> + struct intel_crtc *crtc = intel_crtc_for_pipe(i915, plane->pipe);
> const struct intel_crtc_state *old_crtc_state =
> intel_atomic_get_old_crtc_state(state, crtc);
> struct intel_crtc_state *new_crtc_state =
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 91c19e0a98d7..5a475aa52079 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2592,7 +2592,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state
> *state)
> struct intel_crtc_state *crtc_state;
>
> pipe = ilog2(new_cdclk_state->active_pipes);
> - crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> + crtc = intel_crtc_for_pipe(dev_priv, pipe);
>
> crtc_state = intel_atomic_get_crtc_state(>base, crtc);
> if (IS_ERR(crtc_state))
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 503074dc5690..624a7d719531 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -4830,7 +4830,7 @@ intel_encoder_current_mode(struct intel_encoder
> *encoder)
> if (!encoder->get_hw_state(encoder, ))
> return NULL;
>
> - crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> + crtc = intel_crtc_for_pipe(dev_priv, pipe);
>
> mode = kzalloc(sizeof(*mode), GFP_KERNEL);
> if (!mode)
> @@ -8962,8 +8962,8 @@ static void intel_plane_possible_crtcs_init(struct
> drm_i915_private *dev_priv)
> struct intel_plane *plane;
>
> for_each_intel_plane(_priv->drm, plane) {
> - struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
> - plane->pipe);
> + struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv,
> + plane->pipe);
>
> plane->base.possible_crtcs = drm_crtc_mask(>base);
> }
> @@ -9956,7 +9956,7 @@ int intel_modeset_init(struct drm_i915_private *i915)
>
> void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
> {
> - struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> + struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe);
> /* 640x480@60Hz, ~25175 kHz */
> struct dpll clock = {
> .m1 = 18,
> @@ -10029,7 +10029,7 @@ void i830_enable_pipe(struct drm_i915_private
> *dev_priv, enum pipe pipe)
>
> void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
> {
> - struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> + struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe);
>
> drm_dbg_kms(_priv->drm, "disabling pipe %c due to force quirk\n",
> pipe_name(pipe));
> @@ -10081,7 +10081,7 @@ intel_sanitize_plane_mapping(struct drm_i915_private
> *dev_priv)
> "[PLANE:%d:%s] attached to the wrong pipe,
> disabling plane\n",
> plane->base.base.id, plane->base.name);
>
> - plane_crtc =
Re: [Intel-gfx] [PATCH] drm/i915: Force ww lock for i915_gem_object_ggtt_pin_ww, v2.
On Tue, 30 Nov 2021 at 09:21, Maarten Lankhorst
wrote:
>
> We will need the lock to unbind the vma, and wait for bind to complete.
> Remove the special casing for the !ww path, and force ww locking for all.
>
> Changes since v1:
> - Pass err to for_i915_gem_ww handling for -EDEADLK handling.
>
> Signed-off-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/i915/i915_drv.h | 7 ++-
> drivers/gpu/drm/i915/i915_gem.c | 30 ++
> 2 files changed, 28 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 1bfadd9127fc..8322abe194da 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1842,13 +1842,10 @@ i915_gem_object_ggtt_pin_ww(struct
> drm_i915_gem_object *obj,
> const struct i915_ggtt_view *view,
> u64 size, u64 alignment, u64 flags);
>
> -static inline struct i915_vma * __must_check
> +struct i915_vma * __must_check
> i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
> const struct i915_ggtt_view *view,
> -u64 size, u64 alignment, u64 flags)
> -{
> - return i915_gem_object_ggtt_pin_ww(obj, NULL, view, size, alignment,
> flags);
> -}
> +u64 size, u64 alignment, u64 flags);
>
> int i915_gem_object_unbind(struct drm_i915_gem_object *obj,
>unsigned long flags);
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 527228d4da7e..6002045bd194 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -877,6 +877,8 @@ i915_gem_object_ggtt_pin_ww(struct drm_i915_gem_object
> *obj,
> struct i915_vma *vma;
> int ret;
>
> + GEM_WARN_ON(!ww);
Return something here, or GEM_BUG_ON()? I assume it's going to crash
and burn anyway?
> +
> if (flags & PIN_MAPPABLE &&
> (!view || view->type == I915_GGTT_VIEW_NORMAL)) {
> /*
> @@ -936,10 +938,7 @@ i915_gem_object_ggtt_pin_ww(struct drm_i915_gem_object
> *obj,
> return ERR_PTR(ret);
> }
>
> - if (ww)
> - ret = i915_vma_pin_ww(vma, ww, size, alignment, flags |
> PIN_GLOBAL);
> - else
> - ret = i915_vma_pin(vma, size, alignment, flags | PIN_GLOBAL);
> + ret = i915_vma_pin_ww(vma, ww, size, alignment, flags | PIN_GLOBAL);
>
> if (ret)
> return ERR_PTR(ret);
> @@ -959,6 +958,29 @@ i915_gem_object_ggtt_pin_ww(struct drm_i915_gem_object
> *obj,
> return vma;
> }
>
> +struct i915_vma * __must_check
> +i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
> +const struct i915_ggtt_view *view,
> +u64 size, u64 alignment, u64 flags)
> +{
> + struct i915_gem_ww_ctx ww;
> + struct i915_vma *ret;
> + int err;
> +
> + for_i915_gem_ww(, err, true) {
> + err = i915_gem_object_lock(obj, );
> + if (err)
> + continue;
> +
> + ret = i915_gem_object_ggtt_pin_ww(obj, , view, size,
> + alignment, flags);
> + if (IS_ERR(ret))
> + err = PTR_ERR(ret);
Maybe s/ret/vma/ ? Seeing ret makes me think it's an integer.
Anyway,
Reviewed-by: Matthew Auld
> + }
> +
> + return err ? ERR_PTR(err) : ret;
> +}
> +
> int
> i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
>struct drm_file *file_priv)
> --
> 2.34.1
>
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: break intel_display_types.h dependency on i915_drv.h (rev2)
== Series Details ==
Series: drm/i915: break intel_display_types.h dependency on i915_drv.h (rev2)
URL : https://patchwork.freedesktop.org/series/97173/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10949 -> Patchwork_21716
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21716/index.html
Participating hosts (39 -> 32)
--
Additional (2): fi-kbl-soraka fi-jsl-1
Missing(9): fi-rkl-guc bat-dg1-6 bat-dg1-5 fi-bsw-cyan bat-adlp-6
bat-adlp-4 fi-pnv-d510 bat-jsl-2 bat-jsl-1
Known issues
Here are the changes found in Patchwork_21716 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_fence@basic-busy@bcs0:
- fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271]) +8 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21716/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#2190])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21716/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4613]) +3
similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21716/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html
* igt@i915_selftest@live@execlists:
- fi-bsw-nick:[PASS][4] -> [INCOMPLETE][5] ([i915#2940])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10949/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21716/fi-bsw-nick/igt@i915_selftest@l...@execlists.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][6] ([i915#1886] / [i915#2291])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21716/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-soraka: NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827]) +8
similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21716/fi-kbl-soraka/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-soraka: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#533])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21716/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
* igt@runner@aborted:
- fi-bsw-nick:NOTRUN -> [FAIL][9] ([fdo#109271] / [i915#1436] /
[i915#3428] / [i915#4312])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21716/fi-bsw-nick/igt@run...@aborted.html
Possible fixes
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-1115g4: [FAIL][10] ([i915#1888]) -> [PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10949/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21716/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
[i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
Build changes
-
* Linux: CI_DRM_10949 -> Patchwork_21716
CI-20190529: 20190529
CI_DRM_10949: c43a205a07b34ebbf7fe9205454a422147791ef3 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6295: 2d7f671b872ed856a97957051098974be2380019 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21716: c81d16843e499b02a79f5d7d92c74d3219be764b @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
c81d16843e49 drm/i915/display: stop
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] Revert "drm/i915: Implement Wa_1508744258" (rev2)
== Series Details ==
Series: series starting with [1/2] Revert "drm/i915: Implement Wa_1508744258"
(rev2)
URL : https://patchwork.freedesktop.org/series/97105/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10949 -> Patchwork_21715
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21715/index.html
Participating hosts (39 -> 33)
--
Additional (2): fi-kbl-soraka fi-jsl-1
Missing(8): bat-dg1-6 bat-dg1-5 fi-bsw-cyan bat-adlp-6 bat-adlp-4
fi-pnv-d510 bat-jsl-2 bat-jsl-1
Known issues
Here are the changes found in Patchwork_21715 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_fence@basic-busy@bcs0:
- fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271]) +8 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21715/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#2190])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21715/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4613]) +3
similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21715/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][4] ([i915#1886] / [i915#2291])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21715/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-soraka: NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827]) +8
similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21715/fi-kbl-soraka/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cfl-8109u: [PASS][6] -> [DMESG-FAIL][7] ([i915#295])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10949/fi-cfl-8109u/igt@kms_frontbuffer_track...@basic.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21715/fi-cfl-8109u/igt@kms_frontbuffer_track...@basic.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
- fi-cfl-8109u: [PASS][8] -> [DMESG-WARN][9] ([i915#295]) +10 similar
issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10949/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21715/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-soraka: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#533])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21715/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
* igt@kms_psr@primary_page_flip:
- fi-skl-6600u: [PASS][11] -> [INCOMPLETE][12] ([i915#198])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10949/fi-skl-6600u/igt@kms_psr@primary_page_flip.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21715/fi-skl-6600u/igt@kms_psr@primary_page_flip.html
* igt@runner@aborted:
- fi-bdw-5557u: NOTRUN -> [FAIL][13] ([i915#2426] / [i915#4312])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21715/fi-bdw-5557u/igt@run...@aborted.html
Possible fixes
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-1115g4: [FAIL][14] ([i915#1888]) -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10949/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21715/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#4103]:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: break intel_display_types.h dependency on i915_drv.h (rev2)
== Series Details == Series: drm/i915: break intel_display_types.h dependency on i915_drv.h (rev2) URL : https://patchwork.freedesktop.org/series/97173/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: break intel_display_types.h dependency on i915_drv.h (rev2)
== Series Details == Series: drm/i915: break intel_display_types.h dependency on i915_drv.h (rev2) URL : https://patchwork.freedesktop.org/series/97173/ State : warning == Summary == $ dim checkpatch origin/drm-tip e378d10ac676 drm/i915/display: add intel_crtc_wait_for_next_vblank() and use it fe65a94cc935 drm/i915/crtc: rename intel_get_crtc_for_pipe() to intel_crtc_for_pipe() -:294: WARNING:TABSTOP: Statements should start on a tabstop #294: FILE: drivers/gpu/drm/i915/i915_trace.h:112: + struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); -:303: WARNING:TABSTOP: Statements should start on a tabstop #303: FILE: drivers/gpu/drm/i915/i915_trace.h:135: + struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); total: 0 errors, 2 warnings, 0 checks, 252 lines checked 3a537873f52a drm/i915/crtc: rename intel_get_crtc_for_plane() to intel_crtc_for_plane() 020f325604a5 drm/i915/display: remove intel_wait_for_vblank() 2e66240a65d1 drm/i915/crtc: un-inline some crtc functions and move to intel_crtc.[ch] 0b58bbeef964 drm/i915/fb: move intel_fb_uses_dpt to intel_fb.c and un-inline 9e846bc528ce drm/i915: split out intel_pm_types.h -:106: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #106: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 159 lines checked be3ee6847fa0 drm/i915: move enum hpd_pin to intel_display.h -:41: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__pin' - possible side-effects? #41: FILE: drivers/gpu/drm/i915/display/intel_display.h:370: +#define for_each_hpd_pin(__pin) \ + for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++) total: 0 errors, 0 warnings, 1 checks, 60 lines checked 48cc6caf924d drm/i915/display: convert dp_to_i915() to a macro c81d16843e49 drm/i915/display: stop including i915_drv.h from intel_display_types.h
[Intel-gfx] [PATCH v2 10/10] drm/i915/display: stop including i915_drv.h from intel_display_types.h
Break the dependency on i915_drv.h.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display_types.h| 9 -
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c | 1 +
drivers/gpu/drm/i915/display/intel_dp_link_training.c | 2 +-
drivers/gpu/drm/i915/display/intel_dsi.c | 2 ++
drivers/gpu/drm/i915/display/intel_fb.c | 1 +
drivers/gpu/drm/i915/display/intel_fb_pin.c | 10 +-
drivers/gpu/drm/i915/display/intel_plane_initial.c| 5 +++--
drivers/gpu/drm/i915/display/intel_quirks.c | 1 +
8 files changed, 22 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index f6e76b4d377d..974af6c01cca 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -36,6 +36,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -46,13 +47,19 @@
#include
#include
-#include "i915_drv.h"
+#include "i915_vma.h"
+#include "i915_vma_types.h"
+#include "intel_bios.h"
+#include "intel_display.h"
+#include "intel_display_power.h"
+#include "intel_dpll_mgr.h"
#include "intel_pm_types.h"
struct drm_printer;
struct __intel_global_objs_state;
struct intel_ddi_buf_trans;
struct intel_fbc;
+struct intel_connector;
/*
* Display related stuff
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index 62c112daacf2..97cf3cac0105 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -34,6 +34,7 @@
* for some reason.
*/
+#include "i915_drv.h"
#include "intel_backlight.h"
#include "intel_display_types.h"
#include "intel_dp.h"
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index e264467de8ed..9451f336f28f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -21,11 +21,11 @@
* IN THE SOFTWARE.
*/
+#include "i915_drv.h"
#include "intel_display_types.h"
#include "intel_dp.h"
#include "intel_dp_link_training.h"
-
static void intel_dp_reset_lttpr_common_caps(struct intel_dp *intel_dp)
{
memset(intel_dp->lttpr_common_caps, 0,
sizeof(intel_dp->lttpr_common_caps));
diff --git a/drivers/gpu/drm/i915/display/intel_dsi.c
b/drivers/gpu/drm/i915/display/intel_dsi.c
index 6b0301ba046e..a50422e03a7e 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi.c
@@ -4,6 +4,8 @@
*/
#include
+
+#include "i915_drv.h"
#include "intel_dsi.h"
#include "intel_panel.h"
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
b/drivers/gpu/drm/i915/display/intel_fb.c
index 99769132c35b..23cfe2e5ce2a 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -6,6 +6,7 @@
#include
#include
+#include "i915_drv.h"
#include "intel_display.h"
#include "intel_display_types.h"
#include "intel_dpt.h"
diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c
b/drivers/gpu/drm/i915/display/intel_fb_pin.c
index 3b20f69e0240..31c15e5fca95 100644
--- a/drivers/gpu/drm/i915/display/intel_fb_pin.c
+++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c
@@ -7,13 +7,13 @@
* DOC: display pinning helpers
*/
-#include "intel_display_types.h"
-#include "intel_fb_pin.h"
-#include "intel_fb.h"
+#include "gem/i915_gem_object.h"
+#include "i915_drv.h"
+#include "intel_display_types.h"
#include "intel_dpt.h"
-
-#include "gem/i915_gem_object.h"
+#include "intel_fb.h"
+#include "intel_fb_pin.h"
static struct i915_vma *
intel_pin_fb_obj_dpt(struct drm_framebuffer *fb,
diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c
b/drivers/gpu/drm/i915/display/intel_plane_initial.c
index dcd698a02da2..01ce1d72297f 100644
--- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
+++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
@@ -3,11 +3,12 @@
* Copyright © 2021 Intel Corporation
*/
-#include "intel_display_types.h"
-#include "intel_plane_initial.h"
+#include "i915_drv.h"
#include "intel_atomic_plane.h"
#include "intel_display.h"
+#include "intel_display_types.h"
#include "intel_fb.h"
+#include "intel_plane_initial.h"
static bool
intel_reuse_initial_plane_obj(struct drm_i915_private *i915,
diff --git a/drivers/gpu/drm/i915/display/intel_quirks.c
b/drivers/gpu/drm/i915/display/intel_quirks.c
index 8a52b7a16774..c8488f5ebd04 100644
--- a/drivers/gpu/drm/i915/display/intel_quirks.c
+++ b/drivers/gpu/drm/i915/display/intel_quirks.c
@@ -5,6 +5,7 @@
#include
+#include "i915_drv.h"
#include "intel_display_types.h"
#include "intel_quirks.h"
--
2.30.2
[Intel-gfx] [PATCH v2 09/10] drm/i915/display: convert dp_to_i915() to a macro
Avoid looking into the guts of struct drm_i915_private in
headers. Again, converting an inline function to a macro is less than
ideal, but avoids having to pull in i915_drv.h just for the to_i915()
part.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display_types.h | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 14b4c3bb6030..f6e76b4d377d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1883,11 +1883,7 @@ dp_to_lspcon(struct intel_dp *intel_dp)
return _to_dig_port(intel_dp)->lspcon;
}
-static inline struct drm_i915_private *
-dp_to_i915(struct intel_dp *intel_dp)
-{
- return to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
-}
+#define dp_to_i915(__intel_dp)
to_i915(dp_to_dig_port(__intel_dp)->base.base.dev)
#define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \
(intel_dp)->psr.source_support)
--
2.30.2
[Intel-gfx] [PATCH v2 08/10] drm/i915: move enum hpd_pin to intel_display.h
It's not the ideal location, but a better alternative than
i915_drv.h. The goal is to break the intel_display_types.h to i915_drv.h
dependency.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.h | 24
drivers/gpu/drm/i915/i915_drv.h | 24
2 files changed, 24 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index 38c15ec30ee7..8d8725b45d99 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -346,6 +346,30 @@ enum phy_fia {
FIA3,
};
+enum hpd_pin {
+ HPD_NONE = 0,
+ HPD_TV = HPD_NONE, /* TV is known to be unreliable */
+ HPD_CRT,
+ HPD_SDVO_B,
+ HPD_SDVO_C,
+ HPD_PORT_A,
+ HPD_PORT_B,
+ HPD_PORT_C,
+ HPD_PORT_D,
+ HPD_PORT_E,
+ HPD_PORT_TC1,
+ HPD_PORT_TC2,
+ HPD_PORT_TC3,
+ HPD_PORT_TC4,
+ HPD_PORT_TC5,
+ HPD_PORT_TC6,
+
+ HPD_NUM_PINS
+};
+
+#define for_each_hpd_pin(__pin) \
+ for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
+
#define for_each_pipe(__dev_priv, __p) \
for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \
for_each_if(INTEL_INFO(__dev_priv)->pipe_mask & BIT(__p))
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e2ccc0696df7..27677bb18a6b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -117,30 +117,6 @@
struct drm_i915_gem_object;
-enum hpd_pin {
- HPD_NONE = 0,
- HPD_TV = HPD_NONE, /* TV is known to be unreliable */
- HPD_CRT,
- HPD_SDVO_B,
- HPD_SDVO_C,
- HPD_PORT_A,
- HPD_PORT_B,
- HPD_PORT_C,
- HPD_PORT_D,
- HPD_PORT_E,
- HPD_PORT_TC1,
- HPD_PORT_TC2,
- HPD_PORT_TC3,
- HPD_PORT_TC4,
- HPD_PORT_TC5,
- HPD_PORT_TC6,
-
- HPD_NUM_PINS
-};
-
-#define for_each_hpd_pin(__pin) \
- for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
-
/* Threshold == 5 for long IRQs, 50 for short */
#define HPD_STORM_DEFAULT_THRESHOLD 50
--
2.30.2
[Intel-gfx] [PATCH v2 07/10] drm/i915: split out intel_pm_types.h
This is far from ideal, but it reduces the i915_drv.h dependency from
intel_display_types.h. Maybe in the future we'll need a better split.
Signed-off-by: Jani Nikula
---
.../drm/i915/display/intel_display_types.h| 1 +
drivers/gpu/drm/i915/i915_drv.h | 64 +---
drivers/gpu/drm/i915/intel_pm_types.h | 76 +++
3 files changed, 78 insertions(+), 63 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_pm_types.h
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 5f077e8cea33..14b4c3bb6030 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -47,6 +47,7 @@
#include
#include "i915_drv.h"
+#include "intel_pm_types.h"
struct drm_printer;
struct __intel_global_objs_state;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1bfadd9127fc..e2ccc0696df7 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -89,6 +89,7 @@
#include "intel_device_info.h"
#include "intel_memory_region.h"
#include "intel_pch.h"
+#include "intel_pm_types.h"
#include "intel_runtime_pm.h"
#include "intel_step.h"
#include "intel_uncore.h"
@@ -730,69 +731,6 @@ struct intel_vbt_data {
struct sdvo_device_mapping sdvo_mappings[2];
};
-enum intel_ddb_partitioning {
- INTEL_DDB_PART_1_2,
- INTEL_DDB_PART_5_6, /* IVB+ */
-};
-
-struct ilk_wm_values {
- u32 wm_pipe[3];
- u32 wm_lp[3];
- u32 wm_lp_spr[3];
- bool enable_fbc_wm;
- enum intel_ddb_partitioning partitioning;
-};
-
-struct g4x_pipe_wm {
- u16 plane[I915_MAX_PLANES];
- u16 fbc;
-};
-
-struct g4x_sr_wm {
- u16 plane;
- u16 cursor;
- u16 fbc;
-};
-
-struct vlv_wm_ddl_values {
- u8 plane[I915_MAX_PLANES];
-};
-
-struct vlv_wm_values {
- struct g4x_pipe_wm pipe[3];
- struct g4x_sr_wm sr;
- struct vlv_wm_ddl_values ddl[3];
- u8 level;
- bool cxsr;
-};
-
-struct g4x_wm_values {
- struct g4x_pipe_wm pipe[2];
- struct g4x_sr_wm sr;
- struct g4x_sr_wm hpll;
- bool cxsr;
- bool hpll_en;
- bool fbc_en;
-};
-
-struct skl_ddb_entry {
- u16 start, end; /* in number of blocks, 'end' is exclusive */
-};
-
-static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry)
-{
- return entry->end - entry->start;
-}
-
-static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
- const struct skl_ddb_entry *e2)
-{
- if (e1->start == e2->start && e1->end == e2->end)
- return true;
-
- return false;
-}
-
struct i915_frontbuffer_tracking {
spinlock_t lock;
diff --git a/drivers/gpu/drm/i915/intel_pm_types.h
b/drivers/gpu/drm/i915/intel_pm_types.h
new file mode 100644
index ..211632f58751
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_pm_types.h
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#ifndef __INTEL_PM_TYPES_H__
+#define __INTEL_PM_TYPES_H__
+
+#include
+
+#include "display/intel_display.h"
+
+enum intel_ddb_partitioning {
+ INTEL_DDB_PART_1_2,
+ INTEL_DDB_PART_5_6, /* IVB+ */
+};
+
+struct ilk_wm_values {
+ u32 wm_pipe[3];
+ u32 wm_lp[3];
+ u32 wm_lp_spr[3];
+ bool enable_fbc_wm;
+ enum intel_ddb_partitioning partitioning;
+};
+
+struct g4x_pipe_wm {
+ u16 plane[I915_MAX_PLANES];
+ u16 fbc;
+};
+
+struct g4x_sr_wm {
+ u16 plane;
+ u16 cursor;
+ u16 fbc;
+};
+
+struct vlv_wm_ddl_values {
+ u8 plane[I915_MAX_PLANES];
+};
+
+struct vlv_wm_values {
+ struct g4x_pipe_wm pipe[3];
+ struct g4x_sr_wm sr;
+ struct vlv_wm_ddl_values ddl[3];
+ u8 level;
+ bool cxsr;
+};
+
+struct g4x_wm_values {
+ struct g4x_pipe_wm pipe[2];
+ struct g4x_sr_wm sr;
+ struct g4x_sr_wm hpll;
+ bool cxsr;
+ bool hpll_en;
+ bool fbc_en;
+};
+
+struct skl_ddb_entry {
+ u16 start, end; /* in number of blocks, 'end' is exclusive */
+};
+
+static inline u16 skl_ddb_entry_size(const struct skl_ddb_entry *entry)
+{
+ return entry->end - entry->start;
+}
+
+static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
+ const struct skl_ddb_entry *e2)
+{
+ if (e1->start == e2->start && e1->end == e2->end)
+ return true;
+
+ return false;
+}
+
+#endif /* __INTEL_PM_TYPES_H__ */
--
2.30.2
[Intel-gfx] [PATCH v2 06/10] drm/i915/fb: move intel_fb_uses_dpt to intel_fb.c and un-inline
Move fb functions where they belong, and un-inline to avoid looking into
struct drm_i915_private guts in header files.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display_types.h | 10 --
drivers/gpu/drm/i915/display/intel_fb.c| 10 ++
drivers/gpu/drm/i915/display/intel_fb.h| 2 ++
3 files changed, 12 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index eeaaa101a7b6..5f077e8cea33 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1990,16 +1990,6 @@ intel_crtc_needs_modeset(const struct intel_crtc_state
*crtc_state)
return drm_atomic_crtc_needs_modeset(_state->uapi);
}
-static inline bool intel_modifier_uses_dpt(struct drm_i915_private *i915, u64
modifier)
-{
- return DISPLAY_VER(i915) >= 13 && modifier != DRM_FORMAT_MOD_LINEAR;
-}
-
-static inline bool intel_fb_uses_dpt(const struct drm_framebuffer *fb)
-{
- return fb && intel_modifier_uses_dpt(to_i915(fb->dev), fb->modifier);
-}
-
static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state
*plane_state)
{
return i915_ggtt_offset(plane_state->ggtt_vma);
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
b/drivers/gpu/drm/i915/display/intel_fb.c
index c4a743d0913f..99769132c35b 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -658,6 +658,16 @@ static unsigned int intel_fb_modifier_to_tiling(u64
fb_modifier)
}
}
+static bool intel_modifier_uses_dpt(struct drm_i915_private *i915, u64
modifier)
+{
+ return DISPLAY_VER(i915) >= 13 && modifier != DRM_FORMAT_MOD_LINEAR;
+}
+
+bool intel_fb_uses_dpt(const struct drm_framebuffer *fb)
+{
+ return fb && intel_modifier_uses_dpt(to_i915(fb->dev), fb->modifier);
+}
+
unsigned int intel_cursor_alignment(const struct drm_i915_private *i915)
{
if (IS_I830(i915))
diff --git a/drivers/gpu/drm/i915/display/intel_fb.h
b/drivers/gpu/drm/i915/display/intel_fb.h
index b54997175d6d..ba9df8986c1e 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.h
+++ b/drivers/gpu/drm/i915/display/intel_fb.h
@@ -90,4 +90,6 @@ intel_user_framebuffer_create(struct drm_device *dev,
struct drm_file *filp,
const struct drm_mode_fb_cmd2 *user_mode_cmd);
+bool intel_fb_uses_dpt(const struct drm_framebuffer *fb);
+
#endif /* __INTEL_FB_H__ */
--
2.30.2
[Intel-gfx] [PATCH v2 05/10] drm/i915/crtc: un-inline some crtc functions and move to intel_crtc.[ch]
Move a number of crtc/pipe related functions to intel_crtc.[ch], and
un-inline to avoid looking into struct drm_i915_private guts in header
files.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_crtc.c | 42 ++
drivers/gpu/drm/i915/display/intel_crtc.h | 10 +
.../drm/i915/display/intel_display_types.h| 44 ---
3 files changed, 52 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c
b/drivers/gpu/drm/i915/display/intel_crtc.c
index 243d5cc29734..43554b591904 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -36,6 +36,48 @@ static void assert_vblank_disabled(struct drm_crtc *crtc)
drm_crtc_vblank_put(crtc);
}
+bool intel_pipe_valid(struct drm_i915_private *i915, enum pipe pipe)
+{
+ return (pipe >= 0 &&
+ pipe < ARRAY_SIZE(i915->pipe_to_crtc_mapping) &&
+ INTEL_INFO(i915)->pipe_mask & BIT(pipe) &&
+ i915->pipe_to_crtc_mapping[pipe]);
+}
+
+struct intel_crtc *intel_get_first_crtc(struct drm_i915_private *i915)
+{
+ return to_intel_crtc(drm_crtc_from_index(>drm, 0));
+}
+
+struct intel_crtc *intel_crtc_for_pipe(struct drm_i915_private *i915,
+ enum pipe pipe)
+{
+ /* pipe_to_crtc_mapping may have hole on any of 3 display pipe system */
+ drm_WARN_ON(>drm,
+ !(INTEL_INFO(i915)->pipe_mask & BIT(pipe)));
+ return i915->pipe_to_crtc_mapping[pipe];
+}
+
+struct intel_crtc *intel_crtc_for_plane(struct drm_i915_private *i915,
+ enum i9xx_plane_id plane)
+{
+ return i915->plane_to_crtc_mapping[plane];
+}
+
+void intel_crtc_wait_for_next_vblank(struct intel_crtc *crtc)
+{
+ drm_crtc_wait_one_vblank(>base);
+}
+
+void intel_wait_for_vblank_if_active(struct drm_i915_private *i915,
+enum pipe pipe)
+{
+ struct intel_crtc *crtc = intel_crtc_for_pipe(i915, pipe);
+
+ if (crtc->active)
+ intel_crtc_wait_for_next_vblank(crtc);
+}
+
u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
{
struct drm_device *dev = crtc->base.dev;
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.h
b/drivers/gpu/drm/i915/display/intel_crtc.h
index a0039fdb1eb0..23110e91ecd6 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.h
+++ b/drivers/gpu/drm/i915/display/intel_crtc.h
@@ -8,6 +8,7 @@
#include
+enum i9xx_plane_id;
enum pipe;
struct drm_display_mode;
struct drm_i915_private;
@@ -28,5 +29,14 @@ void intel_crtc_vblank_off(const struct intel_crtc_state
*crtc_state);
void intel_pipe_update_start(struct intel_crtc_state *new_crtc_state);
void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state);
void intel_wait_for_vblank_workers(struct intel_atomic_state *state);
+bool intel_pipe_valid(struct drm_i915_private *i915, enum pipe pipe);
+struct intel_crtc *intel_get_first_crtc(struct drm_i915_private *i915);
+struct intel_crtc *intel_crtc_for_pipe(struct drm_i915_private *i915,
+ enum pipe pipe);
+struct intel_crtc *intel_crtc_for_plane(struct drm_i915_private *i915,
+ enum i9xx_plane_id plane);
+void intel_wait_for_vblank_if_active(struct drm_i915_private *i915,
+enum pipe pipe);
+void intel_crtc_wait_for_next_vblank(struct intel_crtc *crtc);
#endif
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index a48dfd1474dd..eeaaa101a7b6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1773,35 +1773,6 @@ vlv_pipe_to_channel(enum pipe pipe)
}
}
-static inline bool intel_pipe_valid(struct drm_i915_private *i915, enum pipe
pipe)
-{
- return (pipe >= 0 &&
- pipe < ARRAY_SIZE(i915->pipe_to_crtc_mapping) &&
- INTEL_INFO(i915)->pipe_mask & BIT(pipe) &&
- i915->pipe_to_crtc_mapping[pipe]);
-}
-
-static inline struct intel_crtc *
-intel_get_first_crtc(struct drm_i915_private *dev_priv)
-{
- return to_intel_crtc(drm_crtc_from_index(_priv->drm, 0));
-}
-
-static inline struct intel_crtc *
-intel_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
-{
- /* pipe_to_crtc_mapping may have hole on any of 3 display pipe system */
- drm_WARN_ON(_priv->drm,
- !(INTEL_INFO(dev_priv)->pipe_mask & BIT(pipe)));
- return dev_priv->pipe_to_crtc_mapping[pipe];
-}
-
-static inline struct intel_crtc *
-intel_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id
plane)
-{
- return dev_priv->plane_to_crtc_mapping[plane];
-}
-
struct intel_load_detect_pipe {
struct drm_atomic_state *restore_state;
};
@@ -2019,21 +1990,6 @@
[Intel-gfx] [PATCH v2 04/10] drm/i915/display: remove intel_wait_for_vblank()
There are only three call sites remaining for
intel_wait_for_vblank(). Remove the function, and open code it to avoid
new users from showing up.
v2:
- Use intel_crtc_wait_for_next_vblank() (Ville)
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
drivers/gpu/drm/i915/display/intel_crt.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 8 ++--
drivers/gpu/drm/i915/display/intel_display_types.h | 8
4 files changed, 8 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 5a475aa52079..986fb9ba750e 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1690,7 +1690,7 @@ static void bxt_set_cdclk(struct drm_i915_private
*dev_priv,
intel_de_write(dev_priv, CDCLK_CTL, val);
if (pipe != INVALID_PIPE)
- intel_wait_for_vblank(dev_priv, pipe);
+ intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv,
pipe));
if (DISPLAY_VER(dev_priv) >= 11) {
ret = sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c
b/drivers/gpu/drm/i915/display/intel_crt.c
index 42533e6457b5..6a3893c8ff22 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -721,7 +721,7 @@ intel_crt_load_detect(struct intel_crt *crt, u32 pipe)
intel_uncore_posting_read(uncore, pipeconf_reg);
/* Wait for next Vblank to substitue
* border color for Color info */
- intel_wait_for_vblank(dev_priv, pipe);
+ intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv,
pipe));
st00 = intel_uncore_read8(uncore, _VGA_MSR_WRITE);
status = ((st00 & (1 << 4)) != 0) ?
connector_status_connected :
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 624a7d719531..09f088e6272b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2101,8 +2101,12 @@ static void hsw_crtc_enable(struct intel_atomic_state
*state,
* to change the workaround. */
hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe;
if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
- intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
- intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
+ struct intel_crtc *wa_crtc;
+
+ wa_crtc = intel_crtc_for_pipe(dev_priv, hsw_workaround_pipe);
+
+ intel_crtc_wait_for_next_vblank(wa_crtc);
+ intel_crtc_wait_for_next_vblank(wa_crtc);
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 036f9be3045d..a48dfd1474dd 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -2025,14 +2025,6 @@ intel_crtc_wait_for_next_vblank(struct intel_crtc *crtc)
drm_crtc_wait_one_vblank(>base);
}
-static inline void
-intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
-{
- struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe);
-
- intel_crtc_wait_for_next_vblank(crtc);
-}
-
static inline void
intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, enum pipe
pipe)
{
--
2.30.2
[Intel-gfx] [PATCH v2 03/10] drm/i915/crtc: rename intel_get_crtc_for_plane() to intel_crtc_for_plane()
The "get" in the name implies reference counting, remove it. This also
makes the function conform to naming style.
Suggested-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display_types.h | 2 +-
drivers/gpu/drm/i915/intel_pm.c| 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 8009bcfa1a38..036f9be3045d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1797,7 +1797,7 @@ intel_crtc_for_pipe(struct drm_i915_private *dev_priv,
enum pipe pipe)
}
static inline struct intel_crtc *
-intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id
plane)
+intel_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id
plane)
{
return dev_priv->plane_to_crtc_mapping[plane];
}
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index fadcd8af5452..ed760627aa6f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2357,7 +2357,7 @@ static void i9xx_update_wm(struct drm_i915_private
*dev_priv)
fifo_size = i830_get_fifo_size(dev_priv, PLANE_A);
else
fifo_size = i9xx_get_fifo_size(dev_priv, PLANE_A);
- crtc = intel_get_crtc_for_plane(dev_priv, PLANE_A);
+ crtc = intel_crtc_for_plane(dev_priv, PLANE_A);
if (intel_crtc_active(crtc)) {
const struct drm_display_mode *pipe_mode =
>config->hw.pipe_mode;
@@ -2387,7 +2387,7 @@ static void i9xx_update_wm(struct drm_i915_private
*dev_priv)
fifo_size = i830_get_fifo_size(dev_priv, PLANE_B);
else
fifo_size = i9xx_get_fifo_size(dev_priv, PLANE_B);
- crtc = intel_get_crtc_for_plane(dev_priv, PLANE_B);
+ crtc = intel_crtc_for_plane(dev_priv, PLANE_B);
if (intel_crtc_active(crtc)) {
const struct drm_display_mode *pipe_mode =
>config->hw.pipe_mode;
--
2.30.2
[Intel-gfx] [PATCH v2 02/10] drm/i915/crtc: rename intel_get_crtc_for_pipe() to intel_crtc_for_pipe()
The "get" in the name implies reference counting, remove it. This also
makes the function conform to naming style.
Suggested-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
.../gpu/drm/i915/display/intel_atomic_plane.c| 2 +-
drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 16
.../gpu/drm/i915/display/intel_display_types.h | 6 +++---
drivers/gpu/drm/i915/display/intel_dpll.c| 2 +-
drivers/gpu/drm/i915/display/intel_fdi.c | 4 ++--
.../gpu/drm/i915/display/intel_fifo_underrun.c | 10 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 4 ++--
drivers/gpu/drm/i915/display/intel_vdsc.c| 2 +-
drivers/gpu/drm/i915/i915_irq.c | 6 +++---
drivers/gpu/drm/i915/i915_trace.h| 4 ++--
drivers/gpu/drm/i915/intel_pm.c | 8
12 files changed, 33 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index e3a0bfb7be84..27b8f99dd099 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -395,7 +395,7 @@ int intel_plane_atomic_check(struct intel_atomic_state
*state,
const struct intel_plane_state *old_plane_state =
intel_atomic_get_old_plane_state(state, plane);
const struct intel_plane_state *new_master_plane_state;
- struct intel_crtc *crtc = intel_get_crtc_for_pipe(i915, plane->pipe);
+ struct intel_crtc *crtc = intel_crtc_for_pipe(i915, plane->pipe);
const struct intel_crtc_state *old_crtc_state =
intel_atomic_get_old_crtc_state(state, crtc);
struct intel_crtc_state *new_crtc_state =
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 91c19e0a98d7..5a475aa52079 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2592,7 +2592,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state
*state)
struct intel_crtc_state *crtc_state;
pipe = ilog2(new_cdclk_state->active_pipes);
- crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
+ crtc = intel_crtc_for_pipe(dev_priv, pipe);
crtc_state = intel_atomic_get_crtc_state(>base, crtc);
if (IS_ERR(crtc_state))
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 503074dc5690..624a7d719531 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4830,7 +4830,7 @@ intel_encoder_current_mode(struct intel_encoder *encoder)
if (!encoder->get_hw_state(encoder, ))
return NULL;
- crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
+ crtc = intel_crtc_for_pipe(dev_priv, pipe);
mode = kzalloc(sizeof(*mode), GFP_KERNEL);
if (!mode)
@@ -8962,8 +8962,8 @@ static void intel_plane_possible_crtcs_init(struct
drm_i915_private *dev_priv)
struct intel_plane *plane;
for_each_intel_plane(_priv->drm, plane) {
- struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
- plane->pipe);
+ struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv,
+ plane->pipe);
plane->base.possible_crtcs = drm_crtc_mask(>base);
}
@@ -9956,7 +9956,7 @@ int intel_modeset_init(struct drm_i915_private *i915)
void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
{
- struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
+ struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe);
/* 640x480@60Hz, ~25175 kHz */
struct dpll clock = {
.m1 = 18,
@@ -10029,7 +10029,7 @@ void i830_enable_pipe(struct drm_i915_private
*dev_priv, enum pipe pipe)
void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
{
- struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
+ struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe);
drm_dbg_kms(_priv->drm, "disabling pipe %c due to force quirk\n",
pipe_name(pipe));
@@ -10081,7 +10081,7 @@ intel_sanitize_plane_mapping(struct drm_i915_private
*dev_priv)
"[PLANE:%d:%s] attached to the wrong pipe,
disabling plane\n",
plane->base.base.id, plane->base.name);
- plane_crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
+ plane_crtc = intel_crtc_for_pipe(dev_priv, pipe);
intel_plane_disable_noatomic(plane_crtc, plane);
}
}
@@ -10334,7 +10334,7 @@ static void
[Intel-gfx] [PATCH v2 01/10] drm/i915/display: add intel_crtc_wait_for_next_vblank() and use it
intel_wait_for_vblank() goes through a pipe to crtc lookup, while in
most cases we already have the crtc available. Avoid the extra lookups
by adding an intel_crtc based helper.
v2:
- Add intel_crtc_wait_for_next_vblank() helper (Ville)
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_crt.c | 4 +--
drivers/gpu/drm/i915/display/intel_display.c | 32 +--
.../drm/i915/display/intel_display_types.h| 12 +--
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
drivers/gpu/drm/i915/display/intel_sdvo.c | 2 +-
drivers/gpu/drm/i915/display/intel_tv.c | 7 ++--
6 files changed, 32 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c
b/drivers/gpu/drm/i915/display/intel_crt.c
index f0f28572dfdc..42533e6457b5 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -321,8 +321,8 @@ static void hsw_enable_crt(struct intel_atomic_state *state,
intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON);
- intel_wait_for_vblank(dev_priv, pipe);
- intel_wait_for_vblank(dev_priv, pipe);
+ intel_crtc_wait_for_next_vblank(crtc);
+ intel_crtc_wait_for_next_vblank(crtc);
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 4b065a281d69..503074dc5690 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -775,7 +775,7 @@ void intel_plane_disable_noatomic(struct intel_crtc *crtc,
*/
if (HAS_GMCH(dev_priv) &&
intel_set_memory_cxsr(dev_priv, false))
- intel_wait_for_vblank(dev_priv, crtc->pipe);
+ intel_crtc_wait_for_next_vblank(crtc);
/*
* Gen2 reports pipe underruns whenever all planes are disabled.
@@ -785,7 +785,7 @@ void intel_plane_disable_noatomic(struct intel_crtc *crtc,
intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe,
false);
intel_plane_disable_arm(plane, crtc_state);
- intel_wait_for_vblank(dev_priv, crtc->pipe);
+ intel_crtc_wait_for_next_vblank(crtc);
}
unsigned int
@@ -1011,7 +1011,7 @@ bool intel_has_pending_fb_unpin(struct drm_i915_private
*dev_priv)
if (cleanup_done)
continue;
- drm_crtc_wait_one_vblank(crtc);
+ intel_crtc_wait_for_next_vblank(to_intel_crtc(crtc));
return true;
}
@@ -1158,7 +1158,7 @@ void hsw_disable_ips(const struct intel_crtc_state
*crtc_state)
}
/* We need to wait for a vblank before we can disable the plane. */
- intel_wait_for_vblank(dev_priv, crtc->pipe);
+ intel_crtc_wait_for_next_vblank(crtc);
}
static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc)
@@ -1389,7 +1389,6 @@ static void intel_crtc_disable_flip_done(struct
intel_atomic_state *state,
static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
- struct drm_i915_private *i915 = to_i915(state->base.dev);
const struct intel_crtc_state *old_crtc_state =
intel_atomic_get_old_crtc_state(state, crtc);
const struct intel_crtc_state *new_crtc_state =
@@ -1415,7 +1414,7 @@ static void intel_crtc_async_flip_disable_wa(struct
intel_atomic_state *state,
}
if (need_vbl_wait)
- intel_wait_for_vblank(i915, crtc->pipe);
+ intel_crtc_wait_for_next_vblank(crtc);
}
static void intel_pre_plane_update(struct intel_atomic_state *state,
@@ -1434,7 +1433,7 @@ static void intel_pre_plane_update(struct
intel_atomic_state *state,
hsw_disable_ips(old_crtc_state);
if (intel_fbc_pre_update(state, crtc))
- intel_wait_for_vblank(dev_priv, pipe);
+ intel_crtc_wait_for_next_vblank(crtc);
if (!needs_async_flip_vtd_wa(old_crtc_state) &&
needs_async_flip_vtd_wa(new_crtc_state))
@@ -1466,7 +1465,7 @@ static void intel_pre_plane_update(struct
intel_atomic_state *state,
*/
if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv,
false))
- intel_wait_for_vblank(dev_priv, pipe);
+ intel_crtc_wait_for_next_vblank(crtc);
/*
* IVB workaround: must disable low power watermarks for at least
@@ -1477,7 +1476,7 @@ static void intel_pre_plane_update(struct
intel_atomic_state *state,
*/
if (old_crtc_state->hw.active &&
new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv))
- intel_wait_for_vblank(dev_priv, pipe);
+
[Intel-gfx] [PATCH v2 00/10] drm/i915: break intel_display_types.h dependency on i915_drv.h
v2 of https://patchwork.freedesktop.org/series/97173/ BR, Jani. Jani Nikula (10): drm/i915/display: add intel_crtc_wait_for_next_vblank() and use it drm/i915/crtc: rename intel_get_crtc_for_pipe() to intel_crtc_for_pipe() drm/i915/crtc: rename intel_get_crtc_for_plane() to intel_crtc_for_plane() drm/i915/display: remove intel_wait_for_vblank() drm/i915/crtc: un-inline some crtc functions and move to intel_crtc.[ch] drm/i915/fb: move intel_fb_uses_dpt to intel_fb.c and un-inline drm/i915: split out intel_pm_types.h drm/i915: move enum hpd_pin to intel_display.h drm/i915/display: convert dp_to_i915() to a macro drm/i915/display: stop including i915_drv.h from intel_display_types.h .../gpu/drm/i915/display/intel_atomic_plane.c | 2 +- drivers/gpu/drm/i915/display/intel_cdclk.c| 4 +- drivers/gpu/drm/i915/display/intel_crt.c | 6 +- drivers/gpu/drm/i915/display/intel_crtc.c | 42 + drivers/gpu/drm/i915/display/intel_crtc.h | 10 +++ drivers/gpu/drm/i915/display/intel_display.c | 56 ++-- drivers/gpu/drm/i915/display/intel_display.h | 24 + .../drm/i915/display/intel_display_types.h| 72 +++ drivers/gpu/drm/i915/display/intel_dp.c | 2 +- .../drm/i915/display/intel_dp_aux_backlight.c | 1 + .../drm/i915/display/intel_dp_link_training.c | 2 +- drivers/gpu/drm/i915/display/intel_dpll.c | 2 +- drivers/gpu/drm/i915/display/intel_dsi.c | 2 + drivers/gpu/drm/i915/display/intel_fb.c | 11 +++ drivers/gpu/drm/i915/display/intel_fb.h | 2 + drivers/gpu/drm/i915/display/intel_fb_pin.c | 10 +-- drivers/gpu/drm/i915/display/intel_fdi.c | 4 +- .../drm/i915/display/intel_fifo_underrun.c| 10 +-- .../drm/i915/display/intel_plane_initial.c| 5 +- drivers/gpu/drm/i915/display/intel_quirks.c | 1 + drivers/gpu/drm/i915/display/intel_sdvo.c | 2 +- drivers/gpu/drm/i915/display/intel_sprite.c | 4 +- drivers/gpu/drm/i915/display/intel_tv.c | 7 +- drivers/gpu/drm/i915/display/intel_vdsc.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 88 +-- drivers/gpu/drm/i915/i915_irq.c | 6 +- drivers/gpu/drm/i915/i915_trace.h | 4 +- drivers/gpu/drm/i915/intel_pm.c | 12 +-- drivers/gpu/drm/i915/intel_pm_types.h | 76 29 files changed, 252 insertions(+), 217 deletions(-) create mode 100644 drivers/gpu/drm/i915/intel_pm_types.h -- 2.30.2
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/adl_p: Add adl-p ddc pin mapping (rev2)
== Series Details == Series: drm/i915/adl_p: Add adl-p ddc pin mapping (rev2) URL : https://patchwork.freedesktop.org/series/97009/ State : success == Summary == CI Bug Log - changes from CI_DRM_10949 -> Patchwork_21714 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21714/index.html Participating hosts (39 -> 34) -- Additional (3): fi-kbl-soraka fi-jsl-1 fi-icl-u2 Missing(8): bat-dg1-6 bat-dg1-5 fi-bsw-cyan bat-adlp-6 bat-adlp-4 fi-pnv-d510 bat-jsl-2 bat-jsl-1 Known issues Here are the changes found in Patchwork_21714 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@cs-gfx: - fi-rkl-guc: NOTRUN -> [SKIP][1] ([fdo#109315]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21714/fi-rkl-guc/igt@amdgpu/amd_ba...@cs-gfx.html * igt@amdgpu/amd_cs_nop@fork-gfx0: - fi-icl-u2: NOTRUN -> [SKIP][2] ([fdo#109315]) +17 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21714/fi-icl-u2/igt@amdgpu/amd_cs_...@fork-gfx0.html * igt@gem_exec_fence@basic-busy@bcs0: - fi-kbl-soraka: NOTRUN -> [SKIP][3] ([fdo#109271]) +8 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21714/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html * igt@gem_huc_copy@huc-copy: - fi-kbl-soraka: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21714/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html - fi-icl-u2: NOTRUN -> [SKIP][5] ([i915#2190]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21714/fi-icl-u2/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-kbl-soraka: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#4613]) +3 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21714/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html * igt@gem_lmem_swapping@parallel-random-engines: - fi-icl-u2: NOTRUN -> [SKIP][7] ([i915#4613]) +3 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21714/fi-icl-u2/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@i915_selftest@live@gt_pm: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][8] ([i915#1886] / [i915#2291]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21714/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-kbl-soraka: NOTRUN -> [SKIP][9] ([fdo#109271] / [fdo#111827]) +8 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21714/fi-kbl-soraka/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-icl-u2: NOTRUN -> [SKIP][10] ([fdo#111827]) +8 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21714/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-icl-u2: NOTRUN -> [SKIP][11] ([fdo#109278]) +2 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21714/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html * igt@kms_force_connector_basic@force-load-detect: - fi-icl-u2: NOTRUN -> [SKIP][12] ([fdo#109285]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21714/fi-icl-u2/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-kbl-soraka: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#533]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21714/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html * igt@kms_psr@primary_page_flip: - fi-skl-6600u: [PASS][14] -> [INCOMPLETE][15] ([i915#198] / [i915#4547]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10949/fi-skl-6600u/igt@kms_psr@primary_page_flip.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21714/fi-skl-6600u/igt@kms_psr@primary_page_flip.html * igt@prime_vgem@basic-userptr: - fi-icl-u2: NOTRUN -> [SKIP][16] ([i915#3301]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21714/fi-icl-u2/igt@prime_v...@basic-userptr.html * igt@runner@aborted: - fi-skl-6600u: NOTRUN -> [FAIL][17] ([i915#2722] / [i915#3363] / [i915#4312]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21714/fi-skl-6600u/igt@run...@aborted.html Possible fixes * igt@gem_exec_suspend@basic-s3: - fi-tgl-1115g4: [FAIL][18] ([i915#1888]) -> [PASS][19] [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10949/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html [19]:
Re: [Intel-gfx] [PATCH] lib/stackdepot: always do filter_irq_stacks() in stack_depot_save()
On Tue, Nov 30, 2021 at 11:14 AM Marco Elver wrote: > > The non-interrupt portion of interrupt stack traces before interrupt > entry is usually arbitrary. Therefore, saving stack traces of interrupts > (that include entries before interrupt entry) to stack depot leads to > unbounded stackdepot growth. > > As such, use of filter_irq_stacks() is a requirement to ensure > stackdepot can efficiently deduplicate interrupt stacks. > > Looking through all current users of stack_depot_save(), none (except > KASAN) pass the stack trace through filter_irq_stacks() before passing > it on to stack_depot_save(). > > Rather than adding filter_irq_stacks() to all current users of > stack_depot_save(), it became clear that stack_depot_save() should > simply do filter_irq_stacks(). > > Signed-off-by: Marco Elver > --- > lib/stackdepot.c | 13 + > mm/kasan/common.c | 1 - > 2 files changed, 13 insertions(+), 1 deletion(-) > > diff --git a/lib/stackdepot.c b/lib/stackdepot.c > index b437ae79aca1..519c7898c7f2 100644 > --- a/lib/stackdepot.c > +++ b/lib/stackdepot.c > @@ -305,6 +305,9 @@ EXPORT_SYMBOL_GPL(stack_depot_fetch); > * (allocates using GFP flags of @alloc_flags). If @can_alloc is %false, > avoids > * any allocations and will fail if no space is left to store the stack > trace. > * > + * If the stack trace in @entries is from an interrupt, only the portion up > to > + * interrupt entry is saved. > + * > * Context: Any context, but setting @can_alloc to %false is required if > * alloc_pages() cannot be used from the current context. Currently > * this is the case from contexts where neither %GFP_ATOMIC nor > @@ -323,6 +326,16 @@ depot_stack_handle_t __stack_depot_save(unsigned long > *entries, > unsigned long flags; > u32 hash; > > + /* > +* If this stack trace is from an interrupt, including anything before > +* interrupt entry usually leads to unbounded stackdepot growth. > +* > +* Because use of filter_irq_stacks() is a requirement to ensure > +* stackdepot can efficiently deduplicate interrupt stacks, always > +* filter_irq_stacks() to simplify all callers' use of stackdepot. > +*/ > + nr_entries = filter_irq_stacks(entries, nr_entries); > + > if (unlikely(nr_entries == 0) || stack_depot_disable) > goto fast_exit; > > diff --git a/mm/kasan/common.c b/mm/kasan/common.c > index 8428da2aaf17..efaa836e5132 100644 > --- a/mm/kasan/common.c > +++ b/mm/kasan/common.c > @@ -36,7 +36,6 @@ depot_stack_handle_t kasan_save_stack(gfp_t flags, bool > can_alloc) > unsigned int nr_entries; > > nr_entries = stack_trace_save(entries, ARRAY_SIZE(entries), 0); > - nr_entries = filter_irq_stacks(entries, nr_entries); > return __stack_depot_save(entries, nr_entries, flags, can_alloc); > } > > -- > 2.34.0.rc2.393.gf8c9666880-goog > Reviewed-by: Andrey Konovalov
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Skip remap_io_mapping() for non-x86 platforms (rev4)
== Series Details == Series: drm/i915: Skip remap_io_mapping() for non-x86 platforms (rev4) URL : https://patchwork.freedesktop.org/series/96855/ State : success == Summary == CI Bug Log - changes from CI_DRM_10949 -> Patchwork_21713 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21713/index.html Participating hosts (39 -> 32) -- Additional (1): fi-kbl-soraka Missing(8): bat-dg1-6 bat-dg1-5 fi-bsw-cyan bat-adlp-6 bat-adlp-4 fi-pnv-d510 bat-jsl-2 bat-jsl-1 Known issues Here are the changes found in Patchwork_21713 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@cs-gfx: - fi-rkl-guc: NOTRUN -> [SKIP][1] ([fdo#109315]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21713/fi-rkl-guc/igt@amdgpu/amd_ba...@cs-gfx.html * igt@gem_exec_fence@basic-busy@bcs0: - fi-kbl-soraka: NOTRUN -> [SKIP][2] ([fdo#109271]) +8 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21713/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html * igt@gem_huc_copy@huc-copy: - fi-kbl-soraka: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21713/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-kbl-soraka: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +3 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21713/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html * igt@i915_selftest@live@gt_pm: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][5] ([i915#1886] / [i915#2291]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21713/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-kbl-soraka: NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +8 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21713/fi-kbl-soraka/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-kbl-soraka: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#533]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21713/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html * igt@kms_psr@primary_page_flip: - fi-skl-6600u: [PASS][8] -> [INCOMPLETE][9] ([i915#198]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10949/fi-skl-6600u/igt@kms_psr@primary_page_flip.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21713/fi-skl-6600u/igt@kms_psr@primary_page_flip.html Possible fixes * igt@gem_exec_suspend@basic-s3: - fi-tgl-1115g4: [FAIL][10] ([i915#1888]) -> [PASS][11] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10949/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21713/fi-tgl-1115g4/igt@gem_exec_susp...@basic-s3.html * igt@i915_selftest@live@gt_engines: - fi-rkl-guc: [INCOMPLETE][12] ([i915#4432]) -> [PASS][13] [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10949/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21713/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886 [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291 [i915#4432]: https://gitlab.freedesktop.org/drm/intel/issues/4432 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533 Build changes - * Linux: CI_DRM_10949 -> Patchwork_21713 CI-20190529: 20190529 CI_DRM_10949: c43a205a07b34ebbf7fe9205454a422147791ef3 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6295: 2d7f671b872ed856a97957051098974be2380019 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_21713: e1ed6afae3faaa0f6959d1005431e3637c524707 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == e1ed6afae3fa drm/i915: Skip remap_io_mapping() for non-x86 platforms == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21713/index.html
Re: [Intel-gfx] [PATCH v2 00/16] drm/i915: Remove short term pins from execbuf.
On 01/12/2021 11:15, Maarten Lankhorst wrote: On 30-11-2021 19:38, Tvrtko Ursulin wrote: On 30/11/2021 11:17, Maarten Lankhorst wrote: On 30-11-2021 09:54, Tvrtko Ursulin wrote: Hi, On 29/11/2021 13:47, Maarten Lankhorst wrote: New version of the series, with feedback from previous series added. If there was a cover letter sent for this work in the past could you please keep attaching it? Or if there wasn't, could you please write one? I am worried about two things. First is that we need to have a high level overview of the rules/design changes documented so third party people have any hope of getting code right after this lands. (Where we are, where we are going, how we will get there, how far did we get and when we will get to the end.) Second is that when parts of the series land piecemeal (Which they have in this right, right?), it gets very hard to write up a maintainer level changelog. The preparation part is to ensure we always hold vma->obj->resv when unbinding. The first preparation series ensured vma->obj always existed. This was not the case for mock gtt and gen6 aliasing gtt. This allowed us to remove all the special handling for those uncommon cases, and actually enforce we can always take that lock. This part is merged. Sounds good. But also mention the high level motivation for why we always want to hold vma->obj->resv when unbinding in the introduction as well. Patch 2-11 in this series adds the vma->obj->resv to eviction and shrinker. Those are the only parts where we don't take the lock yet. After that, we always hold the lock when required, and we can start requiring the obj-> resv lock when unbinding. This is completed in patch 15. With that fixed, removing short term pins can be done, because for unbind we now always take obj->resv, so holding obj->resv during execbuf submission is sufficient, and all short term pinning can be removed. I'd also like the cover letter to contain a high level description on _why_ is removing short term pins needed or beneficial. What was the flow and object lifetimes so far, and what it will be going forward etc. Previously, short term pinning in execbuf was required because i915_vma was effectively independent from objects, and has its own refcount, locking, and lifetime rules and pinning. This series removes the separate locking, by requiring vma->obj->resv to be held when pinning and unbinding. This will also be required for VM_BIND work. With pinning required for pinning and unbinding, the lock is enough to prevent unbinding when trying to pin with the lock held, like in execbuf. This makes binding/unbinding similar to ttm_bo_validate()'s use, which just cares that an object is in a certain place, without pinning it in place. Having it part of gem bo removes a lot of the vma refcounting, and makes i915_vma more a part of the bo, instead of its own floating object that just happens to be part of a bo. This is also required to make it more compatible with TTM, and migration in general. For future work, it makes things a lot simpler and clear. We want to end up with i915_vma just being a specific mapping of the BO, just like is the case in other drivers. i915_vma->active removal is the next step there, and makes it when object is destroyed, the bindings are destroyed (after idle), instead of object being destroyed when bindings are idle. Excellent, that's exactly the level needed for the cover letter. So that as intro, plus some text about the series details like which part of the overall plan it implements and it will be good. We only pin temporarily when calling i915_gem_evict_vm in execbuf, which could also be handled in theory by just marking all objects as unpinned. As a bonus, using TTM for delayed eviction on all objects becomes easy, just need to get rid of i915_active in i915_vma, as it keeps the object refcount alive. Remainder is removing refcount to i915_vma, to make it a real Sounds on the right track with maybe a bit more text so the readers can easily understand it on the higher level. With the obj->resv being the master lock, pinning for execbuf becomes obsolete and can be removed. Out of personal curiosity about the long term plans - what will be the flow on request retirement in terms of unbinding? Regards, Tvrtko
Re: [Intel-gfx] [PATCH v4 2/2] drm/i915: Use to_root_gt() to refer to the root tile
Hi Michal, > >> fist of all thanks for taking a look at this, I was eagerly > >> waiting for reviewers. > >> > >> On Tue, Nov 30, 2021 at 01:07:30PM -0800, Lucas De Marchi wrote: > >>> On Sun, Nov 28, 2021 at 01:09:26PM +0200, Andi Shyti wrote: > >>> > Starting from a patch from Matt to_root_gt() returns the > >>> > reference to the root tile in order to abstract the root tile > >>> > from th callers. > >>> > > >>> > Being the root tile identified as tile '0', embed the id in the > >>> > name so that i915->gt becomes i915->gt0. > >>> > > >>> > The renaming has been mostly done with the following command and > >>> > some manual fixes. > >>> > > >>> > sed -i -e sed -i 's/\\->gt\./\_root_gt(i915)\->/g' \ > >>> > -e sed -i 's/\_priv\->gt\./\_root_gt(dev_priv)\->/g' \ > >>> > -e 's/\_priv\->gt/to_root_gt(dev_priv)/g' \ > >>> > -e 's/\\->gt/to_root_gt(i915)/g' \ > >>> > -e 's/dev_priv\->gt\./to_root_gt(dev_priv)\->/g' \ > >>> > -e 's/i915\->gt\./to_root_gt(i915)\->/g' \ > >>> > `find drivers/gpu/drm/i915/ -name *.[ch]` > >>> > > >>> > Two small changes have been added to this commit: > >>> > > >>> > 1. intel_reset_gpu() in intel_display.c retreives the gt from > >>> > to_scanout_gt() > >>> > 2. in set_scheduler_caps() the gt is taken from the engine and > >>> > not from i915. > >>> > >>> Ideally the non-automatic changes should be in separate patches, before > >>> the ones that can be done by automation. Because then it becomes easier > >>> to apply the final result without conflicts. > >> > >> OK > >> > >>> This is quite a big diff to merge in one go. Looking at the pending > >>> patches from Michal however I see he had similar changes, split in > >>> sensible chunks.. Could you split your version like that? at least > >>> gt/gem and display would be good to have separate. Or sync with Michal > >>> on how to proceed with these versions Here are his patches: > >>> > >>> drm/i915: Remove i915->ggtt > >>> drm/i915: Use to_gt() helper for GGTT accesses > >>> drm/i915: Use to_gt() helper > >>> drm/i915/gvt: Use to_gt() helper > >>> drm/i915/gem: Use to_gt() helper > >>> drm/i915/gt: Use to_gt() helper > >>> drm/i915/display: Use to_gt() helper > >>> drm/i915: Introduce to_gt() helper > >> > >> I understand... will follow this approach. > >> > >>> This first patch also removed the `struct intel_gt *gt = to_gt(pool)`, > >>> that would otherwise be a leftover in > >>> drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.c > >> > >> One difference from Michal patch is that I am not using the > >> wrapper > >> > >> to_gt(...) > >> > >> but > >> > >> to_root_gt(...) > >> > >> which was introduced by Matt. To me sounds more meaningful as it > >> specifies that we are really looking for the root tile and not > >> any tile. > > > > yes, I think it makes sense, too. Michal, any comment? I think you > > also had other plans to get the root gt by another helper... ? > > The main rationale to use generic "to_gt()" helper name in all existing > i915->gt cases in (other) Michal patches was that on some upcoming > configs we want to distinguish between "primary" and "root" tile and use > "to_root_gt()" helper only when referring to the root tile as described > in Bspec:52416. > > Note that since current code baseline is still "single" tile, you can't > tell whether all of these functions really expects special "root" tile > or just "any" tile. this series is indeed preparatory for the multitile and making it to_gt() now it will require to replace it with to_root_gt() later. The idea is that a GT is root even if it's alone. The next patch after this will be the actual multitile.[*] In this particular patch I am even renaming i915->gt to i915->gt0 to underline the difference. > Thus to avoid confusion or mistakes I would suggest to keep simple name > "to_gt()" as in most cases usages of this helper it will likely be > replaced with iterator from for_each_gt loop and any remaining usages > will just mean "primary" tile or replaced with explicit "to_root_gt()" > if really needed. Knowing what's about to come, I do not see this as a good reason to have to_gt() as a mid step. Right? Andi [*] https://patchwork.freedesktop.org/patch/464475/?series=97352=1
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Skip remap_io_mapping() for non-x86 platforms (rev4)
== Series Details == Series: drm/i915: Skip remap_io_mapping() for non-x86 platforms (rev4) URL : https://patchwork.freedesktop.org/series/96855/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Skip remap_io_mapping() for non-x86 platforms (rev4)
== Series Details == Series: drm/i915: Skip remap_io_mapping() for non-x86 platforms (rev4) URL : https://patchwork.freedesktop.org/series/96855/ State : warning == Summary == $ dim checkpatch origin/drm-tip e1ed6afae3fa drm/i915: Skip remap_io_mapping() for non-x86 platforms -:63: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #63: new file mode 100644 -:84: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #84: FILE: drivers/gpu/drm/i915/i915_mm.h:17: +int remap_io_mapping(struct vm_area_struct *vma, + unsigned long addr, unsigned long pfn, unsigned long size, -:88: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #88: FILE: drivers/gpu/drm/i915/i915_mm.h:21: +static inline int remap_io_mapping(struct vm_area_struct *vma, + unsigned long addr, unsigned long pfn, unsigned long size, total: 0 errors, 1 warnings, 2 checks, 63 lines checked
[Intel-gfx] ✓ Fi.CI.BAT: success for Introduce Raptor Lake S (rev4)
== Series Details == Series: Introduce Raptor Lake S (rev4) URL : https://patchwork.freedesktop.org/series/96869/ State : success == Summary == CI Bug Log - changes from CI_DRM_10949 -> Patchwork_21712 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21712/index.html Participating hosts (39 -> 30) -- Missing(9): fi-tgl-dsi bat-dg1-6 bat-dg1-5 fi-bsw-cyan bat-adlp-6 bat-adlp-4 fi-pnv-d510 bat-jsl-2 bat-jsl-1 Known issues Here are the changes found in Patchwork_21712 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@cs-gfx: - fi-rkl-guc: NOTRUN -> [SKIP][1] ([fdo#109315]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21712/fi-rkl-guc/igt@amdgpu/amd_ba...@cs-gfx.html * igt@i915_pm_rpm@basic-pci-d3-state: - fi-hsw-4770:[PASS][2] -> [SKIP][3] ([fdo#109271]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10949/fi-hsw-4770/igt@i915_pm_...@basic-pci-d3-state.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21712/fi-hsw-4770/igt@i915_pm_...@basic-pci-d3-state.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b: - fi-cfl-8109u: [PASS][4] -> [DMESG-WARN][5] ([i915#295]) +11 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10949/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21712/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html * igt@kms_psr@primary_page_flip: - fi-skl-6600u: [PASS][6] -> [INCOMPLETE][7] ([i915#198] / [i915#4547]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10949/fi-skl-6600u/igt@kms_psr@primary_page_flip.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21712/fi-skl-6600u/igt@kms_psr@primary_page_flip.html * igt@runner@aborted: - fi-skl-6600u: NOTRUN -> [FAIL][8] ([i915#2722] / [i915#3363] / [i915#4312]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21712/fi-skl-6600u/igt@run...@aborted.html Possible fixes * igt@i915_selftest@live@gt_engines: - fi-rkl-guc: [INCOMPLETE][9] ([i915#4432]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10949/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21712/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722 [i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295 [i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 [i915#4432]: https://gitlab.freedesktop.org/drm/intel/issues/4432 [i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547 Build changes - * Linux: CI_DRM_10949 -> Patchwork_21712 CI-20190529: 20190529 CI_DRM_10949: c43a205a07b34ebbf7fe9205454a422147791ef3 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6295: 2d7f671b872ed856a97957051098974be2380019 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_21712: c2d4bf50f1811d78ae4070d62f312bc9e1cca4be @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == c2d4bf50f181 drm/i915/rpl-s: Enable guc submission by default 03d7205d14cb drm/i915/rpl-s: Add PCH Support for Raptor Lake S 91c35932ece3 drm/i915/rpl-s: Add PCI IDS for Raptor Lake S == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21712/index.html
Re: [Intel-gfx] [v3 0/3] Introduce Raptor Lake S
On Wed, 01 Dec 2021, Anusha Srivatsa wrote: > Raptor Lake S(RPL-S) is a version 12 > Display, Media and Render. For all i915 > purposes it is the same as Alder Lake S (ADL-S). > > The series introduces it as a subplatform > of ADL-S. The one difference is the GuC > submission which is default on RPL-S but > was not the case with ADL-S. Acked-by: Jani Nikula on the series, did not check the pci ids in spec. > > Anusha Srivatsa (3): > drm/i915/rpl-s: Add PCI IDS for Raptor Lake S > drm/i915/rpl-s: Add PCH Support for Raptor Lake S > drm/i915/rpl-s: Enable guc submission by default > > arch/x86/kernel/early-quirks.c | 1 + > drivers/gpu/drm/i915/gt/uc/intel_uc.c| 2 +- > drivers/gpu/drm/i915/i915_drv.h | 2 ++ > drivers/gpu/drm/i915/i915_pci.c | 1 + > drivers/gpu/drm/i915/intel_device_info.c | 7 +++ > drivers/gpu/drm/i915/intel_device_info.h | 3 +++ > drivers/gpu/drm/i915/intel_pch.c | 1 + > drivers/gpu/drm/i915/intel_pch.h | 1 + > include/drm/i915_pciids.h| 9 + > 9 files changed, 26 insertions(+), 1 deletion(-) -- Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Introduce Raptor Lake S (rev4)
== Series Details == Series: Introduce Raptor Lake S (rev4) URL : https://patchwork.freedesktop.org/series/96869/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
Re: [Intel-gfx] [Linaro-mm-sig] [RFC PATCH 1/2] dma-fence: Avoid establishing a locking order between fence classes
On 12/1/21 12:25, Christian König wrote: Am 01.12.21 um 12:04 schrieb Thomas Hellström (Intel): On 12/1/21 11:32, Christian König wrote: Am 01.12.21 um 11:15 schrieb Thomas Hellström (Intel): [SNIP] What we could do is to avoid all this by not calling the callback with the lock held in the first place. If that's possible that might be a good idea, pls also see below. The problem with that is dma_fence_signal_locked()/dma_fence_signal_timestamp_locked(). If we could avoid using that or at least allow it to drop the lock then we could call the callback without holding it. Somebody would need to audit the drivers and see if holding the lock is really necessary anywhere. /Thomas Oh, and a follow up question: If there was a way to break the recursion on final put() (using the same basic approach as patch 2 in this series uses to break recursion in enable_signaling()), so that none of these containers did require any special treatment, would it be worth pursuing? I guess it might be possible by having the callbacks drop the references rather than the loop in the final put. + a couple of changes in code iterating over the fence pointers. That won't really help, you just move the recursion from the final put into the callback. How do we recurse from the callback? The introduced fence_put() of individual fence pointers doesn't recurse anymore (at most 1 level), and any callback recursion is broken by the irq_work? Yeah, but then you would need to take another lock to avoid racing with dma_fence_array_signaled(). I figure the big amount of work would be to adjust code that iterates over the individual fence pointers to recognize that they are rcu protected. Could be that we could solve this with RCU, but that sounds like a lot of churn for no gain at all. In other words even with the problems solved I think it would be a really bad idea to allow chaining of dma_fence_array objects. Yes, that was really the question, Is it worth pursuing this? I'm not really suggesting we should allow this as an intentional feature. I'm worried, however, that if we allow these containers to start floating around cross-driver (or even internally) disguised as ordinary dma_fences, they would require a lot of driver special casing, or else completely unexpeced WARN_ON()s and lockdep splats would start to turn up, scaring people off from using them. And that would be a breeding ground for hairy driver-private constructs. Well the question is why we would want to do it? If it's to avoid inter driver lock dependencies by avoiding to call the callback with the spinlock held, then yes please. We had tons of problems with that, resulting in irq_work and work_item delegation all over the place. Yes, that sounds like something desirable, but in these containers, what's causing the lock dependencies is the enable_signaling() callback that is typically called locked. If it's to allow nesting of dma_fence_array instances, then it's most likely a really bad idea even if we fix all the locking order problems. Well I think my use-case where I hit a dead end may illustrate what worries me here: 1) We use a dma-fence-array to coalesce all dependencies for ttm object migration. 2) We use a dma-fence-chain to order the resulting dm_fence into a timeline because the TTM resource manager code requires that. Initially seemingly harmless to me. But after a sequence evict->alloc->clear, the dma-fence-chain feeds into the dma-fence-array for the clearing operation. Code still works fine, and no deep recursion, no warnings. But if I were to add another driver to the system that instead feeds a dma-fence-array into a dma-fence-chain, this would give me a lockdep splat. So then if somebody were to come up with the splendid idea of using a dma-fence-chain to initially coalesce fences, I'd hit the same problem or risk illegaly joining two dma-fence-chains together. To fix this, I would need to look at the incoming fences and iterate over any dma-fence-array or dma-fence-chain that is fed into the dma-fence-array to flatten out the input. In fact all dma-fence-array users would need to do that, and even dma-fence-chain users watching out for not joining chains together or accidently add an array that perhaps came as a disguised dma-fence from antother driver. So the purpose to me would be to allow these containers as input to eachother without a lot of in-driver special-casing, be it by breaking recursion on built-in flattening to avoid a) Hitting issues in the future or with existing interoperating drivers. b) Avoid driver-private containers that also might break the interoperability. (For example the i915 currently driver-private dma_fence_work avoid all these problems, but we're attempting to address issues in common code rather than re-inventing stuff internally). I don't think that a dma_fence_array or dma_fence_chain is the right thing
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Raptor Lake S (rev4)
== Series Details == Series: Introduce Raptor Lake S (rev4) URL : https://patchwork.freedesktop.org/series/96869/ State : warning == Summary == $ dim checkpatch origin/drm-tip 91c35932ece3 drm/i915/rpl-s: Add PCI IDS for Raptor Lake S -:112: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #112: FILE: include/drm/i915_pciids.h:670: +#define INTEL_RPLS_IDS(info) \ + INTEL_VGA_DEVICE(0xA780, info), \ + INTEL_VGA_DEVICE(0xA781, info), \ + INTEL_VGA_DEVICE(0xA782, info), \ + INTEL_VGA_DEVICE(0xA783, info), \ + INTEL_VGA_DEVICE(0xA788, info), \ + INTEL_VGA_DEVICE(0xA789, info) -:112: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects? #112: FILE: include/drm/i915_pciids.h:670: +#define INTEL_RPLS_IDS(info) \ + INTEL_VGA_DEVICE(0xA780, info), \ + INTEL_VGA_DEVICE(0xA781, info), \ + INTEL_VGA_DEVICE(0xA782, info), \ + INTEL_VGA_DEVICE(0xA783, info), \ + INTEL_VGA_DEVICE(0xA788, info), \ + INTEL_VGA_DEVICE(0xA789, info) total: 1 errors, 0 warnings, 1 checks, 63 lines checked 03d7205d14cb drm/i915/rpl-s: Add PCH Support for Raptor Lake S c2d4bf50f181 drm/i915/rpl-s: Enable guc submission by default
