[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: SAGV fixes (rev3)
== Series Details ==
Series: drm/i915: SAGV fixes (rev3)
URL : https://patchwork.freedesktop.org/series/100091/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11244 -> Patchwork_22327
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22327/index.html
Participating hosts (44 -> 42)
--
Additional (1): fi-kbl-8809g
Missing(3): fi-bsw-cyan bat-jsl-2 shard-tglu
Known issues
Here are the changes found in Patchwork_22327 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s0@smem:
- fi-kbl-8809g: NOTRUN -> [DMESG-WARN][1] ([i915#4962]) +1 similar
issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22327/fi-kbl-8809g/igt@gem_exec_suspend@basic...@smem.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-8809g: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#2190])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22327/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@random-engines:
- fi-kbl-8809g: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4613]) +3
similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22327/fi-kbl-8809g/igt@gem_lmem_swapp...@random-engines.html
* igt@i915_pm_rpm@basic-rte:
- fi-kbl-8809g: NOTRUN -> [SKIP][4] ([fdo#109271]) +54 similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22327/fi-kbl-8809g/igt@i915_pm_...@basic-rte.html
* igt@i915_selftest@live@requests:
- fi-blb-e6850: [PASS][5] -> [DMESG-FAIL][6] ([i915#5026])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/fi-blb-e6850/igt@i915_selftest@l...@requests.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22327/fi-blb-e6850/igt@i915_selftest@l...@requests.html
* igt@kms_chamelium@hdmi-edid-read:
- fi-kbl-8809g: NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827]) +8
similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22327/fi-kbl-8809g/igt@kms_chamel...@hdmi-edid-read.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-8809g: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#533])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22327/fi-kbl-8809g/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
* igt@runner@aborted:
- fi-blb-e6850: NOTRUN -> [FAIL][9] ([fdo#109271] / [i915#2403] /
[i915#2426] / [i915#4312])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22327/fi-blb-e6850/igt@run...@aborted.html
- fi-skl-6600u: NOTRUN -> [FAIL][10] ([i915#4312])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22327/fi-skl-6600u/igt@run...@aborted.html
Possible fixes
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: [DMESG-FAIL][11] ([i915#4494] / [i915#4957]) ->
[PASS][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22327/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
- {fi-jsl-1}: [INCOMPLETE][13] -> [PASS][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/fi-jsl-1/igt@i915_selftest@l...@hangcheck.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22327/fi-jsl-1/igt@i915_selftest@l...@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4898]: https://gitlab.freedesktop.org/drm/intel/issues/4898
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
[i915#4962]: https://gitlab.freedesktop.org/drm/intel/issues/4962
[i915#5026]: https://gitlab.freedesktop.org/drm/intel/issues/5026
[i915#5127]: https://gitlab.freedesktop.org/drm/intel/issues/5127
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
Build changes
-
* Linux: CI_DRM_11244 -> Patchwork_22327
CI-20190529: 20190529
CI_DRM_11244:
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Fix disabled crtc state clearing, again
== Series Details == Series: drm/i915: Fix disabled crtc state clearing, again URL : https://patchwork.freedesktop.org/series/100316/ State : success == Summary == CI Bug Log - changes from CI_DRM_11242_full -> Patchwork_22313_full Summary --- **SUCCESS** No regressions found. Participating hosts (11 -> 11) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_22313_full that come from known issues: ### CI changes ### Possible fixes * boot: - shard-glk: ([PASS][1], [PASS][2], [PASS][3], [PASS][4], [FAIL][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25]) ([i915#4392]) -> ([PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11242/shard-glk9/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11242/shard-glk9/boot.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11242/shard-glk8/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11242/shard-glk8/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11242/shard-glk8/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11242/shard-glk8/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11242/shard-glk7/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11242/shard-glk7/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11242/shard-glk7/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11242/shard-glk6/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11242/shard-glk6/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11242/shard-glk5/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11242/shard-glk5/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11242/shard-glk4/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11242/shard-glk4/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11242/shard-glk4/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11242/shard-glk3/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11242/shard-glk3/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11242/shard-glk3/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11242/shard-glk2/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11242/shard-glk2/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11242/shard-glk2/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11242/shard-glk1/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11242/shard-glk1/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11242/shard-glk1/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22313/shard-glk9/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22313/shard-glk9/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22313/shard-glk9/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22313/shard-glk8/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22313/shard-glk8/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22313/shard-glk8/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22313/shard-glk7/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22313/shard-glk7/boot.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22313/shard-glk7/boot.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22313/shard-glk6/boot.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22313/shard-glk6/boot.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22313/shard-glk6/boot.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22313/shard-glk5/boot.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22313/shard-glk5/boot.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22313/shard-glk4/boot.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22313/shard-glk4/boot.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22313/shard-glk4/boot.html [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22313/shard-glk3/boot.html [44]:
[Intel-gfx] [PATCH v3 6/6] drm/i915: Extract intel_bw_check_data_rate()
From: Ville Syrjälä
Extract the data rate calculation loop out from
intel_bw_atomic_check() to make it a bit less confusing.
v2: Deal with 'bool changed'
Reviewed-by: Stanislav Lisovskiy #v1
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_bw.c | 55 +++--
1 file changed, 34 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index 6637da75f878..ad1564ca7269 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -836,25 +836,12 @@ static u16 icl_qgv_points_mask(struct drm_i915_private
*i915)
return mask;
}
-int intel_bw_atomic_check(struct intel_atomic_state *state)
+static int intel_bw_check_data_rate(struct intel_atomic_state *state, bool
*changed)
{
- struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- struct intel_crtc_state *new_crtc_state, *old_crtc_state;
- struct intel_bw_state *new_bw_state = NULL;
- const struct intel_bw_state *old_bw_state = NULL;
- unsigned int data_rate;
- unsigned int num_active_planes;
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+ const struct intel_crtc_state *new_crtc_state, *old_crtc_state;
struct intel_crtc *crtc;
- int i, ret;
- u32 allowed_points = 0;
- unsigned int max_bw_point = 0, max_bw = 0;
- unsigned int num_qgv_points = dev_priv->max_bw[0].num_qgv_points;
- unsigned int num_psf_gv_points = dev_priv->max_bw[0].num_psf_gv_points;
- bool changed = false;
-
- /* FIXME earlier gens need some checks too */
- if (DISPLAY_VER(dev_priv) < 11)
- return 0;
+ int i;
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
@@ -866,6 +853,7 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
intel_bw_crtc_num_active_planes(old_crtc_state);
unsigned int new_active_planes =
intel_bw_crtc_num_active_planes(new_crtc_state);
+ struct intel_bw_state *new_bw_state;
/*
* Avoid locking the bw state when
@@ -882,15 +870,40 @@ int intel_bw_atomic_check(struct intel_atomic_state
*state)
new_bw_state->data_rate[crtc->pipe] = new_data_rate;
new_bw_state->num_active_planes[crtc->pipe] = new_active_planes;
- changed = true;
+ *changed = true;
- drm_dbg_kms(_priv->drm,
- "pipe %c data rate %u num active planes %u\n",
- pipe_name(crtc->pipe),
+ drm_dbg_kms(>drm,
+ "[CRTC:%d:%s] data rate %u num active planes %u\n",
+ crtc->base.base.id, crtc->base.name,
new_bw_state->data_rate[crtc->pipe],
new_bw_state->num_active_planes[crtc->pipe]);
}
+ return 0;
+}
+
+int intel_bw_atomic_check(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ const struct intel_bw_state *old_bw_state;
+ struct intel_bw_state *new_bw_state;
+ unsigned int data_rate;
+ unsigned int num_active_planes;
+ int i, ret;
+ u32 allowed_points = 0;
+ unsigned int max_bw_point = 0, max_bw = 0;
+ unsigned int num_qgv_points = dev_priv->max_bw[0].num_qgv_points;
+ unsigned int num_psf_gv_points = dev_priv->max_bw[0].num_psf_gv_points;
+ bool changed = false;
+
+ /* FIXME earlier gens need some checks too */
+ if (DISPLAY_VER(dev_priv) < 11)
+ return 0;
+
+ ret = intel_bw_check_data_rate(state, );
+ if (ret)
+ return ret;
+
old_bw_state = intel_atomic_get_old_bw_state(state);
new_bw_state = intel_atomic_get_new_bw_state(state);
--
2.34.1
[Intel-gfx] [PATCH v3 5/6] drm/i915: Extract icl_qgv_points_mask()
From: Ville Syrjälä
Declutter intel_bw_atomic_check() a bit by pulling
the max QGV mask calculation out.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_bw.c | 35 -
1 file changed, 22 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index 1fd1d2182d8f..6637da75f878 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -816,6 +816,26 @@ int intel_bw_calc_min_cdclk(struct intel_atomic_state
*state)
return 0;
}
+static u16 icl_qgv_points_mask(struct drm_i915_private *i915)
+{
+ unsigned int num_psf_gv_points = i915->max_bw[0].num_psf_gv_points;
+ unsigned int num_qgv_points = i915->max_bw[0].num_qgv_points;
+ u16 mask = 0;
+
+ /*
+* We can _not_ use the whole ADLS_QGV_PT_MASK here, as PCode rejects
+* it with failure if we try masking any unadvertised points.
+* So need to operate only with those returned from PCode.
+*/
+ if (num_qgv_points > 0)
+ mask |= REG_GENMASK(num_qgv_points - 1, 0);
+
+ if (num_psf_gv_points > 0)
+ mask |= REG_GENMASK(num_psf_gv_points - 1, 0) <<
ADLS_PSF_PT_SHIFT;
+
+ return mask;
+}
+
int intel_bw_atomic_check(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
@@ -831,23 +851,11 @@ int intel_bw_atomic_check(struct intel_atomic_state
*state)
unsigned int num_qgv_points = dev_priv->max_bw[0].num_qgv_points;
unsigned int num_psf_gv_points = dev_priv->max_bw[0].num_psf_gv_points;
bool changed = false;
- u32 mask = 0;
/* FIXME earlier gens need some checks too */
if (DISPLAY_VER(dev_priv) < 11)
return 0;
- /*
-* We can _not_ use the whole ADLS_QGV_PT_MASK here, as PCode rejects
-* it with failure if we try masking any unadvertised points.
-* So need to operate only with those returned from PCode.
-*/
- if (num_qgv_points > 0)
- mask |= REG_GENMASK(num_qgv_points - 1, 0);
-
- if (num_psf_gv_points > 0)
- mask |= REG_GENMASK(num_psf_gv_points - 1, 0) <<
ADLS_PSF_PT_SHIFT;
-
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
unsigned int old_data_rate =
@@ -979,7 +987,8 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
* We store the ones which need to be masked as that is what PCode
* actually accepts as a parameter.
*/
- new_bw_state->qgv_points_mask = ~allowed_points & mask;
+ new_bw_state->qgv_points_mask = ~allowed_points &
+ icl_qgv_points_mask(dev_priv);
/*
* If the actual mask had changed we need to make sure that
--
2.34.1
[Intel-gfx] [PATCH v3 4/6] drm/i915: Pimp icl+ sagv pre/post update
From: Ville Syrjälä Add some debugs on what exactly we're doing to the QGV point mask in the icl+ sagv pre/post plane update hooks. Currently we're just guessing. v2: s/u32/u16/ for consistency with the mask sizes (Stan) Reviewed-by: Stanislav Lisovskiy Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_pm.c | 37 - 1 file changed, 18 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index bf8cf71f5b07..ea7a4bb079d3 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3815,26 +3815,22 @@ static void icl_sagv_pre_plane_update(struct intel_atomic_state *state) intel_atomic_get_old_bw_state(state); const struct intel_bw_state *new_bw_state = intel_atomic_get_new_bw_state(state); - u32 new_mask; + u16 old_mask, new_mask; if (!new_bw_state) return; - /* -* Nothing to mask -*/ - if (new_bw_state->qgv_points_mask == old_bw_state->qgv_points_mask) - return; - + old_mask = old_bw_state->qgv_points_mask; new_mask = old_bw_state->qgv_points_mask | new_bw_state->qgv_points_mask; - /* -* If new mask is zero - means there is nothing to mask, -* we can only unmask, which should be done in unmask. -*/ - if (!new_mask) + if (old_mask == new_mask) return; + WARN_ON(!new_bw_state->base.changed); + + drm_dbg_kms(_priv->drm, "Restricting QGV points: 0x%x -> 0x%x\n", + old_mask, new_mask); + /* * Restrict required qgv points before updating the configuration. * According to BSpec we can't mask and unmask qgv points at the same @@ -3851,19 +3847,22 @@ static void icl_sagv_post_plane_update(struct intel_atomic_state *state) intel_atomic_get_old_bw_state(state); const struct intel_bw_state *new_bw_state = intel_atomic_get_new_bw_state(state); - u32 new_mask = 0; + u16 old_mask, new_mask; if (!new_bw_state) return; - /* -* Nothing to unmask -*/ - if (new_bw_state->qgv_points_mask == old_bw_state->qgv_points_mask) - return; - + old_mask = old_bw_state->qgv_points_mask | new_bw_state->qgv_points_mask; new_mask = new_bw_state->qgv_points_mask; + if (old_mask == new_mask) + return; + + WARN_ON(!new_bw_state->base.changed); + + drm_dbg_kms(_priv->drm, "Relaxing QGV points: 0x%x -> 0x%x\n", + old_mask, new_mask); + /* * Allow required qgv points after updating the configuration. * According to BSpec we can't mask and unmask qgv points at the same -- 2.34.1
[Intel-gfx] [PATCH v3 3/6] drm/i915: Split pre-icl vs. icl+ SAGV hooks apart
From: Ville Syrjälä
To further reduce the confusion between the pre-icl vs. icl+
SAGV codepaths let's do a full split.
Reviewed-by: Stanislav Lisovskiy
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 120
1 file changed, 77 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d0fcc4586983..bf8cf71f5b07 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3782,34 +3782,44 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
return 0;
}
-void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
+static void skl_sagv_pre_plane_update(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+ const struct intel_bw_state *new_bw_state =
+ intel_atomic_get_new_bw_state(state);
+
+ if (!new_bw_state)
+ return;
+
+ if (!intel_can_enable_sagv(i915, new_bw_state))
+ intel_disable_sagv(i915);
+}
+
+static void skl_sagv_post_plane_update(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+ const struct intel_bw_state *new_bw_state =
+ intel_atomic_get_new_bw_state(state);
+
+ if (!new_bw_state)
+ return;
+
+ if (intel_can_enable_sagv(i915, new_bw_state))
+ intel_enable_sagv(i915);
+}
+
+static void icl_sagv_pre_plane_update(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- const struct intel_bw_state *new_bw_state;
- const struct intel_bw_state *old_bw_state;
- u32 new_mask = 0;
+ const struct intel_bw_state *old_bw_state =
+ intel_atomic_get_old_bw_state(state);
+ const struct intel_bw_state *new_bw_state =
+ intel_atomic_get_new_bw_state(state);
+ u32 new_mask;
- /*
-* Just return if we can't control SAGV or don't have it.
-* This is different from situation when we have SAGV but just can't
-* afford it due to DBuf limitation - in case if SAGV is completely
-* disabled in a BIOS, we are not even allowed to send a PCode request,
-* as it will throw an error. So have to check it here.
-*/
- if (!intel_has_sagv(dev_priv))
- return;
-
- new_bw_state = intel_atomic_get_new_bw_state(state);
if (!new_bw_state)
return;
- if (DISPLAY_VER(dev_priv) < 11) {
- if (!intel_can_enable_sagv(dev_priv, new_bw_state))
- intel_disable_sagv(dev_priv);
- return;
- }
-
- old_bw_state = intel_atomic_get_old_bw_state(state);
/*
* Nothing to mask
*/
@@ -3834,34 +3844,18 @@ void intel_sagv_pre_plane_update(struct
intel_atomic_state *state)
icl_pcode_restrict_qgv_points(dev_priv, new_mask);
}
-void intel_sagv_post_plane_update(struct intel_atomic_state *state)
+static void icl_sagv_post_plane_update(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- const struct intel_bw_state *new_bw_state;
- const struct intel_bw_state *old_bw_state;
+ const struct intel_bw_state *old_bw_state =
+ intel_atomic_get_old_bw_state(state);
+ const struct intel_bw_state *new_bw_state =
+ intel_atomic_get_new_bw_state(state);
u32 new_mask = 0;
- /*
-* Just return if we can't control SAGV or don't have it.
-* This is different from situation when we have SAGV but just can't
-* afford it due to DBuf limitation - in case if SAGV is completely
-* disabled in a BIOS, we are not even allowed to send a PCode request,
-* as it will throw an error. So have to check it here.
-*/
- if (!intel_has_sagv(dev_priv))
- return;
-
- new_bw_state = intel_atomic_get_new_bw_state(state);
if (!new_bw_state)
return;
- if (DISPLAY_VER(dev_priv) < 11) {
- if (intel_can_enable_sagv(dev_priv, new_bw_state))
- intel_enable_sagv(dev_priv);
- return;
- }
-
- old_bw_state = intel_atomic_get_old_bw_state(state);
/*
* Nothing to unmask
*/
@@ -3879,6 +3873,46 @@ void intel_sagv_post_plane_update(struct
intel_atomic_state *state)
icl_pcode_restrict_qgv_points(dev_priv, new_mask);
}
+void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+
+ /*
+* Just return if we can't control SAGV or don't have it.
+* This is different from situation when we have SAGV but just can't
+* afford it due to DBuf limitation - in case if SAGV is completely
+
[Intel-gfx] [PATCH v3 2/6] drm/i915: Fix bw atomic check when switching between SAGV vs. no SAGV
From: Ville Syrjälä
If the only thing that is changing is SAGV vs. no SAGV but
the number of active planes and the total data rates end up
unchanged we currently bail out of intel_bw_atomic_check()
early and forget to actually compute the new WGV point
mask and thus won't actually enable/disable SAGV as requested.
This ends up poorly if we end up running with SAGV enabled
when we shouldn't. Usually ends up in underruns.
To fix this let's go through the QGV point mask computation
if either the data rates/number of planes, or the state
of SAGV is changing.
v2: Check more carefully if things are changing to avoid
the extra calculations/debugs from introducing unwanted
overhead
Cc: sta...@vger.kernel.org
Reviewed-by: Stanislav Lisovskiy #v1
Fixes: 20f505f22531 ("drm/i915: Restrict qgv points which don't have enough
bandwidth.")
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_bw.c | 18 --
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
b/drivers/gpu/drm/i915/display/intel_bw.c
index 7bbe0dc5926b..1fd1d2182d8f 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -830,6 +830,7 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
unsigned int max_bw_point = 0, max_bw = 0;
unsigned int num_qgv_points = dev_priv->max_bw[0].num_qgv_points;
unsigned int num_psf_gv_points = dev_priv->max_bw[0].num_psf_gv_points;
+ bool changed = false;
u32 mask = 0;
/* FIXME earlier gens need some checks too */
@@ -873,6 +874,8 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
new_bw_state->data_rate[crtc->pipe] = new_data_rate;
new_bw_state->num_active_planes[crtc->pipe] = new_active_planes;
+ changed = true;
+
drm_dbg_kms(_priv->drm,
"pipe %c data rate %u num active planes %u\n",
pipe_name(crtc->pipe),
@@ -880,7 +883,19 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
new_bw_state->num_active_planes[crtc->pipe]);
}
- if (!new_bw_state)
+ old_bw_state = intel_atomic_get_old_bw_state(state);
+ new_bw_state = intel_atomic_get_new_bw_state(state);
+
+ if (new_bw_state &&
+ intel_can_enable_sagv(dev_priv, old_bw_state) !=
+ intel_can_enable_sagv(dev_priv, new_bw_state))
+ changed = true;
+
+ /*
+* If none of our inputs (data rates, number of active
+* planes, SAGV yes/no) changed then nothing to do here.
+*/
+ if (!changed)
return 0;
ret = intel_atomic_lock_global_state(_bw_state->base);
@@ -966,7 +981,6 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
*/
new_bw_state->qgv_points_mask = ~allowed_points & mask;
- old_bw_state = intel_atomic_get_old_bw_state(state);
/*
* If the actual mask had changed we need to make sure that
* the commits are serialized(in case this is a nomodeset, nonblocking)
--
2.34.1
[Intel-gfx] [PATCH v3 1/6] drm/i915: Correctly populate use_sagv_wm for all pipes
From: Ville Syrjälä
When changing between SAGV vs. no SAGV on tgl+ we have to
update the use_sagv_wm flag for all the crtcs or else
an active pipe not already in the state will end up using
the wrong watermarks. That is especially bad when we end up
with the tighter non-SAGV watermarks with SAGV enabled.
Usually ends up in underruns.
Cc: sta...@vger.kernel.org
Reviewed-by: Stanislav Lisovskiy
Fixes: 7241c57d3140 ("drm/i915: Add TGL+ SAGV support")
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d4d487f040a1..d0fcc4586983 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4008,6 +4008,17 @@ static int intel_compute_sagv_mask(struct
intel_atomic_state *state)
return ret;
}
+ if (intel_can_enable_sagv(dev_priv, new_bw_state) !=
+ intel_can_enable_sagv(dev_priv, old_bw_state)) {
+ ret = intel_atomic_serialize_global_state(_bw_state->base);
+ if (ret)
+ return ret;
+ } else if (new_bw_state->pipe_sagv_reject !=
old_bw_state->pipe_sagv_reject) {
+ ret = intel_atomic_lock_global_state(_bw_state->base);
+ if (ret)
+ return ret;
+ }
+
for_each_new_intel_crtc_in_state(state, crtc,
new_crtc_state, i) {
struct skl_pipe_wm *pipe_wm = _crtc_state->wm.skl.optimal;
@@ -4023,17 +4034,6 @@ static int intel_compute_sagv_mask(struct
intel_atomic_state *state)
intel_can_enable_sagv(dev_priv, new_bw_state);
}
- if (intel_can_enable_sagv(dev_priv, new_bw_state) !=
- intel_can_enable_sagv(dev_priv, old_bw_state)) {
- ret = intel_atomic_serialize_global_state(_bw_state->base);
- if (ret)
- return ret;
- } else if (new_bw_state->pipe_sagv_reject !=
old_bw_state->pipe_sagv_reject) {
- ret = intel_atomic_lock_global_state(_bw_state->base);
- if (ret)
- return ret;
- }
-
return 0;
}
--
2.34.1
[Intel-gfx] [PATCH v3 0/6] drm/i915: SAGV fixes
From: Ville Syrjälä While pokingaround the watermarks/etc. I noticed our SAGV code has a bunch of bugs. Let's try to fix it. OK, v3 which sould avoid the extra debug spew from the bw code. That should help make the stress tests pass in ci. Ville Syrjälä (6): drm/i915: Correctly populate use_sagv_wm for all pipes drm/i915: Fix bw atomic check when switching between SAGV vs. no SAGV drm/i915: Split pre-icl vs. icl+ SAGV hooks apart drm/i915: Pimp icl+ sagv pre/post update drm/i915: Extract icl_qgv_points_mask() drm/i915: Extract intel_bw_check_data_rate() drivers/gpu/drm/i915/display/intel_bw.c | 84 +++ drivers/gpu/drm/i915/intel_pm.c | 177 ++-- 2 files changed, 165 insertions(+), 96 deletions(-) -- 2.34.1
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/3] drm/i915: Fix for PHY_MISC_TC1 offset
== Series Details ==
Series: series starting with [CI,1/3] drm/i915: Fix for PHY_MISC_TC1 offset
URL : https://patchwork.freedesktop.org/series/100373/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11244 -> Patchwork_22326
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22326/index.html
Participating hosts (44 -> 41)
--
Additional (1): fi-kbl-8809g
Missing(4): fi-bsw-cyan bat-jsl-2 fi-bdw-5557u shard-tglu
Known issues
Here are the changes found in Patchwork_22326 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_cs_nop@sync-fork-gfx0:
- fi-skl-6600u: NOTRUN -> [SKIP][1] ([fdo#109271]) +21 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22326/fi-skl-6600u/igt@amdgpu/amd_cs_...@sync-fork-gfx0.html
* igt@gem_exec_suspend@basic-s0@smem:
- fi-kbl-8809g: NOTRUN -> [DMESG-WARN][2] ([i915#4962]) +1 similar
issue
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22326/fi-kbl-8809g/igt@gem_exec_suspend@basic...@smem.html
* igt@gem_huc_copy@huc-copy:
- fi-skl-6600u: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22326/fi-skl-6600u/igt@gem_huc_c...@huc-copy.html
- fi-kbl-8809g: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22326/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@random-engines:
- fi-kbl-8809g: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613]) +3
similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22326/fi-kbl-8809g/igt@gem_lmem_swapp...@random-engines.html
* igt@gem_lmem_swapping@verify-random:
- fi-skl-6600u: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#4613]) +3
similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22326/fi-skl-6600u/igt@gem_lmem_swapp...@verify-random.html
* igt@kms_chamelium@hdmi-edid-read:
- fi-kbl-8809g: NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827]) +8
similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22326/fi-kbl-8809g/igt@kms_chamel...@hdmi-edid-read.html
* igt@kms_chamelium@vga-edid-read:
- fi-skl-6600u: NOTRUN -> [SKIP][8] ([fdo#109271] / [fdo#111827]) +8
similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22326/fi-skl-6600u/igt@kms_chamel...@vga-edid-read.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
- fi-cfl-8109u: [PASS][9] -> [DMESG-WARN][10] ([i915#295]) +11
similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22326/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-skl-6600u: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#533])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22326/fi-skl-6600u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
- fi-kbl-8809g: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#533])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22326/fi-kbl-8809g/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
* igt@kms_psr@cursor_plane_move:
- fi-kbl-8809g: NOTRUN -> [SKIP][13] ([fdo#109271]) +54 similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22326/fi-kbl-8809g/igt@kms_psr@cursor_plane_move.html
Possible fixes
* igt@gem_exec_suspend@basic-s3@smem:
- fi-skl-6600u: [INCOMPLETE][14] ([i915#4547]) -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/fi-skl-6600u/igt@gem_exec_suspend@basic...@smem.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22326/fi-skl-6600u/igt@gem_exec_suspend@basic...@smem.html
* igt@i915_selftest@live@hangcheck:
- {fi-jsl-1}: [INCOMPLETE][16] -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/fi-jsl-1/igt@i915_selftest@l...@hangcheck.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22326/fi-jsl-1/igt@i915_selftest@l...@hangcheck.html
- bat-dg1-6: [DMESG-FAIL][18] ([i915#4494] / [i915#4957]) ->
[PASS][19]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22326/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,1/3] drm/i915: Fix for PHY_MISC_TC1 offset
== Series Details == Series: series starting with [CI,1/3] drm/i915: Fix for PHY_MISC_TC1 offset URL : https://patchwork.freedesktop.org/series/100373/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/3] drm/i915: Fix for PHY_MISC_TC1 offset
== Series Details == Series: series starting with [CI,1/3] drm/i915: Fix for PHY_MISC_TC1 offset URL : https://patchwork.freedesktop.org/series/100373/ State : warning == Summary == $ dim checkpatch origin/drm-tip 2bc5a2246dec drm/i915: Fix for PHY_MISC_TC1 offset -:49: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'port' - possible side-effects? #49: FILE: drivers/gpu/drm/i915/i915_reg.h:9360: +#define DG2_PHY_MISC(port) ((port) == PHY_E ? _MMIO(_DG2_PHY_MISC_TC1) : \ +ICL_PHY_MISC(port)) total: 0 errors, 0 warnings, 1 checks, 20 lines checked d20e83eacf5a drm/i915/dg2: Drop 38.4 MHz MPLLB tables f128d3a75f3d drm/i915/dg2: Enable 5th port
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dp: remove accidental static on what should be a local variable
== Series Details == Series: drm/i915/dp: remove accidental static on what should be a local variable URL : https://patchwork.freedesktop.org/series/100310/ State : success == Summary == CI Bug Log - changes from CI_DRM_11241_full -> Patchwork_22312_full Summary --- **SUCCESS** No regressions found. Participating hosts (11 -> 11) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_22312_full that come from known issues: ### IGT changes ### Issues hit * igt@api_intel_bb@blit-reloc-purge-cache: - shard-skl: [PASS][1] -> [DMESG-WARN][2] ([i915#1982]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11241/shard-skl1/igt@api_intel...@blit-reloc-purge-cache.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22312/shard-skl7/igt@api_intel...@blit-reloc-purge-cache.html * igt@gem_create@create-massive: - shard-kbl: NOTRUN -> [DMESG-WARN][3] ([i915#4991]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22312/shard-kbl7/igt@gem_cre...@create-massive.html * igt@gem_eio@in-flight-immediate: - shard-tglb: [PASS][4] -> [TIMEOUT][5] ([i915#3063]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11241/shard-tglb6/igt@gem_...@in-flight-immediate.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22312/shard-tglb2/igt@gem_...@in-flight-immediate.html * igt@gem_exec_balancer@parallel-ordering: - shard-tglb: NOTRUN -> [DMESG-FAIL][6] ([i915#5076]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22312/shard-tglb6/igt@gem_exec_balan...@parallel-ordering.html * igt@gem_exec_capture@pi@vecs0: - shard-iclb: NOTRUN -> [INCOMPLETE][7] ([i915#3371]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22312/shard-iclb6/igt@gem_exec_capture@p...@vecs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-kbl: NOTRUN -> [FAIL][8] ([i915#2842]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22312/shard-kbl6/igt@gem_exec_fair@basic-pace-s...@rcs0.html * igt@gem_lmem_swapping@heavy-verify-multi: - shard-kbl: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#4613]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22312/shard-kbl6/igt@gem_lmem_swapp...@heavy-verify-multi.html - shard-skl: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#4613]) +1 similar issue [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22312/shard-skl8/igt@gem_lmem_swapp...@heavy-verify-multi.html * igt@gem_lmem_swapping@parallel-random-verify: - shard-iclb: NOTRUN -> [SKIP][11] ([i915#4613]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22312/shard-iclb5/igt@gem_lmem_swapp...@parallel-random-verify.html * igt@gem_lmem_swapping@random-engines: - shard-apl: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#4613]) +2 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22312/shard-apl4/igt@gem_lmem_swapp...@random-engines.html * igt@gem_pwrite@basic-exhaustion: - shard-skl: NOTRUN -> [WARN][13] ([i915#2658]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22312/shard-skl1/igt@gem_pwr...@basic-exhaustion.html * igt@gem_pxp@create-regular-context-1: - shard-iclb: NOTRUN -> [SKIP][14] ([i915#4270]) +2 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22312/shard-iclb6/igt@gem_...@create-regular-context-1.html * igt@gem_pxp@protected-raw-src-copy-not-readible: - shard-tglb: NOTRUN -> [SKIP][15] ([i915#4270]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22312/shard-tglb6/igt@gem_...@protected-raw-src-copy-not-readible.html * igt@gem_softpin@evict-snoop-interruptible: - shard-iclb: NOTRUN -> [SKIP][16] ([fdo#109312]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22312/shard-iclb5/igt@gem_soft...@evict-snoop-interruptible.html * igt@gem_userptr_blits@unsync-unmap-after-close: - shard-tglb: NOTRUN -> [SKIP][17] ([i915#3297]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22312/shard-tglb6/igt@gem_userptr_bl...@unsync-unmap-after-close.html * igt@gem_userptr_blits@unsync-unmap-cycles: - shard-iclb: NOTRUN -> [SKIP][18] ([i915#3297]) +1 similar issue [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22312/shard-iclb6/igt@gem_userptr_bl...@unsync-unmap-cycles.html * igt@gen9_exec_parse@allowed-all: - shard-glk: [PASS][19] -> [DMESG-WARN][20] ([i915#1436] / [i915#716]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11241/shard-glk1/igt@gen9_exec_pa...@allowed-all.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22312/shard-glk5/igt@gen9_exec_pa...@allowed-all.html * igt@gen9_exec_parse@bb-large: -
[Intel-gfx] ✓ Fi.CI.BAT: success for Prep work for next GuC release (rev2)
== Series Details == Series: Prep work for next GuC release (rev2) URL : https://patchwork.freedesktop.org/series/99805/ State : success == Summary == CI Bug Log - changes from CI_DRM_11244 -> Patchwork_22325 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22325/index.html Participating hosts (44 -> 41) -- Additional (1): fi-kbl-8809g Missing(4): fi-bsw-cyan bat-jsl-2 shard-tglu fi-pnv-d510 Known issues Here are the changes found in Patchwork_22325 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s0@smem: - fi-kbl-8809g: NOTRUN -> [DMESG-WARN][1] ([i915#4962]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22325/fi-kbl-8809g/igt@gem_exec_suspend@basic...@smem.html * igt@gem_huc_copy@huc-copy: - fi-skl-6600u: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#2190]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22325/fi-skl-6600u/igt@gem_huc_c...@huc-copy.html - fi-kbl-8809g: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22325/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@random-engines: - fi-kbl-8809g: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +3 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22325/fi-kbl-8809g/igt@gem_lmem_swapp...@random-engines.html * igt@gem_lmem_swapping@verify-random: - fi-skl-6600u: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613]) +3 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22325/fi-skl-6600u/igt@gem_lmem_swapp...@verify-random.html * igt@i915_selftest@live@hangcheck: - fi-hsw-4770:[PASS][6] -> [INCOMPLETE][7] ([i915#4785]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22325/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html * igt@kms_chamelium@hdmi-edid-read: - fi-kbl-8809g: NOTRUN -> [SKIP][8] ([fdo#109271] / [fdo#111827]) +8 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22325/fi-kbl-8809g/igt@kms_chamel...@hdmi-edid-read.html * igt@kms_chamelium@vga-edid-read: - fi-skl-6600u: NOTRUN -> [SKIP][9] ([fdo#109271] / [fdo#111827]) +8 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22325/fi-skl-6600u/igt@kms_chamel...@vga-edid-read.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-skl-6600u: NOTRUN -> [SKIP][10] ([fdo#109271]) +2 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22325/fi-skl-6600u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html * igt@kms_frontbuffer_tracking@basic: - fi-cml-u2: [PASS][11] -> [DMESG-WARN][12] ([i915#4269]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22325/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b: - fi-cfl-8109u: [PASS][13] -> [DMESG-WARN][14] ([i915#295]) +12 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22325/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-b.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-skl-6600u: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#533]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22325/fi-skl-6600u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html - fi-kbl-8809g: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#533]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22325/fi-kbl-8809g/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html * igt@kms_psr@cursor_plane_move: - fi-kbl-8809g: NOTRUN -> [SKIP][17] ([fdo#109271]) +54 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22325/fi-kbl-8809g/igt@kms_psr@cursor_plane_move.html * igt@kms_psr@primary_page_flip: - fi-skl-6600u: NOTRUN -> [FAIL][18] ([i915#4547]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22325/fi-skl-6600u/igt@kms_psr@primary_page_flip.html * igt@runner@aborted: - fi-skl-6600u: NOTRUN -> [FAIL][19] ([i915#4312]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22325/fi-skl-6600u/igt@run...@aborted.html - fi-hsw-4770:NOTRUN -> [FAIL][20] ([fdo#109271] / [i915#1436] / [i915#4312]) [20]:
Re: [Intel-gfx] [PATCH v5 09/19] Doc/gpu/rfc/i915: i915 DG2 64k pagesize uAPI
On Tue, Feb 01, 2022 at 04:11:22PM +0530, Ramalingam C wrote: Details of the 64k pagesize support added as part of DG2 enabling and its implicit impact on the uAPI. v2: improvised the Flat-CCS documentation [Danvet & CQ] v3: made only for 64k pagesize support Signed-off-by: Ramalingam C cc: Daniel Vetter cc: Matthew Auld cc: Simon Ser cc: Pekka Paalanen Cc: Jordan Justen Cc: Kenneth Graunke Cc: mesa-...@lists.freedesktop.org Cc: Tony Ye Cc: Slawomir Milczarek --- Documentation/gpu/rfc/i915_dg2.rst | 25 + Documentation/gpu/rfc/index.rst| 3 +++ 2 files changed, 28 insertions(+) create mode 100644 Documentation/gpu/rfc/i915_dg2.rst diff --git a/Documentation/gpu/rfc/i915_dg2.rst b/Documentation/gpu/rfc/i915_dg2.rst new file mode 100644 index ..f4eb5a219897 --- /dev/null +++ b/Documentation/gpu/rfc/i915_dg2.rst @@ -0,0 +1,25 @@ + +I915 DG2 RFC Section + + +Upstream plan += +Plan to upstream the DG2 enabling is: + +* Merge basic HW enabling for DG2 (Still without pciid) +* Merge the 64k support for lmem +* Merge the flat CCS enabling patches +* Add the pciid for DG2 and enable the DG2 in CI does this make sense after the fact? Earlier version of this patch Daniel Vetter asked this to be moved to the be the first patch. I see you added it in the cover letter, but keeping this in gpu/rfc/i915_dg2.rst doesn't make much sense IMO. Maybe just drop this patch? Lucas De Marchi + + +64K page support for lmem += +On DG2 hw, local-memory supports minimum GTT page size of 64k only. 4k is not +supported anymore. + +DG2 hw doesn't support the 64k (lmem) and 4k (smem) pages in the same ppgtt +Page table. Refer the struct drm_i915_gem_create_ext for the implication of +handling the 64k page size. + +.. kernel-doc:: include/uapi/drm/i915_drm.h +:functions: drm_i915_gem_create_ext diff --git a/Documentation/gpu/rfc/index.rst b/Documentation/gpu/rfc/index.rst index 91e93a705230..afb320ed4028 100644 --- a/Documentation/gpu/rfc/index.rst +++ b/Documentation/gpu/rfc/index.rst @@ -20,6 +20,9 @@ host such documentation: i915_gem_lmem.rst +.. toctree:: +i915_dg2.rst + .. toctree:: i915_scheduler.rst -- 2.20.1
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Prep work for next GuC release (rev2)
== Series Details == Series: Prep work for next GuC release (rev2) URL : https://patchwork.freedesktop.org/series/99805/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/4] drm/i915/dsi: disassociate VBT video transfer mode from register values
== Series Details == Series: series starting with [CI,1/4] drm/i915/dsi: disassociate VBT video transfer mode from register values URL : https://patchwork.freedesktop.org/series/100368/ State : success == Summary == CI Bug Log - changes from CI_DRM_11244 -> Patchwork_22324 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22324/index.html Participating hosts (44 -> 41) -- Additional (1): fi-kbl-8809g Missing(4): fi-bsw-cyan bat-jsl-2 shard-tglu fi-pnv-d510 Known issues Here are the changes found in Patchwork_22324 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_cs_nop@sync-fork-compute0: - fi-snb-2600:NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22324/fi-snb-2600/igt@amdgpu/amd_cs_...@sync-fork-compute0.html * igt@gem_exec_suspend@basic-s0@smem: - fi-kbl-8809g: NOTRUN -> [DMESG-WARN][2] ([i915#4962]) +1 similar issue [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22324/fi-kbl-8809g/igt@gem_exec_suspend@basic...@smem.html * igt@gem_huc_copy@huc-copy: - fi-skl-6600u: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22324/fi-skl-6600u/igt@gem_huc_c...@huc-copy.html - fi-kbl-8809g: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22324/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@random-engines: - fi-kbl-8809g: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613]) +3 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22324/fi-kbl-8809g/igt@gem_lmem_swapp...@random-engines.html * igt@gem_lmem_swapping@verify-random: - fi-skl-6600u: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#4613]) +3 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22324/fi-skl-6600u/igt@gem_lmem_swapp...@verify-random.html * igt@i915_selftest@live@hangcheck: - fi-hsw-4770:[PASS][7] -> [INCOMPLETE][8] ([i915#4785]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22324/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html - fi-bdw-5557u: NOTRUN -> [INCOMPLETE][9] ([i915#3921]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22324/fi-bdw-5557u/igt@i915_selftest@l...@hangcheck.html * igt@kms_chamelium@dp-crc-fast: - fi-bdw-5557u: NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) +8 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22324/fi-bdw-5557u/igt@kms_chamel...@dp-crc-fast.html * igt@kms_chamelium@hdmi-edid-read: - fi-kbl-8809g: NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) +8 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22324/fi-kbl-8809g/igt@kms_chamel...@hdmi-edid-read.html * igt@kms_chamelium@vga-edid-read: - fi-skl-6600u: NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +8 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22324/fi-skl-6600u/igt@kms_chamel...@vga-edid-read.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-skl-6600u: NOTRUN -> [SKIP][13] ([fdo#109271]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22324/fi-skl-6600u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html * igt@kms_frontbuffer_tracking@basic: - fi-cml-u2: [PASS][14] -> [DMESG-WARN][15] ([i915#4269]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22324/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-skl-6600u: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#533]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22324/fi-skl-6600u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html - fi-kbl-8809g: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#533]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22324/fi-kbl-8809g/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html * igt@kms_psr@cursor_plane_move: - fi-kbl-8809g: NOTRUN -> [SKIP][18] ([fdo#109271]) +54 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22324/fi-kbl-8809g/igt@kms_psr@cursor_plane_move.html - fi-bdw-5557u: NOTRUN -> [SKIP][19] ([fdo#109271]) +13 similar issues [19]:
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/mm: Add an iterator to optimally walk over holes suitable for an allocation (rev2)
== Series Details == Series: drm/mm: Add an iterator to optimally walk over holes suitable for an allocation (rev2) URL : https://patchwork.freedesktop.org/series/100136/ State : success == Summary == CI Bug Log - changes from CI_DRM_11241_full -> Patchwork_22310_full Summary --- **SUCCESS** No regressions found. Participating hosts (11 -> 11) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_22310_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@preservation-s3@bcs0: - shard-kbl: NOTRUN -> [DMESG-WARN][1] ([i915#180]) +2 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22310/shard-kbl1/igt@gem_ctx_isolation@preservation...@bcs0.html * igt@gem_exec_balancer@parallel-ordering: - shard-tglb: NOTRUN -> [DMESG-FAIL][2] ([i915#5076]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22310/shard-tglb3/igt@gem_exec_balan...@parallel-ordering.html * igt@gem_exec_capture@pi@bcs0: - shard-skl: NOTRUN -> [INCOMPLETE][3] ([i915#4547]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22310/shard-skl9/igt@gem_exec_capture@p...@bcs0.html * igt@gem_exec_fair@basic-deadline: - shard-skl: NOTRUN -> [FAIL][4] ([i915#2846]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22310/shard-skl4/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: [PASS][5] -> [FAIL][6] ([i915#2842]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11241/shard-glk8/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22310/shard-glk6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_whisper@basic-normal-all: - shard-glk: [PASS][7] -> [DMESG-WARN][8] ([i915#118]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11241/shard-glk8/igt@gem_exec_whis...@basic-normal-all.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22310/shard-glk6/igt@gem_exec_whis...@basic-normal-all.html * igt@gem_exec_whisper@basic-queues-forked-all: - shard-iclb: [PASS][9] -> [INCOMPLETE][10] ([i915#1895]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11241/shard-iclb6/igt@gem_exec_whis...@basic-queues-forked-all.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22310/shard-iclb7/igt@gem_exec_whis...@basic-queues-forked-all.html * igt@gem_lmem_swapping@heavy-verify-multi: - shard-skl: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#4613]) +2 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22310/shard-skl4/igt@gem_lmem_swapp...@heavy-verify-multi.html - shard-apl: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#4613]) +1 similar issue [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22310/shard-apl4/igt@gem_lmem_swapp...@heavy-verify-multi.html * igt@gem_pwrite@basic-exhaustion: - shard-skl: NOTRUN -> [WARN][13] ([i915#2658]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22310/shard-skl8/igt@gem_pwr...@basic-exhaustion.html * igt@gem_pxp@protected-raw-src-copy-not-readible: - shard-tglb: NOTRUN -> [SKIP][14] ([i915#4270]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22310/shard-tglb3/igt@gem_...@protected-raw-src-copy-not-readible.html * igt@gem_render_copy@y-tiled-to-vebox-yf-tiled: - shard-iclb: NOTRUN -> [SKIP][15] ([i915#768]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22310/shard-iclb6/igt@gem_render_c...@y-tiled-to-vebox-yf-tiled.html * igt@gem_userptr_blits@unsync-unmap-after-close: - shard-tglb: NOTRUN -> [SKIP][16] ([i915#3297]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22310/shard-tglb3/igt@gem_userptr_bl...@unsync-unmap-after-close.html * igt@gen9_exec_parse@basic-rejected: - shard-iclb: NOTRUN -> [SKIP][17] ([i915#2856]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22310/shard-iclb6/igt@gen9_exec_pa...@basic-rejected.html * igt@i915_pm_dc@dc6-dpms: - shard-kbl: NOTRUN -> [FAIL][18] ([i915#454]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22310/shard-kbl7/igt@i915_pm...@dc6-dpms.html * igt@i915_pm_dc@dc6-psr: - shard-iclb: NOTRUN -> [FAIL][19] ([i915#454]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22310/shard-iclb6/igt@i915_pm...@dc6-psr.html * igt@i915_pm_rpm@modeset-pc8-residency-stress: - shard-apl: NOTRUN -> [SKIP][20] ([fdo#109271]) +110 similar issues [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22310/shard-apl3/igt@i915_pm_...@modeset-pc8-residency-stress.html * igt@i915_selftest@live@hangcheck: -
Re: [Intel-gfx] [PATCH v8 5/5] drm/i915/uapi: document behaviour for DG2 64K support
Robert Beckett writes:
> From: Matthew Auld
>
> On discrete platforms like DG2, we need to support a minimum page size
> of 64K when dealing with device local-memory. This is quite tricky for
> various reasons, so try to document the new implicit uapi for this.
>
> v3: fix typos and less emphasis
> v2: Fixed suggestions on formatting [Daniel]
>
> Signed-off-by: Matthew Auld
> Signed-off-by: Ramalingam C
> Signed-off-by: Robert Beckett
> Acked-by: Jordan Justen
> Reviewed-by: Ramalingam C
> Reviewed-by: Thomas Hellström
> cc: Simon Ser
> cc: Pekka Paalanen
> Cc: Jordan Justen
> Cc: Kenneth Graunke
> Cc: mesa-...@lists.freedesktop.org
> Cc: Tony Ye
> Cc: Slawomir Milczarek
> ---
> include/uapi/drm/i915_drm.h | 44 -
> 1 file changed, 39 insertions(+), 5 deletions(-)
>
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 5e678917da70..77e5e74c32c1 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -1118,10 +1118,16 @@ struct drm_i915_gem_exec_object2 {
> /**
>* When the EXEC_OBJECT_PINNED flag is specified this is populated by
>* the user with the GTT offset at which this object will be pinned.
> + *
>* When the I915_EXEC_NO_RELOC flag is specified this must contain the
>* presumed_offset of the object.
> + *
>* During execbuffer2 the kernel populates it with the value of the
>* current GTT offset of the object, for future presumed_offset writes.
> + *
> + * See struct drm_i915_gem_create_ext for the rules when dealing with
> + * alignment restrictions with I915_MEMORY_CLASS_DEVICE, on devices with
> + * minimum page sizes, like DG2.
>*/
> __u64 offset;
>
> @@ -3145,11 +3151,39 @@ struct drm_i915_gem_create_ext {
>*
>* The (page-aligned) allocated size for the object will be returned.
>*
> - * Note that for some devices we have might have further minimum
> - * page-size restrictions(larger than 4K), like for device local-memory.
> - * However in general the final size here should always reflect any
> - * rounding up, if for example using the
> I915_GEM_CREATE_EXT_MEMORY_REGIONS
> - * extension to place the object in device local-memory.
> + *
> + * DG2 64K min page size implications:
> + *
> + * On discrete platforms, starting from DG2, we have to contend with GTT
> + * page size restrictions when dealing with I915_MEMORY_CLASS_DEVICE
> + * objects. Specifically the hardware only supports 64K or larger GTT
> + * page sizes for such memory. The kernel will already ensure that all
> + * I915_MEMORY_CLASS_DEVICE memory is allocated using 64K or larger page
> + * sizes underneath.
> + *
> + * Note that the returned size here will always reflect any required
> + * rounding up done by the kernel, i.e 4K will now become 64K on devices
> + * such as DG2.
> + *
> + * Special DG2 GTT address alignment requirement:
> + *
> + * The GTT alignment will also need to be at least 2M for such objects.
> + *
> + * Note that due to how the hardware implements 64K GTT page support, we
> + * have some further complications:
> + *
> + * 1) The entire PDE (which covers a 2MB virtual address range), must
> + * contain only 64K PTEs, i.e mixing 4K and 64K PTEs in the same
> + * PDE is forbidden by the hardware.
> + *
> + * 2) We still need to support 4K PTEs for I915_MEMORY_CLASS_SYSTEM
> + * objects.
> + *
> + * To keep things simple for userland, we mandate that any GTT mappings
> + * must be aligned to and rounded up to 2MB.
Could I get a clarification about this "rounded up" part.
Currently Mesa is aligning the start of each and every buffer VMA to be
2MiB aligned. But, we are *not* taking any steps to "round up" the size
of buffers to 2MiB alignment.
Bob's Mesa MR from a while ago,
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14599
was trying to add this "round up" size for buffers. We didn't accept
this MR because we thought if we have ensured that no other buffer will
use the same 2MiB VMA range, then it should not be required.
If what we are doing is ok, then maybe this "round up" language should
be dropped? Or, perhaps the "round up" mentioned here isn't implying we
must align the size of buffers that we create, and I'm misinterpreting
this.
-Jordan
> As this only wastes virtual
> + * address space and avoids userland having to copy any needlessly
> + * complicated PDE sharing scheme (coloring) and only affects DG2, this
> + * is deemed to be a good compromise.
>*/
> __u64 size;
> /**
> --
> 2.25.1
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,1/4] drm/i915/dsi: disassociate VBT video transfer mode from register values
== Series Details == Series: series starting with [CI,1/4] drm/i915/dsi: disassociate VBT video transfer mode from register values URL : https://patchwork.freedesktop.org/series/100368/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/4] drm/i915/dsi: disassociate VBT video transfer mode from register values
== Series Details == Series: series starting with [CI,1/4] drm/i915/dsi: disassociate VBT video transfer mode from register values URL : https://patchwork.freedesktop.org/series/100368/ State : warning == Summary == $ dim checkpatch origin/drm-tip 0eacdf7065b7 drm/i915/dsi: disassociate VBT video transfer mode from register values c08265978a8c drm/i915/dsi: add separate init timer mask definition for ICL DSI 1a48c1109e26 drm/i915/reg: split out vlv_dsi_regs.h and vlv_dsi_pll_regs.h -:66: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #66: new file mode 100644 -:275: WARNING:LONG_LINE: line length of 106 exceeds 100 columns #275: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:90: +#define MIPI_TEARING_CTRL(port)_MMIO_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL) -:368: WARNING:LONG_LINE: line length of 112 exceeds 100 columns #368: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:183: +#define MIPI_TURN_AROUND_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT) -:373: WARNING:LONG_LINE: line length of 110 exceeds 100 columns #373: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:188: +#define MIPI_DEVICE_RESET_TIMER(port) _MMIO_MIPI(port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER) -:378: WARNING:LONG_LINE: line length of 102 exceeds 100 columns #378: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:193: +#define MIPI_DPI_RESOLUTION(port) _MMIO_MIPI(port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION) -:386: WARNING:LONG_LINE: line length of 108 exceeds 100 columns #386: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:201: +#define MIPI_DBI_FIFO_THROTTLE(port) _MMIO_MIPI(port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE) -:394: WARNING:LONG_LINE: line length of 112 exceeds 100 columns #394: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:209: +#define MIPI_HSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT) -:406: WARNING:LONG_LINE: line length of 110 exceeds 100 columns #406: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:221: +#define MIPI_HACTIVE_AREA_COUNT(port) _MMIO_MIPI(port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT) -:410: WARNING:LONG_LINE: line length of 112 exceeds 100 columns #410: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:225: +#define MIPI_VSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT) -:422: WARNING:LONG_LINE: line length of 131 exceeds 100 columns #422: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:237: +#define MIPI_HIGH_LOW_SWITCH_COUNT(port) _MMIO_MIPI(port, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT) -:456: WARNING:LONG_LINE: line length of 108 exceeds 100 columns #456: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:271: +#define MIPI_VIDEO_MODE_FORMAT(port) _MMIO_MIPI(port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT) -:486: WARNING:LONG_LINE: line length of 105 exceeds 100 columns #486: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:301: +#define MIPI_TLPX_TIME_COUNT(port) _MMIO_MIPI(port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT) -:490: WARNING:LONG_LINE: line length of 105 exceeds 100 columns #490: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:305: +#define MIPI_CLK_LANE_TIMING(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING) -:538: WARNING:LONG_LINE: line length of 106 exceeds 100 columns #538: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:353: +#define MIPI_HS_LP_DBI_ENABLE(port)_MMIO_MIPI(port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE) -:561: WARNING:LONG_LINE: line length of 130 exceeds 100 columns #561: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:376: +#define MIPI_CLK_LANE_SWITCH_TIME_CNT(port)_MMIO_MIPI(port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT) -:569: WARNING:LONG_LINE: line length of 106 exceeds 100 columns #569: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:384: +#define MIPI_STOP_STATE_STALL(port)_MMIO_MIPI(port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL) -:575: WARNING:LONG_LINE: line length of 104 exceeds 100 columns #575: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:390: +#define MIPI_INTR_STAT_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1) -:643: WARNING:LONG_LINE: line length of 104 exceeds 100 columns #643: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:458: +#define MIPI_COMMAND_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS) -:652: WARNING:LONG_LINE: line length of 102 exceeds 100 columns #652: FILE: drivers/gpu/drm/i915/display/vlv_dsi_regs.h:467: +#define MIPI_COMMAND_LENGTH(port) _MMIO_MIPI(port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH) -:658: WARNING:LONG_LINE: line length of 134 exceeds 100 columns #658:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Fix flag query helper function to not modify state
== Series Details ==
Series: drm/i915/guc: Fix flag query helper function to not modify state
URL : https://patchwork.freedesktop.org/series/100364/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11244 -> Patchwork_22323
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22323/index.html
Participating hosts (44 -> 42)
--
Additional (1): fi-kbl-8809g
Missing(3): fi-bsw-cyan bat-jsl-2 shard-tglu
Known issues
Here are the changes found in Patchwork_22323 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s0@smem:
- fi-kbl-8809g: NOTRUN -> [DMESG-WARN][1] ([i915#4962]) +1 similar
issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22323/fi-kbl-8809g/igt@gem_exec_suspend@basic...@smem.html
* igt@gem_huc_copy@huc-copy:
- fi-skl-6600u: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#2190])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22323/fi-skl-6600u/igt@gem_huc_c...@huc-copy.html
- fi-kbl-8809g: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22323/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@random-engines:
- fi-kbl-8809g: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +3
similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22323/fi-kbl-8809g/igt@gem_lmem_swapp...@random-engines.html
* igt@gem_lmem_swapping@verify-random:
- fi-skl-6600u: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613]) +3
similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22323/fi-skl-6600u/igt@gem_lmem_swapp...@verify-random.html
* igt@i915_pm_rpm@basic-rte:
- fi-kbl-8809g: NOTRUN -> [SKIP][6] ([fdo#109271]) +54 similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22323/fi-kbl-8809g/igt@i915_pm_...@basic-rte.html
* igt@kms_chamelium@hdmi-edid-read:
- fi-kbl-8809g: NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827]) +8
similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22323/fi-kbl-8809g/igt@kms_chamel...@hdmi-edid-read.html
* igt@kms_chamelium@vga-edid-read:
- fi-skl-6600u: NOTRUN -> [SKIP][8] ([fdo#109271] / [fdo#111827]) +8
similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22323/fi-skl-6600u/igt@kms_chamel...@vga-edid-read.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-skl-6600u: NOTRUN -> [SKIP][9] ([fdo#109271]) +21 similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22323/fi-skl-6600u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-skl-6600u: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#533])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22323/fi-skl-6600u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
- fi-kbl-8809g: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#533])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22323/fi-kbl-8809g/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
Possible fixes
* igt@gem_exec_suspend@basic-s3@smem:
- fi-skl-6600u: [INCOMPLETE][12] ([i915#4547]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/fi-skl-6600u/igt@gem_exec_suspend@basic...@smem.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22323/fi-skl-6600u/igt@gem_exec_suspend@basic...@smem.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-5: [DMESG-FAIL][14] ([i915#4494] / [i915#4957]) ->
[PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22323/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
- {fi-jsl-1}: [INCOMPLETE][16] -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/fi-jsl-1/igt@i915_selftest@l...@hangcheck.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22323/fi-jsl-1/igt@i915_selftest@l...@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#4494]:
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: SAGV fixes (rev2)
On Thu, Feb 17, 2022 at 08:03:41PM -, Patchwork wrote: > == Series Details == > > Series: drm/i915: SAGV fixes (rev2) > URL : https://patchwork.freedesktop.org/series/100091/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_11239_full -> Patchwork_22302_full > > > Summary > --- > > **FAILURE** > > Serious unknown changes coming with Patchwork_22302_full absolutely need to > be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_22302_full, please notify your bug team to allow > them > to document this new failure mode, which will reduce false positives in CI. > > > > Participating hosts (11 -> 11) > -- > > No changes in participating hosts > > Possible new issues > --- > > Here are the unknown changes that may have been introduced in > Patchwork_22302_full: > > ### IGT changes ### > > Possible regressions > > * igt@kms_cursor_legacy@all-pipes-forked-bo: > - shard-iclb: [PASS][1] -> [INCOMPLETE][2] +10 similar issues Argh. These are due to the extra debug spam from intel_bw_atomic_check() since that now goes throug the full function a lot more. So either we just nuke a bunch of those debugs, or I guess we do it a bit more like what Stan suggested and try to check more carefully if the inputs to to the QGV calculation actually changed. I guess I'll try the latter approach, in case those debugs are actually useful. The challenge will be doing that and keeping the patch looking reasonable for stable... -- Ville Syrjälä Intel
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Plane/wm cleanups (rev3)
== Series Details == Series: drm/i915: Plane/wm cleanups (rev3) URL : https://patchwork.freedesktop.org/series/100020/ State : success == Summary == CI Bug Log - changes from CI_DRM_11241_full -> Patchwork_22307_full Summary --- **SUCCESS** No regressions found. Participating hosts (11 -> 11) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_22307_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_create@create-massive: - shard-skl: NOTRUN -> [DMESG-WARN][1] ([i915#4991]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22307/shard-skl8/igt@gem_cre...@create-massive.html * igt@gem_ctx_isolation@preservation-s3@vcs0: - shard-kbl: NOTRUN -> [DMESG-WARN][2] ([i915#180]) +4 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22307/shard-kbl4/igt@gem_ctx_isolation@preservation...@vcs0.html * igt@gem_exec_balancer@parallel-ordering: - shard-tglb: NOTRUN -> [DMESG-FAIL][3] ([i915#5076]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22307/shard-tglb1/igt@gem_exec_balan...@parallel-ordering.html * igt@gem_exec_capture@pi@bcs0: - shard-iclb: NOTRUN -> [INCOMPLETE][4] ([i915#3371]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22307/shard-iclb5/igt@gem_exec_capture@p...@bcs0.html * igt@gem_exec_capture@pi@rcs0: - shard-skl: NOTRUN -> [INCOMPLETE][5] ([i915#4547]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22307/shard-skl2/igt@gem_exec_capture@p...@rcs0.html * igt@gem_exec_fair@basic-deadline: - shard-skl: NOTRUN -> [FAIL][6] ([i915#2846]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22307/shard-skl9/igt@gem_exec_f...@basic-deadline.html * igt@gem_exec_fair@basic-none-vip@rcs0: - shard-kbl: [PASS][7] -> [FAIL][8] ([i915#2842]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11241/shard-kbl3/igt@gem_exec_fair@basic-none-...@rcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22307/shard-kbl7/igt@gem_exec_fair@basic-none-...@rcs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-tglb: [PASS][9] -> [FAIL][10] ([i915#2842]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11241/shard-tglb8/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22307/shard-tglb5/igt@gem_exec_fair@basic-pace-sh...@rcs0.html - shard-glk: [PASS][11] -> [FAIL][12] ([i915#2842]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11241/shard-glk8/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22307/shard-glk3/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-iclb: [PASS][13] -> [FAIL][14] ([i915#2849]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11241/shard-iclb7/igt@gem_exec_fair@basic-throt...@rcs0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22307/shard-iclb1/igt@gem_exec_fair@basic-throt...@rcs0.html * igt@gem_lmem_swapping@heavy-verify-multi: - shard-kbl: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4613]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22307/shard-kbl3/igt@gem_lmem_swapp...@heavy-verify-multi.html - shard-skl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4613]) +2 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22307/shard-skl9/igt@gem_lmem_swapp...@heavy-verify-multi.html * igt@gem_lmem_swapping@parallel-random-verify: - shard-iclb: NOTRUN -> [SKIP][17] ([i915#4613]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22307/shard-iclb8/igt@gem_lmem_swapp...@parallel-random-verify.html * igt@gem_lmem_swapping@random-engines: - shard-apl: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#4613]) +2 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22307/shard-apl7/igt@gem_lmem_swapp...@random-engines.html * igt@gem_pwrite@basic-exhaustion: - shard-skl: NOTRUN -> [WARN][19] ([i915#2658]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22307/shard-skl10/igt@gem_pwr...@basic-exhaustion.html * igt@gem_pxp@create-regular-context-1: - shard-iclb: NOTRUN -> [SKIP][20] ([i915#4270]) +2 similar issues [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22307/shard-iclb5/igt@gem_...@create-regular-context-1.html * igt@gem_pxp@protected-raw-src-copy-not-readible: - shard-tglb: NOTRUN -> [SKIP][21] ([i915#4270]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22307/shard-tglb1/igt@gem_...@protected-raw-src-copy-not-readible.html *
[Intel-gfx] ✗ Fi.CI.BAT: failure for Move #define wbvind_on_all_cpus (rev2)
== Series Details == Series: Move #define wbvind_on_all_cpus (rev2) URL : https://patchwork.freedesktop.org/series/1/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11244 -> Patchwork_22322 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_22322 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_22322, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22322/index.html Participating hosts (44 -> 40) -- Additional (1): fi-kbl-8809g Missing(5): fi-bdw-5557u shard-tglu fi-bsw-cyan fi-pnv-d510 bat-jsl-2 Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_22322: ### IGT changes ### Possible regressions * igt@gem_exec_fence@basic-busy@rcs0: - fi-blb-e6850: [PASS][1] -> [DMESG-WARN][2] +15 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/fi-blb-e6850/igt@gem_exec_fence@basic-b...@rcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22322/fi-blb-e6850/igt@gem_exec_fence@basic-b...@rcs0.html * igt@gem_exec_fence@nb-await@vecs0: - fi-glk-dsi: [PASS][3] -> [DMESG-WARN][4] +15 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/fi-glk-dsi/igt@gem_exec_fence@nb-aw...@vecs0.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22322/fi-glk-dsi/igt@gem_exec_fence@nb-aw...@vecs0.html * igt@gem_exec_suspend@basic-s0@smem: - fi-kbl-guc: [PASS][5] -> [DMESG-WARN][6] +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/fi-kbl-guc/igt@gem_exec_suspend@basic...@smem.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22322/fi-kbl-guc/igt@gem_exec_suspend@basic...@smem.html - fi-bsw-nick:[PASS][7] -> [DMESG-WARN][8] +13 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/fi-bsw-nick/igt@gem_exec_suspend@basic...@smem.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22322/fi-bsw-nick/igt@gem_exec_suspend@basic...@smem.html - fi-glk-j4005: [PASS][9] -> [DMESG-WARN][10] +15 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/fi-glk-j4005/igt@gem_exec_suspend@basic...@smem.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22322/fi-glk-j4005/igt@gem_exec_suspend@basic...@smem.html - fi-kbl-x1275: [PASS][11] -> [DMESG-WARN][12] +3 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/fi-kbl-x1275/igt@gem_exec_suspend@basic...@smem.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22322/fi-kbl-x1275/igt@gem_exec_suspend@basic...@smem.html - fi-kbl-7567u: [PASS][13] -> [DMESG-WARN][14] +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/fi-kbl-7567u/igt@gem_exec_suspend@basic...@smem.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22322/fi-kbl-7567u/igt@gem_exec_suspend@basic...@smem.html - fi-skl-6600u: [PASS][15] -> [DMESG-WARN][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/fi-skl-6600u/igt@gem_exec_suspend@basic...@smem.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22322/fi-skl-6600u/igt@gem_exec_suspend@basic...@smem.html * igt@gem_exec_suspend@basic-s3@smem: - fi-elk-e7500: [PASS][17] -> [DMESG-WARN][18] +15 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/fi-elk-e7500/igt@gem_exec_suspend@basic...@smem.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22322/fi-elk-e7500/igt@gem_exec_suspend@basic...@smem.html - bat-dg1-6: [PASS][19] -> [DMESG-WARN][20] +4 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/bat-dg1-6/igt@gem_exec_suspend@basic...@smem.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22322/bat-dg1-6/igt@gem_exec_suspend@basic...@smem.html - fi-skl-6700k2: [PASS][21] -> [DMESG-WARN][22] +3 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/fi-skl-6700k2/igt@gem_exec_suspend@basic...@smem.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22322/fi-skl-6700k2/igt@gem_exec_suspend@basic...@smem.html - fi-skl-guc: [PASS][23] -> [DMESG-WARN][24] +3 similar issues [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/fi-skl-guc/igt@gem_exec_suspend@basic...@smem.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22322/fi-skl-guc/igt@gem_exec_suspend@basic...@smem.html - fi-cfl-guc: [PASS][25] -> [DMESG-WARN][26] +3 similar issues
Re: [Intel-gfx] [PATCH v2 1/3] drm/mm: Ensure that the entry is not NULL before extracting rb_node
Hi Tvrtko,
>
> On 17/02/2022 07:50, Vivek Kasireddy wrote:
> > While looking for next holes suitable for an allocation, although,
> > it is highly unlikely, make sure that the DECLARE_NEXT_HOLE_ADDR
> > macro is using a valid node before it extracts the rb_node from it.
>
> Was the need for this just a consequence of insufficient locking in the
> i915 patch?
[Kasireddy, Vivek] Partly, yes; but I figured since we are anyway doing
if (!entry || ..), it makes sense to dereference entry and extract the rb_node
after this check.
Thanks,
Vivek
>
> Regards,
>
> Tvrtko
>
> >
> > Cc: Tvrtko Ursulin
> > Cc: Christian König
> > Signed-off-by: Vivek Kasireddy
> > ---
> > drivers/gpu/drm/drm_mm.c | 5 +++--
> > 1 file changed, 3 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/drm_mm.c b/drivers/gpu/drm/drm_mm.c
> > index 8257f9d4f619..499d8874e4ed 100644
> > --- a/drivers/gpu/drm/drm_mm.c
> > +++ b/drivers/gpu/drm/drm_mm.c
> > @@ -389,11 +389,12 @@ first_hole(struct drm_mm *mm,
> > #define DECLARE_NEXT_HOLE_ADDR(name, first, last) \
> > static struct drm_mm_node *name(struct drm_mm_node *entry, u64 size)
> > \
> > { \
> > - struct rb_node *parent, *node = >rb_hole_addr; \
> > + struct rb_node *parent, *node; \
> > \
> > - if (!entry || RB_EMPTY_NODE(node)) \
> > + if (!entry || RB_EMPTY_NODE(>rb_hole_addr)) \
> > return NULL;\
> > \
> > + node = >rb_hole_addr;\
> > if (usable_hole_addr(node->first, size)) { \
> > node = node->first; \
> > while (usable_hole_addr(node->last, size)) \
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Move #define wbvind_on_all_cpus (rev2)
== Series Details == Series: Move #define wbvind_on_all_cpus (rev2) URL : https://patchwork.freedesktop.org/series/1/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Move #define wbvind_on_all_cpus (rev2)
== Series Details == Series: Move #define wbvind_on_all_cpus (rev2) URL : https://patchwork.freedesktop.org/series/1/ State : warning == Summary == $ dim checkpatch origin/drm-tip 0ef1e9cb0b7b drm_cache: Add logic for wbvind_on_all_cpus -:34: WARNING:INCLUDE_LINUX: Use #include instead of #34: FILE: include/drm/drm_cache.h:37: +#include total: 0 errors, 1 warnings, 0 checks, 20 lines checked 02a63cd8aa4b drm/i915/gem: Remove logic for wbinvd_on_all_cpus 58c17009b626 drm/i915/: Add drm_cache.h
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc/slpc: Use wrapper for reading RP_STATE_CAP (rev2)
== Series Details ==
Series: drm/i915/guc/slpc: Use wrapper for reading RP_STATE_CAP (rev2)
URL : https://patchwork.freedesktop.org/series/100217/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11244 -> Patchwork_22321
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22321/index.html
Participating hosts (44 -> 41)
--
Additional (1): fi-kbl-8809g
Missing(4): fi-bsw-cyan bat-jsl-2 shard-tglu fi-pnv-d510
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_22321:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@hangcheck:
- {fi-ehl-2}: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/fi-ehl-2/igt@i915_selftest@l...@hangcheck.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22321/fi-ehl-2/igt@i915_selftest@l...@hangcheck.html
Known issues
Here are the changes found in Patchwork_22321 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-snb-2600:NOTRUN -> [SKIP][3] ([fdo#109271]) +17 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22321/fi-snb-2600/igt@amdgpu/amd_cs_...@sync-fork-compute0.html
* igt@gem_exec_suspend@basic-s0@smem:
- fi-kbl-8809g: NOTRUN -> [DMESG-WARN][4] ([i915#4962]) +1 similar
issue
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22321/fi-kbl-8809g/igt@gem_exec_suspend@basic...@smem.html
* igt@gem_exec_suspend@basic-s3@smem:
- fi-bdw-5557u: [PASS][5] -> [INCOMPLETE][6] ([i915#146])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/fi-bdw-5557u/igt@gem_exec_suspend@basic...@smem.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22321/fi-bdw-5557u/igt@gem_exec_suspend@basic...@smem.html
* igt@gem_huc_copy@huc-copy:
- fi-skl-6600u: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#2190])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22321/fi-skl-6600u/igt@gem_huc_c...@huc-copy.html
- fi-kbl-8809g: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#2190])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22321/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@random-engines:
- fi-kbl-8809g: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#4613]) +3
similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22321/fi-kbl-8809g/igt@gem_lmem_swapp...@random-engines.html
* igt@gem_lmem_swapping@verify-random:
- fi-skl-6600u: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#4613]) +3
similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22321/fi-skl-6600u/igt@gem_lmem_swapp...@verify-random.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[PASS][11] -> [INCOMPLETE][12] ([i915#3303])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22321/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
* igt@kms_chamelium@hdmi-edid-read:
- fi-kbl-8809g: NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827]) +8
similar issues
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22321/fi-kbl-8809g/igt@kms_chamel...@hdmi-edid-read.html
* igt@kms_chamelium@vga-edid-read:
- fi-skl-6600u: NOTRUN -> [SKIP][14] ([fdo#109271] / [fdo#111827]) +8
similar issues
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22321/fi-skl-6600u/igt@kms_chamel...@vga-edid-read.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-skl-6600u: NOTRUN -> [SKIP][15] ([fdo#109271]) +2 similar issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22321/fi-skl-6600u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-skl-6600u: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#533])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22321/fi-skl-6600u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
- fi-kbl-8809g: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#533])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22321/fi-kbl-8809g/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
* igt@kms_psr@cursor_plane_move:
- fi-kbl-8809g: NOTRUN -> [SKIP][18] ([fdo#109271]) +54 similar issues
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22321/fi-kbl-8809g/igt@kms_psr@cursor_plane_move.html
* igt@kms_psr@primary_page_flip:
-
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dg2: 5th Display output (rev3)
== Series Details == Series: drm/i915/dg2: 5th Display output (rev3) URL : https://patchwork.freedesktop.org/series/100151/ State : success == Summary == CI Bug Log - changes from CI_DRM_11244 -> Patchwork_22320 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/index.html Participating hosts (44 -> 42) -- Additional (1): fi-kbl-8809g Missing(3): fi-bsw-cyan bat-jsl-2 shard-tglu Known issues Here are the changes found in Patchwork_22320 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s0@smem: - fi-kbl-8809g: NOTRUN -> [DMESG-WARN][1] ([i915#4962]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/fi-kbl-8809g/igt@gem_exec_suspend@basic...@smem.html * igt@gem_exec_suspend@basic-s3@smem: - fi-bdw-5557u: [PASS][2] -> [INCOMPLETE][3] ([i915#146]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/fi-bdw-5557u/igt@gem_exec_suspend@basic...@smem.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/fi-bdw-5557u/igt@gem_exec_suspend@basic...@smem.html * igt@gem_huc_copy@huc-copy: - fi-skl-6600u: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/fi-skl-6600u/igt@gem_huc_c...@huc-copy.html - fi-kbl-8809g: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#2190]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@random-engines: - fi-kbl-8809g: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#4613]) +3 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/fi-kbl-8809g/igt@gem_lmem_swapp...@random-engines.html * igt@gem_lmem_swapping@verify-random: - fi-skl-6600u: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#4613]) +3 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/fi-skl-6600u/igt@gem_lmem_swapp...@verify-random.html * igt@i915_pm_rpm@basic-rte: - fi-kbl-8809g: NOTRUN -> [SKIP][8] ([fdo#109271]) +54 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/fi-kbl-8809g/igt@i915_pm_...@basic-rte.html * igt@i915_selftest@live@late_gt_pm: - fi-bsw-nick:[PASS][9] -> [DMESG-FAIL][10] ([i915#2927] / [i915#3428]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html * igt@kms_chamelium@hdmi-edid-read: - fi-kbl-8809g: NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) +8 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/fi-kbl-8809g/igt@kms_chamel...@hdmi-edid-read.html * igt@kms_chamelium@vga-edid-read: - fi-skl-6600u: NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +8 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/fi-skl-6600u/igt@kms_chamel...@vga-edid-read.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-skl-6600u: NOTRUN -> [SKIP][13] ([fdo#109271]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/fi-skl-6600u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html * igt@kms_frontbuffer_tracking@basic: - fi-cml-u2: [PASS][14] -> [DMESG-WARN][15] ([i915#4269]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-skl-6600u: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#533]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/fi-skl-6600u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html - fi-kbl-8809g: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#533]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/fi-kbl-8809g/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-skl-6600u: NOTRUN -> [INCOMPLETE][18] ([i915#5128]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/fi-skl-6600u/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html * igt@runner@aborted: - fi-bsw-nick:NOTRUN -> [FAIL][19] ([fdo#109271] / [i915#1436] / [i915#3428] / [i915#4312]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22320/fi-bsw-nick/igt@run...@aborted.html Possible fixes * igt@gem_exec_suspend@basic-s3@smem: - fi-skl-6600u:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/dg2: 5th Display output (rev3)
== Series Details == Series: drm/i915/dg2: 5th Display output (rev3) URL : https://patchwork.freedesktop.org/series/100151/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dg2: 5th Display output (rev3)
== Series Details == Series: drm/i915/dg2: 5th Display output (rev3) URL : https://patchwork.freedesktop.org/series/100151/ State : warning == Summary == $ dim checkpatch origin/drm-tip 8c0d7cd7a8d7 drm/i915/dg2: Enable 5th port 25ac2dc4165f drm/i915/dg2: Drop 38.4 MHz MPLLB tables 34df0ad1a986 drm/i915: Fix for PHY_MISC_TC1 offset -:46: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'port' - possible side-effects? #46: FILE: drivers/gpu/drm/i915/i915_reg.h:9361: +#define DG2_PHY_MISC(port) ((port) == PHY_E ? _MMIO(_DG2_PHY_MISC_TC1) : \ +ICL_PHY_MISC(port)) total: 0 errors, 0 warnings, 1 checks, 20 lines checked
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Kill the fake lmem support (rev2)
== Series Details ==
Series: drm/i915: Kill the fake lmem support (rev2)
URL : https://patchwork.freedesktop.org/series/100276/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11244 -> Patchwork_22319
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22319/index.html
Participating hosts (44 -> 42)
--
Additional (1): fi-kbl-8809g
Missing(3): fi-bsw-cyan shard-tglu fi-pnv-d510
Known issues
Here are the changes found in Patchwork_22319 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s0@smem:
- fi-kbl-8809g: NOTRUN -> [DMESG-WARN][1] ([i915#4962]) +1 similar
issue
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22319/fi-kbl-8809g/igt@gem_exec_suspend@basic...@smem.html
* igt@gem_exec_suspend@basic-s3:
- fi-skl-6600u: NOTRUN -> [FAIL][2] ([i915#4547])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22319/fi-skl-6600u/igt@gem_exec_susp...@basic-s3.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-8809g: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22319/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-bdw-5557u: NOTRUN -> [SKIP][4] ([fdo#109271]) +7 similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22319/fi-bdw-5557u/igt@gem_lmem_swapp...@basic.html
* igt@gem_lmem_swapping@random-engines:
- fi-kbl-8809g: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613]) +3
similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22319/fi-kbl-8809g/igt@gem_lmem_swapp...@random-engines.html
* igt@i915_pm_rpm@basic-rte:
- fi-kbl-8809g: NOTRUN -> [SKIP][6] ([fdo#109271]) +54 similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22319/fi-kbl-8809g/igt@i915_pm_...@basic-rte.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[PASS][7] -> [DMESG-WARN][8] ([i915#3303])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22319/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
* igt@kms_chamelium@hdmi-edid-read:
- fi-kbl-8809g: NOTRUN -> [SKIP][9] ([fdo#109271] / [fdo#111827]) +8
similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22319/fi-kbl-8809g/igt@kms_chamel...@hdmi-edid-read.html
* igt@kms_chamelium@vga-edid-read:
- fi-bdw-5557u: NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) +8
similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22319/fi-bdw-5557u/igt@kms_chamel...@vga-edid-read.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-8809g: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#533])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22319/fi-kbl-8809g/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-bdw-5557u: NOTRUN -> [INCOMPLETE][12] ([i915#146] / [i915#])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22319/fi-bdw-5557u/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
* igt@runner@aborted:
- fi-skl-6600u: NOTRUN -> [FAIL][13] ([i915#4312])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22319/fi-skl-6600u/igt@run...@aborted.html
Possible fixes
* igt@gem_exec_suspend@basic-s3@smem:
- {bat-rpls-2}: [INCOMPLETE][14] ([i915#4898]) -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/bat-rpls-2/igt@gem_exec_suspend@basic...@smem.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22319/bat-rpls-2/igt@gem_exec_suspend@basic...@smem.html
* igt@i915_selftest@live@hangcheck:
- {fi-jsl-1}: [INCOMPLETE][16] -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11244/fi-jsl-1/igt@i915_selftest@l...@hangcheck.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22319/fi-jsl-1/igt@i915_selftest@l...@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
[i915#1072]:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Kill the fake lmem support (rev2)
== Series Details == Series: drm/i915: Kill the fake lmem support (rev2) URL : https://patchwork.freedesktop.org/series/100276/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] [CI 2/3] drm/i915/dg2: Drop 38.4 MHz MPLLB tables
From: Matt Roper
Our early understanding of DG2 was incorrect; since the 5th display
isn't actually a Type-C output, 38.4 MHz input clocks are never used on
this platform and we can drop the corresponding MPLLB tables.
Cc: Anusha Srivatsa
Cc: José Roberto de Souza
Signed-off-by: Matt Roper
Signed-off-by: Ramalingam C
Reviewed-by: Lucas De Marchi
Reviewed-by: Uma Shankar
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_snps_phy.c | 208 +-
1 file changed, 1 insertion(+), 207 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c
b/drivers/gpu/drm/i915/display/intel_snps_phy.c
index 36a0f78a18dd..f08061c748b3 100644
--- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
@@ -250,197 +250,6 @@ static const struct intel_mpllb_state * const
dg2_dp_100_tables[] = {
NULL,
};
-/*
- * Basic DP link rates with 38.4 MHz reference clock.
- */
-
-static const struct intel_mpllb_state dg2_dp_rbr_38_4 = {
- .clock = 162000,
- .ref_control =
- REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
- .mpllb_cp =
- REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 25) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
- .mpllb_div =
- REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),
- .mpllb_div2 =
- REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 304),
- .mpllb_fracn1 =
- REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
- .mpllb_fracn2 =
- REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 49152),
-};
-
-static const struct intel_mpllb_state dg2_dp_hbr1_38_4 = {
- .clock = 27,
- .ref_control =
- REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
- .mpllb_cp =
- REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 25) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
- .mpllb_div =
- REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
- .mpllb_div2 =
- REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 248),
- .mpllb_fracn1 =
- REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
- .mpllb_fracn2 =
- REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 40960),
-};
-
-static const struct intel_mpllb_state dg2_dp_hbr2_38_4 = {
- .clock = 54,
- .ref_control =
- REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
- .mpllb_cp =
- REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 25) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
- .mpllb_div =
- REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
- .mpllb_div2 =
- REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 248),
- .mpllb_fracn1 =
- REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
- .mpllb_fracn2 =
- REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 40960),
-};
-
-static const struct intel_mpllb_state dg2_dp_hbr3_38_4 = {
- .clock = 81,
- .ref_control =
- REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
- .mpllb_cp =
- REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 26) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
-
[Intel-gfx] [CI 3/3] drm/i915/dg2: Enable 5th port
From: Matt Roper
DG2 supports a 5th display output which the hardware refers to as "TC1,"
even though it isn't a Type-C output. This behaves similarly to the TC1
on past platforms with just a couple minor differences:
* DG2's TC1 bit in SDEISR is at bit 25 rather than 24 as it is on
ICP/TGP/ADP.
* DG2 doesn't need the hpd inversion setting that we had to use on DG1
v2:
intel_ddi_init(dev_priv, PORT_TC1); [Matt]
Cc: Swathi Dhanavanthri
Cc: Lucas De Marchi
Cc: José Roberto de Souza
Signed-off-by: Matt Roper
Signed-off-by: Ramalingam C
Reviewed-by: Lucas De Marchi
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_display.c | 1 +
drivers/gpu/drm/i915/display/intel_gmbus.c | 16 ++--
drivers/gpu/drm/i915/i915_irq.c | 5 -
drivers/gpu/drm/i915/i915_reg.h | 1 +
4 files changed, 20 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index a6ebca9c7f76..ad2077d91f83 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8760,6 +8760,7 @@ static void intel_setup_outputs(struct drm_i915_private
*dev_priv)
intel_ddi_init(dev_priv, PORT_B);
intel_ddi_init(dev_priv, PORT_C);
intel_ddi_init(dev_priv, PORT_D_XELPD);
+ intel_ddi_init(dev_priv, PORT_TC1);
} else if (IS_ALDERLAKE_P(dev_priv)) {
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c
b/drivers/gpu/drm/i915/display/intel_gmbus.c
index 6ce8c10fe975..2fad03250661 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -98,11 +98,21 @@ static const struct gmbus_pin gmbus_pins_dg1[] = {
[GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
};
+static const struct gmbus_pin gmbus_pins_dg2[] = {
+ [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
+ [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
+ [GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
+ [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
+ [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
+};
+
/* pin is expected to be valid */
static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
unsigned int pin)
{
- if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG2)
+ return _pins_dg2[pin];
+ else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
return _pins_dg1[pin];
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
return _pins_icp[pin];
@@ -123,7 +133,9 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private
*dev_priv,
{
unsigned int size;
- if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG2)
+ size = ARRAY_SIZE(gmbus_pins_dg2);
+ else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
size = ARRAY_SIZE(gmbus_pins_dg1);
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
size = ARRAY_SIZE(gmbus_pins_icp);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index fdd568ba4a16..4d81063b128c 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -179,6 +179,7 @@ static const u32 hpd_sde_dg1[HPD_NUM_PINS] = {
[HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
[HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C),
[HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_D),
+ [HPD_PORT_TC1] = SDE_TC_HOTPLUG_DG2(HPD_PORT_TC1),
};
static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
@@ -4424,7 +4425,9 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
if (I915_HAS_HOTPLUG(dev_priv))
dev_priv->hotplug_funcs = _hpd_funcs;
} else {
- if (HAS_PCH_DG1(dev_priv))
+ if (HAS_PCH_DG2(dev_priv))
+ dev_priv->hotplug_funcs = _hpd_funcs;
+ else if (HAS_PCH_DG1(dev_priv))
dev_priv->hotplug_funcs = _hpd_funcs;
else if (DISPLAY_VER(dev_priv) >= 11)
dev_priv->hotplug_funcs = _hpd_funcs;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a24cb2826d9d..3d6df3975638 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6065,6 +6065,7 @@
/* south display engine interrupt: ICP/TGP */
#define SDE_GMBUS_ICP (1 << 23)
#define SDE_TC_HOTPLUG_ICP(hpd_pin)REG_BIT(24 + _HPD_PIN_TC(hpd_pin))
+#define SDE_TC_HOTPLUG_DG2(hpd_pin)REG_BIT(25 + _HPD_PIN_TC(hpd_pin)) /*
sigh */
#define SDE_DDI_HOTPLUG_ICP(hpd_pin) REG_BIT(16 + _HPD_PIN_DDI(hpd_pin))
#define SDE_DDI_HOTPLUG_MASK_ICP
[Intel-gfx] [CI 1/3] drm/i915: Fix for PHY_MISC_TC1 offset
From: Jouni Högander
Currently ICL_PHY_MISC macro is returning offset 0x64C10 for PHY_E.
The PORT_TC1 port is not yet enabled properly in the driver, but
intel_phy_snps.c is relying on intel_phy_is_snps() to filter out
unavailable phys. That function was already considering the last phy as
available. Just correct the offset of the last phy to 0x64C14 as the
rest of the support for it is coming on next commits.
Signed-off-by: Matt Roper
Signed-off-by: Jouni Högander
Signed-off-by: Ramalingam C
Reviewed-by: Uma Shankar
Reviewed-by: Lucas De Marchi
Acked-by: Ville Syrjälä
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_snps_phy.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 6 --
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c
b/drivers/gpu/drm/i915/display/intel_snps_phy.c
index 8573a458811a..36a0f78a18dd 100644
--- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
@@ -32,7 +32,7 @@ void intel_snps_phy_wait_for_calibration(struct
drm_i915_private *i915)
if (!intel_phy_is_snps(i915, phy))
continue;
- if (intel_de_wait_for_clear(i915, ICL_PHY_MISC(phy),
+ if (intel_de_wait_for_clear(i915, DG2_PHY_MISC(phy),
DG2_PHY_DP_TX_ACK_MASK, 25))
drm_err(>drm, "SNPS PHY %c failed to calibrate
after 25ms.\n",
phy);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b23ff4a19200..a24cb2826d9d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9355,8 +9355,10 @@ enum skl_power_gate {
#define _ICL_PHY_MISC_A0x64C00
#define _ICL_PHY_MISC_B0x64C04
-#define ICL_PHY_MISC(port) _MMIO_PORT(port, _ICL_PHY_MISC_A, \
-_ICL_PHY_MISC_B)
+#define _DG2_PHY_MISC_TC1 0x64C14 /* TC1="PHY E" but offset as if "PHY F"
*/
+#define ICL_PHY_MISC(port) _MMIO_PORT(port, _ICL_PHY_MISC_A,
_ICL_PHY_MISC_B)
+#define DG2_PHY_MISC(port) ((port) == PHY_E ? _MMIO(_DG2_PHY_MISC_TC1) : \
+ICL_PHY_MISC(port))
#define ICL_PHY_MISC_MUX_DDID (1 << 28)
#define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23)
#define DG2_PHY_DP_TX_ACK_MASKREG_GENMASK(23, 20)
--
2.35.1
[Intel-gfx] ✓ Fi.CI.BAT: success for Add driver for GSC controller (rev9)
== Series Details == Series: Add driver for GSC controller (rev9) URL : https://patchwork.freedesktop.org/series/98066/ State : success == Summary == CI Bug Log - changes from CI_DRM_11243 -> Patchwork_22318 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22318/index.html Participating hosts (43 -> 41) -- Additional (1): fi-snb-2600 Missing(3): fi-bsw-cyan bat-jsl-2 shard-tglu Known issues Here are the changes found in Patchwork_22318 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@cs-gfx: - fi-hsw-4770:NOTRUN -> [SKIP][1] ([fdo#109271] / [fdo#109315]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22318/fi-hsw-4770/igt@amdgpu/amd_ba...@cs-gfx.html - fi-rkl-guc: NOTRUN -> [SKIP][2] ([fdo#109315]) +17 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22318/fi-rkl-guc/igt@amdgpu/amd_ba...@cs-gfx.html * igt@amdgpu/amd_basic@semaphore: - fi-bsw-nick:NOTRUN -> [SKIP][3] ([fdo#109271]) +17 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22318/fi-bsw-nick/igt@amdgpu/amd_ba...@semaphore.html * igt@gem_huc_copy@huc-copy: - fi-skl-6600u: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22318/fi-skl-6600u/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@verify-random: - fi-skl-6600u: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613]) +3 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22318/fi-skl-6600u/igt@gem_lmem_swapp...@verify-random.html * igt@i915_selftest@live@hangcheck: - bat-dg1-6: [PASS][6] -> [DMESG-FAIL][7] ([i915#4494] / [i915#4957]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11243/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22318/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html * igt@i915_selftest@live@requests: - fi-blb-e6850: [PASS][8] -> [DMESG-FAIL][9] ([i915#5026]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11243/fi-blb-e6850/igt@i915_selftest@l...@requests.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22318/fi-blb-e6850/igt@i915_selftest@l...@requests.html * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: - fi-snb-2600:NOTRUN -> [SKIP][10] ([fdo#109271]) +41 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22318/fi-snb-2600/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html * igt@kms_chamelium@hdmi-crc-fast: - fi-snb-2600:NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) +8 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22318/fi-snb-2600/igt@kms_chamel...@hdmi-crc-fast.html * igt@kms_chamelium@vga-edid-read: - fi-skl-6600u: NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +8 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22318/fi-skl-6600u/igt@kms_chamel...@vga-edid-read.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-skl-6600u: NOTRUN -> [SKIP][13] ([fdo#109271]) +2 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22318/fi-skl-6600u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-skl-6600u: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#533]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22318/fi-skl-6600u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html * igt@kms_psr@primary_page_flip: - fi-skl-6600u: NOTRUN -> [INCOMPLETE][15] ([i915#4838]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22318/fi-skl-6600u/igt@kms_psr@primary_page_flip.html * igt@runner@aborted: - fi-bdw-5557u: NOTRUN -> [FAIL][16] ([i915#2426] / [i915#4312]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22318/fi-bdw-5557u/igt@run...@aborted.html - fi-blb-e6850: NOTRUN -> [FAIL][17] ([fdo#109271] / [i915#2403] / [i915#2426] / [i915#4312]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22318/fi-blb-e6850/igt@run...@aborted.html Possible fixes * igt@gem_flink_basic@bad-flink: - fi-skl-6600u: [INCOMPLETE][18] ([i915#4547]) -> [PASS][19] [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11243/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22318/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html * igt@i915_pm_rpm@module-reload: - fi-kbl-guc: [SKIP][20] ([fdo#109271]) -> [PASS][21] [20]:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add driver for GSC controller (rev9)
== Series Details == Series: Add driver for GSC controller (rev9) URL : https://patchwork.freedesktop.org/series/98066/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add driver for GSC controller (rev9)
== Series Details == Series: Add driver for GSC controller (rev9) URL : https://patchwork.freedesktop.org/series/98066/ State : warning == Summary == $ dim checkpatch origin/drm-tip a7e6a826a5df drm/i915/gsc: add gsc as a mei auxiliary device -:63: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #63: new file mode 100644 -:457: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #457: FILE: drivers/gpu/drm/i915/i915_drv.h:1336: +#define HAS_HECI_GSC(dev_priv) (HAS_HECI_PXP(dev_priv) || HAS_HECI_GSCFI(dev_priv)) total: 0 errors, 1 warnings, 1 checks, 418 lines checked 85bba7a3f97b mei: add support for graphics system controller (gsc) devices -:56: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #56: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 289 lines checked 0769e0dc0e87 mei: gsc: setup char driver alive in spite of firmware handshake failure a2c4c46bcaa5 mei: gsc: add runtime pm handlers e6a2fd91d60c mei: gsc: retrieve the firmware version
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Disconnect PHYs left connected by BIOS on disabled ports
== Series Details ==
Series: drm/i915: Disconnect PHYs left connected by BIOS on disabled ports
URL : https://patchwork.freedesktop.org/series/100336/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11243 -> Patchwork_22317
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22317/index.html
Participating hosts (43 -> 43)
--
Additional (2): fi-snb-2600 fi-pnv-d510
Missing(2): fi-bsw-cyan shard-tglu
Known issues
Here are the changes found in Patchwork_22317 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@cs-multi-fence:
- fi-bsw-nick:NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22317/fi-bsw-nick/igt@amdgpu/amd_ba...@cs-multi-fence.html
* igt@amdgpu/amd_basic@semaphore:
- fi-hsw-4770:NOTRUN -> [SKIP][2] ([fdo#109271] / [fdo#109315]) +17
similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22317/fi-hsw-4770/igt@amdgpu/amd_ba...@semaphore.html
* igt@amdgpu/amd_cs_nop@fork-compute0:
- fi-rkl-guc: NOTRUN -> [SKIP][3] ([fdo#109315]) +17 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22317/fi-rkl-guc/igt@amdgpu/amd_cs_...@fork-compute0.html
* igt@gem_exec_suspend@basic-s3:
- fi-skl-6600u: NOTRUN -> [FAIL][4] ([i915#4547])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22317/fi-skl-6600u/igt@gem_exec_susp...@basic-s3.html
* igt@gem_huc_copy@huc-copy:
- fi-pnv-d510:NOTRUN -> [SKIP][5] ([fdo#109271]) +57 similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22317/fi-pnv-d510/igt@gem_huc_c...@huc-copy.html
* igt@i915_selftest@live@gt_pm:
- fi-tgl-1115g4: [PASS][6] -> [DMESG-FAIL][7] ([i915#3987])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11243/fi-tgl-1115g4/igt@i915_selftest@live@gt_pm.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22317/fi-tgl-1115g4/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: [PASS][8] -> [DMESG-FAIL][9] ([i915#4494] /
[i915#4957])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11243/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22317/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- fi-snb-2600:NOTRUN -> [SKIP][10] ([fdo#109271]) +41 similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22317/fi-snb-2600/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-snb-2600:NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) +8
similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22317/fi-snb-2600/igt@kms_chamel...@hdmi-crc-fast.html
Possible fixes
* igt@gem_exec_suspend@basic-s3@smem:
- {fi-rkl-11600}: [INCOMPLETE][12] ([i915#5127]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11243/fi-rkl-11600/igt@gem_exec_suspend@basic...@smem.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22317/fi-rkl-11600/igt@gem_exec_suspend@basic...@smem.html
* igt@i915_pm_rpm@module-reload:
- fi-kbl-guc: [SKIP][14] ([fdo#109271]) -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11243/fi-kbl-guc/igt@i915_pm_...@module-reload.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22317/fi-kbl-guc/igt@i915_pm_...@module-reload.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-skl-guc: [DMESG-FAIL][16] ([i915#2291] / [i915#541]) ->
[PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11243/fi-skl-guc/igt@i915_selftest@live@gt_heartbeat.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22317/fi-skl-guc/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[INCOMPLETE][18] ([i915#3303]) -> [PASS][19]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11243/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22317/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@late_gt_pm:
- fi-bsw-nick:[DMESG-FAIL][20] ([i915#2927] / [i915#3428]) ->
[PASS][21]
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11243/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22317/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html
* igt@i915_selftest@live@workarounds:
- fi-rkl-guc: [INCOMPLETE][22] -> [PASS][23]
[22]:
Re: [Intel-gfx] [RFC 2/2] drm/i915/migrate: Evict and restore the ccs data
On Mon, Feb 07, 2022 at 03:07:43PM +0530, Ramalingam C wrote:
When we are swapping out the local memory obj on flat-ccs capable platform,
we need to capture the ccs data too along with main meory and we need to
restore it when we are swapping in the content.
Extracting and restoring the CCS data is done through a special cmd called
XY_CTRL_SURF_COPY_BLT
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/gt/intel_migrate.c | 283 +---
1 file changed, 155 insertions(+), 128 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c
b/drivers/gpu/drm/i915/gt/intel_migrate.c
index 5bdab0b3c735..e60ae6ff1847 100644
--- a/drivers/gpu/drm/i915/gt/intel_migrate.c
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
@@ -449,14 +449,146 @@ static bool wa_1209644611_applies(int ver, u32 size)
return height % 4 == 3 && height <= 8;
}
+/**
+ * DOC: Flat-CCS - Memory compression for Local memory
+ *
+ * On Xe-HP and later devices, we use dedicated compression control state (CCS)
+ * stored in local memory for each surface, to support the 3D and media
+ * compression formats.
+ *
+ * The memory required for the CCS of the entire local memory is 1/256 of the
+ * local memory size. So before the kernel boot, the required memory is
reserved
+ * for the CCS data and a secure register will be programmed with the CCS base
+ * address.
+ *
+ * Flat CCS data needs to be cleared when a lmem object is allocated.
+ * And CCS data can be copied in and out of CCS region through
+ * XY_CTRL_SURF_COPY_BLT. CPU can't access the CCS data directly.
+ *
+ * When we exaust the lmem, if the object's placements support smem, then we
can
+ * directly decompress the compressed lmem object into smem and start using it
+ * from smem itself.
+ *
+ * But when we need to swapout the compressed lmem object into a smem region
+ * though objects' placement doesn't support smem, then we copy the lmem
content
+ * as it is into smem region along with ccs data (using XY_CTRL_SURF_COPY_BLT).
+ * When the object is referred, lmem content will be swaped in along with
+ * restoration of the CCS data (using XY_CTRL_SURF_COPY_BLT) at corresponding
+ * location.
+ *
+ *
+ * Flat-CCS Modifiers for different compression formats
+ *
+ *
+ * I915_FORMAT_MOD_F_TILED_DG2_RC_CCS - used to indicate the buffers of Flat
CCS
+ * render compression formats. Though the general layout is same as
+ * I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, new hashing/compression algorithm is
+ * used. Render compression uses 128 byte compression blocks
+ *
+ * I915_FORMAT_MOD_F_TILED_DG2_MC_CCS -used to indicate the buffers of Flat CCS
+ * media compression formats. Though the general layout is same as
+ * I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS, new hashing/compression algorithm is
+ * used. Media compression uses 256 byte compression blocks.
+ *
+ * I915_FORMAT_MOD_F_TILED_DG2_RC_CCS_CC - used to indicate the buffers of Flat
+ * CCS clear color render compression formats. Unified compression format for
+ * clear color render compression. The genral layout is a tiled layout using
+ * 4Kb tiles i.e Tile4 layout.
+ */
+
+static inline u32 *i915_flush_dw(u32 *cmd, u64 dst, u32 flags)
+{
+ /* Mask the 3 LSB to use the PPGTT address space */
+ *cmd++ = MI_FLUSH_DW | flags;
+ *cmd++ = lower_32_bits(dst);
+ *cmd++ = upper_32_bits(dst);
+
+ return cmd;
+}
+
+static u32 calc_ctrl_surf_instr_size(struct drm_i915_private *i915, int size)
+{
+ u32 num_cmds, num_blks, total_size;
+
+ if (!GET_CCS_SIZE(i915, size))
+ return 0;
+
+ /*
+* XY_CTRL_SURF_COPY_BLT transfers CCS in 256 byte
+* blocks. one XY_CTRL_SURF_COPY_BLT command can
+* trnasfer upto 1024 blocks.
+*/
+ num_blks = GET_CCS_SIZE(i915, size);
+ num_cmds = (num_blks + (NUM_CCS_BLKS_PER_XFER - 1)) >> 10;
+ total_size = (XY_CTRL_SURF_INSTR_SIZE) * num_cmds;
+
+ /*
+* We need to add a flush before and after
+* XY_CTRL_SURF_COPY_BLT
+*/
+ total_size += 2 * MI_FLUSH_DW_SIZE;
+ return total_size;
+}
+
+static u32 *_i915_ctrl_surf_copy_blt(u32 *cmd, u64 src_addr, u64 dst_addr,
+u8 src_mem_access, u8 dst_mem_access,
+int src_mocs, int dst_mocs,
+u16 num_ccs_blocks)
+{
+ int i = num_ccs_blocks;
+
+ /*
+* The XY_CTRL_SURF_COPY_BLT instruction is used to copy the CCS
+* data in and out of the CCS region.
+*
+* We can copy at most 1024 blocks of 256 bytes using one
+* XY_CTRL_SURF_COPY_BLT instruction.
+*
+* In case we need to copy more than 1024 blocks, we need to add
+* another instruction to the same batch buffer.
+*
+* 1024 blocks of 256 bytes of CCS represent a total 256KB of CCS.
+*
+* 256 KB of CCS
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/dg2: add Wa_14014947963 (rev2)
On Fri, Feb 11, 2022 at 06:57:43AM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/dg2: add Wa_14014947963 (rev2)
> URL : https://patchwork.freedesktop.org/series/9/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_11215_full -> Patchwork_22252_full
>
>
> Summary
> ---
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_22252_full absolutely need to
> be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_22252_full, please notify your bug team to allow
> them
> to document this new failure mode, which will reduce false positives in CI.
>
>
>
> Participating hosts (11 -> 12)
> --
>
> Additional (1): shard-rkl
>
> Possible new issues
> ---
>
> Here are the unknown changes that may have been introduced in
> Patchwork_22252_full:
>
> ### IGT changes ###
>
> Possible regressions
>
> * igt@gem_ctx_persistence@many-contexts:
> - shard-iclb: [PASS][1] -> [INCOMPLETE][2]
>[1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11215/shard-iclb5/igt@gem_ctx_persiste...@many-contexts.html
>[2]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22252/shard-iclb7/igt@gem_ctx_persiste...@many-contexts.html
<4> [101.282625] WARNING: CPU: 5 PID: 175 at
drivers/gpu/drm/i915/gt/intel_execlists_submission.c:1908
process_csb+0x6d2/0x740 [i915]
which is GEM_WARN_ON(!*execlists->pending). It looks like we used to
have https://gitlab.freedesktop.org/drm/intel/-/issues/3057 for that
warning. I also see several other fdo bugs where the warning is
sporadically tripped by other tests. So it doesn't appear to be caused
by this patch.
>
> * igt@kms_flip@flip-vs-suspend@b-vga1:
> - shard-snb: [PASS][3] -> [DMESG-WARN][4]
>[3]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11215/shard-snb4/igt@kms_flip@flip-vs-susp...@b-vga1.html
>[4]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22252/shard-snb6/igt@kms_flip@flip-vs-susp...@b-vga1.html
<4> [58.614078] unchecked MSR access error: RDMSR from 0x1b0 at rIP:
0x8103a69f (intel_epb_restore+0xf/0xa0)
This isn't coming from the graphics driver. It's also seen on some of
our other suspend/resume tests. E.g.,
https://gitlab.freedesktop.org/drm/intel/-/issues/5090
Not caused by this test.
Matt
>
>
> Suppressed
>
> The following results come from untrusted machines, tests, or statuses.
> They do not affect the overall result.
>
> * igt@gem_exec_whisper@basic-contexts-priority-all:
> - {shard-rkl}:NOTRUN -> [FAIL][5]
>[5]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22252/shard-rkl-5/igt@gem_exec_whis...@basic-contexts-priority-all.html
>
> * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt:
> - {shard-rkl}:NOTRUN -> [INCOMPLETE][6]
>[6]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22252/shard-rkl-5/igt@kms_frontbuffer_track...@psr-1p-primscrn-spr-indfb-draw-blt.html
>
>
> Known issues
>
>
> Here are the changes found in Patchwork_22252_full that come from known
> issues:
>
> ### IGT changes ###
>
> Issues hit
>
> * igt@feature_discovery@chamelium:
> - shard-iclb: NOTRUN -> [SKIP][7] ([fdo#111827])
>[7]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22252/shard-iclb5/igt@feature_discov...@chamelium.html
>
> * igt@gem_ctx_isolation@preservation-s3@vcs0:
> - shard-kbl: [PASS][8] -> [DMESG-WARN][9] ([i915#180]) +1
> similar issue
>[8]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11215/shard-kbl6/igt@gem_ctx_isolation@preservation...@vcs0.html
>[9]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22252/shard-kbl1/igt@gem_ctx_isolation@preservation...@vcs0.html
>
> * igt@gem_exec_capture@pi@bcs0:
> - shard-skl: NOTRUN -> [INCOMPLETE][10] ([i915#4547])
>[10]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22252/shard-skl4/igt@gem_exec_capture@p...@bcs0.html
>
> * igt@gem_exec_fair@basic-deadline:
> - shard-skl: NOTRUN -> [FAIL][11] ([i915#2846])
>[11]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22252/shard-skl3/igt@gem_exec_f...@basic-deadline.html
>
> * igt@gem_exec_fair@basic-none-share@rcs0:
> - shard-kbl: [PASS][12] -> [FAIL][13] ([i915#2842]) +2 similar
> issues
>[12]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11215/shard-kbl4/igt@gem_exec_fair@basic-none-sh...@rcs0.html
>[13]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22252/shard-kbl6/igt@gem_exec_fair@basic-none-sh...@rcs0.html
>
> * igt@gem_exec_fair@basic-none@vcs1:
> - shard-iclb: NOTRUN -> [FAIL][14] ([i915#2842])
>[14]:
>
Re: [Intel-gfx] [PATCH V3] drm/i915/dg2: add Wa_14014947963
On Thu, Feb 10, 2022 at 09:23:33PM -0800, clinton.a.tay...@intel.com wrote: > From: Clint Taylor > > BSPEC: 46123 > v2: Address review feedback [MattR] > v3: move register definition to gt_regs [MattR] > Cc: Matt Roper > Signed-off-by: Clint Taylor Reviewed-by: Matt Roper although see below for a couple style tweaks we should make while applying this. Also, I think we'll need to wait for the maintainers to do a backmerge/crossmerge in drm-intel-gt-next (which I think they're planning to do soon) before applying this since that branch is still missing all the recent register rework. > --- > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++ > drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 + > 2 files changed, 8 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > index a6f0220c2e9f..5c8c3bc65acc 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > @@ -124,6 +124,9 @@ > #define ECOCHK_PPGTT_WT_HSW(0x2 << 3) > #define ECOCHK_PPGTT_WB_HSW(0x3 << 3) > > +#define VF_PREEMPTION_MMIO(0x83a4) > +#define PREEMPTION_VERTEX_COUNT REG_GENMASK(15, 0) While applying we'll hit some merge conflicts due to the cleanup of the file that just landed; while resolving the conflict, we should add an extra space between 'define' and 'PREEMPTION_VERTEX_COUNT' and tab over farther before the REG_GENMASK to match the style of the rest of the file. > + > #define GEN8_RC6_CTX_INFO_MMIO(0x8504) > > #define GAC_ECO_BITS _MMIO(0x14090) > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c > b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index b146a393cd79..9416b1434c64 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -689,6 +689,11 @@ static void dg2_ctx_workarounds_init(struct > intel_engine_cs *engine, > IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) > wa_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7, >DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA); > + > + /* wa_14014947963: dg2_g10 [B0..NONE] dg2_g11 dg2_g12 */ We can probably just simplify the comment down to "Wa_14014947963:dg2" since that's what we've been doing with most of the other DG2 workarounds lately. Including the steppings in the comment isn't terribly useful since the next line shows them pretty clearly (and we run the risk of the comment becoming stale if we update the code later). We can tweak that while applying the patch as well. Matt > + if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_B0, STEP_FOREVER) || > + IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) > + wa_masked_field_set(wal, VF_PREEMPTION, > PREEMPTION_VERTEX_COUNT, 0x4000); > } > > static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine, > -- > 2.34.1 > -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795
Re: [Intel-gfx] [PATCH v5 5/7] drm/i915/gt: Create per-tile RC6 sysfs interface
Hi Andi, I love your patch! Yet something to improve: [auto build test ERROR on drm-tip/drm-tip] [cannot apply to drm-intel/for-linux-next drm-exynos/exynos-drm-next drm/drm-next tegra-drm/drm/tegra/for-next airlied/drm-next v5.17-rc4 next-20220217] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Andi-Shyti/Introduce-multitile-support/20220217-224547 base: git://anongit.freedesktop.org/drm/drm-tip drm-tip config: i386-randconfig-a004 (https://download.01.org/0day-ci/archive/20220218/202202180713.xhysmqw4-...@intel.com/config) compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project d271fc04d5b97b12e6b797c6067d3c96a8d7470e) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://github.com/0day-ci/linux/commit/b358d991c154dc27fa4ef2fc99f8819f4f3e97e7 git remote add linux-review https://github.com/0day-ci/linux git fetch --no-tags linux-review Andi-Shyti/Introduce-multitile-support/20220217-224547 git checkout b358d991c154dc27fa4ef2fc99f8819f4f3e97e7 # save the config file to linux build tree mkdir build_dir COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=i386 SHELL=/bin/bash If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot All errors (new ones prefixed by >>): >> ld.lld: error: undefined symbol: __divdi3 >>> referenced by intel_gt_sysfs_pm.c:35 (drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:35) >>> gpu/drm/i915/gt/intel_gt_sysfs_pm.o:(rc6_residency_ms_show) in archive drivers/built-in.a >>> referenced by intel_gt_sysfs_pm.c:35 (drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:35) >>> gpu/drm/i915/gt/intel_gt_sysfs_pm.o:(rc6p_residency_ms_show) in archive drivers/built-in.a >>> referenced by intel_gt_sysfs_pm.c:35 (drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:35) >>> gpu/drm/i915/gt/intel_gt_sysfs_pm.o:(rc6pp_residency_ms_show) in archive drivers/built-in.a >>> referenced 1 more times --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org
[Intel-gfx] [PATCH 6/8] drm/i915/guc: Rename desc_idx to ctx_id
From: John Harrison
The LRC descriptor pool is going away. So, stop naming context ids as
descriptor pool indecies.
While at it, add a bunch of missing line feeds to some error messages.
Signed-off-by: John Harrison
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 56 +--
1 file changed, 28 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index aa74ec74194a..b70b1ff46418 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -2245,7 +2245,7 @@ static void prepare_context_registration_info(struct
intel_context *ce)
{
struct intel_engine_cs *engine = ce->engine;
struct intel_guc *guc = >gt->uc.guc;
- u32 desc_idx = ce->guc_id.id;
+ u32 ctx_id = ce->guc_id.id;
struct guc_lrc_desc *desc;
struct intel_context *child;
@@ -2258,10 +2258,10 @@ static void prepare_context_registration_info(struct
intel_context *ce)
GEM_BUG_ON(i915_gem_object_is_lmem(guc->ct.vma->obj) !=
i915_gem_object_is_lmem(ce->ring->vma->obj));
- clr_ctx_id_mapping(guc, desc_idx);
- set_ctx_id_mapping(guc, desc_idx, ce);
+ clr_ctx_id_mapping(guc, ctx_id);
+ set_ctx_id_mapping(guc, ctx_id, ce);
- desc = __get_lrc_desc(guc, desc_idx);
+ desc = __get_lrc_desc(guc, ctx_id);
desc->engine_class = engine_class_to_guc_class(engine->class);
desc->engine_submit_mask = engine->logical_mask;
desc->hw_context_desc = ce->lrc.lrca;
@@ -2313,17 +2313,17 @@ static int try_context_registration(struct
intel_context *ce, bool loop)
struct intel_runtime_pm *runtime_pm = engine->uncore->rpm;
struct intel_guc *guc = >gt->uc.guc;
intel_wakeref_t wakeref;
- u32 desc_idx = ce->guc_id.id;
+ u32 ctx_id = ce->guc_id.id;
bool context_registered;
int ret = 0;
GEM_BUG_ON(!sched_state_is_init(ce));
- context_registered = ctx_id_mapped(guc, desc_idx);
+ context_registered = ctx_id_mapped(guc, ctx_id);
if (context_registered)
- clr_ctx_id_mapping(guc, desc_idx);
- set_ctx_id_mapping(guc, desc_idx, ce);
+ clr_ctx_id_mapping(guc, ctx_id);
+ set_ctx_id_mapping(guc, ctx_id, ce);
/*
* The context_lookup xarray is used to determine if the hardware
@@ -2349,7 +2349,7 @@ static int try_context_registration(struct intel_context
*ce, bool loop)
}
spin_unlock_irqrestore(>guc_state.lock, flags);
if (unlikely(disabled)) {
- clr_ctx_id_mapping(guc, desc_idx);
+ clr_ctx_id_mapping(guc, ctx_id);
return 0; /* Will get registered later */
}
@@ -2365,9 +2365,9 @@ static int try_context_registration(struct intel_context
*ce, bool loop)
with_intel_runtime_pm(runtime_pm, wakeref)
ret = register_context(ce, loop);
if (unlikely(ret == -EBUSY)) {
- clr_ctx_id_mapping(guc, desc_idx);
+ clr_ctx_id_mapping(guc, ctx_id);
} else if (unlikely(ret == -ENODEV)) {
- clr_ctx_id_mapping(guc, desc_idx);
+ clr_ctx_id_mapping(guc, ctx_id);
ret = 0;/* Will get registered later */
}
}
@@ -3864,26 +3864,26 @@ void intel_guc_submission_init_early(struct intel_guc
*guc)
}
static inline struct intel_context *
-g2h_context_lookup(struct intel_guc *guc, u32 desc_idx)
+g2h_context_lookup(struct intel_guc *guc, u32 ctx_id)
{
struct intel_context *ce;
- if (unlikely(desc_idx >= GUC_MAX_CONTEXT_ID)) {
+ if (unlikely(ctx_id >= GUC_MAX_CONTEXT_ID)) {
drm_err(_to_gt(guc)->i915->drm,
- "Invalid desc_idx %u", desc_idx);
+ "Invalid ctx_id %u\n", ctx_id);
return NULL;
}
- ce = __get_context(guc, desc_idx);
+ ce = __get_context(guc, ctx_id);
if (unlikely(!ce)) {
drm_err(_to_gt(guc)->i915->drm,
- "Context is NULL, desc_idx %u", desc_idx);
+ "Context is NULL, ctx_id %u\n", ctx_id);
return NULL;
}
if (unlikely(intel_context_is_child(ce))) {
drm_err(_to_gt(guc)->i915->drm,
- "Context is child, desc_idx %u", desc_idx);
+ "Context is child, ctx_id %u\n", ctx_id);
return NULL;
}
@@ -3895,14 +3895,14 @@ int intel_guc_deregister_done_process_msg(struct
intel_guc *guc,
u32 len)
{
struct intel_context *ce;
- u32 desc_idx = msg[0];
+ u32 ctx_id = msg[0];
[Intel-gfx] [PATCH 2/8] drm/i915/guc: Add an explicit 'submission_initialized' flag
From: John Harrison
The LRC descriptor pool is going away. So, stop using it as a check
for whether submission has been initialised or not.
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 2 ++
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 8 +---
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 9d779de16613..568eb6352ef0 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -137,6 +137,8 @@ struct intel_guc {
bool submission_supported;
/** @submission_selected: tracks whether the user enabled GuC
submission */
bool submission_selected;
+ /** @submission_initialized: tracks whether GuC submission has been
initialised */
+ bool submission_initialized;
/**
* @rc_supported: tracks whether we support GuC rc on the current
platform
*/
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 7fb889e14995..11bf56b5a266 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -511,7 +511,7 @@ static void guc_lrc_desc_pool_destroy(struct intel_guc *guc)
static inline bool guc_submission_initialized(struct intel_guc *guc)
{
- return !!guc->lrc_desc_pool_vaddr;
+ return guc->submission_initialized;
}
static inline void _reset_lrc_desc(struct intel_guc *guc, u32 id)
@@ -1813,7 +1813,7 @@ int intel_guc_submission_init(struct intel_guc *guc)
struct intel_gt *gt = guc_to_gt(guc);
int ret;
- if (guc->lrc_desc_pool)
+ if (guc->submission_initialized)
return 0;
ret = guc_lrc_desc_pool_create(guc);
@@ -1845,19 +1845,21 @@ int intel_guc_submission_init(struct intel_guc *guc)
INIT_DELAYED_WORK(>timestamp.work, guc_timestamp_ping);
guc->timestamp.ping_delay = (POLL_TIME_CLKS / gt->clock_frequency + 1)
* HZ;
guc->timestamp.shift = gpm_timestamp_shift(gt);
+ guc->submission_initialized = true;
return 0;
}
void intel_guc_submission_fini(struct intel_guc *guc)
{
- if (!guc->lrc_desc_pool)
+ if (!guc->submission_initialized)
return;
guc_flush_destroyed_contexts(guc);
guc_lrc_desc_pool_destroy(guc);
i915_sched_engine_put(guc->sched_engine);
bitmap_free(guc->submission_state.guc_ids_bitmap);
+ guc->submission_initialized = false;
}
static inline void queue_request(struct i915_sched_engine *sched_engine,
--
2.25.1
[Intel-gfx] [PATCH 8/8] drm/i915/guc: Fix potential invalid pointer dereferences when decoding G2Hs
From: John Harrison
Some G2H handlers were reading the context id field from the payload
before checking the payload met the minimum length required.
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index b70b1ff46418..ea17dca68674 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -3895,12 +3895,13 @@ int intel_guc_deregister_done_process_msg(struct
intel_guc *guc,
u32 len)
{
struct intel_context *ce;
- u32 ctx_id = msg[0];
+ u32 ctx_id;
if (unlikely(len < 1)) {
drm_err(_to_gt(guc)->i915->drm, "Invalid length %u\n", len);
return -EPROTO;
}
+ ctx_id = msg[0];
ce = g2h_context_lookup(guc, ctx_id);
if (unlikely(!ce))
@@ -3946,12 +3947,13 @@ int intel_guc_sched_done_process_msg(struct intel_guc
*guc,
{
struct intel_context *ce;
unsigned long flags;
- u32 ctx_id = msg[0];
+ u32 ctx_id;
if (unlikely(len < 2)) {
drm_err(_to_gt(guc)->i915->drm, "Invalid length %u\n", len);
return -EPROTO;
}
+ ctx_id = msg[0];
ce = g2h_context_lookup(guc, ctx_id);
if (unlikely(!ce))
--
2.25.1
[Intel-gfx] [PATCH 3/8] drm/i915/guc: Better name for context id limit
From: John Harrison
The LRC descriptor pool is going away. So, stop using it as the limit
for how many context ids are available.
While at it, also update a kzalloc(sizeof()*count) to be a
kcalloc(count,size).
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/intel_context.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 4 ++--
.../gpu/drm/i915/gt/uc/intel_guc_submission.c| 16
drivers/gpu/drm/i915/gt/uc/selftest_guc.c| 2 +-
4 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c
b/drivers/gpu/drm/i915/gt/intel_context.c
index 5d0ec7c49b6a..d87145b8fca0 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -400,7 +400,7 @@ intel_context_init(struct intel_context *ce, struct
intel_engine_cs *engine)
INIT_LIST_HEAD(>guc_state.fences);
INIT_LIST_HEAD(>guc_state.requests);
- ce->guc_id.id = GUC_INVALID_LRC_ID;
+ ce->guc_id.id = GUC_INVALID_CONTEXT_ID;
INIT_LIST_HEAD(>guc_id.link);
INIT_LIST_HEAD(>destroyed_link);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
index 6a4612a852e2..11099f0320ce 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
@@ -32,8 +32,8 @@
#define GUC_CLIENT_PRIORITY_NORMAL 3
#define GUC_CLIENT_PRIORITY_NUM4
-#define GUC_MAX_LRC_DESCRIPTORS65535
-#defineGUC_INVALID_LRC_ID GUC_MAX_LRC_DESCRIPTORS
+#define GUC_MAX_CONTEXT_ID 65535
+#defineGUC_INVALID_CONTEXT_ID GUC_MAX_CONTEXT_ID
#define GUC_RENDER_ENGINE 0
#define GUC_VIDEO_ENGINE 1
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 11bf56b5a266..ad784e8068c7 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -354,12 +354,12 @@ request_to_scheduling_context(struct i915_request *rq)
static inline bool context_guc_id_invalid(struct intel_context *ce)
{
- return ce->guc_id.id == GUC_INVALID_LRC_ID;
+ return ce->guc_id.id == GUC_INVALID_CONTEXT_ID;
}
static inline void set_context_guc_id_invalid(struct intel_context *ce)
{
- ce->guc_id.id = GUC_INVALID_LRC_ID;
+ ce->guc_id.id = GUC_INVALID_CONTEXT_ID;
}
static inline struct intel_guc *ce_to_guc(struct intel_context *ce)
@@ -474,7 +474,7 @@ static struct guc_lrc_desc *__get_lrc_desc(struct intel_guc
*guc, u32 index)
{
struct guc_lrc_desc *base = guc->lrc_desc_pool_vaddr;
- GEM_BUG_ON(index >= GUC_MAX_LRC_DESCRIPTORS);
+ GEM_BUG_ON(index >= GUC_MAX_CONTEXT_ID);
return [index];
}
@@ -483,7 +483,7 @@ static inline struct intel_context *__get_context(struct
intel_guc *guc, u32 id)
{
struct intel_context *ce = xa_load(>context_lookup, id);
- GEM_BUG_ON(id >= GUC_MAX_LRC_DESCRIPTORS);
+ GEM_BUG_ON(id >= GUC_MAX_CONTEXT_ID);
return ce;
}
@@ -494,7 +494,7 @@ static int guc_lrc_desc_pool_create(struct intel_guc *guc)
int ret;
size = PAGE_ALIGN(sizeof(struct guc_lrc_desc) *
- GUC_MAX_LRC_DESCRIPTORS);
+ GUC_MAX_CONTEXT_ID);
ret = intel_guc_allocate_and_map_vma(guc, size, >lrc_desc_pool,
(void
**)>lrc_desc_pool_vaddr);
if (ret)
@@ -2441,7 +2441,7 @@ static void __guc_context_sched_disable(struct intel_guc
*guc,
GUC_CONTEXT_DISABLE
};
- GEM_BUG_ON(guc_id == GUC_INVALID_LRC_ID);
+ GEM_BUG_ON(guc_id == GUC_INVALID_CONTEXT_ID);
GEM_BUG_ON(intel_context_is_child(ce));
trace_intel_context_sched_disable(ce);
@@ -3840,7 +3840,7 @@ static bool __guc_submission_selected(struct intel_guc
*guc)
void intel_guc_submission_init_early(struct intel_guc *guc)
{
- guc->submission_state.num_guc_ids = GUC_MAX_LRC_DESCRIPTORS;
+ guc->submission_state.num_guc_ids = GUC_MAX_CONTEXT_ID;
guc->submission_supported = __guc_submission_supported(guc);
guc->submission_selected = __guc_submission_selected(guc);
}
@@ -3850,7 +3850,7 @@ g2h_context_lookup(struct intel_guc *guc, u32 desc_idx)
{
struct intel_context *ce;
- if (unlikely(desc_idx >= GUC_MAX_LRC_DESCRIPTORS)) {
+ if (unlikely(desc_idx >= GUC_MAX_CONTEXT_ID)) {
drm_err(_to_gt(guc)->i915->drm,
"Invalid desc_idx %u", desc_idx);
return NULL;
diff --git a/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
b/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
index a115894d5896..1df71d0796ae 100644
--- a/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
@@ -148,7 +148,7 @@ static int
[Intel-gfx] [PATCH 7/8] drm/i915/guc: Drop obsolete H2G definitions
From: John Harrison
The CTB registration process changed significantly a while back using
a single KLV based H2G. So drop the original and now obsolete H2G
definitions.
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
index 7afdadc7656f..e77f955435ce 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
@@ -131,8 +131,6 @@ enum intel_guc_action {
INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
INTEL_GUC_ACTION_REGISTER_CONTEXT = 0x4502,
INTEL_GUC_ACTION_DEREGISTER_CONTEXT = 0x4503,
- INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER = 0x4505,
- INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER = 0x4506,
INTEL_GUC_ACTION_DEREGISTER_CONTEXT_DONE = 0x4600,
INTEL_GUC_ACTION_REGISTER_CONTEXT_MULTI_LRC = 0x4601,
INTEL_GUC_ACTION_CLIENT_SOFT_RESET = 0x5507,
--
2.25.1
[Intel-gfx] [PATCH 1/8] drm/i915/guc: Do not conflate lrc_desc with GuC id for registration
From: John Harrison
The LRC descriptor pool is going away. So, stop using it as a check for
context registration, use the GuC id instead (being the thing that
actually gets registered with the GuC).
Also, rename the set/clear/query helper functions for context id
mappings to better reflect their purpose and to differentiate from
other registration related helper functions.
Signed-off-by: John Harrison
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 69 ++-
1 file changed, 38 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index b3a429a92c0d..7fb889e14995 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -514,31 +514,20 @@ static inline bool guc_submission_initialized(struct
intel_guc *guc)
return !!guc->lrc_desc_pool_vaddr;
}
-static inline void reset_lrc_desc(struct intel_guc *guc, u32 id)
+static inline void _reset_lrc_desc(struct intel_guc *guc, u32 id)
{
- if (likely(guc_submission_initialized(guc))) {
- struct guc_lrc_desc *desc = __get_lrc_desc(guc, id);
- unsigned long flags;
-
- memset(desc, 0, sizeof(*desc));
+ struct guc_lrc_desc *desc = __get_lrc_desc(guc, id);
- /*
-* xarray API doesn't have xa_erase_irqsave wrapper, so calling
-* the lower level functions directly.
-*/
- xa_lock_irqsave(>context_lookup, flags);
- __xa_erase(>context_lookup, id);
- xa_unlock_irqrestore(>context_lookup, flags);
- }
+ memset(desc, 0, sizeof(*desc));
}
-static inline bool lrc_desc_registered(struct intel_guc *guc, u32 id)
+static inline bool ctx_id_mapped(struct intel_guc *guc, u32 id)
{
return __get_context(guc, id);
}
-static inline void set_lrc_desc_registered(struct intel_guc *guc, u32 id,
- struct intel_context *ce)
+static inline void set_ctx_id_mapping(struct intel_guc *guc, u32 id,
+ struct intel_context *ce)
{
unsigned long flags;
@@ -551,6 +540,24 @@ static inline void set_lrc_desc_registered(struct
intel_guc *guc, u32 id,
xa_unlock_irqrestore(>context_lookup, flags);
}
+static inline void clr_ctx_id_mapping(struct intel_guc *guc, u32 id)
+{
+ unsigned long flags;
+
+ if (unlikely(!guc_submission_initialized(guc)))
+ return;
+
+ _reset_lrc_desc(guc, id);
+
+ /*
+* xarray API doesn't have xa_erase_irqsave wrapper, so calling
+* the lower level functions directly.
+*/
+ xa_lock_irqsave(>context_lookup, flags);
+ __xa_erase(>context_lookup, id);
+ xa_unlock_irqrestore(>context_lookup, flags);
+}
+
static void decr_outstanding_submission_g2h(struct intel_guc *guc)
{
if (atomic_dec_and_test(>outstanding_submission_g2h))
@@ -795,7 +802,7 @@ static int __guc_wq_item_append(struct i915_request *rq)
GEM_BUG_ON(!atomic_read(>guc_id.ref));
GEM_BUG_ON(context_guc_id_invalid(ce));
GEM_BUG_ON(context_wait_for_deregister_to_register(ce));
- GEM_BUG_ON(!lrc_desc_registered(ce_to_guc(ce), ce->guc_id.id));
+ GEM_BUG_ON(!ctx_id_mapped(ce_to_guc(ce), ce->guc_id.id));
/* Insert NOOP if this work queue item will wrap the tail pointer. */
if (wqi_size > wq_space_until_wrap(ce)) {
@@ -923,7 +930,7 @@ static int guc_dequeue_one_context(struct intel_guc *guc)
if (submit) {
struct intel_context *ce = request_to_scheduling_context(last);
- if (unlikely(!lrc_desc_registered(guc, ce->guc_id.id) &&
+ if (unlikely(!ctx_id_mapped(guc, ce->guc_id.id) &&
!intel_context_is_banned(ce))) {
ret = guc_lrc_desc_pin(ce, false);
if (unlikely(ret == -EPIPE)) {
@@ -1897,7 +1904,7 @@ static bool need_tasklet(struct intel_guc *guc, struct
i915_request *rq)
return submission_disabled(guc) || guc->stalled_request ||
!i915_sched_engine_is_empty(sched_engine) ||
- !lrc_desc_registered(guc, ce->guc_id.id);
+ !ctx_id_mapped(guc, ce->guc_id.id);
}
static void guc_submit_request(struct i915_request *rq)
@@ -1954,7 +1961,7 @@ static void __release_guc_id(struct intel_guc *guc,
struct intel_context *ce)
else
ida_simple_remove(>submission_state.guc_ids,
ce->guc_id.id);
- reset_lrc_desc(guc, ce->guc_id.id);
+ clr_ctx_id_mapping(guc, ce->guc_id.id);
set_context_guc_id_invalid(ce);
}
if (!list_empty(>guc_id.link))
@@ -2250,10 +2257,10 @@ static int guc_lrc_desc_pin(struct intel_context *ce,
bool loop)
[Intel-gfx] [PATCH 4/8] drm/i915/guc: Split guc_lrc_desc_pin apart
From: John Harrison
The LRC descriptor pool is going away. Further, the function that was
populating it was also doing a bunch of logic about the context
registration sequence. So, split that code apart into separate state
setup and try to register functions. Note that some of those 'try to
register' code paths actually undo the state setup and leave it to be
redone again later (with potentially different values). This is
inefficient. The next patch will correct this.
Also, move a comment about ignoring return values to the place where
the return values are actually ignored.
Signed-off-by: John Harrison
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 45 ---
1 file changed, 28 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index ad784e8068c7..0ab2d1a24bf6 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -634,7 +634,7 @@ int intel_guc_wait_for_idle(struct intel_guc *guc, long
timeout)
true, timeout);
}
-static int guc_lrc_desc_pin(struct intel_context *ce, bool loop);
+static int try_context_registration(struct intel_context *ce, bool loop);
static int __guc_add_request(struct intel_guc *guc, struct i915_request *rq)
{
@@ -932,7 +932,7 @@ static int guc_dequeue_one_context(struct intel_guc *guc)
if (unlikely(!ctx_id_mapped(guc, ce->guc_id.id) &&
!intel_context_is_banned(ce))) {
- ret = guc_lrc_desc_pin(ce, false);
+ ret = try_context_registration(ce, false);
if (unlikely(ret == -EPIPE)) {
goto deadlk;
} else if (ret == -EBUSY) {
@@ -2237,17 +2237,13 @@ static void guc_context_policy_init(struct
intel_engine_cs *engine,
desc->preemption_timeout = engine->props.preempt_timeout_ms * 1000;
}
-static int guc_lrc_desc_pin(struct intel_context *ce, bool loop)
+static void prepare_context_registration_info(struct intel_context *ce)
{
struct intel_engine_cs *engine = ce->engine;
- struct intel_runtime_pm *runtime_pm = engine->uncore->rpm;
struct intel_guc *guc = >gt->uc.guc;
u32 desc_idx = ce->guc_id.id;
struct guc_lrc_desc *desc;
- bool context_registered;
- intel_wakeref_t wakeref;
struct intel_context *child;
- int ret = 0;
GEM_BUG_ON(!engine->mask);
GEM_BUG_ON(!sched_state_is_init(ce));
@@ -2259,8 +2255,6 @@ static int guc_lrc_desc_pin(struct intel_context *ce,
bool loop)
GEM_BUG_ON(i915_gem_object_is_lmem(guc->ct.vma->obj) !=
i915_gem_object_is_lmem(ce->ring->vma->obj));
- context_registered = ctx_id_mapped(guc, desc_idx);
-
clr_ctx_id_mapping(guc, desc_idx);
set_ctx_id_mapping(guc, desc_idx, ce);
@@ -2308,6 +2302,21 @@ static int guc_lrc_desc_pin(struct intel_context *ce,
bool loop)
clear_children_join_go_memory(ce);
}
+}
+
+static int try_context_registration(struct intel_context *ce, bool loop)
+{
+ struct intel_engine_cs *engine = ce->engine;
+ struct intel_runtime_pm *runtime_pm = engine->uncore->rpm;
+ struct intel_guc *guc = >gt->uc.guc;
+ intel_wakeref_t wakeref;
+ u32 desc_idx = ce->guc_id.id;
+ bool context_registered;
+ int ret = 0;
+
+ context_registered = ctx_id_mapped(guc, desc_idx);
+
+ prepare_context_registration_info(ce);
/*
* The context_lookup xarray is used to determine if the hardware
@@ -3145,7 +3154,7 @@ static int guc_request_alloc(struct i915_request *rq)
if (unlikely(ret < 0))
return ret;
if (context_needs_register(ce, !!ret)) {
- ret = guc_lrc_desc_pin(ce, true);
+ ret = try_context_registration(ce, true);
if (unlikely(ret)) {/* unwind */
if (ret == -EPIPE) {
disable_submission(guc);
@@ -3633,9 +3642,17 @@ static void guc_set_default_submission(struct
intel_engine_cs *engine)
static inline void guc_kernel_context_pin(struct intel_guc *guc,
struct intel_context *ce)
{
+ /*
+* Note: we purposefully do not check the returns below because
+* the registration can only fail if a reset is just starting.
+* This is called at the end of reset so presumably another reset
+* isn't happening and even it did this code would be run again.
+*/
+
if (context_guc_id_invalid(ce))
pin_guc_id(guc, ce);
- guc_lrc_desc_pin(ce, true);
+
+ try_context_registration(ce, true);
}
static inline void guc_init_lrc_mapping(struct intel_guc *guc)
@@ -3653,13 +3670,7 @@ static inline void
[Intel-gfx] [PATCH 0/8] Prep work for next GuC release
From: John Harrison The next GuC firmware release includes some significant backwards breaking API changes. One such is that there is no longer an LRC descriptor pool. A bunch of prep work for that change can be done in advance - the descriptor pool was being used for things it shouldn't really have been used for anyway. Signed-off-by: John Harrison John Harrison (8): drm/i915/guc: Do not conflate lrc_desc with GuC id for registration drm/i915/guc: Add an explicit 'submission_initialized' flag drm/i915/guc: Better name for context id limit drm/i915/guc: Split guc_lrc_desc_pin apart drm/i915/guc: Move lrc desc setup to where it is needed drm/i915/guc: Rename desc_idx to ctx_id drm/i915/guc: Drop obsolete H2G definitions drm/i915/guc: Fix potential invalid pointer dereferences when decoding G2Hs drivers/gpu/drm/i915/gt/intel_context.c | 2 +- .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 2 - drivers/gpu/drm/i915/gt/uc/intel_guc.h| 2 + drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 4 +- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 183 ++ drivers/gpu/drm/i915/gt/uc/selftest_guc.c | 2 +- 6 files changed, 112 insertions(+), 83 deletions(-) -- 2.25.1
[Intel-gfx] [PATCH 5/8] drm/i915/guc: Move lrc desc setup to where it is needed
From: John Harrison
The LRC descriptor was being initialised early on in the context
registration sequence. It could then be determined that the actual
registration needs to be delayed and the descriptor would be wiped
out. This is inefficient, so move the setup to later in the process
after the point of no return.
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 0ab2d1a24bf6..aa74ec74194a 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -2153,6 +2153,8 @@ static int __guc_action_register_context(struct intel_guc
*guc,
0, loop);
}
+static void prepare_context_registration_info(struct intel_context *ce);
+
static int register_context(struct intel_context *ce, bool loop)
{
struct intel_guc *guc = ce_to_guc(ce);
@@ -2163,6 +2165,8 @@ static int register_context(struct intel_context *ce,
bool loop)
GEM_BUG_ON(intel_context_is_child(ce));
trace_intel_context_register(ce);
+ prepare_context_registration_info(ce);
+
if (intel_context_is_parent(ce))
ret = __guc_action_register_multi_lrc(guc, ce, ce->guc_id.id,
offset, loop);
@@ -2246,7 +2250,6 @@ static void prepare_context_registration_info(struct
intel_context *ce)
struct intel_context *child;
GEM_BUG_ON(!engine->mask);
- GEM_BUG_ON(!sched_state_is_init(ce));
/*
* Ensure LRC + CT vmas are is same region as write barrier is done
@@ -2314,9 +2317,13 @@ static int try_context_registration(struct intel_context
*ce, bool loop)
bool context_registered;
int ret = 0;
+ GEM_BUG_ON(!sched_state_is_init(ce));
+
context_registered = ctx_id_mapped(guc, desc_idx);
- prepare_context_registration_info(ce);
+ if (context_registered)
+ clr_ctx_id_mapping(guc, desc_idx);
+ set_ctx_id_mapping(guc, desc_idx, ce);
/*
* The context_lookup xarray is used to determine if the hardware
--
2.25.1
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Disconnect PHYs left connected by BIOS on disabled ports
== Series Details ==
Series: drm/i915: Disconnect PHYs left connected by BIOS on disabled ports
URL : https://patchwork.freedesktop.org/series/100336/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
921ff943d11a drm/i915: Disconnect PHYs left connected by BIOS on disabled ports
-:19: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 64851a32c463 ("drm/i915/tc: Add
a mode for the TypeC PHY's disconnected state")'
#19:
Before commit 64851a32c463e5 the PHY connected state was read out even
total: 1 errors, 0 warnings, 0 checks, 48 lines checked
[Intel-gfx] ✗ Fi.CI.BUILD: warning for Introduce multitile support
== Series Details == Series: Introduce multitile support URL : https://patchwork.freedesktop.org/series/100331/ State : warning == Summary == CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh CHK include/generated/compile.h Kernel: arch/x86/boot/bzImage is ready (#1) MODPOST modules-only.symvers ERROR: modpost: "__divdi3" [drivers/gpu/drm/i915/i915.ko] undefined! scripts/Makefile.modpost:134: recipe for target 'modules-only.symvers' failed make[1]: *** [modules-only.symvers] Error 1 make[1]: *** Deleting file 'modules-only.symvers' Makefile:1746: recipe for target 'modules' failed make: *** [modules] Error 2 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22316/build_32bit.log
[Intel-gfx] ✗ Fi.CI.BAT: failure for Introduce multitile support
== Series Details == Series: Introduce multitile support URL : https://patchwork.freedesktop.org/series/100331/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11243 -> Patchwork_22316 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_22316 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_22316, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22316/index.html Participating hosts (43 -> 43) -- Additional (2): fi-snb-2600 fi-pnv-d510 Missing(2): fi-bsw-cyan shard-tglu Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_22316: ### IGT changes ### Possible regressions * igt@i915_selftest@live@requests: - fi-kbl-soraka: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11243/fi-kbl-soraka/igt@i915_selftest@l...@requests.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22316/fi-kbl-soraka/igt@i915_selftest@l...@requests.html Known issues Here are the changes found in Patchwork_22316 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@cs-multi-fence: - fi-bsw-nick:NOTRUN -> [SKIP][3] ([fdo#109271]) +17 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22316/fi-bsw-nick/igt@amdgpu/amd_ba...@cs-multi-fence.html * igt@amdgpu/amd_basic@semaphore: - fi-hsw-4770:NOTRUN -> [SKIP][4] ([fdo#109271] / [fdo#109315]) +17 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22316/fi-hsw-4770/igt@amdgpu/amd_ba...@semaphore.html * igt@amdgpu/amd_cs_nop@fork-compute0: - fi-rkl-guc: NOTRUN -> [SKIP][5] ([fdo#109315]) +17 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22316/fi-rkl-guc/igt@amdgpu/amd_cs_...@fork-compute0.html * igt@core_hotunplug@unbind-rebind: - fi-pnv-d510:NOTRUN -> [INCOMPLETE][6] ([i915#299]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22316/fi-pnv-d510/igt@core_hotunp...@unbind-rebind.html * igt@gem_huc_copy@huc-copy: - fi-skl-6600u: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#2190]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22316/fi-skl-6600u/igt@gem_huc_c...@huc-copy.html - fi-pnv-d510:NOTRUN -> [SKIP][8] ([fdo#109271]) +38 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22316/fi-pnv-d510/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@verify-random: - fi-skl-6600u: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#4613]) +3 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22316/fi-skl-6600u/igt@gem_lmem_swapp...@verify-random.html * igt@i915_selftest@live@hangcheck: - fi-snb-2600:NOTRUN -> [INCOMPLETE][10] ([i915#3921]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22316/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: - fi-snb-2600:NOTRUN -> [SKIP][11] ([fdo#109271]) +23 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22316/fi-snb-2600/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html * igt@kms_chamelium@hdmi-crc-fast: - fi-snb-2600:NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +8 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22316/fi-snb-2600/igt@kms_chamel...@hdmi-crc-fast.html * igt@kms_chamelium@vga-edid-read: - fi-skl-6600u: NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827]) +8 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22316/fi-skl-6600u/igt@kms_chamel...@vga-edid-read.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-skl-6600u: NOTRUN -> [SKIP][14] ([fdo#109271]) +21 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22316/fi-skl-6600u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-skl-6600u: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#533]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22316/fi-skl-6600u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html * igt@runner@aborted: - fi-pnv-d510:NOTRUN -> [FAIL][16] ([i915#2403] / [i915#4312]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22316/fi-pnv-d510/igt@run...@aborted.html - fi-kbl-soraka: NOTRUN -> [FAIL][17] ([i915#1436] / [i915#4312]) [17]:
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/dg2: Print PHY name properly on calibration error (rev3)
== Series Details == Series: drm/i915/dg2: Print PHY name properly on calibration error (rev3) URL : https://patchwork.freedesktop.org/series/100191/ State : success == Summary == CI Bug Log - changes from CI_DRM_11239_full -> Patchwork_22305_full Summary --- **SUCCESS** No regressions found. Participating hosts (11 -> 11) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_22305_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@preservation-s3@rcs0: - shard-skl: [PASS][1] -> [INCOMPLETE][2] ([i915#4793]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11239/shard-skl7/igt@gem_ctx_isolation@preservation...@rcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22305/shard-skl1/igt@gem_ctx_isolation@preservation...@rcs0.html * igt@gem_ctx_persistence@file: - shard-snb: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22305/shard-snb6/igt@gem_ctx_persiste...@file.html * igt@gem_exec_capture@pi@bcs0: - shard-skl: NOTRUN -> [INCOMPLETE][4] ([i915#4547]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22305/shard-skl8/igt@gem_exec_capture@p...@bcs0.html * igt@gem_exec_capture@pi@rcs0: - shard-iclb: NOTRUN -> [INCOMPLETE][5] ([i915#3371]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22305/shard-iclb5/igt@gem_exec_capture@p...@rcs0.html * igt@gem_exec_fair@basic-flow@rcs0: - shard-tglb: [PASS][6] -> [FAIL][7] ([i915#2842]) +1 similar issue [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11239/shard-tglb6/igt@gem_exec_fair@basic-f...@rcs0.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22305/shard-tglb7/igt@gem_exec_fair@basic-f...@rcs0.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-iclb: [PASS][8] -> [FAIL][9] ([i915#2842]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11239/shard-iclb7/igt@gem_exec_fair@basic-none-sh...@rcs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22305/shard-iclb4/igt@gem_exec_fair@basic-none-sh...@rcs0.html * igt@gem_exec_fair@basic-none-vip@rcs0: - shard-glk: [PASS][10] -> [FAIL][11] ([i915#2842]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11239/shard-glk5/igt@gem_exec_fair@basic-none-...@rcs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22305/shard-glk1/igt@gem_exec_fair@basic-none-...@rcs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-iclb: [PASS][12] -> [FAIL][13] ([i915#2849]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11239/shard-iclb4/igt@gem_exec_fair@basic-throt...@rcs0.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22305/shard-iclb2/igt@gem_exec_fair@basic-throt...@rcs0.html * igt@gem_lmem_swapping@heavy-verify-multi: - shard-kbl: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613]) +1 similar issue [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22305/shard-kbl4/igt@gem_lmem_swapp...@heavy-verify-multi.html * igt@gem_lmem_swapping@heavy-verify-random: - shard-iclb: NOTRUN -> [SKIP][15] ([i915#4613]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22305/shard-iclb6/igt@gem_lmem_swapp...@heavy-verify-random.html * igt@gem_media_vme: - shard-skl: NOTRUN -> [SKIP][16] ([fdo#109271]) +16 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22305/shard-skl10/igt@gem_media_vme.html * igt@gem_pxp@create-regular-context-1: - shard-iclb: NOTRUN -> [SKIP][17] ([i915#4270]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22305/shard-iclb5/igt@gem_...@create-regular-context-1.html * igt@gem_render_copy@y-tiled-to-vebox-linear: - shard-iclb: NOTRUN -> [SKIP][18] ([i915#768]) +1 similar issue [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22305/shard-iclb7/igt@gem_render_c...@y-tiled-to-vebox-linear.html * igt@gem_softpin@allocator-evict-all-engines: - shard-glk: [PASS][19] -> [FAIL][20] ([i915#4171]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11239/shard-glk3/igt@gem_soft...@allocator-evict-all-engines.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22305/shard-glk6/igt@gem_soft...@allocator-evict-all-engines.html * igt@gem_userptr_blits@dmabuf-sync: - shard-iclb: NOTRUN -> [SKIP][21] ([i915#3323]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22305/shard-iclb7/igt@gem_userptr_bl...@dmabuf-sync.html - shard-apl: NOTRUN -> [SKIP][22] ([fdo#109271] / [i915#3323]) [22]:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Introduce multitile support
== Series Details == Series: Introduce multitile support URL : https://patchwork.freedesktop.org/series/100331/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce multitile support
== Series Details == Series: Introduce multitile support URL : https://patchwork.freedesktop.org/series/100331/ State : warning == Summary == $ dim checkpatch origin/drm-tip 84ebedcd8baa drm/i915: Rename INTEL_REGION_LMEM with INTEL_REGION_LMEM_0 3122cf9d817d drm/i915: Prepare for multiple GTs -:252: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'id__' - possible side-effects? #252: FILE: drivers/gpu/drm/i915/gt/intel_gt.h:91: +#define for_each_gt(gt__, i915__, id__) \ + for ((id__) = 0; \ +(id__) < I915_MAX_GT; \ +(id__)++) \ + for_each_if(((gt__) = (i915__)->gt[(id__)])) total: 0 errors, 0 warnings, 1 checks, 435 lines checked 993116c384d8 drm/i915/gt: add gt_is_root() helper cb0e95e71059 drm/i915/gt: create per-tile sysfs interface -:70: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #70: new file mode 100644 total: 0 errors, 1 warnings, 0 checks, 222 lines checked 62eccef7a8ce drm/i915/gt: Create per-tile RC6 sysfs interface -:119: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #119: new file mode 100644 -:207: CHECK:SPACING: No space is necessary after a cast #207: FILE: drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:84: + return sysfs_emit(buff, "%u\n", (u32) rc6_residency); -:222: CHECK:SPACING: No space is necessary after a cast #222: FILE: drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:99: + return sysfs_emit(buff, "%u\n", (u32) rc6p_residency); -:237: CHECK:SPACING: No space is necessary after a cast #237: FILE: drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:114: + return sysfs_emit(buff, "%u\n", (u32) rc6pp_residency); -:252: CHECK:SPACING: No space is necessary after a cast #252: FILE: drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:129: + return sysfs_emit(buff, "%u\n", (u32) rc6_residency); total: 0 errors, 1 warnings, 4 checks, 427 lines checked 8a294f4a2e2e drm/i915/gt: Create per-tile RPS sysfs interfaces -:127: CHECK:SPACING: No space is necessary after a cast #127: FILE: drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:253: + return sysfs_emit(buff, "%u\n", (u32) actual_freq); -:141: CHECK:SPACING: No space is necessary after a cast #141: FILE: drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:267: + return sysfs_emit(buff, "%u\n", (u32) cur_freq); -:156: CHECK:SPACING: No space is necessary after a cast #156: FILE: drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:282: + return sysfs_emit(buff, "%u\n", (u32) boost_freq); -:209: CHECK:SPACING: No space is necessary after a cast #209: FILE: drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:335: + return sysfs_emit(buff, "%d\n", (int) rpe_freq); -:233: ERROR:CODE_INDENT: code indent should use tabs where possible #233: FILE: drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:359: + struct device_attribute *attr,$ -:233: WARNING:LEADING_SPACE: please, no spaces at the start of a line #233: FILE: drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:359: + struct device_attribute *attr,$ -:234: ERROR:CODE_INDENT: code indent should use tabs where possible #234: FILE: drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:360: + const char *buff, size_t count);$ -:234: WARNING:LEADING_SPACE: please, no spaces at the start of a line #234: FILE: drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:360: + const char *buff, size_t count);$ -:238: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_mode' - possible side-effects? #238: FILE: drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:364: +#define INTEL_GT_RPS_SYSFS_ATTR(_name, _mode, _show, _store) \ + struct device_attribute dev_attr_gt_##_name = __ATTR(gt_##_name, _mode, _show, _store); \ + struct device_attribute dev_attr_rps_##_name = __ATTR(rps_##_name, _mode, _show, _store) -:238: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_show' - possible side-effects? #238: FILE: drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:364: +#define INTEL_GT_RPS_SYSFS_ATTR(_name, _mode, _show, _store) \ + struct device_attribute dev_attr_gt_##_name = __ATTR(gt_##_name, _mode, _show, _store); \ + struct device_attribute dev_attr_rps_##_name = __ATTR(rps_##_name, _mode, _show, _store) -:238: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_store' - possible side-effects? #238: FILE: drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:364: +#define INTEL_GT_RPS_SYSFS_ATTR(_name, _mode, _show, _store) \ + struct device_attribute dev_attr_gt_##_name = __ATTR(gt_##_name, _mode, _show, _store); \ + struct device_attribute dev_attr_rps_##_name = __ATTR(rps_##_name, _mode, _show, _store) -:259: CHECK:CAMELCASE: Avoid CamelCase: #259: FILE: drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:385: +static INTEL_GT_RPS_SYSFS_ATTR(RPn_freq_mhz, 0444, rps_rp_mhz_show, NULL); -:272: CHECK:CAMELCASE: Avoid CamelCase: #272: FILE:
[Intel-gfx] [CI 4/4] drm/i915/reg: split out icl_dsi_regs.h
The ICL DSI registers have fairly isolated usage. Split the register macros to a separate file. Cc: Matt Roper Reviewed-by: Matt Roper Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/icl_dsi.c | 1 + drivers/gpu/drm/i915/display/icl_dsi_regs.h | 342 drivers/gpu/drm/i915/i915_irq.c | 1 + drivers/gpu/drm/i915/i915_reg.h | 333 --- 4 files changed, 344 insertions(+), 333 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/icl_dsi_regs.h diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index 3c01565e62b2..13b07c6fd6be 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -29,6 +29,7 @@ #include #include "icl_dsi.h" +#include "icl_dsi_regs.h" #include "intel_atomic.h" #include "intel_backlight.h" #include "intel_combo_phy.h" diff --git a/drivers/gpu/drm/i915/display/icl_dsi_regs.h b/drivers/gpu/drm/i915/display/icl_dsi_regs.h new file mode 100644 index ..f78f28b8dd94 --- /dev/null +++ b/drivers/gpu/drm/i915/display/icl_dsi_regs.h @@ -0,0 +1,342 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2022 Intel Corporation + */ + +#ifndef __ICL_DSI_REGS_H__ +#define __ICL_DSI_REGS_H__ + +#include "i915_reg_defs.h" + +/* Gen11 DSI */ +#define _MMIO_DSI(tc, dsi0, dsi1) _MMIO_TRANS((tc) - TRANSCODER_DSI_0, \ + dsi0, dsi1) +#define _ICL_DSI_ESC_CLK_DIV0 0x6b090 +#define _ICL_DSI_ESC_CLK_DIV1 0x6b890 +#define ICL_DSI_ESC_CLK_DIV(port) _MMIO_PORT((port), \ + _ICL_DSI_ESC_CLK_DIV0, \ + _ICL_DSI_ESC_CLK_DIV1) +#define _ICL_DPHY_ESC_CLK_DIV0 0x162190 +#define _ICL_DPHY_ESC_CLK_DIV1 0x6C190 +#define ICL_DPHY_ESC_CLK_DIV(port) _MMIO_PORT((port), \ + _ICL_DPHY_ESC_CLK_DIV0, \ + _ICL_DPHY_ESC_CLK_DIV1) +#define ICL_BYTE_CLK_PER_ESC_CLK_MASK (0x1f << 16) +#define ICL_BYTE_CLK_PER_ESC_CLK_SHIFT16 +#define ICL_ESC_CLK_DIV_MASK 0x1ff +#define ICL_ESC_CLK_DIV_SHIFT 0 +#define DSI_MAX_ESC_CLK2 /* in KHz */ + +#define _ADL_MIPIO_REG 0x180 +#define ADL_MIPIO_DW(port, dw) _MMIO(_ICL_COMBOPHY(port) + _ADL_MIPIO_REG + 4 * (dw)) +#define TX_ESC_CLK_DIV_PHY_SEL REGBIT(16) +#define TX_ESC_CLK_DIV_PHY_MASK REG_GENMASK(23, 16) +#define TX_ESC_CLK_DIV_PHY REG_FIELD_PREP(TX_ESC_CLK_DIV_PHY_MASK, 0x7f) + +#define _DSI_CMD_FRMCTL_0 0x6b034 +#define _DSI_CMD_FRMCTL_1 0x6b834 +#define DSI_CMD_FRMCTL(port) _MMIO_PORT(port,\ + _DSI_CMD_FRMCTL_0,\ + _DSI_CMD_FRMCTL_1) +#define DSI_FRAME_UPDATE_REQUEST (1 << 31) +#define DSI_PERIODIC_FRAME_UPDATE_ENABLE (1 << 29) +#define DSI_NULL_PACKET_ENABLE (1 << 28) +#define DSI_FRAME_IN_PROGRESS(1 << 0) + +#define _DSI_INTR_MASK_REG_0 0x6b070 +#define _DSI_INTR_MASK_REG_1 0x6b870 +#define DSI_INTR_MASK_REG(port)_MMIO_PORT(port,\ + _DSI_INTR_MASK_REG_0,\ + _DSI_INTR_MASK_REG_1) + +#define _DSI_INTR_IDENT_REG_0 0x6b074 +#define _DSI_INTR_IDENT_REG_1 0x6b874 +#define DSI_INTR_IDENT_REG(port) _MMIO_PORT(port,\ + _DSI_INTR_IDENT_REG_0,\ + _DSI_INTR_IDENT_REG_1) +#define DSI_TE_EVENT (1 << 31) +#define DSI_RX_DATA_OR_BTA_TERMINATED(1 << 30) +#define DSI_TX_DATA (1 << 29) +#define DSI_ULPS_ENTRY_DONE (1 << 28) +#define DSI_NON_TE_TRIGGER_RECEIVED (1 << 27) +#define DSI_HOST_CHKSUM_ERROR(1 << 26) +#define DSI_HOST_MULTI_ECC_ERROR (1 << 25) +#define DSI_HOST_SINGL_ECC_ERROR (1 << 24) +#define DSI_HOST_CONTENTION_DETECTED (1 << 23) +#define DSI_HOST_FALSE_CONTROL_ERROR (1 << 22) +#define DSI_HOST_TIMEOUT_ERROR (1 << 21) +#define DSI_HOST_LOW_POWER_TX_SYNC_ERROR (1 << 20) +#define DSI_HOST_ESCAPE_MODE_ENTRY_ERROR (1 << 19) +#define DSI_FRAME_UPDATE_DONE(1 << 16) +#define DSI_PROTOCOL_VIOLATION_REPORTED (1 << 15) +#define DSI_INVALID_TX_LENGTH(1 << 13) +#define DSI_INVALID_VC (1 << 12) +#define DSI_INVALID_DATA_TYPE
[Intel-gfx] [CI 3/4] drm/i915/reg: split out vlv_dsi_regs.h and vlv_dsi_pll_regs.h
The VLV (including CHV, BXT, and GLK) DSI registers have fairly isolated
usage. Split the register macros to separated files.
Cc: Matt Roper
Reviewed-by: Matt Roper
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c | 3 +-
drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 1 +
drivers/gpu/drm/i915/display/vlv_dsi.c| 1 +
drivers/gpu/drm/i915/display/vlv_dsi_pll.c| 1 +
.../gpu/drm/i915/display/vlv_dsi_pll_regs.h | 109
drivers/gpu/drm/i915/display/vlv_dsi_regs.h | 480 +++
drivers/gpu/drm/i915/gvt/handlers.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 574 --
8 files changed, 595 insertions(+), 575 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/vlv_dsi_pll_regs.h
create mode 100644 drivers/gpu/drm/i915/display/vlv_dsi_regs.h
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 59961621fe4a..ff13cfde8664 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -113,9 +113,10 @@
#include "i9xx_plane.h"
#include "skl_scaler.h"
#include "skl_universal_plane.h"
+#include "vlv_dsi.h"
#include "vlv_dsi_pll.h"
+#include "vlv_dsi_regs.h"
#include "vlv_sideband.h"
-#include "vlv_dsi.h"
static void intel_set_transcoder_timings(const struct intel_crtc_state
*crtc_state);
static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
index a1cd86e53e21..6b4a27372c82 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
@@ -44,6 +44,7 @@
#include "intel_dsi.h"
#include "intel_dsi_vbt.h"
#include "vlv_dsi.h"
+#include "vlv_dsi_regs.h"
#include "vlv_sideband.h"
#define MIPI_TRANSFER_MODE_SHIFT 0
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c
b/drivers/gpu/drm/i915/display/vlv_dsi.c
index f0c38173491e..0d936f658b3f 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
@@ -44,6 +44,7 @@
#include "skl_scaler.h"
#include "vlv_dsi.h"
#include "vlv_dsi_pll.h"
+#include "vlv_dsi_regs.h"
#include "vlv_sideband.h"
/* return pixels in terms of txbyteclkhs */
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
index 1b81797dd02e..df880f44700a 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
@@ -32,6 +32,7 @@
#include "intel_display_types.h"
#include "intel_dsi.h"
#include "vlv_dsi_pll.h"
+#include "vlv_dsi_pll_regs.h"
#include "vlv_sideband.h"
static const u16 lfsr_converts[] = {
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_pll_regs.h
b/drivers/gpu/drm/i915/display/vlv_dsi_pll_regs.h
new file mode 100644
index ..45590e14e54b
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/vlv_dsi_pll_regs.h
@@ -0,0 +1,109 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __VLV_DSI_PLL_REGS_H__
+#define __VLV_DSI_PLL_REGS_H__
+
+#include "vlv_dsi_regs.h"
+
+#define MIPIO_TXESC_CLK_DIV1 _MMIO(0x160004)
+#define GLK_TX_ESC_CLK_DIV1_MASK 0x3FF
+#define MIPIO_TXESC_CLK_DIV2 _MMIO(0x160008)
+#define GLK_TX_ESC_CLK_DIV2_MASK 0x3FF
+
+#define BXT_MAX_VAR_OUTPUT_KHZ 39500
+
+#define BXT_MIPI_CLOCK_CTL _MMIO(0x46090)
+#define BXT_MIPI1_DIV_SHIFT 26
+#define BXT_MIPI2_DIV_SHIFT 10
+#define BXT_MIPI_DIV_SHIFT(port) \
+ _MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \
+ BXT_MIPI2_DIV_SHIFT)
+
+/* TX control divider to select actual TX clock output from (8x/var) */
+#define BXT_MIPI1_TX_ESCLK_SHIFT 26
+#define BXT_MIPI2_TX_ESCLK_SHIFT 10
+#define BXT_MIPI_TX_ESCLK_SHIFT(port) \
+ _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \
+ BXT_MIPI2_TX_ESCLK_SHIFT)
+#define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK(0x3F << 26)
+#define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK(0x3F << 10)
+#define BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port) \
+ _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \
+ BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
+#define BXT_MIPI_TX_ESCLK_DIVIDER(port, val) \
+ (((val) & 0x3F) << BXT_MIPI_TX_ESCLK_SHIFT(port))
+/* RX upper control divider to select actual RX clock output from 8x */
+#define BXT_MIPI1_RX_ESCLK_UPPER_SHIFT21
+#define BXT_MIPI2_RX_ESCLK_UPPER_SHIFT5
+#define BXT_MIPI_RX_ESCLK_UPPER_SHIFT(port) \
+ _MIPI_PORT(port,
[Intel-gfx] [CI 2/4] drm/i915/dsi: add separate init timer mask definition for ICL DSI
Having a separate definition will be useful for splitting VLV and ICL
register files.
Cc: Matt Roper
Reviewed-by: Matt Roper
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/icl_dsi.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h| 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
b/drivers/gpu/drm/i915/display/icl_dsi.c
index 479d5e1165d9..3c01565e62b2 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -570,7 +570,7 @@ gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
/* Program T-INIT master registers */
for_each_dsi_port(port, intel_dsi->ports) {
tmp = intel_de_read(dev_priv, ICL_DSI_T_INIT_MASTER(port));
- tmp &= ~MASTER_INIT_TIMER_MASK;
+ tmp &= ~DSI_T_INIT_MASTER_MASK;
tmp |= intel_dsi->init_count;
intel_de_write(dev_priv, ICL_DSI_T_INIT_MASTER(port), tmp);
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2243d9d1d941..1fe4be8d475c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9001,6 +9001,7 @@ enum skl_power_gate {
#define ICL_DSI_T_INIT_MASTER(port)_MMIO_PORT(port,\
_ICL_DSI_T_INIT_MASTER_0,\
_ICL_DSI_T_INIT_MASTER_1)
+#define DSI_T_INIT_MASTER_MASK REG_GENMASK(15, 0)
#define _DPHY_CLK_TIMING_PARAM_0 0x162180
#define _DPHY_CLK_TIMING_PARAM_1 0x6c180
--
2.30.2
[Intel-gfx] [CI 1/4] drm/i915/dsi: disassociate VBT video transfer mode from register values
The VBT DSI video transfer mode field values have been defined in terms
of the VLV MIPI_VIDEO_MODE_FORMAT register. The ICL DSI code maps that
to ICL DSI_TRANS_FUNC_CONF() register. The values are the same, though
the shift is different.
Make a clean break and disassociate the values from each other. Assume
the values can be different, and translate the VBT value to VLV and ICL
register values as needed. Use the existing macros from intel_bios.h.
This will be useful in splitting the DSI register macros to files by DSI
implementation.
Cc: Matt Roper
Reviewed-by: Matt Roper
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/icl_dsi.c | 11 +++
drivers/gpu/drm/i915/display/intel_dsi.h | 4 +--
drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 10 +++---
drivers/gpu/drm/i915/display/vlv_dsi.c | 33
4 files changed, 39 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
b/drivers/gpu/drm/i915/display/icl_dsi.c
index 2d5bb9195b20..479d5e1165d9 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -788,14 +788,14 @@ gen11_dsi_configure_transcoder(struct intel_encoder
*encoder,
/* program DSI operation mode */
if (is_vid_mode(intel_dsi)) {
tmp &= ~OP_MODE_MASK;
- switch (intel_dsi->video_mode_format) {
+ switch (intel_dsi->video_mode) {
default:
- MISSING_CASE(intel_dsi->video_mode_format);
+ MISSING_CASE(intel_dsi->video_mode);
fallthrough;
- case VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS:
+ case NON_BURST_SYNC_EVENTS:
tmp |= VIDEO_MODE_SYNC_EVENT;
break;
- case VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE:
+ case NON_BURST_SYNC_PULSE:
tmp |= VIDEO_MODE_SYNC_PULSE;
break;
}
@@ -960,8 +960,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder
*encoder,
/* TRANS_HSYNC register to be programmed only for video mode */
if (is_vid_mode(intel_dsi)) {
- if (intel_dsi->video_mode_format ==
- VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE) {
+ if (intel_dsi->video_mode == NON_BURST_SYNC_PULSE) {
/* BSPEC: hsync size should be atleast 16 pixels */
if (hsync_size < 16)
drm_err(_priv->drm,
diff --git a/drivers/gpu/drm/i915/display/intel_dsi.h
b/drivers/gpu/drm/i915/display/intel_dsi.h
index a3a906cb097e..eafef0a87fea 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi.h
+++ b/drivers/gpu/drm/i915/display/intel_dsi.h
@@ -79,8 +79,8 @@ struct intel_dsi {
*/
enum mipi_dsi_pixel_format pixel_format;
- /* video mode format for MIPI_VIDEO_MODE_FORMAT register */
- u32 video_mode_format;
+ /* NON_BURST_SYNC_PULSE, NON_BURST_SYNC_EVENTS, or BURST_MODE */
+ int video_mode;
/* eot for MIPI_EOT_DISABLE register */
u8 eotp_pkt;
diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
index a85574c413e8..a1cd86e53e21 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
@@ -675,11 +675,11 @@ void intel_dsi_log_params(struct intel_dsi *intel_dsi)
drm_dbg_kms(>drm, "Lane count %d\n", intel_dsi->lane_count);
drm_dbg_kms(>drm, "DPHY param reg 0x%x\n", intel_dsi->dphy_reg);
drm_dbg_kms(>drm, "Video mode format %s\n",
- intel_dsi->video_mode_format ==
VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE ?
+ intel_dsi->video_mode == NON_BURST_SYNC_PULSE ?
"non-burst with sync pulse" :
- intel_dsi->video_mode_format ==
VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS ?
+ intel_dsi->video_mode == NON_BURST_SYNC_EVENTS ?
"non-burst with sync events" :
- intel_dsi->video_mode_format == VIDEO_MODE_BURST ?
+ intel_dsi->video_mode == BURST_MODE ?
"burst" : "");
drm_dbg_kms(>drm, "Burst mode ratio %d\n",
intel_dsi->burst_mode_ratio);
@@ -739,7 +739,7 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16
panel_id)
intel_dsi->dual_link = mipi_config->dual_link;
intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
intel_dsi->operation_mode = mipi_config->is_cmd_mode;
- intel_dsi->video_mode_format = mipi_config->video_transfer_mode;
+ intel_dsi->video_mode = mipi_config->video_transfer_mode;
intel_dsi->escape_clk_div =
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: use ref_tracker library for tracking wakerefs
== Series Details == Series: drm/i915: use ref_tracker library for tracking wakerefs URL : https://patchwork.freedesktop.org/series/100327/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11242 -> Patchwork_22315 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_22315 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_22315, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22315/index.html Participating hosts (38 -> 42) -- Additional (7): fi-kbl-soraka bat-dg1-6 bat-adlp-6 bat-rpls-1 bat-rpls-2 bat-jsl-2 bat-jsl-1 Missing(3): fi-bsw-cyan shard-tglu fi-pnv-d510 Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_22315: ### IGT changes ### Possible regressions * igt@i915_selftest@live@gt_engines: - fi-cfl-8109u: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11242/fi-cfl-8109u/igt@i915_selftest@live@gt_engines.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22315/fi-cfl-8109u/igt@i915_selftest@live@gt_engines.html * igt@i915_selftest@live@gt_pm: - fi-kbl-7567u: [PASS][3] -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11242/fi-kbl-7567u/igt@i915_selftest@live@gt_pm.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22315/fi-kbl-7567u/igt@i915_selftest@live@gt_pm.html - fi-cfl-8700k: [PASS][5] -> [INCOMPLETE][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11242/fi-cfl-8700k/igt@i915_selftest@live@gt_pm.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22315/fi-cfl-8700k/igt@i915_selftest@live@gt_pm.html - fi-kbl-7500u: [PASS][7] -> [INCOMPLETE][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11242/fi-kbl-7500u/igt@i915_selftest@live@gt_pm.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22315/fi-kbl-7500u/igt@i915_selftest@live@gt_pm.html - fi-cml-u2: [PASS][9] -> [INCOMPLETE][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11242/fi-cml-u2/igt@i915_selftest@live@gt_pm.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22315/fi-cml-u2/igt@i915_selftest@live@gt_pm.html Known issues Here are the changes found in Patchwork_22315 that come from known issues: ### IGT changes ### Issues hit * igt@fbdev@info: - bat-dg1-6: NOTRUN -> [SKIP][11] ([i915#2582]) +4 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22315/bat-dg1-6/igt@fb...@info.html * igt@gem_exec_fence@basic-busy@bcs0: - fi-kbl-soraka: NOTRUN -> [SKIP][12] ([fdo#109271]) +8 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22315/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html * igt@gem_exec_gttfill@basic: - bat-dg1-6: NOTRUN -> [SKIP][13] ([i915#4086]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22315/bat-dg1-6/igt@gem_exec_gttf...@basic.html * igt@gem_huc_copy@huc-copy: - fi-skl-6600u: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#2190]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22315/fi-skl-6600u/igt@gem_huc_c...@huc-copy.html - fi-kbl-soraka: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#2190]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22315/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-kbl-soraka: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4613]) +3 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22315/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html * igt@gem_lmem_swapping@verify-random: - fi-skl-6600u: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613]) +3 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22315/fi-skl-6600u/igt@gem_lmem_swapp...@verify-random.html * igt@gem_mmap@basic: - bat-dg1-6: NOTRUN -> [SKIP][18] ([i915#4083]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22315/bat-dg1-6/igt@gem_m...@basic.html * igt@gem_tiled_blits@basic: - bat-dg1-6: NOTRUN -> [SKIP][19] ([i915#4077]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22315/bat-dg1-6/igt@gem_tiled_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-dg1-6: NOTRUN -> [SKIP][20] ([i915#4079]) +1 similar issue [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22315/bat-dg1-6/igt@gem_tiled_pread_basic.html * igt@i915_pm_backlight@basic-brightness: - bat-dg1-6: NOTRUN ->
Re: [Intel-gfx] [PATCH v3] drm/i915/display/vrr: Reset VRR capable property on a long hpd
Hi Jani,
This addresses the review comments, could you please take a look at thsi patch?
Manasi
On Tue, Feb 15, 2022 at 12:26:01PM -0800, Manasi Navare wrote:
> With some VRR panels, user can turn VRR ON/OFF on the fly from the panel
> settings.
> When VRR is turned OFF ,sends a long HPD to the driver clearing the Ignore
> MSA bit
> in the DPCD. Currently the driver parses that onevery HPD but fails to reset
> the corresponding VRR Capable Connector property.
> Hence the userspace still sees this as VRR Capable panel which is incorrect.
>
> Fix this by explicitly resetting the connector property.
>
> v2: Reset vrr capable if status == connector_disconnected
> v3: Use i915 and use bool vrr_capable (Jani Nikula)
> v4: Move vrr_capable to after update modes call (Jani N)
> Remove the redundant comment (Jan N)
>
> Cc: Jani Nikula
> Signed-off-by: Manasi Navare
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 17 +
> 1 file changed, 13 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 1046e7fe310a..929e9b6febf1 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4455,6 +4455,12 @@ intel_dp_detect(struct drm_connector *connector,
> memset(_dp->compliance, 0, sizeof(intel_dp->compliance));
> memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
>
> + /* Reset VRR Capable property */
> + drm_dbg_kms(_priv->drm, "[CONNECTOR:%d:%s] VRR capable:
> FALSE\n",
> + connector->base.id, connector->name);
> + drm_connector_set_vrr_capable_property(connector,
> +false);
> +
> if (intel_dp->is_mst) {
> drm_dbg_kms(_priv->drm,
> "MST device may have disappeared %d vs
> %d\n",
> @@ -4569,15 +4575,18 @@ static int intel_dp_get_modes(struct drm_connector
> *connector)
> {
> struct intel_connector *intel_connector = to_intel_connector(connector);
> struct edid *edid;
> + struct drm_i915_private *i915 = to_i915(connector->dev);
> int num_modes = 0;
>
> edid = intel_connector->detect_edid;
> if (edid) {
> - num_modes = intel_connector_update_modes(connector, edid);
> + bool vrr_capable;
>
> - if (intel_vrr_is_capable(connector))
> - drm_connector_set_vrr_capable_property(connector,
> -true);
> + num_modes = intel_connector_update_modes(connector, edid);
> + vrr_capable = intel_vrr_is_capable(connector);
> + drm_dbg_kms(>drm, "[CONNECTOR:%d:%s] VRR capable: %s\n",
> + connector->base.id, connector->name,
> yesno(vrr_capable));
> + drm_connector_set_vrr_capable_property(connector, vrr_capable);
> }
>
> /* Also add fixed mode, which may or may not be present in EDID */
> --
> 2.19.1
>
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/dg2: Move misplaced 'ctx' & 'gt' wa's to engine wa list
On Thu, Feb 17, 2022 at 10:46:44AM +, Patchwork wrote: > == Series Details == > > Series: drm/i915/dg2: Move misplaced 'ctx' & 'gt' wa's to engine wa list > URL : https://patchwork.freedesktop.org/series/100212/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_11238_full -> Patchwork_22291_full > > > Summary > --- > > **FAILURE** > > Serious unknown changes coming with Patchwork_22291_full absolutely need to > be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_22291_full, please notify your bug team to allow > them > to document this new failure mode, which will reduce false positives in CI. > > > > Participating hosts (12 -> 11) > -- > > Missing(1): shard-dg1 > > Possible new issues > --- > > Here are the unknown changes that may have been introduced in > Patchwork_22291_full: > > ### IGT changes ### > > Possible regressions > > * igt@kms_big_fb@x-tiled-8bpp-rotate-180: > - shard-glk: [PASS][1] -> [FAIL][2] >[1]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11238/shard-glk4/igt@kms_big...@x-tiled-8bpp-rotate-180.html >[2]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22291/shard-glk6/igt@kms_big...@x-tiled-8bpp-rotate-180.html https://gitlab.freedesktop.org/drm/intel/-/issues/5138 > > * igt@perf_pmu@module-unload: > - shard-iclb: NOTRUN -> [FAIL][3] >[3]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22291/shard-iclb5/igt@perf_...@module-unload.html https://gitlab.freedesktop.org/drm/intel/-/issues/5136 Neither is caused by this patch. Applied to drm-intel-gt-next. Thanks for the patch. Matt > > > Known issues > > > Here are the changes found in Patchwork_22291_full that come from known > issues: > > ### IGT changes ### > > Issues hit > > * igt@gem_exec_balancer@parallel-balancer: > - shard-iclb: [PASS][4] -> [SKIP][5] ([i915#4525]) >[4]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11238/shard-iclb4/igt@gem_exec_balan...@parallel-balancer.html >[5]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22291/shard-iclb6/igt@gem_exec_balan...@parallel-balancer.html > > * igt@gem_exec_capture@pi@rcs0: > - shard-skl: NOTRUN -> [INCOMPLETE][6] ([i915#4547]) >[6]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22291/shard-skl1/igt@gem_exec_capture@p...@rcs0.html > > * igt@gem_exec_fair@basic-throttle@rcs0: > - shard-iclb: [PASS][7] -> [FAIL][8] ([i915#2849]) >[7]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11238/shard-iclb7/igt@gem_exec_fair@basic-throt...@rcs0.html >[8]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22291/shard-iclb4/igt@gem_exec_fair@basic-throt...@rcs0.html > > * igt@gem_exec_params@secure-non-root: > - shard-iclb: NOTRUN -> [SKIP][9] ([fdo#112283]) >[9]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22291/shard-iclb5/igt@gem_exec_par...@secure-non-root.html > > * igt@gem_exec_whisper@basic-contexts-forked: > - shard-glk: [PASS][10] -> [DMESG-WARN][11] ([i915#118]) +1 > similar issue >[10]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11238/shard-glk2/igt@gem_exec_whis...@basic-contexts-forked.html >[11]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22291/shard-glk7/igt@gem_exec_whis...@basic-contexts-forked.html > > * igt@gem_lmem_swapping@heavy-verify-random: > - shard-skl: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#4613]) > +3 similar issues >[12]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22291/shard-skl10/igt@gem_lmem_swapp...@heavy-verify-random.html > - shard-iclb: NOTRUN -> [SKIP][13] ([i915#4613]) >[13]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22291/shard-iclb3/igt@gem_lmem_swapp...@heavy-verify-random.html > > * igt@gem_lmem_swapping@random-engines: > - shard-apl: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613]) >[14]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22291/shard-apl4/igt@gem_lmem_swapp...@random-engines.html > > * igt@gem_mmap_gtt@cpuset-big-copy: > - shard-skl: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) >[15]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11238/shard-skl4/igt@gem_mmap_...@cpuset-big-copy.html >[16]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22291/shard-skl8/igt@gem_mmap_...@cpuset-big-copy.html > > * igt@gem_pwrite@basic-exhaustion: > - shard-skl: NOTRUN -> [WARN][17] ([i915#2658]) >[17]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22291/shard-skl4/igt@gem_pwr...@basic-exhaustion.html > > * igt@gem_render_copy@y-tiled-to-vebox-linear: > - shard-iclb:
Re: [Intel-gfx] [PATCH] drm/i915/dg2: Move misplaced 'ctx' & 'gt' wa's to engine wa list
On Tue, Feb 15, 2022 at 03:55:31PM -0800, Matt Roper wrote:
> From: Srinivasan Shanmugam
>
> Registers that belong to the shared render/compute reset domain need to
> be placed on an engine workaround list to ensure that they are properly
> re-applied whenever any RCS or CCS engine is reset, even if the
> registers do not belong to a specific engine's MMIO range. We have a
> number of workarounds today that are incorrectly implemented on the 'gt'
> workaround list and need to be moved accordingly. We also have one
> workaround (Wa_22012532006) that is incorrectly implemented on the
> context workaround list, even though the register it is adjusting is not
> part of the RCS engine's context image; it must also be moved.
>
> We'll have some workaround refactoring coming in the near future that
> deals with registers in the reset domain in a more clear way. But in
> the meantime, we should just move these workarounds to
> rcs_engine_wa_init() to place them on the RCS engine's workaround list.
> All production DG2 platforms will have an RCS engine (it's never fused
> off) so these registers will be properly restored after a domain reset
> triggered via an RCS engine _or_ a CCS engine.
>
> Cc: Matt Roper
> Signed-off-by: Srinivasan Shanmugam
> Signed-off-by: Matt Roper
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 62 -
> 1 file changed, 35 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index b146a393cd79..03df02f76473 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -683,12 +683,6 @@ static void dg2_ctx_workarounds_init(struct
> intel_engine_cs *engine,
> /* Wa_16013271637:dg2 */
> wa_masked_en(wal, SLICE_COMMON_ECO_CHICKEN1,
>MSC_MSAA_REODER_BUF_BYPASS_DISABLE);
> -
> - /* Wa_22012532006:dg2 */
> - if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_C0) ||
> - IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0))
> - wa_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7,
> - DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA);
> }
>
> static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine,
> @@ -1440,10 +1434,6 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct
> i915_wa_list *wal)
> }
>
> if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0)) {
> - /* Wa_14010680813:dg2_g10 */
> - wa_write_or(wal, GEN12_GAMSTLB_CTRL, CONTROL_BLOCK_CLKGATE_DIS |
> - EGRESS_BLOCK_CLKGATE_DIS | TAG_BLOCK_CLKGATE_DIS);
> -
> /* Wa_14010948348:dg2_g10 */
> wa_write_or(wal, UNSLCGCTL9430, MSQDUNIT_CLKGATE_DIS);
>
> @@ -1490,16 +1480,6 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct
> i915_wa_list *wal)
> wa_write_or(wal, SSMCGCTL9530, RTFUNIT_CLKGATE_DIS);
> }
>
> - if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0) ||
> - IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0)) {
> - /* Wa_14012362059:dg2 */
> - wa_write_or(wal, GEN12_MERT_MOD_CTRL, FORCE_MISS_FTLB);
> - }
> -
> - /* Wa_1509235366:dg2 */
> - wa_write_or(wal, GEN12_GAMCNTRL_CTRL, INVALIDATION_BROADCAST_MODE_DIS |
> - GLOBAL_INVALIDATION_MODE);
> -
> /* Wa_14014830051:dg2 */
> wa_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
>
> @@ -1508,14 +1488,7 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct
> i915_wa_list *wal)
>* recommended tuning settings documented in the bspec's
>* performance guide section.
>*/
> - wa_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
> wa_write_or(wal, GEN12_SQCM, EN_32B_ACCESS);
> -
> - /* Wa_18018781329:dg2 */
> - wa_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
> - wa_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
> - wa_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB);
> - wa_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB);
> }
>
> static void
> @@ -2049,6 +2022,23 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
> struct i915_wa_list *wal)
> if (IS_DG2(i915)) {
> /* Wa_14015227452:dg2 */
> wa_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE);
> +
> + /* Wa_1509235366:dg2 */
> + wa_write_or(wal, GEN12_GAMCNTRL_CTRL,
> INVALIDATION_BROADCAST_MODE_DIS |
> + GLOBAL_INVALIDATION_MODE);
> +
> + /*
> + * The following are not actually "workarounds" but rather
> + * recommended tuning settings documented in the bspec's
> + * performance guide section.
> + */
> + wa_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
> +
> + /* Wa_18018781329:dg2 */
> +
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: use ref_tracker library for tracking wakerefs
== Series Details == Series: drm/i915: use ref_tracker library for tracking wakerefs URL : https://patchwork.freedesktop.org/series/100327/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: use ref_tracker library for tracking wakerefs
== Series Details ==
Series: drm/i915: use ref_tracker library for tracking wakerefs
URL : https://patchwork.freedesktop.org/series/100327/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
3401795c5e59 lib/ref_tracker: add unlocked leak print helper
-:6: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description
(prefer a maximum 75 chars per line)
#6:
To have reliable detection of leaks, caller must be able to check under the same
-:23: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#23: FILE: include/linux/ref_tracker.h:36:
+void __ref_tracker_dir_print(struct ref_tracker_dir *dir,
+ unsigned int display_limit);
-:49: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#49: FILE: lib/ref_tracker.c:18:
+void __ref_tracker_dir_print(struct ref_tracker_dir *dir,
+ unsigned int display_limit)
total: 0 errors, 1 warnings, 2 checks, 105 lines checked
f9401246d32f lib/ref_tracker: compact stacktraces before printing
a7d1346f3833 lib/ref_tracker: __ref_tracker_dir_print improve printing
-:37: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#37: FILE: include/linux/ref_tracker.h:29:
+static inline void __ref_tracker_dir_init(struct ref_tracker_dir *dir,
+ unsigned int quarantine_count,
-:45: WARNING:STRLCPY: Prefer strscpy over strlcpy - see:
https://lore.kernel.org/r/CAHk-=wgfRnXz0W3D37d01q3JFkr_i_uTL=v6a6g1ouzcprm...@mail.gmail.com/
#45: FILE: include/linux/ref_tracker.h:37:
+ strlcpy(dir->name, name, sizeof(dir->name));
total: 0 errors, 1 warnings, 1 checks, 100 lines checked
537929a5562f lib/ref_tracker: add printing to memory buffer
-:52: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'fmt' - possible side-effects?
#52: FILE: lib/ref_tracker.c:35:
+#define pr_ostream(stream, fmt, args...) \
+({ \
+ struct ostream *_s = (stream); \
+\
+ if (!_s->buf) { \
+ pr_err(fmt, ##args); \
+ } else { \
+ int ret, len = _s->size - _s->used; \
+ ret = snprintf(_s->buf + _s->used, len, pr_fmt(fmt), ##args); \
+ _s->used += min(ret, len); \
+ } \
+})
-:91: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#91: FILE: lib/ref_tracker.c:92:
+void __ref_tracker_dir_print(struct ref_tracker_dir *dir,
+ unsigned int display_limit)
total: 0 errors, 0 warnings, 2 checks, 96 lines checked
deea71578401 lib/ref_tracker: improve allocation flags
eeb686073725 drm/i915: Separate wakeref tracking
-:7: WARNING:REPEATED_WORD: Possible repeated word: 'that'
#7:
utility so that that we can reuse it for other online debugging of
-:453: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#453:
new file mode 100644
-:710: WARNING:NEW_TYPEDEFS: do not add new typedefs
#710: FILE: drivers/gpu/drm/i915/intel_wakeref_tracker.h:13:
+typedef depot_stack_handle_t intel_wakeref_t;
-:715: CHECK:UNCOMMENTED_DEFINITION: spinlock_t definition without comment
#715: FILE: drivers/gpu/drm/i915/intel_wakeref_tracker.h:18:
+ spinlock_t lock;
-:731: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#731: FILE: drivers/gpu/drm/i915/intel_wakeref_tracker.h:34:
+void intel_wakeref_tracker_remove(struct intel_wakeref_tracker *w,
+ intel_wakeref_t handle);
-:768: WARNING:LONG_LINE: line length of 112 exceeds 100 columns
#768: FILE: drivers/gpu/drm/i915/intel_wakeref_tracker.h:71:
+static inline void __intel_wakeref_tracker_show(const struct
intel_wakeref_tracker *w, struct drm_printer *p) {}
-:769: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#769: FILE: drivers/gpu/drm/i915/intel_wakeref_tracker.h:72:
+static inline void intel_wakeref_tracker_show(struct intel_wakeref_tracker *w,
struct drm_printer *p) {}
-:773: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address
mismatch: 'From: Chris Wilson ' != 'Signed-off-by:
Chris Wilson '
total: 0 errors, 6 warnings, 2 checks, 713 lines checked
4cf7b916ce01 drm/i915: Track leaked gt->wakerefs
-:450: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'gt' - possible side-effects?
#450: FILE: drivers/gpu/drm/i915/gt/intel_gt_pm.h:75:
+#define with_intel_gt_pm(gt, wf) \
+ for (wf = intel_gt_pm_get(gt); wf; intel_gt_pm_put(gt, wf), wf = 0)
-:450: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'wf' - possible side-effects?
#450: FILE: drivers/gpu/drm/i915/gt/intel_gt_pm.h:75:
+#define with_intel_gt_pm(gt, wf) \
+ for (wf = intel_gt_pm_get(gt); wf; intel_gt_pm_put(gt, wf), wf = 0)
-:798: ERROR:ASSIGN_IN_IF: do not use assignment in if condition
#798: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:1280:
+ if (!in_reset && (wakeref = intel_gt_pm_get_if_awake(gt))) {
total: 1 errors, 0 warnings, 2 checks, 775 lines checked
2eb9912803ea drm/i915: Correct type of wakeref variable
[Intel-gfx] [PATCH] drm/i915/guc: Fix flag query helper function to not modify state
From: John Harrison
A flag query helper was actually writing to the flags word rather than
just reading. Fix that. Also update the function's comment as it was
out of date.
NB: No need for a 'Fixes' tag. The test was only ever used inside a
BUG_ON during context registration. Rather than asserting that the
condition was true, it was making the condition true. So, in theory,
there was no consequence because we should never have hit a BUG_ON
anyway. Which means the write should always have been a no-op.
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index b3a429a92c0d..d9f4218f5ef4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -174,11 +174,8 @@ static inline void init_sched_state(struct intel_context
*ce)
__maybe_unused
static bool sched_state_is_init(struct intel_context *ce)
{
- /*
-* XXX: Kernel contexts can have SCHED_STATE_NO_LOCK_REGISTERED after
-* suspend.
-*/
- return !(ce->guc_state.sched_state &=
+ /* Kernel contexts can have SCHED_STATE_REGISTERED after suspend. */
+ return !(ce->guc_state.sched_state &
~(SCHED_STATE_BLOCKED_MASK | SCHED_STATE_REGISTERED));
}
--
2.25.1
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: use get_reset_domain() helper
== Series Details ==
Series: drm/i915/gt: use get_reset_domain() helper
URL : https://patchwork.freedesktop.org/series/100326/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11242 -> Patchwork_22314
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22314/index.html
Participating hosts (38 -> 43)
--
Additional (7): bat-dg1-6 bat-dg2-8 bat-adlp-6 bat-rpls-1 bat-rpls-2
bat-jsl-2 bat-jsl-1
Missing(2): fi-bsw-cyan shard-tglu
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_22314:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@core_auth@basic-auth:
- {bat-jsl-2}:NOTRUN -> [DMESG-WARN][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22314/bat-jsl-2/igt@core_a...@basic-auth.html
Known issues
Here are the changes found in Patchwork_22314 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@cs-multi-fence:
- fi-blb-e6850: NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22314/fi-blb-e6850/igt@amdgpu/amd_ba...@cs-multi-fence.html
* igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-snb-2600:NOTRUN -> [SKIP][3] ([fdo#109271]) +17 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22314/fi-snb-2600/igt@amdgpu/amd_cs_...@sync-fork-compute0.html
* igt@amdgpu/amd_cs_nop@sync-fork-gfx0:
- fi-skl-6600u: NOTRUN -> [SKIP][4] ([fdo#109271]) +21 similar issues
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22314/fi-skl-6600u/igt@amdgpu/amd_cs_...@sync-fork-gfx0.html
* igt@fbdev@info:
- bat-dg1-6: NOTRUN -> [SKIP][5] ([i915#2582]) +4 similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22314/bat-dg1-6/igt@fb...@info.html
* igt@gem_exec_gttfill@basic:
- bat-dg1-6: NOTRUN -> [SKIP][6] ([i915#4086])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22314/bat-dg1-6/igt@gem_exec_gttf...@basic.html
* igt@gem_huc_copy@huc-copy:
- fi-skl-6600u: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#2190])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22314/fi-skl-6600u/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@verify-random:
- fi-skl-6600u: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#4613]) +3
similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22314/fi-skl-6600u/igt@gem_lmem_swapp...@verify-random.html
* igt@gem_mmap@basic:
- bat-dg1-6: NOTRUN -> [SKIP][9] ([i915#4083])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22314/bat-dg1-6/igt@gem_m...@basic.html
* igt@gem_tiled_blits@basic:
- bat-dg1-6: NOTRUN -> [SKIP][10] ([i915#4077]) +2 similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22314/bat-dg1-6/igt@gem_tiled_bl...@basic.html
* igt@gem_tiled_pread_basic:
- bat-dg1-6: NOTRUN -> [SKIP][11] ([i915#4079]) +1 similar issue
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22314/bat-dg1-6/igt@gem_tiled_pread_basic.html
* igt@i915_pm_backlight@basic-brightness:
- bat-dg1-6: NOTRUN -> [SKIP][12] ([i915#1155])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22314/bat-dg1-6/igt@i915_pm_backli...@basic-brightness.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: NOTRUN -> [DMESG-FAIL][13] ([i915#4494] / [i915#4957])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22314/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
* igt@kms_addfb_basic@addfb25-x-tiled-legacy:
- bat-dg1-6: NOTRUN -> [SKIP][14] ([i915#4212]) +7 similar issues
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22314/bat-dg1-6/igt@kms_addfb_ba...@addfb25-x-tiled-legacy.html
* igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg1-6: NOTRUN -> [SKIP][15] ([i915#4215])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22314/bat-dg1-6/igt@kms_addfb_ba...@basic-y-tiled-legacy.html
* igt@kms_busy@basic:
- bat-dg1-6: NOTRUN -> [SKIP][16] ([i915#4303])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22314/bat-dg1-6/igt@kms_b...@basic.html
* igt@kms_chamelium@hdmi-edid-read:
- bat-dg1-6: NOTRUN -> [SKIP][17] ([fdo#111827]) +8 similar issues
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22314/bat-dg1-6/igt@kms_chamel...@hdmi-edid-read.html
* igt@kms_chamelium@vga-edid-read:
- fi-skl-6600u: NOTRUN -> [SKIP][18] ([fdo#109271] / [fdo#111827]) +8
similar issues
[18]:
Re: [Intel-gfx] [PATCH v2 1/3] drm/i915/dg2: Enable 5th port
On Fri, Feb 18, 2022 at 12:12:21AM +0530, Ramalingam C wrote: From: Matt Roper DG2 supports a 5th display output which the hardware refers to as "TC1," even though it isn't a Type-C output. This behaves similarly to the TC1 on past platforms with just a couple minor differences: * DG2's TC1 bit in SDEISR is at bit 25 rather than 24 as it is on ICP/TGP/ADP. * DG2 doesn't need the hpd inversion setting that we had to use on DG1 v2: intel_ddi_init(dev_priv, PORT_TC1); [Matt] Cc: Swathi Dhanavanthri Cc: Lucas De Marchi Cc: José Roberto de Souza Signed-off-by: Matt Roper Signed-off-by: Ramalingam C Reviewed-by: Lucas De Marchi Lucas De Marchi
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix disabled crtc state clearing, again
== Series Details == Series: drm/i915: Fix disabled crtc state clearing, again URL : https://patchwork.freedesktop.org/series/100316/ State : success == Summary == CI Bug Log - changes from CI_DRM_11242 -> Patchwork_22313 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22313/index.html Participating hosts (38 -> 42) -- Additional (7): fi-kbl-soraka bat-dg1-6 bat-adlp-6 bat-rpls-1 bat-rpls-2 bat-jsl-2 bat-jsl-1 Missing(3): fi-bsw-cyan shard-tglu fi-pnv-d510 Known issues Here are the changes found in Patchwork_22313 that come from known issues: ### IGT changes ### Issues hit * igt@fbdev@info: - bat-dg1-6: NOTRUN -> [SKIP][1] ([i915#2582]) +4 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22313/bat-dg1-6/igt@fb...@info.html * igt@gem_exec_fence@basic-busy@bcs0: - fi-kbl-soraka: NOTRUN -> [SKIP][2] ([fdo#109271]) +8 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22313/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html * igt@gem_exec_gttfill@basic: - bat-dg1-6: NOTRUN -> [SKIP][3] ([i915#4086]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22313/bat-dg1-6/igt@gem_exec_gttf...@basic.html * igt@gem_huc_copy@huc-copy: - fi-kbl-soraka: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22313/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-kbl-soraka: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613]) +3 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22313/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html * igt@gem_mmap@basic: - bat-dg1-6: NOTRUN -> [SKIP][6] ([i915#4083]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22313/bat-dg1-6/igt@gem_m...@basic.html * igt@gem_tiled_blits@basic: - bat-dg1-6: NOTRUN -> [SKIP][7] ([i915#4077]) +2 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22313/bat-dg1-6/igt@gem_tiled_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-dg1-6: NOTRUN -> [SKIP][8] ([i915#4079]) +1 similar issue [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22313/bat-dg1-6/igt@gem_tiled_pread_basic.html * igt@i915_pm_backlight@basic-brightness: - bat-dg1-6: NOTRUN -> [SKIP][9] ([i915#1155]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22313/bat-dg1-6/igt@i915_pm_backli...@basic-brightness.html * igt@i915_selftest@live@gt_pm: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][10] ([i915#1886] / [i915#2291]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22313/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html * igt@i915_selftest@live@hangcheck: - fi-bdw-5557u: NOTRUN -> [INCOMPLETE][11] ([i915#3921]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22313/fi-bdw-5557u/igt@i915_selftest@l...@hangcheck.html - bat-dg1-6: NOTRUN -> [DMESG-FAIL][12] ([i915#4494] / [i915#4957]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22313/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html * igt@kms_addfb_basic@addfb25-x-tiled-legacy: - bat-dg1-6: NOTRUN -> [SKIP][13] ([i915#4212]) +7 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22313/bat-dg1-6/igt@kms_addfb_ba...@addfb25-x-tiled-legacy.html * igt@kms_addfb_basic@basic-y-tiled-legacy: - bat-dg1-6: NOTRUN -> [SKIP][14] ([i915#4215]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22313/bat-dg1-6/igt@kms_addfb_ba...@basic-y-tiled-legacy.html * igt@kms_busy@basic: - bat-dg1-6: NOTRUN -> [SKIP][15] ([i915#4303]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22313/bat-dg1-6/igt@kms_b...@basic.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-kbl-soraka: NOTRUN -> [SKIP][16] ([fdo#109271] / [fdo#111827]) +8 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22313/fi-kbl-soraka/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_chamelium@dp-crc-fast: - fi-bdw-5557u: NOTRUN -> [SKIP][17] ([fdo#109271] / [fdo#111827]) +8 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22313/fi-bdw-5557u/igt@kms_chamel...@dp-crc-fast.html * igt@kms_chamelium@hdmi-edid-read: - bat-dg1-6: NOTRUN -> [SKIP][18] ([fdo#111827]) +8 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22313/bat-dg1-6/igt@kms_chamel...@hdmi-edid-read.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - bat-dg1-6: NOTRUN -> [SKIP][19] ([i915#4103] / [i915#4213]) +1 similar issue [19]:
Re: [Intel-gfx] [PATCH] drm/i915/pxp: prefer forward declaration over includes
On Mon, Feb 14, 2022 at 07:36:44PM +0200, Jani Nikula wrote: > Always use forward declarations instead of includes in headers if > possible. > > Signed-off-by: Jani Nikula Reviewed-by: Matt Roper > --- > drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h > b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h > index 16990a3f2f85..586be769104f 100644 > --- a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h > +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h > @@ -6,7 +6,7 @@ > #ifndef __INTEL_PXP_PM_H__ > #define __INTEL_PXP_PM_H__ > > -#include "intel_pxp_types.h" > +struct intel_pxp; > > #ifdef CONFIG_DRM_I915_PXP > void intel_pxp_suspend_prepare(struct intel_pxp *pxp); > -- > 2.30.2 > -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795
Re: [Intel-gfx] [PATCH v5 5/7] drm/i915/gt: Create per-tile RC6 sysfs interface
Hi Andi, I love your patch! Yet something to improve: [auto build test ERROR on drm-tip/drm-tip] [cannot apply to drm-intel/for-linux-next drm-exynos/exynos-drm-next drm/drm-next tegra-drm/drm/tegra/for-next airlied/drm-next v5.17-rc4 next-20220217] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Andi-Shyti/Introduce-multitile-support/20220217-224547 base: git://anongit.freedesktop.org/drm/drm-tip drm-tip config: i386-defconfig (https://download.01.org/0day-ci/archive/20220218/202202180400.ppkeh3z4-...@intel.com/config) compiler: gcc-9 (Debian 9.3.0-22) 9.3.0 reproduce (this is a W=1 build): # https://github.com/0day-ci/linux/commit/b358d991c154dc27fa4ef2fc99f8819f4f3e97e7 git remote add linux-review https://github.com/0day-ci/linux git fetch --no-tags linux-review Andi-Shyti/Introduce-multitile-support/20220217-224547 git checkout b358d991c154dc27fa4ef2fc99f8819f4f3e97e7 # save the config file to linux build tree mkdir build_dir make W=1 O=build_dir ARCH=i386 SHELL=/bin/bash If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot All errors (new ones prefixed by >>): ld: drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.o: in function `sysfs_gt_attribute_r_func.isra.0': >> intel_gt_sysfs_pm.c:(.text+0x1b2): undefined reference to `__divdi3' --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org
Re: [Intel-gfx] [PATCH 3/3] drm/i915: Fix for PHY_MISC_TC1 offset
On Wed, Feb 16, 2022 at 09:36:02AM +, Hogander, Jouni wrote:
On Wed, 2022-02-16 at 10:50 +0200, Ville Syrjälä wrote:
On Tue, Feb 15, 2022 at 11:21:54AM +0530, Ramalingam C wrote:
> From: Jouni Högander
>
> Currently ICL_PHY_MISC macro is returning offset 0x64C10 for PHY_E
> port. Correct offset is 0x64C14.
Why is it PHY_E and not PHY_F?
This is a valid question. It seems we have followed intel_phy_is_snps()
here:
// snip
else if (IS_DG2(dev_priv))
/*
* All four "combo" ports and the TC1 port (PHY E) use
* Synopsis PHYs.
*/
return phy <= PHY_E;
// snip
And this is actually the bug that we had. We wouldn't need to bring the
incomplete support for the 5th port if this single had changed: it's
often preferred to prepare the driver first and enable the port/phy as
the last step:
- return phy <= PHY_E;
+ return phy <= PHY_D;
With possibly a change in the commit above. Because in
drivers/gpu/drm/i915/display/intel_snps_phy.c we do:
intel_snps_phy_wait_for_calibration()
{
...
for_each_phy_masked(phy, ~0) {
if (!intel_phy_is_snps(i915, phy))
continue;
...
}
Relying on intel_phy_is_snps() to mask out the unavailable phys.
However, since now we almost have the extra port wired up, I'm not going
to push back on it. Let's just add a comment on the commit message.
And since going with this approach is also acked by Ville who preferred
to contain the additional mapping inside intel_phy_snps.c:
Reviewed-by: Lucas De Marchi
Lucas De Marchi
According to spec port E is "No connection". Better place to fix this
could be intel_phy_is_snps() itself?
> Fix this by handling PHY_E port seprately.
>
> Signed-off-by: Matt Roper
> Signed-off-by: Jouni Högander
> Signed-off-by: Ramalingam C
> ---
> drivers/gpu/drm/i915/display/intel_snps_phy.c | 2 +-
> drivers/gpu/drm/i915/i915_reg.h | 6 --
> 2 files changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c
> b/drivers/gpu/drm/i915/display/intel_snps_phy.c
> index c60575cb5368..f08061c748b3 100644
> --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
> @@ -32,7 +32,7 @@ void intel_snps_phy_wait_for_calibration(struct
> drm_i915_private *i915)
>if (!intel_phy_is_snps(i915, phy))
>continue;
>
> - if (intel_de_wait_for_clear(i915, ICL_PHY_MISC(phy),
> + if (intel_de_wait_for_clear(i915, DG2_PHY_MISC(phy),
>DG2_PHY_DP_TX_ACK_MASK,
> 25))
>drm_err(>drm, "SNPS PHY %c failed to
> calibrate after 25ms.\n",
>phy);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 4d12abb2d7ff..354c25f483cb 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9559,8 +9559,10 @@ enum skl_power_gate {
>
> #define _ICL_PHY_MISC_A 0x64C00
> #define _ICL_PHY_MISC_B 0x64C04
> -#define ICL_PHY_MISC(port)_MMIO_PORT(port, _ICL_PHY_MISC_A, \
> - _ICL_PHY_MISC_B)
> +#define _DG2_PHY_MISC_TC1 0x64C14 /* TC1="PHY E" but offset as if
> "PHY F" */
> +#define ICL_PHY_MISC(port)_MMIO_PORT(port, _ICL_PHY_MISC_A,
> _ICL_PHY_MISC_B)
> +#define DG2_PHY_MISC(port)((port) == PHY_E ?
> _MMIO(_DG2_PHY_MISC_TC1) : \
> + ICL_PHY_MISC(port))
> #define ICL_PHY_MISC_MUX_DDID(1 << 28)
> #define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23)
> #define DG2_PHY_DP_TX_ACK_MASK REG_GENMASK(23,
> 20)
> --
> 2.20.1
BR,
Jouni Högander
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/guc/slpc: Correct the param count for unset param
== Series Details == Series: drm/i915/guc/slpc: Correct the param count for unset param URL : https://patchwork.freedesktop.org/series/100260/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11239_full -> Patchwork_22303_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_22303_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_22303_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (11 -> 11) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_22303_full: ### IGT changes ### Possible regressions * igt@gem_eio@in-flight-contexts-1us: - shard-snb: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11239/shard-snb5/igt@gem_...@in-flight-contexts-1us.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22303/shard-snb7/igt@gem_...@in-flight-contexts-1us.html Known issues Here are the changes found in Patchwork_22303_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@preservation-s3@bcs0: - shard-kbl: NOTRUN -> [DMESG-WARN][3] ([i915#180]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22303/shard-kbl1/igt@gem_ctx_isolation@preservation...@bcs0.html * igt@gem_exec_capture@pi@vecs0: - shard-iclb: NOTRUN -> [INCOMPLETE][4] ([i915#3371]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22303/shard-iclb7/igt@gem_exec_capture@p...@vecs0.html * igt@gem_exec_fair@basic-flow@rcs0: - shard-tglb: [PASS][5] -> [FAIL][6] ([i915#2842]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11239/shard-tglb6/igt@gem_exec_fair@basic-f...@rcs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22303/shard-tglb7/igt@gem_exec_fair@basic-f...@rcs0.html * igt@gem_exec_fair@basic-none-vip@rcs0: - shard-glk: [PASS][7] -> [FAIL][8] ([i915#2842]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11239/shard-glk5/igt@gem_exec_fair@basic-none-...@rcs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22303/shard-glk8/igt@gem_exec_fair@basic-none-...@rcs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-iclb: [PASS][9] -> [FAIL][10] ([i915#2849]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11239/shard-iclb4/igt@gem_exec_fair@basic-throt...@rcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22303/shard-iclb1/igt@gem_exec_fair@basic-throt...@rcs0.html * igt@gem_exec_whisper@basic-queues-forked-all: - shard-glk: [PASS][11] -> [DMESG-WARN][12] ([i915#118]) +2 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11239/shard-glk5/igt@gem_exec_whis...@basic-queues-forked-all.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22303/shard-glk1/igt@gem_exec_whis...@basic-queues-forked-all.html * igt@gem_lmem_swapping@heavy-verify-random: - shard-iclb: NOTRUN -> [SKIP][13] ([i915#4613]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22303/shard-iclb5/igt@gem_lmem_swapp...@heavy-verify-random.html * igt@gem_lmem_swapping@parallel-random: - shard-kbl: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22303/shard-kbl4/igt@gem_lmem_swapp...@parallel-random.html * igt@gem_media_vme: - shard-skl: NOTRUN -> [SKIP][15] ([fdo#109271]) +46 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22303/shard-skl2/igt@gem_media_vme.html * igt@gem_pxp@create-regular-context-1: - shard-iclb: NOTRUN -> [SKIP][16] ([i915#4270]) +1 similar issue [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22303/shard-iclb7/igt@gem_...@create-regular-context-1.html * igt@gem_render_copy@y-tiled-to-vebox-linear: - shard-iclb: NOTRUN -> [SKIP][17] ([i915#768]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22303/shard-iclb6/igt@gem_render_c...@y-tiled-to-vebox-linear.html * igt@gem_userptr_blits@dmabuf-sync: - shard-iclb: NOTRUN -> [SKIP][18] ([i915#3323]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22303/shard-iclb6/igt@gem_userptr_bl...@dmabuf-sync.html - shard-apl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#3323]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22303/shard-apl3/igt@gem_userptr_bl...@dmabuf-sync.html * igt@gem_userptr_blits@input-checking: - shard-kbl:
[Intel-gfx] [PATCH v2 2/3] drm/i915/gem: Remove logic for wbinvd_on_all_cpus
drm_cache.h now handles calls to wbinvd_on_all_cpus.
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/i915/gem/i915_gem_pm.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
index 00359ec9d58b..ee4783e4d135 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
@@ -13,12 +13,7 @@
#include "i915_driver.h"
#include "i915_drv.h"
-#if defined(CONFIG_X86)
-#include
-#else
-#define wbinvd_on_all_cpus() \
- pr_warn(DRIVER_NAME ": Missing cache flush in %s\n", __func__)
-#endif
+#include
void i915_gem_suspend(struct drm_i915_private *i915)
{
--
2.25.1
[Intel-gfx] [PATCH v2 3/3] drm/i915/: Add drm_cache.h
Add drm_cache.h to additionals files that calls wbinvd_on_all_cpus and remove un-needed header files. Signed-off-by: Michael Cheng --- drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 2 +- drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c index 13917231ae81..edb0ebbb089c 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c @@ -9,7 +9,7 @@ #include #include -#include +#include #include "gem/i915_gem_dmabuf.h" #include "i915_drv.h" diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c index 8850d4e0f9cc..dac62e3ba142 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c @@ -7,10 +7,10 @@ #include #include -#include #include #include +#include #include "gem/i915_gem_lmem.h" -- 2.25.1
[Intel-gfx] [PATCH v2 1/3] drm_cache: Add logic for wbvind_on_all_cpus
Add logic for wbvind_on_all_cpus for non-x86 platforms.
v2(Michael Cheng): Change logic to if platform is not x86, then
we add pr_warn for calling wbvind_on_all_cpus.
Signed-off-by: Michael Cheng
---
drivers/gpu/drm/drm_cache.c | 2 --
include/drm/drm_cache.h | 6 ++
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c
index 66597e411764..722e3931d68a 100644
--- a/drivers/gpu/drm/drm_cache.c
+++ b/drivers/gpu/drm/drm_cache.c
@@ -40,8 +40,6 @@
#define MEMCPY_BOUNCE_SIZE 128
#if defined(CONFIG_X86)
-#include
-
/*
* clflushopt is an unordered instruction which needs fencing with mfence or
* sfence to avoid ordering issues. For drm_clflush_page this fencing happens
diff --git a/include/drm/drm_cache.h b/include/drm/drm_cache.h
index 22deb216b59c..24fcf6be1419 100644
--- a/include/drm/drm_cache.h
+++ b/include/drm/drm_cache.h
@@ -34,6 +34,12 @@
#define _DRM_CACHE_H_
#include
+#include
+
+#if !defined(CONFIG_x86)
+#define wbinvd_on_all_cpus() \
+ pr_warn("Missing cache flush in %s\n", __func__)
+#endif
struct iosys_map;
--
2.25.1
[Intel-gfx] [PATCH v2 0/3] Move #define wbvind_on_all_cpus
This series moves the logic for wbvind_on_all_cpus to drm_cache. The logic changes a little here, if platform is not x86 then we throw out a warning for when wbvind_on_all_cpus is being called. v2(Michael Cheng): Move and redo logic for wbvind_on_all_cpus. Also add drm_cache.h where the function is being called and remove uneeded header files. Michael Cheng (3): drm_cache: Add logic for wbvind_on_all_cpus drm/i915/gem: Remove logic for wbinvd_on_all_cpus drm/i915/: Add drm_cache.h drivers/gpu/drm/drm_cache.c| 2 -- drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 2 +- drivers/gpu/drm/i915/gem/i915_gem_pm.c | 7 +-- drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +- include/drm/drm_cache.h| 6 ++ 5 files changed, 9 insertions(+), 10 deletions(-) -- 2.25.1
[Intel-gfx] [Important!] 2022 X.Org Foundation Membership deadline for voting in the election
The 2022 X.Org Foundation elections are rapidly approaching. We will be forwarding instructions on the nomination process to membership in the near future. Please note that only current members can vote in the upcoming election, and that the deadline for new memberships or renewals to vote in the upcoming election is March 17th 2022 at 23:59 UTC. If you are interested in joining the X.Org Foundation or in renewing your membership, please visit the membership system site at: https://members.x.org/ You can find the current election schedule here: https://www.x.org/wiki/BoardOfDirectors/Elections/2022/ Lyude Paul, On behalf of the X.Org elections committee
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: SAGV fixes (rev2)
== Series Details ==
Series: drm/i915: SAGV fixes (rev2)
URL : https://patchwork.freedesktop.org/series/100091/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11239_full -> Patchwork_22302_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_22302_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22302_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (11 -> 11)
--
No changes in participating hosts
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_22302_full:
### IGT changes ###
Possible regressions
* igt@kms_cursor_legacy@all-pipes-forked-bo:
- shard-iclb: [PASS][1] -> [INCOMPLETE][2] +10 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11239/shard-iclb4/igt@kms_cursor_leg...@all-pipes-forked-bo.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22302/shard-iclb5/igt@kms_cursor_leg...@all-pipes-forked-bo.html
* igt@kms_cursor_legacy@all-pipes-single-bo:
- shard-tglb: [PASS][3] -> [INCOMPLETE][4] +9 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11239/shard-tglb5/igt@kms_cursor_leg...@all-pipes-single-bo.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22302/shard-tglb6/igt@kms_cursor_leg...@all-pipes-single-bo.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-skl: NOTRUN -> [INCOMPLETE][5]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22302/shard-skl3/igt@kms_fbcon_...@psr-suspend.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_cursor_legacy@pipe-c-single-move:
- {shard-tglu}: NOTRUN -> [INCOMPLETE][6]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22302/shard-tglu-4/igt@kms_cursor_leg...@pipe-c-single-move.html
* igt@kms_cursor_legacy@pipe-d-forked-move:
- {shard-tglu}: [PASS][7] -> [INCOMPLETE][8] +8 similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11239/shard-tglu-4/igt@kms_cursor_leg...@pipe-d-forked-move.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22302/shard-tglu-4/igt@kms_cursor_leg...@pipe-d-forked-move.html
Known issues
Here are the changes found in Patchwork_22302_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_isolation@preservation-s3@bcs0:
- shard-apl: [PASS][9] -> [DMESG-WARN][10] ([i915#180])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11239/shard-apl7/igt@gem_ctx_isolation@preservation...@bcs0.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22302/shard-apl3/igt@gem_ctx_isolation@preservation...@bcs0.html
* igt@gem_eio@in-flight-immediate:
- shard-tglb: [PASS][11] -> [TIMEOUT][12] ([i915#3063])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11239/shard-tglb1/igt@gem_...@in-flight-immediate.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22302/shard-tglb8/igt@gem_...@in-flight-immediate.html
* igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-glk: [PASS][13] -> [FAIL][14] ([i915#2842])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11239/shard-glk5/igt@gem_exec_fair@basic-none-...@rcs0.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22302/shard-glk8/igt@gem_exec_fair@basic-none-...@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][15] -> [FAIL][16] ([i915#2842])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11239/shard-tglb7/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22302/shard-tglb6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-kbl: NOTRUN -> [FAIL][17] ([i915#2842])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22302/shard-kbl4/igt@gem_exec_fair@basic-pace-s...@rcs0.html
* igt@gem_exec_whisper@basic-normal-all:
- shard-glk: [PASS][18] -> [DMESG-WARN][19] ([i915#118])
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11239/shard-glk5/igt@gem_exec_whis...@basic-normal-all.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22302/shard-glk8/igt@gem_exec_whis...@basic-normal-all.html
* igt@gem_lmem_swapping@heavy-verify-multi:
- shard-kbl: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#4613]) +2
similar issues
[20]:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dp: remove accidental static on what should be a local variable
== Series Details == Series: drm/i915/dp: remove accidental static on what should be a local variable URL : https://patchwork.freedesktop.org/series/100310/ State : success == Summary == CI Bug Log - changes from CI_DRM_11241 -> Patchwork_22312 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22312/index.html Participating hosts (46 -> 43) -- Missing(3): fi-bsw-cyan fi-icl-u2 shard-tglu Known issues Here are the changes found in Patchwork_22312 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s3@smem: - fi-skl-6600u: [PASS][1] -> [INCOMPLETE][2] ([i915#4547]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11241/fi-skl-6600u/igt@gem_exec_suspend@basic...@smem.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22312/fi-skl-6600u/igt@gem_exec_suspend@basic...@smem.html * igt@i915_selftest@live@hangcheck: - bat-dg1-6: [PASS][3] -> [DMESG-FAIL][4] ([i915#4494] / [i915#4957]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11241/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22312/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html - bat-dg1-5: [PASS][5] -> [DMESG-FAIL][6] ([i915#4494] / [i915#4957]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11241/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22312/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html Possible fixes * igt@i915_selftest@live@gt_pm: - fi-tgl-1115g4: [DMESG-FAIL][7] ([i915#3987]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11241/fi-tgl-1115g4/igt@i915_selftest@live@gt_pm.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22312/fi-tgl-1115g4/igt@i915_selftest@live@gt_pm.html * igt@kms_frontbuffer_tracking@basic: - fi-cml-u2: [DMESG-WARN][9] ([i915#4269]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11241/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22312/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html [i915#3987]: https://gitlab.freedesktop.org/drm/intel/issues/3987 [i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269 [i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494 [i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547 [i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957 Build changes - * Linux: CI_DRM_11241 -> Patchwork_22312 CI-20190529: 20190529 CI_DRM_11241: cb239fa15d6782735c7b8df0c0a3075947de7eef @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6347: 37ea4c86f97c0e05fcb6b04cff72ec927930536e @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_22312: 6cb610530c8687e9246cca2c3066c0f547d6ba22 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 6cb610530c86 drm/i915/dp: remove accidental static on what should be a local variable == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22312/index.html
Re: [Intel-gfx] [PATCH v5 6/7] drm/i915/gt: Create per-tile RPS sysfs interfaces
Hi Andi,
I love your patch! Yet something to improve:
[auto build test ERROR on drm-tip/drm-tip]
[cannot apply to drm-intel/for-linux-next drm-exynos/exynos-drm-next
drm/drm-next tegra-drm/drm/tegra/for-next airlied/drm-next v5.17-rc4
next-20220217]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Andi-Shyti/Introduce-multitile-support/20220217-224547
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
config: x86_64-randconfig-a011
(https://download.01.org/0day-ci/archive/20220218/202202180224.l042viyj-...@intel.com/config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
#
https://github.com/0day-ci/linux/commit/f1802e7224006bf4801fe56193bf5eb223a3f4d0
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review
Andi-Shyti/Introduce-multitile-support/20220217-224547
git checkout f1802e7224006bf4801fe56193bf5eb223a3f4d0
# save the config file to linux build tree
mkdir build_dir
make W=1 O=build_dir ARCH=x86_64 SHELL=/bin/bash
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot
All errors (new ones prefixed by >>):
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c: In function 'act_freq_mhz_show':
>> drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:250:20: error: implicit
>> declaration of function 'sysfs_gt_attribute_r_func'
>> [-Werror=implicit-function-declaration]
250 | s64 actual_freq = sysfs_gt_attribute_r_func(dev, attr,
|^
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c: In function
'boost_freq_mhz_store':
>> drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:318:9: error: implicit
>> declaration of function 'sysfs_gt_attribute_w_func'
>> [-Werror=implicit-function-declaration]
318 | return sysfs_gt_attribute_w_func(dev, attr,
| ^
cc1: some warnings being treated as errors
vim +/sysfs_gt_attribute_r_func +250 drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
246
247 static ssize_t act_freq_mhz_show(struct device *dev,
248 struct device_attribute *attr, char
*buff)
249 {
> 250 s64 actual_freq = sysfs_gt_attribute_r_func(dev, attr,
251
__act_freq_mhz_show);
252
253 return sysfs_emit(buff, "%u\n", (u32) actual_freq);
254 }
255
256 static s64 __cur_freq_mhz_show(struct intel_gt *gt)
257 {
258 return intel_rps_get_requested_frequency(>rps);
259 }
260
261 static ssize_t cur_freq_mhz_show(struct device *dev,
262 struct device_attribute *attr, char
*buff)
263 {
264 s64 cur_freq = sysfs_gt_attribute_r_func(dev, attr,
265 __cur_freq_mhz_show);
266
267 return sysfs_emit(buff, "%u\n", (u32) cur_freq);
268 }
269
270 static s64 __boost_freq_mhz_show(struct intel_gt *gt)
271 {
272 return intel_rps_get_boost_frequency(>rps);
273 }
274
275 static ssize_t boost_freq_mhz_show(struct device *dev,
276 struct device_attribute *attr,
277 char *buff)
278 {
279 s64 boost_freq = sysfs_gt_attribute_r_func(dev, attr,
280
__boost_freq_mhz_show);
281
282 return sysfs_emit(buff, "%u\n", (u32) boost_freq);
283 }
284
285 static int __boost_freq_mhz_store(struct intel_gt *gt, u32 val)
286 {
287 struct intel_rps *rps = >rps;
288 bool boost = false;
289
290 /* Validate against (static) hardware limits */
291 val = intel_freq_opcode(rps, val);
292 if (val < rps->min_freq || val > rps->max_freq)
293 return -EINVAL;
294
295 mutex_lock(>lock);
296 if (val != rps->boost_freq) {
297 rps->boost_freq = val;
298 boost = atomic_read(>num_waiters);
299 }
300 mutex_unlock(>lock);
301 if (boost)
302 schedule_work(>work);
303
304 return 0;
305 }
306
307 static ssize_t boost_freq_mhz_store(struct device *dev,
308 struct device_attribute *attr,
309 const char *buff, size_t count)
310 {
311 ssize_t ret;
312 u32 val;
313
314
Re: [Intel-gfx] [PATCH 3/3] drm/i915: Fix for PHY_MISC_TC1 offset
On Tue, Feb 15, 2022 at 11:21:54AM +0530, Ramalingam C wrote: From: Jouni Högander Currently ICL_PHY_MISC macro is returning offset 0x64C10 for PHY_E port. Correct offset is 0x64C14. Fix this by handling PHY_E port seprately. order of the patch here is wrong. This patch should come before the patch initializing the 5th port. Then the commit message is not a fix. This can be done while applying since it's more an order to avoid breaking the tree. Lucas De Marchi
Re: [Intel-gfx] [PATCH 2/3] drm/i915/dg2: Drop 38.4 MHz MPLLB tables
On Tue, Feb 15, 2022 at 11:21:53AM +0530, Ramalingam C wrote:
From: Matt Roper
Our early understanding of DG2 was incorrect; since the 5th display
isn't actually a Type-C output, 38.4 MHz input clocks are never used on
this platform and we can drop the corresponding MPLLB tables.
Cc: Anusha Srivatsa
Cc: José Roberto de Souza
Signed-off-by: Matt Roper
Signed-off-by: Ramalingam C
Reviewed-by: Lucas De Marchi
Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_snps_phy.c | 208 +-
1 file changed, 1 insertion(+), 207 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c
b/drivers/gpu/drm/i915/display/intel_snps_phy.c
index 8573a458811a..c60575cb5368 100644
--- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
@@ -250,197 +250,6 @@ static const struct intel_mpllb_state * const
dg2_dp_100_tables[] = {
NULL,
};
-/*
- * Basic DP link rates with 38.4 MHz reference clock.
- */
-
-static const struct intel_mpllb_state dg2_dp_rbr_38_4 = {
- .clock = 162000,
- .ref_control =
- REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
- .mpllb_cp =
- REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 25) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
- .mpllb_div =
- REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),
- .mpllb_div2 =
- REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 304),
- .mpllb_fracn1 =
- REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
- .mpllb_fracn2 =
- REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 49152),
-};
-
-static const struct intel_mpllb_state dg2_dp_hbr1_38_4 = {
- .clock = 27,
- .ref_control =
- REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
- .mpllb_cp =
- REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 25) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
- .mpllb_div =
- REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
- .mpllb_div2 =
- REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 248),
- .mpllb_fracn1 =
- REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
- .mpllb_fracn2 =
- REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 40960),
-};
-
-static const struct intel_mpllb_state dg2_dp_hbr2_38_4 = {
- .clock = 54,
- .ref_control =
- REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
- .mpllb_cp =
- REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 25) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
- .mpllb_div =
- REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
- .mpllb_div2 =
- REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 248),
- .mpllb_fracn1 =
- REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
- .mpllb_fracn2 =
- REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 40960),
-};
-
-static const struct intel_mpllb_state dg2_dp_hbr3_38_4 = {
- .clock = 81,
- .ref_control =
- REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
- .mpllb_cp =
- REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 26) |
- REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65)
Re: [Intel-gfx] [PATCH v5 07/10] drm/i915/guc: Extract GuC error capture lists on G2H notification.
On Sun, Feb 13, 2022 at 11:47:00AM -0800, Teres Alexis, Alan Previn wrote:
Thanks Umesh for reviewing the patch.
Am fixing all the rest but a couple of comments.
Responses to the latter and other questions below:
...alan
> +enum intel_guc_state_capture_event_status {
> + INTEL_GUC_STATE_CAPTURE_EVENT_STATUS_SUCCESS = 0x0,
> + INTEL_GUC_STATE_CAPTURE_EVENT_STATUS_NOSPACE = 0x1,
> +};
> +
> +#define INTEL_GUC_STATE_CAPTURE_EVENT_STATUS_MASK 0x1
MASK is not needed. See below
Alan: Oh wait, actually the mask for the capture status is 0x00FF
(above is a typo). I'll fix above mask and shall not change the
code below because the upper 24 bits of the first dword of this msg
is not defined.
...
> +static int guc_capture_buf_cnt(struct __guc_capture_bufstate *buf)
> +{
> + if (buf->rd == buf->wr)
> + return 0;
> + if (buf->wr > buf->rd)
> + return (buf->wr - buf->rd);
> + return (buf->size - buf->rd) + buf->wr;
> +}
Is this a circular buffer shared between GuC and kmd? Since the size is
a power of 2, the above function is simply:
Alan: not this is not a circular buffer, so I'll keep the above
version.
static u32 guc_capture_buf_count(struct __guc_capture_bufstate *buf)
{
return (buf->wr - buf->rd) & (buf->size - 1);
}
...
> +static int
> +guc_capture_log_remove_dw(struct intel_guc *guc, struct
__guc_capture_bufstate *buf,
> + u32 *dw)
> +{
> + struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
> + int tries = 2;
> + int avail = 0;
> + u32 *src_data;
> +
> + if (!guc_capture_buf_cnt(buf))
> + return 0;
> +
> + while (tries--) {
> + avail = guc_capture_buf_cnt_to_end(buf);
Shouldn't this be avail = guc_capture_buf_cnt(buf)?
Alan : The "guc_capture_log_get_[foo]" functions only call above
guc_capture_log_remove_dw when there isnt sufficient space to
copy out an entire structure from the space between the read pointer
and the end of the subregion (before the wrap-around). Those function
would populate the structure dword by dword by calling above func.
(NOTE the buffer and all error capture output structs are dword
aligned). Thats why above function tries twice and resets buf->rd = 0
if we find no space left at the end of the subregion (i.e. need to
wrap around) - which can only be done by calling
"guc_capture_buf_cnt_to_end".
...
> +
> + /* Bookkeeping stuff */
> + guc->log_state[GUC_CAPTURE_LOG_BUFFER].flush +=
log_buf_state_local.flush_to_file;
> + new_overflow = intel_guc_check_log_buf_overflow(guc,
> +
>log_state[GUC_CAPTURE_LOG_BUFFER],
> + full_count);
I am not sure how the overflow logic works here and whether it is
applicable to the error capture buffer. Is the guc log buffer one big
buffer where the error capture is just a portion of that buffer? If so,
is the wrap around applicable to just the errorcapture buffer or to the
whole buffer?
Alan: Yes, the guc log buffer is one big log buffer but there are 3 independent
subregions within that are populated with different content and are used
in different ways and timings. Each guc-log subregion (general-logs,
crash-dump and error-capture) has it's own read and write pointers.
got it. I would also put this one detail in the commit message since
it's not quickly inferred.
Also what is the wrap_offset field in struct guc_log_buffer_state?
Alan: This is the byte offset of a location in the subregion that is the 1st
byte
after the last valid guc entry written by Guc firmware before a wraparound
was done. This would generate a tiny hole at the end of the subregion for better
cacheline alignment when flushing entries into the subregion. However,
the error-capture subregion is dword aligned and all of the output structures
used for error-capture are also dword aligned so this can never happen for the
error-capture subregion.
Makes sense, thanks for clarifying.
Umesh
[Intel-gfx] [PATCH] drm/i915/guc/slpc: Use wrapper for reading RP_STATE_CAP
This will ensure correct values for Gen12+ platforms.
v2: Rebase
Cc: Matt Roper
Reviewed-by: Matt Roper
Signed-off-by: Vinay Belgaumkar
---
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
index b3d28b003b73..8a473b2f754f 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
@@ -11,6 +11,7 @@
#include "intel_mchbar_regs.h"
#include "gt/intel_gt.h"
#include "gt/intel_gt_regs.h"
+#include "gt/intel_rps.h"
static inline struct intel_guc *slpc_to_guc(struct intel_guc_slpc *slpc)
{
@@ -579,10 +580,10 @@ static int slpc_use_fused_rp0(struct intel_guc_slpc *slpc)
static void slpc_get_rp_values(struct intel_guc_slpc *slpc)
{
+ struct intel_rps *rps = _to_gt(slpc)->rps;
u32 rp_state_cap;
- rp_state_cap = intel_uncore_read(slpc_to_gt(slpc)->uncore,
-GEN6_RP_STATE_CAP);
+ rp_state_cap = intel_rps_read_state_cap(rps);
slpc->rp0_freq = REG_FIELD_GET(RP0_CAP_MASK, rp_state_cap) *
GT_FREQUENCY_MULTIPLIER;
--
2.34.0
[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Fix cursor coordinates on bigjoiner slave (rev2)
== Series Details == Series: drm/i915: Fix cursor coordinates on bigjoiner slave (rev2) URL : https://patchwork.freedesktop.org/series/100154/ State : failure == Summary == CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh DESCEND objtool CHK include/generated/compile.h CC [M] drivers/gpu/drm/i915/display/intel_cursor.o drivers/gpu/drm/i915/display/intel_cursor.c: In function ‘intel_check_cursor’: drivers/gpu/drm/i915/display/intel_cursor.c:155:18: error: ‘struct intel_crtc_state’ has no member named ‘bigjoiner_slave’; did you mean ‘bigjoiner_pipes’? if (crtc_state->bigjoiner_slave) ^~~ bigjoiner_pipes scripts/Makefile.build:288: recipe for target 'drivers/gpu/drm/i915/display/intel_cursor.o' failed make[4]: *** [drivers/gpu/drm/i915/display/intel_cursor.o] Error 1 scripts/Makefile.build:550: recipe for target 'drivers/gpu/drm/i915' failed make[3]: *** [drivers/gpu/drm/i915] Error 2 scripts/Makefile.build:550: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:550: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:1831: recipe for target 'drivers' failed make: *** [drivers] Error 2
Re: [Intel-gfx] [PATCH] drm/i915/perf: Skip the i915_perf_init for dg2
On Tue, Feb 15, 2022 at 11:01:15AM +0530, Ramalingam C wrote:
i915_perf is not enabled for dg2 yet, hence skip the feature
initialization.
Signed-off-by: Ramalingam C
cc: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_perf.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 36f1325baa7d..5ac9604d07b3 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -4373,6 +4373,10 @@ void i915_perf_init(struct drm_i915_private *i915)
/* XXX const struct i915_perf_ops! */
+ /* i915_perf is not enabled for DG2 yet */
+ if (IS_DG2(i915))
+ return;
+
lgtm
Reviewed-by: Umesh Nerlige Ramappa
Thanks,
Umesh
perf->oa_formats = oa_formats;
if (IS_HASWELL(i915)) {
perf->ops.is_valid_b_counter_reg = gen7_is_valid_b_counter_addr;
--
2.20.1
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/mm: Add an iterator to optimally walk over holes suitable for an allocation (rev2)
== Series Details ==
Series: drm/mm: Add an iterator to optimally walk over holes suitable for an
allocation (rev2)
URL : https://patchwork.freedesktop.org/series/100136/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11241 -> Patchwork_22310
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22310/index.html
Participating hosts (46 -> 43)
--
Additional (1): fi-pnv-d510
Missing(4): fi-kbl-soraka bat-dg2-8 shard-tglu fi-bsw-cyan
Known issues
Here are the changes found in Patchwork_22310 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_huc_copy@huc-copy:
- fi-skl-6600u: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#2190])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22310/fi-skl-6600u/igt@gem_huc_c...@huc-copy.html
- fi-pnv-d510:NOTRUN -> [SKIP][2] ([fdo#109271]) +57 similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22310/fi-pnv-d510/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@verify-random:
- fi-skl-6600u: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4613]) +3
similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22310/fi-skl-6600u/igt@gem_lmem_swapp...@verify-random.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: [PASS][4] -> [DMESG-FAIL][5] ([i915#4494] /
[i915#4957])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11241/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22310/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
- bat-dg1-5: [PASS][6] -> [DMESG-FAIL][7] ([i915#4494] /
[i915#4957])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11241/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22310/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@late_gt_pm:
- fi-bsw-n3050: [PASS][8] -> [DMESG-FAIL][9] ([i915#2927] /
[i915#3428])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11241/fi-bsw-n3050/igt@i915_selftest@live@late_gt_pm.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22310/fi-bsw-n3050/igt@i915_selftest@live@late_gt_pm.html
* igt@kms_chamelium@vga-edid-read:
- fi-skl-6600u: NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) +8
similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22310/fi-skl-6600u/igt@kms_chamel...@vga-edid-read.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-skl-6600u: NOTRUN -> [SKIP][11] ([fdo#109271]) +2 similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22310/fi-skl-6600u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-skl-6600u: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#533])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22310/fi-skl-6600u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
* igt@kms_psr@primary_page_flip:
- fi-skl-6600u: NOTRUN -> [FAIL][13] ([i915#4547])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22310/fi-skl-6600u/igt@kms_psr@primary_page_flip.html
* igt@runner@aborted:
- fi-bsw-n3050: NOTRUN -> [FAIL][14] ([fdo#109271] / [i915#1436] /
[i915#3428] / [i915#4312])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22310/fi-bsw-n3050/igt@run...@aborted.html
- fi-bdw-5557u: NOTRUN -> [FAIL][15] ([i915#2426] / [i915#4312])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22310/fi-bdw-5557u/igt@run...@aborted.html
Possible fixes
* igt@gem_exec_suspend@basic-s3@smem:
- fi-bdw-5557u: [INCOMPLETE][16] ([i915#146]) -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11241/fi-bdw-5557u/igt@gem_exec_suspend@basic...@smem.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22310/fi-bdw-5557u/igt@gem_exec_suspend@basic...@smem.html
* igt@gem_flink_basic@bad-flink:
- fi-skl-6600u: [FAIL][18] ([i915#4547]) -> [PASS][19]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11241/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22310/fi-skl-6600u/igt@gem_flink_ba...@bad-flink.html
* igt@i915_selftest@live@gt_pm:
- fi-tgl-1115g4: [DMESG-FAIL][20] ([i915#3987]) -> [PASS][21]
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11241/fi-tgl-1115g4/igt@i915_selftest@live@gt_pm.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22310/fi-tgl-1115g4/igt@i915_selftest@live@gt_pm.html
{name}: This element is suppressed. This means it is ignored when
Re: [Intel-gfx] [PATCH] drm/i915/guc/slpc: Correct the param count for unset param
On Wed, Feb 16, 2022 at 10:15:04AM -0800, Vinay Belgaumkar wrote:
SLPC unset param H2G only needs one parameter - the id of the
param.
Fixes: 025cb07bebfa ("drm/i915/guc/slpc: Cache platform frequency limits")
Suggested-by: Umesh Nerlige Ramappa
Signed-off-by: Vinay Belgaumkar
---
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
index 13b27b8ff74e..ba21ace973da 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
@@ -110,7 +110,7 @@ static int guc_action_slpc_unset_param(struct intel_guc
*guc, u8 id)
{
u32 request[] = {
GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST,
- SLPC_EVENT(SLPC_EVENT_PARAMETER_UNSET, 2),
+ SLPC_EVENT(SLPC_EVENT_PARAMETER_UNSET, 1),
lgtm,
Reviewed-by: Umesh Nerlige Ramappa
Thanks,
Umesh
id,
};
--
2.34.0
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/mm: Add an iterator to optimally walk over holes suitable for an allocation (rev2)
== Series Details == Series: drm/mm: Add an iterator to optimally walk over holes suitable for an allocation (rev2) URL : https://patchwork.freedesktop.org/series/100136/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/mm: Add an iterator to optimally walk over holes suitable for an allocation (rev2)
== Series Details == Series: drm/mm: Add an iterator to optimally walk over holes suitable for an allocation (rev2) URL : https://patchwork.freedesktop.org/series/100136/ State : warning == Summary == $ dim checkpatch origin/drm-tip 19844014c61e drm/mm: Ensure that the entry is not NULL before extracting rb_node f5597ffa1e23 drm/mm: Add an iterator to optimally walk over holes for an allocation (v4) -:153: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pos' - possible side-effects? #153: FILE: include/drm/drm_mm.h:430: +#define drm_mm_for_each_suitable_hole(pos, mm, range_start, range_end, \ + size, mode) \ + for (pos = __drm_mm_first_hole(mm, range_start, range_end, size, \ + mode & ~DRM_MM_INSERT_ONCE); \ +pos; \ +pos = mode & DRM_MM_INSERT_ONCE ? \ +NULL : __drm_mm_next_hole(mm, pos, size, \ + mode & ~DRM_MM_INSERT_ONCE)) -:153: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'mm' - possible side-effects? #153: FILE: include/drm/drm_mm.h:430: +#define drm_mm_for_each_suitable_hole(pos, mm, range_start, range_end, \ + size, mode) \ + for (pos = __drm_mm_first_hole(mm, range_start, range_end, size, \ + mode & ~DRM_MM_INSERT_ONCE); \ +pos; \ +pos = mode & DRM_MM_INSERT_ONCE ? \ +NULL : __drm_mm_next_hole(mm, pos, size, \ + mode & ~DRM_MM_INSERT_ONCE)) -:153: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'size' - possible side-effects? #153: FILE: include/drm/drm_mm.h:430: +#define drm_mm_for_each_suitable_hole(pos, mm, range_start, range_end, \ + size, mode) \ + for (pos = __drm_mm_first_hole(mm, range_start, range_end, size, \ + mode & ~DRM_MM_INSERT_ONCE); \ +pos; \ +pos = mode & DRM_MM_INSERT_ONCE ? \ +NULL : __drm_mm_next_hole(mm, pos, size, \ + mode & ~DRM_MM_INSERT_ONCE)) -:153: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'mode' - possible side-effects? #153: FILE: include/drm/drm_mm.h:430: +#define drm_mm_for_each_suitable_hole(pos, mm, range_start, range_end, \ + size, mode) \ + for (pos = __drm_mm_first_hole(mm, range_start, range_end, size, \ + mode & ~DRM_MM_INSERT_ONCE); \ +pos; \ +pos = mode & DRM_MM_INSERT_ONCE ? \ +NULL : __drm_mm_next_hole(mm, pos, size, \ + mode & ~DRM_MM_INSERT_ONCE)) -:153: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'mode' may be better as '(mode)' to avoid precedence issues #153: FILE: include/drm/drm_mm.h:430: +#define drm_mm_for_each_suitable_hole(pos, mm, range_start, range_end, \ + size, mode) \ + for (pos = __drm_mm_first_hole(mm, range_start, range_end, size, \ + mode & ~DRM_MM_INSERT_ONCE); \ +pos; \ +pos = mode & DRM_MM_INSERT_ONCE ? \ +NULL : __drm_mm_next_hole(mm, pos, size, \ + mode & ~DRM_MM_INSERT_ONCE)) total: 0 errors, 0 warnings, 5 checks, 114 lines checked 116d1b29f884 drm/i915/gem: Don't try to map and fence large scanout buffers (v8)
[Intel-gfx] ✗ Fi.CI.BAT: failure for use dynamic-debug under drm.debug api
== Series Details ==
Series: use dynamic-debug under drm.debug api
URL : https://patchwork.freedesktop.org/series/100289/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11241 -> Patchwork_22308
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_22308 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22308, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22308/index.html
Participating hosts (46 -> 42)
--
Missing(4): fi-bsw-cyan bat-dg2-8 shard-tglu fi-kbl-8809g
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_22308:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live@workarounds:
- fi-rkl-guc: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11241/fi-rkl-guc/igt@i915_selftest@l...@workarounds.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22308/fi-rkl-guc/igt@i915_selftest@l...@workarounds.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_parallel@engines@userptr:
- {bat-adlp-6}: [PASS][3] -> [INCOMPLETE][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11241/bat-adlp-6/igt@gem_exec_parallel@engi...@userptr.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22308/bat-adlp-6/igt@gem_exec_parallel@engi...@userptr.html
Known issues
Here are the changes found in Patchwork_22308 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@cs-gfx:
- fi-kbl-soraka: NOTRUN -> [SKIP][5] ([fdo#109271]) +17 similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22308/fi-kbl-soraka/igt@amdgpu/amd_ba...@cs-gfx.html
* igt@gem_exec_suspend@basic-s3@smem:
- fi-skl-6600u: [PASS][6] -> [INCOMPLETE][7] ([i915#4547])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11241/fi-skl-6600u/igt@gem_exec_suspend@basic...@smem.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22308/fi-skl-6600u/igt@gem_exec_suspend@basic...@smem.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: [PASS][8] -> [DMESG-FAIL][9] ([i915#4494] /
[i915#4957])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11241/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22308/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
- bat-dg1-5: [PASS][10] -> [DMESG-FAIL][11] ([i915#4494] /
[i915#4957])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11241/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22308/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
Possible fixes
* igt@i915_selftest@live@gt_pm:
- fi-tgl-1115g4: [DMESG-FAIL][12] ([i915#3987]) -> [PASS][13]
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11241/fi-tgl-1115g4/igt@i915_selftest@live@gt_pm.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22308/fi-tgl-1115g4/igt@i915_selftest@live@gt_pm.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [DMESG-WARN][14] ([i915#4269]) -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11241/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22308/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#3987]: https://gitlab.freedesktop.org/drm/intel/issues/3987
[i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
Build changes
-
* Linux: CI_DRM_11241 -> Patchwork_22308
CI-20190529: 20190529
CI_DRM_11241: cb239fa15d6782735c7b8df0c0a3075947de7eef @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6347: 37ea4c86f97c0e05fcb6b04cff72ec927930536e @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22308: 5b2b6e5fdbad06a580282410c14253a686e34dc4 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
5b2b6e5fdbad drm_print: use DEFINE_DYNAMIC_DEBUG_CLASSBITS for drm.debug
39bbb4f0f2da
[Intel-gfx] [PATCH v2 1/3] drm/i915/dg2: Enable 5th port
From: Matt Roper
DG2 supports a 5th display output which the hardware refers to as "TC1,"
even though it isn't a Type-C output. This behaves similarly to the TC1
on past platforms with just a couple minor differences:
* DG2's TC1 bit in SDEISR is at bit 25 rather than 24 as it is on
ICP/TGP/ADP.
* DG2 doesn't need the hpd inversion setting that we had to use on DG1
v2:
intel_ddi_init(dev_priv, PORT_TC1); [Matt]
Cc: Swathi Dhanavanthri
Cc: Lucas De Marchi
Cc: José Roberto de Souza
Signed-off-by: Matt Roper
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/display/intel_display.c | 1 +
drivers/gpu/drm/i915/display/intel_gmbus.c | 16 ++--
drivers/gpu/drm/i915/i915_irq.c | 5 -
drivers/gpu/drm/i915/i915_reg.h | 1 +
4 files changed, 20 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 59961621fe4a..18531ffd4789 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8760,6 +8760,7 @@ static void intel_setup_outputs(struct drm_i915_private
*dev_priv)
intel_ddi_init(dev_priv, PORT_B);
intel_ddi_init(dev_priv, PORT_C);
intel_ddi_init(dev_priv, PORT_D_XELPD);
+ intel_ddi_init(dev_priv, PORT_TC1);
} else if (IS_ALDERLAKE_P(dev_priv)) {
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c
b/drivers/gpu/drm/i915/display/intel_gmbus.c
index 6ce8c10fe975..2fad03250661 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -98,11 +98,21 @@ static const struct gmbus_pin gmbus_pins_dg1[] = {
[GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
};
+static const struct gmbus_pin gmbus_pins_dg2[] = {
+ [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
+ [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
+ [GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
+ [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
+ [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
+};
+
/* pin is expected to be valid */
static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
unsigned int pin)
{
- if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG2)
+ return _pins_dg2[pin];
+ else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
return _pins_dg1[pin];
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
return _pins_icp[pin];
@@ -123,7 +133,9 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private
*dev_priv,
{
unsigned int size;
- if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG2)
+ size = ARRAY_SIZE(gmbus_pins_dg2);
+ else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
size = ARRAY_SIZE(gmbus_pins_dg1);
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
size = ARRAY_SIZE(gmbus_pins_icp);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index fdd568ba4a16..4d81063b128c 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -179,6 +179,7 @@ static const u32 hpd_sde_dg1[HPD_NUM_PINS] = {
[HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
[HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C),
[HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_D),
+ [HPD_PORT_TC1] = SDE_TC_HOTPLUG_DG2(HPD_PORT_TC1),
};
static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
@@ -4424,7 +4425,9 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
if (I915_HAS_HOTPLUG(dev_priv))
dev_priv->hotplug_funcs = _hpd_funcs;
} else {
- if (HAS_PCH_DG1(dev_priv))
+ if (HAS_PCH_DG2(dev_priv))
+ dev_priv->hotplug_funcs = _hpd_funcs;
+ else if (HAS_PCH_DG1(dev_priv))
dev_priv->hotplug_funcs = _hpd_funcs;
else if (DISPLAY_VER(dev_priv) >= 11)
dev_priv->hotplug_funcs = _hpd_funcs;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2243d9d1d941..b5acbbcc8574 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6065,6 +6065,7 @@
/* south display engine interrupt: ICP/TGP */
#define SDE_GMBUS_ICP (1 << 23)
#define SDE_TC_HOTPLUG_ICP(hpd_pin)REG_BIT(24 + _HPD_PIN_TC(hpd_pin))
+#define SDE_TC_HOTPLUG_DG2(hpd_pin)REG_BIT(25 + _HPD_PIN_TC(hpd_pin)) /*
sigh */
#define SDE_DDI_HOTPLUG_ICP(hpd_pin) REG_BIT(16 + _HPD_PIN_DDI(hpd_pin))
#define SDE_DDI_HOTPLUG_MASK_ICP (SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \
[Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/4] drm/i915/dsi: disassociate VBT video transfer mode from register values (rev2)
== Series Details == Series: series starting with [1/4] drm/i915/dsi: disassociate VBT video transfer mode from register values (rev2) URL : https://patchwork.freedesktop.org/series/100249/ State : failure == Summary == Applying: drm/i915/dsi: disassociate VBT video transfer mode from register values Applying: drm/i915/dsi: add separate init timer mask definition for ICL DSI Applying: drm/i915/reg: split out vlv_dsi_regs.h and vlv_dsi_pll_regs.h error: sha1 information is lacking or useless (drivers/gpu/drm/i915/i915_reg.h). error: could not build fake ancestor hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0003 drm/i915/reg: split out vlv_dsi_regs.h and vlv_dsi_pll_regs.h When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".
Re: [Intel-gfx] [PATCH v2 6/6] drm/i915: Extract intel_bw_check_data_rate()
On Wed, Feb 16, 2022 at 07:42:50PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Extract the data rate calculation loop out from
> intel_bw_atomic_check() to make it a bit less confusing.
>
> Cc: Stanislav Lisovskiy
> Signed-off-by: Ville Syrjälä
Reviewed-by: Stanislav Lisovskiy
> ---
> drivers/gpu/drm/i915/display/intel_bw.c | 63 +++--
> 1 file changed, 37 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> b/drivers/gpu/drm/i915/display/intel_bw.c
> index fa03f0935b6d..963b99d3557c 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -835,31 +835,12 @@ static u16 icl_qgv_points_mask(struct drm_i915_private
> *i915)
> return mask;
> }
>
> -int intel_bw_atomic_check(struct intel_atomic_state *state)
> +static int intel_bw_check_data_rate(struct intel_atomic_state *state)
> {
> - struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> - struct intel_crtc_state *new_crtc_state, *old_crtc_state;
> - struct intel_bw_state *new_bw_state = NULL;
> - const struct intel_bw_state *old_bw_state = NULL;
> - unsigned int data_rate;
> - unsigned int num_active_planes;
> + struct drm_i915_private *i915 = to_i915(state->base.dev);
> + const struct intel_crtc_state *new_crtc_state, *old_crtc_state;
> struct intel_crtc *crtc;
> - int i, ret;
> - u32 allowed_points = 0;
> - unsigned int max_bw_point = 0, max_bw = 0;
> - unsigned int num_qgv_points = dev_priv->max_bw[0].num_qgv_points;
> - unsigned int num_psf_gv_points = dev_priv->max_bw[0].num_psf_gv_points;
> -
> - /* FIXME earlier gens need some checks too */
> - if (DISPLAY_VER(dev_priv) < 11)
> - return 0;
> -
> - /*
> - * If we already have the bw state then recompute everything
> - * even if pipe data_rate / active_planes didn't change.
> - * Other things (such as SAGV) may have changed.
> - */
> - new_bw_state = intel_atomic_get_new_bw_state(state);
> + int i;
>
> for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> new_crtc_state, i) {
> @@ -871,6 +852,7 @@ int intel_bw_atomic_check(struct intel_atomic_state
> *state)
> intel_bw_crtc_num_active_planes(old_crtc_state);
> unsigned int new_active_planes =
> intel_bw_crtc_num_active_planes(new_crtc_state);
> + struct intel_bw_state *new_bw_state;
>
> /*
>* Avoid locking the bw state when
> @@ -887,13 +869,42 @@ int intel_bw_atomic_check(struct intel_atomic_state
> *state)
> new_bw_state->data_rate[crtc->pipe] = new_data_rate;
> new_bw_state->num_active_planes[crtc->pipe] = new_active_planes;
>
> - drm_dbg_kms(_priv->drm,
> - "pipe %c data rate %u num active planes %u\n",
> - pipe_name(crtc->pipe),
> + drm_dbg_kms(>drm,
> + "[CRTC:%d:%s] data rate %u num active planes %u\n",
> + crtc->base.base.id, crtc->base.name,
> new_bw_state->data_rate[crtc->pipe],
> new_bw_state->num_active_planes[crtc->pipe]);
> }
>
> + return 0;
> +}
> +
> +int intel_bw_atomic_check(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + const struct intel_bw_state *old_bw_state;
> + struct intel_bw_state *new_bw_state;
> + unsigned int data_rate;
> + unsigned int num_active_planes;
> + int i, ret;
> + u32 allowed_points = 0;
> + unsigned int max_bw_point = 0, max_bw = 0;
> + unsigned int num_qgv_points = dev_priv->max_bw[0].num_qgv_points;
> + unsigned int num_psf_gv_points = dev_priv->max_bw[0].num_psf_gv_points;
> +
> + /* FIXME earlier gens need some checks too */
> + if (DISPLAY_VER(dev_priv) < 11)
> + return 0;
> +
> + ret = intel_bw_check_data_rate(state);
> + if (ret)
> + return ret;
> +
> + /*
> + * If we don't have a bw_state by now then none of the
> + * inputs to the QGV mask computation may have changed.
> + */
> + new_bw_state = intel_atomic_get_new_bw_state(state);
> if (!new_bw_state)
> return 0;
>
> --
> 2.34.1
>
