[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Support Async Flip on Linear buffers (rev4)
== Series Details == Series: drm/i915: Support Async Flip on Linear buffers (rev4) URL : https://patchwork.freedesktop.org/series/103137/ State : failure == Summary == CI Bug Log - changes from CI_DRM_12074_full -> Patchwork_103137v4_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_103137v4_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_103137v4_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (12 -> 12) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_103137v4_full: ### IGT changes ### Possible regressions * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt: - shard-tglb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12074/shard-tglb1/igt@kms_frontbuffer_track...@fbc-1p-primscrn-pri-indfb-draw-blt.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103137v4/shard-tglb6/igt@kms_frontbuffer_track...@fbc-1p-primscrn-pri-indfb-draw-blt.html Known issues Here are the changes found in Patchwork_103137v4_full that come from known issues: ### CI changes ### Possible fixes * boot: - shard-apl: ([PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [FAIL][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27]) ([i915#4386]) -> ([PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51], [PASS][52]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12074/shard-apl3/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12074/shard-apl3/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12074/shard-apl3/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12074/shard-apl4/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12074/shard-apl4/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12074/shard-apl4/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12074/shard-apl4/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12074/shard-apl6/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12074/shard-apl6/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12074/shard-apl6/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12074/shard-apl6/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12074/shard-apl7/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12074/shard-apl7/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12074/shard-apl8/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12074/shard-apl8/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12074/shard-apl1/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12074/shard-apl1/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12074/shard-apl1/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12074/shard-apl1/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12074/shard-apl2/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12074/shard-apl2/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12074/shard-apl2/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12074/shard-apl2/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12074/shard-apl7/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12074/shard-apl3/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103137v4/shard-apl8/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103137v4/shard-apl8/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103137v4/shard-apl8/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103137v4/shard-apl7/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103137v4/shard-apl7/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103137v4/shard-apl7/boot.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103137v4/shard-apl7/boot.html [35]:
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Support Async Flip on Linear buffers (rev5)
== Series Details ==
Series: drm/i915: Support Async Flip on Linear buffers (rev5)
URL : https://patchwork.freedesktop.org/series/103137/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12074 -> Patchwork_103137v5
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103137v5/index.html
Participating hosts (44 -> 43)
--
Additional (1): fi-icl-u2
Missing(2): fi-cml-u2 fi-bdw-samus
Known issues
Here are the changes found in Patchwork_103137v5 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_huc_copy@huc-copy:
- fi-icl-u2: NOTRUN -> [SKIP][1] ([i915#2190])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103137v5/fi-icl-u2/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@random-engines:
- fi-icl-u2: NOTRUN -> [SKIP][2] ([i915#4613]) +3 similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103137v5/fi-icl-u2/igt@gem_lmem_swapp...@random-engines.html
* igt@i915_selftest@live@gem:
- fi-blb-e6850: [PASS][3] -> [DMESG-FAIL][4] ([i915#4528])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12074/fi-blb-e6850/igt@i915_selftest@l...@gem.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103137v5/fi-blb-e6850/igt@i915_selftest@l...@gem.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[PASS][5] -> [INCOMPLETE][6] ([i915#4785])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12074/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103137v5/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-bdw-5557u: [PASS][7] -> [INCOMPLETE][8] ([i915#146] /
[i915#6598] / [i915#6712])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12074/fi-bdw-5557u/igt@i915_susp...@basic-s3-without-i915.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103137v5/fi-bdw-5557u/igt@i915_susp...@basic-s3-without-i915.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: NOTRUN -> [SKIP][9] ([fdo#111827]) +8 similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103137v5/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor:
- fi-icl-u2: NOTRUN -> [SKIP][10] ([i915#4103])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103137v5/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html
* igt@kms_force_connector_basic@force-connector-state:
- fi-icl-u2: NOTRUN -> [WARN][11] ([i915#6008])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103137v5/fi-icl-u2/igt@kms_force_connector_ba...@force-connector-state.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-icl-u2: NOTRUN -> [SKIP][12] ([fdo#109285])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103137v5/fi-icl-u2/igt@kms_force_connector_ba...@force-load-detect.html
* igt@kms_setmode@basic-clone-single-crtc:
- fi-icl-u2: NOTRUN -> [SKIP][13] ([i915#3555])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103137v5/fi-icl-u2/igt@kms_setm...@basic-clone-single-crtc.html
* igt@prime_vgem@basic-userptr:
- fi-icl-u2: NOTRUN -> [SKIP][14] ([fdo#109295] / [i915#3301])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103137v5/fi-icl-u2/igt@prime_v...@basic-userptr.html
* igt@runner@aborted:
- fi-hsw-4770:NOTRUN -> [FAIL][15] ([fdo#109271] / [i915#4312] /
[i915#5594] / [i915#6246])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103137v5/fi-hsw-4770/igt@run...@aborted.html
- fi-blb-e6850: NOTRUN -> [FAIL][16] ([fdo#109271] / [i915#2403] /
[i915#4312])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103137v5/fi-blb-e6850/igt@run...@aborted.html
Possible fixes
* igt@i915_selftest@live@gt_lrc:
- {bat-dg2-8}:[INCOMPLETE][17] ([i915#6580]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12074/bat-dg2-8/igt@i915_selftest@live@gt_lrc.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103137v5/bat-dg2-8/igt@i915_selftest@live@gt_lrc.html
* igt@i915_selftest@live@hangcheck:
- {fi-jsl-1}: [INCOMPLETE][19] ([i915#5134]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12074/fi-jsl-1/igt@i915_selftest@l...@hangcheck.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103137v5/fi-jsl-1/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@requests:
- {bat-rplp-1}: [INCOMPLETE][21] ([i915#6690]) -> [PASS][22]
[21]:
[Intel-gfx] [PATCHv3] drm/i915: Support Async Flip on Linear buffers
Starting from Gen12 Async Flip is supported on linear buffers.
This patch enables support for async on linear buffer.
UseCase: In Hybrid graphics, for hardware unsupported pixel formats it
will be converted to linear memory and then composed.
v2: Added use case
v3: Added FIXME for ICL indicating the restrictions
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_display.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index be7cff722196..f0d2c3cb3bd5 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6610,6 +6610,20 @@ static int intel_async_flip_check_hw(struct
intel_atomic_state *state, struct in
* this selectively if required.
*/
switch (new_plane_state->hw.fb->modifier) {
+ case DRM_FORMAT_MOD_LINEAR:
+ /*
+* FIXME: Async on Linear buffer is supported on ICL as
+* but with additional alignment and fbc restrictions
+* need to be taken care of. These aren't applicable for
+* gen12+.
+*/
+ if (DISPLAY_VER(i915) < 12) {
+ drm_dbg_kms(>drm,
+ "[PLANE:%d:%s] Modifier does not
support async flips\n",
+ plane->base.base.id,
plane->base.name);
+ return -EINVAL;
+ }
+
case I915_FORMAT_MOD_X_TILED:
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Yf_TILED:
--
2.25.1
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Support Async Flip on Linear buffers (rev4)
== Series Details == Series: drm/i915: Support Async Flip on Linear buffers (rev4) URL : https://patchwork.freedesktop.org/series/103137/ State : success == Summary == CI Bug Log - changes from CI_DRM_12074 -> Patchwork_103137v4 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103137v4/index.html Participating hosts (44 -> 42) -- Additional (1): fi-icl-u2 Missing(3): fi-kbl-soraka fi-blb-e6850 fi-bdw-samus Known issues Here are the changes found in Patchwork_103137v4 that come from known issues: ### IGT changes ### Issues hit * igt@gem_huc_copy@huc-copy: - fi-icl-u2: NOTRUN -> [SKIP][1] ([i915#2190]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103137v4/fi-icl-u2/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@random-engines: - fi-icl-u2: NOTRUN -> [SKIP][2] ([i915#4613]) +3 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103137v4/fi-icl-u2/igt@gem_lmem_swapp...@random-engines.html * igt@i915_selftest@live@gt_engines: - bat-dg1-5: [PASS][3] -> [INCOMPLETE][4] ([i915#4418]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12074/bat-dg1-5/igt@i915_selftest@live@gt_engines.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103137v4/bat-dg1-5/igt@i915_selftest@live@gt_engines.html * igt@i915_selftest@live@gt_heartbeat: - fi-bdw-5557u: [PASS][5] -> [DMESG-FAIL][6] ([i915#5334]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12074/fi-bdw-5557u/igt@i915_selftest@live@gt_heartbeat.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103137v4/fi-bdw-5557u/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@hangcheck: - fi-hsw-g3258: [PASS][7] -> [INCOMPLETE][8] ([i915#3303] / [i915#4785]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12074/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103137v4/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-pnv-d510:NOTRUN -> [SKIP][9] ([fdo#109271]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103137v4/fi-pnv-d510/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-icl-u2: NOTRUN -> [SKIP][10] ([fdo#111827]) +8 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103137v4/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor: - fi-icl-u2: NOTRUN -> [SKIP][11] ([i915#4103]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103137v4/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size: - fi-bsw-kefka: [PASS][12] -> [FAIL][13] ([i915#6298]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12074/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions-varying-size.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103137v4/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions-varying-size.html * igt@kms_force_connector_basic@force-connector-state: - fi-icl-u2: NOTRUN -> [WARN][14] ([i915#6008]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103137v4/fi-icl-u2/igt@kms_force_connector_ba...@force-connector-state.html * igt@kms_force_connector_basic@force-load-detect: - fi-icl-u2: NOTRUN -> [SKIP][15] ([fdo#109285]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103137v4/fi-icl-u2/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_frontbuffer_tracking@basic: - fi-cml-u2: [PASS][16] -> [DMESG-WARN][17] ([i915#402]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12074/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103137v4/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html * igt@kms_setmode@basic-clone-single-crtc: - fi-icl-u2: NOTRUN -> [SKIP][18] ([i915#3555]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103137v4/fi-icl-u2/igt@kms_setm...@basic-clone-single-crtc.html * igt@prime_vgem@basic-userptr: - fi-icl-u2: NOTRUN -> [SKIP][19] ([fdo#109295] / [i915#3301]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103137v4/fi-icl-u2/igt@prime_v...@basic-userptr.html * igt@runner@aborted: - fi-hsw-g3258: NOTRUN -> [FAIL][20] ([fdo#109271] / [i915#4312] / [i915#6246]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103137v4/fi-hsw-g3258/igt@run...@aborted.html Possible
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Support Async Flip on Linear buffers (rev4)
== Series Details == Series: drm/i915: Support Async Flip on Linear buffers (rev4) URL : https://patchwork.freedesktop.org/series/103137/ State : warning == Summary == Error: dim checkpatch failed 2efff2608792 drm/i915: Support Async Flip on Linear buffers -:34: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #34: FILE: drivers/gpu/drm/i915/display/intel_display.c:6622: + drm_dbg_kms(>drm, + "[PLANE:%d:%s] Modifier does not support async flips\n", total: 0 errors, 0 warnings, 1 checks, 20 lines checked
[Intel-gfx] [PATCHv3] drm/i915: Support Async Flip on Linear buffers
Starting from Gen12 Async Flip is supported on linear buffers.
This patch enables support for async on linear buffer.
UseCase: In Hybrid graphics, for hardware unsupported pixel formats it
will be converted to linear memory and then composed.
v2: Added use case
v3: Added FIXME for ICL indicating the restrictions
Signed-off-by: Arun R Murthy
---
drivers/gpu/drm/i915/display/intel_display.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index be7cff722196..1880cfe70a7d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6610,6 +6610,20 @@ static int intel_async_flip_check_hw(struct
intel_atomic_state *state, struct in
* this selectively if required.
*/
switch (new_plane_state->hw.fb->modifier) {
+ case DRM_FORMAT_MOD_LINEAR:
+ /*
+* FIXME: Async on Linear buffer is supported on ICL as
+* but with additional alignment and fbc restrictions
+* need to be taken care of. These aren't applicable for
+* gen12+.
+*/
+ if (DISPLAY_VER(i915) < 12) {
+ drm_dbg_kms(>drm,
+ "[PLANE:%d:%s] Modifier does not
support async flips\n",
+ plane->base.base.id, plane->base.name);
+ return -EINVAL;
+ }
+
case I915_FORMAT_MOD_X_TILED:
case I915_FORMAT_MOD_Y_TILED:
case I915_FORMAT_MOD_Yf_TILED:
--
2.25.1
[Intel-gfx] ✓ Fi.CI.IGT: success for i915: CAGF and RC6 changes for MTL (rev2)
== Series Details ==
Series: i915: CAGF and RC6 changes for MTL (rev2)
URL : https://patchwork.freedesktop.org/series/108156/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12073_full -> Patchwork_108156v2_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (10 -> 12)
--
Additional (2): shard-rkl shard-tglu
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_108156v2_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@kms_plane_multiple@tiling-4}:
- {shard-tglu}: NOTRUN -> [SKIP][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v2/shard-tglu-4/igt@kms_plane_multi...@tiling-4.html
Known issues
Here are the changes found in Patchwork_108156v2_full that come from known
issues:
### CI changes ###
Possible fixes
* boot:
- shard-glk: ([PASS][2], [PASS][3], [PASS][4], [PASS][5],
[PASS][6], [PASS][7], [PASS][8], [FAIL][9], [PASS][10], [PASS][11], [PASS][12],
[PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18],
[PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24],
[PASS][25]) ([i915#4392]) -> ([PASS][26], [PASS][27], [PASS][28], [PASS][29],
[PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35],
[PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41],
[PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47],
[PASS][48], [PASS][49], [PASS][50])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk9/boot.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk9/boot.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk9/boot.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk1/boot.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk1/boot.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk1/boot.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk2/boot.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk2/boot.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk2/boot.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk3/boot.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk3/boot.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk3/boot.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk5/boot.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk5/boot.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk5/boot.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk6/boot.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk6/boot.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk6/boot.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk7/boot.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk7/boot.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk7/boot.html
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk8/boot.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk8/boot.html
[25]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk8/boot.html
[26]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v2/shard-glk9/boot.html
[27]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v2/shard-glk9/boot.html
[28]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v2/shard-glk9/boot.html
[29]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v2/shard-glk8/boot.html
[30]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v2/shard-glk8/boot.html
[31]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v2/shard-glk8/boot.html
[32]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v2/shard-glk7/boot.html
[33]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v2/shard-glk7/boot.html
[34]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v2/shard-glk7/boot.html
[35]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v2/shard-glk6/boot.html
[36]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v2/shard-glk6/boot.html
[37]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v2/shard-glk6/boot.html
[38]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v2/shard-glk5/boot.html
[39]:
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: ipc and display sub-struct refactoring
== Series Details ==
Series: drm/i915: ipc and display sub-struct refactoring
URL : https://patchwork.freedesktop.org/series/108157/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12073_full -> Patchwork_108157v1_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (10 -> 12)
--
Additional (2): shard-rkl shard-tglu
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_108157v1_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@kms_plane_multiple@tiling-4}:
- {shard-tglu}: NOTRUN -> [SKIP][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108157v1/shard-tglu-6/igt@kms_plane_multi...@tiling-4.html
New tests
-
New tests have been introduced between CI_DRM_12073_full and
Patchwork_108157v1_full:
### New IGT tests (1) ###
* igt@kms_plane_multiple@tiling-y@pipe-d-hdmi-a-1:
- Statuses : 1 pass(s)
- Exec time: [0.29] s
Known issues
Here are the changes found in Patchwork_108157v1_full that come from known
issues:
### CI changes ###
Possible fixes
* boot:
- shard-glk: ([PASS][2], [PASS][3], [PASS][4], [PASS][5],
[PASS][6], [PASS][7], [PASS][8], [FAIL][9], [PASS][10], [PASS][11], [PASS][12],
[PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18],
[PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24],
[PASS][25]) ([i915#4392]) -> ([PASS][26], [PASS][27], [PASS][28], [PASS][29],
[PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35],
[PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41],
[PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47],
[PASS][48], [PASS][49], [PASS][50])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk9/boot.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk9/boot.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk9/boot.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk1/boot.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk1/boot.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk1/boot.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk2/boot.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk2/boot.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk2/boot.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk3/boot.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk3/boot.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk3/boot.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk5/boot.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk5/boot.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk5/boot.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk6/boot.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk6/boot.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk6/boot.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk7/boot.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk7/boot.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk7/boot.html
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk8/boot.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk8/boot.html
[25]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk8/boot.html
[26]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108157v1/shard-glk9/boot.html
[27]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108157v1/shard-glk9/boot.html
[28]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108157v1/shard-glk9/boot.html
[29]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108157v1/shard-glk8/boot.html
[30]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108157v1/shard-glk8/boot.html
[31]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108157v1/shard-glk8/boot.html
[32]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108157v1/shard-glk8/boot.html
[33]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108157v1/shard-glk7/boot.html
[34]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108157v1/shard-glk7/boot.html
[35]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108157v1/shard-glk7/boot.html
[36]:
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: i915_drv.h > i915_gem.h cleanup
== Series Details ==
Series: drm/i915: i915_drv.h > i915_gem.h cleanup
URL : https://patchwork.freedesktop.org/series/108150/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12073_full -> Patchwork_108150v1_full
Summary
---
**SUCCESS**
No regressions found.
Participating hosts (10 -> 11)
--
Additional (1): shard-tglu
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_108150v1_full:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@kms_plane_multiple@tiling-4}:
- {shard-tglu}: NOTRUN -> [SKIP][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108150v1/shard-tglu-8/igt@kms_plane_multi...@tiling-4.html
New tests
-
New tests have been introduced between CI_DRM_12073_full and
Patchwork_108150v1_full:
### New IGT tests (1) ###
* igt@kms_plane_multiple@tiling-y@pipe-d-hdmi-a-1:
- Statuses : 1 pass(s)
- Exec time: [0.30] s
Known issues
Here are the changes found in Patchwork_108150v1_full that come from known
issues:
### CI changes ###
Possible fixes
* boot:
- shard-glk: ([PASS][2], [PASS][3], [PASS][4], [PASS][5],
[PASS][6], [PASS][7], [PASS][8], [FAIL][9], [PASS][10], [PASS][11], [PASS][12],
[PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18],
[PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24],
[PASS][25]) ([i915#4392]) -> ([PASS][26], [PASS][27], [PASS][28], [PASS][29],
[PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35],
[PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41],
[PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk9/boot.html
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk9/boot.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk9/boot.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk1/boot.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk1/boot.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk1/boot.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk2/boot.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk2/boot.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk2/boot.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk3/boot.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk3/boot.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk3/boot.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk5/boot.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk5/boot.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk5/boot.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk6/boot.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk6/boot.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk6/boot.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk7/boot.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk7/boot.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk7/boot.html
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk8/boot.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk8/boot.html
[25]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk8/boot.html
[26]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108150v1/shard-glk7/boot.html
[27]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108150v1/shard-glk1/boot.html
[28]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108150v1/shard-glk1/boot.html
[29]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108150v1/shard-glk1/boot.html
[30]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108150v1/shard-glk3/boot.html
[31]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108150v1/shard-glk3/boot.html
[32]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108150v1/shard-glk3/boot.html
[33]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108150v1/shard-glk5/boot.html
[34]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108150v1/shard-glk5/boot.html
[35]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108150v1/shard-glk5/boot.html
[36]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108150v1/shard-glk5/boot.html
[37]:
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: consider HAS_FLAT_CCS() in needs_ccs_pages
== Series Details ==
Series: drm/i915: consider HAS_FLAT_CCS() in needs_ccs_pages
URL : https://patchwork.freedesktop.org/series/108139/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12073_full -> Patchwork_108139v1_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_108139v1_full absolutely need
to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_108139v1_full, please notify your bug team to allow
them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (10 -> 12)
--
Additional (2): shard-rkl shard-tglu
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_108139v1_full:
### IGT changes ###
Possible regressions
* igt@kms_atomic_transition@plane-all-transition-fencing@vga-1-pipe-a:
- shard-snb: [PASS][1] -> [DMESG-FAIL][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-snb7/igt@kms_atomic_transition@plane-all-transition-fenc...@vga-1-pipe-a.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108139v1/shard-snb7/igt@kms_atomic_transition@plane-all-transition-fenc...@vga-1-pipe-a.html
* igt@perf@buffer-fill:
- shard-glk: [PASS][3] -> [FAIL][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk1/igt@p...@buffer-fill.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108139v1/shard-glk6/igt@p...@buffer-fill.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@kms_plane_multiple@tiling-yf}:
- {shard-tglu}: NOTRUN -> [SKIP][5] +1 similar issue
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108139v1/shard-tglu-6/igt@kms_plane_multi...@tiling-yf.html
Known issues
Here are the changes found in Patchwork_108139v1_full that come from known
issues:
### CI changes ###
Possible fixes
* boot:
- shard-glk: ([PASS][6], [PASS][7], [PASS][8], [PASS][9],
[PASS][10], [PASS][11], [PASS][12], [FAIL][13], [PASS][14], [PASS][15],
[PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21],
[PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27],
[PASS][28], [PASS][29]) ([i915#4392]) -> ([PASS][30], [PASS][31], [PASS][32],
[PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38],
[PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44],
[PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50],
[PASS][51])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk9/boot.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk9/boot.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk9/boot.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk1/boot.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk1/boot.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk1/boot.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk2/boot.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk2/boot.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk2/boot.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk3/boot.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk3/boot.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk3/boot.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk5/boot.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk5/boot.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk5/boot.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk6/boot.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk6/boot.html
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk6/boot.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk7/boot.html
[25]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk7/boot.html
[26]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk7/boot.html
[27]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk8/boot.html
[28]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk8/boot.html
[29]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/shard-glk8/boot.html
[30]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108139v1/shard-glk9/boot.html
[31]:
Re: [Intel-gfx] [PATCH] drm/i915/guc: Cancel GuC engine busyness worker synchronously
On Fri, 26 Aug 2022 17:21:35 -0700, Umesh Nerlige Ramappa wrote:
>
> The worker is canceled in gt_park path, but earlier it was assumed that
> gt_park path cannot sleep and the cancel is asynchronous. This caused a
> race with suspend flow where the worker runs after suspend and causes an
> unclaimed register access warning. Cancel the worker synchronously since
> the gt_park is indeed allowed to sleep.
Indeed, __gt_park already calls cancel_work_sync and synchronize_irq which
can sleep:
Reviewed-by: Ashutosh Dixit
> v2: Fix author name and sign-off mismatch
>
> Signed-off-by: Umesh Nerlige Ramappa
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4419
> Fixes: 77cdd054dd2c ("drm/i915/pmu: Connect engine busyness stats from GuC to
> pmu")
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 7 ++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index 0d56b615bf78..e6275380b253 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -1438,7 +1438,12 @@ void intel_guc_busyness_park(struct intel_gt *gt)
> if (!guc_submission_initialized(guc))
> return;
>
> - cancel_delayed_work(>timestamp.work);
> + /*
> + * There is a race with suspend flow where the worker runs after suspend
> + * and causes an unclaimed register access warning. Cancel the worker
> + * synchronously here.
> + */
> + cancel_delayed_work_sync(>timestamp.work);
>
> /*
>* Before parking, we should sample engine busyness stats if we need to.
> --
> 2.25.1
>
[Intel-gfx] ✓ Fi.CI.BAT: success for i915: CAGF and RC6 changes for MTL (rev2)
== Series Details ==
Series: i915: CAGF and RC6 changes for MTL (rev2)
URL : https://patchwork.freedesktop.org/series/108156/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12073 -> Patchwork_108156v2
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v2/index.html
Participating hosts (39 -> 41)
--
Additional (5): fi-skl-guc bat-dg2-9 fi-ilk-650 fi-blb-e6850 fi-bsw-nick
Missing(3): fi-cml-u2 fi-icl-u2 fi-bdw-samus
Known issues
Here are the changes found in Patchwork_108156v2 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-bsw-nick:NOTRUN -> [SKIP][1] ([fdo#109271]) +38 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v2/fi-bsw-nick/igt@gem_lmem_swapp...@parallel-random-engines.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-ilk-650: NOTRUN -> [SKIP][2] ([fdo#109271]) +19 similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v2/fi-ilk-650/igt@i915_pm_...@basic-pci-d3-state.html
* igt@i915_pm_rpm@module-reload:
- fi-blb-e6850: NOTRUN -> [SKIP][3] ([fdo#109271]) +42 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v2/fi-blb-e6850/igt@i915_pm_...@module-reload.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-g3258: [PASS][4] -> [INCOMPLETE][5] ([i915#3303] /
[i915#4785])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v2/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@requests:
- fi-blb-e6850: NOTRUN -> [DMESG-FAIL][6] ([i915#4528])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v2/fi-blb-e6850/igt@i915_selftest@l...@requests.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-bdw-5557u: NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v2/fi-bdw-5557u/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-hsw-4770:NOTRUN -> [SKIP][8] ([fdo#109271] / [fdo#111827])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v2/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html
- fi-pnv-d510:NOTRUN -> [SKIP][9] ([fdo#109271])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v2/fi-pnv-d510/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_chamelium@hdmi-edid-read:
- fi-ilk-650: NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) +8
similar issues
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v2/fi-ilk-650/igt@kms_chamel...@hdmi-edid-read.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-bsw-nick:NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) +8
similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v2/fi-bsw-nick/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@runner@aborted:
- fi-blb-e6850: NOTRUN -> [FAIL][12] ([fdo#109271] / [i915#2403] /
[i915#4312])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v2/fi-blb-e6850/igt@run...@aborted.html
- fi-skl-guc: NOTRUN -> [FAIL][13] ([i915#6599])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v2/fi-skl-guc/igt@run...@aborted.html
- fi-hsw-g3258: NOTRUN -> [FAIL][14] ([fdo#109271] / [i915#4312] /
[i915#6246])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v2/fi-hsw-g3258/igt@run...@aborted.html
Possible fixes
* igt@gem_exec_suspend@basic-s0@smem:
- {bat-rplp-1}: [DMESG-WARN][15] ([i915#2867]) -> [PASS][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v2/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
* igt@gem_ringfill@basic-all:
- {bat-dg2-8}:[FAIL][17] ([i915#5886]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/bat-dg2-8/igt@gem_ringf...@basic-all.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v2/bat-dg2-8/igt@gem_ringf...@basic-all.html
* igt@i915_selftest@live@gem:
- fi-pnv-d510:[DMESG-FAIL][19] ([i915#4528]) -> [PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/fi-pnv-d510/igt@i915_selftest@l...@gem.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108156v2/fi-pnv-d510/igt@i915_selftest@l...@gem.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[INCOMPLETE][21] ([i915#4785]) -> [PASS][22]
[21]:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for i915: CAGF and RC6 changes for MTL (rev2)
== Series Details == Series: i915: CAGF and RC6 changes for MTL (rev2) URL : https://patchwork.freedesktop.org/series/108156/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: CAGF and RC6 changes for MTL (rev2)
== Series Details == Series: i915: CAGF and RC6 changes for MTL (rev2) URL : https://patchwork.freedesktop.org/series/108156/ State : warning == Summary == Error: dim checkpatch failed 7cf29ff9789e drm/i915: Prepare more multi-GT initialization -:79: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "gtdef->setup" #79: FILE: drivers/gpu/drm/i915/gt/intel_gt.c:853: +gtdef->setup != NULL; total: 0 errors, 0 warnings, 1 checks, 148 lines checked 9861a75e18f2 drm/i915: Rename and expose common GT early init routine 96ce8665ebbd drm/i915/xelpmp: Expose media as another GT Traceback (most recent call last): File "scripts/spdxcheck.py", line 11, in import git ModuleNotFoundError: No module named 'git' Traceback (most recent call last): File "scripts/spdxcheck.py", line 11, in import git ModuleNotFoundError: No module named 'git' -:83: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #83: new file mode 100644 -:119: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "!uncore->regs" #119: FILE: drivers/gpu/drm/i915/gt/intel_sa_media.c:32: + if (drm_WARN_ON(>drm, uncore->regs == NULL)) total: 0 errors, 1 warnings, 1 checks, 233 lines checked 0322aaf49089 drm/i915/mtl: Modify CAGF functions for MTL e50ddf12a96b drm/i915/mtl: Add C6 residency support for MTL SAMedia
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: ipc and display sub-struct refactoring
== Series Details == Series: drm/i915: ipc and display sub-struct refactoring URL : https://patchwork.freedesktop.org/series/108157/ State : success == Summary == CI Bug Log - changes from CI_DRM_12073 -> Patchwork_108157v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108157v1/index.html Participating hosts (39 -> 42) -- Additional (6): fi-rkl-11600 fi-skl-guc bat-dg2-9 fi-ilk-650 fi-blb-e6850 fi-bsw-nick Missing(3): fi-cml-u2 fi-icl-u2 fi-bdw-samus Known issues Here are the changes found in Patchwork_108157v1 that come from known issues: ### IGT changes ### Issues hit * igt@gem_huc_copy@huc-copy: - fi-rkl-11600: NOTRUN -> [SKIP][1] ([i915#2190]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108157v1/fi-rkl-11600/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@parallel-random-engines: - fi-bsw-nick:NOTRUN -> [SKIP][2] ([fdo#109271]) +38 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108157v1/fi-bsw-nick/igt@gem_lmem_swapp...@parallel-random-engines.html - fi-rkl-11600: NOTRUN -> [SKIP][3] ([i915#4613]) +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108157v1/fi-rkl-11600/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_tiled_pread_basic: - fi-rkl-11600: NOTRUN -> [SKIP][4] ([i915#3282]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108157v1/fi-rkl-11600/igt@gem_tiled_pread_basic.html * igt@i915_pm_backlight@basic-brightness: - fi-rkl-11600: NOTRUN -> [SKIP][5] ([i915#3012]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108157v1/fi-rkl-11600/igt@i915_pm_backli...@basic-brightness.html * igt@i915_pm_rpm@basic-pci-d3-state: - fi-ilk-650: NOTRUN -> [SKIP][6] ([fdo#109271]) +19 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108157v1/fi-ilk-650/igt@i915_pm_...@basic-pci-d3-state.html * igt@i915_pm_rpm@module-reload: - fi-blb-e6850: NOTRUN -> [SKIP][7] ([fdo#109271]) +42 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108157v1/fi-blb-e6850/igt@i915_pm_...@module-reload.html * igt@i915_selftest@live@requests: - fi-blb-e6850: NOTRUN -> [DMESG-FAIL][8] ([i915#4528]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108157v1/fi-blb-e6850/igt@i915_selftest@l...@requests.html - fi-pnv-d510:[PASS][9] -> [DMESG-FAIL][10] ([i915#4528]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/fi-pnv-d510/igt@i915_selftest@l...@requests.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108157v1/fi-pnv-d510/igt@i915_selftest@l...@requests.html * igt@i915_suspend@basic-s3-without-i915: - fi-rkl-11600: NOTRUN -> [INCOMPLETE][11] ([i915#5982]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108157v1/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-hsw-4770:NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108157v1/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_chamelium@hdmi-edid-read: - fi-ilk-650: NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827]) +8 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108157v1/fi-ilk-650/igt@kms_chamel...@hdmi-edid-read.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-bsw-nick:NOTRUN -> [SKIP][14] ([fdo#109271] / [fdo#111827]) +8 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108157v1/fi-bsw-nick/igt@kms_chamel...@hdmi-hpd-fast.html - fi-rkl-11600: NOTRUN -> [SKIP][15] ([fdo#111827]) +7 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108157v1/fi-rkl-11600/igt@kms_chamel...@hdmi-hpd-fast.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor: - fi-rkl-11600: NOTRUN -> [SKIP][16] ([i915#4103]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108157v1/fi-rkl-11600/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html * igt@kms_force_connector_basic@force-load-detect: - fi-rkl-11600: NOTRUN -> [SKIP][17] ([fdo#109285] / [i915#4098]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108157v1/fi-rkl-11600/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_psr@sprite_plane_onoff: - fi-rkl-11600: NOTRUN -> [SKIP][18] ([i915#1072]) +3 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108157v1/fi-rkl-11600/igt@kms_psr@sprite_plane_onoff.html * igt@kms_setmode@basic-clone-single-crtc: - fi-rkl-11600: NOTRUN -> [SKIP][19] ([i915#3555] / [i915#4098]) [19]:
[Intel-gfx] [PATCH 4/5] drm/i915/mtl: Modify CAGF functions for MTL
Updated the CAGF functions to get actual resolved frequency of
3D and SAMedia
Bspec: 66300
Cc: Vinay Belgaumkar
Cc: Ashutosh Dixit
Signed-off-by: Badal Nilawar
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 8
drivers/gpu/drm/i915/gt/intel_rps.c | 5 +
2 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index fb2c56777480..67b58d572941 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1510,6 +1510,14 @@
#define VLV_RENDER_C0_COUNT_MMIO(0x138118)
#define VLV_MEDIA_C0_COUNT _MMIO(0x13811c)
+/*
+ * MTL: Workpoint reg to get Core C state and act freq of 3D, SAMedia/
+ * 3D - 0x0C60 , SAMedia - 0x380C60
+ * Intel uncore handler redirects transactions for SAMedia to
MTL_MEDIA_GSI_BASE
+ */
+#define MTL_MIRROR_TARGET_WP1 _MMIO(0x0C60)
+#define MTL_CAGF_MASKREG_GENMASK(8, 0)
+
#define GEN11_GT_INTR_DW(x)_MMIO(0x190018 + ((x) * 4))
#define GEN11_CSME (31)
#define GEN11_GUNIT (28)
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
b/drivers/gpu/drm/i915/gt/intel_rps.c
index 579ae9ac089c..0f6d109b1aad 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -2044,6 +2044,8 @@ u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat)
if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
cagf = (rpstat >> 8) & 0xff;
+ else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
+ cagf = rpstat & MTL_CAGF_MASK;
else if (GRAPHICS_VER(i915) >= 9)
cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
else if (IS_HASWELL(i915) || IS_BROADWELL(i915))
@@ -2067,6 +2069,9 @@ static u32 read_cagf(struct intel_rps *rps)
vlv_punit_get(i915);
freq = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
vlv_punit_put(i915);
+ } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
+ freq = intel_uncore_read(rps_to_gt(rps)->uncore,
+MTL_MIRROR_TARGET_WP1);
} else if (GRAPHICS_VER(i915) >= 6) {
freq = intel_uncore_read(uncore, GEN6_RPSTAT1);
} else {
--
2.25.1
[Intel-gfx] [PATCH 5/5] drm/i915/mtl: Add C6 residency support for MTL SAMedia
For MTL SAMedia updated relevant functions and places in the code to get
Media C6 residency.
Cc: Vinay Belgaumkar
Cc: Ashutosh Dixit
Cc: Chris Wilson
Signed-off-by: Badal Nilawar
---
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 56 +++
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 10
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 9 ++-
drivers/gpu/drm/i915/gt/intel_rc6.c | 5 +-
drivers/gpu/drm/i915/gt/selftest_rc6.c| 9 ++-
drivers/gpu/drm/i915/i915_pmu.c | 8 ++-
6 files changed, 93 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
index 108b9e76c32e..29b89b980648 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
@@ -269,6 +269,60 @@ static int ilk_drpc(struct seq_file *m)
return 0;
}
+static int mtl_drpc(struct seq_file *m)
+{
+ struct intel_gt *gt = m->private;
+ struct intel_uncore *uncore = gt->uncore;
+ u32 gt_core_status, rcctl1;
+ u32 mtl_powergate_enable = 0, mtl_powergate_status = 0;
+ i915_reg_t reg;
+
+ gt_core_status = intel_uncore_read(uncore, MTL_MIRROR_TARGET_WP1);
+
+ rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL);
+ mtl_powergate_enable = intel_uncore_read(uncore, GEN9_PG_ENABLE);
+ mtl_powergate_status = intel_uncore_read(uncore,
+GEN9_PWRGT_DOMAIN_STATUS);
+
+ seq_printf(m, "RC6 Enabled: %s\n",
+ str_yes_no(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
+ if (gt->type == GT_MEDIA) {
+ seq_printf(m, "Media Well Gating Enabled: %s\n",
+ str_yes_no(mtl_powergate_enable &
GEN9_MEDIA_PG_ENABLE));
+ } else {
+ seq_printf(m, "Render Well Gating Enabled: %s\n",
+ str_yes_no(mtl_powergate_enable &
GEN9_RENDER_PG_ENABLE));
+ }
+
+ seq_puts(m, "Current RC state: ");
+
+ switch ((gt_core_status & MTL_CC_MASK) >> MTL_CC_SHIFT) {
+ case MTL_CC0:
+ seq_puts(m, "on\n");
+ break;
+ case MTL_CC6:
+ seq_puts(m, "RC6\n");
+ break;
+ default:
+ seq_puts(m, "Unknown\n");
+ break;
+ }
+
+ if (gt->type == GT_MEDIA)
+ seq_printf(m, "Media Power Well: %s\n",
+ (mtl_powergate_status &
+ GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
+ else
+ seq_printf(m, "Render Power Well: %s\n",
+ (mtl_powergate_status &
+ GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
+
+ reg = (gt->type == GT_MEDIA) ? MTL_MEDIA_MC6 : GEN6_GT_GFX_RC6;
+ print_rc6_res(m, "RC6 residency since boot:", reg);
+
+ return fw_domains_show(m, NULL);
+}
+
static int drpc_show(struct seq_file *m, void *unused)
{
struct intel_gt *gt = m->private;
@@ -279,6 +333,8 @@ static int drpc_show(struct seq_file *m, void *unused)
with_intel_runtime_pm(gt->uncore->rpm, wakeref) {
if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
err = vlv_drpc(m);
+ else if (MEDIA_VER(i915) >= 13)
+ err = mtl_drpc(m);
else if (GRAPHICS_VER(i915) >= 6)
err = gen6_drpc(m);
else
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 67b58d572941..b14048da9b0c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1517,6 +1517,16 @@
*/
#define MTL_MIRROR_TARGET_WP1 _MMIO(0x0C60)
#define MTL_CAGF_MASKREG_GENMASK(8, 0)
+#define MTL_CC0 0x0
+#define MTL_CC6 0x3
+#define MTL_CC_SHIFT 9
+#define MTL_CC_MASK (0xf << MTL_CC_SHIFT)
+
+/*
+ * MTL: This register contains the total MC6 residency time that SAMedia was
+ * since boot
+ */
+#define MTL_MEDIA_MC6 _MMIO(0x138048)
#define GEN11_GT_INTR_DW(x)_MMIO(0x190018 + ((x) * 4))
#define GEN11_CSME (31)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
index e066cc33d9f2..fb2cf8ee2eeb 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
@@ -138,7 +138,14 @@ static ssize_t rc6_residency_ms_show(struct device *dev,
static u32 __rc6p_residency_ms_show(struct intel_gt *gt)
{
- return get_residency(gt, GEN6_GT_GFX_RC6p);
+ i915_reg_t reg;
+
+ if (gt->type == GT_MEDIA)
+ reg = MTL_MEDIA_MC6;
+ else
+ reg = GEN6_GT_GFX_RC6;
+
+ return
[Intel-gfx] [PATCH 2/5] drm/i915: Rename and expose common GT early init routine
From: Matt Roper
The common early GT init is needed for initialization of all GT types
(root/primary, remote tile, standalone media). Since standalone media
(coming in the next patch) will be implemented in a separate file,
rename and expose the function for use.
Signed-off-by: Matt Roper
Reviewed-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/gt/intel_gt.c | 6 +++---
drivers/gpu/drm/i915/gt/intel_gt.h | 1 +
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 5b4263c708cc..57a6488c0e14 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -35,7 +35,7 @@
#include "intel_uncore.h"
#include "shmem_utils.h"
-static void __intel_gt_init_early(struct intel_gt *gt)
+void intel_gt_common_init_early(struct intel_gt *gt)
{
spin_lock_init(>irq_lock);
@@ -65,7 +65,7 @@ void intel_root_gt_init_early(struct drm_i915_private *i915)
gt->i915 = i915;
gt->uncore = >uncore;
- __intel_gt_init_early(gt);
+ intel_gt_common_init_early(gt);
}
static int intel_gt_probe_lmem(struct intel_gt *gt)
@@ -797,7 +797,7 @@ static int intel_gt_tile_setup(struct intel_gt *gt,
phys_addr_t phys_addr)
gt->uncore = uncore;
gt->uncore->debug = mmio_debug;
- __intel_gt_init_early(gt);
+ intel_gt_common_init_early(gt);
}
intel_uncore_init_early(gt->uncore, gt);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h
b/drivers/gpu/drm/i915/gt/intel_gt.h
index 4d8779529cc2..c9a359f35d0f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -44,6 +44,7 @@ static inline struct intel_gt *gsc_to_gt(struct intel_gsc
*gsc)
return container_of(gsc, struct intel_gt, gsc);
}
+void intel_gt_common_init_early(struct intel_gt *gt);
void intel_root_gt_init_early(struct drm_i915_private *i915);
int intel_gt_assign_ggtt(struct intel_gt *gt);
int intel_gt_init_mmio(struct intel_gt *gt);
--
2.25.1
[Intel-gfx] [PATCH 1/5] drm/i915: Prepare more multi-GT initialization
From: Matt Roper
We're going to introduce an additional intel_gt for MTL's media unit
soon. Let's provide a bit more multi-GT initialization framework in
preparation for that. The initialization will pull the list of GTs for
a platform from the device info structure. Although necessary for the
immediate MTL media enabling, this same framework will also be used
farther down the road when we enable remote tiles on xehpsdv and pvc.
v2:
- Re-add missing test for !HAS_EXTRA_GT_LIST in intel_gt_probe_all().
Cc: Aravind Iddamsetty
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt.c| 54 ---
drivers/gpu/drm/i915/gt/intel_gt.h| 1 -
drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 ++
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/intel_device_info.h | 16 ++
.../gpu/drm/i915/selftests/mock_gem_device.c | 1 +
7 files changed, 70 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 275ad72940c1..41acc285e8bf 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -736,7 +736,7 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt
*gt)
u16 vdbox_mask;
u16 vebox_mask;
- info->engine_mask = RUNTIME_INFO(i915)->platform_engine_mask;
+ GEM_BUG_ON(!info->engine_mask);
if (GRAPHICS_VER(i915) < 11)
return info->engine_mask;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index e4bac2431e41..5b4263c708cc 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -815,20 +815,16 @@ static void
intel_gt_tile_cleanup(struct intel_gt *gt)
{
intel_uncore_cleanup_mmio(gt->uncore);
-
- if (!gt_is_root(gt)) {
- kfree(gt->uncore->debug);
- kfree(gt->uncore);
- kfree(gt);
- }
}
int intel_gt_probe_all(struct drm_i915_private *i915)
{
struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
struct intel_gt *gt = >gt0;
+ const struct intel_gt_definition *gtdef;
phys_addr_t phys_addr;
unsigned int mmio_bar;
+ unsigned int i;
int ret;
mmio_bar = GRAPHICS_VER(i915) == 2 ? GEN2_GTTMMADR_BAR : GTTMMADR_BAR;
@@ -839,14 +835,58 @@ int intel_gt_probe_all(struct drm_i915_private *i915)
* and it has been already initialized early during probe
* in i915_driver_probe()
*/
+ gt->i915 = i915;
+ gt->name = "Primary GT";
+ gt->info.engine_mask = RUNTIME_INFO(i915)->platform_engine_mask;
+
+ drm_dbg(>drm, "Setting up %s\n", gt->name);
ret = intel_gt_tile_setup(gt, phys_addr);
if (ret)
return ret;
i915->gt[0] = gt;
- /* TODO: add more tiles */
+ if (!HAS_EXTRA_GT_LIST(i915))
+ return 0;
+
+ for (i = 1, gtdef = _INFO(i915)->extra_gt_list[i - 1];
+gtdef->setup != NULL;
+i++, gtdef = _INFO(i915)->extra_gt_list[i - 1]) {
+ gt = drmm_kzalloc(>drm, sizeof(*gt), GFP_KERNEL);
+ if (!gt) {
+ ret = -ENOMEM;
+ goto err;
+ }
+
+ gt->i915 = i915;
+ gt->name = gtdef->name;
+ gt->type = gtdef->type;
+ gt->info.engine_mask = gtdef->engine_mask;
+ gt->info.id = i;
+
+ drm_dbg(>drm, "Setting up %s\n", gt->name);
+ if (GEM_WARN_ON(range_overflows_t(resource_size_t,
+ gtdef->mapping_base,
+ SZ_16M,
+ pci_resource_len(pdev,
mmio_bar {
+ ret = -ENODEV;
+ goto err;
+ }
+
+ ret = gtdef->setup(gt, phys_addr + gtdef->mapping_base);
+ if (ret)
+ goto err;
+
+ i915->gt[i] = gt;
+ }
+
return 0;
+
+err:
+ i915_probe_error(i915, "Failed to initialize %s! (%d)\n", gtdef->name,
ret);
+ intel_gt_release_all(i915);
+
+ return ret;
}
int intel_gt_tiles_init(struct drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h
b/drivers/gpu/drm/i915/gt/intel_gt.h
index 40b06adf509a..4d8779529cc2 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -54,7 +54,6 @@ void intel_gt_driver_register(struct intel_gt *gt);
void intel_gt_driver_unregister(struct intel_gt *gt);
void intel_gt_driver_remove(struct intel_gt *gt);
void intel_gt_driver_release(struct intel_gt *gt);
-
void intel_gt_driver_late_release_all(struct drm_i915_private *i915);
int
[Intel-gfx] [PATCH 3/5] drm/i915/xelpmp: Expose media as another GT
From: Matt Roper
Xe_LPM+ platforms have "standalone media." I.e., the media unit is
designed as an additional GT with its own engine list, GuC, forcewake,
etc. Let's allow platforms to include media GTs in their device info.
Cc: Aravind Iddamsetty
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/gt/intel_gt.c | 12 ++--
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 8 +
drivers/gpu/drm/i915/gt/intel_sa_media.c | 39
drivers/gpu/drm/i915/gt/intel_sa_media.h | 15 +
drivers/gpu/drm/i915/i915_pci.c | 15 +
drivers/gpu/drm/i915/intel_device_info.h | 5 ++-
drivers/gpu/drm/i915/intel_uncore.c | 16 --
drivers/gpu/drm/i915/intel_uncore.h | 20 ++--
9 files changed, 123 insertions(+), 8 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_sa_media.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_sa_media.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 522ef9b4aff3..e83e4cd46968 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -123,6 +123,7 @@ gt-y += \
gt/intel_ring.o \
gt/intel_ring_submission.o \
gt/intel_rps.o \
+ gt/intel_sa_media.o \
gt/intel_sseu.o \
gt/intel_sseu_debugfs.o \
gt/intel_timeline.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 57a6488c0e14..bfe77d01f747 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -776,10 +776,15 @@ void intel_gt_driver_late_release_all(struct
drm_i915_private *i915)
}
}
-static int intel_gt_tile_setup(struct intel_gt *gt, phys_addr_t phys_addr)
+static int intel_gt_tile_setup(struct intel_gt *gt,
+ phys_addr_t phys_addr,
+ u32 gsi_offset)
{
int ret;
+ /* GSI offset is only applicable for media GTs */
+ drm_WARN_ON(>i915->drm, gsi_offset);
+
if (!gt_is_root(gt)) {
struct intel_uncore_mmio_debug *mmio_debug;
struct intel_uncore *uncore;
@@ -840,7 +845,7 @@ int intel_gt_probe_all(struct drm_i915_private *i915)
gt->info.engine_mask = RUNTIME_INFO(i915)->platform_engine_mask;
drm_dbg(>drm, "Setting up %s\n", gt->name);
- ret = intel_gt_tile_setup(gt, phys_addr);
+ ret = intel_gt_tile_setup(gt, phys_addr, 0);
if (ret)
return ret;
@@ -873,7 +878,8 @@ int intel_gt_probe_all(struct drm_i915_private *i915)
goto err;
}
- ret = gtdef->setup(gt, phys_addr + gtdef->mapping_base);
+ ret = gtdef->setup(gt, phys_addr + gtdef->mapping_base,
+ gtdef->gsi_offset);
if (ret)
goto err;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index d414785003cc..fb2c56777480 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1578,4 +1578,12 @@
#define GEN12_SFC_DONE(n) _MMIO(0x1cc000 + (n) * 0x1000)
+/*
+ * Standalone Media's non-engine GT registers are located at their regular GT
+ * offsets plus 0x38. This extra offset is stored inside the intel_uncore
+ * structure so that the existing code can be used for both GTs without
+ * modification.
+ */
+#define MTL_MEDIA_GSI_BASE 0x38
+
#endif /* __INTEL_GT_REGS__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_sa_media.c
b/drivers/gpu/drm/i915/gt/intel_sa_media.c
new file mode 100644
index ..8c5c519457cc
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_sa_media.c
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#include
+
+#include "i915_drv.h"
+#include "gt/intel_gt.h"
+#include "gt/intel_sa_media.h"
+
+int intel_sa_mediagt_setup(struct intel_gt *gt, phys_addr_t phys_addr,
+ u32 gsi_offset)
+{
+ struct drm_i915_private *i915 = gt->i915;
+ struct intel_uncore *uncore;
+
+ uncore = drmm_kzalloc(>drm, sizeof(*uncore), GFP_KERNEL);
+ if (!uncore)
+ return -ENOMEM;
+
+ uncore->gsi_offset = gsi_offset;
+
+ intel_gt_common_init_early(gt);
+ intel_uncore_init_early(uncore, gt);
+
+ /*
+* Standalone media shares the general MMIO space with the primary
+* GT. We'll re-use the primary GT's mapping.
+*/
+ uncore->regs = i915->uncore.regs;
+ if (drm_WARN_ON(>drm, uncore->regs == NULL))
+ return -EIO;
+
+ gt->uncore = uncore;
+ gt->phys_addr = phys_addr;
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/i915/gt/intel_sa_media.h
b/drivers/gpu/drm/i915/gt/intel_sa_media.h
new file mode 100644
index
[Intel-gfx] [PATCH 0/5] i915: CAGF and RC6 changes for MTL
This series includes the code changes to get CAGF, RC State and C6 Residency of MTL. The series depends on: https://patchwork.freedesktop.org/series/107908/ We have included 3 patches from from the above series as part of this series in order for this series to compile. These are the first 3 patches authored by Matt Roper. Please do not review these first 3 patches. Only patch 4 and 5 needs review. Cc: Ashutosh Dixit Badal Nilawar (2): drm/i915/mtl: Modify CAGF functions for MTL drm/i915/mtl: Add C6 residency support for MTL SAMedia Matt Roper (3): drm/i915: Prepare more multi-GT initialization drm/i915: Rename and expose common GT early init routine drm/i915/xelpmp: Expose media as another GT drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +- drivers/gpu/drm/i915/gt/intel_gt.c| 70 +++ drivers/gpu/drm/i915/gt/intel_gt.h| 2 +- drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 56 +++ drivers/gpu/drm/i915/gt/intel_gt_regs.h | 26 +++ drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 9 ++- drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 + drivers/gpu/drm/i915/gt/intel_rc6.c | 5 +- drivers/gpu/drm/i915/gt/intel_rps.c | 5 ++ drivers/gpu/drm/i915/gt/intel_sa_media.c | 39 +++ drivers/gpu/drm/i915/gt/intel_sa_media.h | 15 drivers/gpu/drm/i915/gt/selftest_rc6.c| 9 ++- drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu/drm/i915/i915_pci.c | 15 drivers/gpu/drm/i915/i915_pmu.c | 8 ++- drivers/gpu/drm/i915/intel_device_info.h | 19 + drivers/gpu/drm/i915/intel_uncore.c | 16 - drivers/gpu/drm/i915/intel_uncore.h | 20 +- .../gpu/drm/i915/selftests/mock_gem_device.c | 1 + 20 files changed, 301 insertions(+), 22 deletions(-) create mode 100644 drivers/gpu/drm/i915/gt/intel_sa_media.c create mode 100644 drivers/gpu/drm/i915/gt/intel_sa_media.h -- 2.25.1
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: ipc and display sub-struct refactoring
== Series Details == Series: drm/i915: ipc and display sub-struct refactoring URL : https://patchwork.freedesktop.org/series/108157/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: ipc and display sub-struct refactoring
== Series Details == Series: drm/i915: ipc and display sub-struct refactoring URL : https://patchwork.freedesktop.org/series/108157/ State : warning == Summary == Error: dim checkpatch failed 9dbc6786b6df drm/i915/ipc: split out intel_ipc.[ch] Traceback (most recent call last): File "scripts/spdxcheck.py", line 6, in from ply import lex, yacc ModuleNotFoundError: No module named 'ply' -:99: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #99: new file mode 100644 -:166: WARNING:SPDX_LICENSE_TAG: Improper SPDX comment style for 'drivers/gpu/drm/i915/display/intel_ipc.h', please use '/*' instead #166: FILE: drivers/gpu/drm/i915/display/intel_ipc.h:1: +// SPDX-License-Identifier: MIT -:166: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #166: FILE: drivers/gpu/drm/i915/display/intel_ipc.h:1: +// SPDX-License-Identifier: MIT total: 0 errors, 3 warnings, 0 checks, 233 lines checked 19a0ebf31090 drm/i915/ipc: move IPC debugfs to intel_ipc.c d510b07d9964 drm/i915/ipc: register debugfs only if IPC available 24998aaf8687 drm/i915/display: move IPC under display sub-struct c2d4e3412342 drm/i915/display: move hdport under display sub-struct
[Intel-gfx] [PATCH 5/5] drm/i915/display: move hdport under display sub-struct
Move display hdport related members under drm_i915_private display
sub-struct.
Prefer adding anonymous sub-structs even for single members that aren't
our own structs.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_ddi.c | 4 ++--
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_display_core.h | 10 ++
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 4 ++--
drivers/gpu/drm/i915/i915_drv.h | 8
5 files changed, 15 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index f5416433826d..266c379c1d98 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4130,8 +4130,8 @@ intel_ddi_max_lanes(struct intel_digital_port *dig_port)
static bool hti_uses_phy(struct drm_i915_private *i915, enum phy phy)
{
- return i915->hti_state & HDPORT_ENABLED &&
- i915->hti_state & HDPORT_DDI_USED(phy);
+ return i915->display.hdport.hti_state & HDPORT_ENABLED &&
+ i915->display.hdport.hti_state & HDPORT_DDI_USED(phy);
}
static enum hpd_pin xelpd_hpd_pin(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 7834a47e0b4b..2160537fee73 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8774,7 +8774,7 @@ int intel_modeset_init_nogem(struct drm_i915_private
*i915)
* any display resources before we create our display outputs.
*/
if (INTEL_INFO(i915)->display.has_hti)
- i915->hti_state = intel_de_read(i915, HDPORT_STATE);
+ i915->display.hdport.hti_state = intel_de_read(i915,
HDPORT_STATE);
/* Just disable it once at startup */
intel_vga_disable(i915);
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
b/drivers/gpu/drm/i915/display/intel_display_core.h
index 4c9a6b9c5512..eb013c153c48 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -355,6 +355,16 @@ struct intel_display {
struct mutex comp_mutex;
} hdcp;
+ struct {
+ /*
+* HTI (aka HDPORT) state read during initial hw readout. Most
+* platforms don't have HTI, so this will just stay 0. Those
+* that do will use this later to figure out which PLLs and PHYs
+* are unavailable for driver usage.
+*/
+ u32 hti_state;
+ } hdport;
+
struct {
bool enabled;
} ipc;
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index d437fcf04bdd..8260f1168e8b 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3169,10 +3169,10 @@ static void icl_update_active_dpll(struct
intel_atomic_state *state,
static u32 intel_get_hti_plls(struct drm_i915_private *i915)
{
- if (!(i915->hti_state & HDPORT_ENABLED))
+ if (!(i915->display.hdport.hti_state & HDPORT_ENABLED))
return 0;
- return REG_FIELD_GET(HDPORT_DPLL_USED_MASK, i915->hti_state);
+ return REG_FIELD_GET(HDPORT_DPLL_USED_MASK,
i915->display.hdport.hti_state);
}
static int icl_compute_combo_phy_dpll(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1c95c75714da..ae63a8d71392 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -305,14 +305,6 @@ struct drm_i915_private {
struct intel_l3_parity l3_parity;
- /*
-* HTI (aka HDPORT) state read during initial hw readout. Most
-* platforms don't have HTI, so this will just stay 0. Those that do
-* will use this later to figure out which PLLs and PHYs are unavailable
-* for driver usage.
-*/
- u32 hti_state;
-
/*
* edram size in MB.
* Cannot be determined by PCIID. You must always read a register.
--
2.34.1
[Intel-gfx] [PATCH 4/5] drm/i915/display: move IPC under display sub-struct
Move display IPC related members under drm_i915_private display
sub-struct.
Prefer adding anonymous sub-structs even for single members that aren't
our own structs.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display_core.h | 4
drivers/gpu/drm/i915/display/intel_ipc.c | 6 +++---
drivers/gpu/drm/i915/i915_drv.h | 2 --
3 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
b/drivers/gpu/drm/i915/display/intel_display_core.h
index 9086a612365e..4c9a6b9c5512 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -355,6 +355,10 @@ struct intel_display {
struct mutex comp_mutex;
} hdcp;
+ struct {
+ bool enabled;
+ } ipc;
+
struct {
struct i915_power_domains domains;
diff --git a/drivers/gpu/drm/i915/display/intel_ipc.c
b/drivers/gpu/drm/i915/display/intel_ipc.c
index 1285d88b5d25..8fd1251c40bd 100644
--- a/drivers/gpu/drm/i915/display/intel_ipc.c
+++ b/drivers/gpu/drm/i915/display/intel_ipc.c
@@ -10,7 +10,7 @@
bool intel_ipc_is_enabled(struct drm_i915_private *i915)
{
- return i915->ipc_enabled;
+ return i915->display.ipc.enabled;
}
void intel_ipc_enable(struct drm_i915_private *i915)
@@ -50,7 +50,7 @@ void intel_ipc_init(struct drm_i915_private *i915)
if (!HAS_IPC(i915))
return;
- i915->ipc_enabled = intel_ipc_can_enable(i915);
+ i915->display.ipc.enabled = intel_ipc_can_enable(i915);
intel_ipc_enable(i915);
}
@@ -88,7 +88,7 @@ static ssize_t intel_ipc_status_write(struct file *file,
const char __user *ubuf
if (!intel_ipc_is_enabled(i915) && enable)
drm_info(>drm,
"Enabling IPC: WM will be proper only after
next commit\n");
- i915->ipc_enabled = enable;
+ i915->display.ipc.enabled = enable;
intel_ipc_enable(i915);
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c9cca165bf5d..1c95c75714da 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -395,8 +395,6 @@ struct drm_i915_private {
*/
u8 snps_phy_failed_calibration;
- bool ipc_enabled;
-
struct i915_pmu pmu;
struct i915_drm_clients clients;
--
2.34.1
[Intel-gfx] [PATCH 3/5] drm/i915/ipc: register debugfs only if IPC available
It looks like trying to enable IPC via debugfs on platforms that don't
have IPC resulted in dmesg info message about IPC being enabled, which
is clearly not possible and would not happen.
Seems sensible to register IPC debugfs only on platforms that have IPC.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_ipc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ipc.c
b/drivers/gpu/drm/i915/display/intel_ipc.c
index 389d7d8012d9..1285d88b5d25 100644
--- a/drivers/gpu/drm/i915/display/intel_ipc.c
+++ b/drivers/gpu/drm/i915/display/intel_ipc.c
@@ -68,9 +68,6 @@ static int intel_ipc_status_open(struct inode *inode, struct
file *file)
{
struct drm_i915_private *i915 = inode->i_private;
- if (!HAS_IPC(i915))
- return -ENODEV;
-
return single_open(file, intel_ipc_status_show, i915);
}
@@ -111,6 +108,9 @@ void intel_ipc_debugfs_register(struct drm_i915_private
*i915)
{
struct drm_minor *minor = i915->drm.primary;
+ if (!HAS_IPC(i915))
+ return;
+
debugfs_create_file("i915_ipc_status", 0644, minor->debugfs_root,
i915, _ipc_status_fops);
}
--
2.34.1
[Intel-gfx] [PATCH 2/5] drm/i915/ipc: move IPC debugfs to intel_ipc.c
Follow the new direction for debugfs files, moving the details where the
implementation is. It seems quite natural intel_ipc.c is the place that
controls IPC details, even for debugfs, not intel_display_debugfs.c.
Signed-off-by: Jani Nikula
---
.../drm/i915/display/intel_display_debugfs.c | 54 +
drivers/gpu/drm/i915/display/intel_ipc.c | 60 +++
drivers/gpu/drm/i915/display/intel_ipc.h | 1 +
3 files changed, 62 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index a85e6219b403..f4e0a2b119e6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -983,58 +983,6 @@ static int i915_shared_dplls_info(struct seq_file *m, void
*unused)
return 0;
}
-static int i915_ipc_status_show(struct seq_file *m, void *data)
-{
- struct drm_i915_private *dev_priv = m->private;
-
- seq_printf(m, "Isochronous Priority Control: %s\n",
- str_yes_no(intel_ipc_is_enabled(dev_priv)));
- return 0;
-}
-
-static int i915_ipc_status_open(struct inode *inode, struct file *file)
-{
- struct drm_i915_private *dev_priv = inode->i_private;
-
- if (!HAS_IPC(dev_priv))
- return -ENODEV;
-
- return single_open(file, i915_ipc_status_show, dev_priv);
-}
-
-static ssize_t i915_ipc_status_write(struct file *file, const char __user
*ubuf,
-size_t len, loff_t *offp)
-{
- struct seq_file *m = file->private_data;
- struct drm_i915_private *dev_priv = m->private;
- intel_wakeref_t wakeref;
- bool enable;
- int ret;
-
- ret = kstrtobool_from_user(ubuf, len, );
- if (ret < 0)
- return ret;
-
- with_intel_runtime_pm(_priv->runtime_pm, wakeref) {
- if (!intel_ipc_is_enabled(dev_priv) && enable)
- drm_info(_priv->drm,
-"Enabling IPC: WM will be proper only after
next commit\n");
- dev_priv->ipc_enabled = enable;
- intel_ipc_enable(dev_priv);
- }
-
- return len;
-}
-
-static const struct file_operations i915_ipc_status_fops = {
- .owner = THIS_MODULE,
- .open = i915_ipc_status_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release,
- .write = i915_ipc_status_write
-};
-
static int i915_ddb_info(struct seq_file *m, void *unused)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -1911,7 +1859,6 @@ static const struct {
{"i915_dp_test_active", _displayport_test_active_fops},
{"i915_hpd_storm_ctl", _hpd_storm_ctl_fops},
{"i915_hpd_short_storm_ctl", _hpd_short_storm_ctl_fops},
- {"i915_ipc_status", _ipc_status_fops},
{"i915_drrs_ctl", _drrs_ctl_fops},
{"i915_edp_psr_debug", _edp_psr_debug_fops},
};
@@ -1935,6 +1882,7 @@ void intel_display_debugfs_register(struct
drm_i915_private *i915)
intel_dmc_debugfs_register(i915);
intel_fbc_debugfs_register(i915);
+ intel_ipc_debugfs_register(i915);
}
static int i915_panel_show(struct seq_file *m, void *data)
diff --git a/drivers/gpu/drm/i915/display/intel_ipc.c
b/drivers/gpu/drm/i915/display/intel_ipc.c
index 71afec42d374..389d7d8012d9 100644
--- a/drivers/gpu/drm/i915/display/intel_ipc.c
+++ b/drivers/gpu/drm/i915/display/intel_ipc.c
@@ -54,3 +54,63 @@ void intel_ipc_init(struct drm_i915_private *i915)
intel_ipc_enable(i915);
}
+
+static int intel_ipc_status_show(struct seq_file *m, void *data)
+{
+ struct drm_i915_private *i915 = m->private;
+
+ seq_printf(m, "Isochronous Priority Control: %s\n",
+ str_yes_no(intel_ipc_is_enabled(i915)));
+ return 0;
+}
+
+static int intel_ipc_status_open(struct inode *inode, struct file *file)
+{
+ struct drm_i915_private *i915 = inode->i_private;
+
+ if (!HAS_IPC(i915))
+ return -ENODEV;
+
+ return single_open(file, intel_ipc_status_show, i915);
+}
+
+static ssize_t intel_ipc_status_write(struct file *file, const char __user
*ubuf,
+ size_t len, loff_t *offp)
+{
+ struct seq_file *m = file->private_data;
+ struct drm_i915_private *i915 = m->private;
+ intel_wakeref_t wakeref;
+ bool enable;
+ int ret;
+
+ ret = kstrtobool_from_user(ubuf, len, );
+ if (ret < 0)
+ return ret;
+
+ with_intel_runtime_pm(>runtime_pm, wakeref) {
+ if (!intel_ipc_is_enabled(i915) && enable)
+ drm_info(>drm,
+"Enabling IPC: WM will be proper only after
next commit\n");
+ i915->ipc_enabled = enable;
+ intel_ipc_enable(i915);
+ }
+
+ return len;
+}
+
+static const
[Intel-gfx] [PATCH 1/5] drm/i915/ipc: split out intel_ipc.[ch]
Add new files display/intel_ipc.[ch] for the Isochronous Priority
Control (IPC) functionality. Rename functions accordingly, and abstract
direct i915->is_enabled access behind a intel_ipc_is_enabled() function.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 7 ++-
.../drm/i915/display/intel_display_debugfs.c | 7 ++-
drivers/gpu/drm/i915/display/intel_ipc.c | 56 +++
drivers/gpu/drm/i915/display/intel_ipc.h | 17 ++
drivers/gpu/drm/i915/i915_driver.c| 3 +-
drivers/gpu/drm/i915/intel_pm.c | 47 +---
drivers/gpu/drm/i915/intel_pm.h | 2 -
8 files changed, 87 insertions(+), 53 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_ipc.c
create mode 100644 drivers/gpu/drm/i915/display/intel_ipc.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 522ef9b4aff3..535dcd7e3512 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -243,6 +243,7 @@ i915-y += \
display/intel_global_state.o \
display/intel_hdcp.o \
display/intel_hotplug.o \
+ display/intel_ipc.o \
display/intel_lpe_audio.o \
display/intel_modeset_verify.o \
display/intel_modeset_setup.o \
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index be7cff722196..7834a47e0b4b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -98,6 +98,7 @@
#include "intel_frontbuffer.h"
#include "intel_hdcp.h"
#include "intel_hotplug.h"
+#include "intel_ipc.h"
#include "intel_modeset_verify.h"
#include "intel_modeset_setup.h"
#include "intel_overlay.h"
@@ -4751,7 +4752,7 @@ static u16 skl_linetime_wm(const struct intel_crtc_state
*crtc_state)
/* Display WA #1135: BXT:ALL GLK:ALL */
if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
- dev_priv->ipc_enabled)
+ intel_ipc_is_enabled(dev_priv))
linetime_wm /= 2;
return min(linetime_wm, 0x1ff);
@@ -8829,7 +8830,7 @@ int intel_modeset_init(struct drm_i915_private *i915)
intel_hpd_init(i915);
intel_hpd_poll_disable(i915);
- intel_init_ipc(i915);
+ intel_ipc_init(i915);
return 0;
}
@@ -8960,7 +8961,7 @@ void intel_display_resume(struct drm_device *dev)
if (!ret)
ret = __intel_display_resume(i915, state, );
- intel_enable_ipc(i915);
+ intel_ipc_enable(i915);
drm_modeset_drop_locks();
drm_modeset_acquire_fini();
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 5dc364e9db49..a85e6219b403 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -22,6 +22,7 @@
#include "intel_fbdev.h"
#include "intel_hdcp.h"
#include "intel_hdmi.h"
+#include "intel_ipc.h"
#include "intel_panel.h"
#include "intel_pm.h"
#include "intel_psr.h"
@@ -987,7 +988,7 @@ static int i915_ipc_status_show(struct seq_file *m, void
*data)
struct drm_i915_private *dev_priv = m->private;
seq_printf(m, "Isochronous Priority Control: %s\n",
- str_yes_no(dev_priv->ipc_enabled));
+ str_yes_no(intel_ipc_is_enabled(dev_priv)));
return 0;
}
@@ -1015,11 +1016,11 @@ static ssize_t i915_ipc_status_write(struct file *file,
const char __user *ubuf,
return ret;
with_intel_runtime_pm(_priv->runtime_pm, wakeref) {
- if (!dev_priv->ipc_enabled && enable)
+ if (!intel_ipc_is_enabled(dev_priv) && enable)
drm_info(_priv->drm,
"Enabling IPC: WM will be proper only after
next commit\n");
dev_priv->ipc_enabled = enable;
- intel_enable_ipc(dev_priv);
+ intel_ipc_enable(dev_priv);
}
return len;
diff --git a/drivers/gpu/drm/i915/display/intel_ipc.c
b/drivers/gpu/drm/i915/display/intel_ipc.c
new file mode 100644
index ..71afec42d374
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_ipc.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#include "i915_drv.h"
+#include "i915_reg.h"
+#include "intel_ipc.h"
+#include "intel_uncore.h"
+
+bool intel_ipc_is_enabled(struct drm_i915_private *i915)
+{
+ return i915->ipc_enabled;
+}
+
+void intel_ipc_enable(struct drm_i915_private *i915)
+{
+ u32 val;
+
+ if (!HAS_IPC(i915))
+ return;
+
+ val = intel_uncore_read(>uncore, DISP_ARB_CTL2);
+
+ if (intel_ipc_is_enabled(i915))
+ val |= DISP_IPC_ENABLE;
+ else
+ val &= ~DISP_IPC_ENABLE;
+
+
[Intel-gfx] [PATCH 0/5] drm/i915: ipc and display sub-struct refactoring
This display sub-struct refactoring turned into ipc refactoring... Jani Nikula (5): drm/i915/ipc: split out intel_ipc.[ch] drm/i915/ipc: move IPC debugfs to intel_ipc.c drm/i915/ipc: register debugfs only if IPC available drm/i915/display: move IPC under display sub-struct drm/i915/display: move hdport under display sub-struct drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/display/intel_ddi.c | 4 +- drivers/gpu/drm/i915/display/intel_display.c | 9 +- .../gpu/drm/i915/display/intel_display_core.h | 14 +++ .../drm/i915/display/intel_display_debugfs.c | 55 + drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 4 +- drivers/gpu/drm/i915/display/intel_ipc.c | 116 ++ drivers/gpu/drm/i915/display/intel_ipc.h | 18 +++ drivers/gpu/drm/i915/i915_driver.c| 3 +- drivers/gpu/drm/i915/i915_drv.h | 10 -- drivers/gpu/drm/i915/intel_pm.c | 47 +-- drivers/gpu/drm/i915/intel_pm.h | 2 - 12 files changed, 165 insertions(+), 118 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_ipc.c create mode 100644 drivers/gpu/drm/i915/display/intel_ipc.h -- 2.34.1
[Intel-gfx] [PATCH 3/5] drm/i915/xelpmp: Expose media as another GT
From: Matt Roper
Xe_LPM+ platforms have "standalone media." I.e., the media unit is
designed as an additional GT with its own engine list, GuC, forcewake,
etc. Let's allow platforms to include media GTs in their device info.
Cc: Aravind Iddamsetty
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/gt/intel_gt.c | 12 ++--
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 8 +
drivers/gpu/drm/i915/gt/intel_sa_media.c | 39
drivers/gpu/drm/i915/gt/intel_sa_media.h | 15 +
drivers/gpu/drm/i915/i915_pci.c | 15 +
drivers/gpu/drm/i915/intel_device_info.h | 5 ++-
drivers/gpu/drm/i915/intel_uncore.c | 16 --
drivers/gpu/drm/i915/intel_uncore.h | 20 ++--
9 files changed, 123 insertions(+), 8 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_sa_media.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_sa_media.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 522ef9b4aff3..e83e4cd46968 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -123,6 +123,7 @@ gt-y += \
gt/intel_ring.o \
gt/intel_ring_submission.o \
gt/intel_rps.o \
+ gt/intel_sa_media.o \
gt/intel_sseu.o \
gt/intel_sseu_debugfs.o \
gt/intel_timeline.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 57a6488c0e14..bfe77d01f747 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -776,10 +776,15 @@ void intel_gt_driver_late_release_all(struct
drm_i915_private *i915)
}
}
-static int intel_gt_tile_setup(struct intel_gt *gt, phys_addr_t phys_addr)
+static int intel_gt_tile_setup(struct intel_gt *gt,
+ phys_addr_t phys_addr,
+ u32 gsi_offset)
{
int ret;
+ /* GSI offset is only applicable for media GTs */
+ drm_WARN_ON(>i915->drm, gsi_offset);
+
if (!gt_is_root(gt)) {
struct intel_uncore_mmio_debug *mmio_debug;
struct intel_uncore *uncore;
@@ -840,7 +845,7 @@ int intel_gt_probe_all(struct drm_i915_private *i915)
gt->info.engine_mask = RUNTIME_INFO(i915)->platform_engine_mask;
drm_dbg(>drm, "Setting up %s\n", gt->name);
- ret = intel_gt_tile_setup(gt, phys_addr);
+ ret = intel_gt_tile_setup(gt, phys_addr, 0);
if (ret)
return ret;
@@ -873,7 +878,8 @@ int intel_gt_probe_all(struct drm_i915_private *i915)
goto err;
}
- ret = gtdef->setup(gt, phys_addr + gtdef->mapping_base);
+ ret = gtdef->setup(gt, phys_addr + gtdef->mapping_base,
+ gtdef->gsi_offset);
if (ret)
goto err;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index d414785003cc..fb2c56777480 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1578,4 +1578,12 @@
#define GEN12_SFC_DONE(n) _MMIO(0x1cc000 + (n) * 0x1000)
+/*
+ * Standalone Media's non-engine GT registers are located at their regular GT
+ * offsets plus 0x38. This extra offset is stored inside the intel_uncore
+ * structure so that the existing code can be used for both GTs without
+ * modification.
+ */
+#define MTL_MEDIA_GSI_BASE 0x38
+
#endif /* __INTEL_GT_REGS__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_sa_media.c
b/drivers/gpu/drm/i915/gt/intel_sa_media.c
new file mode 100644
index ..8c5c519457cc
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_sa_media.c
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#include
+
+#include "i915_drv.h"
+#include "gt/intel_gt.h"
+#include "gt/intel_sa_media.h"
+
+int intel_sa_mediagt_setup(struct intel_gt *gt, phys_addr_t phys_addr,
+ u32 gsi_offset)
+{
+ struct drm_i915_private *i915 = gt->i915;
+ struct intel_uncore *uncore;
+
+ uncore = drmm_kzalloc(>drm, sizeof(*uncore), GFP_KERNEL);
+ if (!uncore)
+ return -ENOMEM;
+
+ uncore->gsi_offset = gsi_offset;
+
+ intel_gt_common_init_early(gt);
+ intel_uncore_init_early(uncore, gt);
+
+ /*
+* Standalone media shares the general MMIO space with the primary
+* GT. We'll re-use the primary GT's mapping.
+*/
+ uncore->regs = i915->uncore.regs;
+ if (drm_WARN_ON(>drm, uncore->regs == NULL))
+ return -EIO;
+
+ gt->uncore = uncore;
+ gt->phys_addr = phys_addr;
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/i915/gt/intel_sa_media.h
b/drivers/gpu/drm/i915/gt/intel_sa_media.h
new file mode 100644
index
[Intel-gfx] [PATCH 1/5] drm/i915: Prepare more multi-GT initialization
From: Matt Roper
We're going to introduce an additional intel_gt for MTL's media unit
soon. Let's provide a bit more multi-GT initialization framework in
preparation for that. The initialization will pull the list of GTs for
a platform from the device info structure. Although necessary for the
immediate MTL media enabling, this same framework will also be used
farther down the road when we enable remote tiles on xehpsdv and pvc.
v2:
- Re-add missing test for !HAS_EXTRA_GT_LIST in intel_gt_probe_all().
Cc: Aravind Iddamsetty
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt.c| 54 ---
drivers/gpu/drm/i915/gt/intel_gt.h| 1 -
drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 ++
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/intel_device_info.h | 16 ++
.../gpu/drm/i915/selftests/mock_gem_device.c | 1 +
7 files changed, 70 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 275ad72940c1..41acc285e8bf 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -736,7 +736,7 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt
*gt)
u16 vdbox_mask;
u16 vebox_mask;
- info->engine_mask = RUNTIME_INFO(i915)->platform_engine_mask;
+ GEM_BUG_ON(!info->engine_mask);
if (GRAPHICS_VER(i915) < 11)
return info->engine_mask;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index e4bac2431e41..5b4263c708cc 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -815,20 +815,16 @@ static void
intel_gt_tile_cleanup(struct intel_gt *gt)
{
intel_uncore_cleanup_mmio(gt->uncore);
-
- if (!gt_is_root(gt)) {
- kfree(gt->uncore->debug);
- kfree(gt->uncore);
- kfree(gt);
- }
}
int intel_gt_probe_all(struct drm_i915_private *i915)
{
struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
struct intel_gt *gt = >gt0;
+ const struct intel_gt_definition *gtdef;
phys_addr_t phys_addr;
unsigned int mmio_bar;
+ unsigned int i;
int ret;
mmio_bar = GRAPHICS_VER(i915) == 2 ? GEN2_GTTMMADR_BAR : GTTMMADR_BAR;
@@ -839,14 +835,58 @@ int intel_gt_probe_all(struct drm_i915_private *i915)
* and it has been already initialized early during probe
* in i915_driver_probe()
*/
+ gt->i915 = i915;
+ gt->name = "Primary GT";
+ gt->info.engine_mask = RUNTIME_INFO(i915)->platform_engine_mask;
+
+ drm_dbg(>drm, "Setting up %s\n", gt->name);
ret = intel_gt_tile_setup(gt, phys_addr);
if (ret)
return ret;
i915->gt[0] = gt;
- /* TODO: add more tiles */
+ if (!HAS_EXTRA_GT_LIST(i915))
+ return 0;
+
+ for (i = 1, gtdef = _INFO(i915)->extra_gt_list[i - 1];
+gtdef->setup != NULL;
+i++, gtdef = _INFO(i915)->extra_gt_list[i - 1]) {
+ gt = drmm_kzalloc(>drm, sizeof(*gt), GFP_KERNEL);
+ if (!gt) {
+ ret = -ENOMEM;
+ goto err;
+ }
+
+ gt->i915 = i915;
+ gt->name = gtdef->name;
+ gt->type = gtdef->type;
+ gt->info.engine_mask = gtdef->engine_mask;
+ gt->info.id = i;
+
+ drm_dbg(>drm, "Setting up %s\n", gt->name);
+ if (GEM_WARN_ON(range_overflows_t(resource_size_t,
+ gtdef->mapping_base,
+ SZ_16M,
+ pci_resource_len(pdev,
mmio_bar {
+ ret = -ENODEV;
+ goto err;
+ }
+
+ ret = gtdef->setup(gt, phys_addr + gtdef->mapping_base);
+ if (ret)
+ goto err;
+
+ i915->gt[i] = gt;
+ }
+
return 0;
+
+err:
+ i915_probe_error(i915, "Failed to initialize %s! (%d)\n", gtdef->name,
ret);
+ intel_gt_release_all(i915);
+
+ return ret;
}
int intel_gt_tiles_init(struct drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h
b/drivers/gpu/drm/i915/gt/intel_gt.h
index 40b06adf509a..4d8779529cc2 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -54,7 +54,6 @@ void intel_gt_driver_register(struct intel_gt *gt);
void intel_gt_driver_unregister(struct intel_gt *gt);
void intel_gt_driver_remove(struct intel_gt *gt);
void intel_gt_driver_release(struct intel_gt *gt);
-
void intel_gt_driver_late_release_all(struct drm_i915_private *i915);
int
[Intel-gfx] [PATCH 2/5] drm/i915: Rename and expose common GT early init routine
From: Matt Roper
The common early GT init is needed for initialization of all GT types
(root/primary, remote tile, standalone media). Since standalone media
(coming in the next patch) will be implemented in a separate file,
rename and expose the function for use.
Signed-off-by: Matt Roper
Reviewed-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/gt/intel_gt.c | 6 +++---
drivers/gpu/drm/i915/gt/intel_gt.h | 1 +
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 5b4263c708cc..57a6488c0e14 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -35,7 +35,7 @@
#include "intel_uncore.h"
#include "shmem_utils.h"
-static void __intel_gt_init_early(struct intel_gt *gt)
+void intel_gt_common_init_early(struct intel_gt *gt)
{
spin_lock_init(>irq_lock);
@@ -65,7 +65,7 @@ void intel_root_gt_init_early(struct drm_i915_private *i915)
gt->i915 = i915;
gt->uncore = >uncore;
- __intel_gt_init_early(gt);
+ intel_gt_common_init_early(gt);
}
static int intel_gt_probe_lmem(struct intel_gt *gt)
@@ -797,7 +797,7 @@ static int intel_gt_tile_setup(struct intel_gt *gt,
phys_addr_t phys_addr)
gt->uncore = uncore;
gt->uncore->debug = mmio_debug;
- __intel_gt_init_early(gt);
+ intel_gt_common_init_early(gt);
}
intel_uncore_init_early(gt->uncore, gt);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h
b/drivers/gpu/drm/i915/gt/intel_gt.h
index 4d8779529cc2..c9a359f35d0f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -44,6 +44,7 @@ static inline struct intel_gt *gsc_to_gt(struct intel_gsc
*gsc)
return container_of(gsc, struct intel_gt, gsc);
}
+void intel_gt_common_init_early(struct intel_gt *gt);
void intel_root_gt_init_early(struct drm_i915_private *i915);
int intel_gt_assign_ggtt(struct intel_gt *gt);
int intel_gt_init_mmio(struct intel_gt *gt);
--
2.25.1
[Intel-gfx] [PATCH 0/5] i915: CAGF and RC6 changes for MTL
This series includes the code changes to get CAGF, RC State and C6 Residency of MTL. The series depends on: https://patchwork.freedesktop.org/series/107908/ We have included 3 patches from from the above series as part of this series in order for this series to compile. These are the first 3 patches authored by Matt Roper. Please do not review these first 3 patches. Only patch 4 and 5 needs review. Cc: Ashutosh Dixit Badal Nilawar (2): INTEL_DII: drm/i915/mtl: Modify CAGF functions for MTL INTEL_DII: drm/i915/mtl: Add C6 residency support for MTL SAMedia Matt Roper (3): drm/i915: Prepare more multi-GT initialization drm/i915: Rename and expose common GT early init routine drm/i915/xelpmp: Expose media as another GT drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +- drivers/gpu/drm/i915/gt/intel_gt.c| 70 +++ drivers/gpu/drm/i915/gt/intel_gt.h| 2 +- drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 56 +++ drivers/gpu/drm/i915/gt/intel_gt_regs.h | 26 +++ drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 9 ++- drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 + drivers/gpu/drm/i915/gt/intel_rc6.c | 5 +- drivers/gpu/drm/i915/gt/intel_rps.c | 5 ++ drivers/gpu/drm/i915/gt/intel_sa_media.c | 39 +++ drivers/gpu/drm/i915/gt/intel_sa_media.h | 15 drivers/gpu/drm/i915/gt/selftest_rc6.c| 9 ++- drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu/drm/i915/i915_pci.c | 15 drivers/gpu/drm/i915/i915_pmu.c | 8 ++- drivers/gpu/drm/i915/intel_device_info.h | 19 + drivers/gpu/drm/i915/intel_uncore.c | 16 - drivers/gpu/drm/i915/intel_uncore.h | 20 +- .../gpu/drm/i915/selftests/mock_gem_device.c | 1 + 20 files changed, 301 insertions(+), 22 deletions(-) create mode 100644 drivers/gpu/drm/i915/gt/intel_sa_media.c create mode 100644 drivers/gpu/drm/i915/gt/intel_sa_media.h -- 2.25.1
Re: [Intel-gfx] [PATCH] drm/i915: do not reset PLANE_SURF on plane disable on older gens
On Mon, Sep 05, 2022 at 07:02:40PM +0200, Andrzej Hajda wrote: > > > On 05.09.2022 13:48, Ville Syrjälä wrote: > > On Mon, Sep 05, 2022 at 10:05:00AM +0200, Andrzej Hajda wrote: > >> In case of ICL and older generations disabling plane and/or disabling > >> async update is always performed on vblank, > > It should only be broken on bdw-glk (see. need_async_flip_disable_wa). > > On CFL it is reported every drmtip run: > https://intel-gfx-ci.01.org/tree/drm-tip/drmtip.html?testfilter=tiled-max-hw > https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_1209/fi-cfl-8109u/igt@kms_big...@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html#dmesg-warnings402 > https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_1209/fi-cfl-8109u/igt@kms_big...@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html#dmesg-warnings402 > https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_1209/fi-cfl-8109u/igt@kms_big...@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html > https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_1208/fi-cfl-8109u/igt@kms_big...@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html > ... > On APL it is less frequent, probably due to other bugs preventing run of > this test, last seen at: > https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_1190/fi-apl-guc/igt@kms_big...@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html > Similar for SKL: > https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_1181/fi-skl-guc/igt@kms_big...@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html > > I am not sure if I correctly read the docs but [1] says that 9th bit of > PLANE_CFG (Async Address Update Enable) is "not double buffered and the > changes will apply immediately" only for ICL, JSL, LKF1. It got broken in bdw and fixed again in icl. > So the change is not necessary in case of icl_plane_disable_arm. > > [1]: https://gfxspecs.intel.com/Predator/Home/Index/7656 > > > >> but if async update is enabled > >> PLANE_SURF register is updated asynchronously. Writing 0 to PLANE_SURF > >> when plane is still enabled can cause DMAR/PIPE errors. > >> On the other side PLANE_SURF is used to arm plane registers - we need to > >> write to it to trigger update on VBLANK, writting current value should > >> be safe - the buffer address is valid till vblank. > > I think you're effectively saying that somehow the async > > flip disable w/a is not kicking in sometimes. > > I was not aware of existence of this w/a and I am little lost in > figuring out how this w/a can prevent zeroing PLANE_SURF too early. When it works as designed it should: 1. turn off the async flip bit 2. wait for vblank so that gets latched 3. do the sync plane update/disable normally -- Ville Syrjälä Intel
Re: [Intel-gfx] [PATCH] drm/i915: do not reset PLANE_SURF on plane disable on older gens
On 05.09.2022 13:48, Ville Syrjälä wrote: On Mon, Sep 05, 2022 at 10:05:00AM +0200, Andrzej Hajda wrote: In case of ICL and older generations disabling plane and/or disabling async update is always performed on vblank, It should only be broken on bdw-glk (see. need_async_flip_disable_wa). On CFL it is reported every drmtip run: https://intel-gfx-ci.01.org/tree/drm-tip/drmtip.html?testfilter=tiled-max-hw https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_1209/fi-cfl-8109u/igt@kms_big...@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html#dmesg-warnings402 https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_1209/fi-cfl-8109u/igt@kms_big...@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html#dmesg-warnings402 https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_1209/fi-cfl-8109u/igt@kms_big...@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_1208/fi-cfl-8109u/igt@kms_big...@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html ... On APL it is less frequent, probably due to other bugs preventing run of this test, last seen at: https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_1190/fi-apl-guc/igt@kms_big...@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html Similar for SKL: https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_1181/fi-skl-guc/igt@kms_big...@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html I am not sure if I correctly read the docs but [1] says that 9th bit of PLANE_CFG (Async Address Update Enable) is "not double buffered and the changes will apply immediately" only for ICL, JSL, LKF1. So the change is not necessary in case of icl_plane_disable_arm. [1]: https://gfxspecs.intel.com/Predator/Home/Index/7656 but if async update is enabled PLANE_SURF register is updated asynchronously. Writing 0 to PLANE_SURF when plane is still enabled can cause DMAR/PIPE errors. On the other side PLANE_SURF is used to arm plane registers - we need to write to it to trigger update on VBLANK, writting current value should be safe - the buffer address is valid till vblank. I think you're effectively saying that somehow the async flip disable w/a is not kicking in sometimes. I was not aware of existence of this w/a and I am little lost in figuring out how this w/a can prevent zeroing PLANE_SURF too early. Regards Andrzej Signed-off-by: Andrzej Hajda --- drivers/gpu/drm/i915/display/skl_universal_plane.c | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index bcfde81e4d0866..bc9ed60a2d349e 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -615,11 +615,13 @@ skl_plane_disable_arm(struct intel_plane *plane, struct drm_i915_private *dev_priv = to_i915(plane->base.dev); enum plane_id plane_id = plane->id; enum pipe pipe = plane->pipe; + u32 plane_surf; skl_write_plane_wm(plane, crtc_state); intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), 0); - intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 0); + plane_surf = intel_de_read_fw(dev_priv, PLANE_SURF(pipe, plane_id)); + intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), plane_surf); } static void @@ -629,6 +631,7 @@ icl_plane_disable_arm(struct intel_plane *plane, struct drm_i915_private *dev_priv = to_i915(plane->base.dev); enum plane_id plane_id = plane->id; enum pipe pipe = plane->pipe; + u32 plane_surf; if (icl_is_hdr_plane(dev_priv, plane_id)) intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id), 0); @@ -637,7 +640,8 @@ icl_plane_disable_arm(struct intel_plane *plane, intel_psr2_disable_plane_sel_fetch(plane, crtc_state); intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), 0); - intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 0); + plane_surf = intel_de_read_fw(dev_priv, PLANE_SURF(pipe, plane_id)); + intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), plane_surf); } static bool -- 2.25.1
Re: [Intel-gfx] [PATCH 5/5] drm/i915: split out i915_gem.c declarations to i915_gem.h
On 05/09/2022 16:00, Jani Nikula wrote: Declutter i915_drv.h by splitting out the declarations for i915_gem.[ch]. Add a fixme comment about the rest of the stuff in i915_gem.h that doesn't really belong there. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_drv.h | 36 --- drivers/gpu/drm/i915/i915_gem.h | 43 + 2 files changed, 43 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index bbfc295f386b..befb167b3c49 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -972,42 +972,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define HAS_ONE_EU_PER_FUSE_BIT(i915) (INTEL_INFO(i915)->has_one_eu_per_fuse_bit) -/* i915_gem.c */ -void i915_gem_init_early(struct drm_i915_private *dev_priv); -void i915_gem_cleanup_early(struct drm_i915_private *dev_priv); - -void i915_gem_drain_freed_objects(struct drm_i915_private *i915); -void i915_gem_drain_workqueue(struct drm_i915_private *i915); - -struct i915_vma * __must_check -i915_gem_object_ggtt_pin_ww(struct drm_i915_gem_object *obj, - struct i915_gem_ww_ctx *ww, - const struct i915_ggtt_view *view, - u64 size, u64 alignment, u64 flags); - -struct i915_vma * __must_check -i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, -const struct i915_ggtt_view *view, -u64 size, u64 alignment, u64 flags); - -int i915_gem_object_unbind(struct drm_i915_gem_object *obj, - unsigned long flags); -#define I915_GEM_OBJECT_UNBIND_ACTIVE BIT(0) -#define I915_GEM_OBJECT_UNBIND_BARRIER BIT(1) -#define I915_GEM_OBJECT_UNBIND_TEST BIT(2) -#define I915_GEM_OBJECT_UNBIND_VM_TRYLOCK BIT(3) -#define I915_GEM_OBJECT_UNBIND_ASYNC BIT(4) - -void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv); - -int __must_check i915_gem_init(struct drm_i915_private *dev_priv); -void i915_gem_driver_register(struct drm_i915_private *i915); -void i915_gem_driver_unregister(struct drm_i915_private *i915); -void i915_gem_driver_remove(struct drm_i915_private *dev_priv); -void i915_gem_driver_release(struct drm_i915_private *dev_priv); - -int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file); - /* intel_device_info.c */ static inline struct intel_device_info * mkwrite_device_info(struct drm_i915_private *dev_priv) diff --git a/drivers/gpu/drm/i915/i915_gem.h b/drivers/gpu/drm/i915/i915_gem.h index 68d8d52bd541..2fccb19ed9f7 100644 --- a/drivers/gpu/drm/i915/i915_gem.h +++ b/drivers/gpu/drm/i915/i915_gem.h @@ -26,12 +26,55 @@ #define __I915_GEM_H__ #include +#include #include #include "i915_utils.h" +struct drm_file; +struct drm_i915_gem_object; struct drm_i915_private; +struct i915_gem_ww_ctx; +struct i915_ggtt_view; +struct i915_vma; + +void i915_gem_init_early(struct drm_i915_private *i915); +void i915_gem_cleanup_early(struct drm_i915_private *i915); + +void i915_gem_drain_freed_objects(struct drm_i915_private *i915); +void i915_gem_drain_workqueue(struct drm_i915_private *i915); + +struct i915_vma * __must_check +i915_gem_object_ggtt_pin_ww(struct drm_i915_gem_object *obj, + struct i915_gem_ww_ctx *ww, + const struct i915_ggtt_view *view, + u64 size, u64 alignment, u64 flags); + +struct i915_vma * __must_check +i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, +const struct i915_ggtt_view *view, +u64 size, u64 alignment, u64 flags); + +int i915_gem_object_unbind(struct drm_i915_gem_object *obj, + unsigned long flags); +#define I915_GEM_OBJECT_UNBIND_ACTIVE BIT(0) +#define I915_GEM_OBJECT_UNBIND_BARRIER BIT(1) +#define I915_GEM_OBJECT_UNBIND_TEST BIT(2) +#define I915_GEM_OBJECT_UNBIND_VM_TRYLOCK BIT(3) +#define I915_GEM_OBJECT_UNBIND_ASYNC BIT(4) + +void i915_gem_runtime_suspend(struct drm_i915_private *i915); + +int __must_check i915_gem_init(struct drm_i915_private *i915); +void i915_gem_driver_register(struct drm_i915_private *i915); +void i915_gem_driver_unregister(struct drm_i915_private *i915); +void i915_gem_driver_remove(struct drm_i915_private *i915); +void i915_gem_driver_release(struct drm_i915_private *i915); + +int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file); + +/* FIXME: All of the below belong somewhere else. */ For the series: Reviewed-by: Tvrtko Ursulin ((( I think historically i915_gem.h started as a stash for random bits which felt obviously wrong to put elsewhere, but it should be fine to "upgrade" it to a more important status now that you are working on cleaning things up, especially i915_drv.h. Where this "somewhere else" place could be is a bit tricky - I suspect there isn't any great urgency to
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: i915_drv.h > i915_gem.h cleanup
== Series Details ==
Series: drm/i915: i915_drv.h > i915_gem.h cleanup
URL : https://patchwork.freedesktop.org/series/108150/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12073 -> Patchwork_108150v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108150v1/index.html
Participating hosts (39 -> 42)
--
Additional (6): fi-skl-guc bat-dg2-9 fi-ilk-650 fi-kbl-x1275 fi-blb-e6850
fi-bsw-nick
Missing(3): bat-dg2-8 fi-icl-u2 fi-bdw-samus
Known issues
Here are the changes found in Patchwork_108150v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-bsw-nick:NOTRUN -> [SKIP][1] ([fdo#109271]) +38 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108150v1/fi-bsw-nick/igt@gem_lmem_swapp...@parallel-random-engines.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-ilk-650: NOTRUN -> [SKIP][2] ([fdo#109271]) +19 similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108150v1/fi-ilk-650/igt@i915_pm_...@basic-pci-d3-state.html
* igt@i915_pm_rpm@module-reload:
- fi-blb-e6850: NOTRUN -> [SKIP][3] ([fdo#109271]) +42 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108150v1/fi-blb-e6850/igt@i915_pm_...@module-reload.html
* igt@i915_selftest@live@requests:
- fi-blb-e6850: NOTRUN -> [DMESG-FAIL][4] ([i915#4528])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108150v1/fi-blb-e6850/igt@i915_selftest@l...@requests.html
- fi-pnv-d510:[PASS][5] -> [DMESG-FAIL][6] ([i915#4528])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/fi-pnv-d510/igt@i915_selftest@l...@requests.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108150v1/fi-pnv-d510/igt@i915_selftest@l...@requests.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770:NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108150v1/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_chamelium@hdmi-edid-read:
- fi-ilk-650: NOTRUN -> [SKIP][8] ([fdo#109271] / [fdo#111827]) +8
similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108150v1/fi-ilk-650/igt@kms_chamel...@hdmi-edid-read.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-bsw-nick:NOTRUN -> [SKIP][9] ([fdo#109271] / [fdo#111827]) +8
similar issues
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108150v1/fi-bsw-nick/igt@kms_chamel...@hdmi-hpd-fast.html
* igt@runner@aborted:
- fi-kbl-x1275: NOTRUN -> [FAIL][10] ([i915#6219])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108150v1/fi-kbl-x1275/igt@run...@aborted.html
- fi-blb-e6850: NOTRUN -> [FAIL][11] ([fdo#109271] / [i915#2403] /
[i915#4312])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108150v1/fi-blb-e6850/igt@run...@aborted.html
- fi-bdw-5557u: NOTRUN -> [FAIL][12] ([i915#4312])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108150v1/fi-bdw-5557u/igt@run...@aborted.html
- fi-skl-guc: NOTRUN -> [FAIL][13] ([i915#6599])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108150v1/fi-skl-guc/igt@run...@aborted.html
Possible fixes
* igt@gem_exec_suspend@basic-s3@smem:
- {bat-rplp-1}: [DMESG-WARN][14] ([i915#2867]) -> [PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108150v1/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[INCOMPLETE][16] ([i915#4785]) -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108150v1/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@hugepages:
- {bat-rpls-1}: [DMESG-WARN][18] ([i915#5278]) -> [PASS][19]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/bat-rpls-1/igt@i915_selftest@l...@hugepages.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108150v1/bat-rpls-1/igt@i915_selftest@l...@hugepages.html
* igt@i915_selftest@live@slpc:
- {bat-rpls-1}: [DMESG-FAIL][20] ([i915#6367]) -> [PASS][21]
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/bat-rpls-1/igt@i915_selftest@l...@slpc.html
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108150v1/bat-rpls-1/igt@i915_selftest@l...@slpc.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-bdw-5557u: [INCOMPLETE][22]
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: i915_drv.h > i915_gem.h cleanup
== Series Details ==
Series: drm/i915: i915_drv.h > i915_gem.h cleanup
URL : https://patchwork.freedesktop.org/series/108150/
State : warning
== Summary ==
Error: dim checkpatch failed
f236979564b6 drm/i915: remove unused macro I915_GTT_OFFSET_NONE
5b8a57bcb98c drm/i915: remove unused i915_gem_set_global_seqno() declaration
-:7: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+
chars of sha1> ("")' - ie: 'commit 6faf5916e6be ("drm/i915: Remove
HW semaphores for gen7 inter-engine synchronisation")'
#7:
The function was removed four years ago in commit 6faf5916e6be
total: 1 errors, 0 warnings, 0 checks, 8 lines checked
a6f5f4a4d781 drm/i915: un-inline i915_gem_drain_workqueue()
45635a32d093 drm/i915: un-inline i915_gem_drain_freed_objects()
56caaf19ce3f drm/i915: split out i915_gem.c declarations to i915_gem.h
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/psr: Disable PSR2 when SDP is sent on prior line
== Series Details == Series: drm/i915/psr: Disable PSR2 when SDP is sent on prior line URL : https://patchwork.freedesktop.org/series/108137/ State : success == Summary == CI Bug Log - changes from CI_DRM_12071_full -> Patchwork_108137v1_full Summary --- **SUCCESS** No regressions found. Participating hosts (11 -> 12) -- Additional (1): shard-rkl New tests - New tests have been introduced between CI_DRM_12071_full and Patchwork_108137v1_full: ### New IGT tests (1) ### * igt@kms_plane_multiple@tiling-y@pipe-d-hdmi-a-1: - Statuses : 1 pass(s) - Exec time: [0.29] s Known issues Here are the changes found in Patchwork_108137v1_full that come from known issues: ### CI changes ### Issues hit * boot: - shard-snb: ([PASS][1], [PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25]) -> ([PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [FAIL][50]) ([i915#4338]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12071/shard-snb7/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12071/shard-snb7/boot.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12071/shard-snb7/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12071/shard-snb7/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12071/shard-snb6/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12071/shard-snb6/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12071/shard-snb6/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12071/shard-snb6/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12071/shard-snb5/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12071/shard-snb5/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12071/shard-snb5/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12071/shard-snb5/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12071/shard-snb5/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12071/shard-snb4/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12071/shard-snb4/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12071/shard-snb4/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12071/shard-snb4/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12071/shard-snb4/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12071/shard-snb2/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12071/shard-snb2/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12071/shard-snb2/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12071/shard-snb2/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12071/shard-snb2/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12071/shard-snb2/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12071/shard-snb2/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108137v1/shard-snb5/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108137v1/shard-snb5/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108137v1/shard-snb5/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108137v1/shard-snb5/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108137v1/shard-snb4/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108137v1/shard-snb4/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108137v1/shard-snb2/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108137v1/shard-snb2/boot.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108137v1/shard-snb2/boot.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108137v1/shard-snb2/boot.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108137v1/shard-snb2/boot.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108137v1/shard-snb4/boot.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108137v1/shard-snb4/boot.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108137v1/shard-snb4/boot.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108137v1/shard-snb7/boot.html
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: consider HAS_FLAT_CCS() in needs_ccs_pages
== Series Details == Series: drm/i915: consider HAS_FLAT_CCS() in needs_ccs_pages URL : https://patchwork.freedesktop.org/series/108139/ State : success == Summary == CI Bug Log - changes from CI_DRM_12073 -> Patchwork_108139v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108139v1/index.html Participating hosts (39 -> 43) -- Additional (6): fi-rkl-11600 fi-skl-guc fi-ilk-650 fi-kbl-x1275 fi-blb-e6850 fi-bsw-nick Missing(2): fi-icl-u2 fi-bdw-samus Known issues Here are the changes found in Patchwork_108139v1 that come from known issues: ### IGT changes ### Issues hit * igt@gem_huc_copy@huc-copy: - fi-rkl-11600: NOTRUN -> [SKIP][1] ([i915#2190]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108139v1/fi-rkl-11600/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@parallel-random-engines: - fi-bsw-nick:NOTRUN -> [SKIP][2] ([fdo#109271]) +38 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108139v1/fi-bsw-nick/igt@gem_lmem_swapp...@parallel-random-engines.html - fi-rkl-11600: NOTRUN -> [SKIP][3] ([i915#4613]) +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108139v1/fi-rkl-11600/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_tiled_pread_basic: - fi-rkl-11600: NOTRUN -> [SKIP][4] ([i915#3282]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108139v1/fi-rkl-11600/igt@gem_tiled_pread_basic.html * igt@i915_pm_backlight@basic-brightness: - fi-rkl-11600: NOTRUN -> [SKIP][5] ([i915#3012]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108139v1/fi-rkl-11600/igt@i915_pm_backli...@basic-brightness.html * igt@i915_pm_rpm@basic-pci-d3-state: - fi-ilk-650: NOTRUN -> [SKIP][6] ([fdo#109271]) +19 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108139v1/fi-ilk-650/igt@i915_pm_...@basic-pci-d3-state.html * igt@i915_pm_rpm@module-reload: - fi-blb-e6850: NOTRUN -> [SKIP][7] ([fdo#109271]) +42 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108139v1/fi-blb-e6850/igt@i915_pm_...@module-reload.html * igt@i915_selftest@live@gt_engines: - bat-dg1-5: [PASS][8] -> [INCOMPLETE][9] ([i915#4418]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/bat-dg1-5/igt@i915_selftest@live@gt_engines.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108139v1/bat-dg1-5/igt@i915_selftest@live@gt_engines.html * igt@i915_selftest@live@requests: - fi-blb-e6850: NOTRUN -> [DMESG-FAIL][10] ([i915#4528]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108139v1/fi-blb-e6850/igt@i915_selftest@l...@requests.html - fi-pnv-d510:[PASS][11] -> [DMESG-FAIL][12] ([i915#4528]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/fi-pnv-d510/igt@i915_selftest@l...@requests.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108139v1/fi-pnv-d510/igt@i915_selftest@l...@requests.html * igt@i915_selftest@live@ring_submission: - fi-cfl-8109u: [PASS][13] -> [DMESG-WARN][14] ([i915#5904]) +30 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/fi-cfl-8109u/igt@i915_selftest@live@ring_submission.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108139v1/fi-cfl-8109u/igt@i915_selftest@live@ring_submission.html * igt@i915_suspend@basic-s2idle-without-i915: - fi-cfl-8109u: [PASS][15] -> [DMESG-WARN][16] ([i915#5904] / [i915#62]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12073/fi-cfl-8109u/igt@i915_susp...@basic-s2idle-without-i915.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108139v1/fi-cfl-8109u/igt@i915_susp...@basic-s2idle-without-i915.html * igt@i915_suspend@basic-s3-without-i915: - fi-rkl-11600: NOTRUN -> [INCOMPLETE][17] ([i915#5982]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108139v1/fi-rkl-11600/igt@i915_susp...@basic-s3-without-i915.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-hsw-4770:NOTRUN -> [SKIP][18] ([fdo#109271] / [fdo#111827]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108139v1/fi-hsw-4770/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_chamelium@hdmi-edid-read: - fi-ilk-650: NOTRUN -> [SKIP][19] ([fdo#109271] / [fdo#111827]) +8 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108139v1/fi-ilk-650/igt@kms_chamel...@hdmi-edid-read.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-bsw-nick:NOTRUN -> [SKIP][20] ([fdo#109271] / [fdo#111827]) +8 similar issues [20]:
Re: [Intel-gfx] [RFC PATCH v3 10/17] drm/i915/vm_bind: Implement I915_GEM_EXECBUFFER3 ioctl
On 02/09/2022 06:41, Niranjana Vishwanathapura wrote:
On Thu, Sep 01, 2022 at 08:58:57AM +0100, Tvrtko Ursulin wrote:
On 01/09/2022 06:09, Niranjana Vishwanathapura wrote:
On Wed, Aug 31, 2022 at 08:38:48AM +0100, Tvrtko Ursulin wrote:
On 27/08/2022 20:43, Andi Shyti wrote:
From: Niranjana Vishwanathapura
Implement new execbuf3 ioctl (I915_GEM_EXECBUFFER3) which only
works in vm_bind mode. The vm_bind mode only works with
this new execbuf3 ioctl.
The new execbuf3 ioctl will not have any list of objects to validate
bind as all required objects binding would have been requested by the
userspace before submitting the execbuf3.
And the legacy support like relocations etc are removed.
Signed-off-by: Niranjana Vishwanathapura
Signed-off-by: Ramalingam C
Signed-off-by: Andi Shyti
---
[snip]
+static void signal_fence_array(const struct i915_execbuffer *eb,
+ struct dma_fence * const fence)
+{
+ unsigned int n;
+
+ for (n = 0; n < eb->num_fences; n++) {
+ struct drm_syncobj *syncobj;
+ unsigned int flags;
+
+ syncobj = ptr_unpack_bits(eb->fences[n].syncobj, , 2);
+ if (!(flags & I915_TIMELINE_FENCE_SIGNAL))
+ continue;
+
+ if (eb->fences[n].chain_fence) {
+ drm_syncobj_add_point(syncobj,
+ eb->fences[n].chain_fence,
+ fence,
+ eb->fences[n].value);
+ /*
+ * The chain's ownership is transferred to the
+ * timeline.
+ */
+ eb->fences[n].chain_fence = NULL;
+ } else {
+ drm_syncobj_replace_fence(syncobj, fence);
+ }
+ }
+}
Semi-random place to ask - how many of the code here is direct copy
of existing functions from i915_gem_execbuffer.c? There seems to be
some 100% copies at least. And then some more with small tweaks.
Spend some time and try to figure out some code sharing?
During VM_BIND design review, maintainers expressed thought on keeping
execbuf3 completely separate and not touch the legacy execbuf path.
Got a link so this maintainer can see what exactly was said? Just to
make sure there isn't any misunderstanding on what "completely
separate" means to different people.
Here is one (search for copypaste/copy-paste)
https://patchwork.freedesktop.org/patch/486608/?series=93447=3
It is hard to search for old discussion threads. May be maintainers
can provide feedback here directly. Dave, Daniel? :)
Thanks. I had a read and don't see a fundamental conflict with what I
said. Conclusion seemed to be to go with a new ioctl and implement code
sharing where it makes sense. Which is what TODO in the cover letter
acknowledges so there should be no disagreement really.
I also think, execbuf3 should be fully separate. We can do some code
sharing where is a close 100% copy (there is a TODO in cover letter).
There are some changes like the timeline fence array handling here
which looks similar, but the uapi is not exactly the same. Probably,
we should keep them separate and not try to force code sharing at
least at this point.
Okay did not spot that TODO in the cover. But fair since it is RFC to
be unfinished.
I do however think it should be improved before considering the merge.
Because looking at the patch, 100% copies are:
for_each_batch_create_order
for_each_batch_add_order
eb_throttle
eb_pin_timeline
eb_pin_engine
eb_put_engine
__free_fence_array
put_fence_array
await_fence_array
signal_fence_array
retire_requests
eb_request_add
eb_requests_get
eb_requests_put
eb_find_context
Quite a lot.
Then there is a bunch of almost same functions which could be shared
if there weren't two incompatible local struct i915_execbuffer's.
Especially given when the out fence TODO item gets handled a chunk
more will also become a 100% copy.
There are difinitely a few which is 100% copies hence should have a
shared code.
But some are not. Like, fence_array stuff though looks very similar,
the uapi structures are different between execbuf3 and legacy execbuf.
The internal flags are also different (eg., __EXEC3_ENGINE_PINNED vs
__EXEC_ENGINE_PINNED) which causes minor differences hence not a
100% copy.
So, I am not convinced if it is worth carrying legacy stuff into
execbuf3 code. I think we need to look at these on a case by case
basis and see if abstracting common functionality to a separate
shared code makes sense or it is better to keep the code separate.
No one is suggesting to carry any legacy stuff into eb3. What I'd
suggest is to start something like i915_gem_eb_common.h|c and stuff the
100% copies from the above list in there.
Common struct eb with struct eb2 and eb3 inheriting from it should do
the trick. Similarly eb->flags shouldn't be a hard problem to solve.
Then you see what remains and whether it makes sense to consolidate further.
Regards,
Tvrtko
This could be done by having a common struct i915_execbuffer and
[Intel-gfx] [PATCH 2/5] drm/i915: remove unused i915_gem_set_global_seqno() declaration
The function was removed four years ago in commit 6faf5916e6be
("drm/i915: Remove HW semaphores for gen7 inter-engine
synchronisation"). Finish the job.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c813d7906794..54898faa9b72 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1035,8 +1035,6 @@ int i915_gem_object_unbind(struct drm_i915_gem_object
*obj,
void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
-int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
-
int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
void i915_gem_driver_register(struct drm_i915_private *i915);
void i915_gem_driver_unregister(struct drm_i915_private *i915);
--
2.34.1
[Intel-gfx] [PATCH 5/5] drm/i915: split out i915_gem.c declarations to i915_gem.h
Declutter i915_drv.h by splitting out the declarations for i915_gem.[ch]. Add a fixme comment about the rest of the stuff in i915_gem.h that doesn't really belong there. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_drv.h | 36 --- drivers/gpu/drm/i915/i915_gem.h | 43 + 2 files changed, 43 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index bbfc295f386b..befb167b3c49 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -972,42 +972,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define HAS_ONE_EU_PER_FUSE_BIT(i915) (INTEL_INFO(i915)->has_one_eu_per_fuse_bit) -/* i915_gem.c */ -void i915_gem_init_early(struct drm_i915_private *dev_priv); -void i915_gem_cleanup_early(struct drm_i915_private *dev_priv); - -void i915_gem_drain_freed_objects(struct drm_i915_private *i915); -void i915_gem_drain_workqueue(struct drm_i915_private *i915); - -struct i915_vma * __must_check -i915_gem_object_ggtt_pin_ww(struct drm_i915_gem_object *obj, - struct i915_gem_ww_ctx *ww, - const struct i915_ggtt_view *view, - u64 size, u64 alignment, u64 flags); - -struct i915_vma * __must_check -i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, -const struct i915_ggtt_view *view, -u64 size, u64 alignment, u64 flags); - -int i915_gem_object_unbind(struct drm_i915_gem_object *obj, - unsigned long flags); -#define I915_GEM_OBJECT_UNBIND_ACTIVE BIT(0) -#define I915_GEM_OBJECT_UNBIND_BARRIER BIT(1) -#define I915_GEM_OBJECT_UNBIND_TEST BIT(2) -#define I915_GEM_OBJECT_UNBIND_VM_TRYLOCK BIT(3) -#define I915_GEM_OBJECT_UNBIND_ASYNC BIT(4) - -void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv); - -int __must_check i915_gem_init(struct drm_i915_private *dev_priv); -void i915_gem_driver_register(struct drm_i915_private *i915); -void i915_gem_driver_unregister(struct drm_i915_private *i915); -void i915_gem_driver_remove(struct drm_i915_private *dev_priv); -void i915_gem_driver_release(struct drm_i915_private *dev_priv); - -int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file); - /* intel_device_info.c */ static inline struct intel_device_info * mkwrite_device_info(struct drm_i915_private *dev_priv) diff --git a/drivers/gpu/drm/i915/i915_gem.h b/drivers/gpu/drm/i915/i915_gem.h index 68d8d52bd541..2fccb19ed9f7 100644 --- a/drivers/gpu/drm/i915/i915_gem.h +++ b/drivers/gpu/drm/i915/i915_gem.h @@ -26,12 +26,55 @@ #define __I915_GEM_H__ #include +#include #include #include "i915_utils.h" +struct drm_file; +struct drm_i915_gem_object; struct drm_i915_private; +struct i915_gem_ww_ctx; +struct i915_ggtt_view; +struct i915_vma; + +void i915_gem_init_early(struct drm_i915_private *i915); +void i915_gem_cleanup_early(struct drm_i915_private *i915); + +void i915_gem_drain_freed_objects(struct drm_i915_private *i915); +void i915_gem_drain_workqueue(struct drm_i915_private *i915); + +struct i915_vma * __must_check +i915_gem_object_ggtt_pin_ww(struct drm_i915_gem_object *obj, + struct i915_gem_ww_ctx *ww, + const struct i915_ggtt_view *view, + u64 size, u64 alignment, u64 flags); + +struct i915_vma * __must_check +i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, +const struct i915_ggtt_view *view, +u64 size, u64 alignment, u64 flags); + +int i915_gem_object_unbind(struct drm_i915_gem_object *obj, + unsigned long flags); +#define I915_GEM_OBJECT_UNBIND_ACTIVE BIT(0) +#define I915_GEM_OBJECT_UNBIND_BARRIER BIT(1) +#define I915_GEM_OBJECT_UNBIND_TEST BIT(2) +#define I915_GEM_OBJECT_UNBIND_VM_TRYLOCK BIT(3) +#define I915_GEM_OBJECT_UNBIND_ASYNC BIT(4) + +void i915_gem_runtime_suspend(struct drm_i915_private *i915); + +int __must_check i915_gem_init(struct drm_i915_private *i915); +void i915_gem_driver_register(struct drm_i915_private *i915); +void i915_gem_driver_unregister(struct drm_i915_private *i915); +void i915_gem_driver_remove(struct drm_i915_private *i915); +void i915_gem_driver_release(struct drm_i915_private *i915); + +int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file); + +/* FIXME: All of the below belong somewhere else. */ #ifdef CONFIG_DRM_I915_DEBUG_GEM -- 2.34.1
[Intel-gfx] [PATCH 4/5] drm/i915: un-inline i915_gem_drain_freed_objects()
I can't idenfity a single hot path that would require
i915_gem_drain_freed_objects() to be inline. Un-inline it.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 17 +
drivers/gpu/drm/i915/i915_gem.c | 15 +++
2 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 911164dae182..bbfc295f386b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -976,22 +976,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
void i915_gem_init_early(struct drm_i915_private *dev_priv);
void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
-static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
-{
- /*
-* A single pass should suffice to release all the freed objects (along
-* most call paths) , but be a little more paranoid in that freeing
-* the objects does take a little amount of time, during which the rcu
-* callbacks could have added new objects into the freed list, and
-* armed the work again.
-*/
- while (atomic_read(>mm.free_count)) {
- flush_work(>mm.free_work);
- flush_delayed_work(>bdev.wq);
- rcu_barrier();
- }
-}
-
+void i915_gem_drain_freed_objects(struct drm_i915_private *i915);
void i915_gem_drain_workqueue(struct drm_i915_private *i915);
struct i915_vma * __must_check
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 4c89b33ada95..0f49ec9d494a 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1085,6 +1085,21 @@ i915_gem_madvise_ioctl(struct drm_device *dev, void
*data,
return err;
}
+/*
+ * A single pass should suffice to release all the freed objects (along most
+ * call paths), but be a little more paranoid in that freeing the objects does
+ * take a little amount of time, during which the rcu callbacks could have
added
+ * new objects into the freed list, and armed the work again.
+ */
+void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
+{
+ while (atomic_read(>mm.free_count)) {
+ flush_work(>mm.free_work);
+ flush_delayed_work(>bdev.wq);
+ rcu_barrier();
+ }
+}
+
/*
* Similar to objects above (see i915_gem_drain_freed-objects), in general we
* have workers that are armed by RCU and then rearm themselves in their
--
2.34.1
[Intel-gfx] [PATCH 3/5] drm/i915: un-inline i915_gem_drain_workqueue()
i915_gem_drain_workqueue() is not used on any hot paths. Un-unline it.
Replace the do-while with a for loop while at it.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 22 +-
drivers/gpu/drm/i915/i915_gem.c | 22 ++
2 files changed, 23 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 54898faa9b72..911164dae182 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -992,27 +992,7 @@ static inline void i915_gem_drain_freed_objects(struct
drm_i915_private *i915)
}
}
-static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915)
-{
- /*
-* Similar to objects above (see i915_gem_drain_freed-objects), in
-* general we have workers that are armed by RCU and then rearm
-* themselves in their callbacks. To be paranoid, we need to
-* drain the workqueue a second time after waiting for the RCU
-* grace period so that we catch work queued via RCU from the first
-* pass. As neither drain_workqueue() nor flush_workqueue() report
-* a result, we make an assumption that we only don't require more
-* than 3 passes to catch all _recursive_ RCU delayed work.
-*
-*/
- int pass = 3;
- do {
- flush_workqueue(i915->wq);
- rcu_barrier();
- i915_gem_drain_freed_objects(i915);
- } while (--pass);
- drain_workqueue(i915->wq);
-}
+void i915_gem_drain_workqueue(struct drm_i915_private *i915);
struct i915_vma * __must_check
i915_gem_object_ggtt_pin_ww(struct drm_i915_gem_object *obj,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index c2d6172ba4bb..4c89b33ada95 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1085,6 +1085,28 @@ i915_gem_madvise_ioctl(struct drm_device *dev, void
*data,
return err;
}
+/*
+ * Similar to objects above (see i915_gem_drain_freed-objects), in general we
+ * have workers that are armed by RCU and then rearm themselves in their
+ * callbacks. To be paranoid, we need to drain the workqueue a second time
after
+ * waiting for the RCU grace period so that we catch work queued via RCU from
+ * the first pass. As neither drain_workqueue() nor flush_workqueue() report a
+ * result, we make an assumption that we only don't require more than 3 passes
+ * to catch all _recursive_ RCU delayed work.
+ */
+void i915_gem_drain_workqueue(struct drm_i915_private *i915)
+{
+ int i;
+
+ for (i = 0; i < 3; i++) {
+ flush_workqueue(i915->wq);
+ rcu_barrier();
+ i915_gem_drain_freed_objects(i915);
+ }
+
+ drain_workqueue(i915->wq);
+}
+
int i915_gem_init(struct drm_i915_private *dev_priv)
{
int ret;
--
2.34.1
[Intel-gfx] [PATCH 1/5] drm/i915: remove unused macro I915_GTT_OFFSET_NONE
Apparently the last user of the macro was removed in commit 9c4ce97d8025
("drm/i915/display: Be explicit in handling the preallocated vma").
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c9cca165bf5d..c813d7906794 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -459,8 +459,6 @@ static inline struct intel_gt *to_gt(struct
drm_i915_private *i915)
(engine__) && (engine__)->uabi_class == (class__); \
(engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
-#define I915_GTT_OFFSET_NONE ((u32)-1)
-
#define INTEL_INFO(dev_priv) (&(dev_priv)->__info)
#define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime)
#define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps)
--
2.34.1
[Intel-gfx] [PATCH 0/5] drm/i915: i915_drv.h > i915_gem.h cleanup
Some more i915_drv.h cleanup, move the i915_gem.h stuff there. Jani Nikula (5): drm/i915: remove unused macro I915_GTT_OFFSET_NONE drm/i915: remove unused i915_gem_set_global_seqno() declaration drm/i915: un-inline i915_gem_drain_workqueue() drm/i915: un-inline i915_gem_drain_freed_objects() drm/i915: split out i915_gem.c declarations to i915_gem.h drivers/gpu/drm/i915/i915_drv.h | 75 - drivers/gpu/drm/i915/i915_gem.c | 37 drivers/gpu/drm/i915/i915_gem.h | 43 +++ 3 files changed, 80 insertions(+), 75 deletions(-) -- 2.34.1
Re: [Intel-gfx] [PATCH v2 00/41] drm: Analog TV Improvements
On Fri, Sep 02, 2022 at 01:28:16PM +0200, Noralf Trønnes wrote: > > > Den 01.09.2022 21.35, skrev Noralf Trønnes: > > > > > > I have finally found a workaround for my kernel hangs. > > > > Dom had a look at my kernel and found that the VideoCore was fine, and > > he said this: > > > >> That suggests cause of lockup was on arm side rather than VC side. > >> > >> But it's hard to diagnose further. Once you've had a peripheral not > >> respond, the AXI bus locks up and no further operations are possible. > >> Usual causes of this are required clocks being stopped or domains > >> disabled and then trying to access the hardware. > >> > > > > So when I got this on my 64-bit build: > > > > [ 166.702171] SError Interrupt on CPU1, code 0xbf02 -- SError > > [ 166.702187] CPU: 1 PID: 8 Comm: kworker/u8:0 Tainted: GW > > 5.19.0-rc6-00096-gba7973977976-dirty #1 > > [ 166.702200] Hardware name: Raspberry Pi 4 Model B Rev 1.1 (DT) > > [ 166.702206] Workqueue: events_freezable_power_ thermal_zone_device_check > > [ 166.702231] pstate: 20c5 (nzCv daIF -PAN -UAO -TCO -DIT -SSBS > > BTYPE=--) > > [ 166.702242] pc : regmap_mmio_read32le+0x10/0x28 > > [ 166.702261] lr : regmap_mmio_read+0x44/0x70 > > ... > > [ 166.702606] bcm2711_get_temp+0x58/0xb0 [bcm2711_thermal] > > > > I wondered if that reg read was stalled due to a clock being stopped. > > > > Lo and behold, disabling runtime pm and keeping the vec clock running > > all the time fixed it[1]. > > > > I don't know what the problem is, but at least I can now test this patchset. > > > > [1] https://gist.github.com/notro/23b984e7fa05cfbda2db50a421cac065 > > > > It turns out I didn't have to disable runtime pm: > https://gist.github.com/notro/0adcfcb12460b54e54458afe11dc8ea2 If the bcm2711_thermal IP needs that clock to be enabled, it should grab a reference itself, but it looks like even the device tree binding doesn't ask for one. Maxime signature.asc Description: PGP signature
Re: [Intel-gfx] [PATCH v2 19/41] drm/modes: Introduce the tv_mode property as a command-line option
On Fri, Sep 02, 2022 at 12:46:29AM +0200, Mateusz Kwiatkowski wrote:
> > @@ -2212,20 +2239,22 @@ struct drm_named_mode {
> > unsigned int xres;
> > unsigned int yres;
> > unsigned int flags;
> > + unsigned int tv_mode;
> > };
>
> Are _all_ named modes supposed to be about analog TV?
>
> If so, then probably this structure should be renamed drm_named_analog_tv_mode
> or something.
I don't think they need to, but it's the only use case we've had so far.
We could also imagine using UHD for 3840x2160 for example, so I wouldn't
say it's limited to analog tv.
> If not, then including tv_mode in all of them sounds almost dangrous. 0 is a
> valid value for enum drm_connector_tv_mode, corresponding to
> DRM_MODE_TV_MODE_NTSC_443. This is a very weird default (maybe it shouldn't be
> the one that has a numeric value of 0?) and if there ever is a named mode that
> is not related to analog TV, it looks that it will refer to NTSC-443.
>
> Not sure where could that actually propagate, and maybe what I'm saying can't
> happen, but I'm imagining weird scenarios where a GPU that has both a
> VGA/HDMI/whatever output, and a composite output, switches to NTSC-443 on the
> composite output by default because a named mode for the modern output is
> selected.
So, named modes are per-connector so the fact that there's another
output doesn't really matter. Then, the answer is quite simple actually,
the HDMI driver wouldn't register and use the TV mode property at all,
so it would completely ignore it, no matter what value it has.
So it's not really a concern.
> Maybe something like DRM_MODE_TV_MODE_NONE = 0 would make sense?
But I guess we can add it still.
Maxime
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Description: PGP signature
Re: [Intel-gfx] [PATCH v2 10/41] drm/modes: Add a function to generate analog display modes
Hi, On Wed, Aug 31, 2022 at 03:44:52AM +0200, Mateusz Kwiatkowski wrote: > > +#define NTSC_HFP_DURATION_TYP_NS 1500 > > +#define NTSC_HFP_DURATION_MIN_NS 1270 > > +#define NTSC_HFP_DURATION_MAX_NS 2220 > > You've defined those min/typ/max ranges, but you're not using the "typ" field > for anything other than hslen. Yeah... I've left most of them because it was so hard to find most of them, it's useful at least for documentation purposes. And it's a define so there's pretty much no downside to it as far as the final binary is involved. > The actual "typical" value is thus always the midpoint, which isn't > necessarily the best choice. > > In particular, for the standard 720px wide modes at 13.5 MHz, hsync_start > ends up being 735 for 480i and 734 for 576i, instead of 736 and 732 requested > by BT.601. That's all obviously within tolerances, but the image ends up > noticeably off-center (at least on modern TVs), especially in the 576i case. I'll try to fix that up. > > + htotal = params->line_duration_ns * pixel_clock_hz / NSEC_PER_SEC; > > You're multiplying an unsigned int and an unsigned long - both types are only > required to be 32 bit, so this is likely to overflow. You need to use a cast > to > unsigned long long, and then call do_div() for 64-bit division. > > This actually overflowed on me on my Pi running ARM32 kernel, resulting in > negative horizontal porch lengths, and drm_helper_probe_add_cmdline_mode() > taking over the mode generation (badly), and a horrible mess on screen. Indeed, that's bad. > > + vfp = vfp_min + (porches_rem / 2); > > + vbp = porches - vfp; > > Relative position of the vertical sync within the VBI effectively moves the > image up and down. Adding that (porches_rem / 2) moves the image up off center > by that many pixels. I'd keep the VFP always at minimum to keep the image > centered. And you would increase the back porch only then? Maxime signature.asc Description: PGP signature
Re: [Intel-gfx] [PATCH v2 10/41] drm/modes: Add a function to generate analog display modes
Hi,
On Wed, Aug 31, 2022 at 10:14:28AM +0200, Geert Uytterhoeven wrote:
> > > +enum drm_mode_analog {
> > > +DRM_MODE_ANALOG_NTSC,
> > > +DRM_MODE_ANALOG_PAL,
> > > +};
> >
> > Using "NTSC" and "PAL" to describe the 50Hz and 60Hz analog TV modes is
> > common,
> > but strictly speaking a misnomer. Those are color encoding systems, and your
> > patchset fully supports lesser used, but standard encodings for those (e.g.
> > PAL-M for 60Hz and SECAM for 50Hz). I'd propose switching to some more
> > neutral
> > naming scheme. Some ideas:
> >
> > - DRM_MODE_ANALOG_60_HZ / DRM_MODE_ANALOG_50_HZ (after standard refresh
> > rate)
> > - DRM_MODE_ANALOG_525_LINES / DRM_MODE_ANALOG_625_LINES (after standard line
> > count)
>
> IMHO these are bad names, as e.g. VGA640x480@60 is also analog, using
> 60 Hz and 525 lines. Add "TV" to the name?
>
> > - DRM_MODE_ANALOG_JM / DRM_MODE_ANALOG_BDGHIKLN (after corresponding ITU
> > System
> > Letter Designations)
>
> Or DRM_MODE_ITU_*?
> But given the long list of letters, this looks fragile to me.
Does it matter at all? It's an internal API that isn't exposed at all.
I'd rather have a common name that everyone can understand in this case
rather than a *perfect* name where most will scratch their head
wondering what it's about.
Maxime
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Description: PGP signature
Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/display: stop HPD workers before display driver unregister (rev15)
On Tue, Aug 30, 2022 at 04:26:06PM +, Patchwork wrote: > == Series Details == > > Series: drm/i915/display: stop HPD workers before display driver unregister > (rev15) > URL : https://patchwork.freedesktop.org/series/105557/ > State : success Thanks for the patchset, pushed to drm-intel-next. > > == Summary == > > CI Bug Log - changes from CI_DRM_12034_full -> Patchwork_105557v15_full > > > Summary > --- > > **SUCCESS** > > No regressions found. > > > > Participating hosts (11 -> 11) > -- > > No changes in participating hosts > > Known issues > > > Here are the changes found in Patchwork_105557v15_full that come from known > issues: > > ### IGT changes ### > > Issues hit > > * igt@gem_exec_balancer@parallel-balancer: > - shard-iclb: [PASS][1] -> [SKIP][2] ([i915#4525]) +1 similar > issue >[1]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12034/shard-iclb2/igt@gem_exec_balan...@parallel-balancer.html >[2]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v15/shard-iclb7/igt@gem_exec_balan...@parallel-balancer.html > > * igt@gem_exec_fair@basic-none-rrul@rcs0: > - shard-kbl: NOTRUN -> [FAIL][3] ([i915#2842]) >[3]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v15/shard-kbl1/igt@gem_exec_fair@basic-none-r...@rcs0.html > > * igt@gem_exec_fair@basic-none-share@rcs0: > - shard-iclb: [PASS][4] -> [FAIL][5] ([i915#2842]) +1 similar > issue >[4]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12034/shard-iclb6/igt@gem_exec_fair@basic-none-sh...@rcs0.html >[5]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v15/shard-iclb3/igt@gem_exec_fair@basic-none-sh...@rcs0.html > > * igt@gem_exec_fair@basic-pace@vcs1: > - shard-iclb: NOTRUN -> [FAIL][6] ([i915#2842]) >[6]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v15/shard-iclb2/igt@gem_exec_fair@basic-p...@vcs1.html > > * igt@gem_exec_suspend@basic-s3@smem: > - shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([i915#180]) >[7]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12034/shard-kbl4/igt@gem_exec_suspend@basic...@smem.html >[8]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v15/shard-kbl7/igt@gem_exec_suspend@basic...@smem.html > > * igt@gem_lmem_swapping@massive-random: > - shard-apl: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#4613]) >[9]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v15/shard-apl3/igt@gem_lmem_swapp...@massive-random.html > > * igt@gem_lmem_swapping@parallel-random-verify: > - shard-kbl: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#4613]) > +4 similar issues >[10]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v15/shard-kbl4/igt@gem_lmem_swapp...@parallel-random-verify.html > > * igt@gem_softpin@evict-single-offset: > - shard-apl: NOTRUN -> [FAIL][11] ([i915#4171]) >[11]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v15/shard-apl3/igt@gem_soft...@evict-single-offset.html > > * igt@gem_userptr_blits@dmabuf-sync: > - shard-apl: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#3323]) >[12]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v15/shard-apl3/igt@gem_userptr_bl...@dmabuf-sync.html > > * igt@i915_pm_dc@dc9-dpms: > - shard-iclb: [PASS][13] -> [SKIP][14] ([i915#4281]) >[13]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12034/shard-iclb8/igt@i915_pm...@dc9-dpms.html >[14]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v15/shard-iclb3/igt@i915_pm...@dc9-dpms.html > > * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp: > - shard-apl: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#1937]) >[15]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v15/shard-apl6/igt@i915_pm_lpsp@kms-l...@kms-lpsp-dp.html > > * igt@i915_suspend@sysfs-reader: > - shard-apl: [PASS][16] -> [DMESG-WARN][17] ([i915#180]) +1 > similar issue >[16]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12034/shard-apl2/igt@i915_susp...@sysfs-reader.html >[17]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v15/shard-apl2/igt@i915_susp...@sysfs-reader.html > > * igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_mc_ccs: > - shard-apl: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#3886]) > +2 similar issues >[18]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105557v15/shard-apl6/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html > > * igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_mc_ccs: > - shard-kbl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#3886]) > +11 similar issues >[19]: >
[Intel-gfx] ✗ Fi.CI.IGT: failure for Add DP MST DSC support to i915 (rev12)
== Series Details ==
Series: Add DP MST DSC support to i915 (rev12)
URL : https://patchwork.freedesktop.org/series/101492/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12070_full -> Patchwork_101492v12_full
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_101492v12_full absolutely need
to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_101492v12_full, please notify your bug team to allow
them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (11 -> 11)
--
No changes in participating hosts
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_101492v12_full:
### IGT changes ###
Possible regressions
* igt@gem_wait@write-busy@bcs0:
- shard-tglb: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12070/shard-tglb5/igt@gem_wait@write-b...@bcs0.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v12/shard-tglb7/igt@gem_wait@write-b...@bcs0.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_pm_rps@reset:
- {shard-tglu}: [PASS][3] -> [FAIL][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12070/shard-tglu-4/igt@i915_pm_...@reset.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v12/shard-tglu-4/igt@i915_pm_...@reset.html
Known issues
Here are the changes found in Patchwork_101492v12_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_ctx_isolation@preservation-s3@rcs0:
- shard-apl: [PASS][5] -> [DMESG-WARN][6] ([i915#180])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12070/shard-apl1/igt@gem_ctx_isolation@preservation...@rcs0.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v12/shard-apl3/igt@gem_ctx_isolation@preservation...@rcs0.html
* igt@gem_exec_balancer@parallel-keep-in-fence:
- shard-iclb: [PASS][7] -> [SKIP][8] ([i915#4525]) +1 similar issue
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12070/shard-iclb2/igt@gem_exec_balan...@parallel-keep-in-fence.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v12/shard-iclb8/igt@gem_exec_balan...@parallel-keep-in-fence.html
* igt@gem_lmem_swapping@parallel-random-verify-ccs:
- shard-apl: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#4613])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v12/shard-apl3/igt@gem_lmem_swapp...@parallel-random-verify-ccs.html
* igt@gem_mmap_gtt@cpuset-basic-small-copy:
- shard-glk: [PASS][10] -> [DMESG-WARN][11] ([i915#118] /
[i915#1888])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12070/shard-glk3/igt@gem_mmap_...@cpuset-basic-small-copy.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v12/shard-glk3/igt@gem_mmap_...@cpuset-basic-small-copy.html
* igt@gem_render_copy@x-tiled-to-vebox-yf-tiled:
- shard-apl: NOTRUN -> [SKIP][12] ([fdo#109271]) +38 similar issues
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v12/shard-apl3/igt@gem_render_c...@x-tiled-to-vebox-yf-tiled.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a:
- shard-glk: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#1937])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v12/shard-glk3/igt@i915_pm_lpsp@kms-l...@kms-lpsp-hdmi-a.html
* igt@i915_selftest@live@hangcheck:
- shard-tglb: [PASS][14] -> [DMESG-WARN][15] ([i915#5591])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12070/shard-tglb5/igt@i915_selftest@l...@hangcheck.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v12/shard-tglb2/igt@i915_selftest@l...@hangcheck.html
* igt@kms_chamelium@dp-crc-single:
- shard-apl: NOTRUN -> [SKIP][16] ([fdo#109271] / [fdo#111827]) +3
similar issues
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v12/shard-apl6/igt@kms_chamel...@dp-crc-single.html
* igt@kms_chamelium@dp-frame-dump:
- shard-glk: NOTRUN -> [SKIP][17] ([fdo#109271] / [fdo#111827])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v12/shard-glk3/igt@kms_chamel...@dp-frame-dump.html
* igt@kms_draw_crc@draw-method-xrgb-mmap-wc-4tiled:
- shard-glk: NOTRUN -> [SKIP][18] ([fdo#109271]) +2 similar issues
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v12/shard-glk3/igt@kms_draw_...@draw-method-xrgb-mmap-wc-4tiled.html
* igt@kms_flip@flip-vs-suspend@b-vga1:
- shard-snb: [PASS][19] -> [INCOMPLETE][20]
Re: [Intel-gfx] [PATCH] drm/i915: do not reset PLANE_SURF on plane disable on older gens
On Mon, Sep 05, 2022 at 10:05:00AM +0200, Andrzej Hajda wrote: > In case of ICL and older generations disabling plane and/or disabling > async update is always performed on vblank, It should only be broken on bdw-glk (see. need_async_flip_disable_wa). > but if async update is enabled > PLANE_SURF register is updated asynchronously. Writing 0 to PLANE_SURF > when plane is still enabled can cause DMAR/PIPE errors. > On the other side PLANE_SURF is used to arm plane registers - we need to > write to it to trigger update on VBLANK, writting current value should > be safe - the buffer address is valid till vblank. I think you're effectively saying that somehow the async flip disable w/a is not kicking in sometimes. > > Signed-off-by: Andrzej Hajda > --- > drivers/gpu/drm/i915/display/skl_universal_plane.c | 8 ++-- > 1 file changed, 6 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c > b/drivers/gpu/drm/i915/display/skl_universal_plane.c > index bcfde81e4d0866..bc9ed60a2d349e 100644 > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c > @@ -615,11 +615,13 @@ skl_plane_disable_arm(struct intel_plane *plane, > struct drm_i915_private *dev_priv = to_i915(plane->base.dev); > enum plane_id plane_id = plane->id; > enum pipe pipe = plane->pipe; > + u32 plane_surf; > > skl_write_plane_wm(plane, crtc_state); > > intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), 0); > - intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 0); > + plane_surf = intel_de_read_fw(dev_priv, PLANE_SURF(pipe, plane_id)); > + intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), plane_surf); > } > > static void > @@ -629,6 +631,7 @@ icl_plane_disable_arm(struct intel_plane *plane, > struct drm_i915_private *dev_priv = to_i915(plane->base.dev); > enum plane_id plane_id = plane->id; > enum pipe pipe = plane->pipe; > + u32 plane_surf; > > if (icl_is_hdr_plane(dev_priv, plane_id)) > intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id), 0); > @@ -637,7 +640,8 @@ icl_plane_disable_arm(struct intel_plane *plane, > > intel_psr2_disable_plane_sel_fetch(plane, crtc_state); > intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), 0); > - intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 0); > + plane_surf = intel_de_read_fw(dev_priv, PLANE_SURF(pipe, plane_id)); > + intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), plane_surf); > } > > static bool > -- > 2.25.1 -- Ville Syrjälä Intel
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/psr: Disable PSR2 when SDP is sent on prior line
== Series Details == Series: drm/i915/psr: Disable PSR2 when SDP is sent on prior line URL : https://patchwork.freedesktop.org/series/108137/ State : success == Summary == CI Bug Log - changes from CI_DRM_12071 -> Patchwork_108137v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108137v1/index.html Participating hosts (38 -> 38) -- Additional (2): fi-hsw-4770 fi-icl-u2 Missing(2): bat-dg2-8 fi-bdw-samus Known issues Here are the changes found in Patchwork_108137v1 that come from known issues: ### IGT changes ### Issues hit * igt@gem_huc_copy@huc-copy: - fi-icl-u2: NOTRUN -> [SKIP][1] ([i915#2190]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108137v1/fi-icl-u2/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@random-engines: - fi-icl-u2: NOTRUN -> [SKIP][2] ([i915#4613]) +3 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108137v1/fi-icl-u2/igt@gem_lmem_swapp...@random-engines.html * igt@i915_pm_backlight@basic-brightness: - fi-hsw-4770:NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#3012]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108137v1/fi-hsw-4770/igt@i915_pm_backli...@basic-brightness.html * igt@i915_selftest@live@hangcheck: - fi-hsw-g3258: [PASS][4] -> [INCOMPLETE][5] ([i915#3303] / [i915#4785]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12071/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108137v1/fi-hsw-g3258/igt@i915_selftest@l...@hangcheck.html * igt@i915_selftest@live@requests: - fi-pnv-d510:[PASS][6] -> [DMESG-FAIL][7] ([i915#4528]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12071/fi-pnv-d510/igt@i915_selftest@l...@requests.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108137v1/fi-pnv-d510/igt@i915_selftest@l...@requests.html * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: - fi-hsw-4770:NOTRUN -> [SKIP][8] ([fdo#109271]) +9 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108137v1/fi-hsw-4770/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html * igt@kms_chamelium@dp-crc-fast: - fi-hsw-4770:NOTRUN -> [SKIP][9] ([fdo#109271] / [fdo#111827]) +8 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108137v1/fi-hsw-4770/igt@kms_chamel...@dp-crc-fast.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-icl-u2: NOTRUN -> [SKIP][10] ([fdo#111827]) +8 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108137v1/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor: - fi-icl-u2: NOTRUN -> [SKIP][11] ([i915#4103]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108137v1/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor.html * igt@kms_force_connector_basic@force-connector-state: - fi-icl-u2: NOTRUN -> [WARN][12] ([i915#6008]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108137v1/fi-icl-u2/igt@kms_force_connector_ba...@force-connector-state.html * igt@kms_force_connector_basic@force-load-detect: - fi-icl-u2: NOTRUN -> [SKIP][13] ([fdo#109285]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108137v1/fi-icl-u2/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_psr@sprite_plane_onoff: - fi-hsw-4770:NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#1072]) +3 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108137v1/fi-hsw-4770/igt@kms_psr@sprite_plane_onoff.html * igt@kms_setmode@basic-clone-single-crtc: - fi-icl-u2: NOTRUN -> [SKIP][15] ([i915#3555]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108137v1/fi-icl-u2/igt@kms_setm...@basic-clone-single-crtc.html * igt@prime_vgem@basic-userptr: - fi-icl-u2: NOTRUN -> [SKIP][16] ([fdo#109295] / [i915#3301]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108137v1/fi-icl-u2/igt@prime_v...@basic-userptr.html * igt@runner@aborted: - fi-hsw-g3258: NOTRUN -> [FAIL][17] ([fdo#109271] / [i915#4312] / [i915#6246]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108137v1/fi-hsw-g3258/igt@run...@aborted.html Possible fixes * igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions: - fi-bsw-kefka: [FAIL][18] ([i915#6298]) -> [PASS][19] [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12071/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html [19]:
Re: [Intel-gfx] [PATCH] drm/i915: consider HAS_FLAT_CCS() in needs_ccs_pages
LGTM Reviewed-by: Nirmoy Das
On 9/5/2022 12:53 PM, Matthew Auld wrote:
Just move the HAS_FLAT_CCS() check into needs_ccs_pages. This also then
fixes i915_ttm_memcpy_allowed() which was incorrectly reporting true on
DG1, even though it doesn't have small-BAR or flat-CCS.
References: https://gitlab.freedesktop.org/drm/intel/-/issues/6605
Fixes: efeb3caf4341 ("drm/i915/ttm: disallow CPU fallback mode for ccs pages")
Signed-off-by: Matthew Auld
Cc: Nirmoy Das
---
drivers/gpu/drm/i915/gem/i915_gem_object.c | 3 +++
drivers/gpu/drm/i915/gem/i915_gem_ttm.c| 2 +-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c
b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index 389e9f157ca5..85482a04d158 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -723,6 +723,9 @@ bool i915_gem_object_needs_ccs_pages(struct
drm_i915_gem_object *obj)
bool lmem_placement = false;
int i;
+ if (!HAS_FLAT_CCS(to_i915(obj->base.dev)))
+ return false;
+
for (i = 0; i < obj->mm.n_placements; i++) {
/* Compression is not allowed for the objects with smem
placement */
if (obj->mm.placements[i]->type == INTEL_MEMORY_SYSTEM)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index bc9c432edffe..f64a3deb12fc 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -297,7 +297,7 @@ static struct ttm_tt *i915_ttm_tt_create(struct
ttm_buffer_object *bo,
i915_tt->is_shmem = true;
}
- if (HAS_FLAT_CCS(i915) && i915_gem_object_needs_ccs_pages(obj))
+ if (i915_gem_object_needs_ccs_pages(obj))
ccs_pages = DIV_ROUND_UP(DIV_ROUND_UP(bo->base.size,
NUM_BYTES_PER_CCS_BYTE),
PAGE_SIZE);
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: do not reset PLANE_SURF on plane disable on older gens
== Series Details == Series: drm/i915: do not reset PLANE_SURF on plane disable on older gens URL : https://patchwork.freedesktop.org/series/108133/ State : success == Summary == CI Bug Log - changes from CI_DRM_12070_full -> Patchwork_108133v1_full Summary --- **SUCCESS** No regressions found. Participating hosts (11 -> 12) -- Additional (1): shard-rkl Known issues Here are the changes found in Patchwork_108133v1_full that come from known issues: ### CI changes ### Issues hit * boot: - shard-glk: ([PASS][1], [PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25]) -> ([PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [FAIL][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50]) ([i915#4392]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12070/shard-glk1/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12070/shard-glk1/boot.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12070/shard-glk1/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12070/shard-glk2/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12070/shard-glk2/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12070/shard-glk2/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12070/shard-glk3/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12070/shard-glk3/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12070/shard-glk3/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12070/shard-glk5/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12070/shard-glk5/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12070/shard-glk5/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12070/shard-glk6/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12070/shard-glk6/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12070/shard-glk6/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12070/shard-glk7/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12070/shard-glk7/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12070/shard-glk7/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12070/shard-glk8/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12070/shard-glk8/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12070/shard-glk8/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12070/shard-glk8/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12070/shard-glk9/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12070/shard-glk9/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12070/shard-glk9/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108133v1/shard-glk1/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108133v1/shard-glk1/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108133v1/shard-glk1/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108133v1/shard-glk1/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108133v1/shard-glk2/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108133v1/shard-glk2/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108133v1/shard-glk2/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108133v1/shard-glk3/boot.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108133v1/shard-glk3/boot.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108133v1/shard-glk3/boot.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108133v1/shard-glk5/boot.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108133v1/shard-glk5/boot.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108133v1/shard-glk5/boot.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108133v1/shard-glk6/boot.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108133v1/shard-glk6/boot.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108133v1/shard-glk6/boot.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108133v1/shard-glk7/boot.html [43]:
[Intel-gfx] [PATCH] drm/i915: consider HAS_FLAT_CCS() in needs_ccs_pages
Just move the HAS_FLAT_CCS() check into needs_ccs_pages. This also then
fixes i915_ttm_memcpy_allowed() which was incorrectly reporting true on
DG1, even though it doesn't have small-BAR or flat-CCS.
References: https://gitlab.freedesktop.org/drm/intel/-/issues/6605
Fixes: efeb3caf4341 ("drm/i915/ttm: disallow CPU fallback mode for ccs pages")
Signed-off-by: Matthew Auld
Cc: Nirmoy Das
---
drivers/gpu/drm/i915/gem/i915_gem_object.c | 3 +++
drivers/gpu/drm/i915/gem/i915_gem_ttm.c| 2 +-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c
b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index 389e9f157ca5..85482a04d158 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -723,6 +723,9 @@ bool i915_gem_object_needs_ccs_pages(struct
drm_i915_gem_object *obj)
bool lmem_placement = false;
int i;
+ if (!HAS_FLAT_CCS(to_i915(obj->base.dev)))
+ return false;
+
for (i = 0; i < obj->mm.n_placements; i++) {
/* Compression is not allowed for the objects with smem
placement */
if (obj->mm.placements[i]->type == INTEL_MEMORY_SYSTEM)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index bc9c432edffe..f64a3deb12fc 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -297,7 +297,7 @@ static struct ttm_tt *i915_ttm_tt_create(struct
ttm_buffer_object *bo,
i915_tt->is_shmem = true;
}
- if (HAS_FLAT_CCS(i915) && i915_gem_object_needs_ccs_pages(obj))
+ if (i915_gem_object_needs_ccs_pages(obj))
ccs_pages = DIV_ROUND_UP(DIV_ROUND_UP(bo->base.size,
NUM_BYTES_PER_CCS_BYTE),
PAGE_SIZE);
--
2.37.3
Re: [Intel-gfx] [PATCH 9/9] drm/rockchip: convert to using has_audio from display_info
Am Donnerstag, 1. September 2022, 14:47:11 CEST schrieb Jani Nikula:
> Prefer the parsed results for has_audio in display info over calling
> drm_detect_monitor_audio().
>
> Cc: Sandy Huang
> Cc: Heiko Stübner
> Signed-off-by: Jani Nikula
Reviewed-by: Heiko Stuebner
> ---
> drivers/gpu/drm/rockchip/cdn-dp-core.c | 4 ++--
> drivers/gpu/drm/rockchip/inno_hdmi.c | 3 ++-
> 2 files changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.c
> b/drivers/gpu/drm/rockchip/cdn-dp-core.c
> index f77bdf5f5168..50af9861553b 100644
> --- a/drivers/gpu/drm/rockchip/cdn-dp-core.c
> +++ b/drivers/gpu/drm/rockchip/cdn-dp-core.c
> @@ -272,10 +272,10 @@ static int cdn_dp_connector_get_modes(struct
> drm_connector *connector)
> DRM_DEV_DEBUG_KMS(dp->dev, "got edid: width[%d] x height[%d]\n",
> edid->width_cm, edid->height_cm);
>
> - dp->sink_has_audio = drm_detect_monitor_audio(edid);
> -
> drm_connector_update_edid_property(connector, edid);
> ret = drm_add_edid_modes(connector, edid);
> +
> + dp->sink_has_audio = connector->display_info.has_audio;
> }
> mutex_unlock(>lock);
>
> diff --git a/drivers/gpu/drm/rockchip/inno_hdmi.c
> b/drivers/gpu/drm/rockchip/inno_hdmi.c
> index 87b2243ea23e..fadaa795fb3d 100644
> --- a/drivers/gpu/drm/rockchip/inno_hdmi.c
> +++ b/drivers/gpu/drm/rockchip/inno_hdmi.c
> @@ -564,10 +564,11 @@ static int inno_hdmi_connector_get_modes(struct
> drm_connector *connector)
>
> edid = drm_get_edid(connector, hdmi->ddc);
> if (edid) {
> - hdmi->hdmi_data.sink_has_audio = drm_detect_monitor_audio(edid);
> drm_connector_update_edid_property(connector, edid);
> ret = drm_add_edid_modes(connector, edid);
> kfree(edid);
> +
> + hdmi->hdmi_data.sink_has_audio =
> connector->display_info.has_audio;
> }
>
> return ret;
>
Re: [Intel-gfx] [PATCH 8/9] drm/rockchip: cdn-dp: call drm_connector_update_edid_property() unconditionally
Am Donnerstag, 1. September 2022, 14:47:10 CEST schrieb Jani Nikula: > Calling drm_connector_update_edid_property() should be done > unconditionally instead of depending on the number of modes added. Also > match the call order in inno_hdmi and rk3066_hdmi. > > Cc: Sandy Huang > Cc: Heiko Stübner > Signed-off-by: Jani Nikula Reviewed-by: Heiko Stuebner > --- > drivers/gpu/drm/rockchip/cdn-dp-core.c | 5 ++--- > 1 file changed, 2 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.c > b/drivers/gpu/drm/rockchip/cdn-dp-core.c > index c204e9b95c1f..f77bdf5f5168 100644 > --- a/drivers/gpu/drm/rockchip/cdn-dp-core.c > +++ b/drivers/gpu/drm/rockchip/cdn-dp-core.c > @@ -273,10 +273,9 @@ static int cdn_dp_connector_get_modes(struct > drm_connector *connector) > edid->width_cm, edid->height_cm); > > dp->sink_has_audio = drm_detect_monitor_audio(edid); > + > + drm_connector_update_edid_property(connector, edid); > ret = drm_add_edid_modes(connector, edid); > - if (ret) > - drm_connector_update_edid_property(connector, > - edid); > } > mutex_unlock(>lock); > >
[Intel-gfx] [PATCH 2/2] drm/i915/psr: Disable PSR2 when SDP is sent on prior line
Selective update doesn't work if SU start address is 0 and start/end SDP is configured to be sent prior to SU start/end lines. PSR2 has to be disabled in this case for Alder Lake. HSDES: 22012279113 Cc: Mika Kahola Cc: José Roberto de Souza Signed-off-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_psr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 6f03bf16d6f4..90d7cdd743be 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -811,7 +811,8 @@ static bool _compute_psr2_sdp_prior_scanline_indication(struct intel_dp *intel_d if ((hblank_ns - req_ns) > 100) return true; - if (DISPLAY_VER(dev_priv) < 13 || intel_dp->edp_dpcd[0] < DP_EDP_14b) + /* Not supported <13 / Wa_22012279113:adl-p */ + if (DISPLAY_VER(dev_priv) <= 13 || intel_dp->edp_dpcd[0] < DP_EDP_14b) return false; crtc_state->req_psr2_sdp_prior_scanline = true; -- 2.34.1
[Intel-gfx] [PATCH 1/2] drm/i915/psr: Equation changed for sending start/stop on prior line
Equation for sending start/end SDP prior to the SU region start/end has changed. Update used formula. Bspec: 49274 Cc: Mika Kahola Cc: José Roberto de Souza Signed-off-by: Jouni Högander --- drivers/gpu/drm/i915/display/intel_psr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 079b7d3d0c53..6f03bf16d6f4 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -805,8 +805,8 @@ static bool _compute_psr2_sdp_prior_scanline_indication(struct intel_dp *intel_d hblank_total = adjusted_mode->crtc_hblank_end - adjusted_mode->crtc_hblank_start; hblank_ns = div_u64(100ULL * hblank_total, adjusted_mode->crtc_clock); - /* From spec: (72 / number of lanes) * 1000 / symbol clock frequency MHz */ - req_ns = (72 / crtc_state->lane_count) * 1000 / (crtc_state->port_clock / 1000); + /* From spec: ((60 / number of lanes) + 11) * 1000 / symbol clock frequency MHz */ + req_ns = ((60 / crtc_state->lane_count) + 11) * 1000 / (crtc_state->port_clock / 1000); if ((hblank_ns - req_ns) > 100) return true; -- 2.34.1
[Intel-gfx] [PATCH 0/2] drm/i915/psr: Disable PSR2 when SDP is sent on prior line
Selective update doesn't work if SU start address is 0 and start/end SDP is configured to be sent prior to SU start/end lines. PSR2 has to be disabled in this case for Alder Lake. Additionally this patch set updates changed equation for sending start/end SDP prior to the SU region start/end. Cc: Mika Kahola Cc: José Roberto de Souza Jouni Högander (2): drm/i915/psr: Equation changed for sending start/stop on prior line drm/i915/psr: Disable PSR2 when SDP is sent on prior line drivers/gpu/drm/i915/display/intel_psr.c | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) -- 2.34.1
Re: [Intel-gfx] [PATCH 6/6] drm/i915/rps: Freq caps for MTL
On Fri, 02 Sep 2022, Ashutosh Dixit wrote:
> For MTL, when reading from HW, RP0, RP1 (actuall RPe) and RPn freq use an
> entirely different set of registers with different fields, bitwidths and
> units.
>
> Cc: Badal Nilawar
> Signed-off-by: Ashutosh Dixit
> ---
> drivers/gpu/drm/i915/gt/intel_rps.c | 20
> drivers/gpu/drm/i915/i915_reg.h | 9 +
> 2 files changed, 29 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
> b/drivers/gpu/drm/i915/gt/intel_rps.c
> index 579ae9ac089c..e7ab172698e3 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> @@ -1085,6 +1085,23 @@ static u32 intel_rps_read_state_cap(struct intel_rps
> *rps)
> return intel_uncore_read(uncore, GEN6_RP_STATE_CAP);
> }
>
> +static void
> +mtl_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps *caps)
> +{
> + struct intel_uncore *uncore = rps_to_uncore(rps);
> + u32 rp_state_cap = rps_to_gt(rps)->type == GT_MEDIA ?
> + intel_uncore_read(uncore, MTL_MEDIAP_STATE_CAP)
> :
> + intel_uncore_read(uncore, MTL_RP_STATE_CAP);
> + u32 rpe = rps_to_gt(rps)->type == GT_MEDIA ?
> + intel_uncore_read(uncore, MTL_MPE_FREQUENCY) :
> + intel_uncore_read(uncore, MTL_GT_RPE_FREQUENCY);
> +
> + /* MTL values are in units of 16.67 MHz */
> + caps->rp0_freq = REG_FIELD_GET(MTL_RP0_CAP_MASK, rp_state_cap);
> + caps->min_freq = REG_FIELD_GET(MTL_RPN_CAP_MASK, rp_state_cap);
> + caps->rp1_freq = REG_FIELD_GET(MTL_RPE_MASK, rpe);
> +}
> +
> /**
> * gen6_rps_get_freq_caps - Get freq caps exposed by HW
> * @rps: the intel_rps structure
> @@ -1098,6 +1115,9 @@ void gen6_rps_get_freq_caps(struct intel_rps *rps,
> struct intel_rps_freq_caps *c
> struct drm_i915_private *i915 = rps_to_i915(rps);
> u32 rp_state_cap;
>
> + if (IS_METEORLAKE(i915))
> + return mtl_get_freq_caps(rps, caps);
> +
Please make gen6_rps_get_freq_caps() static, and add
intel_rps_get_freq_caps()
{
if (IS_METEORLAKE(i915))
return mtl_get_freq_caps(rps, caps);
else
return gen6_rps_get_freq_caps(rps, caps);
}
Or something.
BR,
Jani.
> rp_state_cap = intel_rps_read_state_cap(rps);
>
> /* static values from HW: RP0 > RP1 > RPn (min_freq) */
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 06d555321651..d78f9675aa57 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1792,6 +1792,15 @@
> #define XEHPSDV_RP_STATE_CAP _MMIO(0x250014)
> #define PVC_RP_STATE_CAP _MMIO(0x281014)
>
> +#define MTL_RP_STATE_CAP _MMIO(0x138000)
> +#define MTL_MEDIAP_STATE_CAP _MMIO(0x138020)
> +#define MTL_RP0_CAP_MASK REG_GENMASK(8, 0)
> +#define MTL_RPN_CAP_MASK REG_GENMASK(24, 16)
> +
> +#define MTL_GT_RPE_FREQUENCY _MMIO(0x13800c)
> +#define MTL_MPE_FREQUENCY_MMIO(0x13802c)
> +#define MTL_RPE_MASK REG_GENMASK(8, 0)
> +
> #define GT0_PERF_LIMIT_REASONS _MMIO(0x1381a8)
> #define GT0_PERF_LIMIT_REASONS_MASK0xde3
> #define PROCHOT_MASK REG_BIT(1)
--
Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] ✓ Fi.CI.BAT: success for Add DP MST DSC support to i915 (rev12)
== Series Details ==
Series: Add DP MST DSC support to i915 (rev12)
URL : https://patchwork.freedesktop.org/series/101492/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12070 -> Patchwork_101492v12
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v12/index.html
Participating hosts (36 -> 35)
--
Missing(1): fi-bdw-samus
Known issues
Here are the changes found in Patchwork_101492v12 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[PASS][1] -> [INCOMPLETE][2] ([i915#4785])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12070/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v12/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
*
igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size:
- fi-bsw-kefka: [PASS][3] -> [FAIL][4] ([i915#6298])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12070/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions-varying-size.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v12/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions-varying-size.html
* igt@runner@aborted:
- fi-hsw-4770:NOTRUN -> [FAIL][5] ([fdo#109271] / [i915#4312] /
[i915#5594] / [i915#6246])
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v12/fi-hsw-4770/igt@run...@aborted.html
Possible fixes
* igt@gem_exec_suspend@basic-s0@smem:
- {bat-rplp-1}: [DMESG-WARN][6] ([i915#2867]) -> [PASS][7]
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12070/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v12/bat-rplp-1/igt@gem_exec_suspend@basic...@smem.html
* igt@i915_pm_rpm@module-reload:
- fi-cfl-8109u: [DMESG-FAIL][8] ([i915#62]) -> [PASS][9]
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12070/fi-cfl-8109u/igt@i915_pm_...@module-reload.html
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v12/fi-cfl-8109u/igt@i915_pm_...@module-reload.html
* igt@i915_selftest@live@reset:
- {bat-rpls-1}: [DMESG-FAIL][10] ([i915#4983] / [i915#5828]) ->
[PASS][11]
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12070/bat-rpls-1/igt@i915_selftest@l...@reset.html
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v12/bat-rpls-1/igt@i915_selftest@l...@reset.html
* igt@i915_selftest@live@ring_submission:
- fi-cfl-8109u: [DMESG-WARN][12] ([i915#5904]) -> [PASS][13] +30
similar issues
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12070/fi-cfl-8109u/igt@i915_selftest@live@ring_submission.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v12/fi-cfl-8109u/igt@i915_selftest@live@ring_submission.html
* igt@i915_suspend@basic-s2idle-without-i915:
- fi-cfl-8109u: [DMESG-WARN][14] ([i915#5904] / [i915#62]) ->
[PASS][15]
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12070/fi-cfl-8109u/igt@i915_susp...@basic-s2idle-without-i915.html
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v12/fi-cfl-8109u/igt@i915_susp...@basic-s2idle-without-i915.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions:
- fi-bsw-kefka: [FAIL][16] ([i915#6298]) -> [PASS][17]
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12070/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v12/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cur...@atomic-transitions.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cfl-8109u: [DMESG-WARN][18] ([i915#62]) -> [PASS][19] +12
similar issues
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12070/fi-cfl-8109u/igt@kms_frontbuffer_track...@basic.html
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101492v12/fi-cfl-8109u/igt@kms_frontbuffer_track...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5594]: https://gitlab.freedesktop.org/drm/intel/issues/5594
[i915#5828]:
Re: [Intel-gfx] [PATCH] drm/i915: Rename ggtt_view as gtt_view
On 01/09/2022 19:38, Niranjana Vishwanathapura wrote:
So far, different views (normal, partial, rotated and remapped)
into the same object are only supported for GGTT mappings.
But with the upcoming VM_BIND feature, PPGTT will also use the
partial view mapping. Hence rename ggtt_view to more generic
gtt_view.
Signed-off-by: Niranjana Vishwanathapura
Acked-by: Tvrtko Ursulin
Easily even r-b since I did scroll through it and it all looks
straightforward.
Regards,
Tvrtko
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.h | 2 +-
.../drm/i915/display/intel_display_types.h| 2 +-
drivers/gpu/drm/i915/display/intel_fb.c | 18 ++---
drivers/gpu/drm/i915/display/intel_fb_pin.c | 4 +-
drivers/gpu/drm/i915/display/intel_fb_pin.h | 4 +-
drivers/gpu/drm/i915/display/intel_fbdev.c| 4 +-
drivers/gpu/drm/i915/gem/i915_gem_domain.c| 4 +-
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 16 ++---
drivers/gpu/drm/i915/gem/i915_gem_object.h| 2 +-
.../drm/i915/gem/selftests/i915_gem_mman.c| 4 +-
drivers/gpu/drm/i915/gt/intel_reset.c | 2 +-
drivers/gpu/drm/i915/i915_debugfs.c | 56 +++
drivers/gpu/drm/i915/i915_drv.h | 4 +-
drivers/gpu/drm/i915/i915_gem.c | 6 +-
drivers/gpu/drm/i915/i915_vma.c | 40 +--
drivers/gpu/drm/i915/i915_vma.h | 18 ++---
drivers/gpu/drm/i915/i915_vma_types.h | 42 ++--
drivers/gpu/drm/i915/selftests/i915_vma.c | 68 +--
19 files changed, 149 insertions(+), 149 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index be7cff722196..8251f87064f6 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -670,7 +670,7 @@ bool intel_plane_uses_fence(const struct intel_plane_state
*plane_state)
return DISPLAY_VER(dev_priv) < 4 ||
(plane->fbc &&
-plane_state->view.gtt.type == I915_GGTT_VIEW_NORMAL);
+plane_state->view.gtt.type == I915_GTT_VIEW_NORMAL);
}
/*
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index e895277c4cd9..e322011877bb 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -45,7 +45,7 @@ struct drm_modeset_acquire_ctx;
struct drm_plane;
struct drm_plane_state;
struct i915_address_space;
-struct i915_ggtt_view;
+struct i915_gtt_view;
struct intel_atomic_state;
struct intel_crtc;
struct intel_crtc_state;
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 0da9b208d56e..01977cd237eb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -105,7 +105,7 @@ struct intel_fb_view {
* In the normal view the FB object's backing store sg list is used
* directly and hence the remap information here is not used.
*/
- struct i915_ggtt_view gtt;
+ struct i915_gtt_view gtt;
/*
* The GTT view (gtt.type) specific information for each FB color
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
b/drivers/gpu/drm/i915/display/intel_fb.c
index b191915ab351..eefa33c555ac 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -1395,7 +1395,7 @@ static u32 calc_plane_remap_info(const struct
intel_framebuffer *fb, int color_p
plane_view_height_tiles(fb, color_plane, dims,
y));
}
- if (view->gtt.type == I915_GGTT_VIEW_ROTATED) {
+ if (view->gtt.type == I915_GTT_VIEW_ROTATED) {
drm_WARN_ON(>drm, remap_info->linear);
check_array_bounds(i915, view->gtt.rotated.plane, color_plane);
@@ -1420,7 +1420,7 @@ static u32 calc_plane_remap_info(const struct intel_framebuffer *fb, int color_p
/* rotate the tile dimensions to match the GTT view */
swap(tile_width, tile_height);
} else {
- drm_WARN_ON(>drm, view->gtt.type !=
I915_GGTT_VIEW_REMAPPED);
+ drm_WARN_ON(>drm, view->gtt.type !=
I915_GTT_VIEW_REMAPPED);
check_array_bounds(i915, view->gtt.remapped.plane, color_plane);
@@ -1503,12 +1503,12 @@ calc_plane_normal_size(const struct intel_framebuffer *fb, int color_plane,
}
static void intel_fb_view_init(struct drm_i915_private *i915, struct intel_fb_view *view,
- enum i915_ggtt_view_type view_type)
+ enum i915_gtt_view_type view_type)
{
memset(view, 0, sizeof(*view));
view->gtt.type = view_type;
- if (view_type == I915_GGTT_VIEW_REMAPPED && IS_ALDERLAKE_P(i915))
+
Re: [Intel-gfx] [PATCH 5/6] drm/i915/mtl: PERF_LIMIT_REASONS changes for MTL
On Fri, 02 Sep 2022, Ashutosh Dixit wrote:
> PERF_LIMIT_REASONS register for MTL media gt is different now.
>
> Cc: Badal Nilawar
> Signed-off-by: Ashutosh Dixit
> ---
> drivers/gpu/drm/i915/gt/intel_gt.h| 8
> drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 4 ++--
> drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 6 +++---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 4 files changed, 14 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h
> b/drivers/gpu/drm/i915/gt/intel_gt.h
> index c9a359f35d0f..7286d47113ee 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.h
> @@ -9,6 +9,7 @@
> #include "intel_engine_types.h"
> #include "intel_gt_types.h"
> #include "intel_reset.h"
> +#include "i915_reg.h"
>
> struct drm_i915_private;
> struct drm_printer;
> @@ -86,6 +87,13 @@ static inline bool intel_gt_is_wedged(const struct
> intel_gt *gt)
> return unlikely(test_bit(I915_WEDGED, >reset.flags));
> }
>
> +static inline
> +i915_reg_t intel_gt_perf_limit_reasons_reg(struct intel_gt *gt)
> +{
> + return gt->type == GT_MEDIA ?
> + MTL_MEDIA_PERF_LIMIT_REASONS : GT0_PERF_LIMIT_REASONS;
> +}
Nowadays, I pretty much think of everything from the standpoint of
setting the example for future changes. Is this what we want people to
copy? Because that's what we do, look for examples for what we want to
achieve, and emulate.
Do we want this to be duplicated for other registers? Choose register
offset based on platform/engine/fusing/whatever parameter? Is this a
register definition that should be in a _regs.h file?
I don't know.
I've also grown to dislike static inlines a lot, and this one's the
worst because it actually can't be static inline because its passed as a
function pointer.
BR,
Jani.
> +
> int intel_gt_probe_all(struct drm_i915_private *i915);
> int intel_gt_tiles_init(struct drm_i915_private *i915);
> void intel_gt_release_all(struct drm_i915_private *i915);
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> index 5c95cba5e5df..fe0091f953c1 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> @@ -661,7 +661,7 @@ static int perf_limit_reasons_get(void *data, u64 *val)
> intel_wakeref_t wakeref;
>
> with_intel_runtime_pm(gt->uncore->rpm, wakeref)
> - *val = intel_uncore_read(gt->uncore, GT0_PERF_LIMIT_REASONS);
> + *val = intel_uncore_read(gt->uncore,
> intel_gt_perf_limit_reasons_reg(gt));
>
> return 0;
> }
> @@ -673,7 +673,7 @@ static int perf_limit_reasons_clear(void *data, u64 val)
>
> /* Clear the upper 16 log bits, the lower 16 status bits are read-only
> */
> with_intel_runtime_pm(gt->uncore->rpm, wakeref)
> - intel_uncore_rmw(gt->uncore, GT0_PERF_LIMIT_REASONS,
> + intel_uncore_rmw(gt->uncore,
> intel_gt_perf_limit_reasons_reg(gt),
>GT0_PERF_LIMIT_REASONS_LOG_MASK, 0);
>
> return 0;
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
> b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
> index e066cc33d9f2..54deae45d81f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
> @@ -510,7 +510,7 @@ struct intel_gt_bool_throttle_attr {
> struct attribute attr;
> ssize_t (*show)(struct device *dev, struct device_attribute *attr,
> char *buf);
> - i915_reg_t reg32;
> + i915_reg_t (*reg32)(struct intel_gt *gt);
> u32 mask;
> };
>
> @@ -521,7 +521,7 @@ static ssize_t throttle_reason_bool_show(struct device
> *dev,
> struct intel_gt *gt = intel_gt_sysfs_get_drvdata(dev, attr->attr.name);
> struct intel_gt_bool_throttle_attr *t_attr =
> (struct intel_gt_bool_throttle_attr *) attr;
> - bool val = rps_read_mask_mmio(>rps, t_attr->reg32, t_attr->mask);
> + bool val = rps_read_mask_mmio(>rps, t_attr->reg32(gt),
> t_attr->mask);
>
> return sysfs_emit(buff, "%u\n", val);
> }
> @@ -530,7 +530,7 @@ static ssize_t throttle_reason_bool_show(struct device
> *dev,
> struct intel_gt_bool_throttle_attr attr_##sysfs_func__ = { \
> .attr = { .name = __stringify(sysfs_func__), .mode = 0444 }, \
> .show = throttle_reason_bool_show, \
> - .reg32 = GT0_PERF_LIMIT_REASONS, \
> + .reg32 = intel_gt_perf_limit_reasons_reg, \
> .mask = mask__, \
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 10126995e1f6..06d555321651 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1803,6 +1803,7 @@
> #define POWER_LIMIT_1_MASK REG_BIT(11)
> #define POWER_LIMIT_2_MASK REG_BIT(12)
> #define GT0_PERF_LIMIT_REASONS_LOG_MASK REG_GENMASK(31, 16)
>
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add DP MST DSC support to i915 (rev12)
== Series Details == Series: Add DP MST DSC support to i915 (rev12) URL : https://patchwork.freedesktop.org/series/101492/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add DP MST DSC support to i915 (rev12)
== Series Details == Series: Add DP MST DSC support to i915 (rev12) URL : https://patchwork.freedesktop.org/series/101492/ State : warning == Summary == Error: dim checkpatch failed 7db025f39397 drm: Add missing DP DSC extended capability definitions. b66d317f17c5 drm/i915: Fix intel_dp_mst_compute_link_config 16ae4fc4558e drm/i915: Extract drm_dp_atomic_find_vcpi_slots cycle to separate function -:86: CHECK:LINE_SPACING: Please don't use multiple blank lines #86: FILE: drivers/gpu/drm/i915/display/intel_dp_mst.c:116: + + total: 0 errors, 0 warnings, 1 checks, 85 lines checked 0c18599f9339 drm/i915: Add DSC support to MST path
Re: [Intel-gfx] [PATCH 3/6] drm/i915/xelpmp: Expose media as another GT
On Fri, 02 Sep 2022, Ashutosh Dixit wrote:
> From: Matt Roper
>
> Xe_LPM+ platforms have "standalone media." I.e., the media unit is
> designed as an additional GT with its own engine list, GuC, forcewake,
> etc. Let's allow platforms to include media GTs in their device info.
>
> Cc: Aravind Iddamsetty
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/Makefile| 1 +
> drivers/gpu/drm/i915/gt/intel_gt.c | 12 ++--
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 8 +
> drivers/gpu/drm/i915/gt/intel_sa_media.c | 39
> drivers/gpu/drm/i915/gt/intel_sa_media.h | 15 +
> drivers/gpu/drm/i915/i915_pci.c | 15 +
> drivers/gpu/drm/i915/intel_device_info.h | 5 ++-
> drivers/gpu/drm/i915/intel_uncore.c | 16 --
> drivers/gpu/drm/i915/intel_uncore.h | 20 ++--
> 9 files changed, 123 insertions(+), 8 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/gt/intel_sa_media.c
> create mode 100644 drivers/gpu/drm/i915/gt/intel_sa_media.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 522ef9b4aff3..e83e4cd46968 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -123,6 +123,7 @@ gt-y += \
> gt/intel_ring.o \
> gt/intel_ring_submission.o \
> gt/intel_rps.o \
> + gt/intel_sa_media.o \
> gt/intel_sseu.o \
> gt/intel_sseu_debugfs.o \
> gt/intel_timeline.o \
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
> b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 57a6488c0e14..bfe77d01f747 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -776,10 +776,15 @@ void intel_gt_driver_late_release_all(struct
> drm_i915_private *i915)
> }
> }
>
> -static int intel_gt_tile_setup(struct intel_gt *gt, phys_addr_t phys_addr)
> +static int intel_gt_tile_setup(struct intel_gt *gt,
> +phys_addr_t phys_addr,
> +u32 gsi_offset)
> {
> int ret;
>
> + /* GSI offset is only applicable for media GTs */
> + drm_WARN_ON(>i915->drm, gsi_offset);
> +
> if (!gt_is_root(gt)) {
> struct intel_uncore_mmio_debug *mmio_debug;
> struct intel_uncore *uncore;
> @@ -840,7 +845,7 @@ int intel_gt_probe_all(struct drm_i915_private *i915)
> gt->info.engine_mask = RUNTIME_INFO(i915)->platform_engine_mask;
>
> drm_dbg(>drm, "Setting up %s\n", gt->name);
> - ret = intel_gt_tile_setup(gt, phys_addr);
> + ret = intel_gt_tile_setup(gt, phys_addr, 0);
> if (ret)
> return ret;
>
> @@ -873,7 +878,8 @@ int intel_gt_probe_all(struct drm_i915_private *i915)
> goto err;
> }
>
> - ret = gtdef->setup(gt, phys_addr + gtdef->mapping_base);
> + ret = gtdef->setup(gt, phys_addr + gtdef->mapping_base,
> +gtdef->gsi_offset);
> if (ret)
> goto err;
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index d414785003cc..fb2c56777480 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -1578,4 +1578,12 @@
>
> #define GEN12_SFC_DONE(n)_MMIO(0x1cc000 + (n) * 0x1000)
>
> +/*
> + * Standalone Media's non-engine GT registers are located at their regular GT
> + * offsets plus 0x38. This extra offset is stored inside the
> intel_uncore
> + * structure so that the existing code can be used for both GTs without
> + * modification.
> + */
> +#define MTL_MEDIA_GSI_BASE 0x38
> +
> #endif /* __INTEL_GT_REGS__ */
> diff --git a/drivers/gpu/drm/i915/gt/intel_sa_media.c
> b/drivers/gpu/drm/i915/gt/intel_sa_media.c
> new file mode 100644
> index ..8c5c519457cc
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/gt/intel_sa_media.c
> @@ -0,0 +1,39 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2021 Intel Corporation
> + */
> +
> +#include
> +
> +#include "i915_drv.h"
> +#include "gt/intel_gt.h"
> +#include "gt/intel_sa_media.h"
> +
> +int intel_sa_mediagt_setup(struct intel_gt *gt, phys_addr_t phys_addr,
> +u32 gsi_offset)
> +{
> + struct drm_i915_private *i915 = gt->i915;
> + struct intel_uncore *uncore;
> +
> + uncore = drmm_kzalloc(>drm, sizeof(*uncore), GFP_KERNEL);
> + if (!uncore)
> + return -ENOMEM;
> +
> + uncore->gsi_offset = gsi_offset;
> +
> + intel_gt_common_init_early(gt);
> + intel_uncore_init_early(uncore, gt);
> +
> + /*
> + * Standalone media shares the general MMIO space with the primary
> + * GT. We'll re-use the primary GT's mapping.
> + */
> + uncore->regs = i915->uncore.regs;
> + if (drm_WARN_ON(>drm, uncore->regs == NULL))
> + return -EIO;
> +
>
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: do not reset PLANE_SURF on plane disable on older gens
== Series Details ==
Series: drm/i915: do not reset PLANE_SURF on plane disable on older gens
URL : https://patchwork.freedesktop.org/series/108133/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12070 -> Patchwork_108133v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108133v1/index.html
Participating hosts (36 -> 34)
--
Missing(2): bat-rpls-2 fi-bdw-samus
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_108133v1:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@core_hotunplug@unbind-rebind:
- {fi-jsl-1}: [PASS][1] -> [INCOMPLETE][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12070/fi-jsl-1/igt@core_hotunp...@unbind-rebind.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108133v1/fi-jsl-1/igt@core_hotunp...@unbind-rebind.html
Known issues
Here are the changes found in Patchwork_108133v1 that come from known issues:
### IGT changes ###
Possible fixes
* igt@i915_pm_rpm@module-reload:
- fi-cfl-8109u: [DMESG-FAIL][3] ([i915#62]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12070/fi-cfl-8109u/igt@i915_pm_...@module-reload.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108133v1/fi-cfl-8109u/igt@i915_pm_...@module-reload.html
* igt@i915_selftest@live@reset:
- {bat-rpls-1}: [DMESG-FAIL][5] ([i915#4983] / [i915#5828]) ->
[PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12070/bat-rpls-1/igt@i915_selftest@l...@reset.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108133v1/bat-rpls-1/igt@i915_selftest@l...@reset.html
* igt@i915_selftest@live@ring_submission:
- fi-cfl-8109u: [DMESG-WARN][7] ([i915#5904]) -> [PASS][8] +30
similar issues
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12070/fi-cfl-8109u/igt@i915_selftest@live@ring_submission.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108133v1/fi-cfl-8109u/igt@i915_selftest@live@ring_submission.html
* igt@i915_suspend@basic-s2idle-without-i915:
- fi-cfl-8109u: [DMESG-WARN][9] ([i915#5904] / [i915#62]) ->
[PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12070/fi-cfl-8109u/igt@i915_susp...@basic-s2idle-without-i915.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108133v1/fi-cfl-8109u/igt@i915_susp...@basic-s2idle-without-i915.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cfl-8109u: [DMESG-WARN][11] ([i915#62]) -> [PASS][12] +12
similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12070/fi-cfl-8109u/igt@kms_frontbuffer_track...@basic.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108133v1/fi-cfl-8109u/igt@kms_frontbuffer_track...@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5828]: https://gitlab.freedesktop.org/drm/intel/issues/5828
[i915#5904]: https://gitlab.freedesktop.org/drm/intel/issues/5904
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
Build changes
-
* Linux: CI_DRM_12070 -> Patchwork_108133v1
CI-20190529: 20190529
CI_DRM_12070: 6f924a2ec43ac35516136a77b1adad0b6d8f8faa @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6643: 9b2970a6d495ddd9ceb2487fc289105bf05812df @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_108133v1: 6f924a2ec43ac35516136a77b1adad0b6d8f8faa @
git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
4a298447c67b drm/i915: do not reset PLANE_SURF on plane disable on older gens
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108133v1/index.html
[Intel-gfx] [PATCH 4/4] drm/i915: Add DSC support to MST path
Whenever we are not able to get enough timeslots
for required PBN, let's try to allocate those
using DSC, just same way as we do for SST.
v2: Removed intel_dp_mst_dsc_compute_config and refactored
intel_dp_dsc_compute_config to support timeslots as a
parameter(Ville Syrjälä)
v3: - Rebased
- Added a debug to see that we at least try reserving
VCPI slots using DSC, because currently its not visible
from the logs, thus making debugging more tricky.
- Moved timeslots to numerator, where it should be.
v4: - Call drm_dp_mst_atomic_check already during link
config computation, because we need to know already
by this moment if uncompressed amount of VCPI slots
needed can fit, otherwise we need to use DSC.
(thanks to Vinod Govindapillai for pointing this out)
v5: - Put pipe_config->bigjoiner_pipes back to original
condition in intel_dp_dsc_compute_config
(don't remember when I lost it)
v6: - Removed unnecessary drm_dp_mst_atomic_check as it is
now always called in a newly introduced
intel_dp_mst_find_vcpi_slots_for_bpp function
(Vinod Govindapillai)
Reviewed-by: Vinod Govindapillai
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp.c | 73 +--
drivers/gpu/drm/i915/display/intel_dp.h | 17 +++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 127
3 files changed, 175 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index dd7351c0bed1..b90dbe119cde 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -116,7 +116,6 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
}
static void intel_dp_unset_edid(struct intel_dp *intel_dp);
-static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
/* Is link rate UHBR and thus 128b/132b? */
bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
@@ -661,11 +660,12 @@ small_joiner_ram_size_bits(struct drm_i915_private *i915)
return 6144 * 8;
}
-static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
- u32 link_clock, u32 lane_count,
- u32 mode_clock, u32 mode_hdisplay,
- bool bigjoiner,
- u32 pipe_bpp)
+u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
+ u32 link_clock, u32 lane_count,
+ u32 mode_clock, u32 mode_hdisplay,
+ bool bigjoiner,
+ u32 pipe_bpp,
+ u32 timeslots)
{
u32 bits_per_pixel, max_bpp_small_joiner_ram;
int i;
@@ -676,8 +676,9 @@ static u16 intel_dp_dsc_get_output_bpp(struct
drm_i915_private *i915,
* for SST -> TimeSlotsPerMTP is 1,
* for MST -> TimeSlotsPerMTP has to be calculated
*/
- bits_per_pixel = (link_clock * lane_count * 8) /
+ bits_per_pixel = (link_clock * lane_count * 8) * timeslots /
intel_dp_mode_to_fec_clock(mode_clock);
+ drm_dbg_kms(>drm, "Max link bpp: %u\n", bits_per_pixel);
/* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
@@ -726,9 +727,9 @@ static u16 intel_dp_dsc_get_output_bpp(struct
drm_i915_private *i915,
return bits_per_pixel << 4;
}
-static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
- int mode_clock, int mode_hdisplay,
- bool bigjoiner)
+u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
+ int mode_clock, int mode_hdisplay,
+ bool bigjoiner)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
u8 min_slice_count, i;
@@ -935,8 +936,8 @@ intel_dp_mode_valid_downstream(struct intel_connector
*connector,
return MODE_OK;
}
-static bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
- int hdisplay, int clock)
+bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
+int hdisplay, int clock)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
@@ -1023,7 +1024,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
target_clock,
mode->hdisplay,
bigjoiner,
- pipe_bpp) >> 4;
+ pipe_bpp, 1) >> 4;
dsc_slice_count =
[Intel-gfx] [PATCH 1/4] drm: Add missing DP DSC extended capability definitions.
Adding DP DSC register definitions, we might need for further DSC implementation, supporting MST and DP branch pass-through mode. v2: - Fixed checkpatch comment warning v3: - Removed function which is not yet used(Jani Nikula) Reviewed-by: Vinod Govindapillai Signed-off-by: Stanislav Lisovskiy --- include/drm/display/drm_dp.h | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h index 6c0871164771..02c4b6f20478 100644 --- a/include/drm/display/drm_dp.h +++ b/include/drm/display/drm_dp.h @@ -239,6 +239,9 @@ #define DP_DSC_SUPPORT 0x060 /* DP 1.4 */ # define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0) +# define DP_DSC_PASS_THROUGH_IS_SUPPORTED (1 << 1) +# define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_COMP_TO_COMP(1 << 2) +# define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_UNCOMP_TO_COMP (1 << 3) #define DP_DSC_REV 0x061 # define DP_DSC_MAJOR_MASK (0xf << 0) @@ -277,12 +280,15 @@ #define DP_DSC_BLK_PREDICTION_SUPPORT 0x066 # define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0) +# define DP_DSC_RGB_COLOR_CONV_BYPASS_SUPPORT (1 << 1) #define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */ #define DP_DSC_MAX_BITS_PER_PIXEL_HI0x068 /* eDP 1.4 */ # define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0) # define DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT 8 +# define DP_DSC_MAX_BPP_DELTA_VERSION_MASK 0x06 +# define DP_DSC_MAX_BPP_DELTA_AVAILABILITY 0x08 #define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069 # define DP_DSC_RGB (1 << 0) @@ -344,11 +350,13 @@ # define DP_DSC_24_PER_DP_DSC_SINK (1 << 2) #define DP_DSC_BITS_PER_PIXEL_INC 0x06F +# define DP_DSC_RGB_YCbCr444_MAX_BPP_DELTA_MASK 0x1f +# define DP_DSC_RGB_YCbCr420_MAX_BPP_DELTA_MASK 0xe0 # define DP_DSC_BITS_PER_PIXEL_1_16 0x0 # define DP_DSC_BITS_PER_PIXEL_1_8 0x1 # define DP_DSC_BITS_PER_PIXEL_1_4 0x2 # define DP_DSC_BITS_PER_PIXEL_1_2 0x3 -# define DP_DSC_BITS_PER_PIXEL_10x4 +# define DP_DSC_BITS_PER_PIXEL_1_1 0x4 #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ # define DP_PSR_IS_SUPPORTED1 -- 2.37.3
[Intel-gfx] [PATCH 3/4] drm/i915: Extract drm_dp_atomic_find_vcpi_slots cycle to separate function
We would be using almost same code to loop through bpps while calling
drm_dp_atomic_find_vcpi_slots - lets remove this duplication by
introducing a new function intel_dp_mst_find_vcpi_slots_for_bpp
v2: Fix pbn_div calculation - shouldn't matter if its DSC or not.
Reviewed-by: Vinod Govindapillai
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 52 +++--
1 file changed, 39 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 24d6a287a6e3..79ac23495165 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -44,10 +44,14 @@
#include "intel_hotplug.h"
#include "skl_scaler.h"
-static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
- struct intel_crtc_state *crtc_state,
- struct drm_connector_state
*conn_state,
- struct link_config_limits *limits)
+static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
+ struct intel_crtc_state
*crtc_state,
+ int max_bpp,
+ int min_bpp,
+ struct link_config_limits
*limits,
+ struct drm_connector_state
*conn_state,
+ int step,
+ bool dsc)
{
struct drm_atomic_state *state = crtc_state->uapi.state;
struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
@@ -58,7 +62,6 @@ static int intel_dp_mst_compute_link_config(struct
intel_encoder *encoder,
struct drm_i915_private *i915 = to_i915(connector->base.dev);
const struct drm_display_mode *adjusted_mode =
_state->hw.adjusted_mode;
- bool constant_n = drm_dp_has_quirk(_dp->desc,
DP_DPCD_QUIRK_CONSTANT_N);
int bpp, slots = -EINVAL;
int ret = 0;
@@ -72,18 +75,20 @@ static int intel_dp_mst_compute_link_config(struct
intel_encoder *encoder,
// TODO: Handle pbn_div changes by adding a new MST helper
if (!mst_state->pbn_div) {
mst_state->pbn_div =
drm_dp_get_vc_payload_bw(_dp->mst_mgr,
- limits->max_rate,
-
limits->max_lane_count);
+
crtc_state->port_clock,
+
crtc_state->lane_count);
}
- for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
+ for (bpp = max_bpp; bpp >= min_bpp; bpp -= step) {
crtc_state->pipe_bpp = bpp;
crtc_state->pbn =
drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock,
- crtc_state->pipe_bpp,
- false);
+ dsc ? bpp << 4 :
crtc_state->pipe_bpp,
+ dsc);
+
slots = drm_dp_atomic_find_time_slots(state, _dp->mst_mgr,
- connector->port,
crtc_state->pbn);
+ connector->port,
+ crtc_state->pbn);
if (slots == -EDEADLK)
return slots;
if (slots >= 0) {
@@ -101,11 +106,32 @@ static int intel_dp_mst_compute_link_config(struct
intel_encoder *encoder,
if (ret && slots >= 0)
slots = ret;
- if (slots < 0) {
+ if (slots < 0)
drm_dbg_kms(>drm, "failed finding vcpi slots:%d\n",
slots);
+
+ return slots;
+}
+
+
+static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state,
+ struct drm_connector_state
*conn_state,
+ struct link_config_limits *limits)
+{
+ const struct drm_display_mode *adjusted_mode =
+ _state->hw.adjusted_mode;
+ struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
+ struct intel_dp *intel_dp = _mst->primary->dp;
+ bool constant_n = drm_dp_has_quirk(_dp->desc,
DP_DPCD_QUIRK_CONSTANT_N);
+ int slots = -EINVAL;
+
+ slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state,
limits->max_bpp,
+limits->min_bpp,
[Intel-gfx] [PATCH 2/4] drm/i915: Fix intel_dp_mst_compute_link_config
We currently always exit that bpp loop because
drm_dp_atomic_find_vcpi_slots doesn't care if we actually
can fit those or not.
I think that wasn't the initial intention here, especially when
we keep trying with lower bpps, we are supposed to keep trying
until we actually find some _working_ configuration, which isn't the
case here.
So added that drm_dp_mst_check here, so that we can make sure
that try all the bpps before we fail.
Reviewed-by: Vinod Govindapillai
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 7713c19042f3..24d6a287a6e3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -60,6 +60,7 @@ static int intel_dp_mst_compute_link_config(struct
intel_encoder *encoder,
_state->hw.adjusted_mode;
bool constant_n = drm_dp_has_quirk(_dp->desc,
DP_DPCD_QUIRK_CONSTANT_N);
int bpp, slots = -EINVAL;
+ int ret = 0;
mst_state = drm_atomic_get_mst_topology_state(state,
_dp->mst_mgr);
if (IS_ERR(mst_state))
@@ -85,10 +86,21 @@ static int intel_dp_mst_compute_link_config(struct
intel_encoder *encoder,
connector->port,
crtc_state->pbn);
if (slots == -EDEADLK)
return slots;
- if (slots >= 0)
- break;
+ if (slots >= 0) {
+ ret = drm_dp_mst_atomic_check(state);
+ /*
+* If we got slots >= 0 and we can fit those based on
check
+* then we can exit the loop. Otherwise keep trying.
+*/
+ if (!ret)
+ break;
+ }
}
+ /* Despite slots are non-zero, we still failed the atomic check */
+ if (ret && slots >= 0)
+ slots = ret;
+
if (slots < 0) {
drm_dbg_kms(>drm, "failed finding vcpi slots:%d\n",
slots);
--
2.37.3
[Intel-gfx] [PATCH 0/4] Add DP MST DSC support to i915
Currently we have only DSC support for DP SST. Stanislav Lisovskiy (4): drm: Add missing DP DSC extended capability definitions. drm/i915: Fix intel_dp_mst_compute_link_config drm/i915: Extract drm_dp_atomic_find_vcpi_slots cycle to separate function drm/i915: Add DSC support to MST path drivers/gpu/drm/i915/display/intel_dp.c | 73 drivers/gpu/drm/i915/display/intel_dp.h | 17 ++ drivers/gpu/drm/i915/display/intel_dp_mst.c | 195 ++-- include/drm/display/drm_dp.h| 10 +- 4 files changed, 237 insertions(+), 58 deletions(-) -- 2.37.3
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: do not reset PLANE_SURF on plane disable on older gens
== Series Details == Series: drm/i915: do not reset PLANE_SURF on plane disable on older gens URL : https://patchwork.freedesktop.org/series/108133/ State : warning == Summary == Error: dim checkpatch failed 574a7dd04303 drm/i915: do not reset PLANE_SURF on plane disable on older gens -:12: WARNING:TYPO_SPELLING: 'writting' may be misspelled - perhaps 'writing'? #12: write to it to trigger update on VBLANK, writting current value should total: 0 errors, 1 warnings, 0 checks, 30 lines checked
Re: [Intel-gfx] [PATCH] Revert "drm/i915/dg2: Add preemption changes for Wa_14015141709"
Quoting Matt Roper (2022-08-27 00:02:33)
> This reverts commit ca6920811aa5428270dd78af0a7a36b10119065a.
>
> The intent of Wa_14015141709 was to inform us that userspace can no
> longer control object-level preemption as it has on past platforms
> (i.e., by twiddling register bit CS_CHICKEN1[0]). The description of
> the workaround in the spec wasn't terribly well-written, and when we
> requested clarification from the hardware teams we were told that on the
> kernel side we should also probably stop setting
> FF_SLICE_CS_CHICKEN1[14], which is the register bit that directs the
> hardware to honor the settings in per-context register CS_CHICKEN1. It
> turns out that this guidance about FF_SLICE_CS_CHICKEN1[14] was a
> mistake; even though CS_CHICKEN1[0] is non-operational and useless to
> userspace, there are other bits in the register that do still work and
> might need to be adjusted by userspace in the future (e.g., to implement
> other workarounds that show up). If we don't set
> FF_SLICE_CS_CHICKEN1[14] in i915, then those future workarounds would
> not take effect.
Here we should be referencing Mesa/Compute runtime/etc. patches that
intend to use these other bits.
This is to ensure that they're actually aware of the hardware changes
ongoing and we end up with fully functional stack and not kernel doing
something other than the userspace attempts to do.
> This miscommunication came to light because another workaround
> (Wa_16013994831) has now shown up that requires userspace to adjust the
> value of CS_CHICKEN[10] in certain circumstances. To ensure userspace's
> updates to this chicken bit are handled properly by the hardware, we
> need to make sure that FF_SLICE_CS_CHICKEN1[14] is once again set by the
> kernel.
>
> Signed-off-by: Matt Roper
Not too many Cc:s for a patch that impacts uAPI. Even the original patch
being reverted definitely should have Cc:d mesa and some mesa devs.
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 3 ---
> 2 files changed, 1 insertion(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 3cdb8294e13f..69a0c6a74474 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -2389,7 +2389,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
> struct i915_wa_list *wal)
> FF_DOP_CLOCK_GATE_DISABLE);
> }
>
> - if (HAS_PERCTX_PREEMPT_CTRL(i915)) {
> + if (IS_GRAPHICS_VER(i915, 9, 12)) {
> /*
> FtrPerCtxtPreemptionGranularityControl:skl,bxt,kbl,cfl,cnl,icl,tgl */
According to the commit description, this is not the W/A being supported
anymore by the whitelisting. Even if it's the same register we're talking about
different bits and different reasons.
We should clearly indicate that.
Can we have a followup patch where the reasoning is explained more
clearly and the userspace side changes are being referenced and at least
some userspace folks Cc'd?
Regards, Joonas
> wa_masked_en(wal,
> GEN7_FF_SLICE_CS_CHICKEN1,
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 2b00ef3626db..d6a1ab6f65de 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1352,9 +1352,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define HAS_GUC_DEPRIVILEGE(dev_priv) \
> (INTEL_INFO(dev_priv)->has_guc_deprivilege)
>
> -#define HAS_PERCTX_PREEMPT_CTRL(i915) \
> - ((GRAPHICS_VER(i915) >= 9) && GRAPHICS_VER_FULL(i915) < IP_VER(12,
> 55))
> -
> #define HAS_D12_PLANE_MINIMIZATION(dev_priv) (IS_ROCKETLAKE(dev_priv) || \
> IS_ALDERLAKE_S(dev_priv))
>
> --
> 2.37.2
>
[Intel-gfx] [GIT PULL] Immutable backlight-detect-refactor branch between acpi, drm-* and pdx86
Hi All, Now that all patches have been reviewed/acked here is an immutable backlight-detect-refactor branch with 6.0-rc1 + the v5 patch-set, for merging into the relevant (acpi, drm-* and pdx86) subsystems. Please pull this branch into the relevant subsystems. I will merge this into the review-hans branch of the pdx86 git tree today and from there it will move to for-next once the builders have successfully build-tested the merge. Regards, Hans The following changes since commit 568035b01cfb107af8d2e4bd2fb9aea22cf5b868: Linux 6.0-rc1 (2022-08-14 15:50:18 -0700) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86.git tags/backlight-detect-refactor-1 for you to fetch changes up to 4f96b1bc156e7076f6efedc2a76a8c7e897c7977: drm/todo: Add entry about dealing with brightness control on devices with > 1 panel (2022-09-03 12:17:27 +0200) Immutable backlight-detect-refactor branch between acpi, drm-* and pdx86 Tag (immutable branch) with v6.0-rc1 + the (acpi/x86) backlight detect refactor work. For merging into the acpi, drm-* and pdx86 subsystems. Hans de Goede (31): ACPI: video: Add acpi_video_backlight_use_native() helper drm/i915: Don't register backlight when another backlight should be used (v2) drm/amdgpu: Don't register backlight when another backlight should be used (v3) drm/radeon: Don't register backlight when another backlight should be used (v3) drm/nouveau: Don't register backlight when another backlight should be used (v2) ACPI: video: Drop backlight_device_get_by_type() call from acpi_video_get_backlight_type() ACPI: video: Remove acpi_video_bus from list before tearing it down ACPI: video: Simplify acpi_video_unregister_backlight() ACPI: video: Make backlight class device registration a separate step (v2) ACPI: video: Remove code to unregister acpi_video backlight when a native backlight registers drm/i915: Call acpi_video_register_backlight() (v3) drm/nouveau: Register ACPI video backlight when nv_backlight registration fails (v2) drm/amdgpu: Register ACPI video backlight when skipping amdgpu backlight registration drm/radeon: Register ACPI video backlight when skipping radeon backlight registration platform/x86: nvidia-wmi-ec-backlight: Move fw interface definitions to a header (v2) ACPI: video: Refactor acpi_video_get_backlight_type() a bit ACPI: video: Add Nvidia WMI EC brightness control detection (v3) ACPI: video: Add Apple GMUX brightness control detection platform/x86: nvidia-wmi-ec-backlight: Use acpi_video_get_backlight_type() platform/x86: apple-gmux: Stop calling acpi/video.h functions platform/x86: toshiba_acpi: Stop using acpi_video_set_dmi_backlight_type() platform/x86: acer-wmi: Move backlight DMI quirks to acpi/video_detect.c platform/x86: asus-wmi: Drop DMI chassis-type check from backlight handling platform/x86: asus-wmi: Move acpi_backlight=vendor quirks to ACPI video_detect.c platform/x86: asus-wmi: Move acpi_backlight=native quirks to ACPI video_detect.c platform/x86: samsung-laptop: Move acpi_backlight=[vendor|native] quirks to ACPI video_detect.c ACPI: video: Remove acpi_video_set_dmi_backlight_type() ACPI: video: Drop "Samsung X360" acpi_backlight=native quirk ACPI: video: Drop NL5x?U, PF4NU1F and PF5?U?? acpi_backlight=native quirks ACPI: video: Fix indentation of video_detect_dmi_table[] entries drm/todo: Add entry about dealing with brightness control on devices with > 1 panel Documentation/gpu/todo.rst | 68 MAINTAINERS| 1 + drivers/acpi/Kconfig | 1 + drivers/acpi/acpi_video.c | 64 ++- drivers/acpi/video_detect.c| 428 - drivers/gpu/drm/Kconfig| 14 + drivers/gpu/drm/amd/amdgpu/atombios_encoders.c | 14 +- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 + drivers/gpu/drm/gma500/Kconfig | 2 + drivers/gpu/drm/i915/Kconfig | 2 + drivers/gpu/drm/i915/display/intel_acpi.c | 27 ++ drivers/gpu/drm/i915/display/intel_acpi.h | 3 + drivers/gpu/drm/i915/display/intel_backlight.c | 7 + drivers/gpu/drm/i915/display/intel_display.c | 2 +- drivers/gpu/drm/nouveau/nouveau_acpi.c | 10 + drivers/gpu/drm/nouveau/nouveau_acpi.h | 4 + drivers/gpu/drm/nouveau/nouveau_backlight.c| 13 + drivers/gpu/drm/radeon/atombios_encoders.c | 7 + drivers/gpu/drm/radeon/radeon_encoders.c | 11 +-
[Intel-gfx] [PATCH] drm/i915: do not reset PLANE_SURF on plane disable on older gens
In case of ICL and older generations disabling plane and/or disabling async update is always performed on vblank, but if async update is enabled PLANE_SURF register is updated asynchronously. Writing 0 to PLANE_SURF when plane is still enabled can cause DMAR/PIPE errors. On the other side PLANE_SURF is used to arm plane registers - we need to write to it to trigger update on VBLANK, writting current value should be safe - the buffer address is valid till vblank. Signed-off-by: Andrzej Hajda --- drivers/gpu/drm/i915/display/skl_universal_plane.c | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index bcfde81e4d0866..bc9ed60a2d349e 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -615,11 +615,13 @@ skl_plane_disable_arm(struct intel_plane *plane, struct drm_i915_private *dev_priv = to_i915(plane->base.dev); enum plane_id plane_id = plane->id; enum pipe pipe = plane->pipe; + u32 plane_surf; skl_write_plane_wm(plane, crtc_state); intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), 0); - intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 0); + plane_surf = intel_de_read_fw(dev_priv, PLANE_SURF(pipe, plane_id)); + intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), plane_surf); } static void @@ -629,6 +631,7 @@ icl_plane_disable_arm(struct intel_plane *plane, struct drm_i915_private *dev_priv = to_i915(plane->base.dev); enum plane_id plane_id = plane->id; enum pipe pipe = plane->pipe; + u32 plane_surf; if (icl_is_hdr_plane(dev_priv, plane_id)) intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id), 0); @@ -637,7 +640,8 @@ icl_plane_disable_arm(struct intel_plane *plane, intel_psr2_disable_plane_sel_fetch(plane, crtc_state); intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), 0); - intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 0); + plane_surf = intel_de_read_fw(dev_priv, PLANE_SURF(pipe, plane_id)); + intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), plane_surf); } static bool -- 2.25.1
Re: [Intel-gfx] [PATCH] drm/i915/gvt: fix double-free bug in split_2MB_gtt_entry.
On Mon, Sep 05, 2022 at 03:46:09PM +0800, Zheng Hacker wrote:
> I rewrote the letter. Hope it works.
>
> There is a double-free security bug in split_2MB_gtt_entry.
>
> Here is a calling chain :
> ppgtt_populate_spt->ppgtt_populate_shadow_entry->split_2MB_gtt_entry.
> If intel_gvt_dma_map_guest_page failed, it will call
> ppgtt_invalidate_spt, which will finally call ppgtt_free_spt and
> kfree(spt). But the caller does not notice that, and it will call
> ppgtt_free_spt again in error path.
>
> Fix this by returning the result of ppgtt_invalidate_spt to
> split_2MB_gtt_entry.
>
> Signed-off-by: Zheng Wang
>
> ---
> drivers/gpu/drm/i915/gvt/gtt.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
> index ce0eb03709c3..9f14fded8c0c 100644
> --- a/drivers/gpu/drm/i915/gvt/gtt.c
> +++ b/drivers/gpu/drm/i915/gvt/gtt.c
> @@ -1215,7 +1215,7 @@ static int split_2MB_gtt_entry(struct intel_vgpu *vgpu,
> ret = intel_gvt_dma_map_guest_page(vgpu, start_gfn +
> sub_index,
>PAGE_SIZE, _addr);
> if (ret) {
> - ppgtt_invalidate_spt(spt);
> + ret = ppgtt_invalidate_spt(spt);
> return ret;
But now you just lost the original error, shouldn't this succeed even if
intel_gvt_dma_map_guest_page() failed?
And how are you causing intel_gvt_dma_map_guest_page() to fail in a real
system?
thanks,
greg k-h
