Re: [Intel-gfx] [PATCH] drm/i915/fbc: Avoid full proxy f_ops for FBC debug attributes

[Deepak R Varma]

On Wed, Dec 28, 2022 at 06:18:12AM -0500, Rodrigo Vivi wrote:
> On Tue, Dec 27, 2022 at 11:36:13PM +0530, Deepak R Varma wrote:
> > On Tue, Dec 27, 2022 at 12:13:56PM -0500, Rodrigo Vivi wrote:
> > > On Tue, Dec 27, 2022 at 01:30:53PM +0530, Deepak R Varma wrote:
> > > > Using DEFINE_SIMPLE_ATTRIBUTE macro with the debugfs_create_file()
> > > > function adds the overhead of introducing a proxy file operation
> > > > functions to wrap the original read/write inside file removal protection
> > > > functions. This adds significant overhead in terms of introducing and
> > > > managing the proxy factory file operations structure and function
> > > > wrapping at runtime.
> > > > As a replacement, a combination of DEFINE_DEBUGFS_ATTRIBUTE macro paired
> > > > with debugfs_create_file_unsafe() is suggested to be used instead.  The
> > > > DEFINE_DEBUGFS_ATTRIBUTE utilises debugfs_file_get() and
> > > > debugfs_file_put() wrappers to protect the original read and write
> > > > function calls for the debug attributes. There is no need for any
> > > > runtime proxy file operations to be managed by the debugfs core.
> > > >
> > > > This Change is reported by the debugfs_simple_attr.cocci Coccinelle
> > > > semantic patch.
> > >
> > > I just checked here with
> > > $ make coccicheck M=drivers/gpu/drm/i915/ MODE=context 
> > > COCCI=./scripts/coccinelle/api/debugfs/debugfs_simple_attr.cocci
> >
> > Hello Rodrigo,
> > Thank you so much for your review and feedback on the patch proposal.
> >
> > >
> > > The part reported by the this script is the s/SIMPLE/DEBUGFS
> > > but the change to the unsafe option is not.
> >
> > If you look at the original commit of this coccinelle file, it calls out the
> > need for pairing debugfs_create_file_unsafe() as well. Please review this
> >
> > commitID: 5103068eaca2: ("debugfs, coccinelle: check for obsolete 
> > DEFINE_SIMPLE_ATTRIBUTE() usage")
>
> +Nicolai and Julia.
>
> It looks like coccinelle got right the
> - DEFINE_SIMPLE_ATTRIBUTE(dsa_fops, dsa_get, dsa_set, dsa_fmt);
> + DEFINE_DEBUGFS_ATTRIBUTE(dsa_fops, dsa_get, dsa_set, dsa_fmt);
>
> but it failed badly on
> - debugfs_create_file(name, mode, parent, data, &dsa_fops)
> + debugfs_create_file_unsafe(name, mode, parent, data, &dsa_fops)
>
> >
> > Based on my review of the code, the functions debugfs_create_file() and
> > debugfs_create_file_unsafe(), both internally call __debugfs_create_file().
> > However, they pass debugfs_full_proxy_file_operations and
> > debugfs_open_proxy_file_operations respectively to it. The former 
> > represents the
> > full proxy factory, where as the later one is lightweight open proxy
> > implementation of the file operations structure.
> >
> > >
> > > This commit message is not explaining why the unsafe is the suggested
> > > or who suggested it.
> >
> > If you find the response above accurate, I will include these details about
> > the _unsafe() function in my commit message in v2.
> >
> > >
> > > If you remove the unsafe part feel free to resend adding:
> >
> > Please confirm you still believe switching to _unsafe() is not necessary.
>
> Based on the coccinelle commit it looks like you are right, but cocinelle
> just failed to detect the case. Let's see what Nicolai and Julia respond
> before we move with any patch here.

Hello Nicolai and Julia,
Can you please review this proposed patch and the feedback comments from Rodrigo
please?

Thank you,
./drv

>
> >
> > >
> > > Reviewed-by: Rodrigo Vivi 
> > > (to both patches, this and the drrs one.
> > >
> > > Also, it looks like you could contribute with other 2 patches:
> > > drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c:64:0-23: WARNING: 
> > > pxp_terminate_fops should be defined with DEFINE_DEBUGFS_ATTRIBUTE
> > > drivers/gpu/drm/i915/gvt/debugfs.c:150:0-23: WARNING: 
> > > vgpu_scan_nonprivbb_fops should be defined with DEFINE_DEBUGFS_ATTRIBUTE
> >
> > Yes, these are on my list. Was waiting for a feedback on the first 
> > submission
> > before I send more similar patches.
> >
> > Appreciate your time and the feedback.
> >
> >
> > Regards,
> > ./drv
> >
> > >
> > > >
> > > > Signed-off-by: Deepak R Varma 
> > > > ---
> > > >  drivers/gpu/drm/i915/display/intel_fbc.c | 12 ++--
> > > >  1 file changed, 6 insertions(+), 6 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c 
> > > > b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > index b5ee5ea0d010..4b481e2f908b 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > > > @@ -1809,10 +1809,10 @@ static int 
> > > > intel_fbc_debugfs_false_color_set(void *data, u64 val)
> > > > return 0;
> > > >  }
> > > >
> > > > -DEFINE_SIMPLE_ATTRIBUTE(intel_fbc_debugfs_false_color_fops,
> > > > -   intel_fbc_debugfs_false_color_get,
> > > > -   intel_fbc_debugfs_false_color_set,
> > > > -   "%llu\n");
> > > > +DEFINE_DEBUGFS_ATTRIBUTE(intel

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Enable a PIPEDMC whenever its corresponding pipe is enabled

[Patchwork]

== Series Details ==

Series: drm/i915: Enable a PIPEDMC whenever its corresponding pipe is enabled
URL   : https://patchwork.freedesktop.org/series/112355/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12537_full -> Patchwork_112355v1_full


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/index.html

Participating hosts (14 -> 10)
--

  Missing(4): shard-rkl0 pig-kbl-iris pig-glk-j5005 pig-skl-6260u 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_112355v1_full:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@drm_fdinfo@most-busy-idle-check-all@rcs0:
- {shard-rkl}:[PASS][1] -> [FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12537/shard-rkl-2/igt@drm_fdinfo@most-busy-idle-check-...@rcs0.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/shard-rkl-2/igt@drm_fdinfo@most-busy-idle-check-...@rcs0.html

  * igt@i915_module_load@reload-with-fault-injection:
- {shard-dg1}:[PASS][3] -> [WARN][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12537/shard-dg1-13/igt@i915_module_l...@reload-with-fault-injection.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/shard-dg1-19/igt@i915_module_l...@reload-with-fault-injection.html

  * igt@kms_plane@pixel-format@pipe-b-planes:
- {shard-rkl}:[PASS][5] -> [SKIP][6] +3 similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12537/shard-rkl-6/igt@kms_plane@pixel-for...@pipe-b-planes.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/shard-rkl-1/igt@kms_plane@pixel-for...@pipe-b-planes.html

  * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes:
- {shard-rkl}:NOTRUN -> [SKIP][7] +1 similar issue
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/shard-rkl-1/igt@kms_plane@plane-panning-bottom-right-susp...@pipe-a-planes.html

  * igt@kms_plane_alpha_blend@alpha-transparent-fb:
- {shard-tglu-9}: NOTRUN -> [SKIP][8]
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/shard-tglu-9/igt@kms_plane_alpha_bl...@alpha-transparent-fb.html

  
Known issues


  Here are the changes found in Patchwork_112355v1_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_fair@basic-pace@vcs0:
- shard-glk:  NOTRUN -> [FAIL][9] ([i915#2842]) +3 similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/shard-glk5/igt@gem_exec_fair@basic-p...@vcs0.html

  * igt@gem_lmem_swapping@heavy-multi:
- shard-glk:  NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#4613])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/shard-glk9/igt@gem_lmem_swapp...@heavy-multi.html

  * igt@gem_pwrite@basic-exhaustion:
- shard-glk:  NOTRUN -> [WARN][11] ([i915#2658])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/shard-glk5/igt@gem_pwr...@basic-exhaustion.html

  * igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_mc_ccs:
- shard-glk:  NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#3886]) +4 
similar issues
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/shard-glk5/igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_mc_ccs.html

  * igt@kms_cdclk@mode-transition:
- shard-glk:  NOTRUN -> [SKIP][13] ([fdo#109271]) +71 similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/shard-glk5/igt@kms_cd...@mode-transition.html

  * igt@kms_chamelium@hdmi-hpd:
- shard-glk:  NOTRUN -> [SKIP][14] ([fdo#109271] / [fdo#111827]) +6 
similar issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/shard-glk9/igt@kms_chamel...@hdmi-hpd.html

  * igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size:
- shard-glk:  [PASS][15] -> [FAIL][16] ([i915#2346])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12537/shard-glk5/igt@kms_cursor_legacy@flip-vs-cur...@atomic-transitions-varying-size.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/shard-glk4/igt@kms_cursor_legacy@flip-vs-cur...@atomic-transitions-varying-size.html

  * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area:
- shard-glk:  NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#658]) +1 
similar issue
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/shard-glk5/igt@kms_psr2...@overlay-plane-update-sf-dmg-area.html

  * igt@sysfs_clients@sema-50:
- shard-glk:  NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#2994]) +1 
similar issue
   [18]: 
https://intel-gfx-ci.01.org

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Enable a PIPEDMC whenever its corresponding pipe is enabled

[Patchwork]

== Series Details ==

Series: drm/i915: Enable a PIPEDMC whenever its corresponding pipe is enabled
URL   : https://patchwork.freedesktop.org/series/112355/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12537 -> Patchwork_112355v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/index.html

Participating hosts (44 -> 42)
--

  Missing(2): fi-bsw-kefka fi-snb-2520m 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_112355v1:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_selftest@live@migrate:
- {bat-dg2-oem1}: [PASS][1] -> [DMESG-FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12537/bat-dg2-oem1/igt@i915_selftest@l...@migrate.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/bat-dg2-oem1/igt@i915_selftest@l...@migrate.html

  
Known issues


  Here are the changes found in Patchwork_112355v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@migrate:
- bat-adlp-4: [PASS][3] -> [DMESG-FAIL][4] ([i915#7699])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12537/bat-adlp-4/igt@i915_selftest@l...@migrate.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/bat-adlp-4/igt@i915_selftest@l...@migrate.html

  
 Possible fixes 

  * igt@gem_exec_suspend@basic-s3@smem:
- {bat-rpls-1}:   [DMESG-WARN][5] ([i915#6687]) -> [PASS][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12537/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html

  * igt@i915_selftest@live@slpc:
- {bat-rpls-1}:   [DMESG-FAIL][7] ([i915#6367]) -> [PASS][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12537/bat-rpls-1/igt@i915_selftest@l...@slpc.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/bat-rpls-1/igt@i915_selftest@l...@slpc.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#5153]: https://gitlab.freedesktop.org/drm/intel/issues/5153
  [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
  [i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
  [i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997
  [i915#7351]: https://gitlab.freedesktop.org/drm/intel/issues/7351
  [i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699


Build changes
-

  * Linux: CI_DRM_12537 -> Patchwork_112355v1

  CI-20190529: 20190529
  CI_DRM_12537: 12e6e0d4999e21d3b510487fb10646fdec3bb6b1 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7105: 305e8d105abf033cb850d1fb118e5cbfb6c9cd40 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_112355v1: 12e6e0d4999e21d3b510487fb10646fdec3bb6b1 @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

0b72b5f56045 drm/i915: Enable a PIPEDMC whenever its corresponding pipe is 
enabled

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112355v1/index.html

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Enable a PIPEDMC whenever its corresponding pipe is enabled

[Patchwork]

== Series Details ==

Series: drm/i915: Enable a PIPEDMC whenever its corresponding pipe is enabled
URL   : https://patchwork.freedesktop.org/series/112355/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Enable a PIPEDMC whenever its corresponding pipe is enabled

[Patchwork]

== Series Details ==

Series: drm/i915: Enable a PIPEDMC whenever its corresponding pipe is enabled
URL   : https://patchwork.freedesktop.org/series/112355/
State : warning

== Summary ==

Error: dim checkpatch failed
af0cece2d473 drm/i915: Enable a PIPEDMC whenever its corresponding pipe is 
enabled
-:130: CHECK:LINE_SPACING: Please don't use multiple blank lines
#130: FILE: drivers/gpu/drm/i915/display/intel_dmc_regs.h:24:
+
+

total: 0 errors, 0 warnings, 1 checks, 103 lines checked

[Intel-gfx] [PATCH] drm/i915: Enable a PIPEDMC whenever its corresponding pipe is enabled

[Imre Deak]

Make sure that PIPEDMCs are enabled whenever the corresponding pipe is
enabled.

This is required at least by the latest ADLP v2.18 firmware, which adds
a new handler enabled by default and running whenever the pipe is
enabled at the vertical referesh rate.

Bspec: 50344, 67620

Signed-off-by: Imre Deak 
---
 drivers/gpu/drm/i915/display/intel_display.c  |  5 
 drivers/gpu/drm/i915/display/intel_dmc.c  | 24 +++
 drivers/gpu/drm/i915/display/intel_dmc.h  |  4 
 drivers/gpu/drm/i915/display/intel_dmc_regs.h | 11 +
 .../drm/i915/display/intel_modeset_setup.c|  4 +++-
 5 files changed, 47 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index e75b9b2a0e015..ddbf22d5667a6 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1918,6 +1918,8 @@ static void hsw_crtc_enable(struct intel_atomic_state 
*state,
if (drm_WARN_ON(&dev_priv->drm, crtc->active))
return;
 
+   intel_dmc_enable_pipe(dev_priv, crtc->pipe);
+
if (!new_crtc_state->bigjoiner_pipes) {
intel_encoders_pre_pll_enable(state, crtc);
 
@@ -2053,6 +2055,7 @@ static void hsw_crtc_disable(struct intel_atomic_state 
*state,
 {
const struct intel_crtc_state *old_crtc_state =
intel_atomic_get_old_crtc_state(state, crtc);
+   struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 
/*
 * FIXME collapse everything to one hook.
@@ -2062,6 +2065,8 @@ static void hsw_crtc_disable(struct intel_atomic_state 
*state,
intel_encoders_disable(state, crtc);
intel_encoders_post_disable(state, crtc);
}
+
+   intel_dmc_disable_pipe(i915, crtc->pipe);
 }
 
 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c 
b/drivers/gpu/drm/i915/display/intel_dmc.c
index 905b5dcdca14f..fe8a8941dbf3a 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -108,6 +108,8 @@ MODULE_FIRMWARE(BXT_DMC_PATH);
 #define DMC_V3_MAX_MMIO_COUNT  20
 #define DMC_V1_MMIO_START_RANGE0x8
 
+#define PIPE_TO_DMC_ID(pipe)(DMC_FW_PIPEA + ((pipe) - PIPE_A))
+
 struct intel_css_header {
/* 0x09 for DMC */
u32 module_type;
@@ -407,6 +409,28 @@ static void pipedmc_clock_gating_wa(struct 
drm_i915_private *i915, bool enable)
 PIPEDMC_GATING_DIS, 0);
 }
 
+void intel_dmc_enable_pipe(struct drm_i915_private *i915, enum pipe pipe)
+{
+   if (!has_dmc_id_fw(i915, PIPE_TO_DMC_ID(pipe)))
+   return;
+
+   if (DISPLAY_VER(i915) >= 14)
+   intel_de_rmw(i915, MTL_PIPEDMC_CONTROL, 0, 
PIPEDMC_ENABLE_MTL(pipe));
+   else
+   intel_de_rmw(i915, PIPEDMC_CONTROL(pipe), 0, PIPEDMC_ENABLE);
+}
+
+void intel_dmc_disable_pipe(struct drm_i915_private *i915, enum pipe pipe)
+{
+   if (!has_dmc_id_fw(i915, PIPE_TO_DMC_ID(pipe)))
+   return;
+
+   if (DISPLAY_VER(i915) >= 14)
+   intel_de_rmw(i915, MTL_PIPEDMC_CONTROL, 
PIPEDMC_ENABLE_MTL(pipe), 0);
+   else
+   intel_de_rmw(i915, PIPEDMC_CONTROL(pipe), PIPEDMC_ENABLE, 0);
+}
+
 /**
  * intel_dmc_load_program() - write the firmware from memory to register.
  * @dev_priv: i915 drm device.
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h 
b/drivers/gpu/drm/i915/display/intel_dmc.h
index 67e03315ef999..c65a5769879fc 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -13,6 +13,8 @@
 struct drm_i915_error_state_buf;
 struct drm_i915_private;
 
+enum pipe;
+
 enum {
DMC_FW_MAIN = 0,
DMC_FW_PIPEA,
@@ -48,6 +50,8 @@ struct intel_dmc {
 void intel_dmc_ucode_init(struct drm_i915_private *i915);
 void intel_dmc_load_program(struct drm_i915_private *i915);
 void intel_dmc_disable_program(struct drm_i915_private *i915);
+void intel_dmc_enable_pipe(struct drm_i915_private *i915, enum pipe pipe);
+void intel_dmc_disable_pipe(struct drm_i915_private *i915, enum pipe pipe);
 void intel_dmc_ucode_fini(struct drm_i915_private *i915);
 void intel_dmc_ucode_suspend(struct drm_i915_private *i915);
 void intel_dmc_ucode_resume(struct drm_i915_private *i915);
diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h 
b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
index 5e5e41644ddfd..aac4f5465c6a2 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
@@ -11,6 +11,17 @@
 #define DMC_PROGRAM(addr, i)   _MMIO((addr) + (i) * 4)
 #define DMC_SSP_BASE_ADDR_GEN9 0x2FC0
 
+#define _PIPEDMC_CONTROL_A 0x45250
+#define _PIPEDMC_CONTROL_B 0x45254
+#define PIPEDMC_CONTROL(pipe)  _MMIO_PIPE(pipe, \
+   

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Fix timeslots argument for DP DSC SST case

[Patchwork]

== Series Details ==

Series: drm/i915: Fix timeslots argument for DP DSC SST case
URL   : https://patchwork.freedesktop.org/series/112349/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12536_full -> Patchwork_112349v1_full


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112349v1/index.html

Participating hosts (13 -> 10)
--

  Missing(3): pig-skl-6260u pig-kbl-iris pig-glk-j5005 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_112349v1_full:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@drm_fdinfo@idle@rcs0:
- {shard-rkl}:[PASS][1] -> [FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12536/shard-rkl-3/igt@drm_fdinfo@i...@rcs0.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112349v1/shard-rkl-4/igt@drm_fdinfo@i...@rcs0.html

  * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes:
- {shard-tglu-9}: NOTRUN -> [SKIP][3] +2 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112349v1/shard-tglu-9/igt@kms_plane@plane-panning-bottom-right-susp...@pipe-b-planes.html

  * igt@kms_plane@plane-panning-bottom-right@pipe-a-planes:
- {shard-rkl}:[SKIP][4] ([i915#1849]) -> [SKIP][5] +5 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12536/shard-rkl-2/igt@kms_plane@plane-panning-bottom-ri...@pipe-a-planes.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112349v1/shard-rkl-4/igt@kms_plane@plane-panning-bottom-ri...@pipe-a-planes.html

  * igt@kms_plane@plane-position-covered@pipe-a-planes:
- {shard-rkl}:[PASS][6] -> [SKIP][7] +1 similar issue
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12536/shard-rkl-6/igt@kms_plane@plane-position-cove...@pipe-a-planes.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112349v1/shard-rkl-3/igt@kms_plane@plane-position-cove...@pipe-a-planes.html

  * igt@kms_plane@plane-position-hole-dpms@pipe-a-planes:
- {shard-tglu}:   NOTRUN -> [SKIP][8] +1 similar issue
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112349v1/shard-tglu-6/igt@kms_plane@plane-position-hole-d...@pipe-a-planes.html

  
Known issues


  Here are the changes found in Patchwork_112349v1_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_fair@basic-pace@vecs0:
- shard-glk:  [PASS][9] -> [FAIL][10] ([i915#2842])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12536/shard-glk8/igt@gem_exec_fair@basic-p...@vecs0.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112349v1/shard-glk2/igt@gem_exec_fair@basic-p...@vecs0.html

  * igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size:
- shard-glk:  [PASS][11] -> [FAIL][12] ([i915#2346])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12536/shard-glk8/igt@kms_cursor_legacy@flip-vs-cur...@atomic-transitions-varying-size.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112349v1/shard-glk3/igt@kms_cursor_legacy@flip-vs-cur...@atomic-transitions-varying-size.html

  * igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a2:
- shard-glk:  [PASS][13] -> [FAIL][14] ([i915#79])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12536/shard-glk2/igt@kms_flip@flip-vs-expired-vbl...@a-hdmi-a2.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112349v1/shard-glk3/igt@kms_flip@flip-vs-expired-vbl...@a-hdmi-a2.html

  
 Possible fixes 

  * igt@fbdev@pan:
- {shard-tglu}:   [SKIP][15] ([i915#2582]) -> [PASS][16]
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12536/shard-tglu-6/igt@fb...@pan.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112349v1/shard-tglu-4/igt@fb...@pan.html

  * igt@fbdev@unaligned-read:
- {shard-rkl}:[SKIP][17] ([i915#2582]) -> [PASS][18]
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12536/shard-rkl-5/igt@fb...@unaligned-read.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112349v1/shard-rkl-6/igt@fb...@unaligned-read.html

  * igt@gem_ctx_persistence@legacy-engines-hang@blt:
- {shard-rkl}:[SKIP][19] ([i915#6252]) -> [PASS][20]
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12536/shard-rkl-5/igt@gem_ctx_persistence@legacy-engines-h...@blt.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112349v1/shard-rkl-1/igt@gem_ctx_persistence@legacy-engines-h...@blt.html

  * igt@gem_exec_fair@basic-deadline:
- shard-glk:  [FAIL][21] ([i915#2846]) -> [PASS][22]
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_1253

Re: [Intel-gfx] [PATCH] drm/i915: Use "%zu" to format size_t

[Andi Shyti]

On Fri, Dec 30, 2022 at 07:35:00PM +0100, Nirmoy Das wrote:
> Switch to %zu for printing size_t which will
> fix compilation warning for 32-bit build.
> 
> Reported-by: kernel test robot 
> Signed-off-by: Nirmoy Das 

Reviewed-by: Andi Shyti 

Andi

> ---
>  drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c 
> b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
> index e767791e40e0..114443096841 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
> @@ -238,7 +238,7 @@ static int shmem_get_pages(struct drm_i915_gem_object 
> *obj)
>   goto rebuild_st;
>   } else {
>   dev_warn(i915->drm.dev,
> -  "Failed to DMA remap %lu pages\n",
> +  "Failed to DMA remap %zu pages\n",
>obj->base.size >> PAGE_SHIFT);
>   goto err_pages;
>   }
> -- 
> 2.38.0

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix timeslots argument for DP DSC SST case

[Patchwork]

== Series Details ==

Series: drm/i915: Fix timeslots argument for DP DSC SST case
URL   : https://patchwork.freedesktop.org/series/112349/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12536 -> Patchwork_112349v1


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112349v1/index.html

Participating hosts (45 -> 41)
--

  Missing(4): fi-kbl-soraka fi-bsw-kefka bat-atsm-1 fi-snb-2520m 

Known issues


  Here are the changes found in Patchwork_112349v1 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@migrate:
- bat-adlp-4: [PASS][1] -> [DMESG-FAIL][2] ([i915#7699])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12536/bat-adlp-4/igt@i915_selftest@l...@migrate.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112349v1/bat-adlp-4/igt@i915_selftest@l...@migrate.html

  
 Possible fixes 

  * igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [DMESG-FAIL][3] ([i915#5334]) -> [PASS][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12536/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112349v1/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@slpc:
- {bat-rpls-1}:   [DMESG-FAIL][5] ([i915#6367]) -> [PASS][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12536/bat-rpls-1/igt@i915_selftest@l...@slpc.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112349v1/bat-rpls-1/igt@i915_selftest@l...@slpc.html

  * 
igt@kms_cursor_legacy@basic-flip-before-cursor@atomic-transitions-varying-size:
- {bat-adlp-9}:   [FAIL][7] ([i915#4289]) -> [PASS][8] +1 similar issue
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12536/bat-adlp-9/igt@kms_cursor_legacy@basic-flip-before-cur...@atomic-transitions-varying-size.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112349v1/bat-adlp-9/igt@kms_cursor_legacy@basic-flip-before-cur...@atomic-transitions-varying-size.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
  [i915#4137]: https://gitlab.freedesktop.org/drm/intel/issues/4137
  [i915#4289]: https://gitlab.freedesktop.org/drm/intel/issues/4289
  [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#5763]: https://gitlab.freedesktop.org/drm/intel/issues/5763
  [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
  [i915#7336]: https://gitlab.freedesktop.org/drm/intel/issues/7336
  [i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699


Build changes
-

  * Linux: CI_DRM_12536 -> Patchwork_112349v1

  CI-20190529: 20190529
  CI_DRM_12536: 4c18d8b1c2a1f11e99f865f60fbce9fedd3376fc @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7105: 305e8d105abf033cb850d1fb118e5cbfb6c9cd40 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_112349v1: 4c18d8b1c2a1f11e99f865f60fbce9fedd3376fc @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

7ee0789c9b7a drm/i915: Fix timeslots argument for DP DSC SST case

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112349v1/index.html

Re: [Intel-gfx] [PATCH v2] drm/i915: dell wyse 3040 shutdown fix

[Alexey Lukyachuk]

On Tue, 27 Dec 2022 20:40:03 +0300
Alexey Lukyachuk  wrote:

> On Tue, 27 Dec 2022 11:39:25 -0500
> Rodrigo Vivi  wrote:
> 
> > On Sun, Dec 25, 2022 at 09:55:08PM +0300, Alexey Lukyanchuk wrote:
> > > dell wyse 3040 doesn't peform poweroff properly, but instead remains in 
> > > turned power on state.
> > 
> > okay, the motivation is explained in the commit msg..
> > 
> > > Additional mutex_lock and 
> > > intel_crtc_wait_for_next_vblank 
> > > feature 6.2 kernel resolve this trouble.
> > 
> > but this why is not very clear... seems that by magic it was found,
> > without explaining what race we are really protecting here.
> > 
> > but even worse is:
> > what about those many random vblank waits in the code? what's the
> > reasoning?
> > 
> > > 
> > > cc: sta...@vger.kernel.org
> > > original commit Link: https://patchwork.freedesktop.org/patch/508926/
> > > fixes: fe0f1e3bfdfeb53e18f1206aea4f40b9bd1f291c
> > > Signed-off-by: Alexey Lukyanchuk 
> > > ---
> > > I got some troubles with this device (dell wyse 3040) since kernel 5.11
> > > started to use i915_driver_shutdown function. I found solution here:
> > > 
> > > https://lore.kernel.org/dri-devel/y1wd6zj8ldjpc...@intel.com/#r
> > > 
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_audio.c | 37 +++---
> > >  1 file changed, 25 insertions(+), 12 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_audio.c 
> > > b/drivers/gpu/drm/i915/display/intel_audio.c
> > > index aacbc6da8..44344ecdf 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_audio.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_audio.c
> > > @@ -336,6 +336,7 @@ static void g4x_audio_codec_disable(struct 
> > > intel_encoder *encoder,
> > >   const struct drm_connector_state 
> > > *old_conn_state)
> > >  {
> > >   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > > + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> > >   u32 eldv, tmp;
> > >  
> > >   tmp = intel_de_read(dev_priv, G4X_AUD_VID_DID);
> > > @@ -348,6 +349,9 @@ static void g4x_audio_codec_disable(struct 
> > > intel_encoder *encoder,
> > >   tmp = intel_de_read(dev_priv, G4X_AUD_CNTL_ST);
> > >   tmp &= ~eldv;
> > >   intel_de_write(dev_priv, G4X_AUD_CNTL_ST, tmp);
> > > +
> > > + intel_crtc_wait_for_next_vblank(crtc);
> > > + intel_crtc_wait_for_next_vblank(crtc);
> > >  }
> > >  
> > >  static void g4x_audio_codec_enable(struct intel_encoder *encoder,
> > > @@ -355,12 +359,15 @@ static void g4x_audio_codec_enable(struct 
> > > intel_encoder *encoder,
> > >  const struct drm_connector_state *conn_state)
> > >  {
> > >   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > >   struct drm_connector *connector = conn_state->connector;
> > >   const u8 *eld = connector->eld;
> > >   u32 eldv;
> > >   u32 tmp;
> > >   int len, i;
> > >  
> > > + intel_crtc_wait_for_next_vblank(crtc);
> > > +
> > >   tmp = intel_de_read(dev_priv, G4X_AUD_VID_DID);
> > >   if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
> > >   eldv = G4X_ELDV_DEVCL_DEVBLC;
> > > @@ -493,6 +500,7 @@ static void hsw_audio_codec_disable(struct 
> > > intel_encoder *encoder,
> > >   const struct drm_connector_state 
> > > *old_conn_state)
> > >  {
> > >   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > > + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> > >   enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
> > >   u32 tmp;
> > >  
> > > @@ -508,6 +516,10 @@ static void hsw_audio_codec_disable(struct 
> > > intel_encoder *encoder,
> > >   tmp |= AUD_CONFIG_N_VALUE_INDEX;
> > >   intel_de_write(dev_priv, HSW_AUD_CFG(cpu_transcoder), tmp);
> > >  
> > > +
> > > + intel_crtc_wait_for_next_vblank(crtc);
> > > + intel_crtc_wait_for_next_vblank(crtc);
> > > +
> > >   /* Invalidate ELD */
> > >   tmp = intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD);
> > >   tmp &= ~AUDIO_ELD_VALID(cpu_transcoder);
> > > @@ -633,6 +645,7 @@ static void hsw_audio_codec_enable(struct 
> > > intel_encoder *encoder,
> > >  const struct drm_connector_state *conn_state)
> > >  {
> > >   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > >   struct drm_connector *connector = conn_state->connector;
> > >   enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > >   const u8 *eld = connector->eld;
> > > @@ -651,12 +664,7 @@ static void hsw_audio_codec_enable(struct 
> > > intel_encoder *encoder,
> > >   tmp &= ~AUDIO_ELD_VALID(cpu_transcoder);
> > >   intel_de_write(dev_priv, HSW_AUD_PIN_ELD_CP_VLD, tmp);
> > >  
> > > - /*
> > > -  * FIXME: We're supposed to wait for vblank here, but we have vblanks
> > > -  * disabled during the mode set. The p

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Implement workaround for DP2 UHBR bandwidth check

[Patchwork]

== Series Details ==

Series: drm/i915: Implement workaround for DP2 UHBR bandwidth check
URL   : https://patchwork.freedesktop.org/series/112345/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12536 -> Patchwork_112345v1


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_112345v1 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_112345v1, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112345v1/index.html

Participating hosts (45 -> 43)
--

  Missing(2): fi-snb-2520m fi-pnv-d510 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_112345v1:

### IGT changes ###

 Possible regressions 

  * igt@i915_selftest@live@slpc:
- fi-kbl-soraka:  [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12536/fi-kbl-soraka/igt@i915_selftest@l...@slpc.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112345v1/fi-kbl-soraka/igt@i915_selftest@l...@slpc.html

  
Known issues


  Here are the changes found in Patchwork_112345v1 that come from known issues:

### IGT changes ###

 Possible fixes 

  * igt@gem_exec_suspend@basic-s3@smem:
- {bat-rpls-1}:   [DMESG-WARN][3] ([i915#6687]) -> [PASS][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12536/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112345v1/bat-rpls-1/igt@gem_exec_suspend@basic...@smem.html

  * igt@i915_module_load@load:
- fi-kbl-soraka:  [DMESG-WARN][5] ([i915#1982]) -> [PASS][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12536/fi-kbl-soraka/igt@i915_module_l...@load.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112345v1/fi-kbl-soraka/igt@i915_module_l...@load.html

  * igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [DMESG-FAIL][7] ([i915#5334]) -> [PASS][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12536/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112345v1/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
- fi-kbl-soraka:  [DMESG-FAIL][9] ([i915#5334]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12536/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112345v1/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html

  * 
igt@kms_cursor_legacy@basic-flip-before-cursor@atomic-transitions-varying-size:
- {bat-adlp-9}:   [FAIL][11] ([i915#4289]) -> [PASS][12] +1 similar 
issue
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12536/bat-adlp-9/igt@kms_cursor_legacy@basic-flip-before-cur...@atomic-transitions-varying-size.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112345v1/bat-adlp-9/igt@kms_cursor_legacy@basic-flip-before-cur...@atomic-transitions-varying-size.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
  [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
  [i915#4258]: https://gitlab.freedesktop.org/drm/intel/issues/4258
  [i915#4289]: https://gitlab.freedesktop.org/drm/intel/issues/4289
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
  [i915#7554]: https://gitlab.freedesktop.org/drm/intel/issues/7554


Build changes
-

  * Linux: CI_DRM_12536 -> Patchwork_112345v1

  CI-20190529: 20190529
  CI_DRM_12536: 4c18d8b1c2a1f11e99f865f60fbce9fedd3376fc @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7105: 305e8d105abf033cb850d1fb118e5cbfb6c9cd40 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_112345v1: 4c18d8b1c2a1f11e99f865f60fbce9fedd3376fc @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

aa51e97eae11 drm/i915: Implement workaround for DP2 UHBR bandwidth check

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112345v1/index.html

[Intel-gfx] [PATCH] drm/i915: Fix timeslots argument for DP DSC SST case

[Stanislav Lisovskiy]

We now accept timeslots param exactly how the variable
sounds: amount of timeslots, but not ratio timeslots/64.
So for SST case(when we have all timeslots for use), it
should be 64, but not 1.
This caused some issues in the tests.

Signed-off-by: Stanislav Lisovskiy 
---
 drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 13baf3cb5f934..362fb394d613c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1696,7 +1696,7 @@ intel_dp_compute_link_config(struct intel_encoder 
*encoder,
str_yes_no(ret), str_yes_no(joiner_needs_dsc),
str_yes_no(intel_dp->force_dsc_en));
ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
- conn_state, &limits, 1, true);
+ conn_state, &limits, 64, 
true);
if (ret < 0)
return ret;
}
-- 
2.37.3

Re: [Intel-gfx] [PATCH] drm/i915: Use "%zu" to format size_t

[Gwan-gyeong Mun]

Nirmoy, thanks for fixing it

Reviewed-by: Gwan-gyeong Mun 

On 12/30/22 8:35 PM, Nirmoy Das wrote:

Switch to %zu for printing size_t which will
fix compilation warning for 32-bit build.

Reported-by: kernel test robot 
Signed-off-by: Nirmoy Das 
---
  drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c 
b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
index e767791e40e0..114443096841 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
@@ -238,7 +238,7 @@ static int shmem_get_pages(struct drm_i915_gem_object *obj)
goto rebuild_st;
} else {
dev_warn(i915->drm.dev,
-"Failed to DMA remap %lu pages\n",
+"Failed to DMA remap %zu pages\n",
 obj->base.size >> PAGE_SHIFT);
goto err_pages;
}

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dsb: Remove check for dsb in dsb_commit

[Nautiyal, Ankit K]

Thanks Sai, will submit for re-run.

From: Yedireswarapu, SaiX Nandan 
Sent: Monday, January 2, 2023 5:09 PM
To: Nautiyal, Ankit K ; 
intel-gfx@lists.freedesktop.org; Vudum, Lakshminarayana 

Cc: Veesam, RavitejaX ; Latvala, Petri 

Subject: RE: ✗ Fi.CI.BAT: failure for drm/i915/dsb: Remove check for dsb in 
dsb_commit

Hi,

Series is too old, the results have already been deleted.
Need a full re-run of this series. 
https://patchwork.freedesktop.org/series/112159/

Please provide the new patchwork series revision if issue is still observed.


Thanks,
Y Sai Nandan

From: Yedireswarapu, SaiX Nandan
Sent: Monday, January 2, 2023 2:49 PM
To: Nautiyal, Ankit K 
mailto:ankit.k.nauti...@intel.com>>; 
intel-gfx@lists.freedesktop.org; Vudum, 
Lakshminarayana 
mailto:lakshminarayana.vu...@intel.com>>
Cc: Veesam, RavitejaX 
mailto:ravitejax.vee...@intel.com>>
Subject: RE: ✗ Fi.CI.BAT: failure for drm/i915/dsb: Remove check for dsb in 
dsb_commit

Hi Ankit,

Can you please provide the patchwork series link (If there needed any 
re-reporting).


Thanks,
Y Sai Nandan



From: Nautiyal, Ankit K 
mailto:ankit.k.nauti...@intel.com>>
Sent: Monday, January 2, 2023 2:17 PM
To: intel-gfx@lists.freedesktop.org; 
Vudum, Lakshminarayana 
mailto:lakshminarayana.vu...@intel.com>>; 
Yedireswarapu, SaiX Nandan 
mailto:saix.nandan.yedireswar...@intel.com>>
Subject: Re: ✗ Fi.CI.BAT: failure for drm/i915/dsb: Remove check for dsb in 
dsb_commit


Hi Lakshmi/Sai

The following issues are known issues, not related to the patch:

  *   igt@i915_selftest@live@execlists: 
https://gitlab.freedesktop.org/drm/intel/-/issues/2940
fi-bsw-n3050: 
PASS
 -> 
INCOMPLETE

  *   igt@i915_selftest@live@guc_multi_lrc: 
https://gitlab.freedesktop.org/drm/intel/-/issues/7174
 *   fi-kbl-soraka: 
PASS
 -> 
INCOMPLETE



Regards,

Ankit


On 12/22/2022 10:21 PM, Patchwork wrote:
Patch Details
Series:
drm/i915/dsb: Remove check for dsb in dsb_commit
URL:
https://patchwork.freedesktop.org/series/112159/
State:
failure
Details:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112159v1/index.html
CI Bug Log - changes from CI_DRM_12522 -> Patchwork_112159v1
Summary

FAILURE

Serious unknown changes coming with Patchwork_112159v1 absolutely need to be
verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_112159v1, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.

External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112159v1/index.html

Participating hosts (44 -> 45)

Additional (3): bat-adlm-1 bat-atsm-1 fi-tgl-dsi
Missing (2): fi-hsw-4770 fi-pnv-d510

Possible new issues

Here are the unknown changes that may have been introduced in 
Patchwork_112159v1:

IGT changes
Possible regressions

  *   igt@i915_selftest@live@execlists:

 *   fi-bsw-n3050: 
PASS
 -> 
INCOMPLETE

  *   igt@i915_selftest@live@guc_multi_lrc:

 *   fi-kbl-soraka: 
PASS
 -> 
INCOMPLETE

Known issues

Here are the changes found in Patchwork_112159v1 that come from known issues:

IGT changes
Issues hit

  *   igt@gem_exec_suspend@basic-s3@smem:

 *   fi-rkl-11600: NOTRUN -> 
FAIL
 (fdo#103375)

  *   igt@kms_chamelium@common-hpd-after-suspend:

 *   fi-rkl-11600: NOTRUN -> 
SKIP
 (fdo#111827)

  *   igt@runner@aborted:

 *   fi-bsw-n3050: NOTRUN -> 
FAIL
 (fdo#109271 / 
i915#4312)

Possible fixes

  *   igt@i915_selftest@live@execlists:

   

Re: [Intel-gfx] [RFC PATCH 00/20] Initial Xe driver submission

[Jani Nikula]

On Mon, 02 Jan 2023, Thomas Zimmermann  wrote:
> Hi
>
> Am 22.12.22 um 23:21 schrieb Matthew Brost:
>> Hello,
>> 
>> This is a submission for Xe, a new driver for Intel GPUs that supports both
>> integrated and discrete platforms starting with Tiger Lake (first platform 
>> with
>> Intel Xe Architecture). The intention of this new driver is to have a fresh 
>> base
>> to work from that is unencumbered by older platforms, whilst also taking the
>> opportunity to rearchitect our driver to increase sharing across the drm
>> subsystem, both leveraging and allowing us to contribute more towards other
>> shared components like TTM and drm/scheduler. The memory model is based on VM
>> bind which is similar to the i915 implementation. Likewise the execbuf
>> implementation for Xe is very similar to execbuf3 in the i915 [1].
>
> After Xe has stabilized, will i915 loose the ability to drive this 
> hardware (and possibly other)?  I'm specfically thinking of the i915 
> code that requires TTM. Keeping that dependecy within Xe only might 
> benefit DRM as a whole.

There's going to be a number of platforms supported by both drivers, and
from purely a i915 standpoint dropping any currently supported platforms
or that dependency from i915 would be a regression.

>> 
>> The code is at a stage where it is already functional and has experimental
>> support for multiple platforms starting from Tiger Lake, with initial support
>> implemented in Mesa (for Iris and Anv, our OpenGL and Vulkan drivers), as 
>> well
>> as in NEO (for OpenCL and Level0). A Mesa MR has been posted [2] and NEO
>> implementation will be released publicly early next year. We also have a 
>> suite
>> of IGTs for XE that will appear on the IGT list shortly.
>> 
>> It has been built with the assumption of supporting multiple architectures 
>> from
>> the get-go, right now with tests running both on X86 and ARM hosts. And we
>> intend to continue working on it and improving on it as part of the kernel
>> community upstream.
>> 
>> The new Xe driver leverages a lot from i915 and work on i915 continues as we
>> ready Xe for production throughout 2023.
>> 
>> As for display, the intent is to share the display code with the i915 driver 
>> so
>> that there is maximum reuse there. Currently this is being done by compiling 
>> the
>> display code twice, but alternatives to that are under consideration and we 
>> want
>> to have more discussion on what the best final solution will look like over 
>> the
>> next few months. Right now, work is ongoing in refactoring the display 
>> codebase
>> to remove as much as possible any unnecessary dependencies on i915 specific 
>> data
>> structures there..
>
> Could both drivers reside in a common parent directory and share 
> something like a DRM Intel helper module with the common code? This 
> would fit well with the common design of DRM helpers.

I think it's too early to tell.

For one thing, setting that up would be a lot of up front infrastructure
work. I'm not sure how to even pull that off when Xe is still
out-of-tree and i915 development plunges on upstream as ever.

For another, realistically, the overlap between supported platforms is
going to end at some point, and eventually new platforms are only going
to be supported with Xe. That's going to open up new possibilities for
refactoring also the display code. I think it would be premature to lock
in to a common directory structure or a common helper module at this
point.

I'm not saying no to the idea, and we've contemplated it before, but I
think there are still too many moving parts to decide to go that way.


BR,
Jani.


>
> Best regards
> Thomas
>
>> 
>> We currently have 2 submission backends, execlists and GuC. The execlist is
>> meant mostly for testing and is not fully functional while GuC backend is 
>> fully
>> functional. As with the i915 and GuC submission, in Xe the GuC firmware is
>> required and should be placed in /lib/firmware/xe.
>> 
>> The GuC firmware can be found in the below location:
>> https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git/tree/i915
>> 
>> The easiest way to setup firmware is:
>> cp -r /lib/firmware/i915 /lib/firmware/xe
>> 
>> The code has been organized such that we have all patches that touch areas
>> outside of drm/xe first for review, and then the actual new driver in a 
>> separate
>> commit. The code which is outside of drm/xe is included in this RFC while
>> drm/xe is not due to the size of the commit. The drm/xe is code is available 
>> in
>> a public repo listed below.
>> 
>> Xe driver commit:
>> https://cgit.freedesktop.org/drm/drm-xe/commit/?h=drm-xe-next&id=9cb016ebbb6a275f57b1cb512b95d5a842391ad7
>> 
>> Xe kernel repo:
>> https://cgit.freedesktop.org/drm/drm-xe/
>> 
>> There's a lot of work still to happen on Xe but we're very excited about it 
>> and
>> wanted to share it early and welcome feedback and discussion.
>> 
>> Cheers,
>> Matthew Brost
>> 
>> [1] https://patchwork.freedeskto

[Intel-gfx] [PATCH] drm/i915: Implement workaround for DP2 UHBR bandwidth check

[Stanislav Lisovskiy]

According to spec, we should check if output_bpp * pixel_rate is less
than DDI clock * 72, if UHBR is used.

Signed-off-by: Stanislav Lisovskiy 
---
 drivers/gpu/drm/i915/display/intel_dp.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index bf80f296a8fdb..13baf3cb5f934 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1582,6 +1582,17 @@ int intel_dp_dsc_compute_config(struct intel_dp 
*intel_dp,
drm_dbg_kms(&dev_priv->drm, "DSC: compressed bpp %d slice count 
%d\n",
pipe_config->dsc.compressed_bpp,
pipe_config->dsc.slice_count);
+
+   /* wa1406899791 */
+   if (intel_dp_is_uhbr(pipe_config)) {
+   int output_bpp = pipe_config->dsc.compressed_bpp;
+
+   if (output_bpp * adjusted_mode->crtc_clock >=
+   pipe_config->port_clock * 72) {
+   drm_dbg_kms(&dev_priv->drm, "DP2 UHBR check 
failed\n");
+   return -EINVAL;
+   }
+   }
}
/*
 * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
-- 
2.37.3

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dsb: Remove check for dsb in dsb_commit

[Yedireswarapu, SaiX Nandan]

Hi,

Series is too old, the results have already been deleted.
Need a full re-run of this series. 
https://patchwork.freedesktop.org/series/112159/

Please provide the new patchwork series revision if issue is still observed.


Thanks,
Y Sai Nandan

From: Yedireswarapu, SaiX Nandan
Sent: Monday, January 2, 2023 2:49 PM
To: Nautiyal, Ankit K ; 
intel-gfx@lists.freedesktop.org; Vudum, Lakshminarayana 

Cc: Veesam, RavitejaX 
Subject: RE: ✗ Fi.CI.BAT: failure for drm/i915/dsb: Remove check for dsb in 
dsb_commit

Hi Ankit,

Can you please provide the patchwork series link (If there needed any 
re-reporting).


Thanks,
Y Sai Nandan



From: Nautiyal, Ankit K 
mailto:ankit.k.nauti...@intel.com>>
Sent: Monday, January 2, 2023 2:17 PM
To: intel-gfx@lists.freedesktop.org; 
Vudum, Lakshminarayana 
mailto:lakshminarayana.vu...@intel.com>>; 
Yedireswarapu, SaiX Nandan 
mailto:saix.nandan.yedireswar...@intel.com>>
Subject: Re: ✗ Fi.CI.BAT: failure for drm/i915/dsb: Remove check for dsb in 
dsb_commit


Hi Lakshmi/Sai

The following issues are known issues, not related to the patch:

  *   igt@i915_selftest@live@execlists: 
https://gitlab.freedesktop.org/drm/intel/-/issues/2940
fi-bsw-n3050: 
PASS
 -> 
INCOMPLETE

  *   igt@i915_selftest@live@guc_multi_lrc: 
https://gitlab.freedesktop.org/drm/intel/-/issues/7174
 *   fi-kbl-soraka: 
PASS
 -> 
INCOMPLETE



Regards,

Ankit


On 12/22/2022 10:21 PM, Patchwork wrote:
Patch Details
Series:
drm/i915/dsb: Remove check for dsb in dsb_commit
URL:
https://patchwork.freedesktop.org/series/112159/
State:
failure
Details:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112159v1/index.html
CI Bug Log - changes from CI_DRM_12522 -> Patchwork_112159v1
Summary

FAILURE

Serious unknown changes coming with Patchwork_112159v1 absolutely need to be
verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_112159v1, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.

External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112159v1/index.html

Participating hosts (44 -> 45)

Additional (3): bat-adlm-1 bat-atsm-1 fi-tgl-dsi
Missing (2): fi-hsw-4770 fi-pnv-d510

Possible new issues

Here are the unknown changes that may have been introduced in 
Patchwork_112159v1:

IGT changes
Possible regressions

  *   igt@i915_selftest@live@execlists:

 *   fi-bsw-n3050: 
PASS
 -> 
INCOMPLETE

  *   igt@i915_selftest@live@guc_multi_lrc:

 *   fi-kbl-soraka: 
PASS
 -> 
INCOMPLETE

Known issues

Here are the changes found in Patchwork_112159v1 that come from known issues:

IGT changes
Issues hit

  *   igt@gem_exec_suspend@basic-s3@smem:

 *   fi-rkl-11600: NOTRUN -> 
FAIL
 (fdo#103375)

  *   igt@kms_chamelium@common-hpd-after-suspend:

 *   fi-rkl-11600: NOTRUN -> 
SKIP
 (fdo#111827)

  *   igt@runner@aborted:

 *   fi-bsw-n3050: NOTRUN -> 
FAIL
 (fdo#109271 / 
i915#4312)

Possible fixes

  *   igt@i915_selftest@live@execlists:

 *   fi-apl-guc: 
FAIL
 -> 
PASS
 +11 similar issues

  *   igt@i915_selftest@live@gt_heartbeat:

 *   fi-apl-guc: 
DMESG-FAIL
 (i915#5334

Re: [Intel-gfx] [RFC 1/4] drm/i915/quirks: Add quirk for 480MHz CDCLK step

[Jani Nikula]

On Mon, 02 Jan 2023, Jani Nikula  wrote:
> On Mon, 02 Jan 2023, Chaitanya Kumar Borah  
> wrote:
>> A new CDCLK step of 480MHz has been added on SKUs that has a
>> RPL-U device id. This is done to support 120Hz displays with
>> more efficiency.
>>
>> RPL-U device ids are currently added within the RPL-P sub
>> platform. It seems to be an overkill to add a separate sub
>> platform just to support this change. Therefore, quirks
>> are a good way to achieve the same.
>
> The thing is, this part is *not* a quirk. It's basic enabling for RPL-U.
>
> If you start conflating quirks and basic enabling to avoid overkill,
> you're eventually going to end up in all kinds of trouble with
> maintenance.

Please start off with adding RPL-U as a subplatform, and let's worry
about the CDCLK after that.

BR,
Jani.

>
>
> BR,
> Jani.
>
>>
>> BSpec: 55409
>>
>> Signed-off-by: Chaitanya Kumar Borah 
>> ---
>>  drivers/gpu/drm/i915/display/intel_quirks.c | 14 ++
>>  drivers/gpu/drm/i915/display/intel_quirks.h |  1 +
>>  2 files changed, 15 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_quirks.c 
>> b/drivers/gpu/drm/i915/display/intel_quirks.c
>> index 6e48d3bcdfec..0a30499835b3 100644
>> --- a/drivers/gpu/drm/i915/display/intel_quirks.c
>> +++ b/drivers/gpu/drm/i915/display/intel_quirks.c
>> @@ -65,6 +65,16 @@ static void quirk_no_pps_backlight_power_hook(struct 
>> drm_i915_private *i915)
>>  drm_info(&i915->drm, "Applying no pps backlight power quirk\n");
>>  }
>>  
>> +/*
>> + * A new step of 480MHz has been added on SKUs that have a RPL-U device id.
>> + * This particular step is to better support 120Hz panels.
>> + */
>> +static void quirk_480mhz_cdclk_step_hook(struct drm_i915_private *i915)
>> +{
>> +intel_set_quirk(i915, QUIRK_480MHZ_CDCLK_STEP);
>> +drm_info(&i915->drm, "Applying 480MHz CDCLK step quirk\n");
>> +}
>> +
>>  struct intel_quirk {
>>  int device;
>>  int subsystem_vendor;
>> @@ -199,6 +209,10 @@ static struct intel_quirk intel_quirks[] = {
>>  /* ECS Liva Q2 */
>>  { 0x3185, 0x1019, 0xa94d, quirk_increase_ddi_disabled_time },
>>  { 0x3184, 0x1019, 0xa94d, quirk_increase_ddi_disabled_time },
>> +/* RPL-U */
>> +{ 0xA7A1, PCI_ANY_ID, PCI_ANY_ID, quirk_480mhz_cdclk_step_hook },
>> +{ 0xA721, PCI_ANY_ID, PCI_ANY_ID, quirk_480mhz_cdclk_step_hook },
>> +{ 0xA7A9, PCI_ANY_ID, PCI_ANY_ID, quirk_480mhz_cdclk_step_hook },
>>  };
>>  
>>  void intel_init_quirks(struct drm_i915_private *i915)
>> diff --git a/drivers/gpu/drm/i915/display/intel_quirks.h 
>> b/drivers/gpu/drm/i915/display/intel_quirks.h
>> index 10a4d163149f..71e05684f5f4 100644
>> --- a/drivers/gpu/drm/i915/display/intel_quirks.h
>> +++ b/drivers/gpu/drm/i915/display/intel_quirks.h
>> @@ -17,6 +17,7 @@ enum intel_quirk_id {
>>  QUIRK_INVERT_BRIGHTNESS,
>>  QUIRK_LVDS_SSC_DISABLE,
>>  QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK,
>> +QUIRK_480MHZ_CDCLK_STEP,
>>  };
>>  
>>  void intel_init_quirks(struct drm_i915_private *i915);

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH v7 0/2] drm/i915/mtl: handle some MTL scaler limitations

[Coelho, Luciano]

On Fri, 2022-12-23 at 15:05 +0200, Luca Coelho wrote:
> Hi,
> 
> Here's an updated version of the patches after Ville's last comments.
> The versioning history is in the patches themselves.
> 
> Please review.
> 
> Cheers,
> Luca.
> 
> 
> Animesh Manna (1):
>   drm/i915/mtl: update scaler source and destination limits for MTL
> 
> Luca Coelho (1):
>   drm/i915/mtl: limit second scaler vertical scaling in ver >= 14
> 
>  drivers/gpu/drm/i915/display/intel_atomic.c | 85 ++---
>  drivers/gpu/drm/i915/display/skl_scaler.c   | 40 --
>  2 files changed, 107 insertions(+), 18 deletions(-)
> 

Hi Ville,

Can you please review this new revision of my patchset? For some reason
I forgot to CC you on this one. 😞

Thanks!

--
Cheers,
Luca.

Re: [Intel-gfx] [RFC 3/4] drm/i915: Initialize intel quirks before CDCLK initialization

[Jani Nikula]

On Mon, 02 Jan 2023, Chaitanya Kumar Borah  
wrote:
> With addition of new quirk QUIRK_480MHZ_CDCLK_STEP, it is imperative
> that quirks should be initialized before CDCLK initialization. Refactor
> the code accordingly.

Any refactors here should improve the clarity between display and the
rest; this is going the opposite direction with calling display code
from common driver code.

BR,
Jani.


>
> Signed-off-by: Chaitanya Kumar Borah 
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 2 --
>  drivers/gpu/drm/i915/i915_driver.c   | 2 ++
>  2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> b/drivers/gpu/drm/i915/display/intel_display.c
> index e75b9b2a0e01..5c71fd83c25b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -8666,8 +8666,6 @@ int intel_modeset_init_noirq(struct drm_i915_private 
> *i915)
>   INIT_WORK(&i915->display.atomic_helper.free_work,
> intel_atomic_helper_free_state_worker);
>  
> - intel_init_quirks(i915);
> -
>   intel_fbc_init(i915);
>  
>   return 0;
> diff --git a/drivers/gpu/drm/i915/i915_driver.c 
> b/drivers/gpu/drm/i915/i915_driver.c
> index c1e427ba57ae..4d1cb46f9863 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -104,6 +104,7 @@
>  #include "intel_pm.h"
>  #include "intel_region_ttm.h"
>  #include "vlv_suspend.h"
> +#include "display/intel_quirks.h"
>  
>  static const struct drm_driver i915_drm_driver;
>  
> @@ -388,6 +389,7 @@ static int i915_driver_early_probe(struct 
> drm_i915_private *dev_priv)
>   if (ret < 0)
>   goto err_gem;
>   intel_irq_init(dev_priv);
> + intel_init_quirks(dev_priv);
>   intel_init_display_hooks(dev_priv);
>   intel_init_clock_gating_hooks(dev_priv);

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [RFC 2/4] drm/i915/display: Add 480 MHz CDCLK steps for RPL-U

[Jani Nikula]

On Mon, 02 Jan 2023, Chaitanya Kumar Borah  
wrote:
> A new step of 480MHz has been added on SKUs that have a RPL-U
> device id to support 120Hz displays more efficiently. Use a
> new quirk to identify the machine for which this change needs
> to be applied.

Again, it's not a quirk, and should not be added as one.

BR,
Jani.

>
> BSpec: 55409
>
> Signed-off-by: Chaitanya Kumar Borah 
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 25 ++
>  1 file changed, 25 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 0c107a38f9d0..f5df0a806765 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -38,6 +38,7 @@
>  #include "intel_pcode.h"
>  #include "intel_psr.h"
>  #include "vlv_sideband.h"
> +#include "intel_quirks.h"
>  
>  /**
>   * DOC: CDCLK / RAWCLK
> @@ -1329,6 +1330,27 @@ static const struct intel_cdclk_vals 
> adlp_cdclk_table[] = {
>   {}
>  };
>  
> +static const struct intel_cdclk_vals rplu_cdclk_table[] = {
> + { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
> + { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
> + { .refclk = 19200, .cdclk = 48, .divider = 2, .ratio = 50 },
> + { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
> + { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
> +
> + { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
> + { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
> + { .refclk = 24000, .cdclk = 48, .divider = 2, .ratio = 40 },
> + { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
> + { .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 },
> +
> + { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
> + { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
> + { .refclk = 38400, .cdclk = 48, .divider = 2, .ratio = 25 },
> + { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
> + { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
> + {}
> +};
> +
>  static const struct intel_cdclk_vals dg2_cdclk_table[] = {
>   { .refclk = 38400, .cdclk = 163200, .divider = 2, .ratio = 34, 
> .waveform = 0x },
>   { .refclk = 38400, .cdclk = 204000, .divider = 2, .ratio = 34, 
> .waveform = 0x9248 },
> @@ -3353,6 +3375,9 @@ void intel_init_cdclk_hooks(struct drm_i915_private 
> *dev_priv)
>   /* Wa_22011320316:adl-p[a0] */
>   if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>   dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;
> + /* BSpec: 55409 */

We don't bother with bspec references in code. Add them in commit
messages.

> + else if (intel_has_quirk(dev_priv, QUIRK_480MHZ_CDCLK_STEP))
> + dev_priv->display.cdclk.table = rplu_cdclk_table;
>   else
>   dev_priv->display.cdclk.table = adlp_cdclk_table;
>   } else if (IS_ROCKETLAKE(dev_priv)) {

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [RFC 1/4] drm/i915/quirks: Add quirk for 480MHz CDCLK step

[Jani Nikula]

On Mon, 02 Jan 2023, Chaitanya Kumar Borah  
wrote:
> A new CDCLK step of 480MHz has been added on SKUs that has a
> RPL-U device id. This is done to support 120Hz displays with
> more efficiency.
>
> RPL-U device ids are currently added within the RPL-P sub
> platform. It seems to be an overkill to add a separate sub
> platform just to support this change. Therefore, quirks
> are a good way to achieve the same.

The thing is, this part is *not* a quirk. It's basic enabling for RPL-U.

If you start conflating quirks and basic enabling to avoid overkill,
you're eventually going to end up in all kinds of trouble with
maintenance.


BR,
Jani.

>
> BSpec: 55409
>
> Signed-off-by: Chaitanya Kumar Borah 
> ---
>  drivers/gpu/drm/i915/display/intel_quirks.c | 14 ++
>  drivers/gpu/drm/i915/display/intel_quirks.h |  1 +
>  2 files changed, 15 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_quirks.c 
> b/drivers/gpu/drm/i915/display/intel_quirks.c
> index 6e48d3bcdfec..0a30499835b3 100644
> --- a/drivers/gpu/drm/i915/display/intel_quirks.c
> +++ b/drivers/gpu/drm/i915/display/intel_quirks.c
> @@ -65,6 +65,16 @@ static void quirk_no_pps_backlight_power_hook(struct 
> drm_i915_private *i915)
>   drm_info(&i915->drm, "Applying no pps backlight power quirk\n");
>  }
>  
> +/*
> + * A new step of 480MHz has been added on SKUs that have a RPL-U device id.
> + * This particular step is to better support 120Hz panels.
> + */
> +static void quirk_480mhz_cdclk_step_hook(struct drm_i915_private *i915)
> +{
> + intel_set_quirk(i915, QUIRK_480MHZ_CDCLK_STEP);
> + drm_info(&i915->drm, "Applying 480MHz CDCLK step quirk\n");
> +}
> +
>  struct intel_quirk {
>   int device;
>   int subsystem_vendor;
> @@ -199,6 +209,10 @@ static struct intel_quirk intel_quirks[] = {
>   /* ECS Liva Q2 */
>   { 0x3185, 0x1019, 0xa94d, quirk_increase_ddi_disabled_time },
>   { 0x3184, 0x1019, 0xa94d, quirk_increase_ddi_disabled_time },
> + /* RPL-U */
> + { 0xA7A1, PCI_ANY_ID, PCI_ANY_ID, quirk_480mhz_cdclk_step_hook },
> + { 0xA721, PCI_ANY_ID, PCI_ANY_ID, quirk_480mhz_cdclk_step_hook },
> + { 0xA7A9, PCI_ANY_ID, PCI_ANY_ID, quirk_480mhz_cdclk_step_hook },
>  };
>  
>  void intel_init_quirks(struct drm_i915_private *i915)
> diff --git a/drivers/gpu/drm/i915/display/intel_quirks.h 
> b/drivers/gpu/drm/i915/display/intel_quirks.h
> index 10a4d163149f..71e05684f5f4 100644
> --- a/drivers/gpu/drm/i915/display/intel_quirks.h
> +++ b/drivers/gpu/drm/i915/display/intel_quirks.h
> @@ -17,6 +17,7 @@ enum intel_quirk_id {
>   QUIRK_INVERT_BRIGHTNESS,
>   QUIRK_LVDS_SSC_DISABLE,
>   QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK,
> + QUIRK_480MHZ_CDCLK_STEP,
>  };
>  
>  void intel_init_quirks(struct drm_i915_private *i915);

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] ✗ Fi.CI.BAT: failure for Add new CDCLK step for RPL-U (rev2)

[Patchwork]

== Series Details ==

Series: Add new CDCLK step for RPL-U (rev2)
URL   : https://patchwork.freedesktop.org/series/111472/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12534 -> Patchwork_111472v2


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_111472v2 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_111472v2, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v2/index.html

Participating hosts (44 -> 40)
--

  Missing(4): fi-kbl-soraka fi-rkl-11600 fi-bsw-kefka fi-snb-2520m 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_111472v2:

### IGT changes ###

 Possible regressions 

  * igt@debugfs_test@read_all_entries:
- fi-icl-u2:  [PASS][1] -> [ABORT][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12534/fi-icl-u2/igt@debugfs_test@read_all_entries.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v2/fi-icl-u2/igt@debugfs_test@read_all_entries.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_flip@basic-flip-vs-wf_vblank:
- {bat-dg1-7}:[SKIP][3] ([i915#4078]) -> [SKIP][4] +3 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12534/bat-dg1-7/igt@kms_flip@basic-flip-vs-wf_vblank.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v2/bat-dg1-7/igt@kms_flip@basic-flip-vs-wf_vblank.html

  
Known issues


  Here are the changes found in Patchwork_111472v2 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@migrate:
- bat-adlp-4: [PASS][5] -> [DMESG-FAIL][6] ([i915#7699])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12534/bat-adlp-4/igt@i915_selftest@l...@migrate.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v2/bat-adlp-4/igt@i915_selftest@l...@migrate.html

  * igt@runner@aborted:
- fi-icl-u2:  NOTRUN -> [FAIL][7] ([i915#4312])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v2/fi-icl-u2/igt@run...@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
  [i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997
  [i915#7654]: https://gitlab.freedesktop.org/drm/intel/issues/7654
  [i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699


Build changes
-

  * Linux: CI_DRM_12534 -> Patchwork_111472v2

  CI-20190529: 20190529
  CI_DRM_12534: 2eb7b99b8190efc92b708a51e41c5f7f86843e42 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7105: 305e8d105abf033cb850d1fb118e5cbfb6c9cd40 @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_111472v2: 2eb7b99b8190efc92b708a51e41c5f7f86843e42 @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

29768498ea74 drm/i915: Apply CDCLK quirk only on QS parts
a7821e51f61e drm/i915: Initialize intel quirks before CDCLK initialization
9d8bb24ebdf6 drm/i915/display: Add 480 MHz CDCLK steps for RPL-U
87d7b9c95594 drm/i915/quirks: Add quirk for 480MHz CDCLK step

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v2/index.html

[Intel-gfx] ✗ Fi.CI.BAT: failure for Enable HDCP2.x via GSC CS (rev5)

[Patchwork]

== Series Details ==

Series: Enable HDCP2.x via GSC CS (rev5)
URL   : https://patchwork.freedesktop.org/series/111876/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12534 -> Patchwork_111876v5


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_111876v5 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_111876v5, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111876v5/index.html

Participating hosts (44 -> 41)
--

  Missing(3): fi-kbl-soraka fi-snb-2520m fi-bsw-n3050 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_111876v5:

### IGT changes ###

 Possible regressions 

  * igt@debugfs_test@read_all_entries:
- fi-icl-u2:  [PASS][1] -> [ABORT][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12534/fi-icl-u2/igt@debugfs_test@read_all_entries.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111876v5/fi-icl-u2/igt@debugfs_test@read_all_entries.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_selftest@live@client:
- {bat-dg2-8}:[PASS][3] -> [FAIL][4] +24 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12534/bat-dg2-8/igt@i915_selftest@l...@client.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111876v5/bat-dg2-8/igt@i915_selftest@l...@client.html

  * igt@i915_selftest@live@coherency:
- {bat-dg2-9}:[PASS][5] -> [FAIL][6] +24 similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12534/bat-dg2-9/igt@i915_selftest@l...@coherency.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111876v5/bat-dg2-9/igt@i915_selftest@l...@coherency.html

  * igt@i915_selftest@live@gt_mocs:
- {bat-dg2-11}:   [PASS][7] -> [DMESG-WARN][8] +8 similar issues
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12534/bat-dg2-11/igt@i915_selftest@live@gt_mocs.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111876v5/bat-dg2-11/igt@i915_selftest@live@gt_mocs.html
- {bat-atsm-1}:   [PASS][9] -> [DMESG-WARN][10] +8 similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12534/bat-atsm-1/igt@i915_selftest@live@gt_mocs.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111876v5/bat-atsm-1/igt@i915_selftest@live@gt_mocs.html
- {bat-dg2-8}:[PASS][11] -> [DMESG-WARN][12] +9 similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12534/bat-dg2-8/igt@i915_selftest@live@gt_mocs.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111876v5/bat-dg2-8/igt@i915_selftest@live@gt_mocs.html

  * igt@i915_selftest@live@gt_timelines:
- {bat-dg2-9}:[PASS][13] -> [DMESG-WARN][14] +9 similar issues
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12534/bat-dg2-9/igt@i915_selftest@live@gt_timelines.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111876v5/bat-dg2-9/igt@i915_selftest@live@gt_timelines.html

  * igt@i915_selftest@live@hangcheck:
- {bat-atsm-1}:   [PASS][15] -> [FAIL][16] +24 similar issues
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12534/bat-atsm-1/igt@i915_selftest@l...@hangcheck.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111876v5/bat-atsm-1/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@perf:
- {bat-dg2-11}:   [PASS][17] -> [FAIL][18] +24 similar issues
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12534/bat-dg2-11/igt@i915_selftest@l...@perf.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111876v5/bat-dg2-11/igt@i915_selftest@l...@perf.html

  * igt@i915_selftest@live@uncore:
- {bat-adln-1}:   [PASS][19] -> [INCOMPLETE][20]
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12534/bat-adln-1/igt@i915_selftest@l...@uncore.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111876v5/bat-adln-1/igt@i915_selftest@l...@uncore.html

  * igt@kms_flip@basic-flip-vs-wf_vblank:
- {bat-dg1-7}:[SKIP][21] ([i915#4078]) -> [SKIP][22] +3 similar 
issues
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12534/bat-dg1-7/igt@kms_flip@basic-flip-vs-wf_vblank.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111876v5/bat-dg1-7/igt@kms_flip@basic-flip-vs-wf_vblank.html

  
Known issues


  Here are the changes found in Patchwork_111876v5 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_module_load@load:
- fi-rkl-11600:   [

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dsb: Remove check for dsb in dsb_commit

[Yedireswarapu, SaiX Nandan]

Hi Ankit,

Can you please provide the patchwork series link (If there needed any 
re-reporting).


Thanks,
Y Sai Nandan



From: Nautiyal, Ankit K 
Sent: Monday, January 2, 2023 2:17 PM
To: intel-gfx@lists.freedesktop.org; Vudum, Lakshminarayana 
; Yedireswarapu, SaiX Nandan 

Subject: Re: ✗ Fi.CI.BAT: failure for drm/i915/dsb: Remove check for dsb in 
dsb_commit


Hi Lakshmi/Sai

The following issues are known issues, not related to the patch:

  *   igt@i915_selftest@live@execlists: 
https://gitlab.freedesktop.org/drm/intel/-/issues/2940
fi-bsw-n3050: 
PASS
 -> 
INCOMPLETE

  *   igt@i915_selftest@live@guc_multi_lrc: 
https://gitlab.freedesktop.org/drm/intel/-/issues/7174
 *   fi-kbl-soraka: 
PASS
 -> 
INCOMPLETE



Regards,

Ankit


On 12/22/2022 10:21 PM, Patchwork wrote:
Patch Details
Series:
drm/i915/dsb: Remove check for dsb in dsb_commit
URL:
https://patchwork.freedesktop.org/series/112159/
State:
failure
Details:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112159v1/index.html
CI Bug Log - changes from CI_DRM_12522 -> Patchwork_112159v1
Summary

FAILURE

Serious unknown changes coming with Patchwork_112159v1 absolutely need to be
verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_112159v1, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.

External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112159v1/index.html

Participating hosts (44 -> 45)

Additional (3): bat-adlm-1 bat-atsm-1 fi-tgl-dsi
Missing (2): fi-hsw-4770 fi-pnv-d510

Possible new issues

Here are the unknown changes that may have been introduced in 
Patchwork_112159v1:

IGT changes
Possible regressions

  *   igt@i915_selftest@live@execlists:

 *   fi-bsw-n3050: 
PASS
 -> 
INCOMPLETE

  *   igt@i915_selftest@live@guc_multi_lrc:

 *   fi-kbl-soraka: 
PASS
 -> 
INCOMPLETE

Known issues

Here are the changes found in Patchwork_112159v1 that come from known issues:

IGT changes
Issues hit

  *   igt@gem_exec_suspend@basic-s3@smem:

 *   fi-rkl-11600: NOTRUN -> 
FAIL
 (fdo#103375)

  *   igt@kms_chamelium@common-hpd-after-suspend:

 *   fi-rkl-11600: NOTRUN -> 
SKIP
 (fdo#111827)

  *   igt@runner@aborted:

 *   fi-bsw-n3050: NOTRUN -> 
FAIL
 (fdo#109271 / 
i915#4312)

Possible fixes

  *   igt@i915_selftest@live@execlists:

 *   fi-apl-guc: 
FAIL
 -> 
PASS
 +11 similar issues

  *   igt@i915_selftest@live@gt_heartbeat:

 *   fi-apl-guc: 
DMESG-FAIL
 (i915#5334) -> 
PASS

  *   igt@i915_suspend@basic-s3-without-i915:

 *   fi-rkl-11600: 
INCOMPLETE
 (i915#4817) -> 
PASS

Warnings

  *   igt@kms_chamelium@common-hpd-after-suspend:

 *   fi-apl-guc: 
SKIP

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dsb: Remove check for dsb in dsb_commit

[Nautiyal, Ankit K]

Hi Lakshmi/Sai

The following issues are known issues, not related to the patch:

 *

   igt@i915_selftest@live@execlists:
   https://gitlab.freedesktop.org/drm/intel/-/issues/2940

   fi-bsw-n3050: PASS
   

   -> INCOMPLETE
   


 *

   igt@i915_selftest@live@guc_multi_lrc:
   https://gitlab.freedesktop.org/drm/intel/-/issues/7174

 o fi-kbl-soraka: PASS
   

   -> INCOMPLETE
   



Regards,

Ankit


On 12/22/2022 10:21 PM, Patchwork wrote:

Project List - Patchwork *Patch Details*
*Series:*   drm/i915/dsb: Remove check for dsb in dsb_commit
*URL:*  https://patchwork.freedesktop.org/series/112159/
*State:*failure
*Details:* 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112159v1/index.html



  CI Bug Log - changes from CI_DRM_12522 -> Patchwork_112159v1


Summary

*FAILURE*

Serious unknown changes coming with Patchwork_112159v1 absolutely need 
to be

verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_112159v1, please notify your bug team to allow 
them
to document this new failure mode, which will reduce false positives 
in CI.


External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112159v1/index.html



Participating hosts (44 -> 45)

Additional (3): bat-adlm-1 bat-atsm-1 fi-tgl-dsi
Missing (2): fi-hsw-4770 fi-pnv-d510


Possible new issues

Here are the unknown changes that may have been introduced in 
Patchwork_112159v1:



  IGT changes


Possible regressions

 *

igt@i915_selftest@live@execlists:

  o fi-bsw-n3050: PASS


-> INCOMPLETE


 *

igt@i915_selftest@live@guc_multi_lrc:

  o fi-kbl-soraka: PASS


-> INCOMPLETE




Known issues

Here are the changes found in Patchwork_112159v1 that come from known 
issues:



  IGT changes


Issues hit

 *

igt@gem_exec_suspend@basic-s3@smem:

  o fi-rkl-11600: NOTRUN -> FAIL


(fdo#103375 )
 *

igt@kms_chamelium@common-hpd-after-suspend:

  o fi-rkl-11600: NOTRUN -> SKIP


(fdo#111827 )
 *

igt@runner@aborted:

  o fi-bsw-n3050: NOTRUN -> FAIL


(fdo#109271
 /
i915#4312 )


Possible fixes

 *

igt@i915_selftest@live@execlists:

  o fi-apl-guc: FAIL


-> PASS


+11 similar issues
 *

igt@i915_selftest@live@gt_heartbeat:

  o fi-apl-guc: DMESG-FAIL


(i915#5334
) ->
PASS


 *

igt@i915_suspend@basic-s3-without-i915:

  o fi-rkl-11600: INCOMPLETE


(i915#4817
) ->
PASS




Warnings

  * igt@kms_chamelium@common-hpd-after-suspend:
  o fi-apl

Re: [Intel-gfx] [PATCH v2] arch: rename all internal names __xchg to __arch_xchg

[Geert Uytterhoeven]

On Thu, Dec 29, 2022 at 12:34 PM Andrzej Hajda  wrote:
> __xchg will be used for non-atomic xchg macro.
>
> Signed-off-by: Andrzej Hajda 
> Reviewed-by: Arnd Bergmann 

Acked-by: Geert Uytterhoeven  [m68k]

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [Intel-gfx] [RFC PATCH 00/20] Initial Xe driver submission

[Thomas Zimmermann]

Hi

Am 22.12.22 um 23:21 schrieb Matthew Brost:

Hello,

This is a submission for Xe, a new driver for Intel GPUs that supports both
integrated and discrete platforms starting with Tiger Lake (first platform with
Intel Xe Architecture). The intention of this new driver is to have a fresh base
to work from that is unencumbered by older platforms, whilst also taking the
opportunity to rearchitect our driver to increase sharing across the drm
subsystem, both leveraging and allowing us to contribute more towards other
shared components like TTM and drm/scheduler. The memory model is based on VM
bind which is similar to the i915 implementation. Likewise the execbuf
implementation for Xe is very similar to execbuf3 in the i915 [1].


After Xe has stabilized, will i915 loose the ability to drive this 
hardware (and possibly other)?  I'm specfically thinking of the i915 
code that requires TTM. Keeping that dependecy within Xe only might 
benefit DRM as a whole.




The code is at a stage where it is already functional and has experimental
support for multiple platforms starting from Tiger Lake, with initial support
implemented in Mesa (for Iris and Anv, our OpenGL and Vulkan drivers), as well
as in NEO (for OpenCL and Level0). A Mesa MR has been posted [2] and NEO
implementation will be released publicly early next year. We also have a suite
of IGTs for XE that will appear on the IGT list shortly.

It has been built with the assumption of supporting multiple architectures from
the get-go, right now with tests running both on X86 and ARM hosts. And we
intend to continue working on it and improving on it as part of the kernel
community upstream.

The new Xe driver leverages a lot from i915 and work on i915 continues as we
ready Xe for production throughout 2023.

As for display, the intent is to share the display code with the i915 driver so
that there is maximum reuse there. Currently this is being done by compiling the
display code twice, but alternatives to that are under consideration and we want
to have more discussion on what the best final solution will look like over the
next few months. Right now, work is ongoing in refactoring the display codebase
to remove as much as possible any unnecessary dependencies on i915 specific data
structures there..


Could both drivers reside in a common parent directory and share 
something like a DRM Intel helper module with the common code? This 
would fit well with the common design of DRM helpers.


Best regards
Thomas



We currently have 2 submission backends, execlists and GuC. The execlist is
meant mostly for testing and is not fully functional while GuC backend is fully
functional. As with the i915 and GuC submission, in Xe the GuC firmware is
required and should be placed in /lib/firmware/xe.

The GuC firmware can be found in the below location:
https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git/tree/i915

The easiest way to setup firmware is:
cp -r /lib/firmware/i915 /lib/firmware/xe

The code has been organized such that we have all patches that touch areas
outside of drm/xe first for review, and then the actual new driver in a separate
commit. The code which is outside of drm/xe is included in this RFC while
drm/xe is not due to the size of the commit. The drm/xe is code is available in
a public repo listed below.

Xe driver commit:
https://cgit.freedesktop.org/drm/drm-xe/commit/?h=drm-xe-next&id=9cb016ebbb6a275f57b1cb512b95d5a842391ad7

Xe kernel repo:
https://cgit.freedesktop.org/drm/drm-xe/

There's a lot of work still to happen on Xe but we're very excited about it and
wanted to share it early and welcome feedback and discussion.

Cheers,
Matthew Brost

[1] https://patchwork.freedesktop.org/series/105879/
[2] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20418

Maarten Lankhorst (12):
   drm/amd: Convert amdgpu to use suballocation helper.
   drm/radeon: Use the drm suballocation manager implementation.
   drm/i915: Remove gem and overlay frontbuffer tracking
   drm/i915/display: Neuter frontbuffer tracking harder
   drm/i915/display: Add more macros to remove all direct calls to uncore
   drm/i915/display: Remove all uncore mmio accesses in favor of intel_de
   drm/i915: Rename find_section to find_bdb_section
   drm/i915/regs: Set DISPLAY_MMIO_BASE to 0 for xe
   drm/i915/display: Fix a use-after-free when intel_edp_init_connector
 fails
   drm/i915/display: Remaining changes to make xe compile
   sound/hda: Allow XE as i915 replacement for sound
   mei/hdcp: Also enable for XE

Matthew Brost (5):
   drm/sched: Convert drm scheduler to use a work queue rather than
 kthread
   drm/sched: Add generic scheduler message interface
   drm/sched: Start run wq before TDR in drm_sched_start
   drm/sched: Submit job before starting TDR
   drm/sched: Add helper to set TDR timeout

Thomas Hellström (3):
   drm/suballoc: Introduce a generic suballocation manager
   drm: Add a gpu page-table walker helper
   drm/ttm: Don't