Re: [Intel-gfx] [PATCH v8 7/8] drm/i915/vdsc: Fill the intel_dsc_get_pps_config function
On 8/17/2023 2:05 PM, Suraj Kandpal wrote:
We have setup both the read and write functions so we can
move ahead and fill in all the readout state from PPS register
into the crtc_state so we can send it for comparision.
--v2
-Shorten comment to just PPSX rather than having the whole
"Readout PPSX register" [Jani]
-Remove pps_temp reinitialization as its being initialized in
the read function [Jani]
-Use REG_FIELD_GET to readout certain fields of dsc registers
[Jani]
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 99 +--
.../gpu/drm/i915/display/intel_vdsc_regs.h| 3 +
2 files changed, 95 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
b/drivers/gpu/drm/i915/display/intel_vdsc.c
index e6c2d3ae60aa..5381976153f8 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -852,20 +852,105 @@ static void intel_dsc_read_and_verify_pps_reg(struct
intel_crtc_state *crtc_stat
static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state)
{
struct drm_dsc_config *vdsc_cfg = _state->dsc.config;
- u32 pps_temp1, pps_temp2;
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ u32 pps_temp;
- /* FIXME: add more state readout as needed */
+ /* PPS_0 */
+ intel_dsc_read_and_verify_pps_reg(crtc_state, 0, _temp);
- /* Readout PPS_0 and PPS_1 registers */
- intel_dsc_read_and_verify_pps_reg(crtc_state, 0, _temp1);
- intel_dsc_read_and_verify_pps_reg(crtc_state, 1, _temp2);
+ vdsc_cfg->bits_per_component = (pps_temp & DSC_BPC_MASK) >>
DSC_BPC_SHIFT;
+ vdsc_cfg->line_buf_depth =
+ (pps_temp & DSC_LINE_BUF_DEPTH_MASK) >>
DSC_LINE_BUF_DEPTH_SHIFT;
+ vdsc_cfg->block_pred_enable = pps_temp & DSC_BLOCK_PREDICTION;
+ vdsc_cfg->convert_rgb = pps_temp & DSC_COLOR_SPACE_CONVERSION;
+ vdsc_cfg->simple_422 = pps_temp & DSC_422_ENABLE;
+ vdsc_cfg->native_422 = pps_temp & DSC_NATIVE_422_ENABLE;
+ vdsc_cfg->native_420 = pps_temp & DSC_NATIVE_420_ENABLE;
+ vdsc_cfg->vbr_enable = pps_temp & DSC_VBR_ENABLE;
- vdsc_cfg->bits_per_pixel = pps_temp2;
+ /* PPS_1 */
+ intel_dsc_read_and_verify_pps_reg(crtc_state, 1, _temp);
- if (pps_temp1 & DSC_NATIVE_420_ENABLE)
+ vdsc_cfg->bits_per_pixel = pps_temp;
+
+ if (vdsc_cfg->native_420)
vdsc_cfg->bits_per_pixel >>= 1;
crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
+
+ /* PPS_2 */
+ intel_dsc_read_and_verify_pps_reg(crtc_state, 2, _temp);
+
+ vdsc_cfg->pic_width = REG_FIELD_GET(DSC_PIC_WIDTH_MASK, pps_temp);
+ vdsc_cfg->pic_height = REG_FIELD_GET(DSC_PIC_HEIGHT_MASK, pps_temp);
+
+ /* PPS_3 */
+ intel_dsc_read_and_verify_pps_reg(crtc_state, 3, _temp);
+
+ vdsc_cfg->slice_width = REG_FIELD_GET(DSC_SLICE_WIDTH_MASK, pps_temp);
+ vdsc_cfg->slice_height = REG_FIELD_GET(DSC_SLICE_HEIGHT_MASK, pps_temp);
+
+ /* PPS_4 */
+ intel_dsc_read_and_verify_pps_reg(crtc_state, 4, _temp);
+
+ vdsc_cfg->initial_dec_delay = REG_FIELD_GET(DSC_INITIAL_DEC_DELAY_MASK,
pps_temp);
+ vdsc_cfg->initial_xmit_delay =
REG_FIELD_GET(DSC_INITIAL_XMIT_DELAY_MASK, pps_temp);
+
+ /* PPS_5 */
+ intel_dsc_read_and_verify_pps_reg(crtc_state, 5, _temp);
+
+ vdsc_cfg->scale_decrement_interval =
REG_FIELD_GET(DSC_SCALE_DEC_INT_MASK, pps_temp);
+ vdsc_cfg->scale_increment_interval =
REG_FIELD_GET(DSC_SCALE_INC_INT_MASK, pps_temp);
+
+ /* PPS_6 */
+ intel_dsc_read_and_verify_pps_reg(crtc_state, 6, _temp);
+
+ vdsc_cfg->initial_scale_value =
REG_FIELD_GET(DSC_INITIAL_SCALE_VALUE_MASK, pps_temp);
+ vdsc_cfg->first_line_bpg_offset =
REG_FIELD_GET(DSC_FIRST_LINE_BPG_OFFSET_MASK, pps_temp);
+ vdsc_cfg->flatness_min_qp = REG_FIELD_GET(DSC_FLATNESS_MIN_QP_MASK,
pps_temp);
+ vdsc_cfg->flatness_max_qp = REG_FIELD_GET(DSC_FLATNESS_MAX_QP_MASK,
pps_temp);
+
+ /* PPS_7 */
+ intel_dsc_read_and_verify_pps_reg(crtc_state, 7, _temp);
+
+ vdsc_cfg->nfl_bpg_offset = REG_FIELD_GET(DSC_NFL_BPG_OFFSET_MASK,
pps_temp);
+ vdsc_cfg->slice_bpg_offset = REG_FIELD_GET(DSC_SLICE_BPG_OFFSET_MASK,
pps_temp);
+
+ /* PPS_8 */
+ intel_dsc_read_and_verify_pps_reg(crtc_state, 8, _temp);
+
+ vdsc_cfg->initial_offset = REG_FIELD_GET(DSC_INITIAL_OFFSET_MASK,
pps_temp);
+ vdsc_cfg->final_offset = REG_FIELD_GET(DSC_FINAL_OFFSET_MASK, pps_temp);
+
+ /* PPS_9 */
+ intel_dsc_read_and_verify_pps_reg(crtc_state, 9, _temp);
+
+ vdsc_cfg->rc_model_size = REG_FIELD_GET(DSC_RC_MODEL_SIZE_MASK,
pps_temp);
+
+ /* PPS_10 */
+ intel_dsc_read_and_verify_pps_reg(crtc_state, 10, _temp);
+
+ vdsc_cfg->rc_quant_incr_limit0 =
Re: [Intel-gfx] [PATCH v8 6/8] drm/i915/vdsc: Remove unused dsc registers
LGTM. Reviewed-by: Ankit Nautiyal On 8/17/2023 2:05 PM, Suraj Kandpal wrote: Now that we have macros that can fetch dsc register values based on pipe and pps parameters we can go ahead and remove all the unused register. Signed-off-by: Suraj Kandpal --- .../gpu/drm/i915/display/intel_vdsc_regs.h| 259 ++ 1 file changed, 24 insertions(+), 235 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h index 862dc708c5fc..7afc487223fb 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h +++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h @@ -46,38 +46,7 @@ _ICL_PIPE_DSS_CTL2_PB, \ _ICL_PIPE_DSS_CTL2_PC) -/* MTL Display Stream Compression registers */ -#define _MTL_DSC0_PICTURE_PARAMETER_SET_17_PB 0x782B4 -#define _MTL_DSC1_PICTURE_PARAMETER_SET_17_PB 0x783B4 -#define _MTL_DSC0_PICTURE_PARAMETER_SET_17_PC 0x784B4 -#define _MTL_DSC1_PICTURE_PARAMETER_SET_17_PC 0x785B4 -#define MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe)_MMIO_PIPE((pipe) - PIPE_B, \ - _MTL_DSC0_PICTURE_PARAMETER_SET_17_PB, \ - _MTL_DSC0_PICTURE_PARAMETER_SET_17_PC) -#define MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe)_MMIO_PIPE((pipe) - PIPE_B, \ - _MTL_DSC1_PICTURE_PARAMETER_SET_17_PB, \ - _MTL_DSC1_PICTURE_PARAMETER_SET_17_PC) -#define DSC_SL_BPG_OFFSET_MASK REG_GENMASK(31, 27) -#define DSC_SL_BPG_OFFSET(offset) REG_FIELD_PREP(DSC_SL_BPG_OFFSET_MASK, offset) - -#define _MTL_DSC0_PICTURE_PARAMETER_SET_18_PB 0x782B8 -#define _MTL_DSC1_PICTURE_PARAMETER_SET_18_PB 0x783B8 -#define _MTL_DSC0_PICTURE_PARAMETER_SET_18_PC 0x784B8 -#define _MTL_DSC1_PICTURE_PARAMETER_SET_18_PC 0x785B8 -#define MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe)_MMIO_PIPE((pipe) - PIPE_B, \ - _MTL_DSC0_PICTURE_PARAMETER_SET_18_PB, \ - _MTL_DSC0_PICTURE_PARAMETER_SET_18_PC) -#define MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe)_MMIO_PIPE((pipe) - PIPE_B, \ - _MTL_DSC1_PICTURE_PARAMETER_SET_18_PB, \ - _MTL_DSC1_PICTURE_PARAMETER_SET_18_PC) -#define DSC_NSL_BPG_OFFSET_MASKREG_GENMASK(31, 16) -#define DSC_SL_OFFSET_ADJ_MASK REG_GENMASK(15, 0) -#define DSC_NSL_BPG_OFFSET(offset) REG_FIELD_PREP(DSC_NSL_BPG_OFFSET_MASK, offset) -#define DSC_SL_OFFSET_ADJ(offset) REG_FIELD_PREP(DSC_SL_OFFSET_ADJ_MASK, offset) - /* Icelake Display Stream Compression Registers */ -#define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200) -#define DSCC_PICTURE_PARAMETER_SET_0 _MMIO(0x6BA00) #define DSCA_PPS_00x6B200 #define DSCC_PPS_00x6BA00 #define DSCA_PPS_REG(pps) _MMIO(DSCA_PPS_0 + (pps) * 4) @@ -86,12 +55,6 @@ #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB 0x78370 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC 0x78470 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC 0x78570 -#define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ - _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \ - _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC) -#define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ - _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \ - _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC) #define ICL_DSC0_PPS_0(pipe) _PICK_EVEN((pipe) - PIPE_B, \ _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \ _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC) @@ -100,6 +63,8 @@ _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC) #define ICL_DSC0_PPS_REG(pipe, pps) _MMIO(ICL_DSC0_PPS_0(pipe) + ((pps) * 4)) #define ICL_DSC1_PPS_REG(pipe, pps) _MMIO(ICL_DSC1_PPS_0(pipe) + ((pps) * 4)) + +/* PPS0 */ #define DSC_NATIVE_422_ENABLEBIT(23) #define DSC_NATIVE_420_ENABLEBIT(22) #define DSC_ALT_ICH_SEL (1 << 20) @@ -112,66 +77,22 @@ #define DSC_VER_MIN_SHIFT4 #define DSC_VER_MAJ (0x1 << 0) -#define DSCA_PICTURE_PARAMETER_SET_1
Re: [Intel-gfx] [PATCH v8 5/8] drm/i915/vdsc: Add function to write in PPS register
On 8/17/2023 2:05 PM, Suraj Kandpal wrote:
Now that we have a function that reads any PPS register based
on intel_dsc_pps enum provided lets create a function that can
write on any PPS.
--v2
-Changes need as PPS enum was dropped
-Remove duplicated code in intel_dsc_write_pps_reg [Jani]
--v3
-Use dsc_split instead of num_vdsc_instances [Ankit]
--v5
-Changes to implement the new dsc_reg array variable passing
[Ankit]
--v7
-Pass no of vdsc instances to get_pps_reg [Ankit]
--v8
-No need for dsc_reg dynamic allocation [Jani]
-Change function to void as no return needs to be sent back
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 272 +++---
1 file changed, 30 insertions(+), 242 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 27ae70b5849f..e6c2d3ae60aa 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -393,6 +393,22 @@ static void intel_dsc_get_pps_reg(const struct
intel_crtc_state *crtc_state, int
}
}
+static void intel_dsc_write_pps_reg(const struct intel_crtc_state *crtc_state,
+ int pps, u32 pps_val)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ i915_reg_t dsc_reg[2];
+ int i, vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
+
+ drm_WARN_ON_ONCE(>drm, ARRAY_SIZE(dsc_reg) < vdsc_per_pipe);
+
+ intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, vdsc_per_pipe);
Send ARRAY_SIZE(dsc_reg) here instead of vdsc_per_pipe, as mentioned in
the previous patch.
With that fixed, this is:
Reviewed-by: Ankit Nautiyal
+
+ for (i = 0; i < min_t(int, ARRAY_SIZE(dsc_reg), vdsc_per_pipe); i++)
+ intel_de_write(i915, dsc_reg[i], pps_val);
+}
+
static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -428,149 +444,41 @@ static void intel_dsc_pps_configure(const struct
intel_crtc_state *crtc_state)
if (vdsc_cfg->vbr_enable)
pps_val |= DSC_VBR_ENABLE;
drm_dbg_kms(_priv->drm, "PPS0 = 0x%08x\n", pps_val);
- if (!is_pipe_dsc(crtc, cpu_transcoder)) {
- intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_0,
- pps_val);
- /*
-* If 2 VDSC instances are needed, configure PPS for second
-* VDSC
-*/
- if (vdsc_instances_per_pipe > 1)
- intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_0,
- pps_val);
- } else {
- intel_de_write(dev_priv,
- ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe),
- pps_val);
- if (vdsc_instances_per_pipe > 1)
- intel_de_write(dev_priv,
- ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe),
- pps_val);
- }
+ intel_dsc_write_pps_reg(crtc_state, 0, pps_val);
/* Populate PICTURE_PARAMETER_SET_1 registers */
pps_val = 0;
pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel);
drm_dbg_kms(_priv->drm, "PPS1 = 0x%08x\n", pps_val);
- if (!is_pipe_dsc(crtc, cpu_transcoder)) {
- intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_1,
- pps_val);
- /*
-* If 2 VDSC instances are needed, configure PPS for second
-* VDSC
-*/
- if (vdsc_instances_per_pipe > 1)
- intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_1,
- pps_val);
- } else {
- intel_de_write(dev_priv,
- ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe),
- pps_val);
- if (vdsc_instances_per_pipe > 1)
- intel_de_write(dev_priv,
- ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe),
- pps_val);
- }
+ intel_dsc_write_pps_reg(crtc_state, 1, pps_val);
/* Populate PICTURE_PARAMETER_SET_2 registers */
pps_val = 0;
pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) |
DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances);
drm_dbg_kms(_priv->drm, "PPS2 = 0x%08x\n", pps_val);
- if (!is_pipe_dsc(crtc, cpu_transcoder)) {
- intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_2,
- pps_val);
- /*
-* If 2 VDSC instances are needed, configure PPS for second
-* VDSC
-*/
-
Re: [Intel-gfx] [PATCH v8 4/8] drm/i915/vdsc: Add function to read any PPS register
On 8/17/2023 2:05 PM, Suraj Kandpal wrote:
Add function to read any PPS register based on the
intel_dsc_pps enum provided. Add a function which will call the
new pps read function and place it in crtc state. Only PPS0 and
PPS1 are readout the rest of the registers will be read in upcoming
patches.
--v2
-Changes in read function as PPS enum is removed
-Initialize pps_val as 0 in pps_read func itself [Jani]
-Create a function that gets the required register and call that
in the common read function [Jani]
-Move the drm_WARN_ON one abstraction layer above [Jani]
--v3
-Send both reg values regardless of dsc engine no [Jani]
-Don't use num_vdsc_instances stick to dsc_split field [Ankit]
--v4
-Manipulate the reg values instead of creating MACRO to change
name of pps [Ankit]
--v5
-Read dsc reg values using array rather than individual variables
[Ankit]
-Loop the verification of all dsc engine reads to future proof it
[Ankit]
-Keep the fix me comment in this patch and remove it in later one
where we add other readouts [Ankit]
-Add switch statement that fills in the required registers based on
no of vdsc engines per pipe.
--v7
-Pass no of vdsc instances from read_reg function [Ankit]
-Fix issue where arrays do not get freed on return for read_and_verify
func [Ankit]
--v8
-Simplify reading and verifying of register and remove dynamically
allocated arrays [Jani]
-Remove no_ from no_vdsc_per_pipe and wherever else it applies [Ankit]
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 118 --
.../gpu/drm/i915/display/intel_vdsc_regs.h| 12 ++
2 files changed, 94 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
b/drivers/gpu/drm/i915/display/intel_vdsc.c
index fbe8ce9fe1ab..27ae70b5849f 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -371,6 +371,28 @@ int intel_dsc_get_num_vdsc_instances(const struct
intel_crtc_state *crtc_state)
return num_vdsc_instances;
}
+static void intel_dsc_get_pps_reg(const struct intel_crtc_state *crtc_state, int pps,
+ i915_reg_t *dsc_reg, int vdsc_per_pipe)
We are sending dsc_reg_size here.
So just fill the dsc_reg with the offsets, irrespective of the no. of
vdsc per pipe.
later we are reading or writing only those which are required based on
vdsc per pipe.
This function will always fills the array with offsets as per dsc_reg size.
In read function, while calling this function, the argument sent is
dsc_reg which is correct.
In write function in the next patch, the argument sent is vdsc_per_pipe,
instead of dsc_reg.
Regards,
Ankit
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ enum pipe pipe = crtc->pipe;
+ bool pipe_dsc;
+
+ pipe_dsc = is_pipe_dsc(crtc, cpu_transcoder);
+
+ switch (vdsc_per_pipe) {
+ case 2:
+ dsc_reg[1] = pipe_dsc ? ICL_DSC1_PPS_REG(pipe, pps) :
DSCC_PPS_REG(pps);
+ fallthrough;
+ case 1:
+ dsc_reg[0] = pipe_dsc ? ICL_DSC0_PPS_REG(pipe, pps) :
DSCA_PPS_REG(pps);
+ break;
+ default:
+ MISSING_CASE(vdsc_per_pipe);
+ }
+}
+
static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -1000,17 +1022,72 @@ void intel_dsc_disable(const struct intel_crtc_state
*old_crtc_state)
}
}
+static bool intel_dsc_read_pps_reg(struct intel_crtc_state *crtc_state,
+ int pps, u32 *pps_val)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ const int vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
+ i915_reg_t dsc_reg[2];
+ int i;
+
+ *pps_val = 0;
+ drm_WARN_ON_ONCE(>drm, ARRAY_SIZE(dsc_reg) < vdsc_per_pipe);
+
+ intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, ARRAY_SIZE(dsc_reg));
+
+ for (i = 0; i < min_t(int, ARRAY_SIZE(dsc_reg), vdsc_per_pipe); i++) {
+ u32 pps_temp;
+
+ pps_temp = intel_de_read(i915, dsc_reg[i]);
+
+ if (i == 0)
+ *pps_val = intel_de_read(i915, dsc_reg[i]);
+ else if (pps_temp != *pps_val)
+ return false;
+ }
+
+ return true;
+}
+
+static void intel_dsc_read_and_verify_pps_reg(struct intel_crtc_state
*crtc_state,
+ int pps, u32 *pps_val)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ int ret;
+
+ ret = intel_dsc_read_pps_reg(crtc_state, pps, pps_val);
+ drm_WARN_ON(>drm, !ret);
+}
Re: [Intel-gfx] [PATCH 4/4] drm/i915/hdcp: Adjust timeout for read in DPMST Scenario
> -Original Message-
> From: Kandpal, Suraj
> Sent: Thursday, August 10, 2023 1:18 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nautiyal, Ankit K ; uma.sha...@intel.com;
> Murthy, Arun R ; Kandpal, Suraj
>
> Subject: [PATCH 4/4] drm/i915/hdcp: Adjust timeout for read in DPMST
> Scenario
>
> Ignore the timeout for dpmst hdcp scenario.
Justification?
Thanks and Regards,
Arun R Murthy
>
> Signed-off-by: Suraj Kandpal
> ---
> drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> index 2a37a43243a3..e8cdc5721966 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> @@ -571,7 +571,7 @@ int intel_dp_hdcp2_read_msg(struct intel_connector
> *connector,
> offset += ret;
> }
>
> - if (hdcp2_msg_data->msg_read_timeout > 0) {
> + if (hdcp2_msg_data->msg_read_timeout > 0 && !aux->is_remote) {
> msg_expired = ktime_after(ktime_get_raw(), msg_end);
> if (msg_expired) {
> drm_dbg_kms(>drm, "msg_id %d, entire msg
> read timeout(mSec): %d\n",
> --
> 2.25.1
Re: [Intel-gfx] [PATCH 3/4] drm/i915/hdcp: Send the correct aux for DPMST HDCP scenario
> -Original Message- > From: Kandpal, Suraj > Sent: Thursday, August 10, 2023 1:18 PM > To: intel-gfx@lists.freedesktop.org > Cc: Nautiyal, Ankit K ; uma.sha...@intel.com; > Murthy, Arun R ; Kandpal, Suraj > > Subject: [PATCH 3/4] drm/i915/hdcp: Send the correct aux for DPMST HDCP > scenario > > Up until now we were sending the base aux stored in dig_port which is not > correct as this causes an issue when monitor is connected via a DPMST hub > causing it to be remote hence we end up seeing AUX failures so let's send the > remote aux in case of DPMST. > > Signed-off-by: Suraj Kandpal Reviewed-by: Arun R Murthy Thanks and Regards, Arun R Murthy > --- > drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 10 -- > 1 file changed, 8 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c > b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c > index 5304aa73b23f..2a37a43243a3 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c > @@ -452,7 +452,10 @@ int intel_dp_hdcp2_write_msg(struct > intel_connector *connector, > > offset = hdcp2_msg_data->offset; > > - aux = _port->dp.aux; > + if (intel_encoder_is_mst(connector->encoder)) > + aux = >port->aux; > + else > + aux = _port->dp.aux; > > /* No msg_id in DP HDCP2.2 msgs */ > bytes_to_write = size - 1; > @@ -518,7 +521,10 @@ int intel_dp_hdcp2_read_msg(struct > intel_connector *connector, > return -EINVAL; > offset = hdcp2_msg_data->offset; > > - aux = >aux; > + if (intel_encoder_is_mst(connector->encoder)) > + aux = >port->aux; > + else > + aux = >aux; > > ret = intel_dp_hdcp2_wait_for_msg(i915, aux, hdcp, > hdcp2_msg_data); > if (ret < 0) > -- > 2.25.1
Re: [Intel-gfx] [PATCH 2/4] drm/i915/hdcp: Propagate aux info in DP HDCP functions
> -Original Message-
> From: Kandpal, Suraj
> Sent: Thursday, August 10, 2023 1:18 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nautiyal, Ankit K ; uma.sha...@intel.com;
> Murthy, Arun R ; Kandpal, Suraj
>
> Subject: [PATCH 2/4] drm/i915/hdcp: Propagate aux info in DP HDCP
> functions
>
> We were propagating dig_port info to dp hdcp2 specific functions.
> Let us clean that up and send drm_dp_aux instead n functions:
Typo.
Its not a good convention to pass the drm_dp core struct in i915 functions.
We have been using i915 wrapper functions for this. Feel its better to
continue the same convention. On the other hand, intel_dp can help in
getting the drm_dp_aux.
> intel_dp_hdcp2_wait_for_msg, get_receiver_id_list_rx_info,
> intel_dp_hdcp2_read_rx_status this optimises mst scenarios where aux ends
> up being remote and not stored in dig_port.
Can this sentence be broken?
Thanks and Regards,
Arun R Murthy
>
> Signed-off-by: Suraj Kandpal
> ---
> drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 43
> 1 file changed, 25 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> index 6cd42363837a..5304aa73b23f 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> @@ -331,13 +331,13 @@ static const struct hdcp2_dp_msg_data
> hdcp2_dp_msg_data[] = { };
>
> static int
> -intel_dp_hdcp2_read_rx_status(struct intel_digital_port *dig_port,
> +intel_dp_hdcp2_read_rx_status(struct drm_i915_private *i915,
> + struct drm_dp_aux *aux,
> u8 *rx_status)
> {
> - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> ssize_t ret;
>
> - ret = drm_dp_dpcd_read(_port->dp.aux,
> + ret = drm_dp_dpcd_read(aux,
> DP_HDCP_2_2_REG_RXSTATUS_OFFSET,
> rx_status,
> HDCP_2_2_DP_RXSTATUS_LEN);
> if (ret != HDCP_2_2_DP_RXSTATUS_LEN) { @@ -350,14 +350,15 @@
> intel_dp_hdcp2_read_rx_status(struct intel_digital_port *dig_port, }
>
> static
> -int hdcp2_detect_msg_availability(struct intel_digital_port *dig_port,
> +int hdcp2_detect_msg_availability(struct drm_i915_private *i915,
> + struct drm_dp_aux *aux,
> u8 msg_id, bool *msg_ready)
> {
> u8 rx_status;
> int ret;
>
> *msg_ready = false;
> - ret = intel_dp_hdcp2_read_rx_status(dig_port, _status);
> + ret = intel_dp_hdcp2_read_rx_status(i915, aux, _status);
> if (ret < 0)
> return ret;
>
> @@ -383,12 +384,10 @@ int hdcp2_detect_msg_availability(struct
> intel_digital_port *dig_port, }
>
> static ssize_t
> -intel_dp_hdcp2_wait_for_msg(struct intel_digital_port *dig_port,
> +intel_dp_hdcp2_wait_for_msg(struct drm_i915_private *i915, struct
> drm_dp_aux *aux,
> + struct intel_hdcp *hdcp,
> const struct hdcp2_dp_msg_data
> *hdcp2_msg_data) {
> - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> - struct intel_dp *dp = _port->dp;
> - struct intel_hdcp *hdcp = >attached_connector->hdcp;
> u8 msg_id = hdcp2_msg_data->msg_id;
> int ret, timeout;
> bool msg_ready = false;
> @@ -411,7 +410,7 @@ intel_dp_hdcp2_wait_for_msg(struct
> intel_digital_port *dig_port,
>* the timeout at wait for CP_IRQ.
>*/
> intel_dp_hdcp_wait_for_cp_irq(hdcp, timeout);
> - ret = hdcp2_detect_msg_availability(dig_port,
> + ret = hdcp2_detect_msg_availability(i915, aux,
> msg_id, _ready);
> if (!msg_ready)
> ret = -ETIMEDOUT;
> @@ -445,6 +444,7 @@ int intel_dp_hdcp2_write_msg(struct intel_connector
> *connector,
> u8 *byte = buf;
> ssize_t ret, bytes_to_write, len;
> const struct hdcp2_dp_msg_data *hdcp2_msg_data;
> + struct drm_dp_aux *aux;
>
> hdcp2_msg_data = get_hdcp2_dp_msg_data(*byte);
> if (!hdcp2_msg_data)
> @@ -452,6 +452,8 @@ int intel_dp_hdcp2_write_msg(struct intel_connector
> *connector,
>
> offset = hdcp2_msg_data->offset;
>
> + aux = _port->dp.aux;
> +
> /* No msg_id in DP HDCP2.2 msgs */
> bytes_to_write = size - 1;
> byte++;
> @@ -460,7 +462,7 @@ int intel_dp_hdcp2_write_msg(struct intel_connector
> *connector,
> len = bytes_to_write > DP_AUX_MAX_PAYLOAD_BYTES ?
> DP_AUX_MAX_PAYLOAD_BYTES :
> bytes_to_write;
>
> - ret = drm_dp_dpcd_write(_port->dp.aux,
> + ret = drm_dp_dpcd_write(aux,
> offset, (void *)byte, len);
> if (ret < 0)
> return ret;
> @@ -474,12 +476,12 @@ int
[Intel-gfx] ✗ Fi.CI.BUILD: failure for HDCP MST aux issue fix (rev2)
== Series Details == Series: HDCP MST aux issue fix (rev2) URL : https://patchwork.freedesktop.org/series/122267/ State : failure == Summary == Error: patch https://patchwork.freedesktop.org/api/1.0/series/122267/revisions/2/mbox/ not applied Applying: drm/i915/hdcp: Use intel_connector argument in intel_hdcp_shim error: patch failed: drivers/gpu/drm/i915/display/intel_display_types.h:504 error: drivers/gpu/drm/i915/display/intel_display_types.h: patch does not apply error: patch failed: drivers/gpu/drm/i915/display/intel_dp_hdcp.c:437 error: drivers/gpu/drm/i915/display/intel_dp_hdcp.c: patch does not apply error: patch failed: drivers/gpu/drm/i915/display/intel_hdcp.c:1415 error: drivers/gpu/drm/i915/display/intel_hdcp.c: patch does not apply error: patch failed: drivers/gpu/drm/i915/display/intel_hdmi.c:1665 error: drivers/gpu/drm/i915/display/intel_hdmi.c: patch does not apply error: Did you hand edit your patch? It does not apply to blobs recorded in its index. hint: Use 'git am --show-current-patch=diff' to see the failed patch Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/display/intel_hdmi.c Patch failed at 0001 drm/i915/hdcp: Use intel_connector argument in intel_hdcp_shim When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". Build failed, no error log produced
Re: [Intel-gfx] [PATCH 1/4] drm/i915/hdcp: Use intel_connector argument in intel_hdcp_shim
Reviewed-by: Arun R Murthy
Thanks and Regards,
Arun R Murthy
From: Kandpal, Suraj
Sent: Thursday, August 10, 2023 1:17 PM
To: intel-gfx@lists.freedesktop.org
Cc: Nautiyal, Ankit K ; uma.sha...@intel.com
; Murthy, Arun R ; Kandpal,
Suraj
Subject: [PATCH 1/4] drm/i915/hdcp: Use intel_connector argument in
intel_hdcp_shim
Update intel_hdcp_shim funcs specifically read_2_2_message,
write_2_2_message and config_stream_type to use intel_connector
argument instead of intel_digital_port as this will help in getting
correct aux later for dp mst scenarios also already hdcp funcs
derive digital_port from connector and then many funcs again get back
the connector from dig_port which doesn't seem right.
Connector specific hdcp functions can derive dig_port on need basis.
Signed-off-by: Suraj Kandpal
---
.../drm/i915/display/intel_display_types.h| 6 ++--
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 10 ---
drivers/gpu/drm/i915/display/intel_hdcp.c | 30 ---
drivers/gpu/drm/i915/display/intel_hdmi.c | 6 ++--
4 files changed, 26 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 731f2ec04d5c..c62f4ec315e8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -504,11 +504,11 @@ struct intel_hdcp_shim {
bool *capable);
/* Write HDCP2.2 messages */
- int (*write_2_2_msg)(struct intel_digital_port *dig_port,
+ int (*write_2_2_msg)(struct intel_connector *connector,
void *buf, size_t size);
/* Read HDCP2.2 messages */
- int (*read_2_2_msg)(struct intel_digital_port *dig_port,
+ int (*read_2_2_msg)(struct intel_connector *connector,
u8 msg_id, void *buf, size_t size);
/*
@@ -516,7 +516,7 @@ struct intel_hdcp_shim {
* type to Receivers. In DP HDCP2.2 Stream type is one of the input to
* the HDCP2.2 Cipher for En/De-Cryption. Not applicable for HDMI.
*/
- int (*config_stream_type)(struct intel_digital_port *dig_port,
+ int (*config_stream_type)(struct intel_connector *connector,
bool is_repeater, u8 type);
/* Enable/Disable HDCP 2.2 stream encryption on DP MST Transport Link
*/
diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index e0c177161407..6cd42363837a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -437,9 +437,10 @@ static const struct hdcp2_dp_msg_data
*get_hdcp2_dp_msg_data(u8 msg_id)
}
static
-int intel_dp_hdcp2_write_msg(struct intel_digital_port *dig_port,
+int intel_dp_hdcp2_write_msg(struct intel_connector *connector,
void *buf, size_t size)
{
+ struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
unsigned int offset;
u8 *byte = buf;
ssize_t ret, bytes_to_write, len;
@@ -494,9 +495,10 @@ ssize_t get_receiver_id_list_rx_info(struct
intel_digital_port *dig_port, u32 *d
}
static
-int intel_dp_hdcp2_read_msg(struct intel_digital_port *dig_port,
+int intel_dp_hdcp2_read_msg(struct intel_connector *connector,
u8 msg_id, void *buf, size_t size)
{
+ struct intel_digital_port *dig_port =
intel_attached_dig_port(connector);
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
struct intel_dp *dp = _port->dp;
struct intel_hdcp *hdcp = >attached_connector->hdcp;
@@ -574,7 +576,7 @@ int intel_dp_hdcp2_read_msg(struct intel_digital_port
*dig_port,
}
static
-int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *dig_port,
+int intel_dp_hdcp2_config_stream_type(struct intel_connector *connector,
bool is_repeater, u8 content_type)
{
int ret;
@@ -593,7 +595,7 @@ int intel_dp_hdcp2_config_stream_type(struct
intel_digital_port *dig_port,
stream_type_msg.msg_id = HDCP_2_2_ERRATA_DP_STREAM_TYPE;
stream_type_msg.stream_type = content_type;
- ret = intel_dp_hdcp2_write_msg(dig_port, _type_msg,
+ ret = intel_dp_hdcp2_write_msg(connector, _type_msg,
sizeof(stream_type_msg));
return ret < 0 ? ret : 0;
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index a42549fa9691..cb45f21f71eb 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -1415,7 +1415,6 @@ static int hdcp2_deauthenticate_port(struct
intel_connector *connector)
/* Authentication flow starts from here */
static int
[Intel-gfx] ✓ Fi.CI.IGT: success for Reduce MTL-specific platform checks (rev5)
== Series Details == Series: Reduce MTL-specific platform checks (rev5) URL : https://patchwork.freedesktop.org/series/120943/ State : success == Summary == CI Bug Log - changes from CI_DRM_13541_full -> Patchwork_120943v5_full Summary --- **SUCCESS** No regressions found. Participating hosts (9 -> 9) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_120943v5_full that come from known issues: ### IGT changes ### Issues hit * igt@api_intel_bb@object-reloc-keep-cache: - shard-dg2: NOTRUN -> [SKIP][1] ([i915#8411]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v5/shard-dg2-10/igt@api_intel...@object-reloc-keep-cache.html * igt@drm_buddy@drm_buddy_test: - shard-snb: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#8661]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v5/shard-snb6/igt@drm_buddy@drm_buddy_test.html * igt@gem_ccs@block-multicopy-compressed: - shard-mtlp: NOTRUN -> [SKIP][3] ([i915#5325]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v5/shard-mtlp-4/igt@gem_...@block-multicopy-compressed.html * igt@gem_ctx_exec@basic-nohangcheck: - shard-rkl: [PASS][4] -> [FAIL][5] ([i915#6268]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/shard-rkl-7/igt@gem_ctx_e...@basic-nohangcheck.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v5/shard-rkl-4/igt@gem_ctx_e...@basic-nohangcheck.html * igt@gem_ctx_persistence@heartbeat-stop: - shard-dg2: NOTRUN -> [SKIP][6] ([i915#8555]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v5/shard-dg2-12/igt@gem_ctx_persiste...@heartbeat-stop.html * igt@gem_ctx_persistence@hostile: - shard-snb: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#1099]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v5/shard-snb6/igt@gem_ctx_persiste...@hostile.html * igt@gem_exec_balancer@bonded-dual: - shard-dg2: NOTRUN -> [SKIP][8] ([i915#4771]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v5/shard-dg2-10/igt@gem_exec_balan...@bonded-dual.html * igt@gem_exec_capture@capture-invisible@lmem0: - shard-dg2: NOTRUN -> [SKIP][9] ([i915#6334]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v5/shard-dg2-10/igt@gem_exec_capture@capture-invisi...@lmem0.html * igt@gem_exec_fair@basic-none-share: - shard-dg2: NOTRUN -> [SKIP][10] ([i915#3539] / [i915#4852]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v5/shard-dg2-10/igt@gem_exec_f...@basic-none-share.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: [PASS][11] -> [FAIL][12] ([i915#2876]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/shard-glk6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v5/shard-glk4/igt@gem_exec_fair@basic-pace-sh...@rcs0.html - shard-rkl: [PASS][13] -> [FAIL][14] ([i915#2842]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/shard-rkl-2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v5/shard-rkl-2/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_reloc@basic-wc-gtt: - shard-mtlp: NOTRUN -> [SKIP][15] ([i915#3281]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v5/shard-mtlp-4/igt@gem_exec_re...@basic-wc-gtt.html * igt@gem_exec_reloc@basic-wc-read: - shard-dg2: NOTRUN -> [SKIP][16] ([i915#3281]) +2 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v5/shard-dg2-10/igt@gem_exec_re...@basic-wc-read.html * igt@gem_lmem_swapping@heavy-multi: - shard-apl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v5/shard-apl6/igt@gem_lmem_swapp...@heavy-multi.html * igt@gem_mmap_gtt@cpuset-big-copy: - shard-dg2: NOTRUN -> [SKIP][18] ([i915#4077]) +2 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v5/shard-dg2-10/igt@gem_mmap_...@cpuset-big-copy.html * igt@gem_mmap_gtt@fault-concurrent-x: - shard-snb: [PASS][19] -> [ABORT][20] ([i915#5161]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/shard-snb6/igt@gem_mmap_...@fault-concurrent-x.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v5/shard-snb5/igt@gem_mmap_...@fault-concurrent-x.html * igt@gem_mmap_wc@read-write-distinct: - shard-dg2: NOTRUN -> [SKIP][21] ([i915#4083]) [21]:
[Intel-gfx] ✓ Fi.CI.IGT: success for Get optimal audio frequency and channels (rev10)
== Series Details == Series: Get optimal audio frequency and channels (rev10) URL : https://patchwork.freedesktop.org/series/119121/ State : success == Summary == CI Bug Log - changes from CI_DRM_13541_full -> Patchwork_119121v10_full Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119121v10/index.html Participating hosts (9 -> 9) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_119121v10_full that come from known issues: ### IGT changes ### Issues hit * igt@api_intel_bb@object-reloc-keep-cache: - shard-dg2: NOTRUN -> [SKIP][1] ([i915#8411]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119121v10/shard-dg2-12/igt@api_intel...@object-reloc-keep-cache.html * igt@drm_buddy@drm_buddy_test: - shard-snb: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#8661]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119121v10/shard-snb4/igt@drm_buddy@drm_buddy_test.html * igt@drm_fdinfo@virtual-busy-idle: - shard-dg2: NOTRUN -> [SKIP][3] ([i915#8414]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119121v10/shard-dg2-3/igt@drm_fdi...@virtual-busy-idle.html * igt@gem_ccs@block-multicopy-compressed: - shard-mtlp: NOTRUN -> [SKIP][4] ([i915#5325]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119121v10/shard-mtlp-6/igt@gem_...@block-multicopy-compressed.html * igt@gem_ctx_persistence@heartbeat-stop: - shard-dg2: NOTRUN -> [SKIP][5] ([i915#8555]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119121v10/shard-dg2-11/igt@gem_ctx_persiste...@heartbeat-stop.html * igt@gem_ctx_persistence@hostile: - shard-snb: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#1099]) +1 similar issue [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119121v10/shard-snb4/igt@gem_ctx_persiste...@hostile.html * igt@gem_eio@banned: - shard-mtlp: [PASS][7] -> [FAIL][8] ([i915#8798]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/shard-mtlp-1/igt@gem_...@banned.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119121v10/shard-mtlp-3/igt@gem_...@banned.html * igt@gem_eio@hibernate: - shard-dg1: [PASS][9] -> [ABORT][10] ([i915#7975] / [i915#8213]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/shard-dg1-19/igt@gem_...@hibernate.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119121v10/shard-dg1-14/igt@gem_...@hibernate.html * igt@gem_eio@in-flight-contexts-10ms: - shard-mtlp: [PASS][11] -> [ABORT][12] ([i915#7941]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/shard-mtlp-4/igt@gem_...@in-flight-contexts-10ms.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119121v10/shard-mtlp-1/igt@gem_...@in-flight-contexts-10ms.html * igt@gem_eio@kms: - shard-glk: [PASS][13] -> [FAIL][14] ([i915#8764]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/shard-glk2/igt@gem_...@kms.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119121v10/shard-glk9/igt@gem_...@kms.html * igt@gem_exec_balancer@bonded-dual: - shard-dg2: NOTRUN -> [SKIP][15] ([i915#4771]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119121v10/shard-dg2-12/igt@gem_exec_balan...@bonded-dual.html * igt@gem_exec_capture@capture-invisible@lmem0: - shard-dg2: NOTRUN -> [SKIP][16] ([i915#6334]) +1 similar issue [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119121v10/shard-dg2-12/igt@gem_exec_capture@capture-invisi...@lmem0.html * igt@gem_exec_capture@pi@bcs0: - shard-mtlp: [PASS][17] -> [FAIL][18] ([i915#4475] / [i915#7765]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/shard-mtlp-2/igt@gem_exec_capture@p...@bcs0.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119121v10/shard-mtlp-7/igt@gem_exec_capture@p...@bcs0.html * igt@gem_exec_fair@basic-flow@rcs0: - shard-tglu: [PASS][19] -> [FAIL][20] ([i915#2842]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/shard-tglu-5/igt@gem_exec_fair@basic-f...@rcs0.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119121v10/shard-tglu-7/igt@gem_exec_fair@basic-f...@rcs0.html * igt@gem_exec_fair@basic-none-share: - shard-dg2: NOTRUN -> [SKIP][21] ([i915#3539] / [i915#4852]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119121v10/shard-dg2-12/igt@gem_exec_f...@basic-none-share.html * igt@gem_exec_fair@basic-none@bcs0: - shard-rkl: [PASS][22] -> [FAIL][23] ([i915#2842]) +1 similar issue [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/shard-rkl-1/igt@gem_exec_fair@basic-n...@bcs0.html
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: mark requests for GuC virtual engines to avoid use-after-free
== Series Details == Series: drm/i915: mark requests for GuC virtual engines to avoid use-after-free URL : https://patchwork.freedesktop.org/series/122709/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13541_full -> Patchwork_122709v1_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_122709v1_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_122709v1_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (9 -> 9) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_122709v1_full: ### CI changes ### Possible regressions * boot: - shard-snb: ([PASS][1], [PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25]) -> ([PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [FAIL][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/shard-snb7/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/shard-snb7/boot.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/shard-snb7/boot.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/shard-snb6/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/shard-snb6/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/shard-snb6/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/shard-snb6/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/shard-snb6/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/shard-snb5/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/shard-snb5/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/shard-snb5/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/shard-snb5/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/shard-snb4/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/shard-snb4/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/shard-snb4/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/shard-snb4/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/shard-snb2/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/shard-snb2/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/shard-snb2/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/shard-snb2/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/shard-snb2/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/shard-snb1/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/shard-snb1/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/shard-snb1/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/shard-snb1/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122709v1/shard-snb1/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122709v1/shard-snb1/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122709v1/shard-snb1/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122709v1/shard-snb1/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122709v1/shard-snb2/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122709v1/shard-snb2/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122709v1/shard-snb2/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122709v1/shard-snb2/boot.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122709v1/shard-snb4/boot.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122709v1/shard-snb4/boot.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122709v1/shard-snb4/boot.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122709v1/shard-snb4/boot.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122709v1/shard-snb5/boot.html [39]:
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/rpl: Update pci ids for RPL P/U
== Series Details == Series: drm/i915/rpl: Update pci ids for RPL P/U URL : https://patchwork.freedesktop.org/series/122712/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13541 -> Patchwork_122712v1 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_122712v1 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_122712v1, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122712v1/index.html Participating hosts (39 -> 39) -- Additional (2): fi-kbl-soraka bat-mtlp-6 Missing(2): fi-tgl-1115g4 fi-snb-2520m Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_122712v1: ### IGT changes ### Possible regressions * igt@gem_exec_suspend@basic-s0@smem: - bat-dg2-9: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/bat-dg2-9/igt@gem_exec_suspend@basic...@smem.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122712v1/bat-dg2-9/igt@gem_exec_suspend@basic...@smem.html * igt@gem_linear_blits@basic: - bat-rplp-1: [PASS][3] -> [SKIP][4] +34 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/bat-rplp-1/igt@gem_linear_bl...@basic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122712v1/bat-rplp-1/igt@gem_linear_bl...@basic.html * igt@i915_pm_rpm@basic-rte: - bat-rplp-1: NOTRUN -> [SKIP][5] +36 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122712v1/bat-rplp-1/igt@i915_pm_...@basic-rte.html * igt@i915_selftest@live@sanitycheck: - bat-rplp-1: NOTRUN -> [FAIL][6] +20 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122712v1/bat-rplp-1/igt@i915_selftest@l...@sanitycheck.html * igt@i915_suspend@basic-s2idle-without-i915: - bat-rplp-1: NOTRUN -> [WARN][7] +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122712v1/bat-rplp-1/igt@i915_susp...@basic-s2idle-without-i915.html Warnings * igt@debugfs_test@basic-hwmon: - bat-rplp-1: [SKIP][8] ([i915#7456]) -> [SKIP][9] [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/bat-rplp-1/igt@debugfs_t...@basic-hwmon.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122712v1/bat-rplp-1/igt@debugfs_t...@basic-hwmon.html * igt@gem_tiled_pread_basic: - bat-rplp-1: [SKIP][10] ([i915#3282]) -> [SKIP][11] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/bat-rplp-1/igt@gem_tiled_pread_basic.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122712v1/bat-rplp-1/igt@gem_tiled_pread_basic.html * igt@kms_psr@cursor_plane_move: - bat-rplp-1: [ABORT][12] ([i915#8469] / [i915#8668]) -> [SKIP][13] [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/bat-rplp-1/igt@kms_psr@cursor_plane_move.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122712v1/bat-rplp-1/igt@kms_psr@cursor_plane_move.html * igt@kms_psr@primary_page_flip: - bat-rplp-1: [SKIP][14] ([i915#1072]) -> [SKIP][15] [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/bat-rplp-1/igt@kms_psr@primary_page_flip.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122712v1/bat-rplp-1/igt@kms_psr@primary_page_flip.html Known issues Here are the changes found in Patchwork_122712v1 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-mtlp-6: NOTRUN -> [SKIP][16] ([i915#7456]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122712v1/bat-mtlp-6/igt@debugfs_t...@basic-hwmon.html * igt@fbdev@info: - bat-mtlp-6: NOTRUN -> [SKIP][17] ([i915#1849] / [i915#2582]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122712v1/bat-mtlp-6/igt@fb...@info.html * igt@fbdev@write: - bat-mtlp-6: NOTRUN -> [SKIP][18] ([i915#2582]) +3 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122712v1/bat-mtlp-6/igt@fb...@write.html * igt@gem_huc_copy@huc-copy: - fi-kbl-soraka: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#2190]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122712v1/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-kbl-soraka: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#4613]) +3 similar issues [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122712v1/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html * igt@gem_lmem_swapping@verify-random: -
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/rpl: Update pci ids for RPL P/U
== Series Details == Series: drm/i915/rpl: Update pci ids for RPL P/U URL : https://patchwork.freedesktop.org/series/122712/ State : warning == Summary == Error: dim sparse failed /home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No such file or directory
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/rpl: Update pci ids for RPL P/U
== Series Details == Series: drm/i915/rpl: Update pci ids for RPL P/U URL : https://patchwork.freedesktop.org/series/122712/ State : warning == Summary == Error: dim checkpatch failed /home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No such file or directory
[Intel-gfx] ✓ Fi.CI.IGT: success for Revert "drm/edid: Fix csync detailed mode parsing" (rev2)
== Series Details == Series: Revert "drm/edid: Fix csync detailed mode parsing" (rev2) URL : https://patchwork.freedesktop.org/series/122455/ State : success == Summary == CI Bug Log - changes from CI_DRM_13541_full -> Patchwork_122455v2_full Summary --- **SUCCESS** No regressions found. Participating hosts (9 -> 9) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_122455v2_full that come from known issues: ### IGT changes ### Issues hit * igt@drm_buddy@drm_buddy_test: - shard-snb: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#8661]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122455v2/shard-snb6/igt@drm_buddy@drm_buddy_test.html * igt@gem_barrier_race@remote-request@rcs0: - shard-tglu: [PASS][2] -> [ABORT][3] ([i915#8190]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/shard-tglu-10/igt@gem_barrier_race@remote-requ...@rcs0.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122455v2/shard-tglu-10/igt@gem_barrier_race@remote-requ...@rcs0.html * igt@gem_ccs@block-multicopy-compressed: - shard-mtlp: NOTRUN -> [SKIP][4] ([i915#5325]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122455v2/shard-mtlp-3/igt@gem_...@block-multicopy-compressed.html * igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-lmem0-lmem0: - shard-dg2: [PASS][5] -> [INCOMPLETE][6] ([i915#7297]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/shard-dg2-11/igt@gem_ccs@suspend-res...@linear-compressed-compfmt0-lmem0-lmem0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122455v2/shard-dg2-2/igt@gem_ccs@suspend-res...@linear-compressed-compfmt0-lmem0-lmem0.html * igt@gem_ctx_exec@basic-nohangcheck: - shard-rkl: [PASS][7] -> [FAIL][8] ([i915#6268]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/shard-rkl-7/igt@gem_ctx_e...@basic-nohangcheck.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122455v2/shard-rkl-4/igt@gem_ctx_e...@basic-nohangcheck.html * igt@gem_ctx_persistence@heartbeat-stop: - shard-dg2: NOTRUN -> [SKIP][9] ([i915#8555]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122455v2/shard-dg2-11/igt@gem_ctx_persiste...@heartbeat-stop.html * igt@gem_ctx_persistence@hostile: - shard-snb: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#1099]) +1 similar issue [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122455v2/shard-snb6/igt@gem_ctx_persiste...@hostile.html * igt@gem_eio@banned: - shard-mtlp: [PASS][11] -> [FAIL][12] ([i915#8798]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/shard-mtlp-1/igt@gem_...@banned.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122455v2/shard-mtlp-6/igt@gem_...@banned.html * igt@gem_exec_capture@capture@vcs1-smem: - shard-mtlp: [PASS][13] -> [DMESG-WARN][14] ([i915#5591]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/shard-mtlp-8/igt@gem_exec_capture@capt...@vcs1-smem.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122455v2/shard-mtlp-5/igt@gem_exec_capture@capt...@vcs1-smem.html * igt@gem_exec_capture@pi@vecs0: - shard-mtlp: [PASS][15] -> [FAIL][16] ([i915#4475] / [i915#7765]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/shard-mtlp-2/igt@gem_exec_capture@p...@vecs0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122455v2/shard-mtlp-2/igt@gem_exec_capture@p...@vecs0.html * igt@gem_exec_endless@dispatch@bcs0: - shard-mtlp: [PASS][17] -> [TIMEOUT][18] ([i915#3778] / [i915#7016]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/shard-mtlp-5/igt@gem_exec_endless@dispa...@bcs0.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122455v2/shard-mtlp-1/igt@gem_exec_endless@dispa...@bcs0.html * igt@gem_exec_fair@basic-none@bcs0: - shard-rkl: [PASS][19] -> [FAIL][20] ([i915#2842]) +1 similar issue [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/shard-rkl-1/igt@gem_exec_fair@basic-n...@bcs0.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122455v2/shard-rkl-2/igt@gem_exec_fair@basic-n...@bcs0.html * igt@gem_exec_reloc@basic-wc-gtt: - shard-mtlp: NOTRUN -> [SKIP][21] ([i915#3281]) +1 similar issue [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122455v2/shard-mtlp-3/igt@gem_exec_re...@basic-wc-gtt.html * igt@gem_exec_schedule@noreorder@rcs0: - shard-mtlp: [PASS][22] -> [DMESG-FAIL][23] ([i915#9121]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/shard-mtlp-4/igt@gem_exec_schedule@noreor...@rcs0.html [23]:
[Intel-gfx] ✓ Fi.CI.BAT: success for Reduce MTL-specific platform checks (rev5)
== Series Details == Series: Reduce MTL-specific platform checks (rev5) URL : https://patchwork.freedesktop.org/series/120943/ State : success == Summary == CI Bug Log - changes from CI_DRM_13541 -> Patchwork_120943v5 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v5/index.html Participating hosts (39 -> 40) -- Additional (2): fi-kbl-soraka bat-mtlp-6 Missing(1): fi-snb-2520m Known issues Here are the changes found in Patchwork_120943v5 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-mtlp-6: NOTRUN -> [SKIP][1] ([i915#7456]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v5/bat-mtlp-6/igt@debugfs_t...@basic-hwmon.html * igt@fbdev@info: - bat-mtlp-6: NOTRUN -> [SKIP][2] ([i915#1849] / [i915#2582]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v5/bat-mtlp-6/igt@fb...@info.html * igt@fbdev@write: - bat-mtlp-6: NOTRUN -> [SKIP][3] ([i915#2582]) +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v5/bat-mtlp-6/igt@fb...@write.html * igt@gem_exec_suspend@basic-s3@smem: - bat-rpls-2: [PASS][4] -> [ABORT][5] ([i915#6687] / [i915#7978] / [i915#8668]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/bat-rpls-2/igt@gem_exec_suspend@basic...@smem.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v5/bat-rpls-2/igt@gem_exec_suspend@basic...@smem.html * igt@gem_huc_copy@huc-copy: - fi-kbl-soraka: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#2190]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v5/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-kbl-soraka: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#4613]) +3 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v5/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html * igt@gem_lmem_swapping@verify-random: - bat-mtlp-6: NOTRUN -> [SKIP][8] ([i915#4613]) +3 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v5/bat-mtlp-6/igt@gem_lmem_swapp...@verify-random.html * igt@gem_mmap@basic: - bat-mtlp-6: NOTRUN -> [SKIP][9] ([i915#4083]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v5/bat-mtlp-6/igt@gem_m...@basic.html * igt@gem_tiled_blits@basic: - bat-mtlp-6: NOTRUN -> [SKIP][10] ([i915#4077]) +2 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v5/bat-mtlp-6/igt@gem_tiled_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-mtlp-6: NOTRUN -> [SKIP][11] ([i915#4079]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v5/bat-mtlp-6/igt@gem_tiled_pread_basic.html * igt@i915_pm_backlight@basic-brightness: - bat-mtlp-6: NOTRUN -> [SKIP][12] ([i915#3546]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v5/bat-mtlp-6/igt@i915_pm_backli...@basic-brightness.html * igt@i915_pm_rps@basic-api: - bat-mtlp-6: NOTRUN -> [SKIP][13] ([i915#6621]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v5/bat-mtlp-6/igt@i915_pm_...@basic-api.html * igt@i915_selftest@live@gt_heartbeat: - fi-apl-guc: [PASS][14] -> [DMESG-FAIL][15] ([i915#5334]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v5/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@gt_pm: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][16] ([i915#1886] / [i915#7913]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v5/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html * igt@i915_selftest@live@migrate: - bat-adlp-9: [PASS][17] -> [DMESG-FAIL][18] ([i915#7699] / [i915#7913]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/bat-adlp-9/igt@i915_selftest@l...@migrate.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v5/bat-adlp-9/igt@i915_selftest@l...@migrate.html * igt@i915_suspend@basic-s3-without-i915: - bat-mtlp-6: NOTRUN -> [SKIP][19] ([i915#6645]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v5/bat-mtlp-6/igt@i915_susp...@basic-s3-without-i915.html * igt@kms_addfb_basic@addfb25-x-tiled-legacy: - bat-mtlp-6: NOTRUN -> [SKIP][20] ([i915#4212]) +8 similar issues [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v5/bat-mtlp-6/igt@kms_addfb_ba...@addfb25-x-tiled-legacy.html * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: - bat-mtlp-6: NOTRUN -> [SKIP][21]
Re: [Intel-gfx] [PATCH v1] drivers: gpu: drm: i915: intel_huc: fix formatting warnings
On Mon, 21 Aug 2023, Nikita B wrote:
> Fix formatting warnings when run "make htmldocs":
> ./drivers/gpu/drm/i915/gt/uc/intel_huc.c:29: WARNING: Unexpected indentation.
> ./drivers/gpu/drm/i915/gt/uc/intel_huc.c:30: WARNING: Block quote ends
> without a blank line; unexpected unindent.
> ./drivers/gpu/drm/i915/gt/uc/intel_huc.c:35: WARNING: Bullet list ends
> without a blank line; unexpected unindent.
>
> Signed-off-by: Nikita B
Already fixed by commit 175b036472f6 ("drm/i915: fix Sphinx indentation
warning") in drm-next.
BR,
Jani.
> ---
> drivers/gpu/drm/i915/gt/uc/intel_huc.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> index ddd146265beb..fa70defcb5b2 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> @@ -26,6 +26,7 @@
> * The kernel driver is only responsible for loading the HuC firmware and
> * triggering its security authentication. This is done differently depending
> * on the platform:
> + *
> * - older platforms (from Gen9 to most Gen12s): the load is performed via
> DMA
> * and the authentication via GuC
> * - DG2: load and authentication are both performed via GSC.
> @@ -33,6 +34,7 @@
> * not-DG2 older platforms), while the authentication is done in 2-steps,
> * a first auth for clear-media workloads via GuC and a second one for all
> * workloads via GSC.
> + *
> * On platforms where the GuC does the authentication, to correctly do so the
> * HuC binary must be loaded before the GuC one.
> * Loading the HuC is optional; however, not using the HuC might negatively
--
Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] [PATCH v4 i-g-t] tests/i915_pm_freq_api: Ignore zero register value
Register read for requested_freq can return 0 when system is
in runtime_pm. Make allowance for this case.
v2: Explicit check for runtime_pm status (Riana)
v3: Revert back to v1, the runtime util functions do not work
as expected.
v4: Add a debug print for min/max freq before test begins
Link: https://gitlab.freedesktop.org/drm/intel/issues/8736
Link: https://gitlab.freedesktop.org/drm/intel/issues/8989
Reviewed-by: Riana Tauro
Signed-off-by: Vinay Belgaumkar
---
tests/i915/i915_pm_freq_api.c | 19 +++
1 file changed, 15 insertions(+), 4 deletions(-)
diff --git a/tests/i915/i915_pm_freq_api.c b/tests/i915/i915_pm_freq_api.c
index cf21cc936..2912287c4 100644
--- a/tests/i915/i915_pm_freq_api.c
+++ b/tests/i915/i915_pm_freq_api.c
@@ -88,6 +88,7 @@ static void test_freq_basic_api(int dirfd, int gt)
static void test_reset(int i915, int dirfd, int gt, int count)
{
uint32_t rpn = get_freq(dirfd, RPS_RPn_FREQ_MHZ);
+ uint32_t req_freq;
int fd;
for (int i = 0; i < count; i++) {
@@ -95,14 +96,18 @@ static void test_reset(int i915, int dirfd, int gt, int
count)
igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn) > 0);
igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpn) > 0);
usleep(ACT_FREQ_LATENCY_US);
- igt_assert_eq(get_freq(dirfd, RPS_CUR_FREQ_MHZ), rpn);
+ req_freq = get_freq(dirfd, RPS_CUR_FREQ_MHZ);
+ if (req_freq)
+ igt_assert_eq(req_freq, rpn);
/* Manually trigger a GT reset */
fd = igt_debugfs_gt_open(i915, gt, "reset", O_WRONLY);
igt_require(fd >= 0);
igt_ignore_warn(write(fd, "1\n", 2));
- igt_assert_eq(get_freq(dirfd, RPS_CUR_FREQ_MHZ), rpn);
+ req_freq = get_freq(dirfd, RPS_CUR_FREQ_MHZ);
+ if (req_freq)
+ igt_assert_eq(req_freq, rpn);
}
close(fd);
}
@@ -110,17 +115,22 @@ static void test_reset(int i915, int dirfd, int gt, int
count)
static void test_suspend(int i915, int dirfd, int gt)
{
uint32_t rpn = get_freq(dirfd, RPS_RPn_FREQ_MHZ);
+ uint32_t req_freq;
igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn) > 0);
igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpn) > 0);
usleep(ACT_FREQ_LATENCY_US);
- igt_assert_eq(get_freq(dirfd, RPS_CUR_FREQ_MHZ), rpn);
+ req_freq = get_freq(dirfd, RPS_CUR_FREQ_MHZ);
+ if (req_freq)
+ igt_assert_eq(req_freq, rpn);
/* Manually trigger a suspend */
igt_system_suspend_autoresume(SUSPEND_STATE_S3,
SUSPEND_TEST_NONE);
- igt_assert_eq(get_freq(dirfd, RPS_CUR_FREQ_MHZ), rpn);
+ req_freq = get_freq(dirfd, RPS_CUR_FREQ_MHZ);
+ if (req_freq)
+ igt_assert_eq(req_freq, rpn);
}
int i915 = -1;
@@ -160,6 +170,7 @@ igt_main
for_each_sysfs_gt_dirfd(i915, dirfd, gt) {
stash_min[gt] = get_freq(dirfd, RPS_MIN_FREQ_MHZ);
stash_max[gt] = get_freq(dirfd, RPS_MAX_FREQ_MHZ);
+ igt_debug("GT: %d, min: %d, max: %d", gt,
stash_min[gt], stash_max[gt]);
igt_pm_ignore_slpc_efficient_freq(i915, dirfd, true);
}
igt_install_exit_handler(restore_sysfs_freq);
--
2.38.1
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Reduce MTL-specific platform checks (rev5)
== Series Details == Series: Reduce MTL-specific platform checks (rev5) URL : https://patchwork.freedesktop.org/series/120943/ State : warning == Summary == Error: dim sparse failed /home/kbuild/linux/maintainer-tools/dim: line 50: /home/kbuild/.dimrc: No such file or directory
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Reduce MTL-specific platform checks (rev5)
== Series Details == Series: Reduce MTL-specific platform checks (rev5) URL : https://patchwork.freedesktop.org/series/120943/ State : warning == Summary == Error: dim checkpatch failed /home/kbuild/linux/maintainer-tools/dim: line 50: /home/kbuild/.dimrc: No such file or directory
[Intel-gfx] ✓ Fi.CI.BAT: success for Get optimal audio frequency and channels (rev10)
== Series Details == Series: Get optimal audio frequency and channels (rev10) URL : https://patchwork.freedesktop.org/series/119121/ State : success == Summary == CI Bug Log - changes from CI_DRM_13541 -> Patchwork_119121v10 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119121v10/index.html Participating hosts (39 -> 38) -- Additional (1): bat-mtlp-6 Missing(2): bat-dg2-9 fi-snb-2520m Known issues Here are the changes found in Patchwork_119121v10 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-mtlp-6: NOTRUN -> [SKIP][1] ([i915#7456]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119121v10/bat-mtlp-6/igt@debugfs_t...@basic-hwmon.html * igt@fbdev@info: - bat-mtlp-6: NOTRUN -> [SKIP][2] ([i915#1849] / [i915#2582]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119121v10/bat-mtlp-6/igt@fb...@info.html * igt@fbdev@write: - bat-mtlp-6: NOTRUN -> [SKIP][3] ([i915#2582]) +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119121v10/bat-mtlp-6/igt@fb...@write.html * igt@gem_lmem_swapping@verify-random: - bat-mtlp-6: NOTRUN -> [SKIP][4] ([i915#4613]) +3 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119121v10/bat-mtlp-6/igt@gem_lmem_swapp...@verify-random.html * igt@gem_mmap@basic: - bat-mtlp-6: NOTRUN -> [SKIP][5] ([i915#4083]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119121v10/bat-mtlp-6/igt@gem_m...@basic.html * igt@gem_tiled_blits@basic: - bat-mtlp-6: NOTRUN -> [SKIP][6] ([i915#4077]) +2 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119121v10/bat-mtlp-6/igt@gem_tiled_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-mtlp-6: NOTRUN -> [SKIP][7] ([i915#4079]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119121v10/bat-mtlp-6/igt@gem_tiled_pread_basic.html * igt@i915_pm_backlight@basic-brightness: - bat-mtlp-6: NOTRUN -> [SKIP][8] ([i915#3546]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119121v10/bat-mtlp-6/igt@i915_pm_backli...@basic-brightness.html * igt@i915_pm_rps@basic-api: - bat-mtlp-6: NOTRUN -> [SKIP][9] ([i915#6621]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119121v10/bat-mtlp-6/igt@i915_pm_...@basic-api.html * igt@i915_selftest@live@mman: - bat-rpls-2: [PASS][10] -> [TIMEOUT][11] ([i915#6794] / [i915#7392]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/bat-rpls-2/igt@i915_selftest@l...@mman.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119121v10/bat-rpls-2/igt@i915_selftest@l...@mman.html * igt@i915_selftest@live@workarounds: - bat-dg1-5: [PASS][12] -> [ABORT][13] ([i915#4983]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/bat-dg1-5/igt@i915_selftest@l...@workarounds.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119121v10/bat-dg1-5/igt@i915_selftest@l...@workarounds.html * igt@i915_suspend@basic-s2idle-without-i915: - bat-rpls-2: [PASS][14] -> [WARN][15] ([i915#8747]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/bat-rpls-2/igt@i915_susp...@basic-s2idle-without-i915.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119121v10/bat-rpls-2/igt@i915_susp...@basic-s2idle-without-i915.html * igt@i915_suspend@basic-s3-without-i915: - bat-mtlp-6: NOTRUN -> [SKIP][16] ([i915#6645]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119121v10/bat-mtlp-6/igt@i915_susp...@basic-s3-without-i915.html * igt@kms_addfb_basic@addfb25-x-tiled-legacy: - bat-mtlp-6: NOTRUN -> [SKIP][17] ([i915#4212]) +8 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119121v10/bat-mtlp-6/igt@kms_addfb_ba...@addfb25-x-tiled-legacy.html * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: - bat-mtlp-6: NOTRUN -> [SKIP][18] ([i915#5190]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119121v10/bat-mtlp-6/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html * igt@kms_cursor_legacy@basic-flip-after-cursor-legacy: - bat-mtlp-6: NOTRUN -> [SKIP][19] ([i915#1845]) +11 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119121v10/bat-mtlp-6/igt@kms_cursor_leg...@basic-flip-after-cursor-legacy.html * igt@kms_flip@basic-flip-vs-dpms: - bat-mtlp-6: NOTRUN -> [SKIP][20] ([i915#3637]) +3 similar issues [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119121v10/bat-mtlp-6/igt@kms_f...@basic-flip-vs-dpms.html * igt@kms_force_connector_basic@force-load-detect:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Get optimal audio frequency and channels (rev10)
== Series Details == Series: Get optimal audio frequency and channels (rev10) URL : https://patchwork.freedesktop.org/series/119121/ State : warning == Summary == Error: dim sparse failed /home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No such file or directory
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Get optimal audio frequency and channels (rev10)
== Series Details == Series: Get optimal audio frequency and channels (rev10) URL : https://patchwork.freedesktop.org/series/119121/ State : warning == Summary == Error: dim checkpatch failed /home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No such file or directory
Re: [Intel-gfx] [CI] drm/i915/gt: Refactor hangcheck selftest to use igt_spinner
-Original Message-
From: Andi Shyti
Sent: Saturday, August 19, 2023 3:50 PM
To: Cavitt, Jonathan
Cc: intel-gfx
Subject: [CI] drm/i915/gt: Refactor hangcheck selftest to use igt_spinner
>
> From: Jonathan Cavitt
>
> The hangcheck live selftest contains duplicate declarations of some
> functions that already exist in igt_spinner.c, such as the creation and
> deconstruction of a spinning batch buffer (spinner) that hangs an engine.
> It's undesireable to have such code duplicated, as the requirements for
> the spinner may change with hardware updates, necessitating both
> execution paths be updated. To avoid this, have the hangcheck live
> selftest use the declaration from igt_spinner. This eliminates the need
> for the declarations in the selftest itself, as well as the associated
> local helper structures, so we can erase those.
>
> Suggested-by: Matt Roper
> Signed-off-by: Jonathan Cavitt
Test fails with -62 (ETIME) on intel_selftest_wait_for_rq
It looks like the cause might be me calling intel_context_put too early?
Let me move those calls to later and see if that helps.
Give me some time to implement those changes.
-Jonathan Cavitt
> ---
> drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 457 ++-
> drivers/gpu/drm/i915/selftests/igt_spinner.c | 15 +-
> drivers/gpu/drm/i915/selftests/igt_spinner.h | 9 +
> 3 files changed, 155 insertions(+), 326 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
> b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
> index 0dd4d00ee894e..36376a4ade8e4 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
> @@ -29,281 +29,40 @@
>
> #define IGT_IDLE_TIMEOUT 50 /* ms; time to wait after flushing between tests
> */
>
> -struct hang {
> - struct intel_gt *gt;
> - struct drm_i915_gem_object *hws;
> - struct drm_i915_gem_object *obj;
> - struct i915_gem_context *ctx;
> - u32 *seqno;
> - u32 *batch;
> -};
> -
> -static int hang_init(struct hang *h, struct intel_gt *gt)
> -{
> - void *vaddr;
> - int err;
> -
> - memset(h, 0, sizeof(*h));
> - h->gt = gt;
> -
> - h->ctx = kernel_context(gt->i915, NULL);
> - if (IS_ERR(h->ctx))
> - return PTR_ERR(h->ctx);
> -
> - GEM_BUG_ON(i915_gem_context_is_bannable(h->ctx));
> -
> - h->hws = i915_gem_object_create_internal(gt->i915, PAGE_SIZE);
> - if (IS_ERR(h->hws)) {
> - err = PTR_ERR(h->hws);
> - goto err_ctx;
> - }
> -
> - h->obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE);
> - if (IS_ERR(h->obj)) {
> - err = PTR_ERR(h->obj);
> - goto err_hws;
> - }
> -
> - i915_gem_object_set_cache_coherency(h->hws, I915_CACHE_LLC);
> - vaddr = i915_gem_object_pin_map_unlocked(h->hws, I915_MAP_WB);
> - if (IS_ERR(vaddr)) {
> - err = PTR_ERR(vaddr);
> - goto err_obj;
> - }
> - h->seqno = memset(vaddr, 0xff, PAGE_SIZE);
> -
> - vaddr = i915_gem_object_pin_map_unlocked(h->obj,
> - intel_gt_coherent_map_type(gt,
> h->obj, false));
> - if (IS_ERR(vaddr)) {
> - err = PTR_ERR(vaddr);
> - goto err_unpin_hws;
> - }
> - h->batch = vaddr;
> -
> - return 0;
> -
> -err_unpin_hws:
> - i915_gem_object_unpin_map(h->hws);
> -err_obj:
> - i915_gem_object_put(h->obj);
> -err_hws:
> - i915_gem_object_put(h->hws);
> -err_ctx:
> - kernel_context_close(h->ctx);
> - return err;
> -}
> -
> -static u64 hws_address(const struct i915_vma *hws,
> -const struct i915_request *rq)
> -{
> - return i915_vma_offset(hws) +
> -offset_in_page(sizeof(u32) * rq->fence.context);
> -}
> -
> -static struct i915_request *
> -hang_create_request(struct hang *h, struct intel_engine_cs *engine)
> -{
> - struct intel_gt *gt = h->gt;
> - struct i915_address_space *vm = i915_gem_context_get_eb_vm(h->ctx);
> - struct drm_i915_gem_object *obj;
> - struct i915_request *rq = NULL;
> - struct i915_vma *hws, *vma;
> - unsigned int flags;
> - void *vaddr;
> - u32 *batch;
> - int err;
> -
> - obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE);
> - if (IS_ERR(obj)) {
> - i915_vm_put(vm);
> - return ERR_CAST(obj);
> - }
> -
> - vaddr = i915_gem_object_pin_map_unlocked(obj,
> intel_gt_coherent_map_type(gt, obj, false));
> - if (IS_ERR(vaddr)) {
> - i915_gem_object_put(obj);
> - i915_vm_put(vm);
> - return ERR_CAST(vaddr);
> - }
> -
> - i915_gem_object_unpin_map(h->obj);
> - i915_gem_object_put(h->obj);
> -
> - h->obj = obj;
> - h->batch = vaddr;
> -
> - vma = i915_vma_instance(h->obj, vm, NULL);
> - if (IS_ERR(vma)) {
> - i915_vm_put(vm);
> - return ERR_CAST(vma);
> - }
> -
> -
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: mark requests for GuC virtual engines to avoid use-after-free
== Series Details == Series: drm/i915: mark requests for GuC virtual engines to avoid use-after-free URL : https://patchwork.freedesktop.org/series/122709/ State : success == Summary == CI Bug Log - changes from CI_DRM_13541 -> Patchwork_122709v1 Summary --- **WARNING** Minor unknown changes coming with Patchwork_122709v1 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_122709v1, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122709v1/index.html Participating hosts (39 -> 38) -- Additional (1): bat-mtlp-6 Missing(2): bat-dg2-9 fi-snb-2520m Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_122709v1: ### IGT changes ### Warnings * igt@i915_suspend@basic-s3-without-i915: - bat-adlm-1: [INCOMPLETE][1] ([i915#7443]) -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/bat-adlm-1/igt@i915_susp...@basic-s3-without-i915.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122709v1/bat-adlm-1/igt@i915_susp...@basic-s3-without-i915.html Known issues Here are the changes found in Patchwork_122709v1 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-mtlp-6: NOTRUN -> [SKIP][3] ([i915#7456]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122709v1/bat-mtlp-6/igt@debugfs_t...@basic-hwmon.html * igt@fbdev@info: - bat-mtlp-6: NOTRUN -> [SKIP][4] ([i915#1849] / [i915#2582]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122709v1/bat-mtlp-6/igt@fb...@info.html * igt@fbdev@write: - bat-mtlp-6: NOTRUN -> [SKIP][5] ([i915#2582]) +3 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122709v1/bat-mtlp-6/igt@fb...@write.html * igt@gem_lmem_swapping@verify-random: - bat-mtlp-6: NOTRUN -> [SKIP][6] ([i915#4613]) +3 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122709v1/bat-mtlp-6/igt@gem_lmem_swapp...@verify-random.html * igt@gem_mmap@basic: - bat-mtlp-6: NOTRUN -> [SKIP][7] ([i915#4083]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122709v1/bat-mtlp-6/igt@gem_m...@basic.html * igt@gem_tiled_blits@basic: - bat-mtlp-6: NOTRUN -> [SKIP][8] ([i915#4077]) +2 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122709v1/bat-mtlp-6/igt@gem_tiled_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-mtlp-6: NOTRUN -> [SKIP][9] ([i915#4079]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122709v1/bat-mtlp-6/igt@gem_tiled_pread_basic.html * igt@i915_pm_backlight@basic-brightness: - bat-mtlp-6: NOTRUN -> [SKIP][10] ([i915#3546]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122709v1/bat-mtlp-6/igt@i915_pm_backli...@basic-brightness.html * igt@i915_pm_rps@basic-api: - bat-mtlp-6: NOTRUN -> [SKIP][11] ([i915#6621]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122709v1/bat-mtlp-6/igt@i915_pm_...@basic-api.html * igt@i915_selftest@live@hangcheck: - fi-skl-guc: [PASS][12] -> [DMESG-FAIL][13] ([i915#8723]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/fi-skl-guc/igt@i915_selftest@l...@hangcheck.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122709v1/fi-skl-guc/igt@i915_selftest@l...@hangcheck.html * igt@i915_suspend@basic-s3-without-i915: - bat-mtlp-6: NOTRUN -> [SKIP][14] ([i915#6645]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122709v1/bat-mtlp-6/igt@i915_susp...@basic-s3-without-i915.html * igt@kms_addfb_basic@addfb25-x-tiled-legacy: - bat-mtlp-6: NOTRUN -> [SKIP][15] ([i915#4212]) +8 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122709v1/bat-mtlp-6/igt@kms_addfb_ba...@addfb25-x-tiled-legacy.html * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: - bat-mtlp-6: NOTRUN -> [SKIP][16] ([i915#5190]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122709v1/bat-mtlp-6/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html * igt@kms_cursor_legacy@basic-flip-after-cursor-legacy: - bat-mtlp-6: NOTRUN -> [SKIP][17] ([i915#1845]) +11 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122709v1/bat-mtlp-6/igt@kms_cursor_leg...@basic-flip-after-cursor-legacy.html * igt@kms_flip@basic-flip-vs-dpms: - bat-mtlp-6: NOTRUN -> [SKIP][18] ([i915#3637]) +3 similar issues [18]:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: mark requests for GuC virtual engines to avoid use-after-free
== Series Details == Series: drm/i915: mark requests for GuC virtual engines to avoid use-after-free URL : https://patchwork.freedesktop.org/series/122709/ State : warning == Summary == Error: dim sparse failed /home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No such file or directory
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: mark requests for GuC virtual engines to avoid use-after-free
== Series Details == Series: drm/i915: mark requests for GuC virtual engines to avoid use-after-free URL : https://patchwork.freedesktop.org/series/122709/ State : warning == Summary == Error: dim checkpatch failed /home/kbuild/linux/maintainer-tools/dim: line 50: /home/kbuild/.dimrc: No such file or directory
[Intel-gfx] [CI] PR for GSC FW release 102.0.0.1655 for MTL
The following changes since commit 0e048b061bde79ad735c7b7b5161ee1bd3400150: Merge branch 'for-upstream' of https://github.com/CirrusLogic/linux-firmware (2023-08-14 13:03:41 -0400) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-firmware mtl_gsc_1655 for you to fetch changes up to 81caac98eda1696fa057191ee969c377154a: i915: add GSC 102.0.0.1655 for MTL (2023-08-21 14:13:11 -0700) Daniele Ceraolo Spurio (1): i915: add GSC 102.0.0.1655 for MTL WHENCE | 3 +++ i915/mtl_gsc_1.bin | Bin 0 -> 1142784 bytes 2 files changed, 3 insertions(+) create mode 100755 i915/mtl_gsc_1.bin
Re: [Intel-gfx] [PATCH] drm/i915/rpl: Update pci ids for RPL P/U
On Tue, Aug 22, 2023 at 12:08:31AM +0530, Dnyaneshwar Bhadane wrote: > Update pci device ids as per bspec for RPL P/U. > Bpsec: 55376 > > Signed-off-by: Dnyaneshwar Bhadane > --- > include/drm/i915_pciids.h | 8 > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h > index e1e10dfbb661..8a697a9a84af 100644 > --- a/include/drm/i915_pciids.h > +++ b/include/drm/i915_pciids.h > @@ -688,15 +688,15 @@ > /* RPL-U */ > #define INTEL_RPLU_IDS(info) \ > INTEL_VGA_DEVICE(0xA721, info), \ > - INTEL_VGA_DEVICE(0xA7A1, info), \ > - INTEL_VGA_DEVICE(0xA7A9, info) I still see these two IDs listed on the bspec page, so I think we need to leave these be (there are presumably already devices using these which would break if we removed them). The comment in the "Notes" column is a somewhat confusing remark about future hardware, not an indication that we should remove these IDs. > + INTEL_VGA_DEVICE(0xA7AC, info), \ > + INTEL_VGA_DEVICE(0xA7AD, info) > > /* RPL-P */ > #define INTEL_RPLP_IDS(info) \ > INTEL_RPLU_IDS(info), \ > INTEL_VGA_DEVICE(0xA720, info), \ > - INTEL_VGA_DEVICE(0xA7A0, info), \ > - INTEL_VGA_DEVICE(0xA7A8, info) Same with these two. Matt > + INTEL_VGA_DEVICE(0xA7AA, info), \ > + INTEL_VGA_DEVICE(0xA7AB, info) > > /* DG2 */ > #define INTEL_DG2_G10_IDS(info) \ > -- > 2.34.1 > -- Matt Roper Graphics Software Engineer Linux GPU Platform Enablement Intel Corporation
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gt: Refactor hangcheck selftest to use igt_spinner (rev3)
== Series Details == Series: drm/i915/gt: Refactor hangcheck selftest to use igt_spinner (rev3) URL : https://patchwork.freedesktop.org/series/122658/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13541 -> Patchwork_122658v3 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_122658v3 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_122658v3, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122658v3/index.html Participating hosts (39 -> 40) -- Additional (2): bat-dg2-8 bat-mtlp-6 Missing(1): fi-snb-2520m Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_122658v3: ### IGT changes ### Possible regressions * igt@i915_selftest@live@hangcheck: - fi-cfl-guc: [PASS][1] -> [DMESG-FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/fi-cfl-guc/igt@i915_selftest@l...@hangcheck.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122658v3/fi-cfl-guc/igt@i915_selftest@l...@hangcheck.html - bat-jsl-3: [PASS][3] -> [ABORT][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/bat-jsl-3/igt@i915_selftest@l...@hangcheck.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122658v3/bat-jsl-3/igt@i915_selftest@l...@hangcheck.html - fi-kbl-x1275: [PASS][5] -> [DMESG-FAIL][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/fi-kbl-x1275/igt@i915_selftest@l...@hangcheck.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122658v3/fi-kbl-x1275/igt@i915_selftest@l...@hangcheck.html - fi-hsw-4770:[PASS][7] -> [ABORT][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122658v3/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html - fi-cfl-8109u: [PASS][9] -> [DMESG-FAIL][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/fi-cfl-8109u/igt@i915_selftest@l...@hangcheck.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122658v3/fi-cfl-8109u/igt@i915_selftest@l...@hangcheck.html - fi-kbl-8809g: [PASS][11] -> [DMESG-FAIL][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/fi-kbl-8809g/igt@i915_selftest@l...@hangcheck.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122658v3/fi-kbl-8809g/igt@i915_selftest@l...@hangcheck.html - bat-mtlp-8: [PASS][13] -> [ABORT][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/bat-mtlp-8/igt@i915_selftest@l...@hangcheck.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122658v3/bat-mtlp-8/igt@i915_selftest@l...@hangcheck.html - fi-kbl-guc: [PASS][15] -> [DMESG-FAIL][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/fi-kbl-guc/igt@i915_selftest@l...@hangcheck.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122658v3/fi-kbl-guc/igt@i915_selftest@l...@hangcheck.html - bat-jsl-1: [PASS][17] -> [ABORT][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/bat-jsl-1/igt@i915_selftest@l...@hangcheck.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122658v3/bat-jsl-1/igt@i915_selftest@l...@hangcheck.html - fi-tgl-1115g4: [PASS][19] -> [ABORT][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/fi-tgl-1115g4/igt@i915_selftest@l...@hangcheck.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122658v3/fi-tgl-1115g4/igt@i915_selftest@l...@hangcheck.html - bat-mtlp-6: NOTRUN -> [ABORT][21] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122658v3/bat-mtlp-6/igt@i915_selftest@l...@hangcheck.html - fi-skl-6600u: [PASS][22] -> [DMESG-FAIL][23] [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/fi-skl-6600u/igt@i915_selftest@l...@hangcheck.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122658v3/fi-skl-6600u/igt@i915_selftest@l...@hangcheck.html - fi-apl-guc: [PASS][24] -> [ABORT][25] [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/fi-apl-guc/igt@i915_selftest@l...@hangcheck.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122658v3/fi-apl-guc/igt@i915_selftest@l...@hangcheck.html - bat-dg1-5: [PASS][26] -> [ABORT][27] [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122658v3/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
Re: [Intel-gfx] [PATCH] gpu: drm: i915: fix documentation style
On 8/21/2023 9:22 AM, Jani Nikula wrote:
On Mon, 21 Aug 2023, "Ricardo B. Marliere" wrote:
This patch fixes the following sphinx warnings in the htmldocs make target:
Documentation/gpu/i915:546: ./drivers/gpu/drm/i915/gt/uc/intel_huc.c:29: ERROR:
Unexpected indentation.
Documentation/gpu/i915:546: ./drivers/gpu/drm/i915/gt/uc/intel_huc.c:30:
WARNING: Block quote ends without a blank line; unexpected unindent.
Documentation/gpu/i915:546: ./drivers/gpu/drm/i915/gt/uc/intel_huc.c:35:
WARNING: Bullet list ends without a blank line; unexpected unindent.
Signed-off-by: Ricardo B. Marliere
Already fixed by commit 175b036472f6 ("drm/i915: fix Sphinx indentation
warning") in drm-next.
Should we send this commit through the -fixes path, so it gets included
in 6.5?
Daniele
BR,
Jani.
---
drivers/gpu/drm/i915/gt/uc/intel_huc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index ddd146265beb..fa70defcb5b2 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -26,6 +26,7 @@
* The kernel driver is only responsible for loading the HuC firmware and
* triggering its security authentication. This is done differently depending
* on the platform:
+ *
* - older platforms (from Gen9 to most Gen12s): the load is performed via DMA
* and the authentication via GuC
* - DG2: load and authentication are both performed via GSC.
@@ -33,6 +34,7 @@
* not-DG2 older platforms), while the authentication is done in 2-steps,
* a first auth for clear-media workloads via GuC and a second one for all
* workloads via GSC.
+ *
* On platforms where the GuC does the authentication, to correctly do so the
* HuC binary must be loaded before the GuC one.
* Loading the HuC is optional; however, not using the HuC might negatively
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/gt: Refactor hangcheck selftest to use igt_spinner (rev3)
== Series Details == Series: drm/i915/gt: Refactor hangcheck selftest to use igt_spinner (rev3) URL : https://patchwork.freedesktop.org/series/122658/ State : warning == Summary == Error: dim sparse failed /home/kbuild/linux/maintainer-tools/dim: line 50: /home/kbuild/.dimrc: No such file or directory
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gt: Refactor hangcheck selftest to use igt_spinner (rev3)
== Series Details == Series: drm/i915/gt: Refactor hangcheck selftest to use igt_spinner (rev3) URL : https://patchwork.freedesktop.org/series/122658/ State : warning == Summary == Error: dim checkpatch failed /home/kbuild/linux/maintainer-tools/dim: line 50: /home/kbuild/.dimrc: No such file or directory
[Intel-gfx] ✓ Fi.CI.BAT: success for Revert "drm/edid: Fix csync detailed mode parsing" (rev2)
== Series Details == Series: Revert "drm/edid: Fix csync detailed mode parsing" (rev2) URL : https://patchwork.freedesktop.org/series/122455/ State : success == Summary == CI Bug Log - changes from CI_DRM_13541 -> Patchwork_122455v2 Summary --- **WARNING** Minor unknown changes coming with Patchwork_122455v2 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_122455v2, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122455v2/index.html Participating hosts (39 -> 39) -- Additional (2): fi-kbl-soraka bat-mtlp-6 Missing(2): fi-snb-2520m fi-pnv-d510 Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_122455v2: ### IGT changes ### Warnings * igt@i915_module_load@load: - bat-adlp-11:[DMESG-WARN][1] ([i915#4423]) -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13541/bat-adlp-11/igt@i915_module_l...@load.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122455v2/bat-adlp-11/igt@i915_module_l...@load.html Known issues Here are the changes found in Patchwork_122455v2 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-adlp-11:NOTRUN -> [SKIP][3] ([i915#7456]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122455v2/bat-adlp-11/igt@debugfs_t...@basic-hwmon.html - bat-mtlp-6: NOTRUN -> [SKIP][4] ([i915#7456]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122455v2/bat-mtlp-6/igt@debugfs_t...@basic-hwmon.html * igt@fbdev@info: - bat-mtlp-6: NOTRUN -> [SKIP][5] ([i915#1849] / [i915#2582]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122455v2/bat-mtlp-6/igt@fb...@info.html * igt@fbdev@write: - bat-mtlp-6: NOTRUN -> [SKIP][6] ([i915#2582]) +3 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122455v2/bat-mtlp-6/igt@fb...@write.html * igt@gem_huc_copy@huc-copy: - fi-kbl-soraka: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#2190]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122455v2/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-kbl-soraka: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#4613]) +3 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122455v2/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html * igt@gem_lmem_swapping@verify-random: - bat-mtlp-6: NOTRUN -> [SKIP][9] ([i915#4613]) +3 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122455v2/bat-mtlp-6/igt@gem_lmem_swapp...@verify-random.html * igt@gem_mmap@basic: - bat-mtlp-6: NOTRUN -> [SKIP][10] ([i915#4083]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122455v2/bat-mtlp-6/igt@gem_m...@basic.html * igt@gem_tiled_blits@basic: - bat-mtlp-6: NOTRUN -> [SKIP][11] ([i915#4077]) +2 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122455v2/bat-mtlp-6/igt@gem_tiled_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-mtlp-6: NOTRUN -> [SKIP][12] ([i915#4079]) +1 similar issue [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122455v2/bat-mtlp-6/igt@gem_tiled_pread_basic.html - bat-adlp-11:NOTRUN -> [SKIP][13] ([i915#3282]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122455v2/bat-adlp-11/igt@gem_tiled_pread_basic.html * igt@i915_pm_backlight@basic-brightness: - bat-mtlp-6: NOTRUN -> [SKIP][14] ([i915#3546]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122455v2/bat-mtlp-6/igt@i915_pm_backli...@basic-brightness.html * igt@i915_pm_rps@basic-api: - bat-mtlp-6: NOTRUN -> [SKIP][15] ([i915#6621]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122455v2/bat-mtlp-6/igt@i915_pm_...@basic-api.html * igt@i915_selftest@live@gt_heartbeat: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][16] ([i915#5334] / [i915#7872]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122455v2/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@gt_pm: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][17] ([i915#1886] / [i915#7913]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122455v2/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html * igt@i915_suspend@basic-s3-without-i915: - bat-mtlp-6: NOTRUN -> [SKIP][18] ([i915#6645]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122455v2/bat-mtlp-6/igt@i915_susp...@basic-s3-without-i915.html *
[Intel-gfx] [PATCH v3 i-g-t] tests/i915_pm_freq_api: Ignore zero register value
Register read for requested_freq can return 0 when system is
in runtime_pm. Make allowance for this case.
v2: Explicit check for runtime_pm status (Riana)
v3: Revert back to v1, the runtime util functions do not work
as expected.
Link: https://gitlab.freedesktop.org/drm/intel/issues/8736
Link: https://gitlab.freedesktop.org/drm/intel/issues/8989
Reviewed-by: Riana Tauro
Signed-off-by: Vinay Belgaumkar
---
tests/i915/i915_pm_freq_api.c | 18 ++
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/tests/i915/i915_pm_freq_api.c b/tests/i915/i915_pm_freq_api.c
index cf21cc936..9c71411ee 100644
--- a/tests/i915/i915_pm_freq_api.c
+++ b/tests/i915/i915_pm_freq_api.c
@@ -88,6 +88,7 @@ static void test_freq_basic_api(int dirfd, int gt)
static void test_reset(int i915, int dirfd, int gt, int count)
{
uint32_t rpn = get_freq(dirfd, RPS_RPn_FREQ_MHZ);
+ uint32_t req_freq;
int fd;
for (int i = 0; i < count; i++) {
@@ -95,14 +96,18 @@ static void test_reset(int i915, int dirfd, int gt, int
count)
igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn) > 0);
igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpn) > 0);
usleep(ACT_FREQ_LATENCY_US);
- igt_assert_eq(get_freq(dirfd, RPS_CUR_FREQ_MHZ), rpn);
+ req_freq = get_freq(dirfd, RPS_CUR_FREQ_MHZ);
+ if (req_freq)
+ igt_assert_eq(req_freq, rpn);
/* Manually trigger a GT reset */
fd = igt_debugfs_gt_open(i915, gt, "reset", O_WRONLY);
igt_require(fd >= 0);
igt_ignore_warn(write(fd, "1\n", 2));
- igt_assert_eq(get_freq(dirfd, RPS_CUR_FREQ_MHZ), rpn);
+ req_freq = get_freq(dirfd, RPS_CUR_FREQ_MHZ);
+ if (req_freq)
+ igt_assert_eq(req_freq, rpn);
}
close(fd);
}
@@ -110,17 +115,22 @@ static void test_reset(int i915, int dirfd, int gt, int
count)
static void test_suspend(int i915, int dirfd, int gt)
{
uint32_t rpn = get_freq(dirfd, RPS_RPn_FREQ_MHZ);
+ uint32_t req_freq;
igt_assert(set_freq(dirfd, RPS_MIN_FREQ_MHZ, rpn) > 0);
igt_assert(set_freq(dirfd, RPS_MAX_FREQ_MHZ, rpn) > 0);
usleep(ACT_FREQ_LATENCY_US);
- igt_assert_eq(get_freq(dirfd, RPS_CUR_FREQ_MHZ), rpn);
+ req_freq = get_freq(dirfd, RPS_CUR_FREQ_MHZ);
+ if (req_freq)
+ igt_assert_eq(req_freq, rpn);
/* Manually trigger a suspend */
igt_system_suspend_autoresume(SUSPEND_STATE_S3,
SUSPEND_TEST_NONE);
- igt_assert_eq(get_freq(dirfd, RPS_CUR_FREQ_MHZ), rpn);
+ req_freq = get_freq(dirfd, RPS_CUR_FREQ_MHZ);
+ if (req_freq)
+ igt_assert_eq(req_freq, rpn);
}
int i915 = -1;
--
2.38.1
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Revert "drm/edid: Fix csync detailed mode parsing" (rev2)
== Series Details == Series: Revert "drm/edid: Fix csync detailed mode parsing" (rev2) URL : https://patchwork.freedesktop.org/series/122455/ State : warning == Summary == Error: dim checkpatch failed /home/kbuild/linux/maintainer-tools/dim: line 50: /home/kbuild/.dimrc: No such file or directory
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Revert "drm/edid: Fix csync detailed mode parsing" (rev2)
== Series Details == Series: Revert "drm/edid: Fix csync detailed mode parsing" (rev2) URL : https://patchwork.freedesktop.org/series/122455/ State : warning == Summary == Error: dim sparse failed /home/kbuild/linux/maintainer-tools/dim: line 50: /home/kbuild/.dimrc: No such file or directory
Re: [Intel-gfx] [PATCH v5 9/9] drm/i915: Replace several IS_METEORLAKE with proper IP version checks
Quoting Matt Roper (2023-08-21 15:06:29-03:00)
>Many of the IS_METEORLAKE conditions throughout the driver are supposed
>to be checks for Xe_LPG and/or Xe_LPM+ IP, not for the MTL platform
>specifically. Update those checks to ensure that the code will still
>operate properly if/when these IP versions show up on future platforms.
>
>v2:
> - Update two more conditions (one for pg_enable, one for MTL HuC
> compatibility).
>v3:
> - Don't change GuC/HuC compatibility check, which sounds like it truly
> is specific to the MTL platform. (Gustavo)
> - Drop a non-lineage workaround number for the OA timestamp frequency
> workaround. (Gustavo)
>
>Cc: Gustavo Sousa
>Signed-off-by: Matt Roper
Reviewed-by: Gustavo Sousa
>---
> drivers/gpu/drm/i915/gem/i915_gem_create.c | 4 ++--
> drivers/gpu/drm/i915/gt/intel_engine_pm.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_mocs.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_rc6.c| 2 +-
> drivers/gpu/drm/i915/gt/intel_reset.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_rps.c| 2 +-
> drivers/gpu/drm/i915/i915_debugfs.c| 2 +-
> drivers/gpu/drm/i915/i915_perf.c | 11 +--
> 8 files changed, 13 insertions(+), 14 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c
>b/drivers/gpu/drm/i915/gem/i915_gem_create.c
>index d24c0ce8805c..19156ba4b9ef 100644
>--- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
>+++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
>@@ -405,8 +405,8 @@ static int ext_set_pat(struct i915_user_extension __user
>*base, void *data)
> BUILD_BUG_ON(sizeof(struct drm_i915_gem_create_ext_set_pat) !=
> offsetofend(struct drm_i915_gem_create_ext_set_pat,
> rsvd));
>
>-/* Limiting the extension only to Meteor Lake */
>-if (!IS_METEORLAKE(i915))
>+/* Limiting the extension only to Xe_LPG and beyond */
>+if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 70))
> return -ENODEV;
>
> if (copy_from_user(, base, sizeof(ext)))
>diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
>b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
>index b538b5c04948..e91fc881dbf1 100644
>--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
>+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
>@@ -21,7 +21,7 @@ static void intel_gsc_idle_msg_enable(struct intel_engine_cs
>*engine)
> {
> struct drm_i915_private *i915 = engine->i915;
>
>-if (IS_METEORLAKE(i915) && engine->id == GSC0) {
>+if (MEDIA_VER(i915) >= 13 && engine->id == GSC0) {
> intel_uncore_write(engine->gt->uncore,
>RC_PSMI_CTRL_GSCCS,
>_MASKED_BIT_DISABLE(IDLE_MSG_DISABLE));
>diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c
>b/drivers/gpu/drm/i915/gt/intel_mocs.c
>index bf8b42d2d327..07269ff3be13 100644
>--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
>+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
>@@ -495,7 +495,7 @@ static unsigned int get_mocs_settings(const struct
>drm_i915_private *i915,
> memset(table, 0, sizeof(struct drm_i915_mocs_table));
>
> table->unused_entries_index = I915_MOCS_PTE;
>-if (IS_METEORLAKE(i915)) {
>+if (IS_GFX_GT_IP_RANGE(>gt0, IP_VER(12, 70), IP_VER(12, 71))) {
> table->size = ARRAY_SIZE(mtl_mocs_table);
> table->table = mtl_mocs_table;
> table->n_entries = MTL_NUM_MOCS_ENTRIES;
>diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c
>b/drivers/gpu/drm/i915/gt/intel_rc6.c
>index 86df42cb5823..8b67abd720be 100644
>--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
>+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
>@@ -123,7 +123,7 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
> * temporary wa and should be removed after fixing real cause
> * of forcewake timeouts.
> */
>-if (IS_METEORLAKE(gt->i915))
>+if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)))
> pg_enable =
> GEN9_MEDIA_PG_ENABLE |
> GEN11_MEDIA_SAMPLER_PG_ENABLE;
>diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
>b/drivers/gpu/drm/i915/gt/intel_reset.c
>index fd6c22aeb670..98575d79c446 100644
>--- a/drivers/gpu/drm/i915/gt/intel_reset.c
>+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
>@@ -705,7 +705,7 @@ static int __reset_guc(struct intel_gt *gt)
>
> static bool needs_wa_14015076503(struct intel_gt *gt, intel_engine_mask_t
> engine_mask)
> {
>-if (!IS_METEORLAKE(gt->i915) || !HAS_ENGINE(gt, GSC0))
>+if (MEDIA_VER_FULL(gt->i915) != IP_VER(13, 0) || !HAS_ENGINE(gt,
>GSC0))
> return false;
>
> if (!__HAS_ENGINE(engine_mask, GSC0))
>diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
>b/drivers/gpu/drm/i915/gt/intel_rps.c
>index 092542f53aad..4feef874e6d6 100644
>--- a/drivers/gpu/drm/i915/gt/intel_rps.c
>+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
>@@ -1161,7 +1161,7 @@ void
Re: [Intel-gfx] [PATCH v5 5/9] drm/i915: Eliminate IS_MTL_MEDIA_STEP
Quoting Matt Roper (2023-08-21 15:06:25-03:00)
>Stepping-specific media behavior shouldn't be tied to MTL as a platform,
>but rather specifically to the Xe_LPM+ IP. Future non-MTL platforms may
>re-use this IP and will need to follow the exact same logic and apply
>the same workarounds. IS_MTL_MEDIA_STEP() is dropped in favor of
>IS_MEDIA_GT_IP_STEP, which checks the media IP version associated with a
>specific IP and also ensures that we're operating on the media GT, not
>the primary GT.
>
>v2:
> - Switch to the IS_GT_IP_STEP macro.
>v3:
> - Switch back to long-form IS_MEDIA_GT_IP_STEP. (Jani)
>v4:
> - Build IS_MEDIA_GT_IP_STEP on top of IS_MEDIA_GT_IP_RANGE and
> IS_MEDIA_STEP building blocks and name the parameters from/until
> rather than begin/fixed.. (Jani)
>v5:
> - Tweak macro comment wording. (Gustavo)
> - Add a check to catch NULL gt in IS_MEDIA_GT_IP_RANGE; this allows it
> to be used safely on i915->media_gt, which may be NULL on some
> platforms. (Gustavo)
>
>Cc: Jani Nikula
>Cc: Gustavo Sousa
>Signed-off-by: Matt Roper
Reviewed-by: Gustavo Sousa
>---
> drivers/gpu/drm/i915/gt/intel_gt.h | 32 +
> drivers/gpu/drm/i915/gt/intel_rc6.c | 3 +--
> drivers/gpu/drm/i915/i915_drv.h | 4
> drivers/gpu/drm/i915/i915_perf.c| 15 --
> 4 files changed, 37 insertions(+), 17 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h
>b/drivers/gpu/drm/i915/gt/intel_gt.h
>index 6e63b46682f7..239848bcb2a4 100644
>--- a/drivers/gpu/drm/i915/gt/intel_gt.h
>+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
>@@ -25,6 +25,20 @@ struct drm_printer;
> GRAPHICS_VER_FULL((gt)->i915) >= (from) && \
> GRAPHICS_VER_FULL((gt)->i915) <= (until)))
>
>+/*
>+ * Check that the GT is a media GT and has an IP version within the
>+ * specified range (inclusive).
>+ *
>+ * Only usable on platforms with a standalone media design (i.e., IP version
>13
>+ * and higher).
>+ */
>+#define IS_MEDIA_GT_IP_RANGE(gt, from, until) ( \
>+BUILD_BUG_ON_ZERO((from) < IP_VER(13, 0)) + \
>+BUILD_BUG_ON_ZERO((until) < (from)) + \
>+((gt) && (gt)->type == GT_MEDIA && \
>+ MEDIA_VER_FULL((gt)->i915) >= (from) && \
>+ MEDIA_VER_FULL((gt)->i915) <= (until)))
>+
> /*
> * Check that the GT is a graphics GT with a specific IP version and has
> * a stepping in the range [from, until). The lower stepping bound is
>@@ -45,6 +59,24 @@ struct drm_printer;
> (IS_GFX_GT_IP_RANGE((gt), (ipver), (ipver)) && \
> IS_GRAPHICS_STEP((gt)->i915, (from), (until
>
>+/*
>+ * Check that the GT is a media GT with a specific IP version and has
>+ * a stepping in the range [from, until). The lower stepping bound is
>+ * inclusive, the upper bound is exclusive. The most common use-case of this
>+ * macro is for checking bounds for workarounds, which usually have a stepping
>+ * ("from") at which the hardware issue is first present and another stepping
>+ * ("until") at which a hardware fix is present and the software workaround is
>+ * no longer necessary. "STEP_FOREVER" can be passed as "until" for
>+ * workarounds that have no upper stepping bound for the specified IP version.
>+ *
>+ * This macro may only be used to match on platforms that have a standalone
>+ * media design (i.e., media version 13 or higher).
>+ */
>+#define IS_MEDIA_GT_IP_STEP(gt, ipver, from, until) ( \
>+BUILD_BUG_ON_ZERO((until) <= (from)) + \
>+(IS_MEDIA_GT_IP_RANGE((gt), (ipver), (ipver)) && \
>+ IS_MEDIA_STEP((gt)->i915, (from), (until
>+
> #define GT_TRACE(gt, fmt, ...) do {\
> const struct intel_gt *gt__ __maybe_unused = (gt);\
> GEM_TRACE("%s " fmt, dev_name(gt__->i915->drm.dev),\
>diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c
>b/drivers/gpu/drm/i915/gt/intel_rc6.c
>index 90933fb8cb97..86df42cb5823 100644
>--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
>+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
>@@ -524,8 +524,7 @@ static bool rc6_supported(struct intel_rc6 *rc6)
> return false;
> }
>
>-if (IS_MTL_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
>-gt->type == GT_MEDIA) {
>+if (IS_MEDIA_GT_IP_STEP(gt, IP_VER(13, 0), STEP_A0, STEP_B0)) {
> drm_notice(>drm,
>"Media RC6 disabled on A step\n");
> return false;
>diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>index 3bb216d55c3e..b0894e7de403 100644
>--- a/drivers/gpu/drm/i915/i915_drv.h
>+++ b/drivers/gpu/drm/i915/i915_drv.h
>@@ -662,10 +662,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> (IS_METEORLAKE(__i915) && \
> IS_DISPLAY_STEP(__i915, since, until))
>
>-#define IS_MTL_MEDIA_STEP(__i915, since, until) \
>-(IS_METEORLAKE(__i915) && \
>- IS_MEDIA_STEP(__i915, since, until))
>-
> #define
[Intel-gfx] [PATCH] drm/i915/rpl: Update pci ids for RPL P/U
Update pci device ids as per bspec for RPL P/U. Bpsec: 55376 Signed-off-by: Dnyaneshwar Bhadane --- include/drm/i915_pciids.h | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index e1e10dfbb661..8a697a9a84af 100644 --- a/include/drm/i915_pciids.h +++ b/include/drm/i915_pciids.h @@ -688,15 +688,15 @@ /* RPL-U */ #define INTEL_RPLU_IDS(info) \ INTEL_VGA_DEVICE(0xA721, info), \ - INTEL_VGA_DEVICE(0xA7A1, info), \ - INTEL_VGA_DEVICE(0xA7A9, info) + INTEL_VGA_DEVICE(0xA7AC, info), \ + INTEL_VGA_DEVICE(0xA7AD, info) /* RPL-P */ #define INTEL_RPLP_IDS(info) \ INTEL_RPLU_IDS(info), \ INTEL_VGA_DEVICE(0xA720, info), \ - INTEL_VGA_DEVICE(0xA7A0, info), \ - INTEL_VGA_DEVICE(0xA7A8, info) + INTEL_VGA_DEVICE(0xA7AA, info), \ + INTEL_VGA_DEVICE(0xA7AB, info) /* DG2 */ #define INTEL_DG2_G10_IDS(info) \ -- 2.34.1
Re: [Intel-gfx] [PATCH v4] drm/i915/display: Dual refresh rate fastset fixes with VRR fastset
Hi Jani,
I have added the Fixes tag as well as the gitlab issue that this patch
fixes as per your feedback on prev rev (Rev3).
Could you please review this version and provide your feedback so we
can get this upstream fix merged.
Thanks for your time and consideration.
Regards
Manasi
On Fri, Aug 18, 2023 at 12:05 PM Manasi Navare
wrote:
>
> Dual refresh rate (DRR) fastset seamlessly lets refresh rate
> throttle without needing a full modeset.
> However with the recent VRR fastset patches that got merged this
> logic was broken. This is broken because now with VRR fastset
> VRR parameters are calculated by default at the nominal refresh rate say
> 120Hz.
> Now when DRR throttle happens to switch refresh rate to 60Hz, crtc clock
> changes and this throws a mismatch in VRR parameters and fastset logic
> for DRR gets thrown off and full modeset is indicated.
>
> This patch fixes this by ignoring the pipe mismatch for VRR parameters
> in the case of DRR and when VRR is not enabled. With this fix, DRR
> will still throttle seamlessly as long as VRR is not enabled.
>
> This will still need a full modeset for both DRR and VRR operating together
> during the refresh rate throttle and then enabling VRR since now VRR
> parameters need to be recomputed with new crtc clock and written to HW.
>
> This DRR + VRR fastset in conjunction needs more work in the driver and
> will be fixed in later patches.
>
> v3:
> Compute new VRR params whenever there is fastset and its non DRRS.
> This will ensure it computes while switching to a fixed RR (Mitul)
>
> v2:
> Check for pipe config mismatch in crtc clock whenever VRR is enabled
>
> Fixes: 1af1d18825d3 ("drm/i915/vrr: Allow VRR to be toggled during fastsets")
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9154
> Cc: Drew Davenport
> Cc: Ville Syrjälä
> Cc: Sean Paul
> Cc: Mitul Golani
> Signed-off-by: Manasi Navare
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 14 --
> 1 file changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 763ab569d8f3..2cf3b22adaf7 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5352,7 +5352,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
> *current_config,
> if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5)
> PIPE_CONF_CHECK_I(pipe_bpp);
>
> - if (!fastset || !pipe_config->seamless_m_n) {
> + if (!fastset || !pipe_config->seamless_m_n ||
> pipe_config->vrr.enable) {
> PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock);
> PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock);
> }
> @@ -5387,11 +5387,13 @@ intel_pipe_config_compare(const struct
> intel_crtc_state *current_config,
>
> if (!fastset)
> PIPE_CONF_CHECK_BOOL(vrr.enable);
> - PIPE_CONF_CHECK_I(vrr.vmin);
> - PIPE_CONF_CHECK_I(vrr.vmax);
> - PIPE_CONF_CHECK_I(vrr.flipline);
> - PIPE_CONF_CHECK_I(vrr.pipeline_full);
> - PIPE_CONF_CHECK_I(vrr.guardband);
> + if ((fastset && !pipe_config->seamless_m_n) ||
> pipe_config->vrr.enable) {
> + PIPE_CONF_CHECK_I(vrr.vmin);
> + PIPE_CONF_CHECK_I(vrr.vmax);
> + PIPE_CONF_CHECK_I(vrr.flipline);
> + PIPE_CONF_CHECK_I(vrr.pipeline_full);
> + PIPE_CONF_CHECK_I(vrr.guardband);
> + }
>
> #undef PIPE_CONF_CHECK_X
> #undef PIPE_CONF_CHECK_I
> --
> 2.42.0.rc1.204.g551eb34607-goog
>
[Intel-gfx] [PATCH v5 9/9] drm/i915: Replace several IS_METEORLAKE with proper IP version checks
Many of the IS_METEORLAKE conditions throughout the driver are supposed
to be checks for Xe_LPG and/or Xe_LPM+ IP, not for the MTL platform
specifically. Update those checks to ensure that the code will still
operate properly if/when these IP versions show up on future platforms.
v2:
- Update two more conditions (one for pg_enable, one for MTL HuC
compatibility).
v3:
- Don't change GuC/HuC compatibility check, which sounds like it truly
is specific to the MTL platform. (Gustavo)
- Drop a non-lineage workaround number for the OA timestamp frequency
workaround. (Gustavo)
Cc: Gustavo Sousa
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gem/i915_gem_create.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 2 +-
drivers/gpu/drm/i915/gt/intel_mocs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_rc6.c| 2 +-
drivers/gpu/drm/i915/gt/intel_reset.c | 2 +-
drivers/gpu/drm/i915/gt/intel_rps.c| 2 +-
drivers/gpu/drm/i915/i915_debugfs.c| 2 +-
drivers/gpu/drm/i915/i915_perf.c | 11 +--
8 files changed, 13 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c
b/drivers/gpu/drm/i915/gem/i915_gem_create.c
index d24c0ce8805c..19156ba4b9ef 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
@@ -405,8 +405,8 @@ static int ext_set_pat(struct i915_user_extension __user
*base, void *data)
BUILD_BUG_ON(sizeof(struct drm_i915_gem_create_ext_set_pat) !=
offsetofend(struct drm_i915_gem_create_ext_set_pat, rsvd));
- /* Limiting the extension only to Meteor Lake */
- if (!IS_METEORLAKE(i915))
+ /* Limiting the extension only to Xe_LPG and beyond */
+ if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 70))
return -ENODEV;
if (copy_from_user(, base, sizeof(ext)))
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
index b538b5c04948..e91fc881dbf1 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
@@ -21,7 +21,7 @@ static void intel_gsc_idle_msg_enable(struct intel_engine_cs
*engine)
{
struct drm_i915_private *i915 = engine->i915;
- if (IS_METEORLAKE(i915) && engine->id == GSC0) {
+ if (MEDIA_VER(i915) >= 13 && engine->id == GSC0) {
intel_uncore_write(engine->gt->uncore,
RC_PSMI_CTRL_GSCCS,
_MASKED_BIT_DISABLE(IDLE_MSG_DISABLE));
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c
b/drivers/gpu/drm/i915/gt/intel_mocs.c
index bf8b42d2d327..07269ff3be13 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -495,7 +495,7 @@ static unsigned int get_mocs_settings(const struct
drm_i915_private *i915,
memset(table, 0, sizeof(struct drm_i915_mocs_table));
table->unused_entries_index = I915_MOCS_PTE;
- if (IS_METEORLAKE(i915)) {
+ if (IS_GFX_GT_IP_RANGE(>gt0, IP_VER(12, 70), IP_VER(12, 71))) {
table->size = ARRAY_SIZE(mtl_mocs_table);
table->table = mtl_mocs_table;
table->n_entries = MTL_NUM_MOCS_ENTRIES;
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c
b/drivers/gpu/drm/i915/gt/intel_rc6.c
index 86df42cb5823..8b67abd720be 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -123,7 +123,7 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
* temporary wa and should be removed after fixing real cause
* of forcewake timeouts.
*/
- if (IS_METEORLAKE(gt->i915))
+ if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)))
pg_enable =
GEN9_MEDIA_PG_ENABLE |
GEN11_MEDIA_SAMPLER_PG_ENABLE;
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
b/drivers/gpu/drm/i915/gt/intel_reset.c
index fd6c22aeb670..98575d79c446 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -705,7 +705,7 @@ static int __reset_guc(struct intel_gt *gt)
static bool needs_wa_14015076503(struct intel_gt *gt, intel_engine_mask_t
engine_mask)
{
- if (!IS_METEORLAKE(gt->i915) || !HAS_ENGINE(gt, GSC0))
+ if (MEDIA_VER_FULL(gt->i915) != IP_VER(13, 0) || !HAS_ENGINE(gt, GSC0))
return false;
if (!__HAS_ENGINE(engine_mask, GSC0))
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
b/drivers/gpu/drm/i915/gt/intel_rps.c
index 092542f53aad..4feef874e6d6 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -1161,7 +1161,7 @@ void gen6_rps_get_freq_caps(struct intel_rps *rps, struct
intel_rps_freq_caps *c
{
struct drm_i915_private *i915 = rps_to_i915(rps);
- if (IS_METEORLAKE(i915))
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
[Intel-gfx] [PATCH v5 4/9] drm/i915: Eliminate IS_MTL_GRAPHICS_STEP
Several workarounds are guarded by IS_MTL_GRAPHICS_STEP. However none
of these workarounds are actually tied to MTL as a platform; they only
relate to the Xe_LPG graphics IP, regardless of what platform it appears
in. At the moment MTL is the only platform that uses Xe_LPG with IP
versions 12.70 and 12.71, but we can't count on this being true in the
future. Switch these to use a new IS_GFX_GT_IP_STEP() macro instead
that is purely based on IP version. IS_GFX_GT_IP_STEP() is also
GT-based rather than device-based, which will help prevent mistakes
where we accidentally try to apply Xe_LPG graphics workarounds to the
Xe_LPM+ media GT and vice-versa.
v2:
- Switch to a more generic and shorter IS_GT_IP_STEP macro that can be
used for both graphics and media IP (and any other kind of GTs that
show up in the future).
v3:
- Switch back to long-form IS_GFX_GT_IP_STEP macro. (Jani)
- Move macro to intel_gt.h. (Andi)
v4:
- Build IS_GFX_GT_IP_STEP on top of IS_GFX_GT_IP_RANGE and
IS_GRAPHICS_STEP building blocks and name the parameters from/until
rather than begin/fixed. (Jani)
- Fix usage examples in comment.
v5:
- Tweak comment on macro. (Gustavo)
Cc: Gustavo Sousa
Cc: Tvrtko Ursulin
Cc: Andi Shyti
Cc: Jani Nikula
Signed-off-by: Matt Roper
Reviewed-by: Gustavo Sousa
Reviewed-by: Andi Shyti
---
.../drm/i915/display/skl_universal_plane.c| 5 +-
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 11 +++--
drivers/gpu/drm/i915/gt/intel_gt.h| 20
drivers/gpu/drm/i915/gt/intel_gt_mcr.c| 7 ++-
drivers/gpu/drm/i915/gt/intel_lrc.c | 4 +-
drivers/gpu/drm/i915/gt/intel_reset.c | 2 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 48 ++-
drivers/gpu/drm/i915/gt/uc/intel_guc.c| 2 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 4 --
10 files changed, 62 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index a408ec2d3958..4566c95da1ca 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -20,6 +20,7 @@
#include "skl_scaler.h"
#include "skl_universal_plane.h"
#include "skl_watermark.h"
+#include "gt/intel_gt.h"
#include "pxp/intel_pxp.h"
static const u32 skl_plane_formats[] = {
@@ -2169,8 +2170,8 @@ static bool skl_plane_has_rc_ccs(struct drm_i915_private
*i915,
enum pipe pipe, enum plane_id plane_id)
{
/* Wa_14017240301 */
- if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
- IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+ if (IS_GFX_GT_IP_STEP(to_gt(i915), IP_VER(12, 70), STEP_A0, STEP_B0) ||
+ IS_GFX_GT_IP_STEP(to_gt(i915), IP_VER(12, 71), STEP_A0, STEP_B0))
return false;
/* Wa_22011186057 */
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index a4ff55aa5e55..6187b25b67ab 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -4,9 +4,9 @@
*/
#include "gen8_engine_cs.h"
-#include "i915_drv.h"
#include "intel_engine_regs.h"
#include "intel_gpu_commands.h"
+#include "intel_gt.h"
#include "intel_lrc.h"
#include "intel_ring.h"
@@ -226,8 +226,8 @@ u32 *gen12_emit_aux_table_inv(struct intel_engine_cs
*engine, u32 *cs)
static int mtl_dummy_pipe_control(struct i915_request *rq)
{
/* Wa_14016712196 */
- if (IS_MTL_GRAPHICS_STEP(rq->i915, M, STEP_A0, STEP_B0) ||
- IS_MTL_GRAPHICS_STEP(rq->i915, P, STEP_A0, STEP_B0)) {
+ if (IS_GFX_GT_IP_STEP(rq->engine->gt, IP_VER(12, 70), STEP_A0, STEP_B0)
||
+ IS_GFX_GT_IP_STEP(rq->engine->gt, IP_VER(12, 71), STEP_A0,
STEP_B0)) {
u32 *cs;
/* dummy PIPE_CONTROL + depth flush */
@@ -799,6 +799,7 @@ u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request
*rq, u32 *cs)
u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
{
struct drm_i915_private *i915 = rq->i915;
+ struct intel_gt *gt = rq->engine->gt;
u32 flags = (PIPE_CONTROL_CS_STALL |
PIPE_CONTROL_TLB_INVALIDATE |
PIPE_CONTROL_TILE_CACHE_FLUSH |
@@ -809,8 +810,8 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request
*rq, u32 *cs)
PIPE_CONTROL_FLUSH_ENABLE);
/* Wa_14016712196 */
- if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
- IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+ if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
+ IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
/* dummy PIPE_CONTROL + depth flush */
cs = gen12_emit_pipe_control(cs, 0,
[Intel-gfx] [PATCH v5 7/9] drm/i915/mtl: Eliminate subplatforms
Now that we properly match the Xe_LPG IP versions associated with
various workarounds, there's no longer any need to define separate MTL
subplatform in the driver. Nothing in the code is conditional on MTL-M
or MTL-P base platforms. Furthermore, I'm not sure the "M" and "P"
designations are even an accurate representation of which specific
platforms would have which IP versions; those were mostly just
placeholders from a long time ago. The reality is that the IP version
present on a platform gets read from a fuse register at driver init; we
shouldn't be trying to guess which IP is present based on PCI ID
anymore.
Signed-off-by: Matt Roper
Reviewed-by: Nemesa Garg
Reviewed-by: Gustavo Sousa
---
drivers/gpu/drm/i915/i915_drv.h | 4
drivers/gpu/drm/i915/intel_device_info.c | 14 --
drivers/gpu/drm/i915/intel_device_info.h | 4
include/drm/i915_pciids.h| 11 +++
4 files changed, 3 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f83016da415b..87ffc477c3b1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -575,10 +575,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_PONTEVECCHIO(i915) IS_PLATFORM(i915, INTEL_PONTEVECCHIO)
#define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE)
-#define IS_METEORLAKE_M(i915) \
- IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M)
-#define IS_METEORLAKE_P(i915) \
- IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_P)
#define IS_DG2_G10(i915) \
IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G10)
#define IS_DG2_G11(i915) \
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index ea0ec6174ce5..9dfa680a4c62 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -206,14 +206,6 @@ static const u16 subplatform_g12_ids[] = {
INTEL_DG2_G12_IDS(0),
};
-static const u16 subplatform_m_ids[] = {
- INTEL_MTL_M_IDS(0),
-};
-
-static const u16 subplatform_p_ids[] = {
- INTEL_MTL_P_IDS(0),
-};
-
static bool find_devid(u16 id, const u16 *p, unsigned int num)
{
for (; num; num--, p++) {
@@ -275,12 +267,6 @@ static void intel_device_info_subplatform_init(struct
drm_i915_private *i915)
} else if (find_devid(devid, subplatform_g12_ids,
ARRAY_SIZE(subplatform_g12_ids))) {
mask = BIT(INTEL_SUBPLATFORM_G12);
- } else if (find_devid(devid, subplatform_m_ids,
- ARRAY_SIZE(subplatform_m_ids))) {
- mask = BIT(INTEL_SUBPLATFORM_M);
- } else if (find_devid(devid, subplatform_p_ids,
- ARRAY_SIZE(subplatform_p_ids))) {
- mask = BIT(INTEL_SUBPLATFORM_P);
}
GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK);
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index 19d120728ff1..39817490b13f 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -129,10 +129,6 @@ enum intel_platform {
#define INTEL_SUBPLATFORM_N1
#define INTEL_SUBPLATFORM_RPLU 2
-/* MTL */
-#define INTEL_SUBPLATFORM_M0
-#define INTEL_SUBPLATFORM_P1
-
enum intel_ppgtt_type {
INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index e1e10dfbb661..38dae757d1a8 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -738,18 +738,13 @@
#define INTEL_ATS_M_IDS(info) \
INTEL_ATS_M150_IDS(info), \
INTEL_ATS_M75_IDS(info)
+
/* MTL */
-#define INTEL_MTL_M_IDS(info) \
+#define INTEL_MTL_IDS(info) \
INTEL_VGA_DEVICE(0x7D40, info), \
- INTEL_VGA_DEVICE(0x7D60, info)
-
-#define INTEL_MTL_P_IDS(info) \
INTEL_VGA_DEVICE(0x7D45, info), \
INTEL_VGA_DEVICE(0x7D55, info), \
+ INTEL_VGA_DEVICE(0x7D60, info), \
INTEL_VGA_DEVICE(0x7DD5, info)
-#define INTEL_MTL_IDS(info) \
- INTEL_MTL_M_IDS(info), \
- INTEL_MTL_P_IDS(info)
-
#endif /* _I915_PCIIDS_H */
--
2.41.0
[Intel-gfx] [PATCH v5 2/9] drm/i915/xelpmp: Don't assume workarounds extend to future platforms
The currently implemented Xe_LPM+ workarounds are specific to media
version 13.00. When new IP versions show up in the future, they'll need
their own workaround lists.
Signed-off-by: Matt Roper
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index f7f3376eccd0..804b38bc9482 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1712,10 +1712,10 @@ gt_init_workarounds(struct intel_gt *gt, struct
i915_wa_list *wal)
gt_tuning_settings(gt, wal);
if (gt->type == GT_MEDIA) {
- if (MEDIA_VER(i915) >= 13)
+ if (MEDIA_VER_FULL(i915) == IP_VER(13, 0))
xelpmp_gt_workarounds_init(gt, wal);
else
- MISSING_CASE(MEDIA_VER(i915));
+ MISSING_CASE(MEDIA_VER_FULL(i915));
return;
}
--
2.41.0
[Intel-gfx] [PATCH v5 8/9] drm/i915/display: Eliminate IS_METEORLAKE checks
Most of the IS_METEORLAKE checks in the display code shouldn't actually
be tied to MTL as a platform, but rather to the Xe_LPD+ display IP
(which is used in MTL, but may show up again in future platforms). In
cases where we're trying to match that specific IP, use a version check
against IP_VER(14, 0). For cases where we're just handling new behavior
introduced by this IP (but which may also be inherited by future IP as
well), use a ver >= 14 check.
The one exception here is the stolen memory workaround Wa_13010847436
(which is mislabelled as "Wa_22018444074" in the code). That's truly a
MTL-specific issue rather than being tied to any of the IP blocks, so
leaving the condition as IS_METEORLAKE is correct there.
v2:
- cdclk check should be >=, not >. (Gustavo)
Signed-off-by: Matt Roper
Reviewed-by: Gustavo Sousa
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 4 ++--
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_dmc.c | 2 +-
4 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index de04a6fe54f3..ad5251ba6fe1 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1841,7 +1841,7 @@ static bool
cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i91
static bool pll_enable_wa_needed(struct drm_i915_private *dev_priv)
{
- return ((IS_DG2(dev_priv) || IS_METEORLAKE(dev_priv)) &&
+ return ((IS_DG2(dev_priv) || DISPLAY_VER_FULL(dev_priv) == IP_VER(14,
0)) &&
dev_priv->display.cdclk.hw.vco > 0 &&
HAS_CDCLK_SQUASH(dev_priv));
}
@@ -3590,7 +3590,7 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = {
*/
void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
{
- if (IS_METEORLAKE(dev_priv)) {
+ if (DISPLAY_VER(dev_priv) >= 14) {
dev_priv->display.funcs.cdclk = _cdclk_funcs;
dev_priv->display.cdclk.table = mtl_cdclk_table;
} else if (IS_DG2(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 26e256165b80..dd489b50ad60 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -31,7 +31,7 @@
bool intel_is_c10phy(struct drm_i915_private *i915, enum phy phy)
{
- if (IS_METEORLAKE(i915) && (phy < PHY_C))
+ if (DISPLAY_VER_FULL(i915) == IP_VER(14, 0) && phy < PHY_C)
return true;
return false;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 8c81206ce90d..db3c26e013e3 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1767,7 +1767,7 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv,
enum phy phy)
if (IS_DG2(dev_priv))
/* DG2's "TC1" output uses a SNPS PHY */
return false;
- else if (IS_ALDERLAKE_P(dev_priv) || IS_METEORLAKE(dev_priv))
+ else if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER_FULL(dev_priv) ==
IP_VER(14, 0))
return phy >= PHY_F && phy <= PHY_I;
else if (IS_TIGERLAKE(dev_priv))
return phy >= PHY_D && phy <= PHY_I;
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index 5f479f3828bb..1623c0c5e8a1 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -998,7 +998,7 @@ void intel_dmc_init(struct drm_i915_private *i915)
INIT_WORK(>work, dmc_load_work_fn);
- if (IS_METEORLAKE(i915)) {
+ if (DISPLAY_VER_FULL(i915) == IP_VER(14, 0)) {
dmc->fw_path = MTL_DMC_PATH;
dmc->max_fw_size = XELPDP_DMC_MAX_FW_SIZE;
} else if (IS_DG2(i915)) {
--
2.41.0
[Intel-gfx] [PATCH v5 6/9] drm/i915: Eliminate IS_MTL_DISPLAY_STEP
Stepping-specific display behavior shouldn't be tied to MTL as a
platform, but rather specifically to the Xe_LPD+ IP. Future non-MTL
platforms may re-use this IP and will need to follow the exact same
logic and apply the same workarounds. IS_MTL_DISPLAY_STEP() is dropped
in favor of a new macro IS_DISPLAY_IP_STEP() that only checks the
display IP version.
v2:
- Rename macro to IS_DISPLAY_IP_STEP for consistency with the
corresponding GT macro and handle steppings the same way.
v3:
- Drop the automatic "STEP_" pasting.
v4:
- Implement IS_DISPLAY_IP_STEP on top of IS_DISPLAY_IP_RANGE /
IS_DISPLAY_STEP building blocks and make the parameters from/until
instead of begin/fixed. (Jani)
- Fix usage details in comment.
v5:
- Tweak macro comment. (Gustavo)
Signed-off-by: Matt Roper
Reviewed-by: Gustavo Sousa
---
.../drm/i915/display/intel_display_device.h | 25 +++
drivers/gpu/drm/i915/display/intel_fbc.c | 3 ++-
drivers/gpu/drm/i915/display/intel_pmdemand.c | 2 +-
drivers/gpu/drm/i915/display/intel_psr.c | 10
drivers/gpu/drm/i915/i915_drv.h | 6 ++---
5 files changed, 35 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h
b/drivers/gpu/drm/i915/display/intel_display_device.h
index eb630a946343..8198401aa5be 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -72,6 +72,31 @@ struct drm_printer;
#define OVERLAY_NEEDS_PHYSICAL(i915)
(DISPLAY_INFO(i915)->overlay_needs_physical)
#define SUPPORTS_TV(i915) (DISPLAY_INFO(i915)->supports_tv)
+/* Check that device has a display IP version within the specific range. */
+#define IS_DISPLAY_IP_RANGE(__i915, from, until) ( \
+ BUILD_BUG_ON_ZERO((from) < IP_VER(2, 0)) + \
+ (DISPLAY_VER_FULL(__i915) >= (from) && \
+DISPLAY_VER_FULL(__i915) <= (until)))
+
+/*
+ * Check if a device has a specific IP version as well as a stepping within the
+ * specified range [from, until). The lower bound is inclusive, the upper
+ * bound is exclusive. The most common use-case of this macro is for checking
+ * bounds for workarounds, which usually have a stepping ("from") at which the
+ * hardware issue is first present and another stepping ("until") at which a
+ * hardware fix is present and the software workaround is no longer necessary.
+ * E.g.,
+ *
+ *IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_B2)
+ *IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_C0, STEP_FOREVER)
+ *
+ * "STEP_FOREVER" can be passed as "until" for workarounds that have no upper
+ * stepping bound for the specified IP version.
+ */
+#define IS_DISPLAY_IP_STEP(__i915, ipver, from, until) \
+ (IS_DISPLAY_IP_RANGE((__i915), (ipver), (ipver)) && \
+IS_DISPLAY_STEP((__i915), (from), (until)))
+
struct intel_display_runtime_info {
struct {
u16 ver;
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display/intel_fbc.c
index 25382022cd27..1c6d467cec26 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -50,6 +50,7 @@
#include "i915_vma.h"
#include "intel_cdclk.h"
#include "intel_de.h"
+#include "intel_display_device.h"
#include "intel_display_trace.h"
#include "intel_display_types.h"
#include "intel_fbc.h"
@@ -1100,7 +1101,7 @@ static int intel_fbc_check_plane(struct
intel_atomic_state *state,
/* Wa_14016291713 */
if ((IS_DISPLAY_VER(i915, 12, 13) ||
-IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
+IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_C0)) &&
crtc_state->has_psr) {
plane_state->no_fbc_reason = "PSR1 enabled (Wa_14016291713)";
return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c
b/drivers/gpu/drm/i915/display/intel_pmdemand.c
index f7608d363634..744e332fa2af 100644
--- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
+++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
@@ -92,7 +92,7 @@ int intel_pmdemand_init(struct drm_i915_private *i915)
_state->base,
_pmdemand_funcs);
- if (IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
+ if (IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_C0))
/* Wa_14016740474 */
intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0,
DMD_RSP_TIMEOUT_DISABLE);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 97d5eef10130..72887c29fb51 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1360,7 +1360,7 @@ static void wm_optimization_wa(struct intel_dp *intel_dp,
bool set_wa_bit = false;
/* Wa_14015648006 */
- if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
+ if
[Intel-gfx] [PATCH v5 1/9] drm/i915: Consolidate condition for Wa_22011802037
The workaround bounds for Wa_22011802037 are somewhat complex and are
replicated in several places throughout the code. Pull the condition
out to a helper function to prevent mistakes if this condition needs to
change again in the future.
Signed-off-by: Matt Roper
Reviewed-by: Gustavo Sousa
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 +---
.../drm/i915/gt/intel_execlists_submission.c | 4 +---
drivers/gpu/drm/i915/gt/intel_reset.c | 18 ++
drivers/gpu/drm/i915/gt/intel_reset.h | 2 ++
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 4 +---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 4 +---
6 files changed, 24 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index ee15486fed0d..dfb69fc977a0 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1617,9 +1617,7 @@ static int __intel_engine_stop_cs(struct intel_engine_cs
*engine,
* Wa_22011802037: Prior to doing a reset, ensure CS is
* stopped, set ring stop bit and prefetch disable bit to halt CS
*/
- if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
- (GRAPHICS_VER(engine->i915) >= 11 &&
- GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
+ if (intel_engine_reset_needs_wa_22011802037(engine->gt))
intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine->mmio_base),
_MASKED_BIT_ENABLE(GEN12_GFX_PREFETCH_DISABLE));
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 8a641bcf777c..4d05321dc5b5 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -3001,9 +3001,7 @@ static void execlists_reset_prepare(struct
intel_engine_cs *engine)
* Wa_22011802037: In addition to stopping the cs, we need
* to wait for any pending mi force wakeups
*/
- if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
- (GRAPHICS_VER(engine->i915) >= 11 &&
- GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
+ if (intel_engine_reset_needs_wa_22011802037(engine->gt))
intel_engine_wait_for_pending_mi_fw(engine);
engine->execlists.reset_ccid = active_ccid(engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
b/drivers/gpu/drm/i915/gt/intel_reset.c
index cc6bd21a3e51..1ff7b42521c9 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -1632,6 +1632,24 @@ void __intel_fini_wedge(struct intel_wedge_me *w)
w->gt = NULL;
}
+/*
+ * Wa_22011802037 requires that we (or the GuC) ensure that no command
+ * streamers are executing MI_FORCE_WAKE while an engine reset is initiated.
+ */
+bool intel_engine_reset_needs_wa_22011802037(struct intel_gt *gt)
+{
+ if (GRAPHICS_VER(gt->i915) < 11)
+ return false;
+
+ if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0))
+ return true;
+
+ if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70))
+ return false;
+
+ return true;
+}
+
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
#include "selftest_reset.c"
#include "selftest_hangcheck.c"
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.h
b/drivers/gpu/drm/i915/gt/intel_reset.h
index 25c975b6e8fc..f615b30b81c5 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.h
+++ b/drivers/gpu/drm/i915/gt/intel_reset.h
@@ -78,4 +78,6 @@ void __intel_fini_wedge(struct intel_wedge_me *w);
bool intel_has_gpu_reset(const struct intel_gt *gt);
bool intel_has_reset_engine(const struct intel_gt *gt);
+bool intel_engine_reset_needs_wa_22011802037(struct intel_gt *gt);
+
#endif /* I915_RESET_H */
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 82a2ecc12b21..da967938fea5 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -288,9 +288,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
flags |= GUC_WA_DUAL_QUEUE;
/* Wa_22011802037: graphics version 11/12 */
- if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
- (GRAPHICS_VER(gt->i915) >= 11 &&
- GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 70)))
+ if (intel_engine_reset_needs_wa_22011802037(gt))
flags |= GUC_WA_PRE_PARSER;
/*
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index a0e3ef1c65d2..1bd5d8f7c40b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1658,9 +1658,7 @@ static void guc_engine_reset_prepare(struct
intel_engine_cs *engine)
* Wa_22011802037: In addition to
[Intel-gfx] [PATCH v5 3/9] drm/i915/xelpg: Call Xe_LPG workaround functions based on IP version
Although some of our Xe_LPG workarounds were already being applied based
on IP version correctly, others were matching on MTL as a base platform,
which is incorrect. Although MTL is the only platform right now that
uses Xe_LPG IP, this may not always be the case. If a future platform
re-uses this graphics IP, the same workarounds should be applied, even
if it isn't a "MTL" platform.
We were also incorrectly applying Xe_LPG workarounds/tuning to the
Xe_LPM+ media IP in one or two places; we should make sure that we don't
try to apply graphics workarounds to the media GT and vice versa where
they don't belong. A new helper macro IS_GT_IP_RANGE() is added to help
ensure this is handled properly -- it checks that the GT matches the IP
type being tested as well as the IP version falling in the proper range.
Note that many of the stepping-based workarounds are still incorrectly
checking for a MTL base platform; that will be remedied in a later
patch.
v2:
- Rework macro into a slightly more generic IS_GT_IP_RANGE() that can
be used for either GFX or MEDIA checks.
v3:
- Switch back to separate macros for gfx and media. (Jani)
- Move macro to intel_gt.h. (Andi)
Cc: Gustavo Sousa
Cc: Tvrtko Ursulin
Cc: Jani Nikula
Cc: Andi Shyti
Signed-off-by: Matt Roper
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_gt.h | 11 ++
drivers/gpu/drm/i915/gt/intel_workarounds.c | 38 +++--
2 files changed, 31 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h
b/drivers/gpu/drm/i915/gt/intel_gt.h
index 6c34547b58b5..15c25980411d 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -14,6 +14,17 @@
struct drm_i915_private;
struct drm_printer;
+/*
+ * Check that the GT is a graphics GT and has an IP version within the
+ * specified range (inclusive).
+ */
+#define IS_GFX_GT_IP_RANGE(gt, from, until) ( \
+ BUILD_BUG_ON_ZERO((from) < IP_VER(2, 0)) + \
+ BUILD_BUG_ON_ZERO((until) < (from)) + \
+ ((gt)->type != GT_MEDIA && \
+GRAPHICS_VER_FULL((gt)->i915) >= (from) && \
+GRAPHICS_VER_FULL((gt)->i915) <= (until)))
+
#define GT_TRACE(gt, fmt, ...) do {\
const struct intel_gt *gt__ __maybe_unused = (gt); \
GEM_TRACE("%s " fmt, dev_name(gt__->i915->drm.dev), \
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 804b38bc9482..3f0686dc3620 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -778,8 +778,8 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs
*engine,
wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE);
}
-static void mtl_ctx_gt_tuning_init(struct intel_engine_cs *engine,
- struct i915_wa_list *wal)
+static void xelpg_ctx_gt_tuning_init(struct intel_engine_cs *engine,
+struct i915_wa_list *wal)
{
struct drm_i915_private *i915 = engine->i915;
@@ -790,12 +790,12 @@ static void mtl_ctx_gt_tuning_init(struct intel_engine_cs
*engine,
wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);
}
-static void mtl_ctx_workarounds_init(struct intel_engine_cs *engine,
-struct i915_wa_list *wal)
+static void xelpg_ctx_workarounds_init(struct intel_engine_cs *engine,
+ struct i915_wa_list *wal)
{
struct drm_i915_private *i915 = engine->i915;
- mtl_ctx_gt_tuning_init(engine, wal);
+ xelpg_ctx_gt_tuning_init(engine, wal);
if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
@@ -904,8 +904,8 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
if (engine->class != RENDER_CLASS)
goto done;
- if (IS_METEORLAKE(i915))
- mtl_ctx_workarounds_init(engine, wal);
+ if (IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 71)))
+ xelpg_ctx_workarounds_init(engine, wal);
else if (IS_PONTEVECCHIO(i915))
; /* noop; none at this time */
else if (IS_DG2(i915))
@@ -1685,10 +1685,8 @@ xelpmp_gt_workarounds_init(struct intel_gt *gt, struct
i915_wa_list *wal)
*/
static void gt_tuning_settings(struct intel_gt *gt, struct i915_wa_list *wal)
{
- if (IS_METEORLAKE(gt->i915)) {
- if (gt->type != GT_MEDIA)
- wa_mcr_write_or(wal, XEHP_L3SCQREG7,
BLEND_FILL_CACHING_OPT_DIS);
-
+ if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71))) {
+ wa_mcr_write_or(wal, XEHP_L3SCQREG7,
BLEND_FILL_CACHING_OPT_DIS);
wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS);
}
@@ -1720,7 +1718,7 @@ gt_init_workarounds(struct intel_gt *gt,
[Intel-gfx] [PATCH v5 5/9] drm/i915: Eliminate IS_MTL_MEDIA_STEP
Stepping-specific media behavior shouldn't be tied to MTL as a platform,
but rather specifically to the Xe_LPM+ IP. Future non-MTL platforms may
re-use this IP and will need to follow the exact same logic and apply
the same workarounds. IS_MTL_MEDIA_STEP() is dropped in favor of
IS_MEDIA_GT_IP_STEP, which checks the media IP version associated with a
specific IP and also ensures that we're operating on the media GT, not
the primary GT.
v2:
- Switch to the IS_GT_IP_STEP macro.
v3:
- Switch back to long-form IS_MEDIA_GT_IP_STEP. (Jani)
v4:
- Build IS_MEDIA_GT_IP_STEP on top of IS_MEDIA_GT_IP_RANGE and
IS_MEDIA_STEP building blocks and name the parameters from/until
rather than begin/fixed.. (Jani)
v5:
- Tweak macro comment wording. (Gustavo)
- Add a check to catch NULL gt in IS_MEDIA_GT_IP_RANGE; this allows it
to be used safely on i915->media_gt, which may be NULL on some
platforms. (Gustavo)
Cc: Jani Nikula
Cc: Gustavo Sousa
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_gt.h | 32 +
drivers/gpu/drm/i915/gt/intel_rc6.c | 3 +--
drivers/gpu/drm/i915/i915_drv.h | 4
drivers/gpu/drm/i915/i915_perf.c| 15 --
4 files changed, 37 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h
b/drivers/gpu/drm/i915/gt/intel_gt.h
index 6e63b46682f7..239848bcb2a4 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -25,6 +25,20 @@ struct drm_printer;
GRAPHICS_VER_FULL((gt)->i915) >= (from) && \
GRAPHICS_VER_FULL((gt)->i915) <= (until)))
+/*
+ * Check that the GT is a media GT and has an IP version within the
+ * specified range (inclusive).
+ *
+ * Only usable on platforms with a standalone media design (i.e., IP version 13
+ * and higher).
+ */
+#define IS_MEDIA_GT_IP_RANGE(gt, from, until) ( \
+ BUILD_BUG_ON_ZERO((from) < IP_VER(13, 0)) + \
+ BUILD_BUG_ON_ZERO((until) < (from)) + \
+ ((gt) && (gt)->type == GT_MEDIA && \
+MEDIA_VER_FULL((gt)->i915) >= (from) && \
+MEDIA_VER_FULL((gt)->i915) <= (until)))
+
/*
* Check that the GT is a graphics GT with a specific IP version and has
* a stepping in the range [from, until). The lower stepping bound is
@@ -45,6 +59,24 @@ struct drm_printer;
(IS_GFX_GT_IP_RANGE((gt), (ipver), (ipver)) && \
IS_GRAPHICS_STEP((gt)->i915, (from), (until
+/*
+ * Check that the GT is a media GT with a specific IP version and has
+ * a stepping in the range [from, until). The lower stepping bound is
+ * inclusive, the upper bound is exclusive. The most common use-case of this
+ * macro is for checking bounds for workarounds, which usually have a stepping
+ * ("from") at which the hardware issue is first present and another stepping
+ * ("until") at which a hardware fix is present and the software workaround is
+ * no longer necessary. "STEP_FOREVER" can be passed as "until" for
+ * workarounds that have no upper stepping bound for the specified IP version.
+ *
+ * This macro may only be used to match on platforms that have a standalone
+ * media design (i.e., media version 13 or higher).
+ */
+#define IS_MEDIA_GT_IP_STEP(gt, ipver, from, until) ( \
+ BUILD_BUG_ON_ZERO((until) <= (from)) + \
+ (IS_MEDIA_GT_IP_RANGE((gt), (ipver), (ipver)) && \
+IS_MEDIA_STEP((gt)->i915, (from), (until
+
#define GT_TRACE(gt, fmt, ...) do {\
const struct intel_gt *gt__ __maybe_unused = (gt); \
GEM_TRACE("%s " fmt, dev_name(gt__->i915->drm.dev), \
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c
b/drivers/gpu/drm/i915/gt/intel_rc6.c
index 90933fb8cb97..86df42cb5823 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -524,8 +524,7 @@ static bool rc6_supported(struct intel_rc6 *rc6)
return false;
}
- if (IS_MTL_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
- gt->type == GT_MEDIA) {
+ if (IS_MEDIA_GT_IP_STEP(gt, IP_VER(13, 0), STEP_A0, STEP_B0)) {
drm_notice(>drm,
"Media RC6 disabled on A step\n");
return false;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3bb216d55c3e..b0894e7de403 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -662,10 +662,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
(IS_METEORLAKE(__i915) && \
IS_DISPLAY_STEP(__i915, since, until))
-#define IS_MTL_MEDIA_STEP(__i915, since, until) \
- (IS_METEORLAKE(__i915) && \
-IS_MEDIA_STEP(__i915, since, until))
-
#define IS_PVC_BD_STEP(__i915, since, until) \
(IS_PONTEVECCHIO(__i915) && \
IS_BASEDIE_STEP(__i915, since, until))
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index dfe7eff7d1a1..605e6e4fedf1
[Intel-gfx] [PATCH v5 0/9] Reduce MTL-specific platform checks
Starting with MTL, the hardware moved to a disaggregated IP design where graphics, media, and display are supposed to be treated independently of the base platform that they're incorporated into. For driver logic that is conditional on these IPs, the code should be checking the IP versions (as read from the GMD_ID registers) rather than trying to match on a specific platform (e.g., MTL). It's possible that these IPs could show up again, without changes, on future non-MTL platforms, or that the current MTL platform could be extended to include new IP versions in future SKUs or refreshes; making sure our driver's conditions are handled appropriately future-proofs for both of these cases. Going forward, conditions like IS_METEORLAKE should be very rare in the driver; in most places our logic will be conditional upon the IP rather than the base platform. v2: - Rework macros slightly; new IP range and stepping range macros can be used with both GFX or MEDIA rather than needing separate macros for each IP. (Tvrtko, Gustavo) - Fix a > that should have been a >=. (Gustavo) - Split non-inheritance of media workarounds by future platforms into its own patch. (Gustavo) - Extra documentation comments v3: - Switch back to separate long-form gfx and media macros with no macro pasting. (Jani) - Move GT-specific macros from intel_drv.h to intel_gt.h. (Andi) - Replace two more IS_METEORLAKE() conditions with IP version checks. v4: - Build IS_*_IP_STEP macros on top of existing range check and stepping check building blocks. (Jani) - Fix parameters in comment examples. v5: - Rebase on top of latest drm-tip changes. - Add NULL check to IS_MEDIA_GT_IP_RANGE() so that it can be used safely on i915->media_gt, even on platforms where that pointer may be NULL. (Gustavo) - Leave the GuC/HuC compatibility check as MTL-specific since that seems to truly be a platform rather than IP limitation. (Gustavo) - Tweak some macro comment documentation. (Gustavo) Cc: Tvrtko Ursulin Cc: Dnyaneshwar Bhadane Cc: Gustavo Sousa Cc: Jani Nikula Cc: Andi Shyti Matt Roper (9): drm/i915: Consolidate condition for Wa_22011802037 drm/i915/xelpmp: Don't assume workarounds extend to future platforms drm/i915/xelpg: Call Xe_LPG workaround functions based on IP version drm/i915: Eliminate IS_MTL_GRAPHICS_STEP drm/i915: Eliminate IS_MTL_MEDIA_STEP drm/i915: Eliminate IS_MTL_DISPLAY_STEP drm/i915/mtl: Eliminate subplatforms drm/i915/display: Eliminate IS_METEORLAKE checks drm/i915: Replace several IS_METEORLAKE with proper IP version checks drivers/gpu/drm/i915/display/intel_cdclk.c| 4 +- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 2 +- drivers/gpu/drm/i915/display/intel_display.c | 2 +- .../drm/i915/display/intel_display_device.h | 25 ++ drivers/gpu/drm/i915/display/intel_dmc.c | 2 +- drivers/gpu/drm/i915/display/intel_fbc.c | 3 +- drivers/gpu/drm/i915/display/intel_pmdemand.c | 2 +- drivers/gpu/drm/i915/display/intel_psr.c | 10 +-- .../drm/i915/display/skl_universal_plane.c| 5 +- drivers/gpu/drm/i915/gem/i915_gem_create.c| 4 +- drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 11 +-- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 +- drivers/gpu/drm/i915/gt/intel_engine_pm.c | 2 +- .../drm/i915/gt/intel_execlists_submission.c | 4 +- drivers/gpu/drm/i915/gt/intel_gt.h| 63 + drivers/gpu/drm/i915/gt/intel_gt_mcr.c| 7 +- drivers/gpu/drm/i915/gt/intel_lrc.c | 4 +- drivers/gpu/drm/i915/gt/intel_mocs.c | 2 +- drivers/gpu/drm/i915/gt/intel_rc6.c | 5 +- drivers/gpu/drm/i915/gt/intel_reset.c | 20 - drivers/gpu/drm/i915/gt/intel_reset.h | 2 + drivers/gpu/drm/i915/gt/intel_rps.c | 2 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 88 ++- drivers/gpu/drm/i915/gt/uc/intel_guc.c| 6 +- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 6 +- drivers/gpu/drm/i915/i915_debugfs.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 18 +--- drivers/gpu/drm/i915/i915_perf.c | 26 ++ drivers/gpu/drm/i915/intel_device_info.c | 14 --- drivers/gpu/drm/i915/intel_device_info.h | 4 - include/drm/i915_pciids.h | 11 +-- 31 files changed, 210 insertions(+), 150 deletions(-) -- 2.41.0
Re: [Intel-gfx] [PATCH 1/3] drm/buddy: Fix contiguous memory allocation issues
Hi,
On 21/08/2023 11:14, Arunpravin Paneer Selvam wrote:
The way now contiguous requests are implemented such that
the size rounded up to power of 2 and the corresponding order
block picked from the freelist.
In addition to the older method, the new method will rounddown
the size to power of 2 and the corresponding order block picked
from the freelist. And for the remaining size we traverse the
tree and try to allocate either from the freelist block's buddy
or from the peer block. If the remaining size from peer/buddy
block is not free, we pick the next freelist block and repeat
the same method.
Moved contiguous/alignment size computation part and trim
function to the drm buddy manager.
I think we should also mention somewhere what issue this is trying to
solve. IIUC the roundup_power_of_two() might in some cases trigger
-ENOSPC even though there might be enough free space, and so to help
with that we introduce a try harder mechanism.
Signed-off-by: Arunpravin Paneer Selvam
---
drivers/gpu/drm/drm_buddy.c | 253 ++--
include/drm/drm_buddy.h | 6 +-
2 files changed, 248 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/drm_buddy.c b/drivers/gpu/drm/drm_buddy.c
index 7098f125b54a..220f60c08a03 100644
--- a/drivers/gpu/drm/drm_buddy.c
+++ b/drivers/gpu/drm/drm_buddy.c
@@ -569,6 +569,197 @@ static int __drm_buddy_alloc_range(struct drm_buddy *mm,
return __alloc_range(mm, , start, size, blocks);
}
+static int __alloc_contiguous_block_from_buddy(struct drm_buddy *mm,
+ u64 size,
+ u64 min_block_size,
+ struct drm_buddy_block *block,
+ struct list_head *blocks)
+{
+ struct drm_buddy_block *buddy, *parent = NULL;
+ u64 start, offset = 0;
+ LIST_HEAD(dfs);
+ int err;
+
+ if (!block)
+ return -EINVAL;
+
+ buddy = __get_buddy(block);
+ if (!buddy)
+ return -ENOSPC;
+
+ if (drm_buddy_block_is_allocated(buddy))
+ return -ENOSPC;
+
+ parent = block->parent;
+ if (!parent)
+ return -ENOSPC;
+
+ if (block->parent->right == block) {
+ u64 remaining;
+
+ /* Compute the leftover size for allocation */
+ remaining = max((size - drm_buddy_block_size(mm, buddy)),
+ min_block_size);
+ if (!IS_ALIGNED(remaining, min_block_size))
+ remaining = round_up(remaining, min_block_size);
+
+ /* Check if remaining size is greater than buddy block size */
+ if (drm_buddy_block_size(mm, buddy) < remaining)
+ return -ENOSPC;
+
+ offset = drm_buddy_block_size(mm, buddy) - remaining;
+ }
+
+ list_add(>tmp_link, );
+ start = drm_buddy_block_offset(parent) + offset;
+
+ err = __alloc_range(mm, , start, size, blocks);
+ if (err)
+ return -ENOSPC;
+
+ return 0;
+}
+
+static int __alloc_contiguous_block_from_peer(struct drm_buddy *mm,
+ u64 size,
+ u64 min_block_size,
+ struct drm_buddy_block *block,
+ struct list_head *blocks)
+{
+ struct drm_buddy_block *first, *peer, *tmp;
+ struct drm_buddy_block *parent = NULL;
+ u64 start, offset = 0;
+ unsigned int order;
+ LIST_HEAD(dfs);
+ int err;
+
+ if (!block)
+ return -EINVAL;
+
+ order = drm_buddy_block_order(block);
+ /* Add freelist block to dfs list */
+ list_add(>tmp_link, );
+
+ tmp = block;
+ parent = block->parent;
+ while (parent) {
+ if (block->parent->left == block) {
+ if (parent->left != tmp) {
+ peer = parent->left;
+ break;
+ }
+ } else {
+ if (parent->right != tmp) {
+ peer = parent->right;
+ break;
+ }
+ }
+
+ tmp = parent;
+ parent = tmp->parent;
+ }
+
+ if (!parent)
+ return -ENOSPC;
+
+ do {
+ if (drm_buddy_block_is_allocated(peer))
+ return -ENOSPC;
+ /* Exit loop if peer block order is equal to block order */
+ if (drm_buddy_block_order(peer) == order)
+ break;
+
+ if (drm_buddy_block_is_split(peer)) {
+ /* Traverse down to the block order level */
+ if (block->parent->left ==
Re: [Intel-gfx] [PATCH v3 0/4] drm/i915/tc: some clean-ups in max lane count handling code
0/4] drm/i915/tc: some clean-ups in max > lane count handling code > > On Fri, Jul 21, 2023 at 02:11:17PM +0300, Luca Coelho wrote: > >Hi, > > > >Here are four patches with some clean-ups in the code that handles the > >max lane count of Type-C connections. > > > >This is done mostly in preparation for a new way to read the pin > >assignments and lane count in future devices. > > > >In v2: > > * Fix some rebasing damage. > > > >In v3: > > * Fixed "assigment" typo, as reported by checkpatch. > > > >Please review. > > what happened to this series? It seems only the last patch is not reviewed. > Are you going to submit a rebased version? > So I had some review comments on patch 3 was waiting for Luciano to upstream the latest changes then review the 4th patch Regards, Suraj Kandpal > > Lucas De Marchi
Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/display: Remove unused POWER_DOMAIN_MODESET
On Sat, Aug 19, 2023 at 03:17:34AM -, Patchwork wrote: > == Series Details == > > Series: drm/i915/display: Remove unused POWER_DOMAIN_MODESET > URL : https://patchwork.freedesktop.org/series/122593/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_13534_full -> Patchwork_122593v1_full > > > Summary > --- > > **FAILURE** > > Serious unknown changes coming with Patchwork_122593v1_full absolutely need > to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_122593v1_full, please notify your bug team to allow > them > to document this new failure mode, which will reduce false positives in CI. > > > > Participating hosts (9 -> 9) > -- > > No changes in participating hosts > > Possible new issues > --- > > Here are the unknown changes that may have been introduced in > Patchwork_122593v1_full: > > ### IGT changes ### > > Possible regressions > > * igt@kms_plane_lowres@tiling-x@pipe-a-hdmi-a-1: > - shard-rkl: NOTRUN -> [ABORT][1] >[1]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122593v1/shard-rkl-7/igt@kms_plane_lowres@tilin...@pipe-a-hdmi-a-1.html https://gitlab.freedesktop.org/drm/intel/-/issues/8875 > > > Warnings > > * igt@kms_psr@psr2_cursor_blt: > - shard-mtlp: [DMESG-WARN][2] ([i915#2017]) -> [DMESG-WARN][3] >[2]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13534/shard-mtlp-1/igt@kms_psr@psr2_cursor_blt.html >[3]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122593v1/shard-mtlp-6/igt@kms_psr@psr2_cursor_blt.html https://gitlab.freedesktop.org/drm/intel/-/issues/9157 Applied to drm-intel-next. Thanks for the patch. Matt > > > Known issues > > > Here are the changes found in Patchwork_122593v1_full that come from known > issues: > > ### IGT changes ### > > Issues hit > > * igt@api_intel_bb@object-reloc-purge-cache: > - shard-mtlp: NOTRUN -> [SKIP][4] ([i915#8411]) >[4]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122593v1/shard-mtlp-5/igt@api_intel...@object-reloc-purge-cache.html > > * igt@device_reset@cold-reset-bound: > - shard-mtlp: NOTRUN -> [SKIP][5] ([i915#7701]) >[5]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122593v1/shard-mtlp-5/igt@device_re...@cold-reset-bound.html > > * igt@drm_fdinfo@all-busy-idle-check-all: > - shard-dg2: NOTRUN -> [SKIP][6] ([i915#8414]) >[6]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122593v1/shard-dg2-11/igt@drm_fdi...@all-busy-idle-check-all.html > > * igt@drm_fdinfo@busy-check-all@ccs0: > - shard-mtlp: NOTRUN -> [SKIP][7] ([i915#8414]) +5 similar issues >[7]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122593v1/shard-mtlp-5/igt@drm_fdinfo@busy-check-...@ccs0.html > > * igt@drm_fdinfo@most-busy-check-all@rcs0: > - shard-rkl: [PASS][8] -> [FAIL][9] ([i915#7742]) >[8]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13534/shard-rkl-4/igt@drm_fdinfo@most-busy-check-...@rcs0.html >[9]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122593v1/shard-rkl-2/igt@drm_fdinfo@most-busy-check-...@rcs0.html > > * igt@feature_discovery@display-4x: > - shard-dg2: NOTRUN -> [SKIP][10] ([i915#1839]) >[10]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122593v1/shard-dg2-11/igt@feature_discov...@display-4x.html > > * igt@gem_ctx_isolation@preservation-s3@rcs0: > - shard-snb: NOTRUN -> [DMESG-WARN][11] ([i915#8841]) +3 similar > issues >[11]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122593v1/shard-snb7/igt@gem_ctx_isolation@preservation...@rcs0.html > > * igt@gem_ctx_persistence@processes: > - shard-snb: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#1099]) >[12]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122593v1/shard-snb6/igt@gem_ctx_persiste...@processes.html > > * igt@gem_eio@hibernate: > - shard-tglu: [PASS][13] -> [ABORT][14] ([i915#7975] / > [i915#8213] / [i915#8398]) >[13]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13534/shard-tglu-9/igt@gem_...@hibernate.html >[14]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122593v1/shard-tglu-10/igt@gem_...@hibernate.html > > * igt@gem_eio@reset-stress: > - shard-snb: NOTRUN -> [FAIL][15] ([i915#8898]) >[15]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122593v1/shard-snb6/igt@gem_...@reset-stress.html > > * igt@gem_exec_balancer@sliced: > - shard-mtlp: NOTRUN -> [SKIP][16] ([i915#4812]) >[16]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122593v1/shard-mtlp-5/igt@gem_exec_balan...@sliced.html > > * igt@gem_exec_capture@pi@ccs0: >
Re: [Intel-gfx] [PATCH] gpu: drm: i915: fix documentation style
On Mon, 21 Aug 2023, "Ricardo B. Marliere" wrote:
> This patch fixes the following sphinx warnings in the htmldocs make target:
>
> Documentation/gpu/i915:546: ./drivers/gpu/drm/i915/gt/uc/intel_huc.c:29:
> ERROR: Unexpected indentation.
> Documentation/gpu/i915:546: ./drivers/gpu/drm/i915/gt/uc/intel_huc.c:30:
> WARNING: Block quote ends without a blank line; unexpected unindent.
> Documentation/gpu/i915:546: ./drivers/gpu/drm/i915/gt/uc/intel_huc.c:35:
> WARNING: Bullet list ends without a blank line; unexpected unindent.
>
> Signed-off-by: Ricardo B. Marliere
Already fixed by commit 175b036472f6 ("drm/i915: fix Sphinx indentation
warning") in drm-next.
BR,
Jani.
> ---
> drivers/gpu/drm/i915/gt/uc/intel_huc.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> index ddd146265beb..fa70defcb5b2 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> @@ -26,6 +26,7 @@
> * The kernel driver is only responsible for loading the HuC firmware and
> * triggering its security authentication. This is done differently depending
> * on the platform:
> + *
> * - older platforms (from Gen9 to most Gen12s): the load is performed via
> DMA
> * and the authentication via GuC
> * - DG2: load and authentication are both performed via GSC.
> @@ -33,6 +34,7 @@
> * not-DG2 older platforms), while the authentication is done in 2-steps,
> * a first auth for clear-media workloads via GuC and a second one for all
> * workloads via GSC.
> + *
> * On platforms where the GuC does the authentication, to correctly do so the
> * HuC binary must be loaded before the GuC one.
> * Loading the HuC is optional; however, not using the HuC might negatively
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH 3/3] drm/i915/display: Add wrapper to Compute SAD
Hi @Jani Nikula
Thanks for reviewing patch series.
> -Original Message-
> From: Jani Nikula
> Sent: 18 August 2023 14:08
> To: Golani, Mitulkumar Ajitkumar
> ; intel-gfx@lists.freedesktop.org
> Cc: jyri.sa...@linux.intel.com
> Subject: Re: [Intel-gfx] [PATCH 3/3] drm/i915/display: Add wrapper to
> Compute SAD
>
> On Thu, 17 Aug 2023, Mitul Golani
> wrote:
> > Compute SADs that takes into account the supported rate and channel
> > based on the capabilities of the audio source.
> > This wrapper function should encapsulate the logic for determining the
> > supported rate and channel and should return a set of SADs that are
> > compatible with the source.
> >
> > --v1:
> > - call intel_audio_compute_eld in this commit as it is defined here
> >
> > --v2:
> > - Handle case when max frequency is less than 32k.
> > - remove drm prefix.
> > - name change for parse_sad to eld_to_sad.
> >
> > --v3:
> > - Use signed int wherever required.
> > - add debug trace when channel is limited.
> >
> > --v4:
> > - remove inline from eld_to_sad.
> > - declare index outside of for loop with int type.
> > - Correct mask value calculation.
> > - remove drm_err, instead just return if eld parsing failed.
> > - remove unncessary typecast
> > - reduce indentation while parsing sad
> > - use intel_audio_compute_eld as static and call bandwidth calculation
> > just before that.
> >
> > --v9:
> > - Handling the case when, sink supported channel is less than max
> > supported. In that case, rate needs to be calibrate in accordance with
> > available bandwidth.
> >
> > Signed-off-by: Mitul Golani
> > ---
> > drivers/gpu/drm/i915/display/intel_audio.c | 107
> > -
> > 1 file changed, 106 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
> > b/drivers/gpu/drm/i915/display/intel_audio.c
> > index 79377e33a59b..c90ac2608eef 100644
> > --- a/drivers/gpu/drm/i915/display/intel_audio.c
> > +++ b/drivers/gpu/drm/i915/display/intel_audio.c
> > @@ -806,6 +806,111 @@ static void calc_audio_config_params(struct
> intel_crtc_state *pipe_config)
> > pipe_config->audio.max_channel_count = 0; }
> >
>
> This was added in previous patch:
>
> +static void calc_audio_config_params(struct intel_crtc_state *pipe_config)
> +{
> +struct drm_display_mode *adjusted_mode = _config-
> >hw.adjusted_mode;
> +int channel_count;
> +int index, rate[] = { 192000, 176000, 96000, 88000, 48000, 44100,
> 32000 };
> +int audio_req_bandwidth, available_blank_bandwidth, vblank,
> hblank;
> +
> +hblank = adjusted_mode->htotal - adjusted_mode->hdisplay;
> +vblank = adjusted_mode->vtotal - adjusted_mode->vdisplay;
> +available_blank_bandwidth = hblank * vblank *
> +drm_mode_vrefresh(adjusted_mode) *
> pipe_config->pipe_bpp;
> +for (channel_count = MAX_CHANNEL_COUNT; channel_count > 0;
> channel_count--) {
> +for (index = 0; index < ARRAY_SIZE(rate); index++) {
> +audio_req_bandwidth =
> calc_audio_bw(channel_count,
> +rate[index]);
> +if (audio_req_bandwidth <
> available_blank_bandwidth) {
> +pipe_config->audio.max_rate = rate[index];
> +pipe_config->audio.max_channel_count =
> channel_count;
> +return;
> +}
> +}
> +}
> +
> +pipe_config->audio.max_rate = 0;
> +pipe_config->audio.max_channel_count = 0;
> +}
>
> And this here:
Thanks I have removed duplicated code for calibration and calculation,
and merged them to one to avoid redundancy.
>
> > +static void calibrate_audio_config_params(struct intel_crtc_state
> > +*pipe_config, int channel) {
> > + struct drm_display_mode *adjusted_mode = _config-
> >hw.adjusted_mode;
> > + int channel_count;
> > + int index, rate[] = { 192000, 176000, 96000, 88000, 48000, 44100,
> 32000 };
> > + int audio_req_bandwidth, available_blank_bandwidth, vblank,
> hblank;
> > +
> > + hblank = adjusted_mode->htotal - adjusted_mode->hdisplay;
> > + vblank = adjusted_mode->vtotal - adjusted_mode->vdisplay;
> > + available_blank_bandwidth = hblank * vblank *
> > + drm_mode_vrefresh(adjusted_mode) *
> pipe_config->pipe_bpp;
> > +
> > + for (index = 0; index < ARRAY_SIZE(rate); index++) {
> > + audio_req_bandwidth = calc_audio_bw(channel_count,
> > + rate[index]);
> > + if (audio_req_bandwidth < available_blank_bandwidth) {
> > + pipe_config->audio.max_rate = rate[index];
> > + pipe_config->audio.max_channel_count =
> channel_count;
> > + return;
> > + }
> > + }
> > +
> > + pipe_config->audio.max_rate = 0;
> > + pipe_config->audio.max_channel_count = 0; }
>
> This kind of
[Intel-gfx] [PATCH 3/3] drm/i915/display: Configure and initialize HDMI audio capabilities
Initialize the source audio capabilities in the crtc_state property,
setting them to their maximum supported values for max_channel and
max_rate. This initialization enables the calculation of audio source
capabilities concerning the available mode bandwidth. These
capabilities encompass parameters such as supported rate and
channel configurations.
Additionally, introduces a wrapper function for computing
Short Audio Descriptors (SADs). The wrapper function incorporates
logic for determining supported rates and channels according to the
capabilities of the audio source. It returns a set of SADs that are
compatible with the audio source's capabilities.
--v1:
- Refactor max_channel and max_rate to this commit as it is being
initialised here
- Remove call for intel_audio_compute_eld to avoid any regression while
merge. instead call it in different commit when it is defined.
- Use int instead of unsigned int for max_channel and max_frequecy
- Update commit message and header
--v2:
- Use signed instead of unsigned variables.
- Avoid using magic numbers and give them proper name.
--v3:
- Move defines to intel_audio.c.
- use consistent naming convention for rate and channel.
- declare num_of_channel and aud_rate separately.
- Declare index value outside of for loop.
- Move Bandwidth calculation to intel_Audio.c as it is common for both
DP and HDMI. Also use static.
--v10:
- Merged patch 2 and 3 to deduplicate function calls.
- Instead using Calibrate and calculated functions separately,
removed code duplication and merged functions.[Nikula, Jani]
- Remove magic value for SAD Channel mask. [Nikula, Jani]
- Corrected rate values based on HDMI Spec [Nikula, Jani]
- Update drm function to extract SAD from ELD [Nikula, Jani]
Signed-off-by: Mitul Golani
---
drivers/gpu/drm/i915/display/intel_audio.c| 127 ++
.../drm/i915/display/intel_display_types.h| 6 +
2 files changed, 133 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
b/drivers/gpu/drm/i915/display/intel_audio.c
index e20ffc8e9654..2584096d80a4 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -64,6 +64,10 @@
* struct _audio_component_audio_ops @audio_ops is called from i915
driver.
*/
+#define AUDIO_SAMPLE_CONTAINER_SIZE32
+#define MAX_CHANNEL_COUNT 8
+#define ELD_SAD_CHANNELS_MASK 0x7
+
struct intel_audio_funcs {
void (*audio_codec_enable)(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
@@ -770,6 +774,127 @@ void intel_audio_sdp_split_update(struct intel_encoder
*encoder,
crtc_state->sdp_split_enable ?
AUD_ENABLE_SDP_SPLIT : 0);
}
+static int sad_to_channels(const u8 *sad)
+{
+ return 1 + (sad[0] & 0x7);
+}
+
+static int calc_audio_bw(int channel_count, int rate)
+{
+ int bandwidth = channel_count * rate * AUDIO_SAMPLE_CONTAINER_SIZE;
+ return bandwidth;
+}
+
+static void calc_and_calibrate_audio_config_params(struct intel_crtc_state
*pipe_config,
+ int channel, bool
calibration_required)
+{
+ struct drm_display_mode *adjusted_mode = _config->hw.adjusted_mode;
+ int channel_count;
+ int index, rate[] = { 192000, 176400, 96000, 88200, 48000, 44100, 32000
};
+ int audio_req_bandwidth, available_blank_bandwidth, vblank, hblank;
+
+ hblank = adjusted_mode->htotal - adjusted_mode->hdisplay;
+ vblank = adjusted_mode->vtotal - adjusted_mode->vdisplay;
+ available_blank_bandwidth = hblank * vblank *
+ drm_mode_vrefresh(adjusted_mode) * pipe_config->pipe_bpp;
+
+ /*
+* Expected calibration of channels and respective rates,
+* based on MAX_CHANNEL_COUNT. First calculate channel and
+* rate based on Maximum that source can compute, letter
+* with respect to sink's maximum channel capacity, calibrate
+* supportive rates.
+*/
+ if (calibration_required) {
+ channel_count = channel;
+ for (index = 0; index < ARRAY_SIZE(rate); index++) {
+ audio_req_bandwidth = calc_audio_bw(channel_count,
+ rate[index]);
+ if (audio_req_bandwidth < available_blank_bandwidth) {
+ pipe_config->audio.max_rate = rate[index];
+ pipe_config->audio.max_channel_count =
channel_count;
+ return;
+ }
+ }
+ } else {
+ for (channel_count = channel; channel_count > 0;
channel_count--) {
+ for (index = 0; index < ARRAY_SIZE(rate); index++) {
+ audio_req_bandwidth =
calc_audio_bw(channel_count, rate[index]);
+ if
[Intel-gfx] [PATCH 1/3] drm/i915: Add has_audio to separate audio parameter in crtc_state
To enhance the relationship between the has_audio and the source
audio parameter, create a separate crtc_state audio property and
add the has_audio parameter into it. Additionally, update the
access of the has_audio parameter from the crtc_state pointer as
it is wrapped under the audio. These modifications establish
a more cohesive structure and improve the accessibility and
organization of the audio-related parameters within the codebase.
--v1:
- add audio instead of audio_config in crtc_state
- add only has_audio then update related parameter access
- refactor other member to different commit where it is being used
- update commit message and header
Signed-off-by: Mitul Golani
Reviewed-by: Jani Nikula
---
drivers/gpu/drm/i915/display/g4x_dp.c| 4 ++--
drivers/gpu/drm/i915/display/g4x_hdmi.c | 16
drivers/gpu/drm/i915/display/intel_audio.c | 6 +++---
drivers/gpu/drm/i915/display/intel_cdclk.c | 6 +++---
.../gpu/drm/i915/display/intel_crtc_state_dump.c | 4 ++--
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
.../gpu/drm/i915/display/intel_display_types.h | 6 +++---
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
drivers/gpu/drm/i915/display/intel_hdmi.c| 2 +-
drivers/gpu/drm/i915/display/intel_sdvo.c| 10 +-
12 files changed, 32 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c
b/drivers/gpu/drm/i915/display/g4x_dp.c
index 4c7187f7913e..59e66cdc4553 100644
--- a/drivers/gpu/drm/i915/display/g4x_dp.c
+++ b/drivers/gpu/drm/i915/display/g4x_dp.c
@@ -345,7 +345,7 @@ static void intel_dp_get_config(struct intel_encoder
*encoder,
tmp = intel_de_read(dev_priv, intel_dp->output_reg);
- pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
+ pipe_config->audio.has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port !=
PORT_A;
if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
u32 trans_dp = intel_de_read(dev_priv,
@@ -625,7 +625,7 @@ static void intel_dp_enable_port(struct intel_dp *intel_dp,
* fail when the power sequencer is freshly used for this port.
*/
intel_dp->DP |= DP_PORT_EN;
- if (crtc_state->has_audio)
+ if (crtc_state->audio.has_audio)
intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.c
b/drivers/gpu/drm/i915/display/g4x_hdmi.c
index 634b14116d9d..8a3b50a59ea8 100644
--- a/drivers/gpu/drm/i915/display/g4x_hdmi.c
+++ b/drivers/gpu/drm/i915/display/g4x_hdmi.c
@@ -178,7 +178,7 @@ static void intel_hdmi_get_config(struct intel_encoder
*encoder,
pipe_config->has_infoframe = true;
if (tmp & HDMI_AUDIO_ENABLE)
- pipe_config->has_audio = true;
+ pipe_config->audio.has_audio = true;
if (!HAS_PCH_SPLIT(dev_priv) &&
tmp & HDMI_COLOR_RANGE_16_235)
@@ -224,7 +224,7 @@ static void g4x_hdmi_enable_port(struct intel_encoder
*encoder,
temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
temp |= SDVO_ENABLE;
- if (pipe_config->has_audio)
+ if (pipe_config->audio.has_audio)
temp |= HDMI_AUDIO_ENABLE;
intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
@@ -240,7 +240,7 @@ static void g4x_enable_hdmi(struct intel_atomic_state
*state,
g4x_hdmi_enable_port(encoder, pipe_config);
- drm_WARN_ON(_priv->drm, pipe_config->has_audio &&
+ drm_WARN_ON(_priv->drm, pipe_config->audio.has_audio &&
!pipe_config->has_hdmi_sink);
intel_audio_codec_enable(encoder, pipe_config, conn_state);
}
@@ -258,7 +258,7 @@ static void ibx_enable_hdmi(struct intel_atomic_state
*state,
temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
temp |= SDVO_ENABLE;
- if (pipe_config->has_audio)
+ if (pipe_config->audio.has_audio)
temp |= HDMI_AUDIO_ENABLE;
/*
@@ -293,7 +293,7 @@ static void ibx_enable_hdmi(struct intel_atomic_state
*state,
intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
}
- drm_WARN_ON(_priv->drm, pipe_config->has_audio &&
+ drm_WARN_ON(_priv->drm, pipe_config->audio.has_audio &&
!pipe_config->has_hdmi_sink);
intel_audio_codec_enable(encoder, pipe_config, conn_state);
}
@@ -313,7 +313,7 @@ static void cpt_enable_hdmi(struct intel_atomic_state
*state,
temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
temp |= SDVO_ENABLE;
- if (pipe_config->has_audio)
+ if (pipe_config->audio.has_audio)
temp |= HDMI_AUDIO_ENABLE;
/*
@@ -348,7 +348,7 @@ static void cpt_enable_hdmi(struct
[Intel-gfx] [PATCH 2/3] drm: Add Wrapper Functions for ELD SAD Extraction
Add wrapper functions to facilitate extracting Short Audio
Descriptor (SAD) information from EDID-Like Data (ELD) pointers
with different constness requirements.
1. `drm_eld_sad`: This function returns a constant `uint8_t`
pointer and wraps the main extraction function, allowing access
to SAD information while maintaining const correctness.
2. `drm_extract_sad_from_eld`: This function returns a mutable
`uint8_t` pointer and implements the core logic for extracting
SAD from the provided ELD pointer. It performs version and
maximum channel checks to ensure proper extraction.
These wrapper functions provide flexibility to the codebase,
allowing users to access SAD information while adhering to
const correctness when needed and modifying the pointer when
required.
Signed-off-by: Mitul Golani
---
include/drm/drm_edid.h | 15 ++-
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h
index 48e93f909ef6..626bc0d542eb 100644
--- a/include/drm/drm_edid.h
+++ b/include/drm/drm_edid.h
@@ -418,11 +418,7 @@ static inline int drm_eld_mnl(const uint8_t *eld)
return (eld[DRM_ELD_CEA_EDID_VER_MNL] & DRM_ELD_MNL_MASK) >>
DRM_ELD_MNL_SHIFT;
}
-/**
- * drm_eld_sad - Get ELD SAD structures.
- * @eld: pointer to an eld memory structure with sad_count set
- */
-static inline const uint8_t *drm_eld_sad(const uint8_t *eld)
+static uint8_t *drm_extract_sad_from_eld(uint8_t *eld)
{
unsigned int ver, mnl;
@@ -437,6 +433,15 @@ static inline const uint8_t *drm_eld_sad(const uint8_t
*eld)
return eld + DRM_ELD_CEA_SAD(mnl, 0);
}
+/**
+ * drm_eld_sad - Get ELD SAD structures.
+ * @eld: pointer to an eld memory structure with sad_count set
+ */
+static inline const uint8_t *drm_eld_sad(const uint8_t *eld)
+{
+ return drm_extract_sad_from_eld((uint8_t *)eld);
+}
+
/**
* drm_eld_sad_count - Get ELD SAD count.
* @eld: pointer to an eld memory structure with sad_count set
--
2.25.1
[Intel-gfx] [PATCH 0/3] Get optimal audio frequency and channels
Currently we do not check if there is enough bandwidth for audio, and what channels and freq it can really support. Also sometimes there can be HW constraints e.g. GLK where audio channels supported are only 2. https://patchwork.freedesktop.org/series/107647/ Obtain the optimal audio rate and channel based on available display timing constraints. This can be achieved by: - Retrieve the supported channel and rate information from SADs - Adding audio-related config parameters in the CRTC state, such as audio support, rate, and channel. - Initializing the audio config parameters with the maximum supported rate and channel by the audio source. - Computing the SADs based on the audio source's capabilities. Signed-off-by: Mitul Golani Mitul Golani (3): drm/i915: Add has_audio to separate audio parameter in crtc_state drm: Add Wrapper Functions for ELD SAD Extraction drm/i915/display: Configure and initialize HDMI audio capabilities drivers/gpu/drm/i915/display/g4x_dp.c | 4 +- drivers/gpu/drm/i915/display/g4x_hdmi.c | 16 +-- drivers/gpu/drm/i915/display/intel_audio.c| 133 +- drivers/gpu/drm/i915/display/intel_cdclk.c| 6 +- .../drm/i915/display/intel_crtc_state_dump.c | 4 +- drivers/gpu/drm/i915/display/intel_ddi.c | 2 +- drivers/gpu/drm/i915/display/intel_display.c | 4 +- .../drm/i915/display/intel_display_types.h| 12 +- drivers/gpu/drm/i915/display/intel_dp.c | 2 +- drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +- drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +- drivers/gpu/drm/i915/display/intel_sdvo.c | 10 +- include/drm/drm_edid.h| 15 +- 13 files changed, 175 insertions(+), 37 deletions(-) -- 2.25.1
[Intel-gfx] [PATCH] drm/i915: mark requests for GuC virtual engines to avoid use-after-free
References to i915_requests may be trapped by userspace inside a
sync_file or dmabuf (dma-resv) and held indefinitely across different
proceses. To counter-act the memory leaks, we try to not to keep
references from the request past their completion.
On the other side on fence release we need to know if rq->engine
is valid and points to hw engine (true for non-virtual requests).
To make it possible extra bit has been added to rq->execution_mask,
for marking virtual engines.
Fixes: bcb9aa45d5a0 ("Revert "drm/i915: Hold reference to intel_context over
life of i915_request"")
Signed-off-by: Chris Wilson
Signed-off-by: Andrzej Hajda
Reviewed-by: Andi Shyti
---
Hi all,
This is squash of revert of fixed patch with Chris fix for internal
branch with expanded description.
I wondered if we should mark requests for non-guc virtual engines.
I have decided to not as for them rq->engine points to real engine at rq
release,
so we can reuse this rq safely.
Regards
Andrzej
---
drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 +
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 3 +++
drivers/gpu/drm/i915/i915_request.c | 7 ++-
3 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index e99a6fa03d4539..a7e6775980043c 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -58,6 +58,7 @@ struct i915_perf_group;
typedef u32 intel_engine_mask_t;
#define ALL_ENGINES ((intel_engine_mask_t)~0ul)
+#define VIRTUAL_ENGINES BIT(BITS_PER_TYPE(intel_engine_mask_t) - 1)
struct intel_hw_status_page {
struct list_head timelines;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index a0e3ef1c65d246..b5b7f2fe8c78e4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -5470,6 +5470,9 @@ guc_create_virtual(struct intel_engine_cs **siblings,
unsigned int count,
ve->base.flags = I915_ENGINE_IS_VIRTUAL;
+ BUILD_BUG_ON(ilog2(VIRTUAL_ENGINES) < I915_NUM_ENGINES);
+ ve->base.mask = VIRTUAL_ENGINES;
+
intel_context_init(>context, >base);
for (n = 0; n < count; n++) {
diff --git a/drivers/gpu/drm/i915/i915_request.c
b/drivers/gpu/drm/i915/i915_request.c
index 7c7da284990df7..f59081066a197a 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -134,9 +134,7 @@ static void i915_fence_release(struct dma_fence *fence)
i915_sw_fence_fini(>semaphore);
/*
-* Keep one request on each engine for reserved use under mempressure
-* do not use with virtual engines as this really is only needed for
-* kernel contexts.
+* Keep one request on each engine for reserved use under mempressure.
*
* We do not hold a reference to the engine here and so have to be
* very careful in what rq->engine we poke. The virtual engine is
@@ -166,8 +164,7 @@ static void i915_fence_release(struct dma_fence *fence)
* know that if the rq->execution_mask is a single bit, rq->engine
* can be a physical engine with the exact corresponding mask.
*/
- if (!intel_engine_is_virtual(rq->engine) &&
- is_power_of_2(rq->execution_mask) &&
+ if (is_power_of_2(rq->execution_mask) &&
!cmpxchg(>engine->request_pool, NULL, rq))
return;
--
2.34.1
Re: [Intel-gfx] [PATCH v4 9/9] drm/i915: Replace several IS_METEORLAKE with proper IP version checks
Quoting Matt Roper (2023-08-14 17:06:42-03:00)
>Many of the IS_METEORLAKE conditions throughout the driver are supposed
>to be checks for Xe_LPG and/or Xe_LPM+ IP, not for the MTL platform
>specifically. Update those checks to ensure that the code will still
>operate properly if/when these IP versions show up on future platforms.
>
>v2:
> - Update two more conditions (one for pg_enable, one for MTL HuC
> compatibility).
>
>Signed-off-by: Matt Roper
>---
> drivers/gpu/drm/i915/gem/i915_gem_create.c | 4 ++--
> drivers/gpu/drm/i915/gt/intel_engine_pm.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_mocs.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_rc6.c| 2 +-
> drivers/gpu/drm/i915/gt/intel_reset.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_rps.c| 2 +-
> drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 3 ++-
> drivers/gpu/drm/i915/i915_debugfs.c| 2 +-
> drivers/gpu/drm/i915/i915_perf.c | 8 +---
> 9 files changed, 15 insertions(+), 12 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c
>b/drivers/gpu/drm/i915/gem/i915_gem_create.c
>index d24c0ce8805c..19156ba4b9ef 100644
>--- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
>+++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
>@@ -405,8 +405,8 @@ static int ext_set_pat(struct i915_user_extension __user
>*base, void *data)
> BUILD_BUG_ON(sizeof(struct drm_i915_gem_create_ext_set_pat) !=
> offsetofend(struct drm_i915_gem_create_ext_set_pat,
> rsvd));
>
>-/* Limiting the extension only to Meteor Lake */
>-if (!IS_METEORLAKE(i915))
>+/* Limiting the extension only to Xe_LPG and beyond */
>+if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 70))
> return -ENODEV;
>
> if (copy_from_user(, base, sizeof(ext)))
>diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
>b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
>index b538b5c04948..e91fc881dbf1 100644
>--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
>+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
>@@ -21,7 +21,7 @@ static void intel_gsc_idle_msg_enable(struct intel_engine_cs
>*engine)
> {
> struct drm_i915_private *i915 = engine->i915;
>
>-if (IS_METEORLAKE(i915) && engine->id == GSC0) {
>+if (MEDIA_VER(i915) >= 13 && engine->id == GSC0) {
> intel_uncore_write(engine->gt->uncore,
>RC_PSMI_CTRL_GSCCS,
>_MASKED_BIT_DISABLE(IDLE_MSG_DISABLE));
>diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c
>b/drivers/gpu/drm/i915/gt/intel_mocs.c
>index 2c014407225c..a2d8a271fe68 100644
>--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
>+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
>@@ -507,7 +507,7 @@ static unsigned int get_mocs_settings(const struct
>drm_i915_private *i915,
> memset(table, 0, sizeof(struct drm_i915_mocs_table));
>
> table->unused_entries_index = I915_MOCS_PTE;
>-if (IS_METEORLAKE(i915)) {
>+if (IS_GFX_GT_IP_RANGE(>gt0, IP_VER(12, 70), IP_VER(12, 71))) {
> table->size = ARRAY_SIZE(mtl_mocs_table);
> table->table = mtl_mocs_table;
> table->n_entries = MTL_NUM_MOCS_ENTRIES;
>diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c
>b/drivers/gpu/drm/i915/gt/intel_rc6.c
>index 748b0c695072..a5d725508c77 100644
>--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
>+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
>@@ -123,7 +123,7 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
> * temporary wa and should be removed after fixing real cause
> * of forcewake timeouts.
> */
>-if (IS_METEORLAKE(gt->i915) ||
>+if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)) ||
> IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) ||
> IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0))
> pg_enable =
>diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
>b/drivers/gpu/drm/i915/gt/intel_reset.c
>index fd6c22aeb670..98575d79c446 100644
>--- a/drivers/gpu/drm/i915/gt/intel_reset.c
>+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
>@@ -705,7 +705,7 @@ static int __reset_guc(struct intel_gt *gt)
>
> static bool needs_wa_14015076503(struct intel_gt *gt, intel_engine_mask_t
> engine_mask)
> {
>-if (!IS_METEORLAKE(gt->i915) || !HAS_ENGINE(gt, GSC0))
>+if (MEDIA_VER_FULL(gt->i915) != IP_VER(13, 0) || !HAS_ENGINE(gt,
>GSC0))
> return false;
>
> if (!__HAS_ENGINE(engine_mask, GSC0))
>diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
>b/drivers/gpu/drm/i915/gt/intel_rps.c
>index 092542f53aad..4feef874e6d6 100644
>--- a/drivers/gpu/drm/i915/gt/intel_rps.c
>+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
>@@ -1161,7 +1161,7 @@ void gen6_rps_get_freq_caps(struct intel_rps *rps,
>struct intel_rps_freq_caps *c
> {
> struct drm_i915_private *i915 = rps_to_i915(rps);
>
>-if (IS_METEORLAKE(i915))
>+if
Re: [Intel-gfx] [PATCH v4 4/9] drm/i915: Eliminate IS_MTL_GRAPHICS_STEP
Hi Matt, On Mon, Aug 14, 2023 at 01:06:37PM -0700, Matt Roper wrote: > Several workarounds are guarded by IS_MTL_GRAPHICS_STEP. However none > of these workarounds are actually tied to MTL as a platform; they only > relate to the Xe_LPG graphics IP, regardless of what platform it appears > in. At the moment MTL is the only platform that uses Xe_LPG with IP > versions 12.70 and 12.71, but we can't count on this being true in the > future. Switch these to use a new IS_GFX_GT_IP_STEP() macro instead > that is purely based on IP version. IS_GFX_GT_IP_STEP() is also > GT-based rather than device-based, which will help prevent mistakes > where we accidentally try to apply Xe_LPG graphics workarounds to the > Xe_LPM+ media GT and vice-versa. > > v2: > - Switch to a more generic and shorter IS_GT_IP_STEP macro that can be >used for both graphics and media IP (and any other kind of GTs that >show up in the future). > v3: > - Switch back to long-form IS_GFX_GT_IP_STEP macro. (Jani) > - Move macro to intel_gt.h. (Andi) > v4: > - Build IS_GFX_GT_IP_STEP on top of IS_GFX_GT_IP_RANGE and >IS_GRAPHICS_STEP building blocks and name the parameters from/until >rather than begin/fixed. (Jani) > - Fix usage examples in comment. > > Cc: Gustavo Sousa > Cc: Tvrtko Ursulin > Cc: Andi Shyti > Cc: Jani Nikula > Signed-off-by: Matt Roper Reviewed-by: Andi Shyti Andi
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Fix Kconfig error for CONFIG_DRM_I915 (rev2)
== Series Details == Series: drm/i915: Fix Kconfig error for CONFIG_DRM_I915 (rev2) URL : https://patchwork.freedesktop.org/series/122415/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13538 -> Patchwork_122415v2 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_122415v2 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_122415v2, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122415v2/index.html Participating hosts (38 -> 39) -- Additional (3): bat-kbl-2 bat-dg2-9 bat-atsm-1 Missing(2): bat-dg2-13 fi-snb-2520m Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_122415v2: ### IGT changes ### Possible regressions * igt@gem_exec_suspend@basic-s3@smem: - fi-skl-guc: [PASS][1] -> [ABORT][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13538/fi-skl-guc/igt@gem_exec_suspend@basic...@smem.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122415v2/fi-skl-guc/igt@gem_exec_suspend@basic...@smem.html Known issues Here are the changes found in Patchwork_122415v2 that come from known issues: ### IGT changes ### Issues hit * igt@core_auth@basic-auth: - bat-adlp-11:NOTRUN -> [ABORT][3] ([i915#9164]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122415v2/bat-adlp-11/igt@core_a...@basic-auth.html * igt@fbdev@info: - bat-kbl-2: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#1849]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122415v2/bat-kbl-2/igt@fb...@info.html * igt@gem_exec_suspend@basic-s0@smem: - bat-atsm-1: NOTRUN -> [DMESG-WARN][5] ([i915#8841]) +3 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122415v2/bat-atsm-1/igt@gem_exec_suspend@basic...@smem.html * igt@gem_exec_suspend@basic-s3@lmem0: - bat-atsm-1: NOTRUN -> [DMESG-WARN][6] ([i915#8504] / [i915#8841]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122415v2/bat-atsm-1/igt@gem_exec_suspend@basic...@lmem0.html * igt@gem_lmem_swapping@parallel-random-engines: - bat-kbl-2: NOTRUN -> [SKIP][7] ([fdo#109271]) +39 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122415v2/bat-kbl-2/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_mmap@basic: - bat-atsm-1: NOTRUN -> [SKIP][8] ([i915#4083]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122415v2/bat-atsm-1/igt@gem_m...@basic.html - bat-dg2-9: NOTRUN -> [SKIP][9] ([i915#4083]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122415v2/bat-dg2-9/igt@gem_m...@basic.html * igt@gem_mmap_gtt@basic: - bat-dg2-9: NOTRUN -> [SKIP][10] ([i915#4077]) +2 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122415v2/bat-dg2-9/igt@gem_mmap_...@basic.html * igt@gem_render_tiled_blits@basic: - bat-dg2-9: NOTRUN -> [SKIP][11] ([i915#4079]) +1 similar issue [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122415v2/bat-dg2-9/igt@gem_render_tiled_bl...@basic.html * igt@gem_tiled_fence_blits@basic: - bat-atsm-1: NOTRUN -> [SKIP][12] ([i915#4077]) +2 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122415v2/bat-atsm-1/igt@gem_tiled_fence_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-atsm-1: NOTRUN -> [SKIP][13] ([i915#4079]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122415v2/bat-atsm-1/igt@gem_tiled_pread_basic.html * igt@i915_pm_backlight@basic-brightness: - bat-dg2-9: NOTRUN -> [SKIP][14] ([i915#5354] / [i915#7561]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122415v2/bat-dg2-9/igt@i915_pm_backli...@basic-brightness.html * igt@i915_pm_rps@basic-api: - bat-atsm-1: NOTRUN -> [SKIP][15] ([i915#6621]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122415v2/bat-atsm-1/igt@i915_pm_...@basic-api.html - bat-dg2-9: NOTRUN -> [SKIP][16] ([i915#6621]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122415v2/bat-dg2-9/igt@i915_pm_...@basic-api.html * igt@i915_selftest@live@execlists: - fi-bsw-n3050: [PASS][17] -> [ABORT][18] ([i915#7911] / [i915#7913]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13538/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122415v2/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html * igt@i915_suspend@basic-s3-without-i915: -
Re: [Intel-gfx] [PATCH v4 6/9] drm/i915: Eliminate IS_MTL_DISPLAY_STEP
Quoting Matt Roper (2023-08-14 17:06:39-03:00)
>Stepping-specific display behavior shouldn't be tied to MTL as a
>platform, but rather specifically to the Xe_LPD+ IP. Future non-MTL
>platforms may re-use this IP and will need to follow the exact same
>logic and apply the same workarounds. IS_MTL_DISPLAY_STEP() is dropped
>in favor of a new macro IS_DISPLAY_IP_STEP() that only checks the
>display IP version.
>
>v2:
> - Rename macro to IS_DISPLAY_IP_STEP for consistency with the
> corresponding GT macro and handle steppings the same way.
>v3:
> - Drop the automatic "STEP_" pasting.
>v4:
> - Implement IS_DISPLAY_IP_STEP on top of IS_DISPLAY_IP_RANGE /
> IS_DISPLAY_STEP building blocks and make the parameters from/until
> instead of begin/fixed. (Jani)
> - Fix usage details in comment.
>
>Signed-off-by: Matt Roper
>---
> .../drm/i915/display/intel_display_device.h | 22 +++
> drivers/gpu/drm/i915/display/intel_fbc.c | 3 ++-
> drivers/gpu/drm/i915/display/intel_pmdemand.c | 2 +-
> drivers/gpu/drm/i915/display/intel_psr.c | 10 -
> drivers/gpu/drm/i915/i915_drv.h | 6 ++---
> 5 files changed, 32 insertions(+), 11 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h
>b/drivers/gpu/drm/i915/display/intel_display_device.h
>index 215e682bd8b7..7aeff1a5204b 100644
>--- a/drivers/gpu/drm/i915/display/intel_display_device.h
>+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
>@@ -71,6 +71,28 @@ struct drm_printer;
> #define OVERLAY_NEEDS_PHYSICAL(i915)
> (DISPLAY_INFO(i915)->overlay_needs_physical)
> #define SUPPORTS_TV(i915)(DISPLAY_INFO(i915)->supports_tv)
>
>+/* Check that device has a display IP version within the specific range. */
>+#define IS_DISPLAY_IP_RANGE(__i915, from, until) ( \
>+BUILD_BUG_ON_ZERO((from) < IP_VER(2, 0)) + \
>+(DISPLAY_VER_FULL(__i915) >= (from) && \
>+ DISPLAY_VER_FULL(__i915) <= (until)))
>+
>+/*
>+ * Check if a device has a specific IP version as well as a stepping within
>+ * the specified range [begin, fixed). The lower bound is inclusive, the
>upper
>+ * bound is exclusive (corresponding to the first hardware stepping when the
>+ * workaround is no longer needed). E.g.,
I think comments for patch #4 apply here as well.
With the same suggestions applied here,
Reviewed-by: Gustavo Sousa
>+ *
>+ *IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_B2)
>+ *IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_C0, STEP_FOREVER)
>+ *
>+ * "STEP_FOREVER" can be passed as the upper stepping bound for workarounds
>that
>+ * have no upper bound on steppings of the specified IP version.
>+ */
>+#define IS_DISPLAY_IP_STEP(__i915, ipver, from, until) \
>+(IS_DISPLAY_IP_RANGE((__i915), (ipver), (ipver)) && \
>+ IS_DISPLAY_STEP((__i915), (from), (until)))
>+
> struct intel_display_runtime_info {
> struct {
> u16 ver;
>diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
>b/drivers/gpu/drm/i915/display/intel_fbc.c
>index 25382022cd27..1c6d467cec26 100644
>--- a/drivers/gpu/drm/i915/display/intel_fbc.c
>+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
>@@ -50,6 +50,7 @@
> #include "i915_vma.h"
> #include "intel_cdclk.h"
> #include "intel_de.h"
>+#include "intel_display_device.h"
> #include "intel_display_trace.h"
> #include "intel_display_types.h"
> #include "intel_fbc.h"
>@@ -1100,7 +1101,7 @@ static int intel_fbc_check_plane(struct
>intel_atomic_state *state,
>
> /* Wa_14016291713 */
> if ((IS_DISPLAY_VER(i915, 12, 13) ||
>- IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
>+ IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_C0)) &&
> crtc_state->has_psr) {
> plane_state->no_fbc_reason = "PSR1 enabled (Wa_14016291713)";
> return 0;
>diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c
>b/drivers/gpu/drm/i915/display/intel_pmdemand.c
>index f7608d363634..744e332fa2af 100644
>--- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
>+++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
>@@ -92,7 +92,7 @@ int intel_pmdemand_init(struct drm_i915_private *i915)
> _state->base,
> _pmdemand_funcs);
>
>-if (IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
>+if (IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_C0))
> /* Wa_14016740474 */
> intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0,
> DMD_RSP_TIMEOUT_DISABLE);
>
>diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
>b/drivers/gpu/drm/i915/display/intel_psr.c
>index 97d5eef10130..72887c29fb51 100644
>--- a/drivers/gpu/drm/i915/display/intel_psr.c
>+++ b/drivers/gpu/drm/i915/display/intel_psr.c
>@@ -1360,7 +1360,7 @@ static void wm_optimization_wa(struct intel_dp *intel_dp,
> bool set_wa_bit = false;
>
> /* Wa_14015648006 */
>-if
Re: [Intel-gfx] [PATCH v4 4/9] drm/i915: Eliminate IS_MTL_GRAPHICS_STEP
Quoting Matt Roper (2023-08-14 17:06:37-03:00)
>Several workarounds are guarded by IS_MTL_GRAPHICS_STEP. However none
>of these workarounds are actually tied to MTL as a platform; they only
>relate to the Xe_LPG graphics IP, regardless of what platform it appears
>in. At the moment MTL is the only platform that uses Xe_LPG with IP
>versions 12.70 and 12.71, but we can't count on this being true in the
>future. Switch these to use a new IS_GFX_GT_IP_STEP() macro instead
>that is purely based on IP version. IS_GFX_GT_IP_STEP() is also
>GT-based rather than device-based, which will help prevent mistakes
>where we accidentally try to apply Xe_LPG graphics workarounds to the
>Xe_LPM+ media GT and vice-versa.
>
>v2:
> - Switch to a more generic and shorter IS_GT_IP_STEP macro that can be
> used for both graphics and media IP (and any other kind of GTs that
> show up in the future).
>v3:
> - Switch back to long-form IS_GFX_GT_IP_STEP macro. (Jani)
> - Move macro to intel_gt.h. (Andi)
>v4:
> - Build IS_GFX_GT_IP_STEP on top of IS_GFX_GT_IP_RANGE and
> IS_GRAPHICS_STEP building blocks and name the parameters from/until
> rather than begin/fixed. (Jani)
> - Fix usage examples in comment.
>
>Cc: Gustavo Sousa
>Cc: Tvrtko Ursulin
>Cc: Andi Shyti
>Cc: Jani Nikula
>Signed-off-by: Matt Roper
>---
> .../drm/i915/display/skl_universal_plane.c| 5 +-
> drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 11 ++--
> drivers/gpu/drm/i915/gt/intel_gt.h| 17 ++
> drivers/gpu/drm/i915/gt/intel_gt_mcr.c| 7 ++-
> drivers/gpu/drm/i915/gt/intel_lrc.c | 4 +-
> drivers/gpu/drm/i915/gt/intel_reset.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 52 ++-
> drivers/gpu/drm/i915/gt/uc/intel_guc.c| 2 +-
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 4 --
> 10 files changed, 61 insertions(+), 45 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
>b/drivers/gpu/drm/i915/display/skl_universal_plane.c
>index ffc15d278a39..d557ecd4e1eb 100644
>--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
>+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
>@@ -20,6 +20,7 @@
> #include "skl_scaler.h"
> #include "skl_universal_plane.h"
> #include "skl_watermark.h"
>+#include "gt/intel_gt.h"
> #include "pxp/intel_pxp.h"
>
> static const u32 skl_plane_formats[] = {
>@@ -2169,8 +2170,8 @@ static bool skl_plane_has_rc_ccs(struct drm_i915_private
>*i915,
> enum pipe pipe, enum plane_id plane_id)
> {
> /* Wa_14017240301 */
>-if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>-IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>+if (IS_GFX_GT_IP_STEP(to_gt(i915), IP_VER(12, 70), STEP_A0, STEP_B0)
>||
>+IS_GFX_GT_IP_STEP(to_gt(i915), IP_VER(12, 71), STEP_A0, STEP_B0))
> return false;
>
> /* Wa_22011186057 */
>diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>index a4ff55aa5e55..6187b25b67ab 100644
>--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>@@ -4,9 +4,9 @@
> */
>
> #include "gen8_engine_cs.h"
>-#include "i915_drv.h"
> #include "intel_engine_regs.h"
> #include "intel_gpu_commands.h"
>+#include "intel_gt.h"
> #include "intel_lrc.h"
> #include "intel_ring.h"
>
>@@ -226,8 +226,8 @@ u32 *gen12_emit_aux_table_inv(struct intel_engine_cs
>*engine, u32 *cs)
> static int mtl_dummy_pipe_control(struct i915_request *rq)
> {
> /* Wa_14016712196 */
>-if (IS_MTL_GRAPHICS_STEP(rq->i915, M, STEP_A0, STEP_B0) ||
>-IS_MTL_GRAPHICS_STEP(rq->i915, P, STEP_A0, STEP_B0)) {
>+if (IS_GFX_GT_IP_STEP(rq->engine->gt, IP_VER(12, 70), STEP_A0,
>STEP_B0) ||
>+IS_GFX_GT_IP_STEP(rq->engine->gt, IP_VER(12, 71), STEP_A0,
>STEP_B0)) {
> u32 *cs;
>
> /* dummy PIPE_CONTROL + depth flush */
>@@ -799,6 +799,7 @@ u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request
>*rq, u32 *cs)
> u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
> {
> struct drm_i915_private *i915 = rq->i915;
>+struct intel_gt *gt = rq->engine->gt;
> u32 flags = (PIPE_CONTROL_CS_STALL |
> PIPE_CONTROL_TLB_INVALIDATE |
> PIPE_CONTROL_TILE_CACHE_FLUSH |
>@@ -809,8 +810,8 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request
>*rq, u32 *cs)
> PIPE_CONTROL_FLUSH_ENABLE);
>
> /* Wa_14016712196 */
>-if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>-IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>+if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
>+IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
> /* dummy PIPE_CONTROL + depth flush */
>
Re: [Intel-gfx] [PATCH v4 5/9] drm/i915: Eliminate IS_MTL_MEDIA_STEP
Quoting Gustavo Sousa (2023-08-21 11:21:55-03:00)
>Quoting Matt Roper (2023-08-14 17:06:38-03:00)
>>Stepping-specific media behavior shouldn't be tied to MTL as a platform,
>>but rather specifically to the Xe_LPM+ IP. Future non-MTL platforms may
>>re-use this IP and will need to follow the exact same logic and apply
>>the same workarounds. IS_MTL_MEDIA_STEP() is dropped in favor of
>>IS_MEDIA_GT_IP_STEP, which checks the media IP version associated with a
>>specific IP and also ensures that we're operating on the media GT, not
>>the primary GT.
>>
>>v2:
>> - Switch to the IS_GT_IP_STEP macro.
>>v3:
>> - Switch back to long-form IS_MEDIA_GT_IP_STEP. (Jani)
>>v4:
>> - Build IS_MEDIA_GT_IP_STEP on top of IS_MEDIA_GT_IP_RANGE and
>> IS_MEDIA_STEP building blocks and name the parameters from/until
>> rather than begin/fixed.. (Jani)
>>
>>Cc: Jani Nikula
>>Signed-off-by: Matt Roper
>>---
>> drivers/gpu/drm/i915/gt/intel_gt.h | 30 +
>> drivers/gpu/drm/i915/gt/intel_rc6.c | 3 +--
>> drivers/gpu/drm/i915/i915_drv.h | 4
>> drivers/gpu/drm/i915/i915_perf.c| 15 ---
>> 4 files changed, 35 insertions(+), 17 deletions(-)
>>
>>diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h
>>b/drivers/gpu/drm/i915/gt/intel_gt.h
>>index 636fd651b8b2..abe9fe4a3bd9 100644
>>--- a/drivers/gpu/drm/i915/gt/intel_gt.h
>>+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
>>@@ -25,6 +25,20 @@ struct drm_printer;
>> GRAPHICS_VER_FULL((gt)->i915) >= (from) && \
>> GRAPHICS_VER_FULL((gt)->i915) <= (until)))
>>
>>+/*
>>+ * Check that the GT is a media GT and has an IP version within the
>>+ * specified range (inclusive).
>>+ *
>>+ * Only usable on platforms with a standalone media design (i.e., IP version
>>13
>>+ * and higher).
>>+ */
>>+#define IS_MEDIA_GT_IP_RANGE(gt, from, until) ( \
>>+BUILD_BUG_ON_ZERO((from) < IP_VER(13, 0)) + \
>>+BUILD_BUG_ON_ZERO((until) < (from)) + \
>>+((gt)->type == GT_MEDIA && \
>>+ MEDIA_VER_FULL((gt)->i915) >= (from) && \
>>+ MEDIA_VER_FULL((gt)->i915) <= (until)))
>>+
>> /*
>> * Check that the GT is a graphics GT with a specific IP version and has
>> * a stepping in the range [begin, fixed). The lower stepping bound is
>>@@ -42,6 +56,22 @@ struct drm_printer;
>> (IS_GFX_GT_IP_RANGE((gt), (ipver), (ipver)) && \
>> IS_GRAPHICS_STEP((gt)->i915, (from), (until
>>
>>+/*
>>+ * Check that the GT is a media GT with a specific IP version and has
>>+ * a stepping in the range [begin, fixed). The lower stepping bound is
>>+ * inclusive, the upper bound is exclusive (corresponding to the first
>>hardware
>>+ * stepping at which the workaround is no longer needed).
>>+ * "STEP_FOREVER" can be passed as the upper stepping bound for workarounds
>>+ * that have no "fixed" version for the specified IP version.
>
>I think the same comments from patch #4 apply here as well.
>
>>+ *
>>+ * This macro may only be used to match on platforms that have a standalone
>>+ * media design (i.e., media version 13 or higher).
>>+ */
>>+#define IS_MEDIA_GT_IP_STEP(gt, ipver, from, until) ( \
>>+BUILD_BUG_ON_ZERO((until) <= (from)) + \
>>+(IS_MEDIA_GT_IP_RANGE((gt), (ipver), (ipver)) && \
>>+ IS_MEDIA_STEP((gt)->i915, (from), (until
>>+
>> #define GT_TRACE(gt, fmt, ...) do {\
>> const struct intel_gt *gt__ __maybe_unused = (gt);\
>> GEM_TRACE("%s " fmt, dev_name(gt__->i915->drm.dev),\
>>diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c
>>b/drivers/gpu/drm/i915/gt/intel_rc6.c
>>index 58bb1c55294c..748b0c695072 100644
>>--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
>>+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
>>@@ -526,8 +526,7 @@ static bool rc6_supported(struct intel_rc6 *rc6)
>> return false;
>> }
>>
>>-if (IS_MTL_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
>>-gt->type == GT_MEDIA) {
>>+if (IS_MEDIA_GT_IP_STEP(gt, IP_VER(13, 0), STEP_A0, STEP_B0)) {
>> drm_notice(>drm,
>>"Media RC6 disabled on A step\n");
>> return false;
>>diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>>index e0e0493d6c1f..42a86483c694 100644
>>--- a/drivers/gpu/drm/i915/i915_drv.h
>>+++ b/drivers/gpu/drm/i915/i915_drv.h
>>@@ -662,10 +662,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>> (IS_METEORLAKE(__i915) && \
>> IS_DISPLAY_STEP(__i915, since, until))
>>
>>-#define IS_MTL_MEDIA_STEP(__i915, since, until) \
>>-(IS_METEORLAKE(__i915) && \
>>- IS_MEDIA_STEP(__i915, since, until))
>>-
>> /*
>> * DG2 hardware steppings are a bit unusual. The hardware design was forked
>> to
>> * create three variants (G10, G11, and G12) which each have distinct
>>diff --git a/drivers/gpu/drm/i915/i915_perf.c
>>b/drivers/gpu/drm/i915/i915_perf.c
>>index
Re: [Intel-gfx] [PATCH v4 3/9] drm/i915/xelpg: Call Xe_LPG workaround functions based on IP version
Hi Matt, On Mon, Aug 14, 2023 at 01:06:36PM -0700, Matt Roper wrote: > Although some of our Xe_LPG workarounds were already being applied based > on IP version correctly, others were matching on MTL as a base platform, > which is incorrect. Although MTL is the only platform right now that > uses Xe_LPG IP, this may not always be the case. If a future platform > re-uses this graphics IP, the same workarounds should be applied, even > if it isn't a "MTL" platform. > > We were also incorrectly applying Xe_LPG workarounds/tuning to the > Xe_LPM+ media IP in one or two places; we should make sure that we don't > try to apply graphics workarounds to the media GT and vice versa where > they don't belong. A new helper macro IS_GT_IP_RANGE() is added to help > ensure this is handled properly -- it checks that the GT matches the IP > type being tested as well as the IP version falling in the proper range. > > Note that many of the stepping-based workarounds are still incorrectly > checking for a MTL base platform; that will be remedied in a later > patch. > > v2: > - Rework macro into a slightly more generic IS_GT_IP_RANGE() that can >be used for either GFX or MEDIA checks. > > v3: > - Switch back to separate macros for gfx and media. (Jani) > - Move macro to intel_gt.h. (Andi) > > Cc: Gustavo Sousa > Cc: Tvrtko Ursulin > Cc: Jani Nikula > Cc: Andi Shyti > Signed-off-by: Matt Roper Reviewed-by: Andi Shyti Andi
Re: [Intel-gfx] [PATCH v4 5/9] drm/i915: Eliminate IS_MTL_MEDIA_STEP
Quoting Matt Roper (2023-08-14 17:06:38-03:00)
>Stepping-specific media behavior shouldn't be tied to MTL as a platform,
>but rather specifically to the Xe_LPM+ IP. Future non-MTL platforms may
>re-use this IP and will need to follow the exact same logic and apply
>the same workarounds. IS_MTL_MEDIA_STEP() is dropped in favor of
>IS_MEDIA_GT_IP_STEP, which checks the media IP version associated with a
>specific IP and also ensures that we're operating on the media GT, not
>the primary GT.
>
>v2:
> - Switch to the IS_GT_IP_STEP macro.
>v3:
> - Switch back to long-form IS_MEDIA_GT_IP_STEP. (Jani)
>v4:
> - Build IS_MEDIA_GT_IP_STEP on top of IS_MEDIA_GT_IP_RANGE and
> IS_MEDIA_STEP building blocks and name the parameters from/until
> rather than begin/fixed.. (Jani)
>
>Cc: Jani Nikula
>Signed-off-by: Matt Roper
>---
> drivers/gpu/drm/i915/gt/intel_gt.h | 30 +
> drivers/gpu/drm/i915/gt/intel_rc6.c | 3 +--
> drivers/gpu/drm/i915/i915_drv.h | 4
> drivers/gpu/drm/i915/i915_perf.c| 15 ---
> 4 files changed, 35 insertions(+), 17 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h
>b/drivers/gpu/drm/i915/gt/intel_gt.h
>index 636fd651b8b2..abe9fe4a3bd9 100644
>--- a/drivers/gpu/drm/i915/gt/intel_gt.h
>+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
>@@ -25,6 +25,20 @@ struct drm_printer;
> GRAPHICS_VER_FULL((gt)->i915) >= (from) && \
> GRAPHICS_VER_FULL((gt)->i915) <= (until)))
>
>+/*
>+ * Check that the GT is a media GT and has an IP version within the
>+ * specified range (inclusive).
>+ *
>+ * Only usable on platforms with a standalone media design (i.e., IP version
>13
>+ * and higher).
>+ */
>+#define IS_MEDIA_GT_IP_RANGE(gt, from, until) ( \
>+BUILD_BUG_ON_ZERO((from) < IP_VER(13, 0)) + \
>+BUILD_BUG_ON_ZERO((until) < (from)) + \
>+((gt)->type == GT_MEDIA && \
>+ MEDIA_VER_FULL((gt)->i915) >= (from) && \
>+ MEDIA_VER_FULL((gt)->i915) <= (until)))
>+
> /*
> * Check that the GT is a graphics GT with a specific IP version and has
> * a stepping in the range [begin, fixed). The lower stepping bound is
>@@ -42,6 +56,22 @@ struct drm_printer;
> (IS_GFX_GT_IP_RANGE((gt), (ipver), (ipver)) && \
> IS_GRAPHICS_STEP((gt)->i915, (from), (until
>
>+/*
>+ * Check that the GT is a media GT with a specific IP version and has
>+ * a stepping in the range [begin, fixed). The lower stepping bound is
>+ * inclusive, the upper bound is exclusive (corresponding to the first
>hardware
>+ * stepping at which the workaround is no longer needed).
>+ * "STEP_FOREVER" can be passed as the upper stepping bound for workarounds
>+ * that have no "fixed" version for the specified IP version.
I think the same comments from patch #4 apply here as well.
>+ *
>+ * This macro may only be used to match on platforms that have a standalone
>+ * media design (i.e., media version 13 or higher).
>+ */
>+#define IS_MEDIA_GT_IP_STEP(gt, ipver, from, until) ( \
>+BUILD_BUG_ON_ZERO((until) <= (from)) + \
>+(IS_MEDIA_GT_IP_RANGE((gt), (ipver), (ipver)) && \
>+ IS_MEDIA_STEP((gt)->i915, (from), (until
>+
> #define GT_TRACE(gt, fmt, ...) do {\
> const struct intel_gt *gt__ __maybe_unused = (gt);\
> GEM_TRACE("%s " fmt, dev_name(gt__->i915->drm.dev),\
>diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c
>b/drivers/gpu/drm/i915/gt/intel_rc6.c
>index 58bb1c55294c..748b0c695072 100644
>--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
>+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
>@@ -526,8 +526,7 @@ static bool rc6_supported(struct intel_rc6 *rc6)
> return false;
> }
>
>-if (IS_MTL_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
>-gt->type == GT_MEDIA) {
>+if (IS_MEDIA_GT_IP_STEP(gt, IP_VER(13, 0), STEP_A0, STEP_B0)) {
> drm_notice(>drm,
>"Media RC6 disabled on A step\n");
> return false;
>diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>index e0e0493d6c1f..42a86483c694 100644
>--- a/drivers/gpu/drm/i915/i915_drv.h
>+++ b/drivers/gpu/drm/i915/i915_drv.h
>@@ -662,10 +662,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> (IS_METEORLAKE(__i915) && \
> IS_DISPLAY_STEP(__i915, since, until))
>
>-#define IS_MTL_MEDIA_STEP(__i915, since, until) \
>-(IS_METEORLAKE(__i915) && \
>- IS_MEDIA_STEP(__i915, since, until))
>-
> /*
> * DG2 hardware steppings are a bit unusual. The hardware design was forked
> to
> * create three variants (G10, G11, and G12) which each have distinct
>diff --git a/drivers/gpu/drm/i915/i915_perf.c
>b/drivers/gpu/drm/i915/i915_perf.c
>index 04bc1f4a1115..2ef8addb0cfd 100644
>--- a/drivers/gpu/drm/i915/i915_perf.c
>+++ b/drivers/gpu/drm/i915/i915_perf.c
>@@ -4223,7 +4223,7 @@ static int
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Fix Kconfig error for CONFIG_DRM_I915 (rev2)
== Series Details == Series: drm/i915: Fix Kconfig error for CONFIG_DRM_I915 (rev2) URL : https://patchwork.freedesktop.org/series/122415/ State : warning == Summary == Error: dim sparse failed /home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No such file or directory
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Fix Kconfig error for CONFIG_DRM_I915 (rev2)
== Series Details == Series: drm/i915: Fix Kconfig error for CONFIG_DRM_I915 (rev2) URL : https://patchwork.freedesktop.org/series/122415/ State : warning == Summary == Error: dim checkpatch failed /home/kbuild/linux/maintainer-tools/dim: line 50: /home/kbuild/.dimrc: No such file or directory
Re: [Intel-gfx] [PATCH v5] drm/i915: Avoid circular locking dependency when flush delayed work on gt reset
Hi Zhanjun,
On Fri, Aug 11, 2023 at 11:20:11AM -0700, Zhanjun Dong wrote:
> This attempts to avoid circular locking dependency between flush delayed
> work and intel_gt_reset.
> When intel_gt_reset was called, task will hold a lock.
> To cacel delayed work here, the _sync version will also acquire a lock,
/cacel/cancel
> which might trigger the possible cirular locking dependency warning.
> When intel_gt_reset called, reset_in_progress flag will be set, add code
> to check the flag, call async verion if reset is in progress.
/verion/version/
> Signed-off-by: Zhanjun Dong
> Cc: John Harrison
> Cc: Andi Shyti
> Cc: Daniel Vetter
> ---
There is no changelog here :/
Can you please add the changelog after the '---' section?
The commit log has changed and...
> drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 11 ++-
> 1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index a0e3ef1c65d2..600388c849f7 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -1359,7 +1359,16 @@ static void guc_enable_busyness_worker(struct
> intel_guc *guc)
>
> static void guc_cancel_busyness_worker(struct intel_guc *guc)
> {
> - cancel_delayed_work_sync(>timestamp.work);
> + /*
> + * When intel_gt_reset was called, task will hold a lock.
> + * To cacel delayed work here, the _sync version will also acquire a
> lock, which might
> + * trigger the possible cirular locking dependency warning.
> + * Check the reset_in_progress flag, call async verion if reset is in
> progress.
> + */
> + if (guc_to_gt(guc)->uc.reset_in_progress)
> + cancel_delayed_work(>timestamp.work);
> + else
> + cancel_delayed_work_sync(>timestamp.work);
... now you are checking out of reset_in_progress.
Normally the convention here is to have the *_locked() version of
the function. But I'm OK with this, as well... John, any opinion?
Anyway, comparing with your previous patch the decision is made
out of different elements and only __reset_guc_busyness_stats()
needed this change.
Andi
> }
>
> static void __reset_guc_busyness_stats(struct intel_guc *guc)
> --
> 2.34.1
Re: [Intel-gfx] [PATCH v4 3/9] drm/i915/xelpg: Call Xe_LPG workaround functions based on IP version
Quoting Matt Roper (2023-08-14 17:06:36-03:00)
>Although some of our Xe_LPG workarounds were already being applied based
>on IP version correctly, others were matching on MTL as a base platform,
>which is incorrect. Although MTL is the only platform right now that
>uses Xe_LPG IP, this may not always be the case. If a future platform
>re-uses this graphics IP, the same workarounds should be applied, even
>if it isn't a "MTL" platform.
>
>We were also incorrectly applying Xe_LPG workarounds/tuning to the
>Xe_LPM+ media IP in one or two places; we should make sure that we don't
>try to apply graphics workarounds to the media GT and vice versa where
>they don't belong. A new helper macro IS_GT_IP_RANGE() is added to help
>ensure this is handled properly -- it checks that the GT matches the IP
>type being tested as well as the IP version falling in the proper range.
>
>Note that many of the stepping-based workarounds are still incorrectly
>checking for a MTL base platform; that will be remedied in a later
>patch.
>
>v2:
> - Rework macro into a slightly more generic IS_GT_IP_RANGE() that can
> be used for either GFX or MEDIA checks.
>
>v3:
> - Switch back to separate macros for gfx and media. (Jani)
> - Move macro to intel_gt.h. (Andi)
>
>Cc: Gustavo Sousa
>Cc: Tvrtko Ursulin
>Cc: Jani Nikula
>Cc: Andi Shyti
>Signed-off-by: Matt Roper
Reviewed-by: Gustavo Sousa
>---
> drivers/gpu/drm/i915/gt/intel_gt.h | 11 ++
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 38 +++--
> 2 files changed, 31 insertions(+), 18 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h
>b/drivers/gpu/drm/i915/gt/intel_gt.h
>index 6c34547b58b5..15c25980411d 100644
>--- a/drivers/gpu/drm/i915/gt/intel_gt.h
>+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
>@@ -14,6 +14,17 @@
> struct drm_i915_private;
> struct drm_printer;
>
>+/*
>+ * Check that the GT is a graphics GT and has an IP version within the
>+ * specified range (inclusive).
>+ */
>+#define IS_GFX_GT_IP_RANGE(gt, from, until) ( \
>+BUILD_BUG_ON_ZERO((from) < IP_VER(2, 0)) + \
>+BUILD_BUG_ON_ZERO((until) < (from)) + \
>+((gt)->type != GT_MEDIA && \
>+ GRAPHICS_VER_FULL((gt)->i915) >= (from) && \
>+ GRAPHICS_VER_FULL((gt)->i915) <= (until)))
>+
> #define GT_TRACE(gt, fmt, ...) do {\
> const struct intel_gt *gt__ __maybe_unused = (gt);\
> GEM_TRACE("%s " fmt, dev_name(gt__->i915->drm.dev),\
>diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>index 3108ad1d6207..80d67e487b55 100644
>--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>@@ -805,8 +805,8 @@ static void dg2_ctx_workarounds_init(struct
>intel_engine_cs *engine,
> wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE);
> }
>
>-static void mtl_ctx_gt_tuning_init(struct intel_engine_cs *engine,
>- struct i915_wa_list *wal)
>+static void xelpg_ctx_gt_tuning_init(struct intel_engine_cs *engine,
>+ struct i915_wa_list *wal)
> {
> struct drm_i915_private *i915 = engine->i915;
>
>@@ -817,12 +817,12 @@ static void mtl_ctx_gt_tuning_init(struct
>intel_engine_cs *engine,
> wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);
> }
>
>-static void mtl_ctx_workarounds_init(struct intel_engine_cs *engine,
>- struct i915_wa_list *wal)
>+static void xelpg_ctx_workarounds_init(struct intel_engine_cs *engine,
>+ struct i915_wa_list *wal)
> {
> struct drm_i915_private *i915 = engine->i915;
>
>-mtl_ctx_gt_tuning_init(engine, wal);
>+xelpg_ctx_gt_tuning_init(engine, wal);
>
> if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
>@@ -931,8 +931,8 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
> if (engine->class != RENDER_CLASS)
> goto done;
>
>-if (IS_METEORLAKE(i915))
>-mtl_ctx_workarounds_init(engine, wal);
>+if (IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 71)))
>+xelpg_ctx_workarounds_init(engine, wal);
> else if (IS_PONTEVECCHIO(i915))
> ; /* noop; none at this time */
> else if (IS_DG2(i915))
>@@ -1791,10 +1791,8 @@ xelpmp_gt_workarounds_init(struct intel_gt *gt, struct
>i915_wa_list *wal)
> */
> static void gt_tuning_settings(struct intel_gt *gt, struct i915_wa_list *wal)
> {
>-if (IS_METEORLAKE(gt->i915)) {
>-if (gt->type != GT_MEDIA)
>-wa_mcr_write_or(wal, XEHP_L3SCQREG7,
>BLEND_FILL_CACHING_OPT_DIS);
>-
>+if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71))) {
>+
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/3] drm/buddy: Fix contiguous memory allocation issues
== Series Details == Series: series starting with [1/3] drm/buddy: Fix contiguous memory allocation issues URL : https://patchwork.freedesktop.org/series/122693/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13538_full -> Patchwork_122693v1_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_122693v1_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_122693v1_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (9 -> 9) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_122693v1_full: ### IGT changes ### Possible regressions * igt@i915_selftest@mock@memory_region: - shard-apl: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13538/shard-apl2/igt@i915_selftest@mock@memory_region.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122693v1/shard-apl6/igt@i915_selftest@mock@memory_region.html - shard-glk: [PASS][3] -> [DMESG-WARN][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13538/shard-glk1/igt@i915_selftest@mock@memory_region.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122693v1/shard-glk1/igt@i915_selftest@mock@memory_region.html - shard-dg2: [PASS][5] -> [DMESG-WARN][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13538/shard-dg2-2/igt@i915_selftest@mock@memory_region.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122693v1/shard-dg2-10/igt@i915_selftest@mock@memory_region.html - shard-rkl: [PASS][7] -> [DMESG-WARN][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13538/shard-rkl-2/igt@i915_selftest@mock@memory_region.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122693v1/shard-rkl-4/igt@i915_selftest@mock@memory_region.html - shard-dg1: [PASS][9] -> [DMESG-WARN][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13538/shard-dg1-16/igt@i915_selftest@mock@memory_region.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122693v1/shard-dg1-17/igt@i915_selftest@mock@memory_region.html - shard-tglu: [PASS][11] -> [DMESG-WARN][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13538/shard-tglu-4/igt@i915_selftest@mock@memory_region.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122693v1/shard-tglu-9/igt@i915_selftest@mock@memory_region.html - shard-mtlp: [PASS][13] -> [DMESG-WARN][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13538/shard-mtlp-8/igt@i915_selftest@mock@memory_region.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122693v1/shard-mtlp-4/igt@i915_selftest@mock@memory_region.html * igt@kms_ccs@pipe-c-crc-primary-basic-4_tiled_dg2_mc_ccs: - shard-dg2: [PASS][15] -> [FAIL][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13538/shard-dg2-6/igt@kms_ccs@pipe-c-crc-primary-basic-4_tiled_dg2_mc_ccs.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122693v1/shard-dg2-12/igt@kms_ccs@pipe-c-crc-primary-basic-4_tiled_dg2_mc_ccs.html Known issues Here are the changes found in Patchwork_122693v1_full that come from known issues: ### IGT changes ### Issues hit * igt@device_reset@unbind-cold-reset-rebind: - shard-mtlp: NOTRUN -> [SKIP][17] ([i915#7701]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122693v1/shard-mtlp-5/igt@device_re...@unbind-cold-reset-rebind.html * igt@drm_fdinfo@busy-check-all@bcs0: - shard-dg1: NOTRUN -> [SKIP][18] ([i915#8414]) +4 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122693v1/shard-dg1-18/igt@drm_fdinfo@busy-check-...@bcs0.html * igt@drm_fdinfo@isolation@bcs0: - shard-dg2: NOTRUN -> [SKIP][19] ([i915#8414]) +9 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122693v1/shard-dg2-2/igt@drm_fdinfo@isolat...@bcs0.html * igt@drm_fdinfo@virtual-busy-idle: - shard-mtlp: NOTRUN -> [SKIP][20] ([i915#8414]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122693v1/shard-mtlp-5/igt@drm_fdi...@virtual-busy-idle.html * igt@feature_discovery@display-2x: - shard-dg2: NOTRUN -> [SKIP][21] ([i915#1839]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122693v1/shard-dg2-2/igt@feature_discov...@display-2x.html * igt@gem_close_race@multigpu-basic-threads: - shard-dg2: NOTRUN -> [SKIP][22] ([i915#7697]) [22]:
Re: [Intel-gfx] [PATCH] drm/i915: Add intel_pcode_probe
On 8/18/2023 6:29 PM, Rodrigo Vivi wrote:
On Fri, Aug 18, 2023 at 11:32:27AM +0530, Sundaresan, Sujaritha wrote:
On 8/18/2023 11:30 AM, Gupta, Anshuman wrote:
-Original Message-
From: Intel-gfx On Behalf Of
Sujaritha Sundaresan
Sent: Friday, August 18, 2023 8:16 AM
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH] drm/i915: Add intel_pcode_probe
Added intel_pcode_probe, promoted wait for lmem init and intel_pcode_init
prior to mmio_probe during load, so that GT registers can be accessed only
after this, else MCA is observed.
Signed-off-by: Sujaritha Sundaresan
Both DG1 and DG2 crashed during i915_pci_probe.
BAT is failing.
Thanks,
Anshuman Gupta.
Hi Anshuman,
Yes I'm currently looking into it.
Thanks,
Suja
---
drivers/gpu/drm/i915/i915_driver.c | 37 -
drivers/gpu/drm/i915/intel_uncore.c | 12 --
2 files changed, 31 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_driver.c
b/drivers/gpu/drm/i915/i915_driver.c
index f8dbee7a5af7..92cafceaf447 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -93,6 +93,7 @@
#include "i915_memcpy.h"
#include "i915_perf.h"
#include "i915_query.h"
+#include "i915_reg.h"
#include "i915_suspend.h"
#include "i915_switcheroo.h"
#include "i915_sysfs.h"
@@ -436,6 +437,32 @@ static int i915_pcode_init(struct drm_i915_private
*i915)
return 0;
}
+static int intel_pcode_probe(struct drm_i915_private *i915) {
+ struct intel_uncore *uncore;
+ int ret;
+
+ /*
+* The boot firmware initializes local memory and assesses its health.
+* If memory training fails, the punit will have been instructed to
+* keep the GT powered down; we won't be able to communicate
with it
+* and we should not continue with driver initialization.
+*/
+ if (IS_DGFX(i915) &&
+ !(__raw_uncore_read32(uncore, GU_CNTL) & LMEM_INIT))
{
+ drm_err(>drm, "LMEM not initialized by firmware\n");
+ return -ENODEV;
+ }
+
+ /*
+* Driver handshakes with pcode via mailbox command to know that
SoC
+* initialization is complete before proceeding further
+*/
+ ret = i915_pcode_init(i915);
+
+ return ret;
+}
+
/**
* i915_driver_hw_probe - setup state requiring device access
* @dev_priv: device private
@@ -547,10 +574,6 @@ static int i915_driver_hw_probe(struct
drm_i915_private *dev_priv)
intel_opregion_setup(dev_priv);
- ret = i915_pcode_init(dev_priv);
- if (ret)
- goto err_opregion;
-
/*
* Fill the dram structure to get the system dram info. This will be
* used for memory latency calculation.
@@ -561,8 +584,6 @@ static int i915_driver_hw_probe(struct
drm_i915_private *dev_priv)
return 0;
-err_opregion:
- intel_opregion_cleanup(dev_priv);
err_msi:
if (pdev->msi_enabled)
pci_disable_msi(pdev);
@@ -778,6 +799,10 @@ int i915_driver_probe(struct pci_dev *pdev, const
struct pci_device_id *ent)
if (ret < 0)
goto out_runtime_pm_put;
+ ret = intel_pcode_probe(i915);
+ if (ret)
+ goto out_tiles_cleanup;
+
ret = i915_driver_mmio_probe(i915);
chicken-egg problem here?!
I don't believe this could ever work. You need the MMIO space to be able
to communicate with PCODE mailbox and check the lmem init, no?!
I believe the bug is that PCODE check should come before the LMEM_INIT
check.
LMEM won't be ready before pcode state that everything was ready for
the lmem access. And on your code pcode ready check is still after
the lmem.
Cc: Aravind Iddamsetty
who was recently raising that we had an order problem there.
Yes looks like there is definitely an ordering issue.
Will look into this more.
if (ret < 0)
goto out_tiles_cleanup;
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index dfefad5a5fec..4a353d4adf86 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -2658,18 +2658,6 @@ int intel_uncore_init_mmio(struct intel_uncore
*uncore)
if (ret)
return ret;
- /*
-* The boot firmware initializes local memory and assesses its health.
-* If memory training fails, the punit will have been instructed to
-* keep the GT powered down; we won't be able to communicate
with it
-* and we should not continue with driver initialization.
-*/
- if (IS_DGFX(i915) &&
- !(__raw_uncore_read32(uncore, GU_CNTL) & LMEM_INIT)) {
- drm_err(>drm, "LMEM not initialized by firmware\n");
- return -ENODEV;
- }
-
if (GRAPHICS_VER(i915) > 5 && !intel_vgpu_active(i915))
uncore->flags |= UNCORE_HAS_FORCEWAKE;
--
2.41.0
Re: [Intel-gfx] [PATCH 03/13] scatterlist: Add sg_set_folio()
在 2023/7/31 5:42, Matthew Wilcox 写道:
On Sun, Jul 30, 2023 at 09:57:06PM +0800, Zhu Yanjun wrote:
在 2023/7/30 19:18, Matthew Wilcox 写道:
On Sun, Jul 30, 2023 at 07:01:26PM +0800, Zhu Yanjun wrote:
Does the following function have folio version?
"
int sg_alloc_append_table_from_pages(struct sg_append_table *sgt_append,
struct page **pages, unsigned int n_pages, unsigned int offset,
unsigned long size, unsigned int max_segment,
unsigned int left_pages, gfp_t gfp_mask)
"
No -- I haven't needed to convert anything that uses
sg_alloc_append_table_from_pages() yet. It doesn't look like it should
be _too_ hard to add a folio version.
In many places, this function is used. So this function needs the folio
version.
It's not used in very many places. But the first one that I see it used
(drivers/infiniband/core/umem.c), you can't do a straightforward folio
conversion:
pinned = pin_user_pages_fast(cur_base,
min_t(unsigned long, npages,
PAGE_SIZE /
sizeof(struct page *)),
gup_flags, page_list);
...
ret = sg_alloc_append_table_from_pages(
>sgt_append, page_list, pinned, 0,
pinned << PAGE_SHIFT, ib_dma_max_seg_size(device),
npages, GFP_KERNEL);
That can't be converted to folios. The GUP might start in the middle of
the folio, and we have no way to communicate that.
This particular usage really needs the phyr work that Jason is doing so
we can efficiently communicate physically contiguous ranges from GUP
to sg.
Hi, Matthew
Thanks. To the following function, it seems that no folio function
replace vmalloc_to_page.
vmalloc_to_page calls virt_to_page to get page. Finally the followings
will be called.
"
(mem_map + ((pfn) - ARCH_PFN_OFFSET))
"
And I do not find the related folio functions with vmalloc_to_page.
And no folio function replaces dma_map_page.
dma_map_page will call dma_map_page_attrs.
Or these 2 function should not be replaced with folio functions?
int irdma_map_vm_page_list(struct irdma_hw *hw, void *va, dma_addr_t
*pg_dma,
u32 pg_cnt)
{
struct page *vm_page;
int i;
u8 *addr;
addr = (u8 *)(uintptr_t)va;
for (i = 0; i < pg_cnt; i++) {
vm_page = vmalloc_to_page(addr);
if (!vm_page)
goto err;
pg_dma[i] = dma_map_page(hw->device, vm_page, 0, PAGE_SIZE,
DMA_BIDIRECTIONAL);
if (dma_mapping_error(hw->device, pg_dma[i]))
goto err;
addr += PAGE_SIZE;
}
return 0;
err:
irdma_unmap_vm_page_list(hw, pg_dma, i);
return -ENOMEM;
}
Thanks,
Zhu Yanjun
Another problem, after folio is used, I want to know the performance after
folio is implemented.
How to make tests to get the performance?
You know what you're working on ... I wouldn't know how best to test
your code.
[Intel-gfx] [PATCH v2 2/2] drm/edid: Fix "Analog composite sync!" for current eDP display panels
VESA Enhanced EDID Standard does not clearly describe how display
panel vendors should setup the Sync Signal Defintions (bit 4 & 3) in
the Detailed Timing Definition (relative offset 17, absolute offset
47h[+18]) for Digital Video Signal Interfaces (bit 7 at offset 14h).
In practice many eDP panels which using a Digital Video Signal
Interfaces (bit 7 at offset 14h == 1) are leaving the Sync Signal
Defintions at offset 47h[+18] blank 0x00, which would mean concerned
with the VESA Standard [1] that they are using "Analog Composite
Sync".
Fix: Just detect Analog Sync Signal if an Analog Video Signal
Interface (bit 7 at offset 14h == 0) is in use. Just detect
Digital Sync Signal if an Digital Video Signal Interface is in
use.
Reference: [1] VESA Enhanced EDID Standard, Release A, Rev.2, Page 35
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8789
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8146
Signed-off-by: Dirk Lehmann
---
drivers/gpu/drm/drm_edid.c | 74 --
include/drm/drm_edid.h | 12 +--
2 files changed, 73 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 1f470968ed14..6afdc34e55ce 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -3437,6 +3437,7 @@ static struct drm_display_mode *drm_mode_detailed(struct
drm_connector *connecto
const struct drm_display_info *info = >display_info;
struct drm_device *dev = connector->dev;
struct drm_display_mode *mode;
+ const struct edid *edid = drm_edid->edid;
const struct detailed_pixel_timing *pt = >data.pixel_data;
unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
@@ -3456,10 +3457,6 @@ static struct drm_display_mode *drm_mode_detailed(struct
drm_connector *connecto
connector->base.id, connector->name);
return NULL;
}
- if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
- drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Composite sync not
supported\n",
- connector->base.id, connector->name);
- }
/* it is incorrect if hsync/vsync width is zero */
if (!hsync_pulse_width || !vsync_pulse_width) {
@@ -3505,11 +3502,68 @@ static struct drm_display_mode
*drm_mode_detailed(struct drm_connector *connecto
if (info->quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC;
+ } else if (edid->input & DRM_EDID_INPUT_DIGITAL) {
+ /* !info->quirks && edid->input == DIGITAL */
+ switch (pt->misc & DRM_EDID_PT_SYNC_MASK) {
+ /* VESA Enhanced EDID Standard, Release A, Rev.2, Page 35
+*
+* CASE DRM_EDID_PT_ANALOG_CSYNC:
+*
+* (pt->misc & DRM_EDID_PT_SYNC_MASK == 0x00) means
+* "Analog Composite Sync" as described in VESA
+* Standard. But many digital display panels without
+* composite sync are also using 0x00 here.
+*
+* Therefore use DEFAULT: as we are currently on an
+* digital video signal interface.
+*/
+ case DRM_EDID_PT_DIGITAL_CSYNC:
+ drm_dbg_kms(dev,
+ "[CONNECTOR:%d:%s] Digital composite sync!\n",
+ connector->base.id, connector->name);
+ mode->flags |= DRM_MODE_FLAG_CSYNC;
+ mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
+ DRM_MODE_FLAG_PCSYNC : DRM_MODE_FLAG_NCSYNC;
+ break;
+ case DRM_EDID_PT_DIGITAL_SEPARATE_SYNC:
+ drm_dbg_kms(dev,
+ "[CONNECTOR:%d:%s] Digital seperate sync!\n",
+ connector->base.id, connector->name);
+ goto digital_default;
+ break; /* Missing BREAK throws a compiler warning */
+ default:
+digital_default:
+ mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
+ DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
+ mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
+ DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
+ break;
+ }
} else {
- mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
- DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
- mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
- DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
+ /*
[Intel-gfx] [PATCH v2 1/2] Revert "drm/edid: Fix csync detailed mode parsing"
From: Jani Nikula
This reverts commit ca62297b2085b5b3168bd891ca24862242c635a1.
Commit ca62297b2085 ("drm/edid: Fix csync detailed mode parsing") fixed
EDID detailed mode sync parsing. Unfortunately, there are quite a few
displays out there that have bogus (zero) sync field that are broken by
the change. Zero means analog composite sync, which is not right for
digital displays, and the modes get rejected. Regardless, it used to
work, and it needs to continue to work. Revert the change.
Rejecting modes with analog composite sync was the part that fixed the
gitlab issue 8146 [1]. We'll need to get back to the drawing board with
that.
[1] https://gitlab.freedesktop.org/drm/intel/-/issues/8146
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8789
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8930
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9044
Fixes: ca62297b2085 ("drm/edid: Fix csync detailed mode parsing")
Cc: Ville Syrjälä
Cc: dri-de...@lists.freedesktop.org
Cc: # v6.4+
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_edid.c | 29 -
include/drm/drm_edid.h | 12 +++-
2 files changed, 11 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index e0dbd9140726..1f470968ed14 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -3456,6 +3456,10 @@ static struct drm_display_mode *drm_mode_detailed(struct
drm_connector *connecto
connector->base.id, connector->name);
return NULL;
}
+ if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
+ drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Composite sync not
supported\n",
+ connector->base.id, connector->name);
+ }
/* it is incorrect if hsync/vsync width is zero */
if (!hsync_pulse_width || !vsync_pulse_width) {
@@ -3502,27 +3506,10 @@ static struct drm_display_mode
*drm_mode_detailed(struct drm_connector *connecto
if (info->quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC;
} else {
- switch (pt->misc & DRM_EDID_PT_SYNC_MASK) {
- case DRM_EDID_PT_ANALOG_CSYNC:
- case DRM_EDID_PT_BIPOLAR_ANALOG_CSYNC:
- drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Analog composite
sync!\n",
- connector->base.id, connector->name);
- mode->flags |= DRM_MODE_FLAG_CSYNC |
DRM_MODE_FLAG_NCSYNC;
- break;
- case DRM_EDID_PT_DIGITAL_CSYNC:
- drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Digital composite
sync!\n",
- connector->base.id, connector->name);
- mode->flags |= DRM_MODE_FLAG_CSYNC;
- mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
- DRM_MODE_FLAG_PCSYNC : DRM_MODE_FLAG_NCSYNC;
- break;
- case DRM_EDID_PT_DIGITAL_SEPARATE_SYNC:
- mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
- DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
- mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
- DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
- break;
- }
+ mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
+ DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
+ mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
+ DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
}
set_size:
diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h
index 169755d3de19..48e93f909ef6 100644
--- a/include/drm/drm_edid.h
+++ b/include/drm/drm_edid.h
@@ -61,15 +61,9 @@ struct std_timing {
u8 vfreq_aspect;
} __attribute__((packed));
-#define DRM_EDID_PT_SYNC_MASK (3 << 3)
-# define DRM_EDID_PT_ANALOG_CSYNC (0 << 3)
-# define DRM_EDID_PT_BIPOLAR_ANALOG_CSYNC (1 << 3)
-# define DRM_EDID_PT_DIGITAL_CSYNC (2 << 3)
-# define DRM_EDID_PT_CSYNC_ON_RGB (1 << 1) /* analog csync only */
-# define DRM_EDID_PT_CSYNC_SERRATE(1 << 2)
-# define DRM_EDID_PT_DIGITAL_SEPARATE_SYNC (3 << 3)
-# define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1) /* also digital csync */
-# define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2)
+#define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1)
+#define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2)
+#define DRM_EDID_PT_SEPARATE_SYNC (3 << 3)
#define DRM_EDID_PT_STEREO (1 << 5)
#define DRM_EDID_PT_INTERLACED (1 << 7)
--
2.40.1
[Intel-gfx] [PATCH v3] drm/i915: Fix Kconfig error for CONFIG_DRM_I915
When CONFIG_DRM_I915 is set to 'y' and CONFIG_BACKLIGHT_CLASS_DEVICE
is set to 'm', we encountered an ld.lld error during the build process:
ld.lld: error: undefined symbol: backlight_device_get_by_name
>>> referenced by intel_backlight.c:955
>>> vmlinux.o:(intel_backlight_device_register)
ld.lld: error: undefined symbol: backlight_device_register
>>> referenced by intel_backlight.c:971
>>> vmlinux.o:(intel_backlight_device_register)
ld.lld: error: undefined symbol: backlight_device_unregister
>>> referenced by intel_backlight.c:999
>>> vmlinux.o:(intel_backlight_device_unregister)
This issue occurred because intel_backlight_device_register and
intel_backlight_device_unregister were enclosed within
\#if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE) and #endif directives.
However, according to Kconfig, CONFIG_DRM_I915 will select
BACKLIGHT_CLASS_DEVICE only if ACPI is enabled.
This led to an error when ACPI is not enabled.
Change IS_ENABLED to IS_REACHABLE and use IS_REACHABLE to encompass
the implementation of intel_connector_register() to solve this issue.
Signed-off-by: Wang Jinchao
---
drivers/gpu/drm/i915/display/intel_backlight.c | 2 +-
drivers/gpu/drm/i915/display/intel_backlight.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c
b/drivers/gpu/drm/i915/display/intel_backlight.c
index 2e8f17c04522..d812cdc74a84 100644
--- a/drivers/gpu/drm/i915/display/intel_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_backlight.c
@@ -795,7 +795,7 @@ void intel_backlight_enable(const struct intel_crtc_state
*crtc_state,
mutex_unlock(>display.backlight.lock);
}
-#if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
+#if IS_REACHABLE(CONFIG_BACKLIGHT_CLASS_DEVICE)
static u32 intel_panel_get_backlight(struct intel_connector *connector)
{
struct drm_i915_private *i915 = to_i915(connector->base.dev);
diff --git a/drivers/gpu/drm/i915/display/intel_backlight.h
b/drivers/gpu/drm/i915/display/intel_backlight.h
index 339643f63897..207fe1c613d8 100644
--- a/drivers/gpu/drm/i915/display/intel_backlight.h
+++ b/drivers/gpu/drm/i915/display/intel_backlight.h
@@ -36,7 +36,7 @@ u32 intel_backlight_invert_pwm_level(struct intel_connector
*connector, u32 leve
u32 intel_backlight_level_to_pwm(struct intel_connector *connector, u32 level);
u32 intel_backlight_level_from_pwm(struct intel_connector *connector, u32 val);
-#if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
+#if IS_REACHABLE(CONFIG_BACKLIGHT_CLASS_DEVICE)
int intel_backlight_device_register(struct intel_connector *connector);
void intel_backlight_device_unregister(struct intel_connector *connector);
#else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
--
2.40.0
Re: [Intel-gfx] [PATCH v2 2/2] drm/edid: Fix "Analog composite sync!" for current eDP display panels
Hey Jani,
On 8/17/23 15:05, Jani Nikula wrote:
On Thu, 17 Aug 2023, Dirk Lehmann wrote:
VESA Enhanced EDID Standard does not clearly describe how display
panel vendors should setup the Sync Signal Defintions (bit 4 & 3) in
the Detailed Timing Definition (relative offset 17, absolute offset
47h[+18]) for Digital Video Signal Interfaces (bit 7 at offset 14h).
In practice many eDP panels which using a Digital Video Signal
Interfaces (bit 7 at offset 14h == 1) are leaving the Sync Signal
Defintions at offset 47h[+18] blank 0x00, which would mean concerned
with the VESA Standard [1] that they are using "Analog Composite
Sync".
Fix: Just detect Analog Sync Signal if an Analog Video Signal
Interface (bit 7 at offset 14h == 0) is in use. Just detect
Digital Sync Signal if an Digital Video Signal Interface is in
use.
Reference: [1] VESA Enhanced EDID Standard, Release A, Rev.2, Page 35
Please don't reply with patches in-reply-to other people's patches.
Sorry, I am new with such patch lists :/ ...
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8789
This is now fixed by the revert that I just pushed.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8146
I don't think this patch fixes that one; see below.
Signed-off-by: Dirk Lehmann
---
drivers/gpu/drm/drm_edid.c | 74 --
include/drm/drm_edid.h | 12 +--
2 files changed, 73 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 1f470968ed14..6afdc34e55ce 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -3437,6 +3437,7 @@ static struct drm_display_mode *drm_mode_detailed(struct
drm_connector *connecto
const struct drm_display_info *info = >display_info;
struct drm_device *dev = connector->dev;
struct drm_display_mode *mode;
+ const struct edid *edid = drm_edid->edid;
const struct detailed_pixel_timing *pt = >data.pixel_data;
unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
@@ -3456,10 +3457,6 @@ static struct drm_display_mode *drm_mode_detailed(struct
drm_connector *connecto
connector->base.id, connector->name);
return NULL;
}
- if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
- drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Composite sync not
supported\n",
- connector->base.id, connector->name);
- }
/* it is incorrect if hsync/vsync width is zero */
if (!hsync_pulse_width || !vsync_pulse_width) {
@@ -3505,11 +3502,68 @@ static struct drm_display_mode
*drm_mode_detailed(struct drm_connector *connecto
if (info->quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC;
+ } else if (edid->input & DRM_EDID_INPUT_DIGITAL) {
+ /* !info->quirks && edid->input == DIGITAL */
+ switch (pt->misc & DRM_EDID_PT_SYNC_MASK) {
+ /* VESA Enhanced EDID Standard, Release A, Rev.2, Page 35
+*
+* CASE DRM_EDID_PT_ANALOG_CSYNC:
+*
+* (pt->misc & DRM_EDID_PT_SYNC_MASK == 0x00) means
+* "Analog Composite Sync" as described in VESA
+* Standard. But many digital display panels without
+* composite sync are also using 0x00 here.
+*
+* Therefore use DEFAULT: as we are currently on an
+* digital video signal interface.
+*/
+ case DRM_EDID_PT_DIGITAL_CSYNC:
+ drm_dbg_kms(dev,
+ "[CONNECTOR:%d:%s] Digital composite sync!\n",
+ connector->base.id, connector->name);
+ mode->flags |= DRM_MODE_FLAG_CSYNC;
+ mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
+ DRM_MODE_FLAG_PCSYNC : DRM_MODE_FLAG_NCSYNC;
+ break;
+ case DRM_EDID_PT_DIGITAL_SEPARATE_SYNC:
+ drm_dbg_kms(dev,
+ "[CONNECTOR:%d:%s] Digital seperate sync!\n",
+ connector->base.id, connector->name);
+ goto digital_default;
+ break; /* Missing BREAK throws a compiler warning */
fallthrough; will do the trick.
Cool, that's new for me. FALLTHROUGH really works, great :)
+ default:
+digital_default:
+ mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
+ DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
+ mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
+
[Intel-gfx] ✓ Fi.CI.IGT: success for SDP split for DP-MST (rev2)
== Series Details == Series: SDP split for DP-MST (rev2) URL : https://patchwork.freedesktop.org/series/122460/ State : success == Summary == CI Bug Log - changes from CI_DRM_13536_full -> Patchwork_122460v2_full Summary --- **SUCCESS** No regressions found. Participating hosts (9 -> 9) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_122460v2_full that come from known issues: ### IGT changes ### Issues hit * igt@api_intel_bb@blit-reloc-purge-cache: - shard-mtlp: NOTRUN -> [SKIP][1] ([i915#8411]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v2/shard-mtlp-1/igt@api_intel...@blit-reloc-purge-cache.html * igt@drm_buddy@drm_buddy_test: - shard-snb: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#8661]) +2 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v2/shard-snb1/igt@drm_buddy@drm_buddy_test.html * igt@drm_fdinfo@busy-check-all@bcs0: - shard-dg1: NOTRUN -> [SKIP][3] ([i915#8414]) +4 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v2/shard-dg1-17/igt@drm_fdinfo@busy-check-...@bcs0.html * igt@drm_fdinfo@busy-idle-check-all@vcs0: - shard-dg2: NOTRUN -> [SKIP][4] ([i915#8414]) +10 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v2/shard-dg2-11/igt@drm_fdinfo@busy-idle-check-...@vcs0.html * igt@drm_fdinfo@virtual-busy-all: - shard-mtlp: NOTRUN -> [SKIP][5] ([i915#8414]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v2/shard-mtlp-3/igt@drm_fdi...@virtual-busy-all.html * igt@gem_busy@semaphore: - shard-dg2: NOTRUN -> [SKIP][6] ([i915#3936]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v2/shard-dg2-10/igt@gem_b...@semaphore.html * igt@gem_ccs@block-copy-compressed: - shard-mtlp: NOTRUN -> [SKIP][7] ([i915#5325]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v2/shard-mtlp-1/igt@gem_...@block-copy-compressed.html * igt@gem_ctx_exec@basic-nohangcheck: - shard-tglu: [PASS][8] -> [FAIL][9] ([i915#6268]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-tglu-7/igt@gem_ctx_e...@basic-nohangcheck.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v2/shard-tglu-3/igt@gem_ctx_e...@basic-nohangcheck.html * igt@gem_ctx_persistence@heartbeat-many: - shard-dg1: NOTRUN -> [SKIP][10] ([i915#8555]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v2/shard-dg1-17/igt@gem_ctx_persiste...@heartbeat-many.html * igt@gem_ctx_persistence@saturated-hostile-nopreempt@ccs0: - shard-dg2: NOTRUN -> [SKIP][11] ([i915#5882]) +9 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v2/shard-dg2-10/igt@gem_ctx_persistence@saturated-hostile-nopree...@ccs0.html * igt@gem_eio@in-flight-suspend: - shard-dg1: [PASS][12] -> [DMESG-WARN][13] ([i915#4391]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-dg1-17/igt@gem_...@in-flight-suspend.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v2/shard-dg1-19/igt@gem_...@in-flight-suspend.html * igt@gem_eio@reset-stress: - shard-dg2: NOTRUN -> [FAIL][14] ([i915#5784]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v2/shard-dg2-10/igt@gem_...@reset-stress.html * igt@gem_exec_balancer@bonded-false-hang: - shard-dg2: NOTRUN -> [SKIP][15] ([i915#4812]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v2/shard-dg2-2/igt@gem_exec_balan...@bonded-false-hang.html * igt@gem_exec_balancer@bonded-sync: - shard-dg2: NOTRUN -> [SKIP][16] ([i915#4771]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v2/shard-dg2-11/igt@gem_exec_balan...@bonded-sync.html * igt@gem_exec_balancer@noheartbeat: - shard-mtlp: NOTRUN -> [SKIP][17] ([i915#8555]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v2/shard-mtlp-1/igt@gem_exec_balan...@noheartbeat.html * igt@gem_exec_capture@capture-invisible@lmem0: - shard-dg2: NOTRUN -> [SKIP][18] ([i915#6334]) +1 similar issue [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v2/shard-dg2-11/igt@gem_exec_capture@capture-invisi...@lmem0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-apl: [PASS][19] -> [FAIL][20] ([i915#2842]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/shard-apl6/igt@gem_exec_fair@basic-pace-s...@rcs0.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v2/shard-apl2/igt@gem_exec_fair@basic-pace-s...@rcs0.html * igt@gem_exec_fair@basic-pace@rcs0: - shard-glk: [PASS][21] ->
Re: [Intel-gfx] [PATCH 1/3] drm/buddy: Fix contiguous memory allocation issues
Am 21.08.23 um 12:14 schrieb Arunpravin Paneer Selvam:
The way now contiguous requests are implemented such that
the size rounded up to power of 2 and the corresponding order
block picked from the freelist.
In addition to the older method, the new method will rounddown
the size to power of 2 and the corresponding order block picked
from the freelist. And for the remaining size we traverse the
tree and try to allocate either from the freelist block's buddy
or from the peer block. If the remaining size from peer/buddy
block is not free, we pick the next freelist block and repeat
the same method.
I think it's worth mentioning that Xinhui tried something similar a few
month ago, but that didn't looked like it would work. For this here I'm
more confident.
Of hand the implementation looks clean to me, but Matthew or others
which have more background in how the implementation works need to take
a look as well.
Thanks,
Christian.
Moved contiguous/alignment size computation part and trim
function to the drm buddy manager.
Signed-off-by: Arunpravin Paneer Selvam
---
drivers/gpu/drm/drm_buddy.c | 253 ++--
include/drm/drm_buddy.h | 6 +-
2 files changed, 248 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/drm_buddy.c b/drivers/gpu/drm/drm_buddy.c
index 7098f125b54a..220f60c08a03 100644
--- a/drivers/gpu/drm/drm_buddy.c
+++ b/drivers/gpu/drm/drm_buddy.c
@@ -569,6 +569,197 @@ static int __drm_buddy_alloc_range(struct drm_buddy *mm,
return __alloc_range(mm, , start, size, blocks);
}
+static int __alloc_contiguous_block_from_buddy(struct drm_buddy *mm,
+ u64 size,
+ u64 min_block_size,
+ struct drm_buddy_block *block,
+ struct list_head *blocks)
+{
+ struct drm_buddy_block *buddy, *parent = NULL;
+ u64 start, offset = 0;
+ LIST_HEAD(dfs);
+ int err;
+
+ if (!block)
+ return -EINVAL;
+
+ buddy = __get_buddy(block);
+ if (!buddy)
+ return -ENOSPC;
+
+ if (drm_buddy_block_is_allocated(buddy))
+ return -ENOSPC;
+
+ parent = block->parent;
+ if (!parent)
+ return -ENOSPC;
+
+ if (block->parent->right == block) {
+ u64 remaining;
+
+ /* Compute the leftover size for allocation */
+ remaining = max((size - drm_buddy_block_size(mm, buddy)),
+ min_block_size);
+ if (!IS_ALIGNED(remaining, min_block_size))
+ remaining = round_up(remaining, min_block_size);
+
+ /* Check if remaining size is greater than buddy block size */
+ if (drm_buddy_block_size(mm, buddy) < remaining)
+ return -ENOSPC;
+
+ offset = drm_buddy_block_size(mm, buddy) - remaining;
+ }
+
+ list_add(>tmp_link, );
+ start = drm_buddy_block_offset(parent) + offset;
+
+ err = __alloc_range(mm, , start, size, blocks);
+ if (err)
+ return -ENOSPC;
+
+ return 0;
+}
+
+static int __alloc_contiguous_block_from_peer(struct drm_buddy *mm,
+ u64 size,
+ u64 min_block_size,
+ struct drm_buddy_block *block,
+ struct list_head *blocks)
+{
+ struct drm_buddy_block *first, *peer, *tmp;
+ struct drm_buddy_block *parent = NULL;
+ u64 start, offset = 0;
+ unsigned int order;
+ LIST_HEAD(dfs);
+ int err;
+
+ if (!block)
+ return -EINVAL;
+
+ order = drm_buddy_block_order(block);
+ /* Add freelist block to dfs list */
+ list_add(>tmp_link, );
+
+ tmp = block;
+ parent = block->parent;
+ while (parent) {
+ if (block->parent->left == block) {
+ if (parent->left != tmp) {
+ peer = parent->left;
+ break;
+ }
+ } else {
+ if (parent->right != tmp) {
+ peer = parent->right;
+ break;
+ }
+ }
+
+ tmp = parent;
+ parent = tmp->parent;
+ }
+
+ if (!parent)
+ return -ENOSPC;
+
+ do {
+ if (drm_buddy_block_is_allocated(peer))
+ return -ENOSPC;
+ /* Exit loop if peer block order is equal to block order */
+ if (drm_buddy_block_order(peer) == order)
+ break;
+
+ if (drm_buddy_block_is_split(peer)) {
+ /* Traverse
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/buddy: Fix contiguous memory allocation issues
== Series Details == Series: series starting with [1/3] drm/buddy: Fix contiguous memory allocation issues URL : https://patchwork.freedesktop.org/series/122693/ State : success == Summary == CI Bug Log - changes from CI_DRM_13538 -> Patchwork_122693v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122693v1/index.html Participating hosts (38 -> 38) -- Additional (1): fi-kbl-soraka Missing(1): fi-snb-2520m Known issues Here are the changes found in Patchwork_122693v1 that come from known issues: ### IGT changes ### Issues hit * igt@core_auth@basic-auth: - bat-adlp-11:NOTRUN -> [ABORT][1] ([i915#8011]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122693v1/bat-adlp-11/igt@core_a...@basic-auth.html * igt@gem_busy@busy@all-engines: - bat-mtlp-8: [PASS][2] -> [DMESG-FAIL][3] ([i915#9121]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13538/bat-mtlp-8/igt@gem_busy@b...@all-engines.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122693v1/bat-mtlp-8/igt@gem_busy@b...@all-engines.html * igt@gem_huc_copy@huc-copy: - fi-kbl-soraka: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122693v1/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-kbl-soraka: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613]) +3 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122693v1/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html * igt@i915_selftest@live@gt_heartbeat: - fi-apl-guc: [PASS][6] -> [DMESG-FAIL][7] ([i915#5334]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13538/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122693v1/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@gt_pm: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][8] ([i915#1886] / [i915#7913]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122693v1/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html * igt@i915_selftest@live@requests: - bat-mtlp-8: [PASS][9] -> [ABORT][10] ([i915#7982]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13538/bat-mtlp-8/igt@i915_selftest@l...@requests.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122693v1/bat-mtlp-8/igt@i915_selftest@l...@requests.html * igt@i915_suspend@basic-s3-without-i915: - bat-rpls-1: NOTRUN -> [ABORT][11] ([i915#6687] / [i915#7978] / [i915#8668]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122693v1/bat-rpls-1/igt@i915_susp...@basic-s3-without-i915.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-kbl-soraka: NOTRUN -> [SKIP][12] ([fdo#109271]) +8 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122693v1/fi-kbl-soraka/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html Possible fixes * igt@i915_selftest@live@hangcheck: - bat-rpls-1: [ABORT][13] ([i915#7677]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13538/bat-rpls-1/igt@i915_selftest@l...@hangcheck.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122693v1/bat-rpls-1/igt@i915_selftest@l...@hangcheck.html * igt@i915_selftest@live@mman: - bat-rpls-2: [TIMEOUT][15] ([i915#6794] / [i915#7392]) -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13538/bat-rpls-2/igt@i915_selftest@l...@mman.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122693v1/bat-rpls-2/igt@i915_selftest@l...@mman.html * igt@i915_suspend@basic-s2idle-without-i915: - bat-rpls-2: [WARN][17] ([i915#8747]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13538/bat-rpls-2/igt@i915_susp...@basic-s2idle-without-i915.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122693v1/bat-rpls-2/igt@i915_susp...@basic-s2idle-without-i915.html Warnings * igt@i915_module_load@load: - bat-adlp-11:[ABORT][19] ([i915#4423]) -> [DMESG-WARN][20] ([i915#4423]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13538/bat-adlp-11/igt@i915_module_l...@load.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122693v1/bat-adlp-11/igt@i915_module_l...@load.html * igt@kms_psr@primary_page_flip: - bat-rplp-1: [SKIP][21] ([i915#1072]) -> [ABORT][22] ([i915#8442] / [i915#8668] / [i915#8860]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13538/bat-rplp-1/igt@kms_psr@primary_page_flip.html [22]:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/3] drm/buddy: Fix contiguous memory allocation issues
== Series Details == Series: series starting with [1/3] drm/buddy: Fix contiguous memory allocation issues URL : https://patchwork.freedesktop.org/series/122693/ State : warning == Summary == Error: dim sparse failed /home/kbuild/linux/maintainer-tools/dim: line 50: /home/kbuild/.dimrc: No such file or directory
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/buddy: Fix contiguous memory allocation issues
== Series Details == Series: series starting with [1/3] drm/buddy: Fix contiguous memory allocation issues URL : https://patchwork.freedesktop.org/series/122693/ State : warning == Summary == Error: dim checkpatch failed /home/kbuild/linux/maintainer-tools/dim: line 50: /home/kbuild/.dimrc: No such file or directory
[Intel-gfx] [PATCH 3/3] drm/i915: Remove the contiguous computation and trim
As we have implemented a new method for contiguous allocation
which requires actual size and actual min_block_size, hence we
have moved the roundup and alignment size computation to buddy
allocator. This way gpu drivers pass the required size and
alignment to buddy allocator and rest of the operations taken
care by drm_buddy_alloc_blocks() function.
We have moved the trim function call to the drm_buddy_alloc_blocks()
function as we dont have the roundup or aligned size in our driver.
Now we have all in one place and it will be easy to manage in
buddy allocator.
Signed-off-by: Arunpravin Paneer Selvam
---
drivers/gpu/drm/i915/i915_ttm_buddy_manager.c | 23 +++
1 file changed, 3 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
b/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
index a1bc804cfa15..0d735d5c2b35 100644
--- a/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
+++ b/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
@@ -59,6 +59,9 @@ static int i915_ttm_buddy_man_alloc(struct
ttm_resource_manager *man,
if (place->flags & TTM_PL_FLAG_TOPDOWN)
bman_res->flags |= DRM_BUDDY_TOPDOWN_ALLOCATION;
+ if (place->flags & TTM_PL_FLAG_CONTIGUOUS)
+ bman_res->flags |= DRM_BUDDY_CONTIGUOUS_ALLOCATION;
+
if (place->fpfn || lpfn != man->size)
bman_res->flags |= DRM_BUDDY_RANGE_ALLOCATION;
@@ -72,18 +75,6 @@ static int i915_ttm_buddy_man_alloc(struct
ttm_resource_manager *man,
GEM_BUG_ON(min_page_size < mm->chunk_size);
GEM_BUG_ON(!IS_ALIGNED(size, min_page_size));
- if (place->fpfn + PFN_UP(bman_res->base.size) != place->lpfn &&
- place->flags & TTM_PL_FLAG_CONTIGUOUS) {
- unsigned long pages;
-
- size = roundup_pow_of_two(size);
- min_page_size = size;
-
- pages = size >> ilog2(mm->chunk_size);
- if (pages > lpfn)
- lpfn = pages;
- }
-
if (size > lpfn << PAGE_SHIFT) {
err = -E2BIG;
goto err_free_res;
@@ -107,14 +98,6 @@ static int i915_ttm_buddy_man_alloc(struct
ttm_resource_manager *man,
if (unlikely(err))
goto err_free_blocks;
- if (place->flags & TTM_PL_FLAG_CONTIGUOUS) {
- u64 original_size = (u64)bman_res->base.size;
-
- drm_buddy_block_trim(mm,
-original_size,
-_res->blocks);
- }
-
if (lpfn <= bman->visible_size) {
bman_res->used_visible_size = PFN_UP(bman_res->base.size);
} else {
--
2.25.1
[Intel-gfx] [PATCH 2/3] drm/amdgpu: Remove the contiguous computation and trim
As we have implemented a new method for contiguous allocation
which requires actual size and actual min_block_size, hence we
have moved the roundup and alignment size computation to buddy
allocator. This way gpu drivers pass the required size and
alignment to buddy allocator and rest of the operations taken
care by drm_buddy_alloc_blocks() function.
We have moved the trim function call to the drm_buddy_alloc_blocks()
function as we dont have the roundup or aligned size in our driver.
Now we have all in one place and it will be easy to manage in
buddy allocator.
Signed-off-by: Arunpravin Paneer Selvam
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 58 ++--
1 file changed, 4 insertions(+), 54 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
index c7085a747b03..18f58efc9dc7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
@@ -424,9 +424,9 @@ static int amdgpu_vram_mgr_new(struct ttm_resource_manager
*man,
const struct ttm_place *place,
struct ttm_resource **res)
{
- u64 vis_usage = 0, max_bytes, cur_size, min_block_size;
struct amdgpu_vram_mgr *mgr = to_vram_mgr(man);
struct amdgpu_device *adev = to_amdgpu_device(mgr);
+ u64 vis_usage = 0, max_bytes, min_block_size;
struct amdgpu_vram_mgr_resource *vres;
u64 size, remaining_size, lpfn, fpfn;
struct drm_buddy *mm = >mm;
@@ -474,6 +474,9 @@ static int amdgpu_vram_mgr_new(struct ttm_resource_manager
*man,
if (place->flags & TTM_PL_FLAG_TOPDOWN)
vres->flags |= DRM_BUDDY_TOPDOWN_ALLOCATION;
+ if (place->flags & TTM_PL_FLAG_CONTIGUOUS)
+ vres->flags |= DRM_BUDDY_CONTIGUOUS_ALLOCATION;
+
if (fpfn || lpfn != mgr->mm.size)
/* Allocate blocks in desired range */
vres->flags |= DRM_BUDDY_RANGE_ALLOCATION;
@@ -496,25 +499,6 @@ static int amdgpu_vram_mgr_new(struct ttm_resource_manager
*man,
!(size & (((u64)pages_per_block << PAGE_SHIFT)
- 1)))
min_block_size = (u64)pages_per_block << PAGE_SHIFT;
- cur_size = size;
-
- if (fpfn + size != (u64)place->lpfn << PAGE_SHIFT) {
- /*
-* Except for actual range allocation, modify the size
and
-* min_block_size conforming to continuous flag
enablement
-*/
- if (place->flags & TTM_PL_FLAG_CONTIGUOUS) {
- size = roundup_pow_of_two(size);
- min_block_size = size;
- /*
-* Modify the size value if size is not
-* aligned with min_block_size
-*/
- } else if (!IS_ALIGNED(size, min_block_size)) {
- size = round_up(size, min_block_size);
- }
- }
-
r = drm_buddy_alloc_blocks(mm, fpfn,
lpfn,
size,
@@ -531,40 +515,6 @@ static int amdgpu_vram_mgr_new(struct ttm_resource_manager
*man,
}
mutex_unlock(>lock);
- if (cur_size != size) {
- struct drm_buddy_block *block;
- struct list_head *trim_list;
- u64 original_size;
- LIST_HEAD(temp);
-
- trim_list = >blocks;
- original_size = (u64)vres->base.size;
-
- /*
-* If size value is rounded up to min_block_size, trim the last
-* block to the required size
-*/
- if (!list_is_singular(>blocks)) {
- block = list_last_entry(>blocks, typeof(*block),
link);
- list_move_tail(>link, );
- trim_list =
- /*
-* Compute the original_size value by subtracting the
-* last block size with (aligned size - original size)
-*/
- original_size = amdgpu_vram_mgr_block_size(block) -
(size - cur_size);
- }
-
- mutex_lock(>lock);
- drm_buddy_block_trim(mm,
-original_size,
-trim_list);
- mutex_unlock(>lock);
-
- if (!list_empty())
- list_splice_tail(trim_list, >blocks);
- }
-
vres->base.start = 0;
list_for_each_entry(block, >blocks, link) {
unsigned long start;
--
2.25.1
[Intel-gfx] [PATCH 1/3] drm/buddy: Fix contiguous memory allocation issues
The way now contiguous requests are implemented such that
the size rounded up to power of 2 and the corresponding order
block picked from the freelist.
In addition to the older method, the new method will rounddown
the size to power of 2 and the corresponding order block picked
from the freelist. And for the remaining size we traverse the
tree and try to allocate either from the freelist block's buddy
or from the peer block. If the remaining size from peer/buddy
block is not free, we pick the next freelist block and repeat
the same method.
Moved contiguous/alignment size computation part and trim
function to the drm buddy manager.
Signed-off-by: Arunpravin Paneer Selvam
---
drivers/gpu/drm/drm_buddy.c | 253 ++--
include/drm/drm_buddy.h | 6 +-
2 files changed, 248 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/drm_buddy.c b/drivers/gpu/drm/drm_buddy.c
index 7098f125b54a..220f60c08a03 100644
--- a/drivers/gpu/drm/drm_buddy.c
+++ b/drivers/gpu/drm/drm_buddy.c
@@ -569,6 +569,197 @@ static int __drm_buddy_alloc_range(struct drm_buddy *mm,
return __alloc_range(mm, , start, size, blocks);
}
+static int __alloc_contiguous_block_from_buddy(struct drm_buddy *mm,
+ u64 size,
+ u64 min_block_size,
+ struct drm_buddy_block *block,
+ struct list_head *blocks)
+{
+ struct drm_buddy_block *buddy, *parent = NULL;
+ u64 start, offset = 0;
+ LIST_HEAD(dfs);
+ int err;
+
+ if (!block)
+ return -EINVAL;
+
+ buddy = __get_buddy(block);
+ if (!buddy)
+ return -ENOSPC;
+
+ if (drm_buddy_block_is_allocated(buddy))
+ return -ENOSPC;
+
+ parent = block->parent;
+ if (!parent)
+ return -ENOSPC;
+
+ if (block->parent->right == block) {
+ u64 remaining;
+
+ /* Compute the leftover size for allocation */
+ remaining = max((size - drm_buddy_block_size(mm, buddy)),
+ min_block_size);
+ if (!IS_ALIGNED(remaining, min_block_size))
+ remaining = round_up(remaining, min_block_size);
+
+ /* Check if remaining size is greater than buddy block size */
+ if (drm_buddy_block_size(mm, buddy) < remaining)
+ return -ENOSPC;
+
+ offset = drm_buddy_block_size(mm, buddy) - remaining;
+ }
+
+ list_add(>tmp_link, );
+ start = drm_buddy_block_offset(parent) + offset;
+
+ err = __alloc_range(mm, , start, size, blocks);
+ if (err)
+ return -ENOSPC;
+
+ return 0;
+}
+
+static int __alloc_contiguous_block_from_peer(struct drm_buddy *mm,
+ u64 size,
+ u64 min_block_size,
+ struct drm_buddy_block *block,
+ struct list_head *blocks)
+{
+ struct drm_buddy_block *first, *peer, *tmp;
+ struct drm_buddy_block *parent = NULL;
+ u64 start, offset = 0;
+ unsigned int order;
+ LIST_HEAD(dfs);
+ int err;
+
+ if (!block)
+ return -EINVAL;
+
+ order = drm_buddy_block_order(block);
+ /* Add freelist block to dfs list */
+ list_add(>tmp_link, );
+
+ tmp = block;
+ parent = block->parent;
+ while (parent) {
+ if (block->parent->left == block) {
+ if (parent->left != tmp) {
+ peer = parent->left;
+ break;
+ }
+ } else {
+ if (parent->right != tmp) {
+ peer = parent->right;
+ break;
+ }
+ }
+
+ tmp = parent;
+ parent = tmp->parent;
+ }
+
+ if (!parent)
+ return -ENOSPC;
+
+ do {
+ if (drm_buddy_block_is_allocated(peer))
+ return -ENOSPC;
+ /* Exit loop if peer block order is equal to block order */
+ if (drm_buddy_block_order(peer) == order)
+ break;
+
+ if (drm_buddy_block_is_split(peer)) {
+ /* Traverse down to the block order level */
+ if (block->parent->left == block)
+ peer = peer->right;
+ else
+ peer = peer->left;
+ } else {
+ break;
+ }
+ } while (1);
+
+ if (block->parent->left == block) {
+ u64 remaining;
+
+
[Intel-gfx] ✓ Fi.CI.BAT: success for SDP split for DP-MST (rev2)
== Series Details == Series: SDP split for DP-MST (rev2) URL : https://patchwork.freedesktop.org/series/122460/ State : success == Summary == CI Bug Log - changes from CI_DRM_13536 -> Patchwork_122460v2 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v2/index.html Participating hosts (38 -> 39) -- Additional (2): fi-kbl-soraka fi-pnv-d510 Missing(1): fi-snb-2520m Known issues Here are the changes found in Patchwork_122460v2 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s0@smem: - bat-dg2-9: [PASS][1] -> [INCOMPLETE][2] ([i915#8011]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/bat-dg2-9/igt@gem_exec_suspend@basic...@smem.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v2/bat-dg2-9/igt@gem_exec_suspend@basic...@smem.html * igt@gem_huc_copy@huc-copy: - fi-kbl-soraka: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v2/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-kbl-soraka: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +3 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v2/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html * igt@i915_selftest@live@gt_heartbeat: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][5] ([i915#5334] / [i915#7872]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v2/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@gt_pm: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][6] ([i915#1886] / [i915#7913]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v2/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html * igt@kms_addfb_basic@size-max: - fi-kbl-soraka: NOTRUN -> [INCOMPLETE][7] ([i915#9160]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v2/fi-kbl-soraka/igt@kms_addfb_ba...@size-max.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-kbl-soraka: NOTRUN -> [SKIP][8] ([fdo#109271]) +8 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v2/fi-kbl-soraka/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html * igt@kms_psr@primary_mmap_gtt: - bat-rplp-1: NOTRUN -> [ABORT][9] ([i915#8442] / [i915#8469] / [i915#8668]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v2/bat-rplp-1/igt@kms_psr@primary_mmap_gtt.html * igt@kms_psr@primary_page_flip: - fi-pnv-d510:NOTRUN -> [SKIP][10] ([fdo#109271]) +30 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v2/fi-pnv-d510/igt@kms_psr@primary_page_flip.html Warnings * igt@kms_psr@sprite_plane_onoff: - bat-rplp-1: [ABORT][11] ([i915#8442] / [i915#8668] / [i915#8712]) -> [SKIP][12] ([i915#1072]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13536/bat-rplp-1/igt@kms_psr@sprite_plane_onoff.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122460v2/bat-rplp-1/igt@kms_psr@sprite_plane_onoff.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334 [i915#7872]: https://gitlab.freedesktop.org/drm/intel/issues/7872 [i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913 [i915#8011]: https://gitlab.freedesktop.org/drm/intel/issues/8011 [i915#8442]: https://gitlab.freedesktop.org/drm/intel/issues/8442 [i915#8469]: https://gitlab.freedesktop.org/drm/intel/issues/8469 [i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668 [i915#8712]: https://gitlab.freedesktop.org/drm/intel/issues/8712 [i915#9160]: https://gitlab.freedesktop.org/drm/intel/issues/9160 Build changes - * Linux: CI_DRM_13536 -> Patchwork_122460v2 CI-20190529: 20190529 CI_DRM_13536: 7a825a06c6ee60a6586ddf8b4adb03ea5262bda7 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7444: 7444 Patchwork_122460v2: 7a825a06c6ee60a6586ddf8b4adb03ea5262bda7 @ git://anongit.freedesktop.org/gfx-ci/linux ### Linux commits 24d34e8b4971 drm/i915/display: configure SDP split for DP-MST 488b37d3fb4d drm/i915/display: update intel_dp_has_audio to support MST 950aca0ada01 drm/i915/display: combine DP audio compute config steps c2736b7b178d drm/i915/display: remove redundant parameter from sdp split update == Logs == For more details see:
Re: [Intel-gfx] [REGRESSION] HDMI connector detection broken in 6.3 on Intel(R) Celeron(R) N3060 integrated graphics
On Tue, Aug 15, 2023 at 11:12:46AM +0300, Jani Nikula wrote: > On Mon, 14 Aug 2023, Imre Deak wrote: > > On Sun, Aug 13, 2023 at 03:41:30PM +0200, Linux regression tracking > > (Thorsten Leemhuis) wrote: > > Hi, > > > >> On 11.08.23 20:10, Mikhail Rudenko wrote: > >> > On 2023-08-11 at 08:45 +02, Thorsten Leemhuis > >> > wrote: > >> >> On 10.08.23 21:33, Mikhail Rudenko wrote: > >> >>> The following is a copy an issue I posted to drm/i915 gitlab [1] two > >> >>> months ago. I repost it to the mailing lists in hope that it will help > >> >>> the right people pay attention to it. > >> >> > >> >> Thx for your report. Wonder why Dmitry (who authored a4e771729a51) or > >> >> Thomas (who committed it) it didn't look into this, but maybe the i915 > >> >> devs didn't forward the report to them. > >> > >> For the record: they did, and Jani mentioned already. Sorry, should have > >> phrased this differently. > >> > >> >> Let's see if these mails help. Just wondering: does reverting > >> >> a4e771729a51 from 6.5-rc5 or drm-tip help as well? > >> > > >> > I've redone my tests with 6.5-rc5, and here are the results: > >> > (1) 6.5-rc5 -> still affected > >> > (2) 6.5-rc5 + revert a4e771729a51 -> not affected > >> > (3) 6.5-rc5 + two patches [1][2] suggested on i915 gitlab by @ideak -> > >> > not affected (!) > >> > > >> > Should we somehow tell regzbot about (3)? > >> > >> That's good to know, thx. But the more important things are: > >> > >> * When will those be merged? They are not yet in next yet afaics, so it > >> might take some time to mainline them, especially at this point of the > >> devel cycle. Imre, could you try to prod the right people so that these > >> are ideally upstreamed rather sooner than later, as they fix a regression? > > > > I think the patches ([1] and [2]) could be merged via the drm-intel-next > > (drm-intel-fixes) tree Cc'ing also stable. Jani, is this ok? > > It's fine by me, but need drm-misc maintainer ack to merge [1] via > drm-intel. That's fine for me Maxime signature.asc Description: PGP signature
Re: [Intel-gfx] [PATCH v3] drm/i915: Fix Kconfig error for CONFIG_DRM_I915
On Sun, 20 Aug 2023, Wang Jinchao wrote:
> When CONFIG_DRM_I915 is set to 'y' and CONFIG_BACKLIGHT_CLASS_DEVICE
> is set to 'm', we encountered an ld.lld error during the build process:
>
> ld.lld: error: undefined symbol: backlight_device_get_by_name
> >>> referenced by intel_backlight.c:955
> >>> vmlinux.o:(intel_backlight_device_register)
>
> ld.lld: error: undefined symbol: backlight_device_register
> >>> referenced by intel_backlight.c:971
> >>> vmlinux.o:(intel_backlight_device_register)
>
> ld.lld: error: undefined symbol: backlight_device_unregister
> >>> referenced by intel_backlight.c:999
> >>> vmlinux.o:(intel_backlight_device_unregister)
>
> This issue occurred because intel_backlight_device_register and
> intel_backlight_device_unregister were enclosed within
> \#if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE) and #endif directives.
> However, according to Kconfig, CONFIG_DRM_I915 will select
> BACKLIGHT_CLASS_DEVICE only if ACPI is enabled.
> This led to an error when ACPI is not enabled.
> Change IS_ENABLED to IS_REACHABLE and use IS_REACHABLE to encompass
> the implementation of intel_connector_register() to solve this issue.
I told you in [1] what the real fix is.
The IS_REACHABLE() solution has been suggested a number of times, but I
think it's creating an unexpected and silent failure configuration. I
think IS_REACHABLE() is the wrong thing to do in most cases.
BR,
Jani.
[1] https://lore.kernel.org/r/87o7jaythm@intel.com
>
> Signed-off-by: Wang Jinchao
> ---
> drivers/gpu/drm/i915/display/intel_backlight.c | 2 +-
> drivers/gpu/drm/i915/display/intel_backlight.h | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c
> b/drivers/gpu/drm/i915/display/intel_backlight.c
> index 2e8f17c04522..d812cdc74a84 100644
> --- a/drivers/gpu/drm/i915/display/intel_backlight.c
> +++ b/drivers/gpu/drm/i915/display/intel_backlight.c
> @@ -795,7 +795,7 @@ void intel_backlight_enable(const struct intel_crtc_state
> *crtc_state,
> mutex_unlock(>display.backlight.lock);
> }
>
> -#if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
> +#if IS_REACHABLE(CONFIG_BACKLIGHT_CLASS_DEVICE)
> static u32 intel_panel_get_backlight(struct intel_connector *connector)
> {
> struct drm_i915_private *i915 = to_i915(connector->base.dev);
> diff --git a/drivers/gpu/drm/i915/display/intel_backlight.h
> b/drivers/gpu/drm/i915/display/intel_backlight.h
> index 339643f63897..207fe1c613d8 100644
> --- a/drivers/gpu/drm/i915/display/intel_backlight.h
> +++ b/drivers/gpu/drm/i915/display/intel_backlight.h
> @@ -36,7 +36,7 @@ u32 intel_backlight_invert_pwm_level(struct intel_connector
> *connector, u32 leve
> u32 intel_backlight_level_to_pwm(struct intel_connector *connector, u32
> level);
> u32 intel_backlight_level_from_pwm(struct intel_connector *connector, u32
> val);
>
> -#if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
> +#if IS_REACHABLE(CONFIG_BACKLIGHT_CLASS_DEVICE)
> int intel_backlight_device_register(struct intel_connector *connector);
> void intel_backlight_device_unregister(struct intel_connector *connector);
> #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH] drm/i915/display: add lock while printing frontbuffer tracking bits to debugfs
On Mon, 2023-08-14 at 19:34 +0300, Juha-Pekka Heikkila wrote:
> Add missing spin_lock/unlock
>
> Signed-off-by: Juha-Pekka Heikkila
Reviewed-by: Jouni Högander
> ---
> drivers/gpu/drm/i915/display/intel_display_debugfs.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 63c1fb9e479f..f05b52381a83 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -43,12 +43,16 @@ static int i915_frontbuffer_tracking(struct
> seq_file *m, void *unused)
> {
> struct drm_i915_private *dev_priv = node_to_i915(m->private);
>
> + spin_lock(_priv->display.fb_tracking.lock);
> +
> seq_printf(m, "FB tracking busy bits: 0x%08x\n",
> dev_priv->display.fb_tracking.busy_bits);
>
> seq_printf(m, "FB tracking flip bits: 0x%08x\n",
> dev_priv->display.fb_tracking.flip_bits);
>
> + spin_unlock(_priv->display.fb_tracking.lock);
> +
> return 0;
> }
>
