Re: [Intel-gfx] [PATCH 10/42] drm/i915/tc: remove "fia" from intel_tc_port_fia_max_lane_count()
> From: Luca Coelho
>
> It is irrelevant for the caller that the max lane count is being derived from
> a FIA
> register, so having "fia" in the function name is irrelevant. Rename the
> function accordingly.
>
LGTM.
Reviewed-by: Suraj Kandpal
> Signed-off-by: Luca Coelho
> Reviewed-by: Lucas De Marchi
> Link: https://lore.kernel.org/r/2023072121.369227-5-
> luciano.coe...@intel.com
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 2 +-
> drivers/gpu/drm/i915/display/intel_dp.c | 4 ++--
> drivers/gpu/drm/i915/display/intel_tc.c | 4 ++--
> drivers/gpu/drm/i915/display/intel_tc.h | 2 +-
> 4 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 26e256165b80..a5918bf30c31 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -58,7 +58,7 @@ static u8 intel_cx0_get_owned_lane_mask(struct
> drm_i915_private *i915,
>* In DP-alt with pin assignment D, only PHY lane 0 is owned
>* by display and lane 1 is owned by USB.
>*/
> - return intel_tc_port_fia_max_lane_count(dig_port) > 2
> + return intel_tc_port_max_lane_count(dig_port) > 2
> ? INTEL_CX0_BOTH_LANES : INTEL_CX0_LANE0; }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 9f40da20e88d..84584864511b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -306,13 +306,13 @@ static int
> intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> int source_max = intel_dp_max_source_lane_count(dig_port);
> int sink_max = intel_dp->max_sink_lane_count;
> - int fia_max = intel_tc_port_fia_max_lane_count(dig_port);
> + int port_max = intel_tc_port_max_lane_count(dig_port);
> int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp-
> >lttpr_common_caps);
>
> if (lttpr_max)
> sink_max = min(sink_max, lttpr_max);
>
> - return min3(source_max, sink_max, fia_max);
> + return min3(source_max, sink_max, port_max);
> }
>
> int intel_dp_max_lane_count(struct intel_dp *intel_dp) diff --git
> a/drivers/gpu/drm/i915/display/intel_tc.c
> b/drivers/gpu/drm/i915/display/intel_tc.c
> index 43b8eeba26f8..3c94bbcb5497 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.c
> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> @@ -337,7 +337,7 @@ static int intel_tc_port_get_max_lane_count(struct
> intel_digital_port *dig_port)
> }
> }
>
> -int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
> +int intel_tc_port_max_lane_count(struct intel_digital_port *dig_port)
> {
> struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> struct intel_tc_port *tc = to_tc_port(dig_port); @@ -589,7 +589,7
> @@ static bool tc_phy_verify_legacy_or_dp_alt_mode(struct intel_tc_port
> *tc,
> struct intel_digital_port *dig_port = tc->dig_port;
> int max_lanes;
>
> - max_lanes = intel_tc_port_fia_max_lane_count(dig_port);
> + max_lanes = intel_tc_port_max_lane_count(dig_port);
> if (tc->mode == TC_PORT_LEGACY) {
> drm_WARN_ON(>drm, max_lanes != 4);
> return true;
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.h
> b/drivers/gpu/drm/i915/display/intel_tc.h
> index ffc0e2a74e43..80a61e52850e 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.h
> +++ b/drivers/gpu/drm/i915/display/intel_tc.h
> @@ -20,7 +20,7 @@ bool intel_tc_port_connected(struct intel_encoder
> *encoder); bool intel_tc_port_connected_locked(struct intel_encoder
> *encoder);
>
> u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port
> *dig_port); -int intel_tc_port_fia_max_lane_count(struct intel_digital_port
> *dig_port);
> +int intel_tc_port_max_lane_count(struct intel_digital_port *dig_port);
> void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
> int required_lanes);
>
> --
> 2.40.1
Re: [Intel-gfx] [PATCH v3 4/4] drm/i915/tc: remove "fia" from intel_tc_port_fia_max_lane_count()
> It is irrelevant for the caller that the max lane count is being derived from
> a FIA
> register, so having "fia" in the function name is irrelevant. Rename the
> function accordingly.
>
> Signed-off-by: Luca Coelho
LGTM.
Reviewed-by: Suraj Kandpal
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 2 +-
> drivers/gpu/drm/i915/display/intel_dp.c | 4 ++--
> drivers/gpu/drm/i915/display/intel_tc.c | 4 ++--
> drivers/gpu/drm/i915/display/intel_tc.h | 2 +-
> 4 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 1b00ef2c6185..6d4f7b20ce85 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2534,7 +2534,7 @@ static void intel_cx0_phy_lane_reset(struct
> drm_i915_private *i915, {
> enum port port = encoder->port;
> enum phy phy = intel_port_to_phy(i915, port);
> - bool both_lanes =
> intel_tc_port_fia_max_lane_count(enc_to_dig_port(encoder)) > 2;
> + bool both_lanes =
> +intel_tc_port_max_lane_count(enc_to_dig_port(encoder)) > 2;
> u8 lane_mask = lane_reversal ? INTEL_CX0_LANE1 :
> INTEL_CX0_LANE0;
> u32 lane_pipe_reset = both_lanes ?
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 03675620e3ea..b974af839acb 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -306,13 +306,13 @@ static int
> intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> int source_max = intel_dp_max_source_lane_count(dig_port);
> int sink_max = intel_dp->max_sink_lane_count;
> - int fia_max = intel_tc_port_fia_max_lane_count(dig_port);
> + int port_max = intel_tc_port_max_lane_count(dig_port);
> int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp-
> >lttpr_common_caps);
>
> if (lttpr_max)
> sink_max = min(sink_max, lttpr_max);
>
> - return min3(source_max, sink_max, fia_max);
> + return min3(source_max, sink_max, port_max);
> }
>
> int intel_dp_max_lane_count(struct intel_dp *intel_dp) diff --git
> a/drivers/gpu/drm/i915/display/intel_tc.c
> b/drivers/gpu/drm/i915/display/intel_tc.c
> index 43b8eeba26f8..3c94bbcb5497 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.c
> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> @@ -337,7 +337,7 @@ static int intel_tc_port_get_max_lane_count(struct
> intel_digital_port *dig_port)
> }
> }
>
> -int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
> +int intel_tc_port_max_lane_count(struct intel_digital_port *dig_port)
> {
> struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> struct intel_tc_port *tc = to_tc_port(dig_port); @@ -589,7 +589,7
> @@ static bool tc_phy_verify_legacy_or_dp_alt_mode(struct intel_tc_port
> *tc,
> struct intel_digital_port *dig_port = tc->dig_port;
> int max_lanes;
>
> - max_lanes = intel_tc_port_fia_max_lane_count(dig_port);
> + max_lanes = intel_tc_port_max_lane_count(dig_port);
> if (tc->mode == TC_PORT_LEGACY) {
> drm_WARN_ON(>drm, max_lanes != 4);
> return true;
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.h
> b/drivers/gpu/drm/i915/display/intel_tc.h
> index ffc0e2a74e43..80a61e52850e 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.h
> +++ b/drivers/gpu/drm/i915/display/intel_tc.h
> @@ -20,7 +20,7 @@ bool intel_tc_port_connected(struct intel_encoder
> *encoder); bool intel_tc_port_connected_locked(struct intel_encoder
> *encoder);
>
> u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port
> *dig_port); -int intel_tc_port_fia_max_lane_count(struct intel_digital_port
> *dig_port);
> +int intel_tc_port_max_lane_count(struct intel_digital_port *dig_port);
> void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
> int required_lanes);
>
> --
> 2.39.2
Re: [Intel-gfx] [PATCH 09/42] drm/i915/tc: move legacy code out of the main _max_lane_count() func
> -Original Message-
> From: Intel-gfx On Behalf Of Lucas
> De Marchi
> Sent: Wednesday, August 23, 2023 10:37 PM
> To: intel...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Coelho, Luciano
> Subject: [Intel-gfx] [PATCH 09/42] drm/i915/tc: move legacy code out of the
> main _max_lane_count() func
>
> From: Luca Coelho
>
> This makes the code a bit more symmetric and readable, especially when we
> start adding more display version-specific alternatives.
>
> Signed-off-by: Luca Coelho
> Link: https://lore.kernel.org/r/2023072121.369227-4-
> luciano.coe...@intel.com
> ---
> drivers/gpu/drm/i915/display/intel_tc.c | 32 +++--
> 1 file changed, 19 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
> b/drivers/gpu/drm/i915/display/intel_tc.c
> index de848b329f4b..43b8eeba26f8 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.c
> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> @@ -311,23 +311,12 @@ static int mtl_tc_port_get_max_lane_count(struct
> intel_digital_port *dig_port)
> }
> }
>
> -int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
> +static int intel_tc_port_get_max_lane_count(struct intel_digital_port
> +*dig_port)
> {
> struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> - struct intel_tc_port *tc = to_tc_port(dig_port);
> - enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
> intel_wakeref_t wakeref;
> - u32 lane_mask;
> -
> - if (!intel_phy_is_tc(i915, phy) || tc->mode != TC_PORT_DP_ALT)
> - return 4;
> + u32 lane_mask = 0;
>
> - assert_tc_cold_blocked(tc);
> -
> - if (DISPLAY_VER(i915) >= 14)
> - return mtl_tc_port_get_max_lane_count(dig_port);
> -
> - lane_mask = 0;
> with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE,
> wakeref)
> lane_mask = intel_tc_port_get_lane_mask(dig_port);
>
> @@ -348,6 +337,23 @@ int intel_tc_port_fia_max_lane_count(struct
> intel_digital_port *dig_port)
> }
> }
Rather than having two functions:
mtl_tc_port_get_max_lane_count()
& intel_tc_port_get_max_lane_count() that both call:
with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref)
lane_mask = intel_tc_port_get_lane_mask(dig_port);
to get the lane mask the us directly pass the lane_mask to the above two
functions
and make the call for getting the lane_mask common i.e lets call it in
intel_tc_port_fia_max_lane_count().
Regards,
Suraj Kandpal
>
> +int intel_tc_port_fia_max_lane_count(struct intel_digital_port
> +*dig_port) {
> + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> + struct intel_tc_port *tc = to_tc_port(dig_port);
> + enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
> +
> + if (!intel_phy_is_tc(i915, phy) || tc->mode != TC_PORT_DP_ALT)
> + return 4;
> +
> + assert_tc_cold_blocked(tc);
> +
> + if (DISPLAY_VER(i915) >= 14)
> + return mtl_tc_port_get_max_lane_count(dig_port);
> +
> + return intel_tc_port_get_max_lane_count(dig_port);
> +}
> +
> void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
> int required_lanes)
> {
> --
> 2.40.1
Re: [Intel-gfx] [PATCH 28/42] drm/i915/xe2lpd: enable odd size and panning for planar yuv on xe2lpd
> Subject: [PATCH 28/42] drm/i915/xe2lpd: enable odd size and panning for
> planar yuv on xe2lpd
>
> From: Juha-Pekka Heikkilä
>
> Enable odd size and panning for planar yuv formats.
>
> Cc: Suraj Kandpal
> Signed-off-by: Juha-Pekka Heikkilä
> Signed-off-by: Lucas De Marchi
Maybe add the Bspec/ HSD reference in here otherwise
LGTM
Reviewed-by: Suraj Kandpal
> ---
> drivers/gpu/drm/i915/display/intel_atomic_plane.c | 8
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index fb13f0bb8c52..da6ee7f0675a 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -986,6 +986,14 @@ int intel_plane_check_src_coordinates(struct
> intel_plane_state *plane_state)
> if (fb->format->format == DRM_FORMAT_RGB565 && rotated) {
> hsub = 2;
> vsub = 2;
> + } else if (DISPLAY_VER(i915) >= 20 &&
> + intel_format_info_is_yuv_semiplanar(fb->format, fb-
> >modifier)) {
> + /*
> + * This allow NV12 and P0xx formats to have odd size and/or
> odd
> + * source coordinates on DISPLAY_VER(i915) >= 20
> + */
> + hsub = 1;
> + vsub = 1;
> } else {
> hsub = fb->format->hsub;
> vsub = fb->format->vsub;
> --
> 2.40.1
[Intel-gfx] ✓ Fi.CI.BAT: success for Panel replay phase1 implementation (rev6)
== Series Details == Series: Panel replay phase1 implementation (rev6) URL : https://patchwork.freedesktop.org/series/94470/ State : success == Summary == CI Bug Log - changes from CI_DRM_13558 -> Patchwork_94470v6 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/index.html Participating hosts (39 -> 39) -- Additional (1): bat-dg2-9 Missing(1): fi-snb-2520m Known issues Here are the changes found in Patchwork_94470v6 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-rplp-1: NOTRUN -> [SKIP][1] ([i915#7456]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/bat-rplp-1/igt@debugfs_t...@basic-hwmon.html * igt@gem_exec_suspend@basic-s0@smem: - bat-jsl-3: [PASS][2] -> [ABORT][3] ([i915#5122]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13558/bat-jsl-3/igt@gem_exec_suspend@basic...@smem.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/bat-jsl-3/igt@gem_exec_suspend@basic...@smem.html * igt@gem_mmap@basic: - bat-dg2-9: NOTRUN -> [SKIP][4] ([i915#4083]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/bat-dg2-9/igt@gem_m...@basic.html * igt@gem_mmap_gtt@basic: - bat-dg2-9: NOTRUN -> [SKIP][5] ([i915#4077]) +2 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/bat-dg2-9/igt@gem_mmap_...@basic.html * igt@gem_render_tiled_blits@basic: - bat-dg2-9: NOTRUN -> [SKIP][6] ([i915#4079]) +1 similar issue [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/bat-dg2-9/igt@gem_render_tiled_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-rplp-1: NOTRUN -> [SKIP][7] ([i915#3282]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/bat-rplp-1/igt@gem_tiled_pread_basic.html * igt@i915_pm_backlight@basic-brightness: - bat-dg2-9: NOTRUN -> [SKIP][8] ([i915#5354] / [i915#7561]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/bat-dg2-9/igt@i915_pm_backli...@basic-brightness.html * igt@i915_pm_rps@basic-api: - bat-dg2-9: NOTRUN -> [SKIP][9] ([i915#6621]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/bat-dg2-9/igt@i915_pm_...@basic-api.html * igt@i915_suspend@basic-s3-without-i915: - bat-jsl-3: [PASS][10] -> [FAIL][11] ([fdo#103375]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13558/bat-jsl-3/igt@i915_susp...@basic-s3-without-i915.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/bat-jsl-3/igt@i915_susp...@basic-s3-without-i915.html * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: - bat-dg2-9: NOTRUN -> [SKIP][12] ([i915#5190]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/bat-dg2-9/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html * igt@kms_addfb_basic@basic-y-tiled-legacy: - bat-dg2-9: NOTRUN -> [SKIP][13] ([i915#4215] / [i915#5190]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/bat-dg2-9/igt@kms_addfb_ba...@basic-y-tiled-legacy.html * igt@kms_addfb_basic@framebuffer-vs-set-tiling: - bat-dg2-9: NOTRUN -> [SKIP][14] ([i915#4212]) +7 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/bat-dg2-9/igt@kms_addfb_ba...@framebuffer-vs-set-tiling.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - bat-rplp-1: NOTRUN -> [SKIP][15] ([i915#4103] / [i915#4213]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/bat-rplp-1/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html - bat-dg2-9: NOTRUN -> [SKIP][16] ([i915#4103] / [i915#4213]) +1 similar issue [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/bat-dg2-9/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html * igt@kms_force_connector_basic@force-load-detect: - bat-rplp-1: NOTRUN -> [SKIP][17] ([fdo#109285]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/bat-rplp-1/igt@kms_force_connector_ba...@force-load-detect.html - bat-dg2-9: NOTRUN -> [SKIP][18] ([fdo#109285]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/bat-dg2-9/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_force_connector_basic@prune-stale-modes: - bat-dg2-9: NOTRUN -> [SKIP][19] ([i915#5274]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/bat-dg2-9/igt@kms_force_connector_ba...@prune-stale-modes.html * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence: - bat-dg2-11: NOTRUN -> [SKIP][20] ([i915#1845] / [i915#5354]) +3 similar
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Panel replay phase1 implementation (rev6)
== Series Details == Series: Panel replay phase1 implementation (rev6) URL : https://patchwork.freedesktop.org/series/94470/ State : warning == Summary == Error: dim sparse failed /home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No such file or directory
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Panel replay phase1 implementation (rev6)
== Series Details == Series: Panel replay phase1 implementation (rev6) URL : https://patchwork.freedesktop.org/series/94470/ State : warning == Summary == Error: dim checkpatch failed /home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No such file or directory
[Intel-gfx] ✓ Fi.CI.BAT: success for eDP DSC fixes (rev2)
== Series Details == Series: eDP DSC fixes (rev2) URL : https://patchwork.freedesktop.org/series/122792/ State : success == Summary == CI Bug Log - changes from CI_DRM_13558 -> Patchwork_122792v2 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122792v2/index.html Participating hosts (39 -> 40) -- Additional (2): fi-kbl-soraka bat-dg2-9 Missing(1): fi-snb-2520m Known issues Here are the changes found in Patchwork_122792v2 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-rplp-1: NOTRUN -> [SKIP][1] ([i915#7456]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122792v2/bat-rplp-1/igt@debugfs_t...@basic-hwmon.html * igt@gem_huc_copy@huc-copy: - fi-kbl-soraka: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#2190]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122792v2/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-kbl-soraka: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4613]) +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122792v2/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html * igt@gem_mmap@basic: - bat-dg2-9: NOTRUN -> [SKIP][4] ([i915#4083]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122792v2/bat-dg2-9/igt@gem_m...@basic.html * igt@gem_mmap_gtt@basic: - bat-dg2-9: NOTRUN -> [SKIP][5] ([i915#4077]) +2 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122792v2/bat-dg2-9/igt@gem_mmap_...@basic.html * igt@gem_render_tiled_blits@basic: - bat-dg2-9: NOTRUN -> [SKIP][6] ([i915#4079]) +1 similar issue [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122792v2/bat-dg2-9/igt@gem_render_tiled_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-rplp-1: NOTRUN -> [SKIP][7] ([i915#3282]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122792v2/bat-rplp-1/igt@gem_tiled_pread_basic.html * igt@i915_pm_backlight@basic-brightness: - bat-dg2-9: NOTRUN -> [SKIP][8] ([i915#5354] / [i915#7561]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122792v2/bat-dg2-9/igt@i915_pm_backli...@basic-brightness.html * igt@i915_pm_rps@basic-api: - bat-dg2-9: NOTRUN -> [SKIP][9] ([i915#6621]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122792v2/bat-dg2-9/igt@i915_pm_...@basic-api.html * igt@i915_selftest@live@gt_pm: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][10] ([i915#1886] / [i915#7913]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122792v2/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: - bat-dg2-9: NOTRUN -> [SKIP][11] ([i915#5190]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122792v2/bat-dg2-9/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html * igt@kms_addfb_basic@basic-y-tiled-legacy: - bat-dg2-9: NOTRUN -> [SKIP][12] ([i915#4215] / [i915#5190]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122792v2/bat-dg2-9/igt@kms_addfb_ba...@basic-y-tiled-legacy.html * igt@kms_addfb_basic@framebuffer-vs-set-tiling: - bat-dg2-9: NOTRUN -> [SKIP][13] ([i915#4212]) +7 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122792v2/bat-dg2-9/igt@kms_addfb_ba...@framebuffer-vs-set-tiling.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-kbl-soraka: NOTRUN -> [SKIP][14] ([fdo#109271]) +8 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122792v2/fi-kbl-soraka/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - bat-rplp-1: NOTRUN -> [SKIP][15] ([i915#4103] / [i915#4213]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122792v2/bat-rplp-1/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html - bat-dg2-9: NOTRUN -> [SKIP][16] ([i915#4103] / [i915#4213]) +1 similar issue [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122792v2/bat-dg2-9/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html * igt@kms_force_connector_basic@force-load-detect: - bat-rplp-1: NOTRUN -> [SKIP][17] ([fdo#109285]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122792v2/bat-rplp-1/igt@kms_force_connector_ba...@force-load-detect.html - bat-dg2-9: NOTRUN -> [SKIP][18] ([fdo#109285]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122792v2/bat-dg2-9/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_force_connector_basic@prune-stale-modes: - bat-dg2-9:
[Intel-gfx] [PATCH v2 6/6] drm/i915/dp_link_training: Emit a link-status=Bad uevent with trigger property
When a link-training attempt fails, emit a uevent to user space that includes the trigger property, which in this case will be link-statue=Bad. This will allow userspace to parse the uevent property and better understand the reason for the previous modeset failure. Signed-off-by: Gil Dekel V2: - init link_status_property inline. --- drivers/gpu/drm/i915/display/intel_dp.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index e8b10f59e141..328e9f030033 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -42,6 +42,7 @@ #include #include #include +#include #include "g4x_dp.h" #include "i915_drv.h" @@ -5995,6 +5996,8 @@ static void intel_dp_modeset_retry_work_fn(struct work_struct *work) struct intel_dp *intel_dp = container_of(work, typeof(*intel_dp), modeset_retry_work); struct drm_connector *connector = _dp->attached_connector->base; + struct drm_property *link_status_property = + connector->dev->mode_config.link_status_property; /* Set the connector's (and possibly all its downstream MST ports') link * status to BAD. @@ -6011,7 +6014,7 @@ static void intel_dp_modeset_retry_work_fn(struct work_struct *work) } mutex_unlock(>dev->mode_config.mutex); /* Send Hotplug uevent so userspace can reprobe */ - drm_kms_helper_connector_hotplug_event(connector); + drm_sysfs_connector_property_event(connector, link_status_property); } bool -- Gil Dekel, Software Engineer, Google / ChromeOS Display and Graphics
[Intel-gfx] [PATCH v2 5/6] drm/i915/dp_link_training: Set all downstream MST ports to BAD before retrying
Before sending a uevent to userspace in order to trigger a corrective
modeset, we change the failing connector's link-status to BAD. However,
the downstream MST branch ports are left in their original GOOD state.
This patch utilizes the drm helper function
drm_dp_set_mst_topology_link_status() to rectify this and set all
downstream MST connectors' link-status to BAD before emitting the uevent
to userspace.
Signed-off-by: Gil Dekel
---
drivers/gpu/drm/i915/display/intel_dp.c | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 42353b1ac487..e8b10f59e141 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5995,16 +5995,20 @@ static void intel_dp_modeset_retry_work_fn(struct
work_struct *work)
struct intel_dp *intel_dp =
container_of(work, typeof(*intel_dp), modeset_retry_work);
struct drm_connector *connector = _dp->attached_connector->base;
- drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s]\n", connector->base.id,
- connector->name);
- /* Grab the locks before changing connector property*/
- mutex_lock(>dev->mode_config.mutex);
- /* Set connector link status to BAD and send a Uevent to notify
-* userspace to do a modeset.
+ /* Set the connector's (and possibly all its downstream MST ports') link
+* status to BAD.
*/
+ mutex_lock(>dev->mode_config.mutex);
+ drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] link status %d -> %d\n",
+ connector->base.id, connector->name,
+ connector->state->link_status, DRM_MODE_LINK_STATUS_BAD);
drm_connector_set_link_status_property(connector,
DRM_MODE_LINK_STATUS_BAD);
+ if (intel_dp->is_mst) {
+ drm_dp_set_mst_topology_link_status(_dp->mst_mgr,
+ DRM_MODE_LINK_STATUS_BAD);
+ }
mutex_unlock(>dev->mode_config.mutex);
/* Send Hotplug uevent so userspace can reprobe */
drm_kms_helper_connector_hotplug_event(connector);
--
Gil Dekel, Software Engineer, Google / ChromeOS Display and Graphics
[Intel-gfx] [PATCH v2 4/6] drm/i915: Move DP modeset_retry_work into intel_dp
Currently, link-training fallback is only implemented for SST, so having
modeset_retry_work in intel_connector makes sense. However, we hope to
implement link training fallback for MST in a follow-up patchset, so
moving modeset_retry_work to indel_dp will make handling both SST and
MST connectors simpler. This patch does exactly that, and updates all
modeset_retry_work dependencies to use an intel_dp instead.
Credit: this patch is a rebase of Lyude Pual's original patch:
https://patchwork.freedesktop.org/patch/216627/?series=41576=3
Signed-off-by: Gil Dekel
---
drivers/gpu/drm/i915/display/intel_display.c | 14 +++---
drivers/gpu/drm/i915/display/intel_display_types.h | 6 +++---
drivers/gpu/drm/i915/display/intel_dp.c| 11 ---
.../gpu/drm/i915/display/intel_dp_link_training.c | 3 +--
4 files changed, 19 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index db3c26e013e3..2ec75aa0b4ee 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7962,20 +7962,28 @@ void i830_disable_pipe(struct drm_i915_private
*dev_priv, enum pipe pipe)
void intel_hpd_poll_fini(struct drm_i915_private *i915)
{
- struct intel_connector *connector;
struct drm_connector_list_iter conn_iter;
+ struct intel_connector *connector;
+ struct intel_dp *intel_dp;
+ struct intel_encoder *encoder;
/* Kill all the work that may have been queued by hpd. */
drm_connector_list_iter_begin(>drm, _iter);
for_each_intel_connector_iter(connector, _iter) {
- if (connector->modeset_retry_work.func)
- cancel_work_sync(>modeset_retry_work);
if (connector->hdcp.shim) {
cancel_delayed_work_sync(>hdcp.check_work);
cancel_work_sync(>hdcp.prop_work);
}
}
drm_connector_list_iter_end(_iter);
+
+ for_each_intel_dp(>drm, encoder) {
+ if (encoder->type == DRM_MODE_CONNECTOR_eDP ||
+ encoder->type == DRM_MODE_CONNECTOR_DisplayPort) {
+ intel_dp = enc_to_intel_dp(encoder);
+ cancel_work_sync(_dp->modeset_retry_work);
+ }
+ }
}
bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 731f2ec04d5c..b92bb69a3fe4 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -620,9 +620,6 @@ struct intel_connector {
struct intel_dp *mst_port;
- /* Work struct to schedule a uevent on link train failure */
- struct work_struct modeset_retry_work;
-
struct intel_hdcp hdcp;
};
@@ -1779,6 +1776,9 @@ struct intel_dp {
/* Displayport compliance testing */
struct intel_dp_compliance compliance;
+ /* Work struct to schedule a uevent on link train failure */
+ struct work_struct modeset_retry_work;
+
/* Downstream facing port caps */
struct {
int min_tmds_clock, max_tmds_clock;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 01b180c8d9bd..42353b1ac487 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5992,12 +5992,9 @@ static bool intel_edp_init_connector(struct intel_dp
*intel_dp,
static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
{
- struct intel_connector *intel_connector;
- struct drm_connector *connector;
-
- intel_connector = container_of(work, typeof(*intel_connector),
- modeset_retry_work);
- connector = _connector->base;
+ struct intel_dp *intel_dp =
+ container_of(work, typeof(*intel_dp), modeset_retry_work);
+ struct drm_connector *connector = _dp->attached_connector->base;
drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s]\n", connector->base.id,
connector->name);
@@ -6027,7 +6024,7 @@ intel_dp_init_connector(struct intel_digital_port
*dig_port,
int type;
/* Initialize the work for modeset in case of link train failure */
- INIT_WORK(_connector->modeset_retry_work,
+ INIT_WORK(_dp->modeset_retry_work,
intel_dp_modeset_retry_work_fn);
if (drm_WARN(dev, dig_port->max_lanes < 1,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 31d0d7854003..87d13cd03ef5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -1063,7 +1063,6 @@ intel_dp_link_train_phy(struct intel_dp
[Intel-gfx] [PATCH v2 3/6] drm/dp_mst: Add drm_dp_set_mst_topology_link_status()
Unlike SST, MST can support multiple displays connected to a single
connector. However, this also means that if the DisplayPort link to the
top-level MST branch device becomes unstable, then every single branch
device has an unstable link.
Since there are multiple downstream ports per connector, setting the
link status of the parent mstb's port to BAD is not enough. All of the
downstream mstb ports must also have their link status set to BAD.
This aligns to how the DP link status logic in DRM works. We notify
userspace that all of the mstb ports need retraining and apply new lower
bandwidth constraints to all future atomic commits on the topology that
follow.
Since any driver supporting MST needs to figure out which connectors
live downstream on an MST topology and update their link status in order
to retrain MST links properly, we add the
drm_dp_set_mst_topology_link_status() helper. This helper simply marks
the link status of all connectors living in that topology as bad. We
will make use of this helper in i915 later in this series.
Credit: this patch is a refactor of Lyude Pual's original patch:
https://patchwork.kernel.org/project/dri-devel/patch/20180308232421.14049-5-ly...@redhat.com/
Signed-off-by: Gil Dekel
---
drivers/gpu/drm/display/drm_dp_mst_topology.c | 39 +++
include/drm/display/drm_dp_mst_helper.h | 3 ++
2 files changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c
b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index ed96cfcfa304..17cbadfb6ccb 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -3566,6 +3566,45 @@ int drm_dp_get_vc_payload_bw(const struct
drm_dp_mst_topology_mgr *mgr,
}
EXPORT_SYMBOL(drm_dp_get_vc_payload_bw);
+/**
+ * drm_dp_set_mst_topology_link_status() - set all downstream MST ports' link
status
+ * @mgr: MST topology manager to set state for
+ * @status: The new status to set the MST topology to
+ *
+ * Set all downstream ports' link-status within the topology to the given
status.
+ */
+void drm_dp_set_mst_topology_link_status(struct drm_dp_mst_topology_mgr *mgr,
+enum drm_link_status status)
+{
+ struct drm_dp_mst_port *port;
+ struct drm_dp_mst_branch *rmstb;
+ struct drm_dp_mst_branch *mstb =
+ drm_dp_mst_topology_get_mstb_validated(mgr, mgr->mst_primary);
+
+ list_for_each_entry_reverse(port, >ports, next) {
+ struct drm_connector *connector = port->connector;
+
+ if (connector) {
+ mutex_lock(>dev->mode_config.mutex);
+ drm_dbg_kms(
+ connector->dev,
+ "[MST-CONNECTOR:%d:%s] link status %d -> %d\n",
+ connector->base.id, connector->name,
+ connector->state->link_status, status);
+ connector->state->link_status = status;
+ mutex_unlock(>dev->mode_config.mutex);
+ }
+
+ rmstb = drm_dp_mst_topology_get_mstb_validated(mstb->mgr,
+ port->mstb);
+ if (rmstb) {
+ drm_dp_set_mst_topology_link_status(rmstb->mgr, status);
+ drm_dp_mst_topology_put_mstb(rmstb);
+ }
+ }
+}
+EXPORT_SYMBOL(drm_dp_set_mst_topology_link_status);
+
/**
* drm_dp_read_mst_cap() - check whether or not a sink supports MST
* @aux: The DP AUX channel to use
diff --git a/include/drm/display/drm_dp_mst_helper.h
b/include/drm/display/drm_dp_mst_helper.h
index ed5c9660563c..855d488bf364 100644
--- a/include/drm/display/drm_dp_mst_helper.h
+++ b/include/drm/display/drm_dp_mst_helper.h
@@ -832,6 +832,9 @@ struct edid *drm_dp_mst_get_edid(struct drm_connector
*connector,
int drm_dp_get_vc_payload_bw(const struct drm_dp_mst_topology_mgr *mgr,
int link_rate, int link_lane_count);
+void drm_dp_set_mst_topology_link_status(struct drm_dp_mst_topology_mgr *mgr,
+enum drm_link_status status);
+
int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc);
void drm_dp_mst_update_slots(struct drm_dp_mst_topology_state *mst_state,
uint8_t link_encoding_cap);
--
Gil Dekel, Software Engineer, Google / ChromeOS Display and Graphics
[Intel-gfx] [PATCH v2 2/6] drm/i915/dp_link_training: Add a final failing state to link training fallback for MST
Currently, MST link training has no fallback. This means that if an MST
base connector fails to link-train once, the training completely fails,
which makes this case significantly more common than a complete SST link
training failure.
Similar to the final failure state of SST, this patch zeros out both
max_link_rate and max_link_lane_count. In addition, it stops resetting
MST params so the zeroing of the HBR fields stick. This ensures that
the MST base connector's modes will be completely pruned, since it is
effectively left with 0Gbps bandwidth.
Signed-off-by: Gil Dekel
---
drivers/gpu/drm/i915/display/intel_dp.c | 27 ++-
drivers/gpu/drm/i915/display/intel_dp.h | 2 +-
.../drm/i915/display/intel_dp_link_training.c | 8 +++---
3 files changed, 20 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 2152ddbab557..01b180c8d9bd 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -630,7 +630,7 @@ static bool intel_dp_can_link_train_fallback_for_edp(struct
intel_dp *intel_dp,
return true;
}
-int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
+void intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
int link_rate, u8 lane_count)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
@@ -638,18 +638,23 @@ int intel_dp_get_link_train_fallback_values(struct
intel_dp *intel_dp,
/*
* TODO: Enable fallback on MST links once MST link compute can handle
-* the fallback params.
+* the fallback params. For now, similar to the SST case, ensure all of
+* the base connector's modes are pruned in the next connector probe by
+* effectively reducing its bandwidth to 0 so userspace can ignore it
+* within the next modeset attempt.
*/
if (intel_dp->is_mst) {
drm_err(>drm, "Link Training Unsuccessful\n");
- return -1;
+ intel_dp->max_link_rate = 0;
+ intel_dp->max_link_lane_count = 0;
+ return;
}
if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) {
drm_dbg_kms(>drm,
"Retrying Link training for eDP with max
parameters\n");
intel_dp->use_max_params = true;
- return 0;
+ return;
}
index = intel_dp_rate_index(intel_dp->common_rates,
@@ -662,7 +667,7 @@ int intel_dp_get_link_train_fallback_values(struct intel_dp
*intel_dp,
lane_count)) {
drm_dbg_kms(>drm,
"Retrying Link training for eDP with same
parameters\n");
- return 0;
+ return;
}
intel_dp->max_link_rate = intel_dp_common_rate(intel_dp, index
- 1);
intel_dp->max_link_lane_count = lane_count;
@@ -673,7 +678,7 @@ int intel_dp_get_link_train_fallback_values(struct intel_dp
*intel_dp,
lane_count >> 1))
{
drm_dbg_kms(>drm,
"Retrying Link training for eDP with same
parameters\n");
- return 0;
+ return;
}
intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
intel_dp->max_link_lane_count = lane_count >> 1;
@@ -686,10 +691,7 @@ int intel_dp_get_link_train_fallback_values(struct
intel_dp *intel_dp,
*/
intel_dp->max_link_rate = 0;
intel_dp->max_link_lane_count = 0;
- return 0;
}
-
- return 0;
}
u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
@@ -5310,10 +5312,11 @@ intel_dp_detect(struct drm_connector *connector,
intel_dp_configure_mst(intel_dp);
/*
-* TODO: Reset link params when switching to MST mode, until MST
-* supports link training fallback params.
+* Note: Even though MST link training fallback is not yet implemented,
+* do not reset. This is because the base connector needs to have all
+* its modes pruned when link training for the MST port fails.
*/
- if (intel_dp->reset_link_params || intel_dp->is_mst) {
+ if (intel_dp->reset_link_params) {
intel_dp_reset_max_link_params(intel_dp);
intel_dp->reset_link_params = false;
}
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
b/drivers/gpu/drm/i915/display/intel_dp.h
index 788a577ebe16..7388510e0cb2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -40,7 +40,7 @@ bool intel_dp_init_connector(struct intel_digital_port
[Intel-gfx] [PATCH v2 1/6] drm/i915/dp_link_training: Add a final failing state to link training fallback
Instead of silently giving up when all link-training fallback values are
exhausted, this patch modifies the fallback's failure branch to reduces
both max_link_lane_count and max_link_rate to zero (0) and continues to
emit uevents until userspace stops attempting to modeset.
By doing so, we ensure the failing connector, which is in
link-status=Bad, has all its modes pruned (due to effectively having a
bandwidth of 0Gbps).
It is then the userspace's responsibility to ignore connectors with no
modes, even if they are marked as connected.
Signed-off-by: Gil Dekel
---
drivers/gpu/drm/i915/display/intel_dp.c | 18 --
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 7067ee3a4bd3..2152ddbab557 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -276,8 +276,12 @@ static int intel_dp_common_len_rate_limit(const struct
intel_dp *intel_dp,
static int intel_dp_common_rate(struct intel_dp *intel_dp, int index)
{
+ /* This occurs when max link rate drops to 0 via link training
fallback*/
+ if (index < 0)
+ return 0;
+
if (drm_WARN_ON(_to_i915(intel_dp)->drm,
- index < 0 || index >= intel_dp->num_common_rates))
+ index >= intel_dp->num_common_rates))
return 162000;
return intel_dp->common_rates[index];
@@ -318,6 +322,9 @@ static int intel_dp_max_common_lane_count(struct intel_dp
*intel_dp)
int intel_dp_max_lane_count(struct intel_dp *intel_dp)
{
switch (intel_dp->max_link_lane_count) {
+ /* This occurs when max link lane count drops to 0 via link training
fallback*/
+ case 0:
+ return 0;
case 1:
case 2:
case 4:
@@ -672,7 +679,14 @@ int intel_dp_get_link_train_fallback_values(struct
intel_dp *intel_dp,
intel_dp->max_link_lane_count = lane_count >> 1;
} else {
drm_err(>drm, "Link Training Unsuccessful\n");
- return -1;
+ /*
+* Ensure all of the connector's modes are pruned in the next
+* probe by effectively reducing its bandwidth to 0 so userspace
+* can ignore it within the next modeset attempt.
+*/
+ intel_dp->max_link_rate = 0;
+ intel_dp->max_link_lane_count = 0;
+ return 0;
}
return 0;
--
Gil Dekel, Software Engineer, Google / ChromeOS Display and Graphics
[Intel-gfx] [PATCH v2 0/6] drm/i915/dp_link_training: Define a final failure state when link training fails
Next version of https://patchwork.freedesktop.org/series/122643/ Reorganize into: 1) Add for final failure state for SST and MST link training fallback. 2) Add a DRM helper for setting downstream MST ports' link-status state. 3) Make handling SST and MST connectors simpler via intel_dp. 4) Update link-status for downstream MST ports. 5) Emit a uevent with the "link-status" trigger property. Gil Dekel (6): drm/i915/dp_link_training: Add a final failing state to link training fallback drm/i915/dp_link_training: Add a final failing state to link training fallback for MST drm/dp_mst: Add drm_dp_set_mst_topology_link_status() drm/i915: Move DP modeset_retry_work into intel_dp drm/i915/dp_link_training: Set all downstream MST ports to BAD before retrying drm/i915/dp_link_training: Emit a link-status=Bad uevent with trigger property drivers/gpu/drm/display/drm_dp_mst_topology.c | 39 ++ drivers/gpu/drm/i915/display/intel_display.c | 14 +++- .../drm/i915/display/intel_display_types.h| 6 +- drivers/gpu/drm/i915/display/intel_dp.c | 75 --- drivers/gpu/drm/i915/display/intel_dp.h | 2 +- .../drm/i915/display/intel_dp_link_training.c | 11 ++- include/drm/display/drm_dp_mst_helper.h | 3 + 7 files changed, 110 insertions(+), 40 deletions(-) -- Gil Dekel, Software Engineer, Google / ChromeOS Display and Graphics
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for eDP DSC fixes (rev2)
== Series Details == Series: eDP DSC fixes (rev2) URL : https://patchwork.freedesktop.org/series/122792/ State : warning == Summary == Error: dim sparse failed /home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No such file or directory
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for eDP DSC fixes (rev2)
== Series Details ==
Series: eDP DSC fixes (rev2)
URL : https://patchwork.freedesktop.org/series/122792/
State : warning
== Summary ==
Error: dim checkpatch failed
a622a8c6cd95 drm/display/dp: Default 8 bpc support when DSC is supported
-:26: ERROR:SPACING: space required before the open parenthesis '('
#26: FILE: drivers/gpu/drm/display/drm_dp_helper.c:2451:
+ if(!drm_dp_sink_supports_dsc(dsc_dpcd))
total: 1 errors, 0 warnings, 0 checks, 21 lines checked
35c5c7dc2d80 drivers/drm/i915: Honor limits->max_bpp while computing DSC max
input bpp
-:25: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#25: FILE: drivers/gpu/drm/i915/display/intel_dp.c:2068:
+ min(max_bpc,
conn_state->max_requested_bpc));
total: 0 errors, 1 warnings, 0 checks, 12 lines checked
[Intel-gfx] [PATCH v4 6/6] drm/i915/panelreplay: enable/disable panel replay
TRANS_DP2_CTL register is programmed to enable panel replay from source
and sink is enabled through panel replay dpcd configuration address.
Bspec: 1407940617
v1: Initial version.
v2:
- Use pr_* flags instead psr_* flags. [Jouni]
- Remove intel_dp_is_edp check as edp1.5 also has panel replay. [Jouni]
v3: cover letter updated and selective fetch condition check is added
before updating its bit in PSR2_MAN_TRK_CTL register. [Jouni]
Note: Initial plan is to enable panel replay in full-screen live active
frame update mode. In a incremental approach panel replay will be enabled
in selctive update mode if there is any gap in curent implementation.
Cc: Jouni Högander
Signed-off-by: Animesh Manna
---
.../drm/i915/display/intel_display_types.h| 1 +
drivers/gpu/drm/i915/display/intel_psr.c | 72 ++-
2 files changed, 57 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 97cef458f42b..46f2e8a42d1d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1696,6 +1696,7 @@ struct intel_psr {
u16 su_y_granularity;
bool source_panel_replay_support;
bool sink_panel_replay_support;
+ bool panel_replay_enabled;
u32 dc3co_exitline;
u32 dc3co_exit_delay;
struct delayed_work dc3co_work;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index c92acc7be4f1..ccb714f2c9e6 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -596,8 +596,14 @@ static void intel_psr_enable_sink(struct intel_dp
*intel_dp)
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
u8 dpcd_val = DP_PSR_ENABLE;
- /* Enable ALPM at sink for psr2 */
+ if (intel_dp->psr.panel_replay_enabled) {
+ drm_dp_dpcd_writeb(_dp->aux, PANEL_REPLAY_CONFIG,
+ DP_PANEL_REPLAY_ENABLE);
+ return;
+ }
+
if (intel_dp->psr.psr2_enabled) {
+ /* Enable ALPM at sink for psr2 */
drm_dp_dpcd_writeb(_dp->aux, DP_RECEIVER_ALPM_CONFIG,
DP_ALPM_ENABLE |
DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
@@ -747,6 +753,18 @@ static int psr2_block_count(struct intel_dp *intel_dp)
return psr2_block_count_lines(intel_dp) / 4;
}
+static void dg2_activate_panel_replay(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+ if (intel_dp->psr.psr2_sel_fetch_enabled)
+ intel_de_rmw(dev_priv,
PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder),
+0, ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE);
+
+ intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0,
+TRANS_DP2_PANEL_REPLAY_ENABLE);
+}
+
static void hsw_activate_psr2(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -1295,6 +1313,9 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
crtc_state->infoframes.enable |=
intel_hdmi_infoframe_enable(DP_SDP_VSC);
intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state,
_state->psr_vsc);
+
+ drm_dbg_kms(_priv->drm, "has_pr = %d, has_psr = %d, has_psr2 = %d,
infoframes_enable = %d\n",
+ crtc_state->has_panel_replay, crtc_state->has_psr,
crtc_state->has_psr2, crtc_state->infoframes.enable);
}
void intel_psr_get_config(struct intel_encoder *encoder,
@@ -1310,18 +1331,23 @@ void intel_psr_get_config(struct intel_encoder *encoder,
return;
intel_dp = _port->dp;
- if (!CAN_PSR(intel_dp))
+ if (!(CAN_PSR(intel_dp) || CAN_PANEL_REPLAY(intel_dp)))
return;
mutex_lock(_dp->psr.lock);
if (!intel_dp->psr.enabled)
goto unlock;
- /*
-* Not possible to read EDP_PSR/PSR2_CTL registers as it is
-* enabled/disabled because of frontbuffer tracking and others.
-*/
- pipe_config->has_psr = true;
+ if (intel_dp->psr.panel_replay_enabled) {
+ pipe_config->has_panel_replay = true;
+ } else {
+ /*
+* Not possible to read EDP_PSR/PSR2_CTL registers as it is
+* enabled/disabled because of frontbuffer tracking and others.
+*/
+ pipe_config->has_psr = true;
+ }
+
pipe_config->has_psr2 = intel_dp->psr.psr2_enabled;
pipe_config->infoframes.enable |=
intel_hdmi_infoframe_enable(DP_SDP_VSC);
@@ -1358,8 +1384,10 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
lockdep_assert_held(_dp->psr.lock);
- /* psr1 and psr2 are mutually exclusive.*/
-
[Intel-gfx] [PATCH v4 5/6] drm/i915/panelreplay: Enable panel replay dpcd initialization for DP
Due to similarity panel replay dpcd initialization got added in psr function which is specific for edp panel. This patch enables panel replay initialization for dp connector. Signed-off-by: Animesh Manna --- drivers/gpu/drm/i915/display/intel_psr.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 8dd61c62492d..c92acc7be4f1 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -2732,6 +2732,9 @@ void intel_psr_init(struct intel_dp *intel_dp) if (!(HAS_PSR(dev_priv) || HAS_PANEL_REPLAY(dev_priv))) return; + if (!intel_dp_is_edp(intel_dp)) + intel_psr_init_dpcd(intel_dp); + /* * HSW spec explicitly says PSR is tied to port A. * BDW+ platforms have a instance of PSR registers per transcoder but -- 2.29.0
[Intel-gfx] [PATCH v4 2/6] drm/i915/panelreplay: Added HAS_PANEL_REPLAY() macro
Platforms having Display 13 and above will support panel replay feature of DP 2.0 monitor. Added a HAS_PANEL_REPLAY() macro to check for panel replay capability. v1: Initial version. v2: DISPLAY_VER() removed as HAS_DP20() is having platform check. [Jouni] Cc: Jouni Högander Signed-off-by: Animesh Manna --- drivers/gpu/drm/i915/display/intel_display_device.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h index 8198401aa5be..ab615a3199da 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.h +++ b/drivers/gpu/drm/i915/display/intel_display_device.h @@ -61,6 +61,7 @@ struct drm_printer; #define HAS_MSO(i915) (DISPLAY_VER(i915) >= 12) #define HAS_OVERLAY(i915) (DISPLAY_INFO(i915)->has_overlay) #define HAS_PSR(i915) (DISPLAY_INFO(i915)->has_psr) +#define HAS_PANEL_REPLAY(dev_priv) (HAS_DP20(dev_priv)) #define HAS_PSR_HW_TRACKING(i915) (DISPLAY_INFO(i915)->has_psr_hw_tracking) #define HAS_PSR2_SEL_FETCH(i915) (DISPLAY_VER(i915) >= 12) #define HAS_SAGV(i915) (DISPLAY_VER(i915) >= 9 && !IS_LP(i915)) -- 2.29.0
[Intel-gfx] [PATCH v4 4/6] drm/i915/panelreplay: Initializaton and compute config for panel replay
Modify existing PSR implementation to enable panel replay feature of DP 2.0
which is similar to PSR feature of EDP panel. There is different DPCD
address to check panel capability compare to PSR and vsc sdp header
is different.
v1: Initial version.
v2:
- Set source_panel_replay_support flag under HAS_PNEL_REPLAY() check. [Jouni]
- Code restructured around intel_panel_replay_init
and renamed to intel_panel_replay_init_dpcd. [Jouni]
- Remove the initial code modification around has_psr2 flag. [Jouni]
- Add CAN_PANEL_REPLAY() in intel_encoder_can_psr which is used to
enable in intel_psr_post_plane_update. [Jouni]
v3:
- Initialize both psr and panel-replay. [Jouni]
- Initialize both panel replay and psr if detected. [Jouni]
- Refactoring psr function by introducing _psr_compute_config(). [Jouni]
- Add check for !is_edp while deriving source_panel_replay_support. [Jouni]
- Enable panel replay dpcd initialization in a separate patch. [Jouni]
v4:
- HAS_PANEL_REPLAY() check not needed during sink capability check.[Jouni]
- Set either panel replay source support or psr.[Jouni]
Cc: Jouni Högander
Signed-off-by: Animesh Manna
---
.../drm/i915/display/intel_display_types.h| 12 ++-
drivers/gpu/drm/i915/display/intel_dp.c | 44 --
drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +
drivers/gpu/drm/i915/display/intel_psr.c | 87 +--
4 files changed, 107 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 731f2ec04d5c..97cef458f42b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1202,6 +1202,7 @@ struct intel_crtc_state {
bool has_psr2;
bool enable_psr2_sel_fetch;
bool req_psr2_sdp_prior_scanline;
+ bool has_panel_replay;
bool wm_level_disabled;
u32 dc3co_exitline;
u16 su_y_granularity;
@@ -1693,6 +1694,8 @@ struct intel_psr {
bool irq_aux_error;
u16 su_w_granularity;
u16 su_y_granularity;
+ bool source_panel_replay_support;
+ bool sink_panel_replay_support;
u32 dc3co_exitline;
u32 dc3co_exit_delay;
struct delayed_work dc3co_work;
@@ -1983,12 +1986,15 @@ dp_to_lspcon(struct intel_dp *intel_dp)
#define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \
(intel_dp)->psr.source_support)
+#define CAN_PANEL_REPLAY(intel_dp) ((intel_dp)->psr.sink_panel_replay_support
&& \
+ (intel_dp)->psr.source_panel_replay_support)
+
static inline bool intel_encoder_can_psr(struct intel_encoder *encoder)
{
- if (!intel_encoder_is_dp(encoder))
+ if (intel_encoder_is_dp(encoder) || (encoder->type ==
INTEL_OUTPUT_DP_MST))
+ return CAN_PSR(enc_to_intel_dp(encoder)) ||
CAN_PANEL_REPLAY(enc_to_intel_dp(encoder));
+ else
return false;
-
- return CAN_PSR(enc_to_intel_dp(encoder));
}
static inline struct intel_digital_port *
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 7067ee3a4bd3..b3301cf0da0a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2337,12 +2337,22 @@ static void intel_dp_compute_vsc_colorimetry(const
struct intel_crtc_state *crtc
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- /*
-* Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
-* VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
-* Colorimetry Format indication.
-*/
- vsc->revision = 0x5;
+ if (crtc_state->has_panel_replay) {
+ /*
+* Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
+* VSC SDP supporting 3D stereo, Panel Replay, and Pixel
+* Encoding/Colorimetry Format indication.
+*/
+ vsc->revision = 0x7;
+ } else {
+ /*
+* Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
+* VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
+* Colorimetry Format indication.
+*/
+ vsc->revision = 0x5;
+ }
+
vsc->length = 0x13;
/* DP 1.4a spec, Table 2-120 */
@@ -2451,6 +2461,21 @@ void intel_dp_compute_psr_vsc_sdp(struct intel_dp
*intel_dp,
vsc->revision = 0x4;
vsc->length = 0xe;
}
+ } else if (crtc_state->has_panel_replay) {
+ if (intel_dp->psr.colorimetry_support &&
+ intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
+ /* [Panel Replay with colorimetry info] */
+
[Intel-gfx] [PATCH v4 3/6] drm/i915/psr: Move psr specific dpcd init into own function
From: Jouni Högander
This patch is preparing adding panel replay specific dpcd init.
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 39 +---
1 file changed, 22 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 72887c29fb51..b1c0494826f9 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -472,27 +472,22 @@ static void intel_dp_get_su_granularity(struct intel_dp
*intel_dp)
intel_dp->psr.su_y_granularity = y;
}
-void intel_psr_init_dpcd(struct intel_dp *intel_dp)
+static void _psr_init_dpcd(struct intel_dp *intel_dp)
{
- struct drm_i915_private *dev_priv =
+ struct drm_i915_private *i915 =
to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
- drm_dp_dpcd_read(_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
-sizeof(intel_dp->psr_dpcd));
-
- if (!intel_dp->psr_dpcd[0])
- return;
- drm_dbg_kms(_priv->drm, "eDP panel supports PSR version %x\n",
+ drm_dbg_kms(>drm, "eDP panel supports PSR version %x\n",
intel_dp->psr_dpcd[0]);
if (drm_dp_has_quirk(_dp->desc, DP_DPCD_QUIRK_NO_PSR)) {
- drm_dbg_kms(_priv->drm,
+ drm_dbg_kms(>drm,
"PSR support not currently available for this
panel\n");
return;
}
if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) {
- drm_dbg_kms(_priv->drm,
+ drm_dbg_kms(>drm,
"Panel lacks power state control, PSR cannot be
enabled\n");
return;
}
@@ -501,7 +496,7 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
intel_dp->psr.sink_sync_latency =
intel_dp_get_sink_sync_latency(intel_dp);
- if (DISPLAY_VER(dev_priv) >= 9 &&
+ if (DISPLAY_VER(i915) >= 9 &&
(intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) {
bool y_req = intel_dp->psr_dpcd[1] &
DP_PSR2_SU_Y_COORDINATE_REQUIRED;
@@ -519,14 +514,24 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
* GTC first.
*/
intel_dp->psr.sink_psr2_support = y_req && alpm;
- drm_dbg_kms(_priv->drm, "PSR2 %ssupported\n",
+ drm_dbg_kms(>drm, "PSR2 %ssupported\n",
intel_dp->psr.sink_psr2_support ? "" : "not ");
+ }
+}
- if (intel_dp->psr.sink_psr2_support) {
- intel_dp->psr.colorimetry_support =
- intel_dp_get_colorimetry_status(intel_dp);
- intel_dp_get_su_granularity(intel_dp);
- }
+void intel_psr_init_dpcd(struct intel_dp *intel_dp)
+{
+ drm_dp_dpcd_read(_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
+sizeof(intel_dp->psr_dpcd));
+
+ if (intel_dp->psr_dpcd[0])
+ _psr_init_dpcd(intel_dp);
+ /* TODO: Add PR case here */
+
+ if (intel_dp->psr.sink_psr2_support) {
+ intel_dp->psr.colorimetry_support =
+ intel_dp_get_colorimetry_status(intel_dp);
+ intel_dp_get_su_granularity(intel_dp);
}
}
--
2.29.0
[Intel-gfx] [PATCH v4 1/6] drm/panelreplay: dpcd register definition for panelreplay
DPCD register definition added to check and enable panel replay capability of the sink. Cc: Jouni Högander Signed-off-by: Animesh Manna --- include/drm/display/drm_dp.h | 11 +++ 1 file changed, 11 insertions(+) diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h index e69cece404b3..a38dc5f1731e 100644 --- a/include/drm/display/drm_dp.h +++ b/include/drm/display/drm_dp.h @@ -543,6 +543,10 @@ /* DFP Capability Extension */ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT0x0a3 /* 2.0 */ +#define DP_PANEL_REPLAY_CAP 0x0b0 +# define DP_PANEL_REPLAY_SUPPORT(1 << 0) +# define DP_PANEL_REPLAY_SU_SUPPORT (1 << 1) + /* Link Configuration */ #defineDP_LINK_BW_SET 0x100 # define DP_LINK_RATE_TABLE0x00/* eDP 1.4 */ @@ -716,6 +720,13 @@ #define DP_BRANCH_DEVICE_CTRL 0x1a1 # define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0) +#define PANEL_REPLAY_CONFIG 0x1b0 +# define DP_PANEL_REPLAY_ENABLE (1 << 0) +# define DP_PANEL_REPLAY_UNRECOVERABLE_ERROR(1 << 3) +# define DP_PANEL_REPLAY_RFB_STORAGE_ERROR (1 << 4) +# define DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR (1 << 5) +# define DP_PANEL_REPLAY_SU_ENABLE (1 << 6) + #define DP_PAYLOAD_ALLOCATE_SET0x1c0 #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1 #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2 -- 2.29.0
[Intel-gfx] [PATCH v4 0/6] Panel replay phase1 implementation
Panel Replay is a power saving feature for DP 2.0 monitor and similar to PSR on EDP. These patches are basic enablement patches added on top of existing psr framework to enable full-screen live active frame update mode of panel replay. Panel replay also can be enabled in selective update mode which will be enabled in a incremental approach. As per current design panel replay priority is higher than psr. intel_dp->psr.panel_replay_enabled flag indicate panel replay is enabled. intel_dp->psr.panel_replay_enabled + intel_dp->psr.psr2_enabled indicates panel replay is enabled in selective update mode. intel_dp->psr.panel_replay_enabled + intel_dp->psr.psr2_enabled + intel_psr.selective_fetch enabled indicates panel replay is enabled in selective update mode with selective fetch. PSR replated flags remain same like before. Note: The patches are under testing by using panel replay emulator and panel is not avalible. Cc: Jouni Högander Signed-off-by: Animesh Manna Animesh Manna (5): drm/panelreplay: dpcd register definition for panelreplay drm/i915/panelreplay: Added HAS_PANEL_REPLAY() macro drm/i915/panelreplay: Initializaton and compute config for panel replay drm/i915/panelreplay: Enable panel replay dpcd initialization for DP drm/i915/panelreplay: enable/disable panel replay Jouni Högander (1): drm/i915/psr: Move psr specific dpcd init into own function .../drm/i915/display/intel_display_device.h | 1 + .../drm/i915/display/intel_display_types.h| 13 +- drivers/gpu/drm/i915/display/intel_dp.c | 44 +++- drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 + drivers/gpu/drm/i915/display/intel_psr.c | 197 -- include/drm/display/drm_dp.h | 11 + 6 files changed, 199 insertions(+), 70 deletions(-) -- 2.29.0
[Intel-gfx] [PATCH 1/2] drm/display/dp: Default 8 bpc support when DSC is supported
As per DP v1.4, a DP DSC Sink device shall support 8bpc in DPCD 6Ah.
Apparently some panels that do support DSC, are not setting the bit for
8bpc.
So always assume 8bpc support by DSC decoder, when DSC is claimed to be
supported.
v2: Use helper to check dsc support. (Ankit)
Signed-off-by: Ankit Nautiyal
---
drivers/gpu/drm/display/drm_dp_helper.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dp_helper.c
b/drivers/gpu/drm/display/drm_dp_helper.c
index e6a78fd32380..309fc10cde78 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -2447,14 +2447,19 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8
dsc_dpcd[DP_DSC_RECEIVER_CAP_S
u8 dsc_bpc[3])
{
int num_bpc = 0;
+
+ if(!drm_dp_sink_supports_dsc(dsc_dpcd))
+ return 0;
+
u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT];
if (color_depth & DP_DSC_12_BPC)
dsc_bpc[num_bpc++] = 12;
if (color_depth & DP_DSC_10_BPC)
dsc_bpc[num_bpc++] = 10;
- if (color_depth & DP_DSC_8_BPC)
- dsc_bpc[num_bpc++] = 8;
+
+ /* A DP DSC Sink devices shall support 8 bpc. */
+ dsc_bpc[num_bpc++] = 8;
return num_bpc;
}
--
2.40.1
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display/vrr: Compute VRR min/max based on highest clock mode for DRRS panel
== Series Details == Series: drm/i915/display/vrr: Compute VRR min/max based on highest clock mode for DRRS panel URL : https://patchwork.freedesktop.org/series/122812/ State : success == Summary == CI Bug Log - changes from CI_DRM_13558 -> Patchwork_122812v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122812v1/index.html Participating hosts (39 -> 38) -- Missing(1): fi-snb-2520m Known issues Here are the changes found in Patchwork_122812v1 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-rplp-1: NOTRUN -> [SKIP][1] ([i915#7456]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122812v1/bat-rplp-1/igt@debugfs_t...@basic-hwmon.html * igt@gem_tiled_pread_basic: - bat-rplp-1: NOTRUN -> [SKIP][2] ([i915#3282]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122812v1/bat-rplp-1/igt@gem_tiled_pread_basic.html * igt@i915_selftest@live@migrate: - bat-dg2-11: [PASS][3] -> [DMESG-WARN][4] ([i915#7699]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13558/bat-dg2-11/igt@i915_selftest@l...@migrate.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122812v1/bat-dg2-11/igt@i915_selftest@l...@migrate.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - bat-rplp-1: NOTRUN -> [SKIP][5] ([i915#4103] / [i915#4213]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122812v1/bat-rplp-1/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html * igt@kms_force_connector_basic@force-load-detect: - bat-rplp-1: NOTRUN -> [SKIP][6] ([fdo#109285]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122812v1/bat-rplp-1/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence: - bat-dg2-11: NOTRUN -> [SKIP][7] ([i915#1845] / [i915#5354]) +3 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122812v1/bat-dg2-11/igt@kms_pipe_crc_ba...@nonblocking-crc-frame-sequence.html * igt@kms_psr@primary_page_flip: - bat-rplp-1: NOTRUN -> [ABORT][8] ([i915#8442] / [i915#8668] / [i915#8860]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122812v1/bat-rplp-1/igt@kms_psr@primary_page_flip.html Possible fixes * igt@i915_selftest@live@gt_heartbeat: - fi-apl-guc: [DMESG-FAIL][9] ([i915#5334]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13558/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122812v1/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845 [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282 [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103 [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213 [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334 [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354 [i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456 [i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699 [i915#8442]: https://gitlab.freedesktop.org/drm/intel/issues/8442 [i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668 [i915#8860]: https://gitlab.freedesktop.org/drm/intel/issues/8860 Build changes - * Linux: CI_DRM_13558 -> Patchwork_122812v1 CI-20190529: 20190529 CI_DRM_13558: 2d5f57f6436263ecb456228603356d81173b1ceb @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7451: 5d48d1fb231f449fe2f80cda14ea7a1ecfda59fa @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_122812v1: 2d5f57f6436263ecb456228603356d81173b1ceb @ git://anongit.freedesktop.org/gfx-ci/linux ### Linux commits edefbdd29440 drm/i915/display/vrr: Compute VRR min/max based on highest clock mode for DRRS panel == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122812v1/index.html
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/display/vrr: Compute VRR min/max based on highest clock mode for DRRS panel
== Series Details == Series: drm/i915/display/vrr: Compute VRR min/max based on highest clock mode for DRRS panel URL : https://patchwork.freedesktop.org/series/122812/ State : warning == Summary == Error: dim sparse failed /home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No such file or directory
[Intel-gfx] [PATCH] drm/i915/display/vrr: Compute VRR min/max based on highest clock mode for DRRS panel
In case of a DRRS panel, there is a preferred panel mode and there is
a downclock mode with lower pixel clock. But the Vtotal for both remains
the same. This means even in downclocking mode the VRR Vtotal min/max
should remain the same.
So in this case always use the highest clock mode to compute VRR
parameters.
Cc: Ville Syrjälä
Cc: Jani Nikula
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/display/intel_dp.c | 4 ++--
drivers/gpu/drm/i915/display/intel_dp.h | 2 ++
drivers/gpu/drm/i915/display/intel_vrr.c | 7 ---
3 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 7067ee3a4bd3..c572a018ce57 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1509,8 +1509,8 @@ static bool has_seamless_m_n(struct intel_connector
*connector)
intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
}
-static int intel_dp_mode_clock(const struct intel_crtc_state *crtc_state,
- const struct drm_connector_state *conn_state)
+int intel_dp_mode_clock(const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state)
{
struct intel_connector *connector =
to_intel_connector(conn_state->connector);
const struct drm_display_mode *adjusted_mode =
_state->hw.adjusted_mode;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
b/drivers/gpu/drm/i915/display/intel_dp.h
index 788a577ebe16..3c9866356359 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -119,6 +119,8 @@ u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
bool bigjoiner);
bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp,
int hdisplay, int clock);
+int intel_dp_mode_clock(const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state);
static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
{
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
b/drivers/gpu/drm/i915/display/intel_vrr.c
index 88e4759b538b..18a4e0e4e696 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -8,6 +8,7 @@
#include "i915_reg.h"
#include "intel_de.h"
#include "intel_display_types.h"
+#include "intel_dp.h"
#include "intel_vrr.h"
bool intel_vrr_is_capable(struct intel_connector *connector)
@@ -106,7 +107,7 @@ intel_vrr_compute_config(struct intel_crtc_state
*crtc_state,
to_intel_connector(conn_state->connector);
struct drm_display_mode *adjusted_mode = _state->hw.adjusted_mode;
const struct drm_display_info *info = >base.display_info;
- int vmin, vmax;
+ int vmin, vmax, clock = intel_dp_mode_clock(crtc_state, conn_state);
if (!intel_vrr_is_capable(connector))
return;
@@ -114,9 +115,9 @@ intel_vrr_compute_config(struct intel_crtc_state
*crtc_state,
if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
return;
- vmin = DIV_ROUND_UP(adjusted_mode->crtc_clock * 1000,
+ vmin = DIV_ROUND_UP(clock * 1000,
adjusted_mode->crtc_htotal *
info->monitor_range.max_vfreq);
- vmax = adjusted_mode->crtc_clock * 1000 /
+ vmax = clock * 1000 /
(adjusted_mode->crtc_htotal * info->monitor_range.min_vfreq);
vmin = max_t(int, vmin, adjusted_mode->crtc_vtotal);
--
2.42.0.rc1.204.g551eb34607-goog
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Add missing CCS documentation.
== Series Details == Series: drm/i915: Add missing CCS documentation. URL : https://patchwork.freedesktop.org/series/122807/ State : success == Summary == CI Bug Log - changes from CI_DRM_13555 -> Patchwork_122807v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122807v1/index.html Participating hosts (41 -> 39) -- Missing(2): fi-kbl-soraka fi-snb-2520m Known issues Here are the changes found in Patchwork_122807v1 that come from known issues: ### IGT changes ### Possible fixes * igt@gem_exec_suspend@basic-s0@lmem0: - bat-dg2-9: [INCOMPLETE][1] ([i915#6311]) -> [PASS][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13555/bat-dg2-9/igt@gem_exec_suspend@basic...@lmem0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122807v1/bat-dg2-9/igt@gem_exec_suspend@basic...@lmem0.html * igt@i915_selftest@live@migrate: - bat-dg2-11: [DMESG-WARN][3] ([i915#7699]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13555/bat-dg2-11/igt@i915_selftest@l...@migrate.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122807v1/bat-dg2-11/igt@i915_selftest@l...@migrate.html * igt@i915_suspend@basic-s3-without-i915: - fi-apl-guc: [DMESG-WARN][5] ([i915#1982]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13555/fi-apl-guc/igt@i915_susp...@basic-s3-without-i915.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122807v1/fi-apl-guc/igt@i915_susp...@basic-s3-without-i915.html [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#6311]: https://gitlab.freedesktop.org/drm/intel/issues/6311 [i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699 Build changes - * Linux: CI_DRM_13555 -> Patchwork_122807v1 CI-20190529: 20190529 CI_DRM_13555: d3f73a72a15187baccea646d2346679c14b1bc10 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7451: 5d48d1fb231f449fe2f80cda14ea7a1ecfda59fa @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_122807v1: d3f73a72a15187baccea646d2346679c14b1bc10 @ git://anongit.freedesktop.org/gfx-ci/linux ### Linux commits ab89f2250ac8 drm/i915: Add missing CCS documentation. == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122807v1/index.html
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Add missing CCS documentation.
== Series Details == Series: drm/i915: Add missing CCS documentation. URL : https://patchwork.freedesktop.org/series/122807/ State : warning == Summary == Error: dim sparse failed /home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No such file or directory
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Add missing CCS documentation.
== Series Details == Series: drm/i915: Add missing CCS documentation. URL : https://patchwork.freedesktop.org/series/122807/ State : warning == Summary == Error: dim checkpatch failed /home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No such file or directory
Re: [Intel-gfx] [PATCH] drm/i915: Add missing CCS documentation.
On Wed, Aug 23, 2023 at 05:39:01PM -0400, Rodrigo Vivi wrote:
> Let's introduce the basic documentation about CCS.
> While doing that, also removed the legacy execution flag name. That flag
> simply doesn't exist for CCS and it is not needed on current context
> submission. Those flag names are only needed on legacy context,
> while on new ones we only need to pass the engine ID.
>
> It is worth mention that this documentation should probably live with
> the engine definitions rather than in the i915.rst file directly and
> that more updates are likely need in this section. But this should
> come later.
It may be better to just delete this completely and instead provide a
reference to the better engine documentation we already have in
include/uapi/drm/i915_drm.h?
>
> Fixes: 944823c94639 ("drm/i915/xehp: Define compute class and engine")
> Cc: Matt Roper
> Cc: Sushma Venkatesh Reddy
> Cc: Joonas Lahtinen
> Cc: Tvrtko Ursulin
> Signed-off-by: Rodrigo Vivi
> ---
> Documentation/gpu/i915.rst | 24 +++-
> 1 file changed, 11 insertions(+), 13 deletions(-)
>
> diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
> index 60ea21734902..87bdcd616944 100644
> --- a/Documentation/gpu/i915.rst
> +++ b/Documentation/gpu/i915.rst
> @@ -267,19 +267,17 @@ i915 driver.
> Intel GPU Basics
>
>
> -An Intel GPU has multiple engines. There are several engine types.
> -
> -- RCS engine is for rendering 3D and performing compute, this is named
> - `I915_EXEC_RENDER` in user space.
> -- BCS is a blitting (copy) engine, this is named `I915_EXEC_BLT` in user
> - space.
> -- VCS is a video encode and decode engine, this is named `I915_EXEC_BSD`
> - in user space
> -- VECS is video enhancement engine, this is named `I915_EXEC_VEBOX` in user
> - space.
> -- The enumeration `I915_EXEC_DEFAULT` does not refer to specific engine;
> - instead it is to be used by user space to specify a default rendering
> - engine (for 3D) that may or may not be the same as RCS.
> +An Intel GPU has multiple engines. There are several engine types:
> +
> +- Render Command Streamer (RCS). An engine for rendering 3D and
> + performing compute on platforms without CCS.
I don't think the "without CCS" here is accurate; even platforms with
CCS engines can still access the GPGPU pipeline via the RCS.
> +- Blitting Command Streamer (BCS). An engine for performing blitting and/or
> + copying operations.
> +- Video Command Streamer. An engine used for video decoding. For historical
> + reasons this engine was alsso called 'BCS'.
I don't think this is true? As far as I recall, BCS has always referred
to the blitter/copy engines, not the VCS.
Matt
> +- Video Enhancement Command Streamer (VECS). The engine used only by media.
> +- Compute Command Streamer (CCS). An engine that has access to the media and
> + GPGPU pipelines, but not the 3D pipeline.
>
> The Intel GPU family is a family of integrated GPU's using Unified
> Memory Access. For having the GPU "do work", user space will feed the
> --
> 2.41.0
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
Re: [Intel-gfx] [Intel-xe] [PATCH 34/42] drm/i915/lnl: Start using CDCLK through PLL
On Wed, Aug 23, 2023 at 10:07:32AM -0700, Lucas De Marchi wrote:
> From: Stanislav Lisovskiy
>
> Introduce correspondent definitions and for choosing between CD2X CDCLK
> and PLL CDCLK as a source.
>
> Signed-off-by: Stanislav Lisovskiy
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 14 --
> drivers/gpu/drm/i915/i915_reg.h| 3 +++
> 2 files changed, 15 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index ed45a2cf5c9a..04937aaabcee 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1932,8 +1932,7 @@ static void _bxt_set_cdclk(struct drm_i915_private
> *dev_priv,
> dg2_cdclk_squash_program(dev_priv, waveform);
>
> val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |
> - bxt_cdclk_cd2x_pipe(dev_priv, pipe) |
> - skl_cdclk_decimal(cdclk);
> + bxt_cdclk_cd2x_pipe(dev_priv, pipe);
>
> /*
>* Disable SSA Precharge when CD clock frequency < 500 MHz,
> @@ -1942,6 +1941,17 @@ static void _bxt_set_cdclk(struct drm_i915_private
> *dev_priv,
> if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
> cdclk >= 50)
> val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
> +
> + if (DISPLAY_VER(dev_priv) >= 20)
> + /*
> + * Using CDCLK through PLL seems to be always better option when
> + * its supported, both in terms of performance and power
> + * consumption.
> + */
I'm not sure what this comment is based on. But the table on bspec
68861 specifically tells us to set this bit for the cdclk table we
implemented in the last patch, so the logic is correct regardless.
> + val |= CDCLK_SOURCE_SEL_CDCLK_PLL;
> + else
> + val |= skl_cdclk_decimal(cdclk);
> +
> intel_de_write(dev_priv, CDCLK_CTL, val);
>
> if (pipe != INVALID_PIPE)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index fa85530afac3..d5850761a75a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5933,6 +5933,9 @@ enum skl_power_gate {
> #define CDCLK_FREQ_540 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 1)
> #define CDCLK_FREQ_337_308 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 2)
> #define CDCLK_FREQ_675_617 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 3)
> +#define CDCLK_SOURCE_SEL_MASK REG_BIT(25)
> +#define CDCLK_SOURCE_SEL_CD2X
> REG_FIELD_PREP(CDCLK_SOURCE_SEL_MASK, 0)
No need to make a single-bit "mask" or define the unused
CDCLK_SOURCE_SEL_CD2X here. We can just define
CDCLK_SOURCE_SEL_CDCLK_PLL as REG_BIT(25) directly.
Matt
> +#define CDCLK_SOURCE_SEL_CDCLK_PLL REG_FIELD_PREP(CDCLK_SOURCE_SEL_MASK, 1)
> #define BXT_CDCLK_CD2X_DIV_SEL_MASK REG_GENMASK(23, 22)
> #define BXT_CDCLK_CD2X_DIV_SEL_1
> REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 0)
> #define BXT_CDCLK_CD2X_DIV_SEL_1_5
> REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 1)
> --
> 2.40.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
[Intel-gfx] [PATCH] drm/i915: Add missing CCS documentation.
Let's introduce the basic documentation about CCS.
While doing that, also removed the legacy execution flag name. That flag
simply doesn't exist for CCS and it is not needed on current context
submission. Those flag names are only needed on legacy context,
while on new ones we only need to pass the engine ID.
It is worth mention that this documentation should probably live with
the engine definitions rather than in the i915.rst file directly and
that more updates are likely need in this section. But this should
come later.
Fixes: 944823c94639 ("drm/i915/xehp: Define compute class and engine")
Cc: Matt Roper
Cc: Sushma Venkatesh Reddy
Cc: Joonas Lahtinen
Cc: Tvrtko Ursulin
Signed-off-by: Rodrigo Vivi
---
Documentation/gpu/i915.rst | 24 +++-
1 file changed, 11 insertions(+), 13 deletions(-)
diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index 60ea21734902..87bdcd616944 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -267,19 +267,17 @@ i915 driver.
Intel GPU Basics
-An Intel GPU has multiple engines. There are several engine types.
-
-- RCS engine is for rendering 3D and performing compute, this is named
- `I915_EXEC_RENDER` in user space.
-- BCS is a blitting (copy) engine, this is named `I915_EXEC_BLT` in user
- space.
-- VCS is a video encode and decode engine, this is named `I915_EXEC_BSD`
- in user space
-- VECS is video enhancement engine, this is named `I915_EXEC_VEBOX` in user
- space.
-- The enumeration `I915_EXEC_DEFAULT` does not refer to specific engine;
- instead it is to be used by user space to specify a default rendering
- engine (for 3D) that may or may not be the same as RCS.
+An Intel GPU has multiple engines. There are several engine types:
+
+- Render Command Streamer (RCS). An engine for rendering 3D and
+ performing compute on platforms without CCS.
+- Blitting Command Streamer (BCS). An engine for performing blitting and/or
+ copying operations.
+- Video Command Streamer. An engine used for video decoding. For historical
+ reasons this engine was alsso called 'BCS'.
+- Video Enhancement Command Streamer (VECS). The engine used only by media.
+- Compute Command Streamer (CCS). An engine that has access to the media and
+ GPGPU pipelines, but not the 3D pipeline.
The Intel GPU family is a family of integrated GPU's using Unified
Memory Access. For having the GPU "do work", user space will feed the
--
2.41.0
Re: [Intel-gfx] [Intel-xe] [PATCH 33/42] drm/i915/lnl: Add CDCLK table
On Wed, Aug 23, 2023 at 10:07:31AM -0700, Lucas De Marchi wrote:
> From: Stanislav Lisovskiy
>
> Add a new Lunar Lake CDCLK table from BSpec and also a helper function
> in order to be able to find lowest possible CDCLK, which has required
> MDCLK for the correspodent pixel rate.
>
> Bspec: 68861
> Signed-off-by: Stanislav Lisovskiy
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 52 +-
> 1 file changed, 50 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 3e566f45996d..ed45a2cf5c9a 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1381,6 +1381,31 @@ static const struct intel_cdclk_vals mtl_cdclk_table[]
> = {
> {}
> };
>
> +static const struct intel_cdclk_vals lnl_cdclk_table[] = {
> + { .refclk = 38400, .cdclk = 153600, .mdclk = 614400, .divider = 2,
> .ratio = 16, .waveform = 0x },
> + { .refclk = 38400, .cdclk = 172800, .mdclk = 614400, .divider = 2,
> .ratio = 16, .waveform = 0xad5a },
> + { .refclk = 38400, .cdclk = 192000, .mdclk = 614400, .divider = 2,
> .ratio = 16, .waveform = 0xb6b6 },
> + { .refclk = 38400, .cdclk = 211200, .mdclk = 614400, .divider = 2,
> .ratio = 16, .waveform = 0xdbb6 },
> + { .refclk = 38400, .cdclk = 230400, .mdclk = 614400, .divider = 2,
> .ratio = 16, .waveform = 0x },
> + { .refclk = 38400, .cdclk = 249600, .mdclk = 614400, .divider = 2,
> .ratio = 16, .waveform = 0xf7de },
> + { .refclk = 38400, .cdclk = 268800, .mdclk = 614400, .divider = 2,
> .ratio = 16, .waveform = 0xfefe },
> + { .refclk = 38400, .cdclk = 288000, .mdclk = 614400, .divider = 2,
> .ratio = 16, .waveform = 0xfffe },
> + { .refclk = 38400, .cdclk = 307200, .mdclk = 614400, .divider = 2,
> .ratio = 16, .waveform = 0x },
Shouldn't waveform be 0x for this one?
> + { .refclk = 38400, .cdclk = 33, .mdclk = 96, .divider = 2,
> .ratio = 25, .waveform = 0xdbb6 },
> + { .refclk = 38400, .cdclk = 36, .mdclk = 96, .divider = 2,
> .ratio = 25, .waveform = 0x },
> + { .refclk = 38400, .cdclk = 39, .mdclk = 96, .divider = 2,
> .ratio = 25, .waveform = 0xf7de },
> + { .refclk = 38400, .cdclk = 42, .mdclk = 96, .divider = 2,
> .ratio = 25, .waveform = 0xfefe },
> + { .refclk = 38400, .cdclk = 45, .mdclk = 96, .divider = 2,
> .ratio = 25, .waveform = 0xfffe },
> + { .refclk = 38400, .cdclk = 48, .mdclk = 96, .divider = 2,
> .ratio = 25, .waveform = 0x },
Ditto.
> + { .refclk = 38400, .cdclk = 487200, .mdclk = 1113600, .divider = 2,
> .ratio = 29, .waveform = 0xfefe },
> + { .refclk = 38400, .cdclk = 522000, .mdclk = 1113600, .divider = 2,
> .ratio = 29, .waveform = 0xfffe },
> + { .refclk = 38400, .cdclk = 556800, .mdclk = 1113600, .divider = 2,
> .ratio = 29, .waveform = 0x },
Ditto.
> + { .refclk = 38400, .cdclk = 571200, .mdclk = 1305600, .divider = 2,
> .ratio = 34, .waveform = 0xfefe },
> + { .refclk = 38400, .cdclk = 612000, .mdclk = 1305600, .divider = 2,
> .ratio = 34, .waveform = 0xfffe },
> + { .refclk = 38400, .cdclk = 652800, .mdclk = 1305600, .divider = 2,
> .ratio = 34, .waveform = 0x },
Ditto.
> + {}
> +};
As noted on the previous patch, I don't see a need for the .mdclk field
since that's equivalent to the vco value that we're already tracking.
Matt
> +
> static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
> {
> const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
> @@ -2531,12 +2556,32 @@ intel_set_cdclk_post_plane_update(struct
> intel_atomic_state *state)
> }
> }
>
> +static int
> +cdclk_match_by_refclk_mdclk(struct drm_i915_private *i915, int pixel_rate)
> +{
> + const struct intel_cdclk_vals *table = i915->display.cdclk.table;
> + int i;
> +
> + for (i = 0; table[i].refclk; i++)
> + if (table[i].refclk == i915->display.cdclk.hw.ref &&
> + table[i].mdclk >= pixel_rate)
> + return table[i].cdclk;
> +
> + drm_WARN(>drm, 1,
> + "Cannot satisfy pixel rate %d with refclk %u\n",
> + pixel_rate, i915->display.cdclk.hw.ref);
> +
> + return 0;
> +}
> +
> static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state
> *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> int pixel_rate = crtc_state->pixel_rate;
>
> - if (DISPLAY_VER(dev_priv) >= 10)
> + if (DISPLAY_VER(dev_priv) >= 20)
> + return cdclk_match_by_refclk_mdclk(dev_priv, pixel_rate);
> + else if (DISPLAY_VER(dev_priv) >= 10)
> return DIV_ROUND_UP(pixel_rate, 2);
> else if (DISPLAY_VER(dev_priv) == 9 ||
>IS_BROADWELL(dev_priv) ||
[Intel-gfx] ✗ Fi.CI.BAT: failure for Apply Wa_16018031267 / Wa_16018063123 (rev2)
== Series Details ==
Series: Apply Wa_16018031267 / Wa_16018063123 (rev2)
URL : https://patchwork.freedesktop.org/series/122804/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13554 -> Patchwork_122804v2
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_122804v2 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_122804v2, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122804v2/index.html
Participating hosts (40 -> 39)
--
Missing(1): fi-snb-2520m
Possible new issues
---
Here are the unknown changes that may have been introduced in
Patchwork_122804v2:
### IGT changes ###
Possible regressions
* igt@i915_module_load@load:
- bat-dg2-11: [PASS][1] -> [ABORT][2]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13554/bat-dg2-11/igt@i915_module_l...@load.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122804v2/bat-dg2-11/igt@i915_module_l...@load.html
- bat-atsm-1: [PASS][3] -> [ABORT][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13554/bat-atsm-1/igt@i915_module_l...@load.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122804v2/bat-atsm-1/igt@i915_module_l...@load.html
- bat-dg2-9: [PASS][5] -> [ABORT][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13554/bat-dg2-9/igt@i915_module_l...@load.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122804v2/bat-dg2-9/igt@i915_module_l...@load.html
* igt@i915_selftest@live@gt_lrc:
- bat-dg1-5: [PASS][7] -> [DMESG-FAIL][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13554/bat-dg1-5/igt@i915_selftest@live@gt_lrc.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122804v2/bat-dg1-5/igt@i915_selftest@live@gt_lrc.html
- fi-rkl-11600: [PASS][9] -> [DMESG-FAIL][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13554/fi-rkl-11600/igt@i915_selftest@live@gt_lrc.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122804v2/fi-rkl-11600/igt@i915_selftest@live@gt_lrc.html
- bat-mtlp-8: [PASS][11] -> [DMESG-FAIL][12]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13554/bat-mtlp-8/igt@i915_selftest@live@gt_lrc.html
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122804v2/bat-mtlp-8/igt@i915_selftest@live@gt_lrc.html
- bat-adlm-1: [PASS][13] -> [DMESG-FAIL][14]
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13554/bat-adlm-1/igt@i915_selftest@live@gt_lrc.html
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122804v2/bat-adlm-1/igt@i915_selftest@live@gt_lrc.html
- fi-tgl-1115g4: [PASS][15] -> [DMESG-FAIL][16]
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13554/fi-tgl-1115g4/igt@i915_selftest@live@gt_lrc.html
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122804v2/fi-tgl-1115g4/igt@i915_selftest@live@gt_lrc.html
- bat-rpls-1: [PASS][17] -> [DMESG-FAIL][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13554/bat-rpls-1/igt@i915_selftest@live@gt_lrc.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122804v2/bat-rpls-1/igt@i915_selftest@live@gt_lrc.html
- bat-mtlp-6: [PASS][19] -> [DMESG-FAIL][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13554/bat-mtlp-6/igt@i915_selftest@live@gt_lrc.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122804v2/bat-mtlp-6/igt@i915_selftest@live@gt_lrc.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_module_load@load:
- {bat-dg2-13}: [DMESG-WARN][21] ([i915#8879]) -> [ABORT][22]
[21]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13554/bat-dg2-13/igt@i915_module_l...@load.html
[22]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122804v2/bat-dg2-13/igt@i915_module_l...@load.html
- {bat-dg2-14}: [DMESG-WARN][23] ([i915#8879]) -> [ABORT][24]
[23]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13554/bat-dg2-14/igt@i915_module_l...@load.html
[24]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122804v2/bat-dg2-14/igt@i915_module_l...@load.html
Known issues
Here are the changes found in Patchwork_122804v2 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@gt_lrc:
- bat-adlp-9: [PASS][25] -> [DMESG-FAIL][26] ([i915#7913])
[25]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13554/bat-adlp-9/igt@i915_selftest@live@gt_lrc.html
[26]:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Apply Wa_16018031267 / Wa_16018063123 (rev2)
== Series Details == Series: Apply Wa_16018031267 / Wa_16018063123 (rev2) URL : https://patchwork.freedesktop.org/series/122804/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Apply Wa_16018031267 / Wa_16018063123 (rev2)
== Series Details == Series: Apply Wa_16018031267 / Wa_16018063123 (rev2) URL : https://patchwork.freedesktop.org/series/122804/ State : warning == Summary == Error: dim checkpatch failed 00f4bda3e3b0 drm/i915: Add WABB blit for Wa_16018031267 / Wa_16018063123 -:11: WARNING:BAD_SIGN_OFF: Co-developed-by: should not be used to attribute nominal patch author 'Nirmoy Das ' #11: Co-developed-by: Nirmoy Das -:11: WARNING:BAD_SIGN_OFF: Co-developed-by: must be immediately followed by Signed-off-by: #11: Co-developed-by: Nirmoy Das -:54: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants #54: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:836: + GEM_BUG_ON(lrc_ring_wa_bb_per_ctx(engine) == -1); -:74: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #74: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:1017: + * ^I^Ithe PER_CTX_BB. When disabled, the function returns$ -:75: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #75: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:1018: + * ^I^Ithe location of the INDIRECT_CTX.$ -:110: ERROR:TRAILING_WHITESPACE: trailing whitespace #110: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:1402: +^Iu32 addr = intel_gt_scratch_offset(gt, INTEL_GT_SCRATCH_FIELD_DUMMY_BLIT); $ -:164: CHECK:LINE_SPACING: Please don't use multiple blank lines #164: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:1456: + + -:180: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants #180: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:1472: + GEM_BUG_ON(cs - start > I915_GTT_PAGE_SIZE / sizeof(*cs)); -:225: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #225: FILE: drivers/gpu/drm/i915/gt/selftest_lrc.c:1583: +emit_wabb_ctx_canary(const struct intel_context *ce, + u32 *cs, bool per_ctx) -:250: ERROR:CODE_INDENT: code indent should use tabs where possible #250: FILE: drivers/gpu/drm/i915/gt/selftest_lrc.c:1607: +return emit_wabb_ctx_canary(ce, cs, true);$ -:250: WARNING:LEADING_SPACE: please, no spaces at the start of a line #250: FILE: drivers/gpu/drm/i915/gt/selftest_lrc.c:1607: +return emit_wabb_ctx_canary(ce, cs, true);$ -:354: ERROR:TRAILING_WHITESPACE: trailing whitespace #354: FILE: drivers/gpu/drm/i915/gt/selftest_lrc.c:1739: +}^I^I$ -:375: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects? #375: FILE: drivers/gpu/drm/i915/i915_drv.h:816: +#define NEEDS_FASTCOLOR_BLT_WABB(i915) (GRAPHICS_VER_FULL(i915) == IP_VER(12, 70) || \ +GRAPHICS_VER_FULL(i915) == IP_VER(12, 71) || \ +IS_PONTEVECCHIO(i915) || \ +IS_DG2(i915)) -:380: ERROR:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Nirmoy Das ' total: 4 errors, 7 warnings, 3 checks, 330 lines checked 506e01dfa9cc drm/i915: Set copy engine arbitration for Wa_16018031267 / Wa_16018063123
Re: [Intel-gfx] [Intel-xe] [PATCH 32/42] drm/i915/lnl: Introduce MDCLK
On Wed, Aug 23, 2023 at 10:07:30AM -0700, Lucas De Marchi wrote:
> From: Stanislav Lisovskiy
>
> In Lunar Lake we now separate MDCLK from CDLCK, which used to be before
> always 2 times CDCLK. Now we might afford lower CDCLK, while having
> higher memory clock, so improving bandwidth and power consumption at the
> same time. This is prep work required to enable that.
>
> Signed-off-by: Stanislav Lisovskiy
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 30 ++
> drivers/gpu/drm/i915/display/intel_cdclk.h | 2 +-
> 2 files changed, 31 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index fdd8d04fe12c..3e566f45996d 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1223,6 +1223,7 @@ static void skl_cdclk_uninit_hw(struct drm_i915_private
> *dev_priv)
>
> struct intel_cdclk_vals {
> u32 cdclk;
> + u32 mdclk;
> u16 refclk;
> u16 waveform;
> u8 divider; /* CD2X divider * 2 */
> @@ -1524,6 +1525,8 @@ static void bxt_de_pll_readout(struct drm_i915_private
> *dev_priv,
> static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
> struct intel_cdclk_config *cdclk_config)
> {
> + const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
> + int i, ratio, tbl_waveform = 0;
> u32 squash_ctl = 0;
> u32 divider;
> int div;
> @@ -1574,10 +1577,36 @@ static void bxt_get_cdclk(struct drm_i915_private
> *dev_priv,
>
> cdclk_config->cdclk = DIV_ROUND_CLOSEST(hweight16(waveform) *
> cdclk_config->vco, size
> * div);
> + tbl_waveform = squash_ctl & CDCLK_SQUASH_WAVEFORM_MASK;
> } else {
> cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div);
> }
>
> + ratio = cdclk_config->vco / cdclk_config->ref;
> +
> + for (i = 0; table[i].refclk; i++) {
> + if (table[i].refclk != cdclk_config->ref)
> + continue;
> +
> + if (table[i].divider != div)
> + continue;
> +
> + if (table[i].waveform != tbl_waveform)
> + continue;
> +
> + if (table[i].ratio != ratio)
> + continue;
> +
> + /*
> + * Supported from LunarLake HW onwards, however considering that
> + * besides this the whole procedure is the same, we keep this
> + * for all the platforms.
> + */
> + cdclk_config->mdclk = table[i].mdclk;
> +
> + break;
> + }
I might be misunderstanding something, but from bspec 68861, is looks
like the mdclk frequency is always just "ratio * refclk." Which is the
value we already have stored in cdclk_config->vco. Do we need to do
this extra lookup or track this value separately?
Matt
> +
> out:
> /*
>* Can't read this out :( Let's assume it's
> @@ -2191,6 +2220,7 @@ bool intel_cdclk_needs_modeset(const struct
> intel_cdclk_config *a,
> const struct intel_cdclk_config *b)
> {
> return a->cdclk != b->cdclk ||
> + a->mdclk != b->mdclk ||
> a->vco != b->vco ||
> a->ref != b->ref;
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h
> b/drivers/gpu/drm/i915/display/intel_cdclk.h
> index 48fd7d39e0cd..3e7eabd4d7b6 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.h
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
> @@ -16,7 +16,7 @@ struct intel_atomic_state;
> struct intel_crtc_state;
>
> struct intel_cdclk_config {
> - unsigned int cdclk, vco, ref, bypass;
> + unsigned int cdclk, mdclk, vco, ref, bypass;
> u8 voltage_level;
> };
>
> --
> 2.40.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
Re: [Intel-gfx] [Intel-xe] [PATCH 31/42] drm/i915/lnl: Add gmbus/ddc support
On Wed, Aug 23, 2023 at 10:07:29AM -0700, Lucas De Marchi wrote:
> LNL's south display uses the same table as MTP. Check for LNL's fake PCH
> to make it consistent with the other checks.
>
> The VBT table doesn't contain the VBT -> spec mapping for LNL. Like in
> other cases, uses the same as the previous platform.
>
> Bspec: 68971, 20124
> Cc: Anusha Srivatsa
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/display/intel_bios.c | 2 +-
> drivers/gpu/drm/i915/display/intel_gmbus.c | 5 -
> 2 files changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index 097c1f23d3ae..3772b91e155c 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -2195,7 +2195,7 @@ static u8 map_ddc_pin(struct drm_i915_private *i915, u8
> vbt_pin)
> const u8 *ddc_pin_map;
> int i, n_entries;
>
> - if (HAS_PCH_MTP(i915) || IS_ALDERLAKE_P(i915)) {
> + if (HAS_PCH_MTP(i915) || IS_ALDERLAKE_P(i915) || IS_LUNARLAKE(i915)) {
The LUNARLAKE here vs PCH_LNL below seems inconsistent. Either way, we
should probably put the newer platform first in the condition.
Aside from those
Reviewed-by: Matt Roper
> ddc_pin_map = adlp_ddc_pin_map;
> n_entries = ARRAY_SIZE(adlp_ddc_pin_map);
> } else if (IS_ALDERLAKE_S(i915)) {
> diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c
> b/drivers/gpu/drm/i915/display/intel_gmbus.c
> index e95ddb580ef6..801fabbccf7e 100644
> --- a/drivers/gpu/drm/i915/display/intel_gmbus.c
> +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
> @@ -155,7 +155,10 @@ static const struct gmbus_pin *get_gmbus_pin(struct
> drm_i915_private *i915,
> const struct gmbus_pin *pins;
> size_t size;
>
> - if (INTEL_PCH_TYPE(i915) >= PCH_DG2) {
> + if (INTEL_PCH_TYPE(i915) >= PCH_LNL) {
> + pins = gmbus_pins_mtp;
> + size = ARRAY_SIZE(gmbus_pins_mtp);
> + } else if (INTEL_PCH_TYPE(i915) >= PCH_DG2) {
> pins = gmbus_pins_dg2;
> size = ARRAY_SIZE(gmbus_pins_dg2);
> } else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) {
> --
> 2.40.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
Re: [Intel-gfx] [Intel-xe] [PATCH 30/42] drm/i915/xe2lpd: Extend Wa_15010685871
On Wed, Aug 23, 2023 at 10:07:28AM -0700, Lucas De Marchi wrote:
> Xe2_LPD also needs workaround 15010685871.
>
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 4207863b7b2a..fdd8d04fe12c 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1839,9 +1839,9 @@ static bool
> cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i91
>
> static bool pll_enable_wa_needed(struct drm_i915_private *dev_priv)
> {
> - return ((IS_DG2(dev_priv) || IS_METEORLAKE(dev_priv)) &&
> - dev_priv->display.cdclk.hw.vco > 0 &&
> - HAS_CDCLK_SQUASH(dev_priv));
> + return (IS_DG2(dev_priv) || IS_METEORLAKE(dev_priv) ||
> + DISPLAY_VER(dev_priv) == 20) &&
We may have future 20.xx platforms for which this doesn't hold true.
This should probably be a "DISPLAY_VER_FULL(dev_priv) == IP_VER(20, 0)"
to exactly match Xe2_LPD and nothing else.
Note that the drm-intel version of the code has already replaced the MTL
check with an Xe_LPD+ version check, but that hasn't propagated to
drm-xe-next yet.
While we're here, we can probably re-order this too (newest platform
first).
Matt
> + dev_priv->display.cdclk.hw.vco > 0 &&
> HAS_CDCLK_SQUASH(dev_priv);
> }
>
> static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
> --
> 2.40.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
Re: [Intel-gfx] [Intel-xe] [PATCH 29/42] drm/i915/xe2lpd: Add support for HPD
On Wed, Aug 23, 2023 at 10:07:27AM -0700, Lucas De Marchi wrote:
> From: Gustavo Sousa
>
> Hotplug setup for Xe2_LPD differs from Xe_LPD+ by the fact that the
> extra programming for hotplug inversion and DDI HPD filter duration is
> not necessary anymore. As mtp_hpd_irq_setup() is reasonably small,
> prefer to fork it into a new function for Xe2_LPD instead of adding a
> platform check.
>
> BSpec: 68970
It might be worth adding 69940 to the list here, since that's useful for
confirming the hpd pin => bit mapping.
> Signed-off-by: Gustavo Sousa
> Signed-off-by: Lucas De Marchi
> ---
> .../gpu/drm/i915/display/intel_hotplug_irq.c | 19 ++-
> 1 file changed, 18 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> index f76b9deb64b4..74aea0d8d9ae 100644
> --- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> @@ -163,7 +163,9 @@ static void intel_hpd_init_pins(struct drm_i915_private
> *dev_priv)
> (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv)))
> return;
>
> - if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
> + if (INTEL_PCH_TYPE(dev_priv) >= PCH_LNL)
> + hpd->pch_hpd = hpd_mtp;
> + else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
> hpd->pch_hpd = hpd_sde_dg1;
> else if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTP)
> hpd->pch_hpd = hpd_mtp;
> @@ -1061,6 +1063,19 @@ static void mtp_hpd_irq_setup(struct drm_i915_private
> *i915)
> mtp_tc_hpd_detection_setup(i915);
> }
>
> +static void xe2lpd_sde_hpd_irq_setup(struct drm_i915_private *i915)
> +{
> + u32 hotplug_irqs, enabled_irqs;
> +
> + enabled_irqs = intel_hpd_enabled_irqs(i915,
> i915->display.hotplug.pch_hpd);
> + hotplug_irqs = intel_hpd_hotplug_irqs(i915,
> i915->display.hotplug.pch_hpd);
> +
> + ibx_display_interrupt_update(i915, hotplug_irqs, enabled_irqs);
> +
> + mtp_ddi_hpd_detection_setup(i915);
> + mtp_tc_hpd_detection_setup(i915);
> +}
> +
> static bool is_xelpdp_pica_hpd_pin(enum hpd_pin hpd_pin)
> {
> return hpd_pin >= HPD_PORT_TC1 && hpd_pin <= HPD_PORT_TC4;
> @@ -1120,6 +1135,8 @@ static void xelpdp_hpd_irq_setup(struct
> drm_i915_private *i915)
>
> xelpdp_pica_hpd_detection_setup(i915);
>
> + if (INTEL_PCH_TYPE(i915) >= PCH_LNL)
> + xe2lpd_sde_hpd_irq_setup(i915);
> if (INTEL_PCH_TYPE(i915) >= PCH_MTP)
I think we want an 'else if' here.
Matt
> mtp_hpd_irq_setup(i915);
> }
> --
> 2.40.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
Re: [Intel-gfx] [Intel-xe] [PATCH 27/42] drm/i915/xe2lpd: Read pin assignment from IOM
On Wed, Aug 23, 2023 at 10:07:25AM -0700, Lucas De Marchi wrote:
> From: Luca Coelho
>
> Starting from display version 20, we need to read the pin assignment
> from the IOM TCSS_DDI_STATUS register instead of reading it from the
> FIA.
>
> We use the pin assignment to decide the maximum lane count. So, to
> support this change, add a new lnl_tc_port_get_max_lane_count() function
> that reads from the TCSS_DDI_STATUS register and decides the maximum
> lane count based on that.
>
> BSpec: 69594
> Cc: Mika Kahola
> Signed-off-by: Luca Coelho
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/display/intel_tc.c | 28 +
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 2 files changed, 29 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
> b/drivers/gpu/drm/i915/display/intel_tc.c
> index 3c94bbcb5497..37b0f8529b4f 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.c
> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> @@ -290,6 +290,31 @@ u32 intel_tc_port_get_pin_assignment_mask(struct
> intel_digital_port *dig_port)
> DP_PIN_ASSIGNMENT_SHIFT(tc->phy_fia_idx);
> }
>
> +static int lnl_tc_port_get_max_lane_count(struct intel_digital_port
> *dig_port)
> +{
> + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> + enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
> + intel_wakeref_t wakeref;
> + u32 val, pin_assignment;
> +
> + with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref)
Do we need this? I don't think POWER_DOMAIN_DISPLAY_CORE has been tied
to any power wells since VLV/CHV.
Hmm, it looks like we actually grab it (and even assert it) in a bunch of
places on modern platforms that don't make sense to me since it isn't
tied to anything.
I guess leaving this here doesn't hurt anything, although we might want
to go back and take another look at this in the future.
Reviewed-by: Matt Roper
> + val = intel_de_read(i915, TCSS_DDI_STATUS(tc_port));
> +
> + pin_assignment =
> + REG_FIELD_GET(TCSS_DDI_STATUS_PIN_ASSIGNMENT_MASK, val);
> +
> + switch (pin_assignment) {
> + default:
> + MISSING_CASE(pin_assignment);
> + fallthrough;
> + case DP_PIN_ASSIGNMENT_D:
> + return 2;
> + case DP_PIN_ASSIGNMENT_C:
> + case DP_PIN_ASSIGNMENT_E:
> + return 4;
> + }
> +}
> +
> static int mtl_tc_port_get_max_lane_count(struct intel_digital_port
> *dig_port)
> {
> struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> @@ -348,6 +373,9 @@ int intel_tc_port_max_lane_count(struct
> intel_digital_port *dig_port)
>
> assert_tc_cold_blocked(tc);
>
> + if (DISPLAY_VER(i915) >= 20)
> + return lnl_tc_port_get_max_lane_count(dig_port);
> +
> if (DISPLAY_VER(i915) >= 14)
> return mtl_tc_port_get_max_lane_count(dig_port);
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e31a985b02d5..fa85530afac3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6628,6 +6628,7 @@ enum skl_power_gate {
> #define TCSS_DDI_STATUS(tc) _MMIO(_PICK_EVEN(tc, \
>
> _TCSS_DDI_STATUS_1, \
>
> _TCSS_DDI_STATUS_2))
> +#define TCSS_DDI_STATUS_PIN_ASSIGNMENT_MASK REG_GENMASK(28, 25)
> #define TCSS_DDI_STATUS_READY REG_BIT(2)
> #define TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT REG_BIT(1)
> #define TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT REG_BIT(0)
> --
> 2.40.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
Re: [Intel-gfx] [Intel-xe] [PATCH 25/42] drm/i915/xe2lpd: Add support for DP aux channels
On Wed, Aug 23, 2023 at 01:01:44PM -0700, Matt Roper wrote:
On Wed, Aug 23, 2023 at 10:07:23AM -0700, Lucas De Marchi wrote:
From: Gustavo Sousa
The location of aux channels registers for Xe2 display changed w.r.t.
the previous version.
This is another case of "PICA register ordering where 'A' comes after
'TC4.'" We should probably consolidate on the same design used in
"drm/i915/xe2lpd: Move registers to PICA."
yeah... I'm actually not very happy with that implementation and
thinking if we can have something different. Maybe a regs struct per
port or phy? Then during init we just set the right offset on each of
them rather than calculating the offset every time. Maybe it'd still be
a challenge to support multiple platforms moving the register offsets
left and right, dunno. Also, maybe we should consider such a refactor
only after these patches settle so we can have everything applied
to refactor at once. Thoughts?
Lucas De Marchi
Matt
BSpec: 69010
Signed-off-by: Gustavo Sousa
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dp_aux.c | 43 -
1 file changed, 42 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c
b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index 3fcf609a1444..1ab6964ee1c2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -714,6 +714,44 @@ static i915_reg_t xelpdp_aux_data_reg(struct intel_dp
*intel_dp, int index)
}
}
+static i915_reg_t xe2lpd_aux_ctl_reg(struct intel_dp *intel_dp)
+{
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ enum aux_ch aux_ch = dig_port->aux_ch;
+
+ switch (aux_ch) {
+ case AUX_CH_A:
+ case AUX_CH_B:
+ case AUX_CH_USBC1:
+ case AUX_CH_USBC2:
+ case AUX_CH_USBC3:
+ case AUX_CH_USBC4:
+ return XE2LPD_DP_AUX_CH_CTL(aux_ch);
+ default:
+ MISSING_CASE(aux_ch);
+ return XE2LPD_DP_AUX_CH_CTL(AUX_CH_A);
+ }
+}
+
+static i915_reg_t xe2lpd_aux_data_reg(struct intel_dp *intel_dp, int index)
+{
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ enum aux_ch aux_ch = dig_port->aux_ch;
+
+ switch (aux_ch) {
+ case AUX_CH_A:
+ case AUX_CH_B:
+ case AUX_CH_USBC1:
+ case AUX_CH_USBC2:
+ case AUX_CH_USBC3:
+ case AUX_CH_USBC4:
+ return XE2LPD_DP_AUX_CH_DATA(aux_ch, index);
+ default:
+ MISSING_CASE(aux_ch);
+ return XE2LPD_DP_AUX_CH_DATA(AUX_CH_A, index);
+ }
+}
+
void intel_dp_aux_fini(struct intel_dp *intel_dp)
{
if (cpu_latency_qos_request_active(_dp->pm_qos))
@@ -731,7 +769,10 @@ void intel_dp_aux_init(struct intel_dp *intel_dp)
struct intel_encoder *encoder = _port->base;
enum aux_ch aux_ch = dig_port->aux_ch;
- if (DISPLAY_VER(dev_priv) >= 14) {
+ if (DISPLAY_VER(dev_priv) >= 20) {
+ intel_dp->aux_ch_ctl_reg = xe2lpd_aux_ctl_reg;
+ intel_dp->aux_ch_data_reg = xe2lpd_aux_data_reg;
+ } else if (DISPLAY_VER(dev_priv) >= 14) {
intel_dp->aux_ch_ctl_reg = xelpdp_aux_ctl_reg;
intel_dp->aux_ch_data_reg = xelpdp_aux_data_reg;
} else if (DISPLAY_VER(dev_priv) >= 12) {
--
2.40.1
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
Re: [Intel-gfx] [Intel-xe] [PATCH 26/42] drm/i915/xe2lpd: Handle port AUX interrupts
On Wed, Aug 23, 2023 at 10:07:24AM -0700, Lucas De Marchi wrote:
> From: Gustavo Sousa
>
> Differently from previous version, Xe2_LPD groups all port AUX interrupt
> bits into PICA interrupt registers.
>
> BSpec: 68958, 69697
> Signed-off-by: Gustavo Sousa
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/display/intel_display_irq.c | 4 +++-
> drivers/gpu/drm/i915/display/intel_hotplug_irq.c | 3 +++
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> 3 files changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c
> b/drivers/gpu/drm/i915/display/intel_display_irq.c
> index 62ce55475554..bff4a76310c0 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
> @@ -792,7 +792,9 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private
> *dev_priv)
> {
> u32 mask;
>
> - if (DISPLAY_VER(dev_priv) >= 14)
> + if (DISPLAY_VER(dev_priv) >= 20)
> + return 0;
> + else if (DISPLAY_VER(dev_priv) >= 14)
> return TGL_DE_PORT_AUX_DDIA |
> TGL_DE_PORT_AUX_DDIB;
> else if (DISPLAY_VER(dev_priv) >= 13)
> diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> index f95fa793fabb..f76b9deb64b4 100644
> --- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> @@ -514,6 +514,9 @@ void xelpdp_pica_irq_handler(struct drm_i915_private
> *i915, u32 iir)
> u32 trigger_aux = iir & XELPDP_AUX_TC_MASK;
> u32 pin_mask = 0, long_mask = 0;
>
> + if (DISPLAY_VER(i915) >= 20)
> + trigger_aux |= iir & XE2LPD_AUX_DDI_MASK;
> +
> for (pin = HPD_PORT_TC1; pin <= HPD_PORT_TC4; pin++) {
> u32 val;
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 84c5a76065a0..e31a985b02d5 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4520,6 +4520,9 @@
> #define XELPDP_AUX_TC(hpd_pin) REG_BIT(8 +
> _HPD_PIN_TC(hpd_pin))
> #define XELPDP_AUX_TC_MASK REG_GENMASK(11, 8)
>
> +#define XE2LPD_AUX_DDI(hpd_pin) REG_BIT(6 +
> _HPD_PIN_DDI(hpd_pin))
> +#define XE2LPD_AUX_DDI_MASK REG_GENMASK(7, 6)
> +
It seems like we have extra, atypical whitespace around the fields of
this register. I'd drop the blank line here, as well as the one above
the new definitions so that things are a bit more compact. Otherwise,
Reviewed-by: Matt Roper
> #define XELPDP_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin))
> #define XELPDP_TBT_HOTPLUG_MASK REG_GENMASK(3, 0)
>
> --
> 2.40.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
Re: [Intel-gfx] [Intel-xe] [PATCH 25/42] drm/i915/xe2lpd: Add support for DP aux channels
On Wed, Aug 23, 2023 at 10:07:23AM -0700, Lucas De Marchi wrote:
> From: Gustavo Sousa
>
> The location of aux channels registers for Xe2 display changed w.r.t.
> the previous version.
This is another case of "PICA register ordering where 'A' comes after
'TC4.'" We should probably consolidate on the same design used in
"drm/i915/xe2lpd: Move registers to PICA."
Matt
>
> BSpec: 69010
> Signed-off-by: Gustavo Sousa
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/display/intel_dp_aux.c | 43 -
> 1 file changed, 42 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c
> b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> index 3fcf609a1444..1ab6964ee1c2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
> @@ -714,6 +714,44 @@ static i915_reg_t xelpdp_aux_data_reg(struct intel_dp
> *intel_dp, int index)
> }
> }
>
> +static i915_reg_t xe2lpd_aux_ctl_reg(struct intel_dp *intel_dp)
> +{
> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> + enum aux_ch aux_ch = dig_port->aux_ch;
> +
> + switch (aux_ch) {
> + case AUX_CH_A:
> + case AUX_CH_B:
> + case AUX_CH_USBC1:
> + case AUX_CH_USBC2:
> + case AUX_CH_USBC3:
> + case AUX_CH_USBC4:
> + return XE2LPD_DP_AUX_CH_CTL(aux_ch);
> + default:
> + MISSING_CASE(aux_ch);
> + return XE2LPD_DP_AUX_CH_CTL(AUX_CH_A);
> + }
> +}
> +
> +static i915_reg_t xe2lpd_aux_data_reg(struct intel_dp *intel_dp, int index)
> +{
> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> + enum aux_ch aux_ch = dig_port->aux_ch;
> +
> + switch (aux_ch) {
> + case AUX_CH_A:
> + case AUX_CH_B:
> + case AUX_CH_USBC1:
> + case AUX_CH_USBC2:
> + case AUX_CH_USBC3:
> + case AUX_CH_USBC4:
> + return XE2LPD_DP_AUX_CH_DATA(aux_ch, index);
> + default:
> + MISSING_CASE(aux_ch);
> + return XE2LPD_DP_AUX_CH_DATA(AUX_CH_A, index);
> + }
> +}
> +
> void intel_dp_aux_fini(struct intel_dp *intel_dp)
> {
> if (cpu_latency_qos_request_active(_dp->pm_qos))
> @@ -731,7 +769,10 @@ void intel_dp_aux_init(struct intel_dp *intel_dp)
> struct intel_encoder *encoder = _port->base;
> enum aux_ch aux_ch = dig_port->aux_ch;
>
> - if (DISPLAY_VER(dev_priv) >= 14) {
> + if (DISPLAY_VER(dev_priv) >= 20) {
> + intel_dp->aux_ch_ctl_reg = xe2lpd_aux_ctl_reg;
> + intel_dp->aux_ch_data_reg = xe2lpd_aux_data_reg;
> + } else if (DISPLAY_VER(dev_priv) >= 14) {
> intel_dp->aux_ch_ctl_reg = xelpdp_aux_ctl_reg;
> intel_dp->aux_ch_data_reg = xelpdp_aux_data_reg;
> } else if (DISPLAY_VER(dev_priv) >= 12) {
> --
> 2.40.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
Re: [Intel-gfx] [Intel-xe] [PATCH 24/42] drm/i915/display: Remove FBC capability from fused off pipes
On Wed, Aug 23, 2023 at 10:07:22AM -0700, Lucas De Marchi wrote:
> From: Clint Taylor
>
> If a particular pipe is disabled by fuse also remove the FBC for that
> pipe.
>
> Bspec: 69464
> Cc: Anusha Srivatsa
> Cc: Gustavo Sousa
> Signed-off-by: Clint Taylor
> Signed-off-by: Lucas De Marchi
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_display_device.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
> b/drivers/gpu/drm/i915/display/intel_display_device.c
> index b853cd0c704a..c4ff5a08c269 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> @@ -962,16 +962,19 @@ void intel_display_device_info_runtime_init(struct
> drm_i915_private *i915)
> if (dfsm & SKL_DFSM_PIPE_B_DISABLE) {
> display_runtime->pipe_mask &= ~BIT(PIPE_B);
> display_runtime->cpu_transcoder_mask &=
> ~BIT(TRANSCODER_B);
> + display_runtime->fbc_mask &= ~BIT(INTEL_FBC_B);
> }
> if (dfsm & SKL_DFSM_PIPE_C_DISABLE) {
> display_runtime->pipe_mask &= ~BIT(PIPE_C);
> display_runtime->cpu_transcoder_mask &=
> ~BIT(TRANSCODER_C);
> + display_runtime->fbc_mask &= ~BIT(INTEL_FBC_C);
> }
>
> if (DISPLAY_VER(i915) >= 12 &&
> (dfsm & TGL_DFSM_PIPE_D_DISABLE)) {
> display_runtime->pipe_mask &= ~BIT(PIPE_D);
> display_runtime->cpu_transcoder_mask &=
> ~BIT(TRANSCODER_D);
> + display_runtime->fbc_mask &= ~BIT(INTEL_FBC_D);
> }
>
> if (!display_runtime->pipe_mask)
> --
> 2.40.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
Re: [Intel-gfx] [Intel-xe] [PATCH 23/42] drm/i915/xe2lpd: FBC is now supported on all pipes
On Wed, Aug 23, 2023 at 10:07:21AM -0700, Lucas De Marchi wrote:
> From: Matt Roper
>
> FBC is no longer limited by pipe.
It looks like we lost the part of this patch that adds this to the
xe2_lpd_display device info structure.
Matt
>
> Bspec: 68881, 68904
> Signed-off-by: Matt Roper
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/display/intel_fbc.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h
> b/drivers/gpu/drm/i915/display/intel_fbc.h
> index 4adb98afe6ff..6720ec8ee8a2 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.h
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.h
> @@ -20,6 +20,8 @@ struct intel_plane_state;
> enum intel_fbc_id {
> INTEL_FBC_A,
> INTEL_FBC_B,
> + INTEL_FBC_C,
> + INTEL_FBC_D,
>
> I915_MAX_FBCS,
> };
> --
> 2.40.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
Re: [Intel-gfx] [Intel-xe] [PATCH 21/42] drm/i915/xe2lpd: Add display power well
On Wed, Aug 23, 2023 at 12:44:56PM -0700, Matt Roper wrote:
> On Wed, Aug 23, 2023 at 10:07:19AM -0700, Lucas De Marchi wrote:
> > From: Ravi Kumar Vodapalli
> >
> > Add Display Power Well for LNL platform, mostly it is same as MTL
> > platform so reused the code
> >
> > Changes are:
> > 1. AUX_CH_CTL and AUX_CH_DATA1 are different from MTL so added extra
> >logic xelpdp_aux_power_well_ops functions.
> > 2. PGPICA1 contains type-C capable port slices which requires the well
> >to power powered up, so added new power well definition for PGPICA1
> >
> > BSpec: 68886
> > Signed-off-by: Ravi Kumar Vodapalli
> > Signed-off-by: Gustavo Sousa
> > Signed-off-by: Lucas De Marchi
> > ---
> > .../i915/display/intel_display_power_map.c| 36 ++-
> > .../i915/display/intel_display_power_well.c | 63 ++-
> > .../i915/display/intel_display_power_well.h | 1 +
> > .../gpu/drm/i915/display/intel_dp_aux_regs.h | 27
> > 4 files changed, 123 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c
> > b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> > index 5ad04cd42c15..cef3b313c9f5 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> > @@ -1545,6 +1545,38 @@ static const struct i915_power_well_desc_list
> > xelpdp_power_wells[] = {
> > I915_PW_DESCRIPTORS(xelpdp_power_wells_main),
> > };
> >
> > +I915_DECL_PW_DOMAINS(xe2lpd_pwdoms_pica_tc,
> > +POWER_DOMAIN_PORT_DDI_LANES_TC1,
> > +POWER_DOMAIN_PORT_DDI_LANES_TC2,
> > +POWER_DOMAIN_PORT_DDI_LANES_TC3,
> > +POWER_DOMAIN_PORT_DDI_LANES_TC4,
> > +POWER_DOMAIN_AUX_USBC1,
> > +POWER_DOMAIN_AUX_USBC2,
> > +POWER_DOMAIN_AUX_USBC3,
> > +POWER_DOMAIN_AUX_USBC4,
> > +POWER_DOMAIN_AUX_TBT1,
> > +POWER_DOMAIN_AUX_TBT2,
> > +POWER_DOMAIN_AUX_TBT3,
> > +POWER_DOMAIN_AUX_TBT4,
> > +POWER_DOMAIN_INIT);
> > +
> > +static const struct i915_power_well_desc xe2lpd_power_wells_pica[] = {
> > + {
> > + .instances = _PW_INSTANCES(I915_PW("PICA_TC",
> > + _pwdoms_pica_tc,
> > + .id = DISP_PW_ID_NONE),
> > + ),
> > + .ops = _pica_power_well_ops,
> > + },
> > +};
> > +
> > +static const struct i915_power_well_desc_list xe2lpd_power_wells[] = {
> > + I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
> > + I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
> > + I915_PW_DESCRIPTORS(xelpdp_power_wells_main),
> > + I915_PW_DESCRIPTORS(xe2lpd_power_wells_pica),
> > +};
>
> Are we missing a "dc_off" power well here? This patch might have
> originally been written before we separated dc_off out from main.
>
> Assuming the DC state requirements are the same for Xe2_LPD as they were
> for Xe_LPD and Xe_LPD+ (I haven't checked), then adding
>
> I915_PW_DESCRIPTORS(xelpd_power_wells_dc_off),
>
> immediately before xelpdp_power_wells_main should be sufficient.
Okay, this is actually taken care of by the next patch in the series.
Disregard this comment.
Matt
>
> > +
> > static void init_power_well_domains(const struct i915_power_well_instance
> > *inst,
> > struct i915_power_well *power_well)
> > {
> > @@ -1652,7 +1684,9 @@ int intel_display_power_map_init(struct
> > i915_power_domains *power_domains)
> > return 0;
> > }
> >
> > - if (DISPLAY_VER(i915) >= 14)
> > + if (DISPLAY_VER(i915) >= 20)
> > + return set_power_wells(power_domains, xe2lpd_power_wells);
> > + else if (DISPLAY_VER(i915) >= 14)
> > return set_power_wells(power_domains, xelpdp_power_wells);
> > else if (IS_DG2(i915))
> > return set_power_wells(power_domains, xehpd_power_wells);
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > index 916009894d89..e1fb0bd7b3bf 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > @@ -1795,7 +1795,11 @@ static void xelpdp_aux_power_well_enable(struct
> > drm_i915_private *dev_priv,
> > {
> > enum aux_ch aux_ch =
> > i915_power_well_instance(power_well)->xelpdp.aux_ch;
> >
> > - intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch),
> > + i915_reg_t aux_ch_ctl = DISPLAY_VER(dev_priv) >= 20 ?
> > + XE2LPD_DP_AUX_CH_CTL(aux_ch) :
> > + XELPDP_DP_AUX_CH_CTL(aux_ch);
> > +
> > + intel_de_rmw(dev_priv, aux_ch_ctl,
> > XELPDP_DP_AUX_CH_CTL_POWER_REQUEST,
> >
Re: [Intel-gfx] [Intel-xe] [PATCH 21/42] drm/i915/xe2lpd: Add display power well
On Wed, Aug 23, 2023 at 10:07:19AM -0700, Lucas De Marchi wrote:
> From: Ravi Kumar Vodapalli
>
> Add Display Power Well for LNL platform, mostly it is same as MTL
> platform so reused the code
>
> Changes are:
> 1. AUX_CH_CTL and AUX_CH_DATA1 are different from MTL so added extra
>logic xelpdp_aux_power_well_ops functions.
> 2. PGPICA1 contains type-C capable port slices which requires the well
>to power powered up, so added new power well definition for PGPICA1
>
> BSpec: 68886
> Signed-off-by: Ravi Kumar Vodapalli
> Signed-off-by: Gustavo Sousa
> Signed-off-by: Lucas De Marchi
> ---
> .../i915/display/intel_display_power_map.c| 36 ++-
> .../i915/display/intel_display_power_well.c | 63 ++-
> .../i915/display/intel_display_power_well.h | 1 +
> .../gpu/drm/i915/display/intel_dp_aux_regs.h | 27
> 4 files changed, 123 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c
> b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> index 5ad04cd42c15..cef3b313c9f5 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> @@ -1545,6 +1545,38 @@ static const struct i915_power_well_desc_list
> xelpdp_power_wells[] = {
> I915_PW_DESCRIPTORS(xelpdp_power_wells_main),
> };
>
> +I915_DECL_PW_DOMAINS(xe2lpd_pwdoms_pica_tc,
> + POWER_DOMAIN_PORT_DDI_LANES_TC1,
> + POWER_DOMAIN_PORT_DDI_LANES_TC2,
> + POWER_DOMAIN_PORT_DDI_LANES_TC3,
> + POWER_DOMAIN_PORT_DDI_LANES_TC4,
> + POWER_DOMAIN_AUX_USBC1,
> + POWER_DOMAIN_AUX_USBC2,
> + POWER_DOMAIN_AUX_USBC3,
> + POWER_DOMAIN_AUX_USBC4,
> + POWER_DOMAIN_AUX_TBT1,
> + POWER_DOMAIN_AUX_TBT2,
> + POWER_DOMAIN_AUX_TBT3,
> + POWER_DOMAIN_AUX_TBT4,
> + POWER_DOMAIN_INIT);
> +
> +static const struct i915_power_well_desc xe2lpd_power_wells_pica[] = {
> + {
> + .instances = _PW_INSTANCES(I915_PW("PICA_TC",
> + _pwdoms_pica_tc,
> + .id = DISP_PW_ID_NONE),
> +),
> + .ops = _pica_power_well_ops,
> + },
> +};
> +
> +static const struct i915_power_well_desc_list xe2lpd_power_wells[] = {
> + I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
> + I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
> + I915_PW_DESCRIPTORS(xelpdp_power_wells_main),
> + I915_PW_DESCRIPTORS(xe2lpd_power_wells_pica),
> +};
Are we missing a "dc_off" power well here? This patch might have
originally been written before we separated dc_off out from main.
Assuming the DC state requirements are the same for Xe2_LPD as they were
for Xe_LPD and Xe_LPD+ (I haven't checked), then adding
I915_PW_DESCRIPTORS(xelpd_power_wells_dc_off),
immediately before xelpdp_power_wells_main should be sufficient.
> +
> static void init_power_well_domains(const struct i915_power_well_instance
> *inst,
> struct i915_power_well *power_well)
> {
> @@ -1652,7 +1684,9 @@ int intel_display_power_map_init(struct
> i915_power_domains *power_domains)
> return 0;
> }
>
> - if (DISPLAY_VER(i915) >= 14)
> + if (DISPLAY_VER(i915) >= 20)
> + return set_power_wells(power_domains, xe2lpd_power_wells);
> + else if (DISPLAY_VER(i915) >= 14)
> return set_power_wells(power_domains, xelpdp_power_wells);
> else if (IS_DG2(i915))
> return set_power_wells(power_domains, xehpd_power_wells);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index 916009894d89..e1fb0bd7b3bf 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -1795,7 +1795,11 @@ static void xelpdp_aux_power_well_enable(struct
> drm_i915_private *dev_priv,
> {
> enum aux_ch aux_ch =
> i915_power_well_instance(power_well)->xelpdp.aux_ch;
>
> - intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch),
> + i915_reg_t aux_ch_ctl = DISPLAY_VER(dev_priv) >= 20 ?
> + XE2LPD_DP_AUX_CH_CTL(aux_ch) :
> + XELPDP_DP_AUX_CH_CTL(aux_ch);
> +
> + intel_de_rmw(dev_priv, aux_ch_ctl,
>XELPDP_DP_AUX_CH_CTL_POWER_REQUEST,
>XELPDP_DP_AUX_CH_CTL_POWER_REQUEST);
>
> @@ -1813,7 +1817,11 @@ static void xelpdp_aux_power_well_disable(struct
> drm_i915_private *dev_priv,
> {
> enum aux_ch aux_ch =
> i915_power_well_instance(power_well)->xelpdp.aux_ch;
>
> - intel_de_rmw(dev_priv,
Re: [Intel-gfx] [REGRESSION] HDMI connector detection broken in 6.3 on Intel(R) Celeron(R) N3060 integrated graphics
On Mon, Aug 21, 2023 at 11:27:29AM +0200, Maxime Ripard wrote: > On Tue, Aug 15, 2023 at 11:12:46AM +0300, Jani Nikula wrote: > > On Mon, 14 Aug 2023, Imre Deak wrote: > > > On Sun, Aug 13, 2023 at 03:41:30PM +0200, Linux regression tracking > > > (Thorsten Leemhuis) wrote: > > > Hi, > > > > > >> On 11.08.23 20:10, Mikhail Rudenko wrote: > > >> > On 2023-08-11 at 08:45 +02, Thorsten Leemhuis > > >> > wrote: > > >> >> On 10.08.23 21:33, Mikhail Rudenko wrote: > > >> >>> The following is a copy an issue I posted to drm/i915 gitlab [1] two > > >> >>> months ago. I repost it to the mailing lists in hope that it will > > >> >>> help > > >> >>> the right people pay attention to it. > > >> >> > > >> >> Thx for your report. Wonder why Dmitry (who authored a4e771729a51) or > > >> >> Thomas (who committed it) it didn't look into this, but maybe the i915 > > >> >> devs didn't forward the report to them. > > >> > > >> For the record: they did, and Jani mentioned already. Sorry, should have > > >> phrased this differently. > > >> > > >> >> Let's see if these mails help. Just wondering: does reverting > > >> >> a4e771729a51 from 6.5-rc5 or drm-tip help as well? > > >> > > > >> > I've redone my tests with 6.5-rc5, and here are the results: > > >> > (1) 6.5-rc5 -> still affected > > >> > (2) 6.5-rc5 + revert a4e771729a51 -> not affected > > >> > (3) 6.5-rc5 + two patches [1][2] suggested on i915 gitlab by @ideak -> > > >> > not affected (!) > > >> > > > >> > Should we somehow tell regzbot about (3)? > > >> > > >> That's good to know, thx. But the more important things are: > > >> > > >> * When will those be merged? They are not yet in next yet afaics, so it > > >> might take some time to mainline them, especially at this point of the > > >> devel cycle. Imre, could you try to prod the right people so that these > > >> are ideally upstreamed rather sooner than later, as they fix a > > >> regression? > > > > > > I think the patches ([1] and [2]) could be merged via the drm-intel-next > > > (drm-intel-fixes) tree Cc'ing also stable. Jani, is this ok? > > > > It's fine by me, but need drm-misc maintainer ack to merge [1] via > > drm-intel. > > That's fine for me Thanks, I pushed the patches to drm-intel-next. > Maxime
Re: [Intel-gfx] [Intel-xe] [PATCH 20/42] drm/i915/xe2lpd: Register DE_RRMR has been removed
On Wed, Aug 23, 2023 at 10:07:18AM -0700, Lucas De Marchi wrote: > From: Clint Taylor > > Do not read DE_RRMR register after display version 20. This register > contains display state information during GFX state dumps. > > Bspec: 69456 > Cc: Anusha Srivatsa > Cc: Gustavo Sousa > Signed-off-by: Clint Taylor > Signed-off-by: Lucas De Marchi > --- > drivers/gpu/drm/i915/i915_gpu_error.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c > b/drivers/gpu/drm/i915/i915_gpu_error.c > index 4749f99e6320..fe2fa6f966f2 100644 > --- a/drivers/gpu/drm/i915/i915_gpu_error.c > +++ b/drivers/gpu/drm/i915/i915_gpu_error.c > @@ -1755,7 +1755,7 @@ static void gt_record_display_regs(struct > intel_gt_coredump *gt) > struct intel_uncore *uncore = gt->_gt->uncore; > struct drm_i915_private *i915 = uncore->i915; > > - if (GRAPHICS_VER(i915) >= 6) > + if (DISPLAY_VER(i915) >= 6 && DISPLAY_VER(i915) < 20) We have IS_DISPLAY_VER() that's slightly simpler for ranges like this. Aside from that, Reviewed-by: Matt Roper Matt > gt->derrmr = intel_uncore_read(uncore, DERRMR); > > if (GRAPHICS_VER(i915) >= 8) > -- > 2.40.1 > -- Matt Roper Graphics Software Engineer Linux GPU Platform Enablement Intel Corporation
Re: [Intel-gfx] [Intel-xe] [PATCH 18/42] drm/i915/xe2lpd: Move registers to PICA
On Wed, Aug 23, 2023 at 10:07:16AM -0700, Lucas De Marchi wrote:
> Some registers for DDI A/B moved to PICA and now follow the same format
> as the ones for the PORT_TC ports. The wrapper here deals with 2 issues:
>
> - Share the implementation between xe2lpd and previous
> platforms: there are minor layout changes, it's mostly the
> register location that changed
> - Handle offsets after TC ports
>
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 81 ++-
> .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 71 ++--
> drivers/gpu/drm/i915/display/intel_ddi.c | 18 +++--
> 3 files changed, 117 insertions(+), 53 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index a5918bf30c31..6533ec417806 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -98,7 +98,7 @@ static void intel_cx0_phy_transaction_end(struct
> intel_encoder *encoder, intel_w
> static void intel_clear_response_ready_flag(struct drm_i915_private *i915,
> enum port port, int lane)
> {
> - intel_de_rmw(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane),
> + intel_de_rmw(i915, xelpdp_port_p2m_msgbus_status_reg(i915, port, lane),
>0, XELPDP_PORT_P2M_RESPONSE_READY |
> XELPDP_PORT_P2M_ERROR_SET);
> }
>
> @@ -106,10 +106,10 @@ static void intel_cx0_bus_reset(struct drm_i915_private
> *i915, enum port port, i
> {
> enum phy phy = intel_port_to_phy(i915, port);
>
> - intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
> + intel_de_write(i915, xelpdp_port_m2p_msgbus_ctl_reg(i915, port, lane),
> XELPDP_PORT_M2P_TRANSACTION_RESET);
>
> - if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port,
> lane),
> + if (intel_de_wait_for_clear(i915, xelpdp_port_m2p_msgbus_ctl_reg(i915,
> port, lane),
> XELPDP_PORT_M2P_TRANSACTION_RESET,
> XELPDP_MSGBUS_TIMEOUT_SLOW)) {
> drm_err_once(>drm, "Failed to bring PHY %c to idle.\n",
> phy_name(phy));
> @@ -125,7 +125,7 @@ static int intel_cx0_wait_for_ack(struct drm_i915_private
> *i915, enum port port,
> enum phy phy = intel_port_to_phy(i915, port);
>
> if (__intel_de_wait_for_register(i915,
> - XELPDP_PORT_P2M_MSGBUS_STATUS(port,
> lane),
> +
> xelpdp_port_p2m_msgbus_status_reg(i915, port, lane),
>XELPDP_PORT_P2M_RESPONSE_READY,
>XELPDP_PORT_P2M_RESPONSE_READY,
>XELPDP_MSGBUS_TIMEOUT_FAST_US,
> @@ -160,7 +160,7 @@ static int __intel_cx0_read_once(struct drm_i915_private
> *i915, enum port port,
> int ack;
> u32 val;
>
> - if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port,
> lane),
> + if (intel_de_wait_for_clear(i915, xelpdp_port_m2p_msgbus_ctl_reg(i915,
> port, lane),
> XELPDP_PORT_M2P_TRANSACTION_PENDING,
> XELPDP_MSGBUS_TIMEOUT_SLOW)) {
> drm_dbg_kms(>drm,
> @@ -169,7 +169,7 @@ static int __intel_cx0_read_once(struct drm_i915_private
> *i915, enum port port,
> return -ETIMEDOUT;
> }
>
> - intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
> + intel_de_write(i915, xelpdp_port_m2p_msgbus_ctl_reg(i915, port, lane),
> XELPDP_PORT_M2P_TRANSACTION_PENDING |
> XELPDP_PORT_M2P_COMMAND_READ |
> XELPDP_PORT_M2P_ADDRESS(addr));
> @@ -220,7 +220,7 @@ static int __intel_cx0_write_once(struct drm_i915_private
> *i915, enum port port,
> int ack;
> u32 val;
>
> - if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port,
> lane),
> + if (intel_de_wait_for_clear(i915, xelpdp_port_m2p_msgbus_ctl_reg(i915,
> port, lane),
> XELPDP_PORT_M2P_TRANSACTION_PENDING,
> XELPDP_MSGBUS_TIMEOUT_SLOW)) {
> drm_dbg_kms(>drm,
> @@ -229,14 +229,14 @@ static int __intel_cx0_write_once(struct
> drm_i915_private *i915, enum port port,
> return -ETIMEDOUT;
> }
>
> - intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
> + intel_de_write(i915, xelpdp_port_m2p_msgbus_ctl_reg(i915, port, lane),
> XELPDP_PORT_M2P_TRANSACTION_PENDING |
> (committed ? XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED :
> XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED) |
> XELPDP_PORT_M2P_DATA(data) |
>
[Intel-gfx] [PATCH v2 1/2] drm/i915: Add WABB blit for Wa_16018031267 / Wa_16018063123
From: Nirmoy Das
Apply WABB blit for Wa_16018031267 / Wa_16018063123.
Additionally, update the lrc selftest to exercise the new
WABB changes.
Signed-off-by: Jonathan Cavitt
Co-developed-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/intel_engine_regs.h | 3 +
drivers/gpu/drm/i915/gt/intel_gt_types.h| 3 +
drivers/gpu/drm/i915/gt/intel_lrc.c | 114 +++-
drivers/gpu/drm/i915/gt/selftest_lrc.c | 65 +++
drivers/gpu/drm/i915/i915_drv.h | 5 +
5 files changed, 169 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_regs.h
b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
index 6b9d9f837669..2e06bea73297 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
@@ -118,6 +118,9 @@
#define CCID_EXTENDED_STATE_RESTORE BIT(2)
#define CCID_EXTENDED_STATE_SAVE BIT(3)
#define RING_BB_PER_CTX_PTR(base) _MMIO((base) + 0x1c0) /* gen8+
*/
+#define PER_CTX_BB_FORCE BIT(2)
+#define PER_CTX_BB_VALID BIT(0)
+
#define RING_INDIRECT_CTX(base)_MMIO((base) + 0x1c4)
/* gen8+ */
#define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base) + 0x1c8) /* gen8+
*/
#define ECOSKPD(base) _MMIO((base) + 0x1d0)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index def7dd0eb6f1..81989659ff78 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -307,6 +307,9 @@ enum intel_gt_scratch_field {
/* 8 bytes */
INTEL_GT_SCRATCH_FIELD_COHERENTL3_WA = 256,
+
+ /* 8 bytes */
+ INTEL_GT_SCRATCH_FIELD_DUMMY_BLIT = 384,
};
#define intel_gt_support_legacy_fencing(gt) ((gt)->ggtt->num_fences > 0)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 967fe4d77a87..444ad1977b10 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -828,6 +828,18 @@ lrc_ring_indirect_offset_default(const struct
intel_engine_cs *engine)
return 0;
}
+static void
+lrc_setup_bb_per_ctx(u32 *regs,
+const struct intel_engine_cs *engine,
+u32 ctx_bb_ggtt_addr)
+{
+ GEM_BUG_ON(lrc_ring_wa_bb_per_ctx(engine) == -1);
+ regs[lrc_ring_wa_bb_per_ctx(engine) + 1] =
+ ctx_bb_ggtt_addr |
+ PER_CTX_BB_FORCE |
+ PER_CTX_BB_VALID;
+}
+
static void
lrc_setup_indirect_ctx(u32 *regs,
const struct intel_engine_cs *engine,
@@ -997,7 +1009,18 @@ static u32 context_wa_bb_offset(const struct
intel_context *ce)
return PAGE_SIZE * ce->wa_bb_page;
}
-static u32 *context_indirect_bb(const struct intel_context *ce)
+/**
+ * context_wabb -
+ * Generates the location of the desired batch buffer used for workarounds
+ * @ce:The context used for the workaround.
+ * @per_ctx: When enabled, the function returns the location of
+ * the PER_CTX_BB. When disabled, the function returns
+ * the location of the INDIRECT_CTX.
+ *
+ * Returns: The location of the PER_CTX_BB or INDIRECT_CTX in the ce
+ * context, depending on if per_ctx is true or false, respectively.
+ */
+static u32 *context_wabb(const struct intel_context *ce, bool per_ctx)
{
void *ptr;
@@ -1006,6 +1029,7 @@ static u32 *context_indirect_bb(const struct
intel_context *ce)
ptr = ce->lrc_reg_state;
ptr -= LRC_STATE_OFFSET; /* back to start of context image */
ptr += context_wa_bb_offset(ce);
+ ptr += per_ctx ? PAGE_SIZE : 0;
return ptr;
}
@@ -1082,7 +1106,8 @@ __lrc_alloc_state(struct intel_context *ce, struct
intel_engine_cs *engine)
if (GRAPHICS_VER(engine->i915) >= 12) {
ce->wa_bb_page = context_size / PAGE_SIZE;
- context_size += PAGE_SIZE;
+ /* INDIRECT_CTX and PER_CTX_BB need separate pages. */
+ context_size += PAGE_SIZE * 2;
}
if (intel_context_is_parent(ce) && intel_engine_uses_guc(engine)) {
@@ -1370,12 +1395,94 @@ gen12_emit_indirect_ctx_xcs(const struct intel_context
*ce, u32 *cs)
return gen12_emit_aux_table_inv(ce->engine, cs);
}
+static u32 *xehp_emit_fastcolor_blt_wabb(const struct intel_context *ce, u32
*cs)
+{
+ struct intel_gt *gt = ce->engine->gt;
+ int mocs = gt->mocs.uc_index << 1;
+ u32 addr = intel_gt_scratch_offset(gt,
INTEL_GT_SCRATCH_FIELD_DUMMY_BLIT);
+
+ /**
+* Wa_16018031267 / Wa_16018063123 requires that SW forces the
+* main copy engine arbitration into round robin mode. We
+* additionally need to submit the following WABB blt command
+* to produce 4 subblits with each subblit generating 0 byte
+* write requests as WABB:
+*
+*
[Intel-gfx] [PATCH v2 2/2] drm/i915: Set copy engine arbitration for Wa_16018031267 / Wa_16018063123
From: Nirmoy Das Set copy engine arbitration into round robin mode for part of Wa_16018031267 / Wa_16018063123 mitigation. Signed-off-by: Nirmoy Das Signed-off-by: Jonathan Cavitt --- drivers/gpu/drm/i915/gt/intel_engine_regs.h | 3 +++ drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++ 2 files changed, 9 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_regs.h b/drivers/gpu/drm/i915/gt/intel_engine_regs.h index 2e06bea73297..823c6c40213f 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_regs.h @@ -124,6 +124,9 @@ #define RING_INDIRECT_CTX(base)_MMIO((base) + 0x1c4) /* gen8+ */ #define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base) + 0x1c8) /* gen8+ */ #define ECOSKPD(base) _MMIO((base) + 0x1d0) +#define XEHP_BLITTER_SCHEDULING_MODE_MASKREG_GENMASK(12, 11) +#define XEHP_BLITTER_ROUND_ROBIN_MODE\ + REG_FIELD_PREP(XEHP_BLITTER_SCHEDULING_MODE_MASK, 1) #define ECO_CONSTANT_BUFFER_SR_DISABLE REG_BIT(4) #define ECO_GATING_CX_ONLY REG_BIT(3) #define GEN6_BLITTER_FBC_NOTIFY REG_BIT(3) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 864d41bcf6bb..674ac99d8a83 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -2769,6 +2769,12 @@ xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) RING_SEMA_WAIT_POLL(engine->mmio_base), 1); } + /* Wa_16018031267, Wa_16018063123 */ + if (engine->class == COPY_ENGINE_CLASS && + NEEDS_FASTCOLOR_BLT_WABB(i915)) + wa_masked_field_set(wal, ECOSKPD(engine->mmio_base), + XEHP_BLITTER_SCHEDULING_MODE_MASK, + XEHP_BLITTER_ROUND_ROBIN_MODE); } static void -- 2.25.1
[Intel-gfx] [PATCH v2 0/2] Apply Wa_16018031267 / Wa_16018063123
Apply Wa_16018031267 / Wa_16018063123. This necessitates submitting a fastcolor blit as WABB and setting the copy engine arbitration to round-robin mode. v2: - Rename old platform check in second patch to match declaration in first patch. - Refactor second patch name to match first patch. Signed-off-by: Nirmoy Das Signed-off-by: Jonathan Cavitt CC: Joonas Lahtinen CC: Rodrigo Vivi CC: Tomasz Mistat CC: Gregory F Germano CC: Matt Roper CC: James Ausmus Nirmoy Das (2): drm/i915: Add WABB blit for Wa_16018031267 / Wa_16018063123 drm/i915: Set copy engine arbitration for Wa_16018031267 / Wa_16018063123 drivers/gpu/drm/i915/gt/intel_engine_regs.h | 6 ++ drivers/gpu/drm/i915/gt/intel_gt_types.h| 3 + drivers/gpu/drm/i915/gt/intel_lrc.c | 114 +++- drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++ drivers/gpu/drm/i915/gt/selftest_lrc.c | 65 +++ drivers/gpu/drm/i915/i915_drv.h | 5 + 6 files changed, 178 insertions(+), 21 deletions(-) -- 2.25.1
Re: [Intel-gfx] [Intel-xe] [PATCH 16/42] drm/i915/xe2lpd: Move D2D enable/disable
On Wed, Aug 23, 2023 at 10:07:14AM -0700, Lucas De Marchi wrote:
> Bits to enable/disable and check state for D2D moved from
> XELPDP_PORT_BUF_CTL1 to DDI_BUF_CTL. Make the functions
As of Xe2, DDI_BUF_CTL is now renamed to "DDI_CTL_DE" in the spec, so
you might want to toss a mention of the new register name in the commit
message here to make it easier to lookup in the spec. E.g.,
"... (now named DDI_CTL_DE in the spec) ..." Otherwise,
Reviewed-by: Matt Roper
> mtl_ddi_disable_d2d() and mtl_ddi_enable_d2d generic to work with
> multiple reg location and bitfield layout.
>
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 38 +---
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> 2 files changed, 30 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 61722556bb47..a9440c0ecf61 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2356,13 +2356,22 @@ mtl_ddi_enable_d2d(struct intel_encoder *encoder)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> enum port port = encoder->port;
> + i915_reg_t reg;
> + u32 set_bits, wait_bits;
>
> - intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port), 0,
> - XELPDP_PORT_BUF_D2D_LINK_ENABLE);
> + if (DISPLAY_VER(dev_priv) >= 20) {
> + reg = DDI_BUF_CTL(port);
> + set_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
> + wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
> + } else {
> + reg = XELPDP_PORT_BUF_CTL1(port);
> + set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
> + wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
> + }
>
> - if (wait_for_us((intel_de_read(dev_priv, XELPDP_PORT_BUF_CTL1(port)) &
> - XELPDP_PORT_BUF_D2D_LINK_STATE), 100)) {
> - drm_err(_priv->drm, "Timeout waiting for D2D Link enable
> for PORT_BUF_CTL %c\n",
> + intel_de_rmw(dev_priv, reg, 0, set_bits);
> + if (wait_for_us(intel_de_read(dev_priv, reg) & wait_bits, 100)) {
> + drm_err(_priv->drm, "Timeout waiting for D2D Link enable
> for DDI/PORT_BUF_CTL %c\n",
> port_name(port));
> }
> }
> @@ -2809,13 +2818,22 @@ mtl_ddi_disable_d2d_link(struct intel_encoder
> *encoder)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> enum port port = encoder->port;
> + i915_reg_t reg;
> + u32 clr_bits, wait_bits;
>
> - intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port),
> - XELPDP_PORT_BUF_D2D_LINK_ENABLE, 0);
> + if (DISPLAY_VER(dev_priv) >= 20) {
> + reg = DDI_BUF_CTL(port);
> + clr_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
> + wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
> + } else {
> + reg = XELPDP_PORT_BUF_CTL1(port);
> + clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
> + wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
> + }
>
> - if (wait_for_us(!(intel_de_read(dev_priv, XELPDP_PORT_BUF_CTL1(port)) &
> - XELPDP_PORT_BUF_D2D_LINK_STATE), 100))
> - drm_err(_priv->drm, "Timeout waiting for D2D Link disable
> for PORT_BUF_CTL %c\n",
> + intel_de_rmw(dev_priv, reg, clr_bits, 0);
> + if (wait_for_us(!(intel_de_read(dev_priv, reg) & wait_bits), 100))
> + drm_err(_priv->drm, "Timeout waiting for D2D Link disable
> for DDI/PORT_BUF_CTL %c\n",
> port_name(port));
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index dcf64e32cd54..84c5a76065a0 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5723,6 +5723,8 @@ enum skl_power_gate {
> /* Known as DDI_CTL_DE in MTL+ */
> #define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B)
> #define DDI_BUF_CTL_ENABLE (1 << 31)
> +#define XE2LPD_DDI_BUF_D2D_LINK_ENABLE REG_BIT(29)
> +#define XE2LPD_DDI_BUF_D2D_LINK_STATE REG_BIT(28)
> #define DDI_BUF_TRANS_SELECT(n) ((n) << 24)
> #define DDI_BUF_EMP_MASK(0xf << 24)
> #define DDI_BUF_PHY_LINK_RATE(r)((r) << 20)
> --
> 2.40.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
[Intel-gfx] [PATCH 0/2] Apply Wa_16018031267 / Wa_16018063123
Apply Wa_16018031267 / Wa_16018063123. This necessitates submitting a fastcolor blit as WABB and setting the copy engine arbitration to round-robin mode. Signed-off-by: Nirmoy Das Signed-off-by: Jonathan Cavitt CC: Joonas Lahtinen CC: Rodrigo Vivi CC: Tomasz Mistat CC: Gregory F Germano CC: Matt Roper CC: James Ausmus Nirmoy Das (2): drm/i915: Add WABB blit for Wa_16018031267 / Wa_16018063123 drm/i915: Set copy engine arbitration for pipeblit WA drivers/gpu/drm/i915/gt/intel_engine_regs.h | 6 ++ drivers/gpu/drm/i915/gt/intel_gt_types.h| 3 + drivers/gpu/drm/i915/gt/intel_lrc.c | 114 +++- drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++ drivers/gpu/drm/i915/gt/selftest_lrc.c | 65 +++ drivers/gpu/drm/i915/i915_drv.h | 5 + 6 files changed, 178 insertions(+), 21 deletions(-) -- 2.25.1
[Intel-gfx] [PATCH 1/2] drm/i915: Add WABB blit for Wa_16018031267 / Wa_16018063123
From: Nirmoy Das
Apply WABB blit for Wa_16018031267 / Wa_16018063123.
Additionally, update the lrc selftest to exercise the new
WABB changes.
Signed-off-by: Jonathan Cavitt
Co-developed-by: Nirmoy Das
---
drivers/gpu/drm/i915/gt/intel_engine_regs.h | 3 +
drivers/gpu/drm/i915/gt/intel_gt_types.h| 3 +
drivers/gpu/drm/i915/gt/intel_lrc.c | 114 +++-
drivers/gpu/drm/i915/gt/selftest_lrc.c | 65 +++
drivers/gpu/drm/i915/i915_drv.h | 5 +
5 files changed, 169 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_regs.h
b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
index 6b9d9f837669..2e06bea73297 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
@@ -118,6 +118,9 @@
#define CCID_EXTENDED_STATE_RESTORE BIT(2)
#define CCID_EXTENDED_STATE_SAVE BIT(3)
#define RING_BB_PER_CTX_PTR(base) _MMIO((base) + 0x1c0) /* gen8+
*/
+#define PER_CTX_BB_FORCE BIT(2)
+#define PER_CTX_BB_VALID BIT(0)
+
#define RING_INDIRECT_CTX(base)_MMIO((base) + 0x1c4)
/* gen8+ */
#define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base) + 0x1c8) /* gen8+
*/
#define ECOSKPD(base) _MMIO((base) + 0x1d0)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index def7dd0eb6f1..81989659ff78 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -307,6 +307,9 @@ enum intel_gt_scratch_field {
/* 8 bytes */
INTEL_GT_SCRATCH_FIELD_COHERENTL3_WA = 256,
+
+ /* 8 bytes */
+ INTEL_GT_SCRATCH_FIELD_DUMMY_BLIT = 384,
};
#define intel_gt_support_legacy_fencing(gt) ((gt)->ggtt->num_fences > 0)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 967fe4d77a87..444ad1977b10 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -828,6 +828,18 @@ lrc_ring_indirect_offset_default(const struct
intel_engine_cs *engine)
return 0;
}
+static void
+lrc_setup_bb_per_ctx(u32 *regs,
+const struct intel_engine_cs *engine,
+u32 ctx_bb_ggtt_addr)
+{
+ GEM_BUG_ON(lrc_ring_wa_bb_per_ctx(engine) == -1);
+ regs[lrc_ring_wa_bb_per_ctx(engine) + 1] =
+ ctx_bb_ggtt_addr |
+ PER_CTX_BB_FORCE |
+ PER_CTX_BB_VALID;
+}
+
static void
lrc_setup_indirect_ctx(u32 *regs,
const struct intel_engine_cs *engine,
@@ -997,7 +1009,18 @@ static u32 context_wa_bb_offset(const struct
intel_context *ce)
return PAGE_SIZE * ce->wa_bb_page;
}
-static u32 *context_indirect_bb(const struct intel_context *ce)
+/**
+ * context_wabb -
+ * Generates the location of the desired batch buffer used for workarounds
+ * @ce:The context used for the workaround.
+ * @per_ctx: When enabled, the function returns the location of
+ * the PER_CTX_BB. When disabled, the function returns
+ * the location of the INDIRECT_CTX.
+ *
+ * Returns: The location of the PER_CTX_BB or INDIRECT_CTX in the ce
+ * context, depending on if per_ctx is true or false, respectively.
+ */
+static u32 *context_wabb(const struct intel_context *ce, bool per_ctx)
{
void *ptr;
@@ -1006,6 +1029,7 @@ static u32 *context_indirect_bb(const struct
intel_context *ce)
ptr = ce->lrc_reg_state;
ptr -= LRC_STATE_OFFSET; /* back to start of context image */
ptr += context_wa_bb_offset(ce);
+ ptr += per_ctx ? PAGE_SIZE : 0;
return ptr;
}
@@ -1082,7 +1106,8 @@ __lrc_alloc_state(struct intel_context *ce, struct
intel_engine_cs *engine)
if (GRAPHICS_VER(engine->i915) >= 12) {
ce->wa_bb_page = context_size / PAGE_SIZE;
- context_size += PAGE_SIZE;
+ /* INDIRECT_CTX and PER_CTX_BB need separate pages. */
+ context_size += PAGE_SIZE * 2;
}
if (intel_context_is_parent(ce) && intel_engine_uses_guc(engine)) {
@@ -1370,12 +1395,94 @@ gen12_emit_indirect_ctx_xcs(const struct intel_context
*ce, u32 *cs)
return gen12_emit_aux_table_inv(ce->engine, cs);
}
+static u32 *xehp_emit_fastcolor_blt_wabb(const struct intel_context *ce, u32
*cs)
+{
+ struct intel_gt *gt = ce->engine->gt;
+ int mocs = gt->mocs.uc_index << 1;
+ u32 addr = intel_gt_scratch_offset(gt,
INTEL_GT_SCRATCH_FIELD_DUMMY_BLIT);
+
+ /**
+* Wa_16018031267 / Wa_16018063123 requires that SW forces the
+* main copy engine arbitration into round robin mode. We
+* additionally need to submit the following WABB blt command
+* to produce 4 subblits with each subblit generating 0 byte
+* write requests as WABB:
+*
+*
[Intel-gfx] [PATCH 2/2] drm/i915: Set copy engine arbitration for pipeblit WA
From: Nirmoy Das Set copy engine arbitration into round robin mode for part of Wa_16018031267 / Wa_16018063123 mitigation. Signed-off-by: Nirmoy Das Signed-off-by: Jonathan Cavitt --- drivers/gpu/drm/i915/gt/intel_engine_regs.h | 3 +++ drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++ 2 files changed, 9 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_regs.h b/drivers/gpu/drm/i915/gt/intel_engine_regs.h index 2e06bea73297..823c6c40213f 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_regs.h @@ -124,6 +124,9 @@ #define RING_INDIRECT_CTX(base)_MMIO((base) + 0x1c4) /* gen8+ */ #define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base) + 0x1c8) /* gen8+ */ #define ECOSKPD(base) _MMIO((base) + 0x1d0) +#define XEHP_BLITTER_SCHEDULING_MODE_MASKREG_GENMASK(12, 11) +#define XEHP_BLITTER_ROUND_ROBIN_MODE\ + REG_FIELD_PREP(XEHP_BLITTER_SCHEDULING_MODE_MASK, 1) #define ECO_CONSTANT_BUFFER_SR_DISABLE REG_BIT(4) #define ECO_GATING_CX_ONLY REG_BIT(3) #define GEN6_BLITTER_FBC_NOTIFY REG_BIT(3) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 864d41bcf6bb..8d5c13752599 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -2769,6 +2769,12 @@ xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) RING_SEMA_WAIT_POLL(engine->mmio_base), 1); } + /* Wa_16018031267, Wa_16018063123 */ + if (engine->class == COPY_ENGINE_CLASS && + NEEDS_DUMMY_PIPEBLT_WABB(i915)) + wa_masked_field_set(wal, ECOSKPD(engine->mmio_base), + XEHP_BLITTER_SCHEDULING_MODE_MASK, + XEHP_BLITTER_ROUND_ROBIN_MODE); } static void -- 2.25.1
[Intel-gfx] PR for GSC FW release 102.0.0.1655 for MTL
The following changes since commit 0e048b061bde79ad735c7b7b5161ee1bd3400150: Merge branch 'for-upstream' of https://github.com/CirrusLogic/linux-firmware (2023-08-14 13:03:41 -0400) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-firmware mtl_gsc_1655 for you to fetch changes up to 81caac98eda1696fa057191ee969c377154a: i915: add GSC 102.0.0.1655 for MTL (2023-08-21 14:13:11 -0700) Daniele Ceraolo Spurio (1): i915: add GSC 102.0.0.1655 for MTL WHENCE | 3 +++ i915/mtl_gsc_1.bin | Bin 0 -> 1142784 bytes 2 files changed, 3 insertions(+) create mode 100755 i915/mtl_gsc_1.bin
Re: [Intel-gfx] [Intel-xe] [PATCH 15/42] drm/i915/xe2lpd: Treat cursor plane as regular plane for DDB allocation
On Wed, Aug 23, 2023 at 10:07:13AM -0700, Lucas De Marchi wrote:
> From: Stanislav Lisovskiy
>
> We now start calculating relative plane data rate for sursor plane as
s/sursor/cursor/
> well, as instructed by BSpec and also treat cursor plane same way as
> other planes, when doing allocation, i.e not using fixed allocation for
> cursor anymore.
>
> Signed-off-by: Stanislav Lisovskiy
> Signed-off-by: Lucas De Marchi
Bspec: 68907
Reviewed-by: Matt Roper
> ---
> .../gpu/drm/i915/display/intel_atomic_plane.c| 6 +++---
> drivers/gpu/drm/i915/display/skl_watermark.c | 16 +---
> 2 files changed, 12 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index cb60165bc415..fb13f0bb8c52 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -219,9 +219,6 @@ intel_plane_relative_data_rate(const struct
> intel_crtc_state *crtc_state,
> int width, height;
> unsigned int rel_data_rate;
>
> - if (plane->id == PLANE_CURSOR)
> - return 0;
> -
> if (!plane_state->uapi.visible)
> return 0;
>
> @@ -249,6 +246,9 @@ intel_plane_relative_data_rate(const struct
> intel_crtc_state *crtc_state,
>
> rel_data_rate = width * height * fb->format->cpp[color_plane];
>
> + if (plane->id == PLANE_CURSOR)
> + return rel_data_rate;
> +
> return intel_adjusted_rate(_state->uapi.src,
> _state->uapi.dst,
> rel_data_rate);
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
> b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 063929a42a42..64a122d3c9c0 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -1367,7 +1367,7 @@ skl_total_relative_data_rate(const struct
> intel_crtc_state *crtc_state)
> u64 data_rate = 0;
>
> for_each_plane_id_on_crtc(crtc, plane_id) {
> - if (plane_id == PLANE_CURSOR)
> + if (plane_id == PLANE_CURSOR && DISPLAY_VER(i915) < 20)
> continue;
>
> data_rate += crtc_state->rel_data_rate[plane_id];
> @@ -1514,10 +1514,12 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state
> *state,
> return 0;
>
> /* Allocate fixed number of blocks for cursor. */
> - cursor_size = skl_cursor_allocation(crtc_state, num_active);
> - iter.size -= cursor_size;
> - skl_ddb_entry_init(_state->wm.skl.plane_ddb[PLANE_CURSOR],
> -alloc->end - cursor_size, alloc->end);
> + if (DISPLAY_VER(i915) < 20) {
> + cursor_size = skl_cursor_allocation(crtc_state, num_active);
> + iter.size -= cursor_size;
> + skl_ddb_entry_init(_state->wm.skl.plane_ddb[PLANE_CURSOR],
> +alloc->end - cursor_size, alloc->end);
> + }
>
> iter.data_rate = skl_total_relative_data_rate(crtc_state);
>
> @@ -1531,7 +1533,7 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state
> *state,
> const struct skl_plane_wm *wm =
> _state->wm.skl.optimal.planes[plane_id];
>
> - if (plane_id == PLANE_CURSOR) {
> + if (plane_id == PLANE_CURSOR && DISPLAY_VER(i915) < 20)
> {
> const struct skl_ddb_entry *ddb =
> _state->wm.skl.plane_ddb[plane_id];
>
> @@ -1579,7 +1581,7 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state
> *state,
> const struct skl_plane_wm *wm =
> _state->wm.skl.optimal.planes[plane_id];
>
> - if (plane_id == PLANE_CURSOR)
> + if (plane_id == PLANE_CURSOR && DISPLAY_VER(i915) < 20)
> continue;
>
> if (DISPLAY_VER(i915) < 11 &&
> --
> 2.40.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
Re: [Intel-gfx] [Intel-xe] [PATCH 14/42] drm/i915/lnl: Add fake PCH
On Wed, Aug 23, 2023 at 10:07:12AM -0700, Lucas De Marchi wrote:
> From: Gustavo Sousa
>
> LNL has south display on the same SoC. As such, define a new fake PCH
> entry for it.
As mentioned on the earlier patches, either matching on display IP or
PICA ID might be more appropriate than matching on LNL base platform?
Matt
>
> Signed-off-by: Gustavo Sousa
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/soc/intel_pch.c | 5 -
> drivers/gpu/drm/i915/soc/intel_pch.h | 2 ++
> 2 files changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/soc/intel_pch.c
> b/drivers/gpu/drm/i915/soc/intel_pch.c
> index cf795ecdcc26..5b9a01d26cab 100644
> --- a/drivers/gpu/drm/i915/soc/intel_pch.c
> +++ b/drivers/gpu/drm/i915/soc/intel_pch.c
> @@ -220,7 +220,10 @@ void intel_detect_pch(struct drm_i915_private *dev_priv)
>* South display engine on the same PCI device: just assign the fake
>* PCH.
>*/
> - if (IS_DG2(dev_priv)) {
> + if (IS_LUNARLAKE(dev_priv)) {
> + dev_priv->pch_type = PCH_LNL;
> + return;
> + } else if (IS_DG2(dev_priv)) {
> dev_priv->pch_type = PCH_DG2;
> return;
> } else if (IS_DG1(dev_priv)) {
> diff --git a/drivers/gpu/drm/i915/soc/intel_pch.h
> b/drivers/gpu/drm/i915/soc/intel_pch.h
> index 32aff5a70d04..1b03ea60a7a8 100644
> --- a/drivers/gpu/drm/i915/soc/intel_pch.h
> +++ b/drivers/gpu/drm/i915/soc/intel_pch.h
> @@ -30,6 +30,7 @@ enum intel_pch {
> /* Fake PCHs, functionality handled on the same PCI dev */
> PCH_DG1 = 1024,
> PCH_DG2,
> + PCH_LNL,
> };
>
> #define INTEL_PCH_DEVICE_ID_MASK 0xff80
> @@ -66,6 +67,7 @@ enum intel_pch {
>
> #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
> #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
> +#define HAS_PCH_LNL(dev_priv)
> (INTEL_PCH_TYPE(dev_priv) == PCH_LNL)
> #define HAS_PCH_MTP(dev_priv)
> (INTEL_PCH_TYPE(dev_priv) == PCH_MTP)
> #define HAS_PCH_DG2(dev_priv)
> (INTEL_PCH_TYPE(dev_priv) == PCH_DG2)
> #define HAS_PCH_ADP(dev_priv)
> (INTEL_PCH_TYPE(dev_priv) == PCH_ADP)
> --
> 2.40.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
Re: [Intel-gfx] [Intel-xe] [PATCH 13/42] drm/i915: Re-order if/else ladder in intel_detect_pch()
On Wed, Aug 23, 2023 at 10:07:11AM -0700, Lucas De Marchi wrote:
> Follow the convention of checking the last platform first and reword the
> comment to convey there are more platforms than just DG1.
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/soc/intel_pch.c | 13 -
> 1 file changed, 8 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/soc/intel_pch.c
> b/drivers/gpu/drm/i915/soc/intel_pch.c
> index ba9843cb1b13..cf795ecdcc26 100644
> --- a/drivers/gpu/drm/i915/soc/intel_pch.c
> +++ b/drivers/gpu/drm/i915/soc/intel_pch.c
> @@ -216,13 +216,16 @@ void intel_detect_pch(struct drm_i915_private *dev_priv)
> unsigned short id;
> enum intel_pch pch_type;
>
> - /* DG1 has south engine display on the same PCI device */
> - if (IS_DG1(dev_priv)) {
> - dev_priv->pch_type = PCH_DG1;
> - return;
> - } else if (IS_DG2(dev_priv)) {
> + /*
> + * South display engine on the same PCI device: just assign the fake
> + * PCH.
> + */
> + if (IS_DG2(dev_priv)) {
> dev_priv->pch_type = PCH_DG2;
> return;
> + } else if (IS_DG1(dev_priv)) {
> + dev_priv->pch_type = PCH_DG1;
> + return;
> }
>
> /*
> --
> 2.40.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
Re: [Intel-gfx] [Intel-xe] [PATCH 12/42] drm/i915/lnl: Add display definitions
On Wed, Aug 23, 2023 at 10:07:10AM -0700, Lucas De Marchi wrote:
> From: Balasubramani Vivekanandan
>
> Add Lunar Lake platform definitions for i915 display. The support for
> LNL will be added to the xe driver, with i915 only driving the display
> side. Therefore define IS_LUNARLAKE to 0 to disable it when building the
> i915 module.
>
> Signed-off-by: Balasubramani Vivekanandan
>
> Signed-off-by: Lucas De Marchi
> ---
> .../gpu/drm/i915/display/intel_display_device.c | 15 +++
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> 2 files changed, 16 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
> b/drivers/gpu/drm/i915/display/intel_display_device.c
> index f87470da25d0..b853cd0c704a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> @@ -727,6 +727,20 @@ static const struct intel_display_device_info
> xe_lpdp_display = {
> BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
> };
>
> +static const struct intel_display_device_info xe2_lpd_display = {
> + XE_LPD_FEATURES,
> + .has_cdclk_crawl = 1,
> + .has_cdclk_squash = 1,
XE_LPD_FEATURES, crawl, squash, transcoder mask, and port mask are all
common between Xe_LPD+ and Xe2_LPD. Maybe we should add an
XE_LPDP_FEATURES macro first, and then re-use it here so that the deltas
are smaller and it's more obvious what the key changes are with this new
IP?
> +
> + .__runtime_defaults.ip.ver = 20,
> + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B),
With Xe2, FBC is supported on all pipes now (bspec 68881, 68904).
> + .__runtime_defaults.cpu_transcoder_mask =
> + BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
> + BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
> + .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
> + BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
> +};
> +
> __diag_pop();
>
> #undef INTEL_VGA_DEVICE
> @@ -795,6 +809,7 @@ static const struct {
> const struct intel_display_device_info *display;
> } gmdid_display_map[] = {
> { 14, 0, _lpdp_display },
> + { 20, 0, _lpd_display },
> };
>
> static const struct intel_display_device_info *
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 07f79b1028e1..96ac9a9cc155 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -574,6 +574,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define IS_DG2(i915) IS_PLATFORM(i915, INTEL_DG2)
> #define IS_PONTEVECCHIO(i915) IS_PLATFORM(i915, INTEL_PONTEVECCHIO)
> #define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE)
> +#define IS_LUNARLAKE(dev_priv) 0
As noted on the previous patch, we might be able to drop this completely
if we update the fake PCH and gmbus code to match on display IP. Given
that PCH isn't even involved in south display handling anymore, that
seems like it might be reasonable? If anything, we're more likely to
need to match on PICA ID (which has its own GMD_ID register) than base
platform at some point in the future.
Matt
>
> #define IS_METEORLAKE_M(i915) \
> IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M)
> --
> 2.40.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
Re: [Intel-gfx] [Intel-xe] [PATCH 11/42] drm/xe/lnl: Add IS_LUNARLAKE
On Wed, Aug 23, 2023 at 10:07:09AM -0700, Lucas De Marchi wrote: > From: Balasubramani Vivekanandan > > Add IS_LUNARLAKE in the compat-i915-headers. That macro, to be used by > the xe driver, checks for the platform, whereas the macro on the i915 > side is always false. Stepping back, do we really need this macro? Most display code should be matching on the display IP rather than the platform going forward. Looking at this series, I only see this used for fake PCH and GMBUS, both of which I think could probably be checking the display IP rather than the platform. Matt > > Signed-off-by: Balasubramani Vivekanandan > > --- > drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h > b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h > index d64d34181790..38b64ff6b9ea 100644 > --- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h > +++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h > @@ -79,6 +79,7 @@ static inline struct drm_i915_private *kdev_to_i915(struct > device *kdev) > #define IS_DG2(dev_priv) IS_PLATFORM(dev_priv, XE_DG2) > #define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, XE_PVC) > #define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_METEORLAKE) > +#define IS_LUNARLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_LUNARLAKE) > > #define IS_HSW_ULT(dev_priv) (dev_priv && 0) > #define IS_BDW_ULT(dev_priv) (dev_priv && 0) > -- > 2.40.1 > -- Matt Roper Graphics Software Engineer Linux GPU Platform Enablement Intel Corporation
Re: [Intel-gfx] [PATCH v5] drm/i915: Avoid circular locking dependency when flush delayed work on gt reset
On 8/23/2023 09:00, Daniel Vetter wrote:
On Tue, Aug 22, 2023 at 11:53:24AM -0700, John Harrison wrote:
On 8/11/2023 11:20, Zhanjun Dong wrote:
This attempts to avoid circular locking dependency between flush delayed
work and intel_gt_reset.
When intel_gt_reset was called, task will hold a lock.
To cacel delayed work here, the _sync version will also acquire a lock,
which might trigger the possible cirular locking dependency warning.
When intel_gt_reset called, reset_in_progress flag will be set, add code
to check the flag, call async verion if reset is in progress.
Signed-off-by: Zhanjun Dong
Cc: John Harrison
Cc: Andi Shyti
Cc: Daniel Vetter
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index a0e3ef1c65d2..600388c849f7 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1359,7 +1359,16 @@ static void guc_enable_busyness_worker(struct intel_guc
*guc)
static void guc_cancel_busyness_worker(struct intel_guc *guc)
{
- cancel_delayed_work_sync(>timestamp.work);
+ /*
+* When intel_gt_reset was called, task will hold a lock.
+* To cacel delayed work here, the _sync version will also acquire a
lock, which might
+* trigger the possible cirular locking dependency warning.
+* Check the reset_in_progress flag, call async verion if reset is in
progress.
+*/
This needs to explain in much more detail what is going on and why it is not
a problem. E.g.:
The busyness worker needs to be cancelled. In general that means
using the synchronous cancel version to ensure that an in-progress
worker will not keep executing beyond whatever is happening that
needs the cancel. E.g. suspend, driver unload, etc. However, in the
case of a reset, the synchronous version is not required and can
trigger a false deadlock detection warning.
The business worker takes the reset mutex to protect against resets
interfering with it. However, it does a trylock and bails out if the
reset lock is already acquired. Thus there is no actual deadlock or
other concern with the worker running concurrently with a reset. So
an asynchronous cancel is safe in the case of a reset rather than a
driver unload or suspend type operation. On the other hand, if the
cancel_sync version is used when a reset is in progress then the
mutex deadlock detection sees the mutex being acquired through
multiple paths and complains.
So just don't bother. That keeps the detection code happy and is
safe because of the trylock code described above.
So why do we even need to cancel anything if it doesn't do anything while
the reset is in progress?
It still needs to be cancelled. The worker only aborts if it is actively
executing concurrently with the reset. It might not start to execute
until after the reset has completed. And there is presumably a reason
why the cancel is being called, a reason not necessarily related to
resets at all. Leaving the worker to run arbitrarily after the driver is
expecting it to be stopped will lead to much worse things than a fake
lockdep splat, e.g. a use after free pointer deref.
John.
Just remove the cancel from the reset path as uneeded instead, and explain
why that's ok? Because that's defacto what the cancel_work with a
potential deadlock scenario for cancel_work_sync does, you either don't
need it at all, or the replacement creates a bug.
-Daniel
John.
+ if (guc_to_gt(guc)->uc.reset_in_progress)
+ cancel_delayed_work(>timestamp.work);
+ else
+ cancel_delayed_work_sync(>timestamp.work);
}
static void __reset_guc_busyness_stats(struct intel_guc *guc)
[Intel-gfx] ✗ Fi.CI.BUILD: failure for Enable Lunar Lake display
== Series Details == Series: Enable Lunar Lake display URL : https://patchwork.freedesktop.org/series/122799/ State : failure == Summary == Error: patch https://patchwork.freedesktop.org/api/1.0/series/122799/revisions/1/mbox/ not applied Applying: drm/i915: Start using plane scale factor for relative data rate error: sha1 information is lacking or useless (drivers/gpu/drm/i915/display/intel_atomic_plane.c). error: could not build fake ancestor hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0001 drm/i915: Start using plane scale factor for relative data rate When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". Build failed, no error log produced
[Intel-gfx] ✗ Fi.CI.IGT: failure for HDCP MST aux issue fix (rev3)
== Series Details == Series: HDCP MST aux issue fix (rev3) URL : https://patchwork.freedesktop.org/series/122267/ State : failure == Summary == CI Bug Log - changes from CI_DRM_13549_full -> Patchwork_122267v3_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_122267v3_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_122267v3_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (9 -> 9) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_122267v3_full: ### IGT changes ### Possible regressions * igt@syncobj_timeline@invalid-wait-illegal-handle: - shard-mtlp: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13549/shard-mtlp-4/igt@syncobj_timel...@invalid-wait-illegal-handle.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122267v3/shard-mtlp-7/igt@syncobj_timel...@invalid-wait-illegal-handle.html Known issues Here are the changes found in Patchwork_122267v3_full that come from known issues: ### IGT changes ### Issues hit * igt@api_intel_bb@blit-reloc-keep-cache: - shard-dg2: NOTRUN -> [SKIP][3] ([i915#8411]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122267v3/shard-dg2-6/igt@api_intel...@blit-reloc-keep-cache.html * igt@api_intel_bb@blit-reloc-purge-cache: - shard-mtlp: NOTRUN -> [SKIP][4] ([i915#8411]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122267v3/shard-mtlp-7/igt@api_intel...@blit-reloc-purge-cache.html * igt@api_intel_bb@object-noreloc-keep-cache-simple: - shard-snb: NOTRUN -> [SKIP][5] ([fdo#109271]) +97 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122267v3/shard-snb2/igt@api_intel...@object-noreloc-keep-cache-simple.html * igt@drm_fdinfo@all-busy-idle-check-all: - shard-dg2: NOTRUN -> [SKIP][6] ([i915#8414]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122267v3/shard-dg2-6/igt@drm_fdi...@all-busy-idle-check-all.html * igt@feature_discovery@display-3x: - shard-dg2: NOTRUN -> [SKIP][7] ([i915#1839]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122267v3/shard-dg2-6/igt@feature_discov...@display-3x.html * igt@feature_discovery@display-4x: - shard-mtlp: NOTRUN -> [SKIP][8] ([i915#1839]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122267v3/shard-mtlp-7/igt@feature_discov...@display-4x.html * igt@gem_ccs@block-multicopy-inplace: - shard-mtlp: NOTRUN -> [SKIP][9] ([i915#5325]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122267v3/shard-mtlp-7/igt@gem_...@block-multicopy-inplace.html * igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-smem-lmem0: - shard-dg2: [PASS][10] -> [INCOMPLETE][11] ([i915#6311] / [i915#7297]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13549/shard-dg2-11/igt@gem_ccs@suspend-res...@linear-compressed-compfmt0-smem-lmem0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122267v3/shard-dg2-3/igt@gem_ccs@suspend-res...@linear-compressed-compfmt0-smem-lmem0.html * igt@gem_ctx_persistence@legacy-engines-cleanup: - shard-snb: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#1099]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122267v3/shard-snb2/igt@gem_ctx_persiste...@legacy-engines-cleanup.html * igt@gem_ctx_sseu@invalid-args: - shard-dg2: NOTRUN -> [SKIP][13] ([i915#280]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122267v3/shard-dg2-3/igt@gem_ctx_s...@invalid-args.html * igt@gem_eio@reset-stress: - shard-dg1: [PASS][14] -> [FAIL][15] ([i915#5784]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13549/shard-dg1-17/igt@gem_...@reset-stress.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122267v3/shard-dg1-17/igt@gem_...@reset-stress.html * igt@gem_exec_balancer@noheartbeat: - shard-mtlp: NOTRUN -> [SKIP][16] ([i915#8555]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122267v3/shard-mtlp-7/igt@gem_exec_balan...@noheartbeat.html * igt@gem_exec_fair@basic-none@bcs0: - shard-rkl: [PASS][17] -> [FAIL][18] ([i915#2842]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13549/shard-rkl-4/igt@gem_exec_fair@basic-n...@bcs0.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122267v3/shard-rkl-7/igt@gem_exec_fair@basic-n...@bcs0.html * igt@gem_exec_fair@basic-pace: - shard-mtlp: NOTRUN ->
[Intel-gfx] [PATCH 28/42] drm/i915/xe2lpd: enable odd size and panning for planar yuv on xe2lpd
From: Juha-Pekka Heikkilä
Enable odd size and panning for planar yuv formats.
Cc: Suraj Kandpal
Signed-off-by: Juha-Pekka Heikkilä
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_atomic_plane.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index fb13f0bb8c52..da6ee7f0675a 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -986,6 +986,14 @@ int intel_plane_check_src_coordinates(struct
intel_plane_state *plane_state)
if (fb->format->format == DRM_FORMAT_RGB565 && rotated) {
hsub = 2;
vsub = 2;
+ } else if (DISPLAY_VER(i915) >= 20 &&
+ intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) {
+ /*
+* This allow NV12 and P0xx formats to have odd size and/or odd
+* source coordinates on DISPLAY_VER(i915) >= 20
+*/
+ hsub = 1;
+ vsub = 1;
} else {
hsub = fb->format->hsub;
vsub = fb->format->vsub;
--
2.40.1
[Intel-gfx] [PATCH 35/42] drm/i915/lnl: Introduce MDCLK_CDCLK ratio to DBuf
From: Stanislav Lisovskiy
When we change MDCLK/CDCLK the BSpec now instructs us to write a ratio
between MDCLK/CDCLK to MBUS CTL and DBUF CTL registers during that
change.
Previsouly DBuf state and CDCLK were not anyhow coupled together. Now
at compute stage when we know which CDCLK/MDCLK we are going to use, we
need to update the DBuf state with that ratio, being properly encoded,
so that it gets written to those registers, once DBuf state is being
update. The criteria for updating DBuf state is also a CDCLK/MDCLK ratio
change now.
Cc: Mika Kahola
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_cdclk.c| 16 +
drivers/gpu/drm/i915/display/skl_watermark.c | 35 ---
drivers/gpu/drm/i915/display/skl_watermark.h | 1 +
.../gpu/drm/i915/display/skl_watermark_regs.h | 2 ++
4 files changed, 50 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 04937aaabcee..aa1000db3cb9 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -37,6 +37,7 @@
#include "intel_pci_config.h"
#include "intel_pcode.h"
#include "intel_psr.h"
+#include "skl_watermark.h"
#include "vlv_sideband.h"
/**
@@ -1827,6 +1828,15 @@ static bool cdclk_pll_is_unknown(unsigned int vco)
return vco == ~0;
}
+static int get_mdclk_cdclk_ratio(struct drm_i915_private *i915,
+const struct intel_cdclk_config *cdclk_config)
+{
+ if (DISPLAY_VER(i915) >= 20)
+ return cdclk_config->mdclk / cdclk_config->cdclk - 1;
+ else
+ return 1;
+}
+
static int cdclk_squash_divider(u16 waveform)
{
return hweight16(waveform ?: 0x);
@@ -2727,6 +2737,7 @@ static int intel_compute_min_cdclk(struct
intel_cdclk_state *cdclk_state)
struct intel_crtc_state *crtc_state;
int min_cdclk, i;
enum pipe pipe;
+ struct intel_dbuf_state *dbuf_state;
for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
int ret;
@@ -2760,6 +2771,11 @@ static int intel_compute_min_cdclk(struct
intel_cdclk_state *cdclk_state)
}
}
+ dbuf_state = intel_atomic_get_new_dbuf_state(state);
+ if (dbuf_state)
+ dbuf_state->mdclk_cdclk_ratio =
+ get_mdclk_cdclk_ratio(dev_priv, _state->actual);
+
min_cdclk = max(cdclk_state->force_min_cdclk,
cdclk_state->bw_min_cdclk);
for_each_pipe(dev_priv, pipe)
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
b/drivers/gpu/drm/i915/display/skl_watermark.c
index 64a122d3c9c0..79454b4d99e3 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -3472,6 +3472,23 @@ int intel_dbuf_init(struct drm_i915_private *i915)
return 0;
}
+static int get_mbus_mdclk_cdclk_ratio(struct drm_i915_private *i915,
+ int mdclk_cdclk_ratio,
+ int mbus_joined)
+{
+ if (DISPLAY_VER(i915) >= 20) {
+ if (mbus_joined)
+ return (mdclk_cdclk_ratio << 1) + 1;
+ else
+ return mdclk_cdclk_ratio;
+ }
+
+ if (mbus_joined)
+ return 3;
+
+ return 1;
+}
+
/*
* Configure MBUS_CTL and all DBUF_CTL_S of each slice to join_mbus state
before
* update the request state of all DBUS slices.
@@ -3483,10 +3500,16 @@ static void update_mbus_pre_enable(struct
intel_atomic_state *state)
enum dbuf_slice slice;
const struct intel_dbuf_state *dbuf_state =
intel_atomic_get_new_dbuf_state(state);
+ int tracker_state_service;
if (!HAS_MBUS_JOINING(i915))
return;
+ tracker_state_service =
+ get_mbus_mdclk_cdclk_ratio(i915,
+ dbuf_state->mdclk_cdclk_ratio,
+ dbuf_state->joined_mbus);
+
/*
* TODO: Implement vblank synchronized MBUS joining changes.
* Must be properly coordinated with dbuf reprogramming.
@@ -3494,13 +3517,15 @@ static void update_mbus_pre_enable(struct
intel_atomic_state *state)
if (dbuf_state->joined_mbus) {
mbus_ctl = MBUS_HASHING_MODE_1x4 | MBUS_JOIN |
MBUS_JOIN_PIPE_SELECT_NONE;
- dbuf_min_tracker_val = DBUF_MIN_TRACKER_STATE_SERVICE(3);
} else {
mbus_ctl = MBUS_HASHING_MODE_2x2 |
MBUS_JOIN_PIPE_SELECT_NONE;
- dbuf_min_tracker_val = DBUF_MIN_TRACKER_STATE_SERVICE(1);
}
+ dbuf_min_tracker_val =
DBUF_MIN_TRACKER_STATE_SERVICE(tracker_state_service);
+
+ mbus_ctl |=
[Intel-gfx] [PATCH 34/42] drm/i915/lnl: Start using CDCLK through PLL
From: Stanislav Lisovskiy
Introduce correspondent definitions and for choosing between CD2X CDCLK
and PLL CDCLK as a source.
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 14 --
drivers/gpu/drm/i915/i915_reg.h| 3 +++
2 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index ed45a2cf5c9a..04937aaabcee 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1932,8 +1932,7 @@ static void _bxt_set_cdclk(struct drm_i915_private
*dev_priv,
dg2_cdclk_squash_program(dev_priv, waveform);
val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |
- bxt_cdclk_cd2x_pipe(dev_priv, pipe) |
- skl_cdclk_decimal(cdclk);
+ bxt_cdclk_cd2x_pipe(dev_priv, pipe);
/*
* Disable SSA Precharge when CD clock frequency < 500 MHz,
@@ -1942,6 +1941,17 @@ static void _bxt_set_cdclk(struct drm_i915_private
*dev_priv,
if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
cdclk >= 50)
val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
+
+ if (DISPLAY_VER(dev_priv) >= 20)
+ /*
+* Using CDCLK through PLL seems to be always better option when
+* its supported, both in terms of performance and power
+* consumption.
+*/
+ val |= CDCLK_SOURCE_SEL_CDCLK_PLL;
+ else
+ val |= skl_cdclk_decimal(cdclk);
+
intel_de_write(dev_priv, CDCLK_CTL, val);
if (pipe != INVALID_PIPE)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fa85530afac3..d5850761a75a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5933,6 +5933,9 @@ enum skl_power_gate {
#define CDCLK_FREQ_540REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 1)
#define CDCLK_FREQ_337_308REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 2)
#define CDCLK_FREQ_675_617REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 3)
+#define CDCLK_SOURCE_SEL_MASK REG_BIT(25)
+#define CDCLK_SOURCE_SEL_CD2X REG_FIELD_PREP(CDCLK_SOURCE_SEL_MASK, 0)
+#define CDCLK_SOURCE_SEL_CDCLK_PLLREG_FIELD_PREP(CDCLK_SOURCE_SEL_MASK, 1)
#define BXT_CDCLK_CD2X_DIV_SEL_MASK REG_GENMASK(23, 22)
#define BXT_CDCLK_CD2X_DIV_SEL_1
REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 0)
#define BXT_CDCLK_CD2X_DIV_SEL_1_5
REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 1)
--
2.40.1
[Intel-gfx] [PATCH 25/42] drm/i915/xe2lpd: Add support for DP aux channels
From: Gustavo Sousa
The location of aux channels registers for Xe2 display changed w.r.t.
the previous version.
BSpec: 69010
Signed-off-by: Gustavo Sousa
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dp_aux.c | 43 -
1 file changed, 42 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c
b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index 3fcf609a1444..1ab6964ee1c2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -714,6 +714,44 @@ static i915_reg_t xelpdp_aux_data_reg(struct intel_dp
*intel_dp, int index)
}
}
+static i915_reg_t xe2lpd_aux_ctl_reg(struct intel_dp *intel_dp)
+{
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ enum aux_ch aux_ch = dig_port->aux_ch;
+
+ switch (aux_ch) {
+ case AUX_CH_A:
+ case AUX_CH_B:
+ case AUX_CH_USBC1:
+ case AUX_CH_USBC2:
+ case AUX_CH_USBC3:
+ case AUX_CH_USBC4:
+ return XE2LPD_DP_AUX_CH_CTL(aux_ch);
+ default:
+ MISSING_CASE(aux_ch);
+ return XE2LPD_DP_AUX_CH_CTL(AUX_CH_A);
+ }
+}
+
+static i915_reg_t xe2lpd_aux_data_reg(struct intel_dp *intel_dp, int index)
+{
+ struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+ enum aux_ch aux_ch = dig_port->aux_ch;
+
+ switch (aux_ch) {
+ case AUX_CH_A:
+ case AUX_CH_B:
+ case AUX_CH_USBC1:
+ case AUX_CH_USBC2:
+ case AUX_CH_USBC3:
+ case AUX_CH_USBC4:
+ return XE2LPD_DP_AUX_CH_DATA(aux_ch, index);
+ default:
+ MISSING_CASE(aux_ch);
+ return XE2LPD_DP_AUX_CH_DATA(AUX_CH_A, index);
+ }
+}
+
void intel_dp_aux_fini(struct intel_dp *intel_dp)
{
if (cpu_latency_qos_request_active(_dp->pm_qos))
@@ -731,7 +769,10 @@ void intel_dp_aux_init(struct intel_dp *intel_dp)
struct intel_encoder *encoder = _port->base;
enum aux_ch aux_ch = dig_port->aux_ch;
- if (DISPLAY_VER(dev_priv) >= 14) {
+ if (DISPLAY_VER(dev_priv) >= 20) {
+ intel_dp->aux_ch_ctl_reg = xe2lpd_aux_ctl_reg;
+ intel_dp->aux_ch_data_reg = xe2lpd_aux_data_reg;
+ } else if (DISPLAY_VER(dev_priv) >= 14) {
intel_dp->aux_ch_ctl_reg = xelpdp_aux_ctl_reg;
intel_dp->aux_ch_data_reg = xelpdp_aux_data_reg;
} else if (DISPLAY_VER(dev_priv) >= 12) {
--
2.40.1
[Intel-gfx] [PATCH 38/42] drm/i915/lnl: Serialize global state if mdclk/cdclk ratio changes.
From: Stanislav Lisovskiy
mdclk_cdclk_ratio is a part of dbuf_state and if it changes, it requires
hw to be poked, so we must serialize the global state in that case.
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 19 +++
1 file changed, 15 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 4d8b960389ec..38a9c47e4ae1 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2789,7 +2789,8 @@ static int intel_compute_min_cdclk(struct
intel_cdclk_state *cdclk_state)
struct intel_crtc_state *crtc_state;
int min_cdclk, i;
enum pipe pipe;
- struct intel_dbuf_state *dbuf_state;
+ struct intel_dbuf_state *new_dbuf_state;
+ struct intel_dbuf_state *old_dbuf_state;
for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
int ret;
@@ -2823,11 +2824,21 @@ static int intel_compute_min_cdclk(struct
intel_cdclk_state *cdclk_state)
}
}
- dbuf_state = intel_atomic_get_new_dbuf_state(state);
- if (dbuf_state)
- dbuf_state->mdclk_cdclk_ratio =
+ new_dbuf_state = intel_atomic_get_new_dbuf_state(state);
+ old_dbuf_state = intel_atomic_get_old_dbuf_state(state);
+ if (new_dbuf_state && old_dbuf_state) {
+ new_dbuf_state->mdclk_cdclk_ratio =
get_mdclk_cdclk_ratio(dev_priv, _state->actual);
+ if (new_dbuf_state->mdclk_cdclk_ratio !=
old_dbuf_state->mdclk_cdclk_ratio) {
+ int ret;
+
+ ret =
intel_atomic_serialize_global_state(_dbuf_state->base);
+ if (ret)
+ return ret;
+ }
+ }
+
min_cdclk = max(cdclk_state->force_min_cdclk,
cdclk_state->bw_min_cdclk);
for_each_pipe(dev_priv, pipe)
--
2.40.1
[Intel-gfx] [PATCH 18/42] drm/i915/xe2lpd: Move registers to PICA
Some registers for DDI A/B moved to PICA and now follow the same format
as the ones for the PORT_TC ports. The wrapper here deals with 2 issues:
- Share the implementation between xe2lpd and previous
platforms: there are minor layout changes, it's mostly the
register location that changed
- Handle offsets after TC ports
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 81 ++-
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 71 ++--
drivers/gpu/drm/i915/display/intel_ddi.c | 18 +++--
3 files changed, 117 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index a5918bf30c31..6533ec417806 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -98,7 +98,7 @@ static void intel_cx0_phy_transaction_end(struct
intel_encoder *encoder, intel_w
static void intel_clear_response_ready_flag(struct drm_i915_private *i915,
enum port port, int lane)
{
- intel_de_rmw(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane),
+ intel_de_rmw(i915, xelpdp_port_p2m_msgbus_status_reg(i915, port, lane),
0, XELPDP_PORT_P2M_RESPONSE_READY |
XELPDP_PORT_P2M_ERROR_SET);
}
@@ -106,10 +106,10 @@ static void intel_cx0_bus_reset(struct drm_i915_private
*i915, enum port port, i
{
enum phy phy = intel_port_to_phy(i915, port);
- intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
+ intel_de_write(i915, xelpdp_port_m2p_msgbus_ctl_reg(i915, port, lane),
XELPDP_PORT_M2P_TRANSACTION_RESET);
- if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port,
lane),
+ if (intel_de_wait_for_clear(i915, xelpdp_port_m2p_msgbus_ctl_reg(i915,
port, lane),
XELPDP_PORT_M2P_TRANSACTION_RESET,
XELPDP_MSGBUS_TIMEOUT_SLOW)) {
drm_err_once(>drm, "Failed to bring PHY %c to idle.\n",
phy_name(phy));
@@ -125,7 +125,7 @@ static int intel_cx0_wait_for_ack(struct drm_i915_private
*i915, enum port port,
enum phy phy = intel_port_to_phy(i915, port);
if (__intel_de_wait_for_register(i915,
-XELPDP_PORT_P2M_MSGBUS_STATUS(port,
lane),
+
xelpdp_port_p2m_msgbus_status_reg(i915, port, lane),
XELPDP_PORT_P2M_RESPONSE_READY,
XELPDP_PORT_P2M_RESPONSE_READY,
XELPDP_MSGBUS_TIMEOUT_FAST_US,
@@ -160,7 +160,7 @@ static int __intel_cx0_read_once(struct drm_i915_private
*i915, enum port port,
int ack;
u32 val;
- if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port,
lane),
+ if (intel_de_wait_for_clear(i915, xelpdp_port_m2p_msgbus_ctl_reg(i915,
port, lane),
XELPDP_PORT_M2P_TRANSACTION_PENDING,
XELPDP_MSGBUS_TIMEOUT_SLOW)) {
drm_dbg_kms(>drm,
@@ -169,7 +169,7 @@ static int __intel_cx0_read_once(struct drm_i915_private
*i915, enum port port,
return -ETIMEDOUT;
}
- intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
+ intel_de_write(i915, xelpdp_port_m2p_msgbus_ctl_reg(i915, port, lane),
XELPDP_PORT_M2P_TRANSACTION_PENDING |
XELPDP_PORT_M2P_COMMAND_READ |
XELPDP_PORT_M2P_ADDRESS(addr));
@@ -220,7 +220,7 @@ static int __intel_cx0_write_once(struct drm_i915_private
*i915, enum port port,
int ack;
u32 val;
- if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port,
lane),
+ if (intel_de_wait_for_clear(i915, xelpdp_port_m2p_msgbus_ctl_reg(i915,
port, lane),
XELPDP_PORT_M2P_TRANSACTION_PENDING,
XELPDP_MSGBUS_TIMEOUT_SLOW)) {
drm_dbg_kms(>drm,
@@ -229,14 +229,14 @@ static int __intel_cx0_write_once(struct drm_i915_private
*i915, enum port port,
return -ETIMEDOUT;
}
- intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
+ intel_de_write(i915, xelpdp_port_m2p_msgbus_ctl_reg(i915, port, lane),
XELPDP_PORT_M2P_TRANSACTION_PENDING |
(committed ? XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED :
XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED) |
XELPDP_PORT_M2P_DATA(data) |
XELPDP_PORT_M2P_ADDRESS(addr));
- if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port,
lane),
+ if (intel_de_wait_for_clear(i915, xelpdp_port_m2p_msgbus_ctl_reg(i915,
[Intel-gfx] [PATCH 41/42] drm/i915/xe2lpd: Update mbus on post plane updates
From: Stanislav Lisovskiy
According to BSpec we need to write the MBUS CTL and DBUF CTL both for
increasing CDCLK case (pre plane) and for decreasing CDCLK case (post
plane). Make sure those updates are in place for Xe2-LPD.
Since the mbus update is not only on pre-enable anymore, also rename the
function accordingly.
Cc: Mika Kahola
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/skl_watermark.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
b/drivers/gpu/drm/i915/display/skl_watermark.c
index 79454b4d99e3..77a4c85538c2 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -3493,7 +3493,7 @@ static int get_mbus_mdclk_cdclk_ratio(struct
drm_i915_private *i915,
* Configure MBUS_CTL and all DBUF_CTL_S of each slice to join_mbus state
before
* update the request state of all DBUS slices.
*/
-static void update_mbus_pre_enable(struct intel_atomic_state *state)
+static void update_mbus(struct intel_atomic_state *state)
{
struct drm_i915_private *i915 = to_i915(state->base.dev);
u32 mbus_ctl, dbuf_min_tracker_val;
@@ -3552,7 +3552,7 @@ void intel_dbuf_pre_plane_update(struct
intel_atomic_state *state)
WARN_ON(!new_dbuf_state->base.changed);
- update_mbus_pre_enable(state);
+ update_mbus(state);
gen9_dbuf_slices_update(i915,
old_dbuf_state->enabled_slices |
new_dbuf_state->enabled_slices);
@@ -3574,6 +3574,9 @@ void intel_dbuf_post_plane_update(struct
intel_atomic_state *state)
WARN_ON(!new_dbuf_state->base.changed);
+ if (DISPLAY_VER(i915) >= 20)
+ update_mbus(state);
+
gen9_dbuf_slices_update(i915,
new_dbuf_state->enabled_slices);
}
--
2.40.1
[Intel-gfx] [PATCH 39/42] drm/i915/lnl: Add pll table for LNL platform
From: Ravi Kumar Vodapalli
Add PLL Table for Lunar Lake platform.
BSpec: 68862
Cc: Clint Taylor
Cc: Anusha Srivatsa
Signed-off-by: Ravi Kumar Vodapalli
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 411 ++-
1 file changed, 406 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 6533ec417806..c8da6985c179 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -697,6 +697,261 @@ static const struct intel_c10pll_state * const
mtl_c10_edp_tables[] = {
NULL,
};
+static const struct intel_c10pll_state lnl_c10_dp_rbr = {
+ .clock = 162000,
+ .tx = 0x10,
+ .cmn = 0x21,
+ .pll[0] = 0xB4,
+ .pll[1] = 0,
+ .pll[2] = 0x30,
+ .pll[3] = 0x1,
+ .pll[4] = 0x26,
+ .pll[5] = 0xC0,
+ .pll[6] = 0x98,
+ .pll[7] = 0x46,
+ .pll[8] = 0x1,
+ .pll[9] = 0x1,
+ .pll[10] = 0,
+ .pll[11] = 0,
+ .pll[12] = 0xC0,
+ .pll[13] = 0,
+ .pll[14] = 0,
+ .pll[15] = 0x2,
+ .pll[16] = 0x84,
+ .pll[17] = 0x4F,
+ .pll[18] = 0xE5,
+ .pll[19] = 0x23,
+};
+
+static const struct intel_c10pll_state lnl_c10_dp_hbr1 = {
+ .clock = 27,
+ .tx = 0x10,
+ .cmn = 0x21,
+ .pll[0] = 0xF4,
+ .pll[1] = 0,
+ .pll[2] = 0xF8,
+ .pll[3] = 0x0,
+ .pll[4] = 0x20,
+ .pll[5] = 0xA0,
+ .pll[6] = 0x29,
+ .pll[7] = 0x10,
+ .pll[8] = 0x1, /* Verify */
+ .pll[9] = 0x1,
+ .pll[10] = 0,
+ .pll[11] = 0,
+ .pll[12] = 0xA0,
+ .pll[13] = 0,
+ .pll[14] = 0,
+ .pll[15] = 0x1,
+ .pll[16] = 0x84,
+ .pll[17] = 0x4F,
+ .pll[18] = 0xE5,
+ .pll[19] = 0x23,
+};
+
+static const struct intel_c10pll_state lnl_c10_dp_hbr2 = {
+ .clock = 54,
+ .tx = 0x10,
+ .cmn = 0x21,
+ .pll[0] = 0xF4,
+ .pll[1] = 0,
+ .pll[2] = 0xF8,
+ .pll[3] = 0,
+ .pll[4] = 0x20,
+ .pll[5] = 0xA0,
+ .pll[6] = 0x29,
+ .pll[7] = 0x10,
+ .pll[8] = 0x1,
+ .pll[9] = 0x1,
+ .pll[10] = 0,
+ .pll[11] = 0,
+ .pll[12] = 0xA0,
+ .pll[13] = 0,
+ .pll[14] = 0,
+ .pll[15] = 0,
+ .pll[16] = 0x84,
+ .pll[17] = 0x4F,
+ .pll[18] = 0xE5,
+ .pll[19] = 0x23,
+};
+
+static const struct intel_c10pll_state lnl_c10_dp_hbr3 = {
+ .clock = 81,
+ .tx = 0x10,
+ .cmn = 0x21,
+ .pll[0] = 0x34,
+ .pll[1] = 0,
+ .pll[2] = 0x84,
+ .pll[3] = 0x1,
+ .pll[4] = 0x30,
+ .pll[5] = 0xF0,
+ .pll[6] = 0x3D,
+ .pll[7] = 0x98,
+ .pll[8] = 0x1,
+ .pll[9] = 0x1,
+ .pll[10] = 0,
+ .pll[11] = 0,
+ .pll[12] = 0xF0,
+ .pll[13] = 0,
+ .pll[14] = 0,
+ .pll[15] = 0,
+ .pll[16] = 0x84,
+ .pll[17] = 0x0F,
+ .pll[18] = 0xE5,
+ .pll[19] = 0x23,
+};
+
+static const struct intel_c10pll_state lnl_c10_edp_r216 = {
+ .clock = 216000,
+ .tx = 0x10,
+ .cmn = 0x21,
+ .pll[0] = 0x4,
+ .pll[1] = 0,
+ .pll[2] = 0xA2,
+ .pll[3] = 0x1,
+ .pll[4] = 0x33,
+ .pll[5] = 0x10,
+ .pll[6] = 0x75,
+ .pll[7] = 0xB3,
+ .pll[8] = 0x1,
+ .pll[9] = 0x1,
+ .pll[10] = 0,
+ .pll[11] = 0,
+ .pll[12] = 0,
+ .pll[13] = 0,
+ .pll[14] = 0,
+ .pll[15] = 0x2,
+ .pll[16] = 0x85,
+ .pll[17] = 0x20,
+ .pll[18] = 0xE6,
+ .pll[19] = 0x2F,
+};
+
+static const struct intel_c10pll_state lnl_c10_edp_r243 = {
+ .clock = 243000,
+ .tx = 0x10,
+ .cmn = 0x21,
+ .pll[0] = 0x34,
+ .pll[1] = 0,
+ .pll[2] = 0xDA,
+ .pll[3] = 0x1,
+ .pll[4] = 0x39,
+ .pll[5] = 0x12,
+ .pll[6] = 0xE3,
+ .pll[7] = 0xE9,
+ .pll[8] = 0x1,
+ .pll[9] = 0x1,
+ .pll[10] = 0,
+ .pll[11] = 0,
+ .pll[12] = 0x20,
+ .pll[13] = 0,
+ .pll[14] = 0,
+ .pll[15] = 0x2,
+ .pll[16] = 0x85,
+ .pll[17] = 0xA0,
+ .pll[18] = 0xE6,
+ .pll[19] = 0x2F,
+};
+
+static const struct intel_c10pll_state lnl_c10_edp_r324 = {
+ .clock = 324000,
+ .tx = 0x10,
+ .cmn = 0x21,
+ .pll[0] = 0xB4,
+ .pll[1] = 0,
+ .pll[2] = 0x30,
+ .pll[3] = 0x1,
+ .pll[4] = 0x26,
+ .pll[5] = 0xC0,
+ .pll[6] = 0x98,
+ .pll[7] = 0x46,
+ .pll[8] = 0x1,
+ .pll[9] = 0x1,
+ .pll[10] = 0,
+ .pll[11] = 0,
+ .pll[12] = 0xC0,
+ .pll[13] = 0,
+ .pll[14] = 0,
+ .pll[15] = 0x1,
+ .pll[16] = 0x85,
+ .pll[17] = 0x60,
+ .pll[18] = 0xE6,
+ .pll[19] = 0x2F,
+};
+
+static const struct intel_c10pll_state lnl_c10_edp_r432 = {
+ .clock = 432000,
+
[Intel-gfx] [PATCH 42/42] drm/xe/lnl: Enable the display support
From: Balasubramani Vivekanandan
Enable the display support for LUNARLAKE
Signed-off-by: Balasubramani Vivekanandan
---
drivers/gpu/drm/xe/xe_pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 7fb00ea410a6..f723e19e8ca5 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -337,6 +337,7 @@ static const struct xe_device_desc mtl_desc = {
static const struct xe_device_desc lnl_desc = {
PLATFORM(XE_LUNARLAKE),
+ .has_display = true,
.require_force_probe = true,
};
--
2.40.1
[Intel-gfx] [PATCH 19/42] drm/i915/xe2lpd: Don't try to program PLANE_AUX_DIST
From: Matt Roper Since Xe2LPD technically has FlatCCS, it doesn't have AuxCCS registers like PLANE_AUX_DIST. However we currently have HAS_FLAT_CCS hardcoded to 0 since compression isn't ready; we need to make sure this doesn't cause the display code to go back to trying to write this register. Signed-off-by: Matt Roper Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/skl_universal_plane.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 3c212d8401c8..4dfd8b627147 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -1254,7 +1254,7 @@ icl_plane_update_noarm(struct intel_plane *plane, } /* FLAT CCS doesn't need to program AUX_DIST */ - if (!HAS_FLAT_CCS(dev_priv)) + if (!HAS_FLAT_CCS(dev_priv) && DISPLAY_VER(dev_priv) < 20) intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id), skl_plane_aux_dist(plane_state, color_plane)); -- 2.40.1
[Intel-gfx] [PATCH 09/42] drm/i915/tc: move legacy code out of the main _max_lane_count() func
From: Luca Coelho
This makes the code a bit more symmetric and readable, especially when
we start adding more display version-specific alternatives.
Signed-off-by: Luca Coelho
Link: https://lore.kernel.org/r/2023072121.369227-4-luciano.coe...@intel.com
---
drivers/gpu/drm/i915/display/intel_tc.c | 32 +++--
1 file changed, 19 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
b/drivers/gpu/drm/i915/display/intel_tc.c
index de848b329f4b..43b8eeba26f8 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -311,23 +311,12 @@ static int mtl_tc_port_get_max_lane_count(struct
intel_digital_port *dig_port)
}
}
-int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
+static int intel_tc_port_get_max_lane_count(struct intel_digital_port
*dig_port)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
- struct intel_tc_port *tc = to_tc_port(dig_port);
- enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
intel_wakeref_t wakeref;
- u32 lane_mask;
-
- if (!intel_phy_is_tc(i915, phy) || tc->mode != TC_PORT_DP_ALT)
- return 4;
+ u32 lane_mask = 0;
- assert_tc_cold_blocked(tc);
-
- if (DISPLAY_VER(i915) >= 14)
- return mtl_tc_port_get_max_lane_count(dig_port);
-
- lane_mask = 0;
with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref)
lane_mask = intel_tc_port_get_lane_mask(dig_port);
@@ -348,6 +337,23 @@ int intel_tc_port_fia_max_lane_count(struct
intel_digital_port *dig_port)
}
}
+int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
+{
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct intel_tc_port *tc = to_tc_port(dig_port);
+ enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
+
+ if (!intel_phy_is_tc(i915, phy) || tc->mode != TC_PORT_DP_ALT)
+ return 4;
+
+ assert_tc_cold_blocked(tc);
+
+ if (DISPLAY_VER(i915) >= 14)
+ return mtl_tc_port_get_max_lane_count(dig_port);
+
+ return intel_tc_port_get_max_lane_count(dig_port);
+}
+
void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
int required_lanes)
{
--
2.40.1
[Intel-gfx] [PATCH 37/42] drm/i915/xe2lpd: Write DBuf after CDCLK change in post plane
From: Stanislav Lisovskiy
Previously we always updated DBuf MBUS CTL and DBUF CTL regs after
CDCLK has been changed(CDCLK_CTL), however for Xe2-LPD we can't do like
that anymore. According to BSpec, we have to first update DBuf regs and
then write CDCLK regs, when CDCLK is decreased, which we do in post
plane.
So now we do CDCLK post plane update only after DBuf regs are
written (CDCLK/MDCLK separation requires MDCLK/CDCLK ratio to be written
to DBuf regs).
Cc: Mika Kahola
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_display.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index f9eda7ad892e..de813831a5cf 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7113,7 +7113,7 @@ static void intel_atomic_commit_tail(struct
intel_atomic_state *state)
/* Now enable the clocks, plane, pipe, and connectors that we set up. */
dev_priv->display.funcs.display->commit_modeset_enables(state);
- if (state->modeset)
+ if (state->modeset && DISPLAY_VER(dev_priv) < 20)
intel_set_cdclk_post_plane_update(state);
intel_wait_for_vblank_workers(state);
@@ -7160,6 +7160,9 @@ static void intel_atomic_commit_tail(struct
intel_atomic_state *state)
intel_dbuf_post_plane_update(state);
intel_psr_post_plane_update(state);
+ if (state->modeset && DISPLAY_VER(dev_priv) >= 20)
+ intel_set_cdclk_post_plane_update(state);
+
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
intel_post_plane_update(state, crtc);
--
2.40.1
[Intel-gfx] [PATCH 40/42] drm/i915/lnl: Add support to check c10 phy link rate
From: Ravi Kumar Vodapalli
Add support to check c10 phy link rate for LNL in
intel_c10_phy_check_hdmi_link_rate() function.
BSpec: 68862
Signed-off-by: Ravi Kumar Vodapalli
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index c8da6985c179..d9c43f3b4f34 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2137,11 +2137,16 @@ static const struct intel_c20pll_state * const
mtl_c20_hdmi_tables[] = {
NULL,
};
-static int intel_c10_phy_check_hdmi_link_rate(int clock)
+static int intel_c10_phy_check_hdmi_link_rate(struct drm_i915_private *i915,
int clock)
{
- const struct intel_c10pll_state * const *tables = mtl_c10_hdmi_tables;
+ const struct intel_c10pll_state * const *tables;
int i;
+ if (DISPLAY_VER(i915) >= 20)
+ tables = lnl_c10_hdmi_tables;
+ else
+ tables = mtl_c10_hdmi_tables;
+
for (i = 0; tables[i]; i++) {
if (clock == tables[i]->clock)
return MODE_OK;
@@ -2414,7 +2419,7 @@ int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi
*hdmi, int clock)
enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
if (intel_is_c10phy(i915, phy))
- return intel_c10_phy_check_hdmi_link_rate(clock);
+ return intel_c10_phy_check_hdmi_link_rate(i915, clock);
return intel_c20_phy_check_hdmi_link_rate(clock);
}
--
2.40.1
[Intel-gfx] [PATCH 27/42] drm/i915/xe2lpd: Read pin assignment from IOM
From: Luca Coelho
Starting from display version 20, we need to read the pin assignment
from the IOM TCSS_DDI_STATUS register instead of reading it from the
FIA.
We use the pin assignment to decide the maximum lane count. So, to
support this change, add a new lnl_tc_port_get_max_lane_count() function
that reads from the TCSS_DDI_STATUS register and decides the maximum
lane count based on that.
BSpec: 69594
Cc: Mika Kahola
Signed-off-by: Luca Coelho
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_tc.c | 28 +
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
b/drivers/gpu/drm/i915/display/intel_tc.c
index 3c94bbcb5497..37b0f8529b4f 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -290,6 +290,31 @@ u32 intel_tc_port_get_pin_assignment_mask(struct
intel_digital_port *dig_port)
DP_PIN_ASSIGNMENT_SHIFT(tc->phy_fia_idx);
}
+static int lnl_tc_port_get_max_lane_count(struct intel_digital_port *dig_port)
+{
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
+ intel_wakeref_t wakeref;
+ u32 val, pin_assignment;
+
+ with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref)
+ val = intel_de_read(i915, TCSS_DDI_STATUS(tc_port));
+
+ pin_assignment =
+ REG_FIELD_GET(TCSS_DDI_STATUS_PIN_ASSIGNMENT_MASK, val);
+
+ switch (pin_assignment) {
+ default:
+ MISSING_CASE(pin_assignment);
+ fallthrough;
+ case DP_PIN_ASSIGNMENT_D:
+ return 2;
+ case DP_PIN_ASSIGNMENT_C:
+ case DP_PIN_ASSIGNMENT_E:
+ return 4;
+ }
+}
+
static int mtl_tc_port_get_max_lane_count(struct intel_digital_port *dig_port)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
@@ -348,6 +373,9 @@ int intel_tc_port_max_lane_count(struct intel_digital_port
*dig_port)
assert_tc_cold_blocked(tc);
+ if (DISPLAY_VER(i915) >= 20)
+ return lnl_tc_port_get_max_lane_count(dig_port);
+
if (DISPLAY_VER(i915) >= 14)
return mtl_tc_port_get_max_lane_count(dig_port);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e31a985b02d5..fa85530afac3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6628,6 +6628,7 @@ enum skl_power_gate {
#define TCSS_DDI_STATUS(tc)_MMIO(_PICK_EVEN(tc, \
_TCSS_DDI_STATUS_1, \
_TCSS_DDI_STATUS_2))
+#define TCSS_DDI_STATUS_PIN_ASSIGNMENT_MASK REG_GENMASK(28, 25)
#define TCSS_DDI_STATUS_READY REG_BIT(2)
#define TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT REG_BIT(1)
#define TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT REG_BIT(0)
--
2.40.1
[Intel-gfx] [PATCH 30/42] drm/i915/xe2lpd: Extend Wa_15010685871
Xe2_LPD also needs workaround 15010685871.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 4207863b7b2a..fdd8d04fe12c 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1839,9 +1839,9 @@ static bool
cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i91
static bool pll_enable_wa_needed(struct drm_i915_private *dev_priv)
{
- return ((IS_DG2(dev_priv) || IS_METEORLAKE(dev_priv)) &&
- dev_priv->display.cdclk.hw.vco > 0 &&
- HAS_CDCLK_SQUASH(dev_priv));
+ return (IS_DG2(dev_priv) || IS_METEORLAKE(dev_priv) ||
+ DISPLAY_VER(dev_priv) == 20) &&
+ dev_priv->display.cdclk.hw.vco > 0 &&
HAS_CDCLK_SQUASH(dev_priv);
}
static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
--
2.40.1
[Intel-gfx] [PATCH 16/42] drm/i915/xe2lpd: Move D2D enable/disable
Bits to enable/disable and check state for D2D moved from
XELPDP_PORT_BUF_CTL1 to DDI_BUF_CTL. Make the functions
mtl_ddi_disable_d2d() and mtl_ddi_enable_d2d generic to work with
multiple reg location and bitfield layout.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_ddi.c | 38 +---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 files changed, 30 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 61722556bb47..a9440c0ecf61 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2356,13 +2356,22 @@ mtl_ddi_enable_d2d(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum port port = encoder->port;
+ i915_reg_t reg;
+ u32 set_bits, wait_bits;
- intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port), 0,
-XELPDP_PORT_BUF_D2D_LINK_ENABLE);
+ if (DISPLAY_VER(dev_priv) >= 20) {
+ reg = DDI_BUF_CTL(port);
+ set_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
+ wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
+ } else {
+ reg = XELPDP_PORT_BUF_CTL1(port);
+ set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
+ wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
+ }
- if (wait_for_us((intel_de_read(dev_priv, XELPDP_PORT_BUF_CTL1(port)) &
-XELPDP_PORT_BUF_D2D_LINK_STATE), 100)) {
- drm_err(_priv->drm, "Timeout waiting for D2D Link enable
for PORT_BUF_CTL %c\n",
+ intel_de_rmw(dev_priv, reg, 0, set_bits);
+ if (wait_for_us(intel_de_read(dev_priv, reg) & wait_bits, 100)) {
+ drm_err(_priv->drm, "Timeout waiting for D2D Link enable
for DDI/PORT_BUF_CTL %c\n",
port_name(port));
}
}
@@ -2809,13 +2818,22 @@ mtl_ddi_disable_d2d_link(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum port port = encoder->port;
+ i915_reg_t reg;
+ u32 clr_bits, wait_bits;
- intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port),
-XELPDP_PORT_BUF_D2D_LINK_ENABLE, 0);
+ if (DISPLAY_VER(dev_priv) >= 20) {
+ reg = DDI_BUF_CTL(port);
+ clr_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
+ wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
+ } else {
+ reg = XELPDP_PORT_BUF_CTL1(port);
+ clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
+ wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
+ }
- if (wait_for_us(!(intel_de_read(dev_priv, XELPDP_PORT_BUF_CTL1(port)) &
- XELPDP_PORT_BUF_D2D_LINK_STATE), 100))
- drm_err(_priv->drm, "Timeout waiting for D2D Link disable
for PORT_BUF_CTL %c\n",
+ intel_de_rmw(dev_priv, reg, clr_bits, 0);
+ if (wait_for_us(!(intel_de_read(dev_priv, reg) & wait_bits), 100))
+ drm_err(_priv->drm, "Timeout waiting for D2D Link disable
for DDI/PORT_BUF_CTL %c\n",
port_name(port));
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index dcf64e32cd54..84c5a76065a0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5723,6 +5723,8 @@ enum skl_power_gate {
/* Known as DDI_CTL_DE in MTL+ */
#define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B)
#define DDI_BUF_CTL_ENABLE(1 << 31)
+#define XE2LPD_DDI_BUF_D2D_LINK_ENABLEREG_BIT(29)
+#define XE2LPD_DDI_BUF_D2D_LINK_STATE REG_BIT(28)
#define DDI_BUF_TRANS_SELECT(n) ((n) << 24)
#define DDI_BUF_EMP_MASK (0xf << 24)
#define DDI_BUF_PHY_LINK_RATE(r) ((r) << 20)
--
2.40.1
[Intel-gfx] [PATCH 32/42] drm/i915/lnl: Introduce MDCLK
From: Stanislav Lisovskiy
In Lunar Lake we now separate MDCLK from CDLCK, which used to be before
always 2 times CDCLK. Now we might afford lower CDCLK, while having
higher memory clock, so improving bandwidth and power consumption at the
same time. This is prep work required to enable that.
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 30 ++
drivers/gpu/drm/i915/display/intel_cdclk.h | 2 +-
2 files changed, 31 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index fdd8d04fe12c..3e566f45996d 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1223,6 +1223,7 @@ static void skl_cdclk_uninit_hw(struct drm_i915_private
*dev_priv)
struct intel_cdclk_vals {
u32 cdclk;
+ u32 mdclk;
u16 refclk;
u16 waveform;
u8 divider; /* CD2X divider * 2 */
@@ -1524,6 +1525,8 @@ static void bxt_de_pll_readout(struct drm_i915_private
*dev_priv,
static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
struct intel_cdclk_config *cdclk_config)
{
+ const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
+ int i, ratio, tbl_waveform = 0;
u32 squash_ctl = 0;
u32 divider;
int div;
@@ -1574,10 +1577,36 @@ static void bxt_get_cdclk(struct drm_i915_private
*dev_priv,
cdclk_config->cdclk = DIV_ROUND_CLOSEST(hweight16(waveform) *
cdclk_config->vco, size
* div);
+ tbl_waveform = squash_ctl & CDCLK_SQUASH_WAVEFORM_MASK;
} else {
cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div);
}
+ ratio = cdclk_config->vco / cdclk_config->ref;
+
+ for (i = 0; table[i].refclk; i++) {
+ if (table[i].refclk != cdclk_config->ref)
+ continue;
+
+ if (table[i].divider != div)
+ continue;
+
+ if (table[i].waveform != tbl_waveform)
+ continue;
+
+ if (table[i].ratio != ratio)
+ continue;
+
+ /*
+* Supported from LunarLake HW onwards, however considering that
+* besides this the whole procedure is the same, we keep this
+* for all the platforms.
+*/
+ cdclk_config->mdclk = table[i].mdclk;
+
+ break;
+ }
+
out:
/*
* Can't read this out :( Let's assume it's
@@ -2191,6 +2220,7 @@ bool intel_cdclk_needs_modeset(const struct
intel_cdclk_config *a,
const struct intel_cdclk_config *b)
{
return a->cdclk != b->cdclk ||
+ a->mdclk != b->mdclk ||
a->vco != b->vco ||
a->ref != b->ref;
}
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h
b/drivers/gpu/drm/i915/display/intel_cdclk.h
index 48fd7d39e0cd..3e7eabd4d7b6 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -16,7 +16,7 @@ struct intel_atomic_state;
struct intel_crtc_state;
struct intel_cdclk_config {
- unsigned int cdclk, vco, ref, bypass;
+ unsigned int cdclk, mdclk, vco, ref, bypass;
u8 voltage_level;
};
--
2.40.1
[Intel-gfx] [PATCH 29/42] drm/i915/xe2lpd: Add support for HPD
From: Gustavo Sousa
Hotplug setup for Xe2_LPD differs from Xe_LPD+ by the fact that the
extra programming for hotplug inversion and DDI HPD filter duration is
not necessary anymore. As mtp_hpd_irq_setup() is reasonably small,
prefer to fork it into a new function for Xe2_LPD instead of adding a
platform check.
BSpec: 68970
Signed-off-by: Gustavo Sousa
Signed-off-by: Lucas De Marchi
---
.../gpu/drm/i915/display/intel_hotplug_irq.c | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
index f76b9deb64b4..74aea0d8d9ae 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
@@ -163,7 +163,9 @@ static void intel_hpd_init_pins(struct drm_i915_private
*dev_priv)
(!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv)))
return;
- if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_LNL)
+ hpd->pch_hpd = hpd_mtp;
+ else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
hpd->pch_hpd = hpd_sde_dg1;
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTP)
hpd->pch_hpd = hpd_mtp;
@@ -1061,6 +1063,19 @@ static void mtp_hpd_irq_setup(struct drm_i915_private
*i915)
mtp_tc_hpd_detection_setup(i915);
}
+static void xe2lpd_sde_hpd_irq_setup(struct drm_i915_private *i915)
+{
+ u32 hotplug_irqs, enabled_irqs;
+
+ enabled_irqs = intel_hpd_enabled_irqs(i915,
i915->display.hotplug.pch_hpd);
+ hotplug_irqs = intel_hpd_hotplug_irqs(i915,
i915->display.hotplug.pch_hpd);
+
+ ibx_display_interrupt_update(i915, hotplug_irqs, enabled_irqs);
+
+ mtp_ddi_hpd_detection_setup(i915);
+ mtp_tc_hpd_detection_setup(i915);
+}
+
static bool is_xelpdp_pica_hpd_pin(enum hpd_pin hpd_pin)
{
return hpd_pin >= HPD_PORT_TC1 && hpd_pin <= HPD_PORT_TC4;
@@ -1120,6 +1135,8 @@ static void xelpdp_hpd_irq_setup(struct drm_i915_private
*i915)
xelpdp_pica_hpd_detection_setup(i915);
+ if (INTEL_PCH_TYPE(i915) >= PCH_LNL)
+ xe2lpd_sde_hpd_irq_setup(i915);
if (INTEL_PCH_TYPE(i915) >= PCH_MTP)
mtp_hpd_irq_setup(i915);
}
--
2.40.1
[Intel-gfx] [PATCH 17/42] drm/i915/xe2lpd: D2D Enable preserve bits in DDI_BUF_CTL
From: Clint Taylor
Display Ver 20 moved the D2D Enable bit to DDI_BUF_CTL(DDI_CTL_DE)
register. We used multiple variables for HDMI and DisplayPort copies of
this register. Consolidate the various locations to use
intel_digital_port saved_port_bits.
Cc: Anusha Srivatsa
Cc: Gustavo Sousa
Cc: Radhakrishna Sripada
Signed-off-by: Clint Taylor
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_ddi.c | 40 +---
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
2 files changed, 22 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index a9440c0ecf61..3147ed174d83 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -324,26 +324,25 @@ static void intel_ddi_init_dp_buf_reg(struct
intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
enum phy phy = intel_port_to_phy(i915, encoder->port);
/* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain()
later */
- intel_dp->DP = dig_port->saved_port_bits |
+ dig_port->saved_port_bits |=
DDI_PORT_WIDTH(crtc_state->lane_count) |
DDI_BUF_TRANS_SELECT(0);
if (DISPLAY_VER(i915) >= 14) {
if (intel_dp_is_uhbr(crtc_state))
- intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT;
+ dig_port->saved_port_bits |= DDI_BUF_PORT_DATA_40BIT;
else
- intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT;
+ dig_port->saved_port_bits |= DDI_BUF_PORT_DATA_10BIT;
}
if (IS_ALDERLAKE_P(i915) && intel_phy_is_tc(i915, phy)) {
- intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock);
+ dig_port->saved_port_bits |=
ddi_buf_phy_link_rate(crtc_state->port_clock);
if (!intel_tc_port_in_tbt_alt_mode(dig_port))
- intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
+ dig_port->saved_port_bits |=
DDI_BUF_CTL_TC_PHY_OWNERSHIP;
}
}
@@ -1449,7 +1448,7 @@ hsw_set_signal_levels(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+ struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
int level = intel_ddi_level(encoder, crtc_state, 0);
enum port port = encoder->port;
u32 signal_levels;
@@ -1466,10 +1465,10 @@ hsw_set_signal_levels(struct intel_encoder *encoder,
drm_dbg_kms(_priv->drm, "Using signal levels %08x\n",
signal_levels);
- intel_dp->DP &= ~DDI_BUF_EMP_MASK;
- intel_dp->DP |= signal_levels;
+ dig_port->saved_port_bits &= ~DDI_BUF_EMP_MASK;
+ dig_port->saved_port_bits |= signal_levels;
- intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
+ intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
}
@@ -2355,6 +2354,7 @@ static void
mtl_ddi_enable_d2d(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
enum port port = encoder->port;
i915_reg_t reg;
u32 set_bits, wait_bits;
@@ -2362,6 +2362,7 @@ mtl_ddi_enable_d2d(struct intel_encoder *encoder)
if (DISPLAY_VER(dev_priv) >= 20) {
reg = DDI_BUF_CTL(port);
set_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
+ dig_port->saved_port_bits |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
} else {
reg = XELPDP_PORT_BUF_CTL1(port);
@@ -2817,6 +2818,7 @@ static void
mtl_ddi_disable_d2d_link(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
enum port port = encoder->port;
i915_reg_t reg;
u32 clr_bits, wait_bits;
@@ -2824,6 +2826,7 @@ mtl_ddi_disable_d2d_link(struct intel_encoder *encoder)
if (DISPLAY_VER(dev_priv) >= 20) {
reg = DDI_BUF_CTL(port);
clr_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
+ dig_port->saved_port_bits &= ~XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
} else {
reg = XELPDP_PORT_BUF_CTL1(port);
@@ -3162,7 +3165,6 @@ static void
[Intel-gfx] [PATCH 33/42] drm/i915/lnl: Add CDCLK table
From: Stanislav Lisovskiy
Add a new Lunar Lake CDCLK table from BSpec and also a helper function
in order to be able to find lowest possible CDCLK, which has required
MDCLK for the correspodent pixel rate.
Bspec: 68861
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 52 +-
1 file changed, 50 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 3e566f45996d..ed45a2cf5c9a 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1381,6 +1381,31 @@ static const struct intel_cdclk_vals mtl_cdclk_table[] =
{
{}
};
+static const struct intel_cdclk_vals lnl_cdclk_table[] = {
+ { .refclk = 38400, .cdclk = 153600, .mdclk = 614400, .divider = 2,
.ratio = 16, .waveform = 0x },
+ { .refclk = 38400, .cdclk = 172800, .mdclk = 614400, .divider = 2,
.ratio = 16, .waveform = 0xad5a },
+ { .refclk = 38400, .cdclk = 192000, .mdclk = 614400, .divider = 2,
.ratio = 16, .waveform = 0xb6b6 },
+ { .refclk = 38400, .cdclk = 211200, .mdclk = 614400, .divider = 2,
.ratio = 16, .waveform = 0xdbb6 },
+ { .refclk = 38400, .cdclk = 230400, .mdclk = 614400, .divider = 2,
.ratio = 16, .waveform = 0x },
+ { .refclk = 38400, .cdclk = 249600, .mdclk = 614400, .divider = 2,
.ratio = 16, .waveform = 0xf7de },
+ { .refclk = 38400, .cdclk = 268800, .mdclk = 614400, .divider = 2,
.ratio = 16, .waveform = 0xfefe },
+ { .refclk = 38400, .cdclk = 288000, .mdclk = 614400, .divider = 2,
.ratio = 16, .waveform = 0xfffe },
+ { .refclk = 38400, .cdclk = 307200, .mdclk = 614400, .divider = 2,
.ratio = 16, .waveform = 0x },
+ { .refclk = 38400, .cdclk = 33, .mdclk = 96, .divider = 2,
.ratio = 25, .waveform = 0xdbb6 },
+ { .refclk = 38400, .cdclk = 36, .mdclk = 96, .divider = 2,
.ratio = 25, .waveform = 0x },
+ { .refclk = 38400, .cdclk = 39, .mdclk = 96, .divider = 2,
.ratio = 25, .waveform = 0xf7de },
+ { .refclk = 38400, .cdclk = 42, .mdclk = 96, .divider = 2,
.ratio = 25, .waveform = 0xfefe },
+ { .refclk = 38400, .cdclk = 45, .mdclk = 96, .divider = 2,
.ratio = 25, .waveform = 0xfffe },
+ { .refclk = 38400, .cdclk = 48, .mdclk = 96, .divider = 2,
.ratio = 25, .waveform = 0x },
+ { .refclk = 38400, .cdclk = 487200, .mdclk = 1113600, .divider = 2,
.ratio = 29, .waveform = 0xfefe },
+ { .refclk = 38400, .cdclk = 522000, .mdclk = 1113600, .divider = 2,
.ratio = 29, .waveform = 0xfffe },
+ { .refclk = 38400, .cdclk = 556800, .mdclk = 1113600, .divider = 2,
.ratio = 29, .waveform = 0x },
+ { .refclk = 38400, .cdclk = 571200, .mdclk = 1305600, .divider = 2,
.ratio = 34, .waveform = 0xfefe },
+ { .refclk = 38400, .cdclk = 612000, .mdclk = 1305600, .divider = 2,
.ratio = 34, .waveform = 0xfffe },
+ { .refclk = 38400, .cdclk = 652800, .mdclk = 1305600, .divider = 2,
.ratio = 34, .waveform = 0x },
+ {}
+};
+
static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
{
const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
@@ -2531,12 +2556,32 @@ intel_set_cdclk_post_plane_update(struct
intel_atomic_state *state)
}
}
+static int
+cdclk_match_by_refclk_mdclk(struct drm_i915_private *i915, int pixel_rate)
+{
+ const struct intel_cdclk_vals *table = i915->display.cdclk.table;
+ int i;
+
+ for (i = 0; table[i].refclk; i++)
+ if (table[i].refclk == i915->display.cdclk.hw.ref &&
+ table[i].mdclk >= pixel_rate)
+ return table[i].cdclk;
+
+ drm_WARN(>drm, 1,
+"Cannot satisfy pixel rate %d with refclk %u\n",
+pixel_rate, i915->display.cdclk.hw.ref);
+
+ return 0;
+}
+
static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
int pixel_rate = crtc_state->pixel_rate;
- if (DISPLAY_VER(dev_priv) >= 10)
+ if (DISPLAY_VER(dev_priv) >= 20)
+ return cdclk_match_by_refclk_mdclk(dev_priv, pixel_rate);
+ else if (DISPLAY_VER(dev_priv) >= 10)
return DIV_ROUND_UP(pixel_rate, 2);
else if (DISPLAY_VER(dev_priv) == 9 ||
IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
@@ -3581,7 +3626,10 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs =
{
*/
void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
{
- if (IS_METEORLAKE(dev_priv)) {
+ if (DISPLAY_VER(dev_priv) >= 20) {
+ dev_priv->display.funcs.cdclk = _cdclk_funcs;
+ dev_priv->display.cdclk.table = lnl_cdclk_table;
+ } else if (IS_METEORLAKE(dev_priv)) {
[Intel-gfx] [PATCH 08/42] drm/i915/tc: make intel_tc_port_get_lane_mask() static
From: Luca Coelho
This function is only used locally, so make it static and remove the
definition from the header file.
Signed-off-by: Luca Coelho
Reviewed-by: Suraj Kandpal
Link: https://lore.kernel.org/r/2023072121.369227-3-luciano.coe...@intel.com
---
drivers/gpu/drm/i915/display/intel_tc.c | 2 +-
drivers/gpu/drm/i915/display/intel_tc.h | 1 -
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
b/drivers/gpu/drm/i915/display/intel_tc.c
index 71bbc2b16a0e..de848b329f4b 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -260,7 +260,7 @@ assert_tc_port_power_enabled(struct intel_tc_port *tc)
!intel_display_power_is_enabled(i915,
tc_port_power_domain(tc)));
}
-u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
+static u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
struct intel_tc_port *tc = to_tc_port(dig_port);
diff --git a/drivers/gpu/drm/i915/display/intel_tc.h
b/drivers/gpu/drm/i915/display/intel_tc.h
index 3b16491925fa..ffc0e2a74e43 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.h
+++ b/drivers/gpu/drm/i915/display/intel_tc.h
@@ -19,7 +19,6 @@ bool intel_tc_port_in_legacy_mode(struct intel_digital_port
*dig_port);
bool intel_tc_port_connected(struct intel_encoder *encoder);
bool intel_tc_port_connected_locked(struct intel_encoder *encoder);
-u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port);
u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port);
int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port);
void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
--
2.40.1
[Intel-gfx] [PATCH 14/42] drm/i915/lnl: Add fake PCH
From: Gustavo Sousa
LNL has south display on the same SoC. As such, define a new fake PCH
entry for it.
Signed-off-by: Gustavo Sousa
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/soc/intel_pch.c | 5 -
drivers/gpu/drm/i915/soc/intel_pch.h | 2 ++
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/soc/intel_pch.c
b/drivers/gpu/drm/i915/soc/intel_pch.c
index cf795ecdcc26..5b9a01d26cab 100644
--- a/drivers/gpu/drm/i915/soc/intel_pch.c
+++ b/drivers/gpu/drm/i915/soc/intel_pch.c
@@ -220,7 +220,10 @@ void intel_detect_pch(struct drm_i915_private *dev_priv)
* South display engine on the same PCI device: just assign the fake
* PCH.
*/
- if (IS_DG2(dev_priv)) {
+ if (IS_LUNARLAKE(dev_priv)) {
+ dev_priv->pch_type = PCH_LNL;
+ return;
+ } else if (IS_DG2(dev_priv)) {
dev_priv->pch_type = PCH_DG2;
return;
} else if (IS_DG1(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/soc/intel_pch.h
b/drivers/gpu/drm/i915/soc/intel_pch.h
index 32aff5a70d04..1b03ea60a7a8 100644
--- a/drivers/gpu/drm/i915/soc/intel_pch.h
+++ b/drivers/gpu/drm/i915/soc/intel_pch.h
@@ -30,6 +30,7 @@ enum intel_pch {
/* Fake PCHs, functionality handled on the same PCI dev */
PCH_DG1 = 1024,
PCH_DG2,
+ PCH_LNL,
};
#define INTEL_PCH_DEVICE_ID_MASK 0xff80
@@ -66,6 +67,7 @@ enum intel_pch {
#define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
#define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
+#define HAS_PCH_LNL(dev_priv) (INTEL_PCH_TYPE(dev_priv) ==
PCH_LNL)
#define HAS_PCH_MTP(dev_priv) (INTEL_PCH_TYPE(dev_priv) ==
PCH_MTP)
#define HAS_PCH_DG2(dev_priv) (INTEL_PCH_TYPE(dev_priv) ==
PCH_DG2)
#define HAS_PCH_ADP(dev_priv) (INTEL_PCH_TYPE(dev_priv) ==
PCH_ADP)
--
2.40.1
[Intel-gfx] [PATCH 26/42] drm/i915/xe2lpd: Handle port AUX interrupts
From: Gustavo Sousa
Differently from previous version, Xe2_LPD groups all port AUX interrupt
bits into PICA interrupt registers.
BSpec: 68958, 69697
Signed-off-by: Gustavo Sousa
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_display_irq.c | 4 +++-
drivers/gpu/drm/i915/display/intel_hotplug_irq.c | 3 +++
drivers/gpu/drm/i915/i915_reg.h | 3 +++
3 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c
b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 62ce55475554..bff4a76310c0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -792,7 +792,9 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private
*dev_priv)
{
u32 mask;
- if (DISPLAY_VER(dev_priv) >= 14)
+ if (DISPLAY_VER(dev_priv) >= 20)
+ return 0;
+ else if (DISPLAY_VER(dev_priv) >= 14)
return TGL_DE_PORT_AUX_DDIA |
TGL_DE_PORT_AUX_DDIB;
else if (DISPLAY_VER(dev_priv) >= 13)
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
index f95fa793fabb..f76b9deb64b4 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
@@ -514,6 +514,9 @@ void xelpdp_pica_irq_handler(struct drm_i915_private *i915,
u32 iir)
u32 trigger_aux = iir & XELPDP_AUX_TC_MASK;
u32 pin_mask = 0, long_mask = 0;
+ if (DISPLAY_VER(i915) >= 20)
+ trigger_aux |= iir & XE2LPD_AUX_DDI_MASK;
+
for (pin = HPD_PORT_TC1; pin <= HPD_PORT_TC4; pin++) {
u32 val;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 84c5a76065a0..e31a985b02d5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4520,6 +4520,9 @@
#define XELPDP_AUX_TC(hpd_pin)REG_BIT(8 +
_HPD_PIN_TC(hpd_pin))
#define XELPDP_AUX_TC_MASKREG_GENMASK(11, 8)
+#define XE2LPD_AUX_DDI(hpd_pin) REG_BIT(6 +
_HPD_PIN_DDI(hpd_pin))
+#define XE2LPD_AUX_DDI_MASK REG_GENMASK(7, 6)
+
#define XELPDP_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin))
#define XELPDP_TBT_HOTPLUG_MASK REG_GENMASK(3, 0)
--
2.40.1
[Intel-gfx] [PATCH 10/42] drm/i915/tc: remove "fia" from intel_tc_port_fia_max_lane_count()
From: Luca Coelho
It is irrelevant for the caller that the max lane count is being
derived from a FIA register, so having "fia" in the function name is
irrelevant. Rename the function accordingly.
Signed-off-by: Luca Coelho
Reviewed-by: Lucas De Marchi
Link: https://lore.kernel.org/r/2023072121.369227-5-luciano.coe...@intel.com
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 2 +-
drivers/gpu/drm/i915/display/intel_dp.c | 4 ++--
drivers/gpu/drm/i915/display/intel_tc.c | 4 ++--
drivers/gpu/drm/i915/display/intel_tc.h | 2 +-
4 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 26e256165b80..a5918bf30c31 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -58,7 +58,7 @@ static u8 intel_cx0_get_owned_lane_mask(struct
drm_i915_private *i915,
* In DP-alt with pin assignment D, only PHY lane 0 is owned
* by display and lane 1 is owned by USB.
*/
- return intel_tc_port_fia_max_lane_count(dig_port) > 2
+ return intel_tc_port_max_lane_count(dig_port) > 2
? INTEL_CX0_BOTH_LANES : INTEL_CX0_LANE0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 9f40da20e88d..84584864511b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -306,13 +306,13 @@ static int intel_dp_max_common_lane_count(struct intel_dp
*intel_dp)
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
int source_max = intel_dp_max_source_lane_count(dig_port);
int sink_max = intel_dp->max_sink_lane_count;
- int fia_max = intel_tc_port_fia_max_lane_count(dig_port);
+ int port_max = intel_tc_port_max_lane_count(dig_port);
int lttpr_max =
drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);
if (lttpr_max)
sink_max = min(sink_max, lttpr_max);
- return min3(source_max, sink_max, fia_max);
+ return min3(source_max, sink_max, port_max);
}
int intel_dp_max_lane_count(struct intel_dp *intel_dp)
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
b/drivers/gpu/drm/i915/display/intel_tc.c
index 43b8eeba26f8..3c94bbcb5497 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -337,7 +337,7 @@ static int intel_tc_port_get_max_lane_count(struct
intel_digital_port *dig_port)
}
}
-int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
+int intel_tc_port_max_lane_count(struct intel_digital_port *dig_port)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
struct intel_tc_port *tc = to_tc_port(dig_port);
@@ -589,7 +589,7 @@ static bool tc_phy_verify_legacy_or_dp_alt_mode(struct
intel_tc_port *tc,
struct intel_digital_port *dig_port = tc->dig_port;
int max_lanes;
- max_lanes = intel_tc_port_fia_max_lane_count(dig_port);
+ max_lanes = intel_tc_port_max_lane_count(dig_port);
if (tc->mode == TC_PORT_LEGACY) {
drm_WARN_ON(>drm, max_lanes != 4);
return true;
diff --git a/drivers/gpu/drm/i915/display/intel_tc.h
b/drivers/gpu/drm/i915/display/intel_tc.h
index ffc0e2a74e43..80a61e52850e 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.h
+++ b/drivers/gpu/drm/i915/display/intel_tc.h
@@ -20,7 +20,7 @@ bool intel_tc_port_connected(struct intel_encoder *encoder);
bool intel_tc_port_connected_locked(struct intel_encoder *encoder);
u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port);
-int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port);
+int intel_tc_port_max_lane_count(struct intel_digital_port *dig_port);
void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
int required_lanes);
--
2.40.1
[Intel-gfx] [PATCH 36/42] drm/i915/lnl: Add support for CDCLK initialization sequence
From: Ravi Kumar Vodapalli
Add CDCLK initialization sequence changes and CDCLK set frequency
sequence for LNL platform.
CDCLK frequency change sequence is different for LNL compared to MTL
when a change in mdclk/cdclk ratio is observed. Below are changes to be
made:
1. In MBUS_CTL register translation Throttle Min value.
2. In DBUF_CTL_S* register Min Tracker State Service value.
BSpec: 68846, 68864
Signed-off-by: Ravi Kumar Vodapalli
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 58 --
drivers/gpu/drm/i915/i915_reg.h| 2 +
2 files changed, 57 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index aa1000db3cb9..4d8b960389ec 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -38,6 +38,7 @@
#include "intel_pcode.h"
#include "intel_psr.h"
#include "skl_watermark.h"
+#include "skl_watermark_regs.h"
#include "vlv_sideband.h"
/**
@@ -1727,7 +1728,12 @@ static void adlp_cdclk_pll_crawl(struct drm_i915_private
*dev_priv, int vco)
static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe
pipe)
{
- if (DISPLAY_VER(dev_priv) >= 12) {
+ if (DISPLAY_VER(dev_priv) >= 20) {
+ if (pipe == INVALID_PIPE)
+ return LNL_CDCLK_CD2X_PIPE_NONE;
+ else
+ return LNL_CDCLK_CD2X_PIPE(pipe);
+ } else if (DISPLAY_VER(dev_priv) >= 12) {
if (pipe == INVALID_PIPE)
return TGL_CDCLK_CD2X_PIPE_NONE;
else
@@ -1837,6 +1843,47 @@ static int get_mdclk_cdclk_ratio(struct drm_i915_private
*i915,
return 1;
}
+static void lnl_prog_mbus_dbuf_ctrl(struct drm_i915_private *i915,
+ const struct intel_cdclk_config
*cdclk_config)
+{
+ int min_throttle_val;
+ int min_tracker_state;
+ enum dbuf_slice slice;
+ int mdclk_cdclk_div_ratio;
+ int mbus_join = intel_de_read(i915, MBUS_CTL) & MBUS_JOIN;
+
+ mdclk_cdclk_div_ratio = get_mdclk_cdclk_ratio(i915, cdclk_config);
+
+ min_throttle_val =
MBUS_TRANS_THROTTLE_MIN_SELECT(mdclk_cdclk_div_ratio);
+
+ intel_de_rmw(i915, MBUS_CTL, MBUS_TRANS_THROTTLE_MIN_MASK,
min_throttle_val);
+
+ if (mbus_join)
+ mdclk_cdclk_div_ratio = (mdclk_cdclk_div_ratio << 1) + 1;
+
+ min_tracker_state =
DBUF_MIN_TRACKER_STATE_SERVICE(mdclk_cdclk_div_ratio);
+
+ for_each_dbuf_slice(i915, slice)
+ intel_de_rmw(i915, DBUF_CTL_S(slice),
+DBUF_MIN_TRACKER_STATE_SERVICE_MASK,
+min_tracker_state);
+}
+
+static void lnl_cdclk_squash_program(struct drm_i915_private *i915,
+const struct intel_cdclk_config
*cdclk_config,
+u16 waveform)
+{
+ if (cdclk_config->cdclk < i915->display.cdclk.hw.cdclk)
+ /* Program mbus_ctrl and dbuf_ctrl registers as Pre hook */
+ lnl_prog_mbus_dbuf_ctrl(i915, cdclk_config);
+
+ dg2_cdclk_squash_program(i915, waveform);
+
+ if (cdclk_config->cdclk > i915->display.cdclk.hw.cdclk)
+ /* Program mbus_ctrl and dbuf_ctrl registers as Post hook */
+ lnl_prog_mbus_dbuf_ctrl(i915, cdclk_config);
+}
+
static int cdclk_squash_divider(u16 waveform)
{
return hweight16(waveform ?: 0x);
@@ -1938,8 +1985,13 @@ static void _bxt_set_cdclk(struct drm_i915_private
*dev_priv,
else
clock = cdclk;
- if (HAS_CDCLK_SQUASH(dev_priv))
- dg2_cdclk_squash_program(dev_priv, waveform);
+ if (HAS_CDCLK_SQUASH(dev_priv)) {
+ if (DISPLAY_VER(dev_priv) >= 20)
+ lnl_cdclk_squash_program(dev_priv, cdclk_config,
+waveform);
+ else
+ dg2_cdclk_squash_program(dev_priv, waveform);
+ }
val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |
bxt_cdclk_cd2x_pipe(dev_priv, pipe);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d5850761a75a..c9639f0f4f49 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5944,6 +5944,8 @@ enum skl_power_gate {
#define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe) << 20)
#define CDCLK_DIVMUX_CD_OVERRIDE (1 << 19)
#define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3)
+#define LNL_CDCLK_CD2X_PIPE(pipe) ((pipe) << 19)
+#define LNL_CDCLK_CD2X_PIPE_NONE (7 << 19)
#define ICL_CDCLK_CD2X_PIPE(pipe) (_PICK(pipe, 0, 2, 6) << 19)
#define ICL_CDCLK_CD2X_PIPE_NONE (7 << 19)
#define TGL_CDCLK_CD2X_PIPE(pipe) BXT_CDCLK_CD2X_PIPE(pipe)
--
2.40.1
[Intel-gfx] [PATCH 31/42] drm/i915/lnl: Add gmbus/ddc support
LNL's south display uses the same table as MTP. Check for LNL's fake PCH
to make it consistent with the other checks.
The VBT table doesn't contain the VBT -> spec mapping for LNL. Like in
other cases, uses the same as the previous platform.
Bspec: 68971, 20124
Cc: Anusha Srivatsa
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_bios.c | 2 +-
drivers/gpu/drm/i915/display/intel_gmbus.c | 5 -
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
b/drivers/gpu/drm/i915/display/intel_bios.c
index 097c1f23d3ae..3772b91e155c 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2195,7 +2195,7 @@ static u8 map_ddc_pin(struct drm_i915_private *i915, u8
vbt_pin)
const u8 *ddc_pin_map;
int i, n_entries;
- if (HAS_PCH_MTP(i915) || IS_ALDERLAKE_P(i915)) {
+ if (HAS_PCH_MTP(i915) || IS_ALDERLAKE_P(i915) || IS_LUNARLAKE(i915)) {
ddc_pin_map = adlp_ddc_pin_map;
n_entries = ARRAY_SIZE(adlp_ddc_pin_map);
} else if (IS_ALDERLAKE_S(i915)) {
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c
b/drivers/gpu/drm/i915/display/intel_gmbus.c
index e95ddb580ef6..801fabbccf7e 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -155,7 +155,10 @@ static const struct gmbus_pin *get_gmbus_pin(struct
drm_i915_private *i915,
const struct gmbus_pin *pins;
size_t size;
- if (INTEL_PCH_TYPE(i915) >= PCH_DG2) {
+ if (INTEL_PCH_TYPE(i915) >= PCH_LNL) {
+ pins = gmbus_pins_mtp;
+ size = ARRAY_SIZE(gmbus_pins_mtp);
+ } else if (INTEL_PCH_TYPE(i915) >= PCH_DG2) {
pins = gmbus_pins_dg2;
size = ARRAY_SIZE(gmbus_pins_dg2);
} else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) {
--
2.40.1
[Intel-gfx] [PATCH 20/42] drm/i915/xe2lpd: Register DE_RRMR has been removed
From: Clint Taylor Do not read DE_RRMR register after display version 20. This register contains display state information during GFX state dumps. Bspec: 69456 Cc: Anusha Srivatsa Cc: Gustavo Sousa Signed-off-by: Clint Taylor Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/i915_gpu_error.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index 4749f99e6320..fe2fa6f966f2 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -1755,7 +1755,7 @@ static void gt_record_display_regs(struct intel_gt_coredump *gt) struct intel_uncore *uncore = gt->_gt->uncore; struct drm_i915_private *i915 = uncore->i915; - if (GRAPHICS_VER(i915) >= 6) + if (DISPLAY_VER(i915) >= 6 && DISPLAY_VER(i915) < 20) gt->derrmr = intel_uncore_read(uncore, DERRMR); if (GRAPHICS_VER(i915) >= 8) -- 2.40.1
[Intel-gfx] [PATCH 22/42] drm/i915/xe2lpd: Add DC state support
From: Matt Roper
Xe2_LPD supports DC5, DC6, and DC9 (DC3CO no longer exists). The
overall programming and requirements to enter DC states are similar to
those of Xe_LPD+ although AUX transactions do not require DC5/DC6 exit
as they did previously.
Bspec: 68851, 68857, 68886, 69115
Cc: Anusha Srivatsa
Signed-off-by: Matt Roper
Signed-off-by: Lucas De Marchi
---
.../drm/i915/display/intel_display_power.c| 4 +++-
.../i915/display/intel_display_power_map.c| 19 +++
2 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 7e2059abae9a..508a3225d9f0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -944,7 +944,9 @@ static u32 get_allowed_dc_mask(const struct
drm_i915_private *dev_priv,
if (!HAS_DISPLAY(dev_priv))
return 0;
- if (IS_DG2(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 20)
+ max_dc = 2;
+ else if (IS_DG2(dev_priv))
max_dc = 1;
else if (IS_DG1(dev_priv))
max_dc = 3;
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c
b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index cef3b313c9f5..d74a742437c3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -1570,9 +1570,28 @@ static const struct i915_power_well_desc
xe2lpd_power_wells_pica[] = {
},
};
+I915_DECL_PW_DOMAINS(xe2lpd_pwdoms_dc_off,
+ POWER_DOMAIN_DC_OFF,
+ XELPD_PW_C_POWER_DOMAINS,
+ XELPD_PW_D_POWER_DOMAINS,
+ POWER_DOMAIN_AUDIO_MMIO,
+ POWER_DOMAIN_MODESET,
+ POWER_DOMAIN_INIT);
+
+static const struct i915_power_well_desc xe2lpd_power_wells_dcoff[] = {
+ {
+ .instances = _PW_INSTANCES(
+ I915_PW("DC_off", _pwdoms_dc_off,
+ .id = SKL_DISP_DC_OFF),
+ ),
+ .ops = _dc_off_power_well_ops,
+ },
+};
+
static const struct i915_power_well_desc_list xe2lpd_power_wells[] = {
I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
+ I915_PW_DESCRIPTORS(xe2lpd_power_wells_dcoff),
I915_PW_DESCRIPTORS(xelpdp_power_wells_main),
I915_PW_DESCRIPTORS(xe2lpd_power_wells_pica),
};
--
2.40.1
[Intel-gfx] [PATCH 15/42] drm/i915/xe2lpd: Treat cursor plane as regular plane for DDB allocation
From: Stanislav Lisovskiy
We now start calculating relative plane data rate for sursor plane as
well, as instructed by BSpec and also treat cursor plane same way as
other planes, when doing allocation, i.e not using fixed allocation for
cursor anymore.
Signed-off-by: Stanislav Lisovskiy
Signed-off-by: Lucas De Marchi
---
.../gpu/drm/i915/display/intel_atomic_plane.c| 6 +++---
drivers/gpu/drm/i915/display/skl_watermark.c | 16 +---
2 files changed, 12 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index cb60165bc415..fb13f0bb8c52 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -219,9 +219,6 @@ intel_plane_relative_data_rate(const struct
intel_crtc_state *crtc_state,
int width, height;
unsigned int rel_data_rate;
- if (plane->id == PLANE_CURSOR)
- return 0;
-
if (!plane_state->uapi.visible)
return 0;
@@ -249,6 +246,9 @@ intel_plane_relative_data_rate(const struct
intel_crtc_state *crtc_state,
rel_data_rate = width * height * fb->format->cpp[color_plane];
+ if (plane->id == PLANE_CURSOR)
+ return rel_data_rate;
+
return intel_adjusted_rate(_state->uapi.src,
_state->uapi.dst,
rel_data_rate);
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
b/drivers/gpu/drm/i915/display/skl_watermark.c
index 063929a42a42..64a122d3c9c0 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -1367,7 +1367,7 @@ skl_total_relative_data_rate(const struct
intel_crtc_state *crtc_state)
u64 data_rate = 0;
for_each_plane_id_on_crtc(crtc, plane_id) {
- if (plane_id == PLANE_CURSOR)
+ if (plane_id == PLANE_CURSOR && DISPLAY_VER(i915) < 20)
continue;
data_rate += crtc_state->rel_data_rate[plane_id];
@@ -1514,10 +1514,12 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state
*state,
return 0;
/* Allocate fixed number of blocks for cursor. */
- cursor_size = skl_cursor_allocation(crtc_state, num_active);
- iter.size -= cursor_size;
- skl_ddb_entry_init(_state->wm.skl.plane_ddb[PLANE_CURSOR],
- alloc->end - cursor_size, alloc->end);
+ if (DISPLAY_VER(i915) < 20) {
+ cursor_size = skl_cursor_allocation(crtc_state, num_active);
+ iter.size -= cursor_size;
+ skl_ddb_entry_init(_state->wm.skl.plane_ddb[PLANE_CURSOR],
+ alloc->end - cursor_size, alloc->end);
+ }
iter.data_rate = skl_total_relative_data_rate(crtc_state);
@@ -1531,7 +1533,7 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state
*state,
const struct skl_plane_wm *wm =
_state->wm.skl.optimal.planes[plane_id];
- if (plane_id == PLANE_CURSOR) {
+ if (plane_id == PLANE_CURSOR && DISPLAY_VER(i915) < 20)
{
const struct skl_ddb_entry *ddb =
_state->wm.skl.plane_ddb[plane_id];
@@ -1579,7 +1581,7 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state
*state,
const struct skl_plane_wm *wm =
_state->wm.skl.optimal.planes[plane_id];
- if (plane_id == PLANE_CURSOR)
+ if (plane_id == PLANE_CURSOR && DISPLAY_VER(i915) < 20)
continue;
if (DISPLAY_VER(i915) < 11 &&
--
2.40.1
[Intel-gfx] [PATCH 21/42] drm/i915/xe2lpd: Add display power well
From: Ravi Kumar Vodapalli
Add Display Power Well for LNL platform, mostly it is same as MTL
platform so reused the code
Changes are:
1. AUX_CH_CTL and AUX_CH_DATA1 are different from MTL so added extra
logic xelpdp_aux_power_well_ops functions.
2. PGPICA1 contains type-C capable port slices which requires the well
to power powered up, so added new power well definition for PGPICA1
BSpec: 68886
Signed-off-by: Ravi Kumar Vodapalli
Signed-off-by: Gustavo Sousa
Signed-off-by: Lucas De Marchi
---
.../i915/display/intel_display_power_map.c| 36 ++-
.../i915/display/intel_display_power_well.c | 63 ++-
.../i915/display/intel_display_power_well.h | 1 +
.../gpu/drm/i915/display/intel_dp_aux_regs.h | 27
4 files changed, 123 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c
b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index 5ad04cd42c15..cef3b313c9f5 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -1545,6 +1545,38 @@ static const struct i915_power_well_desc_list
xelpdp_power_wells[] = {
I915_PW_DESCRIPTORS(xelpdp_power_wells_main),
};
+I915_DECL_PW_DOMAINS(xe2lpd_pwdoms_pica_tc,
+POWER_DOMAIN_PORT_DDI_LANES_TC1,
+POWER_DOMAIN_PORT_DDI_LANES_TC2,
+POWER_DOMAIN_PORT_DDI_LANES_TC3,
+POWER_DOMAIN_PORT_DDI_LANES_TC4,
+POWER_DOMAIN_AUX_USBC1,
+POWER_DOMAIN_AUX_USBC2,
+POWER_DOMAIN_AUX_USBC3,
+POWER_DOMAIN_AUX_USBC4,
+POWER_DOMAIN_AUX_TBT1,
+POWER_DOMAIN_AUX_TBT2,
+POWER_DOMAIN_AUX_TBT3,
+POWER_DOMAIN_AUX_TBT4,
+POWER_DOMAIN_INIT);
+
+static const struct i915_power_well_desc xe2lpd_power_wells_pica[] = {
+ {
+ .instances = _PW_INSTANCES(I915_PW("PICA_TC",
+ _pwdoms_pica_tc,
+ .id = DISP_PW_ID_NONE),
+ ),
+ .ops = _pica_power_well_ops,
+ },
+};
+
+static const struct i915_power_well_desc_list xe2lpd_power_wells[] = {
+ I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+ I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
+ I915_PW_DESCRIPTORS(xelpdp_power_wells_main),
+ I915_PW_DESCRIPTORS(xe2lpd_power_wells_pica),
+};
+
static void init_power_well_domains(const struct i915_power_well_instance
*inst,
struct i915_power_well *power_well)
{
@@ -1652,7 +1684,9 @@ int intel_display_power_map_init(struct
i915_power_domains *power_domains)
return 0;
}
- if (DISPLAY_VER(i915) >= 14)
+ if (DISPLAY_VER(i915) >= 20)
+ return set_power_wells(power_domains, xe2lpd_power_wells);
+ else if (DISPLAY_VER(i915) >= 14)
return set_power_wells(power_domains, xelpdp_power_wells);
else if (IS_DG2(i915))
return set_power_wells(power_domains, xehpd_power_wells);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c
b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 916009894d89..e1fb0bd7b3bf 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -1795,7 +1795,11 @@ static void xelpdp_aux_power_well_enable(struct
drm_i915_private *dev_priv,
{
enum aux_ch aux_ch =
i915_power_well_instance(power_well)->xelpdp.aux_ch;
- intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch),
+ i915_reg_t aux_ch_ctl = DISPLAY_VER(dev_priv) >= 20 ?
+ XE2LPD_DP_AUX_CH_CTL(aux_ch) :
+ XELPDP_DP_AUX_CH_CTL(aux_ch);
+
+ intel_de_rmw(dev_priv, aux_ch_ctl,
XELPDP_DP_AUX_CH_CTL_POWER_REQUEST,
XELPDP_DP_AUX_CH_CTL_POWER_REQUEST);
@@ -1813,7 +1817,11 @@ static void xelpdp_aux_power_well_disable(struct
drm_i915_private *dev_priv,
{
enum aux_ch aux_ch =
i915_power_well_instance(power_well)->xelpdp.aux_ch;
- intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch),
+ i915_reg_t aux_ch_ctl = DISPLAY_VER(dev_priv) >= 20 ?
+ XE2LPD_DP_AUX_CH_CTL(aux_ch) :
+ XELPDP_DP_AUX_CH_CTL(aux_ch);
+
+ intel_de_rmw(dev_priv, aux_ch_ctl,
XELPDP_DP_AUX_CH_CTL_POWER_REQUEST,
0);
usleep_range(10, 30);
@@ -1823,11 +1831,53 @@ static bool xelpdp_aux_power_well_enabled(struct
drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
enum aux_ch aux_ch =
[Intel-gfx] [PATCH 24/42] drm/i915/display: Remove FBC capability from fused off pipes
From: Clint Taylor
If a particular pipe is disabled by fuse also remove the FBC for that
pipe.
Bspec: 69464
Cc: Anusha Srivatsa
Cc: Gustavo Sousa
Signed-off-by: Clint Taylor
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_display_device.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
b/drivers/gpu/drm/i915/display/intel_display_device.c
index b853cd0c704a..c4ff5a08c269 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -962,16 +962,19 @@ void intel_display_device_info_runtime_init(struct
drm_i915_private *i915)
if (dfsm & SKL_DFSM_PIPE_B_DISABLE) {
display_runtime->pipe_mask &= ~BIT(PIPE_B);
display_runtime->cpu_transcoder_mask &=
~BIT(TRANSCODER_B);
+ display_runtime->fbc_mask &= ~BIT(INTEL_FBC_B);
}
if (dfsm & SKL_DFSM_PIPE_C_DISABLE) {
display_runtime->pipe_mask &= ~BIT(PIPE_C);
display_runtime->cpu_transcoder_mask &=
~BIT(TRANSCODER_C);
+ display_runtime->fbc_mask &= ~BIT(INTEL_FBC_C);
}
if (DISPLAY_VER(i915) >= 12 &&
(dfsm & TGL_DFSM_PIPE_D_DISABLE)) {
display_runtime->pipe_mask &= ~BIT(PIPE_D);
display_runtime->cpu_transcoder_mask &=
~BIT(TRANSCODER_D);
+ display_runtime->fbc_mask &= ~BIT(INTEL_FBC_D);
}
if (!display_runtime->pipe_mask)
--
2.40.1
