✗ Fi.CI.IGT: failure for Documentation/i915: remove kernel-doc for DMC wakelocks
== Series Details == Series: Documentation/i915: remove kernel-doc for DMC wakelocks URL : https://patchwork.freedesktop.org/series/133435/ State : failure == Summary == CI Bug Log - changes from CI_DRM_14746_full -> Patchwork_133435v1_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_133435v1_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_133435v1_full, please notify your bug team (i915-ci-in...@lists.freedesktop.org) to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (9 -> 9) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_133435v1_full: ### IGT changes ### Possible regressions * igt@gem_eio@in-flight-10ms: - shard-dg1: NOTRUN -> [INCOMPLETE][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133435v1/shard-dg1-16/igt@gem_...@in-flight-10ms.html * igt@kms_flip@flip-vs-panning-vs-hang@c-hdmi-a1: - shard-glk: NOTRUN -> [INCOMPLETE][2] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133435v1/shard-glk6/igt@kms_flip@flip-vs-panning-vs-h...@c-hdmi-a1.html Known issues Here are the changes found in Patchwork_133435v1_full that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - shard-rkl: NOTRUN -> [SKIP][3] ([i915#9318]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133435v1/shard-rkl-1/igt@debugfs_t...@basic-hwmon.html * igt@drm_fdinfo@busy-idle@vcs1: - shard-dg1: NOTRUN -> [SKIP][4] ([i915#8414]) +4 other tests skip [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133435v1/shard-dg1-15/igt@drm_fdinfo@busy-i...@vcs1.html * igt@gem_bad_reloc@negative-reloc-bltcopy: - shard-dg2: NOTRUN -> [SKIP][5] ([i915#3281]) +1 other test skip [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133435v1/shard-dg2-3/igt@gem_bad_re...@negative-reloc-bltcopy.html * igt@gem_ccs@block-multicopy-compressed: - shard-rkl: NOTRUN -> [SKIP][6] ([i915#9323]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133435v1/shard-rkl-6/igt@gem_...@block-multicopy-compressed.html * igt@gem_ccs@suspend-resume: - shard-dg1: NOTRUN -> [SKIP][7] ([i915#9323]) +1 other test skip [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133435v1/shard-dg1-15/igt@gem_...@suspend-resume.html * igt@gem_ctx_persistence@heartbeat-close: - shard-dg1: NOTRUN -> [SKIP][8] ([i915#8555]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133435v1/shard-dg1-15/igt@gem_ctx_persiste...@heartbeat-close.html * igt@gem_ctx_sseu@engines: - shard-dg2: NOTRUN -> [SKIP][9] ([i915#280]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133435v1/shard-dg2-3/igt@gem_ctx_s...@engines.html * igt@gem_ctx_sseu@mmap-args: - shard-tglu: NOTRUN -> [SKIP][10] ([i915#280]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133435v1/shard-tglu-7/igt@gem_ctx_s...@mmap-args.html * igt@gem_exec_balancer@bonded-sync: - shard-dg1: NOTRUN -> [SKIP][11] ([i915#4771]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133435v1/shard-dg1-15/igt@gem_exec_balan...@bonded-sync.html * igt@gem_exec_balancer@parallel-bb-first: - shard-rkl: NOTRUN -> [SKIP][12] ([i915#4525]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133435v1/shard-rkl-6/igt@gem_exec_balan...@parallel-bb-first.html * igt@gem_exec_fair@basic-pace: - shard-dg1: NOTRUN -> [SKIP][13] ([i915#3539]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133435v1/shard-dg1-15/igt@gem_exec_f...@basic-pace.html * igt@gem_exec_fair@basic-pace@rcs0: - shard-rkl: [PASS][14] -> [FAIL][15] ([i915#2842]) +2 other tests fail [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14746/shard-rkl-1/igt@gem_exec_fair@basic-p...@rcs0.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133435v1/shard-rkl-3/igt@gem_exec_fair@basic-p...@rcs0.html * igt@gem_exec_fence@submit67: - shard-dg2: NOTRUN -> [SKIP][16] ([i915#4812]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133435v1/shard-dg2-3/igt@gem_exec_fe...@submit67.html * igt@gem_exec_flush@basic-batch-kernel-default-wb: - shard-dg1: NOTRUN -> [SKIP][17] ([i915#3539] / [i915#4852]) +2 other tests skip [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133435v1/shard-dg1-14/igt@gem_exec_fl...@basic-batch-kernel-default-wb.html * igt@gem_exec_flush@basic-uc-pro-default: - shard-dg2: NOTRUN
Re: [RFC PATCH 0/3] Introducing I915_FORMAT_MOD_4_TILED_XE2_CCS Modifier for Xe2
On Tuesday, May 7, 2024 3:56:57 PM PDT Matt Roper wrote: > On Mon, May 06, 2024 at 09:52:35PM +0300, Juha-Pekka Heikkila wrote: > > These patches introduce I915_FORMAT_MOD_4_TILED_XE2_CCS modifier, which, > > from the kernel's perspective, behaves similarly to `I915_FORMAT_MOD_4_TILED`. > > This new modifier is primarily intended for user space to effectively monitor > > compression status, especially when dealing with a mix of compressed and > > uncompressed buffers. > > > > The addition of this modifier facilitates user space in managing compression > > status, particularly when utilizing both compressed and uncompressed buffers > > concurrently. To leverage compression for these buffers, user space > > applications must configure the appropriate Page Attribute Table (PAT) index. > > Display engine will treat all Tile4 as if it were compressed under all > > circumstances on Xe2 architecture. > > I may have missed some discussion about this, but I thought the previous > consensus was that we didn't want/need new modifiers for compression on > Xe2? If a userspace client (or the display hardware) receives a buffer > of unknown origin and unknown compression status, it's always fine to > select a compressed PAT when binding the buffer to read since even for > uncompressed buffers the CCS metadata will accurately reflect the > compression status. Unlike Xe1, where generating content without > compression enabled would leave random garbage in the FlatCCS area, Xe2 > will set the corresponding FlatCCS to '0x0' for each block, indicating > uncompressed data. > > Can you explain more what the benefit of handling these modifiers > explicitly is? > > > Matt Thanks, Matt! I'm a bit late in getting up to speed with the Xe2 compression changes; this is really good information. As I understand it...all blocks on the GPU behave in the way you mentioned, where generating uncompressed data via the GPU will set FlatCCS = 0, so you can assume a compressed PAT entry and everything works. One snag is...I've heard that CPU access doesn't work that way. So, if you mmap a buffer on the CPU, and write data with the CPU, then I think we're back to the "FlatCCS contains uninitialized garbage" case, where it's unsafe to assume a compressed PAT. And... we don't really know when sharing buffers whether the other side is going to want to do CPU access. It would be really nice to assume compression by default, though, which got me thinking: if we mmap a buffer via DRM_XE_GEM_MMAP_OFFSET, could xe.ko disable compression for us? So, resolve any outstanding CCS data, and then switch any PAT entries to uncompressed. Mapping would block until that resolve is done. It could leave compression off forever (once you CPU map a buffer, it's never compressed again). Or it could turn CCS back on when map count reaches 0 (but frankly I'm not sure that's terribly important, and sounds more complex). As I understand it, at least on discrete GPUs, the kernel already has to do something similar for eviction, when migrating BOs to system memory (which doesn't support compression). So this would be doing basically the same "resolve and disable CCS" step the kernel can presumably already do, but now on mmap as well. What do you think? Viable? Crazy? Have I missed something? --Ken signature.asc Description: This is a digitally signed message part.
Re: [RESEND 1/6] drm/nouveau: convert to using is_hdmi and has_audio from display info
Reviewed-by: Lyude Paul
On Fri, 2024-05-10 at 18:08 +0300, Jani Nikula wrote:
> Prefer the parsed results for is_hdmi and has_audio in display info
> over
> calling drm_detect_hdmi_monitor() and drm_detect_monitor_audio(),
> respectively.
>
> Conveniently, this also removes the need to use edid_blob_ptr.
>
> v2: Reverse a backwards if condition (Ilia)
>
> Cc: Karol Herbst
> Cc: Lyude Paul
> Cc: Danilo Krummrich
> Cc: nouv...@lists.freedesktop.org
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/nouveau/dispnv50/disp.c | 8
> drivers/gpu/drm/nouveau/dispnv50/head.c | 8 +---
> drivers/gpu/drm/nouveau/nouveau_connector.c | 2 +-
> 3 files changed, 6 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c
> b/drivers/gpu/drm/nouveau/dispnv50/disp.c
> index 0c3d88ad0b0e..168c27213287 100644
> --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c
> +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c
> @@ -751,7 +751,7 @@ nv50_audio_enable(struct drm_encoder *encoder,
> struct nouveau_crtc *nv_crtc,
> struct nouveau_encoder *nv_encoder =
> nouveau_encoder(encoder);
> struct nvif_outp *outp = _encoder->outp;
>
> - if (!nv50_audio_supported(encoder) ||
> !drm_detect_monitor_audio(nv_connector->edid))
> + if (!nv50_audio_supported(encoder) || !nv_connector-
> >base.display_info.has_audio)
> return;
>
> mutex_lock(>audio.lock);
> @@ -1765,7 +1765,7 @@ nv50_sor_atomic_enable(struct drm_encoder
> *encoder, struct drm_atomic_state *sta
> if ((disp->disp->object.oclass == GT214_DISP ||
> disp->disp->object.oclass >= GF110_DISP) &&
> nv_encoder->dcb->type != DCB_OUTPUT_LVDS &&
> - drm_detect_monitor_audio(nv_connector->edid))
> + nv_connector->base.display_info.has_audio)
> hda = true;
>
> if (!nvif_outp_acquired(outp))
> @@ -1774,7 +1774,7 @@ nv50_sor_atomic_enable(struct drm_encoder
> *encoder, struct drm_atomic_state *sta
> switch (nv_encoder->dcb->type) {
> case DCB_OUTPUT_TMDS:
> if (disp->disp->object.oclass != NV50_DISP &&
> - drm_detect_hdmi_monitor(nv_connector->edid))
> + nv_connector->base.display_info.is_hdmi)
> nv50_hdmi_enable(encoder, nv_crtc,
> nv_connector, state, mode, hda);
>
> if (nv_encoder->outp.or.link & 1) {
> @@ -1787,7 +1787,7 @@ nv50_sor_atomic_enable(struct drm_encoder
> *encoder, struct drm_atomic_state *sta
> */
> if (mode->clock >= 165000 &&
> nv_encoder->dcb->duallink_possible &&
> - !drm_detect_hdmi_monitor(nv_connector-
> >edid))
> + !nv_connector-
> >base.display_info.is_hdmi)
> proto =
> NV507D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS;
> } else {
> proto =
> NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B;
> diff --git a/drivers/gpu/drm/nouveau/dispnv50/head.c
> b/drivers/gpu/drm/nouveau/dispnv50/head.c
> index 83355dbc15ee..d7c74cc43ba5 100644
> --- a/drivers/gpu/drm/nouveau/dispnv50/head.c
> +++ b/drivers/gpu/drm/nouveau/dispnv50/head.c
> @@ -127,14 +127,8 @@ nv50_head_atomic_check_view(struct
> nv50_head_atom *armh,
> struct drm_display_mode *omode = >state.adjusted_mode;
> struct drm_display_mode *umode = >state.mode;
> int mode = asyc->scaler.mode;
> - struct edid *edid;
> int umode_vdisplay, omode_hdisplay, omode_vdisplay;
>
> - if (connector->edid_blob_ptr)
> - edid = (struct edid *)connector->edid_blob_ptr-
> >data;
> - else
> - edid = NULL;
> -
> if (!asyc->scaler.full) {
> if (mode == DRM_MODE_SCALE_NONE)
> omode = umode;
> @@ -162,7 +156,7 @@ nv50_head_atomic_check_view(struct nv50_head_atom
> *armh,
> */
> if ((asyc->scaler.underscan.mode == UNDERSCAN_ON ||
> (asyc->scaler.underscan.mode == UNDERSCAN_AUTO &&
> - drm_detect_hdmi_monitor(edid {
> + connector->display_info.is_hdmi))) {
> u32 bX = asyc->scaler.underscan.hborder;
> u32 bY = asyc->scaler.underscan.vborder;
> u32 r = (asyh->view.oH << 19) / asyh->view.oW;
> diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c
> b/drivers/gpu/drm/nouveau/nouveau_connector.c
> index 856b3ef5edb8..938832a6af15 100644
> --- a/drivers/gpu/drm/nouveau/nouveau_connector.c
> +++ b/drivers/gpu/drm/nouveau/nouveau_connector.c
> @@ -1034,7 +1034,7 @@ get_tmds_link_bandwidth(struct drm_connector
> *connector)
> unsigned duallink_scale =
> nouveau_duallink && nv_encoder->dcb-
> >duallink_possible ? 2 : 1;
>
> - if (drm_detect_hdmi_monitor(nv_connector->edid)) {
> + if (nv_connector->base.display_info.is_hdmi) {
> info = _connector->base.display_info;
> duallink_scale
Re: [PATCH 0/9] drm/i915: Plane fb refactoring
On Mon, May 06, 2024 at 03:57:09PM +0300, Ville Syrjala wrote: > From: Ville Syrjälä > > A bit of cleanup/refactoring around plane fb stuff. > This is mainly prep work for a slightly bigger rework > of alignment handling. > > Ville Syrjälä (9): > drm/i915: Split gen2 vs. gen3 .max_stride() > drm/i915: Clean up skl+ plane stride limits > drm/i915: Drop 'uses_fence' parameter from intel_pin_fb_obj_dpt() > drm/i915: Extract intel_plane_needs_physical() > drm/i915: Polish types in fb calculations Pushed up to here. Thanks for the review. > drm/i915: Constify 'fb' in during pinning > drm/i915: Change intel_fbdev_fb_alloc() reuturn type > drm/i915: Cleanup fbdev fb setup > drm/i915: Rename the fb pinning functions to indicate the address > space Some of the rest touch xe as well. Lucas, can you toss me an ack to merge via drm-intel-next? > > drivers/gpu/drm/i915/display/i9xx_plane.c | 34 --- > .../gpu/drm/i915/display/intel_atomic_plane.c | 8 ++ > .../gpu/drm/i915/display/intel_atomic_plane.h | 1 + > drivers/gpu/drm/i915/display/intel_dpt.c | 6 +- > drivers/gpu/drm/i915/display/intel_dpt.h | 6 +- > drivers/gpu/drm/i915/display/intel_fb.c | 27 +++--- > drivers/gpu/drm/i915/display/intel_fb_pin.c | 73 +++--- > drivers/gpu/drm/i915/display/intel_fb_pin.h | 12 +-- > drivers/gpu/drm/i915/display/intel_fbdev.c| 39 > drivers/gpu/drm/i915/display/intel_fbdev_fb.c | 6 +- > drivers/gpu/drm/i915/display/intel_fbdev_fb.h | 5 +- > .../drm/i915/display/skl_universal_plane.c| 94 ++- > drivers/gpu/drm/xe/display/xe_fb_pin.c| 18 ++-- > drivers/gpu/drm/xe/display/xe_plane_initial.c | 4 +- > 14 files changed, 175 insertions(+), 158 deletions(-) > > -- > 2.43.2 -- Ville Syrjälä Intel
✓ Fi.CI.BAT: success for drm/i915: skl+ plane register stuff
== Series Details == Series: drm/i915: skl+ plane register stuff URL : https://patchwork.freedesktop.org/series/133458/ State : success == Summary == CI Bug Log - changes from CI_DRM_14747 -> Patchwork_133458v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/index.html Participating hosts (42 -> 42) -- Additional (2): fi-glk-j4005 bat-mtlp-8 Missing(2): bat-dg2-11 fi-snb-2520m Known issues Here are the changes found in Patchwork_133458v1 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-arls-3: NOTRUN -> [SKIP][1] ([i915#9318]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/bat-arls-3/igt@debugfs_t...@basic-hwmon.html - bat-mtlp-8: NOTRUN -> [SKIP][2] ([i915#9318]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/bat-mtlp-8/igt@debugfs_t...@basic-hwmon.html * igt@gem_huc_copy@huc-copy: - fi-glk-j4005: NOTRUN -> [SKIP][3] ([i915#2190]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/fi-glk-j4005/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@parallel-random-engines: - bat-arls-3: NOTRUN -> [SKIP][4] ([i915#10213]) +3 other tests skip [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/bat-arls-3/igt@gem_lmem_swapp...@parallel-random-engines.html - bat-mtlp-8: NOTRUN -> [SKIP][5] ([i915#4613]) +3 other tests skip [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/bat-mtlp-8/igt@gem_lmem_swapp...@parallel-random-engines.html - fi-glk-j4005: NOTRUN -> [SKIP][6] ([i915#4613]) +3 other tests skip [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/fi-glk-j4005/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_mmap@basic: - bat-mtlp-8: NOTRUN -> [SKIP][7] ([i915#4083]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/bat-mtlp-8/igt@gem_m...@basic.html - bat-arls-3: NOTRUN -> [SKIP][8] ([i915#4083]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/bat-arls-3/igt@gem_m...@basic.html * igt@gem_render_tiled_blits@basic: - bat-mtlp-8: NOTRUN -> [SKIP][9] ([i915#4079]) +1 other test skip [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/bat-mtlp-8/igt@gem_render_tiled_bl...@basic.html - bat-arls-3: NOTRUN -> [SKIP][10] ([i915#10197] / [i915#10211] / [i915#4079]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/bat-arls-3/igt@gem_render_tiled_bl...@basic.html * igt@gem_tiled_blits@basic: - bat-arls-3: NOTRUN -> [SKIP][11] ([i915#10196] / [i915#4077]) +2 other tests skip [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/bat-arls-3/igt@gem_tiled_bl...@basic.html * igt@gem_tiled_fence_blits@basic: - bat-mtlp-8: NOTRUN -> [SKIP][12] ([i915#4077]) +2 other tests skip [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/bat-mtlp-8/igt@gem_tiled_fence_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-arls-3: NOTRUN -> [SKIP][13] ([i915#10206] / [i915#4079]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/bat-arls-3/igt@gem_tiled_pread_basic.html * igt@i915_pm_rps@basic-api: - bat-mtlp-8: NOTRUN -> [SKIP][14] ([i915#6621]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/bat-mtlp-8/igt@i915_pm_...@basic-api.html - bat-arls-3: NOTRUN -> [SKIP][15] ([i915#10209]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/bat-arls-3/igt@i915_pm_...@basic-api.html * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: - bat-mtlp-8: NOTRUN -> [SKIP][16] ([i915#5190]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/bat-mtlp-8/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html * igt@kms_addfb_basic@basic-y-tiled-legacy: - bat-mtlp-8: NOTRUN -> [SKIP][17] ([i915#4212]) +8 other tests skip [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/bat-mtlp-8/igt@kms_addfb_ba...@basic-y-tiled-legacy.html - bat-arls-3: NOTRUN -> [SKIP][18] ([i915#10200]) +9 other tests skip [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/bat-arls-3/igt@kms_addfb_ba...@basic-y-tiled-legacy.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - bat-arls-3: NOTRUN -> [SKIP][19] ([i915#10202]) +1 other test skip [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v1/bat-arls-3/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - bat-mtlp-8: NOTRUN -> [SKIP][20]
✓ Fi.CI.BAT: success for drm, nouveau/radeon/amdpgu: edid_blob_ptr cleanups
== Series Details == Series: drm, nouveau/radeon/amdpgu: edid_blob_ptr cleanups URL : https://patchwork.freedesktop.org/series/133455/ State : success == Summary == CI Bug Log - changes from CI_DRM_14747 -> Patchwork_133455v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133455v1/index.html Participating hosts (42 -> 42) -- Additional (3): fi-glk-j4005 bat-mtlp-8 fi-kbl-8809g Missing(3): bat-dg2-11 bat-jsl-1 fi-snb-2520m Known issues Here are the changes found in Patchwork_133455v1 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-arls-3: NOTRUN -> [SKIP][1] ([i915#9318]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133455v1/bat-arls-3/igt@debugfs_t...@basic-hwmon.html - bat-mtlp-8: NOTRUN -> [SKIP][2] ([i915#9318]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133455v1/bat-mtlp-8/igt@debugfs_t...@basic-hwmon.html * igt@gem_huc_copy@huc-copy: - fi-kbl-8809g: NOTRUN -> [SKIP][3] ([i915#2190]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133455v1/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html - fi-glk-j4005: NOTRUN -> [SKIP][4] ([i915#2190]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133455v1/fi-glk-j4005/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic@lmem0: - bat-dg2-8: [PASS][5] -> [FAIL][6] ([i915#10378]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14747/bat-dg2-8/igt@gem_lmem_swapping@ba...@lmem0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133455v1/bat-dg2-8/igt@gem_lmem_swapping@ba...@lmem0.html * igt@gem_lmem_swapping@parallel-random-engines: - bat-arls-3: NOTRUN -> [SKIP][7] ([i915#10213]) +3 other tests skip [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133455v1/bat-arls-3/igt@gem_lmem_swapp...@parallel-random-engines.html - bat-mtlp-8: NOTRUN -> [SKIP][8] ([i915#4613]) +3 other tests skip [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133455v1/bat-mtlp-8/igt@gem_lmem_swapp...@parallel-random-engines.html - fi-glk-j4005: NOTRUN -> [SKIP][9] ([i915#4613]) +3 other tests skip [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133455v1/fi-glk-j4005/igt@gem_lmem_swapp...@parallel-random-engines.html - fi-kbl-8809g: NOTRUN -> [SKIP][10] ([i915#4613]) +3 other tests skip [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133455v1/fi-kbl-8809g/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_mmap@basic: - bat-mtlp-8: NOTRUN -> [SKIP][11] ([i915#4083]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133455v1/bat-mtlp-8/igt@gem_m...@basic.html - bat-arls-3: NOTRUN -> [SKIP][12] ([i915#4083]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133455v1/bat-arls-3/igt@gem_m...@basic.html * igt@gem_render_tiled_blits@basic: - bat-mtlp-8: NOTRUN -> [SKIP][13] ([i915#4079]) +1 other test skip [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133455v1/bat-mtlp-8/igt@gem_render_tiled_bl...@basic.html - bat-arls-3: NOTRUN -> [SKIP][14] ([i915#10197] / [i915#10211] / [i915#4079]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133455v1/bat-arls-3/igt@gem_render_tiled_bl...@basic.html * igt@gem_tiled_blits@basic: - bat-arls-3: NOTRUN -> [SKIP][15] ([i915#10196] / [i915#4077]) +2 other tests skip [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133455v1/bat-arls-3/igt@gem_tiled_bl...@basic.html * igt@gem_tiled_fence_blits@basic: - bat-mtlp-8: NOTRUN -> [SKIP][16] ([i915#4077]) +2 other tests skip [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133455v1/bat-mtlp-8/igt@gem_tiled_fence_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-arls-3: NOTRUN -> [SKIP][17] ([i915#10206] / [i915#4079]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133455v1/bat-arls-3/igt@gem_tiled_pread_basic.html * igt@i915_pm_rps@basic-api: - bat-mtlp-8: NOTRUN -> [SKIP][18] ([i915#6621]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133455v1/bat-mtlp-8/igt@i915_pm_...@basic-api.html - bat-arls-3: NOTRUN -> [SKIP][19] ([i915#10209]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133455v1/bat-arls-3/igt@i915_pm_...@basic-api.html * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: - bat-mtlp-8: NOTRUN -> [SKIP][20] ([i915#5190]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133455v1/bat-mtlp-8/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html * igt@kms_addfb_basic@basic-y-tiled-legacy: - bat-mtlp-8: NOTRUN -> [SKIP][21] ([i915#4212]) +8
✗ Fi.CI.SPARSE: warning for drm, nouveau/radeon/amdpgu: edid_blob_ptr cleanups
== Series Details == Series: drm, nouveau/radeon/amdpgu: edid_blob_ptr cleanups URL : https://patchwork.freedesktop.org/series/133455/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
Re: [RESEND 0/6] drm, nouveau/radeon/amdpgu: edid_blob_ptr cleanups
On Fri, May 10, 2024 at 11:17 AM Jani Nikula wrote: > > I've sent this some moths ago, let's try again... > > BR, > Jani. > > Jani Nikula (6): > drm/nouveau: convert to using is_hdmi and has_audio from display info > drm/radeon: convert to using is_hdmi and has_audio from display info > drm/radeon: remove radeon_connector_edid() and stop using > edid_blob_ptr > drm/amdgpu: remove amdgpu_connector_edid() and stop using > edid_blob_ptr > drm/edid: add a helper for EDID sysfs property show > drm/connector: update edid_blob_ptr documentation Series is: Acked-by: Alex Deucher > > .../gpu/drm/amd/amdgpu/amdgpu_connectors.c| 16 - > .../gpu/drm/amd/amdgpu/amdgpu_connectors.h| 1 - > drivers/gpu/drm/amd/amdgpu/dce_v10_0.c| 4 +-- > drivers/gpu/drm/amd/amdgpu/dce_v11_0.c| 4 +-- > drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 4 +-- > drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 4 +-- > drivers/gpu/drm/drm_crtc_internal.h | 2 ++ > drivers/gpu/drm/drm_edid.c| 33 +++ > drivers/gpu/drm/drm_sysfs.c | 24 ++ > drivers/gpu/drm/nouveau/dispnv50/disp.c | 8 ++--- > drivers/gpu/drm/nouveau/dispnv50/head.c | 8 + > drivers/gpu/drm/nouveau/nouveau_connector.c | 2 +- > drivers/gpu/drm/radeon/atombios_encoders.c| 10 +++--- > drivers/gpu/drm/radeon/evergreen_hdmi.c | 5 ++- > drivers/gpu/drm/radeon/radeon_audio.c | 13 > drivers/gpu/drm/radeon/radeon_connectors.c| 27 --- > drivers/gpu/drm/radeon/radeon_display.c | 2 +- > drivers/gpu/drm/radeon/radeon_encoders.c | 4 +-- > drivers/gpu/drm/radeon/radeon_mode.h | 2 -- > include/drm/drm_connector.h | 6 +++- > 20 files changed, 79 insertions(+), 100 deletions(-) > > -- > 2.39.2 >
[PATCH 16/16] drm/i915: Handle SKL+ WM/DDB registers next to all other plane registers
From: Ville Syrjälä
Having the plane WM/DDB regitster write functions in skl_watermarks.c
is rather annoying when trying to implement DSB based plane updates.
Move them into the respective files that handle all other plane
register writes. Less places where I need to worry about the DSB
vs. MMIO decisions.
The downside is that we spread the wm struct details a bit further
afield. But if that becomes too annoying we can probably abstract
things a bit more with a few extra functions.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cursor.c | 32 +++
.../drm/i915/display/skl_universal_plane.c| 60
.../drm/i915/display/skl_universal_plane.h| 5 +
drivers/gpu/drm/i915/display/skl_watermark.c | 95 +--
drivers/gpu/drm/i915/display/skl_watermark.h | 13 ++-
5 files changed, 107 insertions(+), 98 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c
b/drivers/gpu/drm/i915/display/intel_cursor.c
index d2b459634732..3ecab15d1431 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -24,6 +24,7 @@
#include "intel_psr.h"
#include "intel_psr_regs.h"
#include "intel_vblank.h"
+#include "skl_universal_plane.h"
#include "skl_watermark.h"
#include "gem/i915_gem_object.h"
@@ -556,6 +557,37 @@ static void i9xx_cursor_update_sel_fetch_arm(struct
intel_plane *plane,
}
}
+static void skl_write_cursor_wm(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *i915 = to_i915(plane->base.dev);
+ enum plane_id plane_id = plane->id;
+ enum pipe pipe = plane->pipe;
+ const struct skl_pipe_wm *pipe_wm = _state->wm.skl.optimal;
+ const struct skl_ddb_entry *ddb =
+ _state->wm.skl.plane_ddb[plane_id];
+ int level;
+
+ for (level = 0; level < i915->display.wm.num_levels; level++)
+ intel_de_write_fw(i915, CUR_WM(pipe, level),
+
skl_plane_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));
+
+ intel_de_write_fw(i915, CUR_WM_TRANS(pipe),
+ skl_plane_wm_reg_val(skl_plane_trans_wm(pipe_wm,
plane_id)));
+
+ if (HAS_HW_SAGV_WM(i915)) {
+ const struct skl_plane_wm *wm = _wm->planes[plane_id];
+
+ intel_de_write_fw(i915, CUR_WM_SAGV(pipe),
+ skl_plane_wm_reg_val(>sagv.wm0));
+ intel_de_write_fw(i915, CUR_WM_SAGV_TRANS(pipe),
+ skl_plane_wm_reg_val(>sagv.trans_wm));
+ }
+
+ intel_de_write_fw(i915, CUR_BUF_CFG(pipe),
+ skl_plane_ddb_reg_val(ddb));
+}
+
/* TODO: split into noarm+arm pair */
static void i9xx_cursor_update_arm(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index ab560820bb23..a9914cb31631 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -617,6 +617,66 @@ static u32 skl_plane_stride(const struct intel_plane_state
*plane_state,
return stride / skl_plane_stride_mult(fb, color_plane, rotation);
}
+u32 skl_plane_ddb_reg_val(const struct skl_ddb_entry *entry)
+{
+ if (!entry->end)
+ return 0;
+
+ return PLANE_BUF_END(entry->end - 1) |
+ PLANE_BUF_START(entry->start);
+}
+
+u32 skl_plane_wm_reg_val(const struct skl_wm_level *level)
+{
+ u32 val = 0;
+
+ if (level->enable)
+ val |= PLANE_WM_EN;
+ if (level->ignore_lines)
+ val |= PLANE_WM_IGNORE_LINES;
+ val |= REG_FIELD_PREP(PLANE_WM_BLOCKS_MASK, level->blocks);
+ val |= REG_FIELD_PREP(PLANE_WM_LINES_MASK, level->lines);
+
+ return val;
+}
+
+static void skl_write_plane_wm(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *i915 = to_i915(plane->base.dev);
+ enum plane_id plane_id = plane->id;
+ enum pipe pipe = plane->pipe;
+ const struct skl_pipe_wm *pipe_wm = _state->wm.skl.optimal;
+ const struct skl_ddb_entry *ddb =
+ _state->wm.skl.plane_ddb[plane_id];
+ const struct skl_ddb_entry *ddb_y =
+ _state->wm.skl.plane_ddb_y[plane_id];
+ int level;
+
+ for (level = 0; level < i915->display.wm.num_levels; level++)
+ intel_de_write_fw(i915, PLANE_WM(pipe, plane_id, level),
+
skl_plane_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));
+
+ intel_de_write_fw(i915, PLANE_WM_TRANS(pipe, plane_id),
+ skl_plane_wm_reg_val(skl_plane_trans_wm(pipe_wm,
plane_id)));
+
+ if
[PATCH 15/16] drm/i915: Nuke skl_write_wm_level() and skl_ddb_entry_write()
From: Ville Syrjälä
Get rid of skl_ddb_entry_write() and skl_write_wm_level() and
just call intel_de_write_fw() directly.
This is prep work towards DSB based plane updates where these
wrappers are more of a hinderance.
Done with cocci mostly:
@@
expression D, R, L;
@@
- skl_write_wm_level(D, R, L)
+ intel_de_write_fw(D, R, skl_plane_wm_reg_val(L))
@@
expression D, R, B;
@@
- skl_ddb_entry_write(D, R, B)
+ intel_de_write_fw(D, R, skl_plane_ddb_reg_val(B))
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/skl_watermark.c | 57
1 file changed, 22 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
b/drivers/gpu/drm/i915/display/skl_watermark.c
index 8a0a26ab8e6a..1daceb8ef9de 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -2374,13 +2374,6 @@ static u32 skl_plane_ddb_reg_val(const struct
skl_ddb_entry *entry)
PLANE_BUF_START(entry->start);
}
-static void skl_ddb_entry_write(struct drm_i915_private *i915,
- i915_reg_t reg,
- const struct skl_ddb_entry *entry)
-{
- intel_de_write_fw(i915, reg, skl_plane_ddb_reg_val(entry));
-}
-
static u32 skl_plane_wm_reg_val(const struct skl_wm_level *level)
{
u32 val = 0;
@@ -2395,13 +2388,6 @@ static u32 skl_plane_wm_reg_val(const struct
skl_wm_level *level)
return val;
}
-static void skl_write_wm_level(struct drm_i915_private *i915,
- i915_reg_t reg,
- const struct skl_wm_level *level)
-{
- intel_de_write_fw(i915, reg, skl_plane_wm_reg_val(level));
-}
-
void skl_write_plane_wm(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state)
{
@@ -2416,27 +2402,27 @@ void skl_write_plane_wm(struct intel_plane *plane,
int level;
for (level = 0; level < i915->display.wm.num_levels; level++)
- skl_write_wm_level(i915, PLANE_WM(pipe, plane_id, level),
- skl_plane_wm_level(pipe_wm, plane_id,
level));
+ intel_de_write_fw(i915, PLANE_WM(pipe, plane_id, level),
+
skl_plane_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));
- skl_write_wm_level(i915, PLANE_WM_TRANS(pipe, plane_id),
- skl_plane_trans_wm(pipe_wm, plane_id));
+ intel_de_write_fw(i915, PLANE_WM_TRANS(pipe, plane_id),
+ skl_plane_wm_reg_val(skl_plane_trans_wm(pipe_wm,
plane_id)));
if (HAS_HW_SAGV_WM(i915)) {
const struct skl_plane_wm *wm = _wm->planes[plane_id];
- skl_write_wm_level(i915, PLANE_WM_SAGV(pipe, plane_id),
- >sagv.wm0);
- skl_write_wm_level(i915, PLANE_WM_SAGV_TRANS(pipe, plane_id),
- >sagv.trans_wm);
+ intel_de_write_fw(i915, PLANE_WM_SAGV(pipe, plane_id),
+ skl_plane_wm_reg_val(>sagv.wm0));
+ intel_de_write_fw(i915, PLANE_WM_SAGV_TRANS(pipe, plane_id),
+ skl_plane_wm_reg_val(>sagv.trans_wm));
}
- skl_ddb_entry_write(i915,
- PLANE_BUF_CFG(pipe, plane_id), ddb);
+ intel_de_write_fw(i915, PLANE_BUF_CFG(pipe, plane_id),
+ skl_plane_ddb_reg_val(ddb));
if (DISPLAY_VER(i915) < 11)
- skl_ddb_entry_write(i915,
- PLANE_NV12_BUF_CFG(pipe, plane_id), ddb_y);
+ intel_de_write_fw(i915, PLANE_NV12_BUF_CFG(pipe, plane_id),
+ skl_plane_ddb_reg_val(ddb_y));
}
void skl_write_cursor_wm(struct intel_plane *plane,
@@ -2451,22 +2437,23 @@ void skl_write_cursor_wm(struct intel_plane *plane,
int level;
for (level = 0; level < i915->display.wm.num_levels; level++)
- skl_write_wm_level(i915, CUR_WM(pipe, level),
- skl_plane_wm_level(pipe_wm, plane_id,
level));
+ intel_de_write_fw(i915, CUR_WM(pipe, level),
+
skl_plane_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));
- skl_write_wm_level(i915, CUR_WM_TRANS(pipe),
- skl_plane_trans_wm(pipe_wm, plane_id));
+ intel_de_write_fw(i915, CUR_WM_TRANS(pipe),
+ skl_plane_wm_reg_val(skl_plane_trans_wm(pipe_wm,
plane_id)));
if (HAS_HW_SAGV_WM(i915)) {
const struct skl_plane_wm *wm = _wm->planes[plane_id];
- skl_write_wm_level(i915, CUR_WM_SAGV(pipe),
- >sagv.wm0);
- skl_write_wm_level(i915, CUR_WM_SAGV_TRANS(pipe),
- >sagv.trans_wm);
+ intel_de_write_fw(i915,
[PATCH 14/16] drm/i915: Extract skl_plane_{wm,ddb}_reg_val()
From: Ville Syrjälä
Extract helpers to calculate the final wm/ddb register
values for skl+. Will allow me to more cleanly remove the
register write wrappers for these registers.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/skl_watermark.c | 29 +---
1 file changed, 19 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
b/drivers/gpu/drm/i915/display/skl_watermark.c
index 2a2073bf3aca..8a0a26ab8e6a 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -2365,21 +2365,23 @@ static int skl_build_pipe_wm(struct intel_atomic_state
*state,
return skl_wm_check_vblank(crtc_state);
}
+static u32 skl_plane_ddb_reg_val(const struct skl_ddb_entry *entry)
+{
+ if (!entry->end)
+ return 0;
+
+ return PLANE_BUF_END(entry->end - 1) |
+ PLANE_BUF_START(entry->start);
+}
+
static void skl_ddb_entry_write(struct drm_i915_private *i915,
i915_reg_t reg,
const struct skl_ddb_entry *entry)
{
- if (entry->end)
- intel_de_write_fw(i915, reg,
- PLANE_BUF_END(entry->end - 1) |
- PLANE_BUF_START(entry->start));
- else
- intel_de_write_fw(i915, reg, 0);
+ intel_de_write_fw(i915, reg, skl_plane_ddb_reg_val(entry));
}
-static void skl_write_wm_level(struct drm_i915_private *i915,
- i915_reg_t reg,
- const struct skl_wm_level *level)
+static u32 skl_plane_wm_reg_val(const struct skl_wm_level *level)
{
u32 val = 0;
@@ -2390,7 +2392,14 @@ static void skl_write_wm_level(struct drm_i915_private
*i915,
val |= REG_FIELD_PREP(PLANE_WM_BLOCKS_MASK, level->blocks);
val |= REG_FIELD_PREP(PLANE_WM_LINES_MASK, level->lines);
- intel_de_write_fw(i915, reg, val);
+ return val;
+}
+
+static void skl_write_wm_level(struct drm_i915_private *i915,
+ i915_reg_t reg,
+ const struct skl_wm_level *level)
+{
+ intel_de_write_fw(i915, reg, skl_plane_wm_reg_val(level));
}
void skl_write_plane_wm(struct intel_plane *plane,
--
2.43.2
[PATCH 13/16] drm/i915: Refactor skl+ plane register offset calculations
From: Ville Syrjälä Currentluy every skl+ plane register defines some intermediate macros to calculate the final register offset. Pull all of that into common macros, simplifying the final register offset stuff into just five defines: - raw register offsets for the planes 1 and 2 on pipes A and B - the final parametrized macro Signed-off-by: Ville Syrjälä --- .../i915/display/skl_universal_plane_regs.h | 186 +- 1 file changed, 93 insertions(+), 93 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h index 18dbe717ea21..07bcdf4e195d 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h @@ -8,6 +8,15 @@ #include "intel_display_reg_defs.h" +#define _SKL_PLANE(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \ + _PLANE((plane), _PIPE((pipe), (reg_1_a), (reg_1_b)), _PIPE((pipe), (reg_2_a), (reg_2_b))) +#define _SKL_PLANE_DW(pipe, plane, dw, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \ + (_SKL_PLANE((pipe), (plane), (reg_1_a), (reg_1_b), (reg_2_a), (reg_2_b)) + (dw) * 4) +#define _MMIO_SKL_PLANE(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \ + _MMIO(_SKL_PLANE((pipe), (plane), (reg_1_a), (reg_1_b), (reg_2_a), (reg_2_b))) +#define _MMIO_SKL_PLANE_DW(pipe, plane, dw, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \ + _MMIO(_SKL_PLANE_DW((pipe), (plane), (dw), (reg_1_a), (reg_1_b), (reg_2_a), (reg_2_b))) + #define _PLANE_CTL_1_A 0x70180 #define PLANE_CTL_ENABLE REG_BIT(31) #define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */ @@ -75,9 +84,9 @@ #define _PLANE_CTL_2_A 0x70280 #define _PLANE_CTL_1_B 0x71180 #define _PLANE_CTL_2_B 0x71280 -#define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B) -#define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B) -#define PLANE_CTL(pipe, plane) _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe)) +#define PLANE_CTL(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ + _PLANE_CTL_1_A, _PLANE_CTL_1_B, \ + _PLANE_CTL_2_A, _PLANE_CTL_2_B) #define _PLANE_STRIDE_1_A 0x70188 #define PLANE_STRIDE__MASK REG_GENMASK(11, 0) @@ -85,10 +94,9 @@ #define _PLANE_STRIDE_2_A 0x70288 #define _PLANE_STRIDE_1_B 0x71188 #define _PLANE_STRIDE_2_B 0x71288 -#define _PLANE_STRIDE_1(pipe) _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B) -#define _PLANE_STRIDE_2(pipe) _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B) -#define PLANE_STRIDE(pipe, plane) _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe)) - +#define PLANE_STRIDE(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ + _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B, \ + _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B) #define _PLANE_POS_1_A 0x7018c #define PLANE_POS_Y_MASK REG_GENMASK(31, 16) #define PLANE_POS_Y(y) REG_FIELD_PREP(PLANE_POS_Y_MASK, (y)) @@ -97,9 +105,9 @@ #define _PLANE_POS_2_A 0x7028c #define _PLANE_POS_1_B 0x7118c #define _PLANE_POS_2_B 0x7128c -#define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B) -#define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B) -#define PLANE_POS(pipe, plane) _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe)) +#define PLANE_POS(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ + _PLANE_POS_1_A, _PLANE_POS_1_B, \ + _PLANE_POS_2_A, _PLANE_POS_2_B) #define _PLANE_SIZE_1_A0x70190 #define PLANE_HEIGHT_MASKREG_GENMASK(31, 16) @@ -109,26 +117,26 @@ #define _PLANE_SIZE_2_A0x70290 #define _PLANE_SIZE_1_B0x71190 #define _PLANE_SIZE_2_B0x71290 -#define _PLANE_SIZE_1(pipe)_PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B) -#define _PLANE_SIZE_2(pipe)_PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B) -#define PLANE_SIZE(pipe, plane)_MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe)) +#define PLANE_SIZE(pipe, plane)_MMIO_SKL_PLANE((pipe), (plane), \ +
[PATCH 12/16] drm/i915: Drop a few unwanted tabs from skl+ plane reg defines
From: Ville Syrjälä A few extra tabs have snuck into the skl+ plane register bit definitions. Remove them. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/skl_universal_plane_regs.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h index 8ef9bd50d021..18dbe717ea21 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h @@ -199,17 +199,17 @@ #define _PLANE_CUS_CTL_1_A 0x701c8 #define PLANE_CUS_ENABLE REG_BIT(31) -#define PLANE_CUS_Y_PLANE_MASK REG_BIT(30) +#define PLANE_CUS_Y_PLANE_MASK REG_BIT(30) #define PLANE_CUS_Y_PLANE_4_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0) #define PLANE_CUS_Y_PLANE_5_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1) #define PLANE_CUS_Y_PLANE_6_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0) #define PLANE_CUS_Y_PLANE_7_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1) -#define PLANE_CUS_HPHASE_SIGN_NEGATIVE REG_BIT(19) +#define PLANE_CUS_HPHASE_SIGN_NEGATIVE REG_BIT(19) #define PLANE_CUS_HPHASE_MASKREG_GENMASK(17, 16) #define PLANE_CUS_HPHASE_0 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 0) #define PLANE_CUS_HPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 1) #define PLANE_CUS_HPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 2) -#define PLANE_CUS_VPHASE_SIGN_NEGATIVE REG_BIT(15) +#define PLANE_CUS_VPHASE_SIGN_NEGATIVE REG_BIT(15) #define PLANE_CUS_VPHASE_MASKREG_GENMASK(13, 12) #define PLANE_CUS_VPHASE_0 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 0) #define PLANE_CUS_VPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 1) -- 2.43.2
[PATCH 11/16] drm/i915: Use REG_BIT for PLANE_WM bits
From: Ville Syrjälä A couple of PLANE_WM bits were still using the hand rolled (1< --- drivers/gpu/drm/i915/display/skl_universal_plane_regs.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h index 0ad14727e334..8ef9bd50d021 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h @@ -300,8 +300,8 @@ _MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + (index) * 4) #define _PLANE_WM_1_A_00x70240 -#define PLANE_WM_EN (1 << 31) -#define PLANE_WM_IGNORE_LINES(1 << 30) +#define PLANE_WM_EN REG_BIT(31) +#define PLANE_WM_IGNORE_LINESREG_BIT(30) #define PLANE_WM_LINES_MASK REG_GENMASK(26, 14) #define PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0) #define _PLANE_WM_1_B_00x71240 -- 2.43.2
[PATCH 10/16] drm/i915: Shuffle the skl+ plane register definitions
From: Ville Syrjälä Rearrange the plane skl+ universal plane register definitions: - keep everything related to the same register in one place - sort based on register offset - unify the whitespace/etc a bit Signed-off-by: Ville Syrjälä --- .../i915/display/skl_universal_plane_regs.h | 502 -- 1 file changed, 207 insertions(+), 295 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h index 0558d97614e1..0ad14727e334 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h @@ -9,8 +9,6 @@ #include "intel_display_reg_defs.h" #define _PLANE_CTL_1_A 0x70180 -#define _PLANE_CTL_2_A 0x70280 -#define _PLANE_CTL_3_A 0x70380 #define PLANE_CTL_ENABLE REG_BIT(31) #define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */ #define PLANE_CTL_ARB_SLOTS(x) REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */ @@ -74,59 +72,132 @@ #define PLANE_CTL_ROTATE_90 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 1) #define PLANE_CTL_ROTATE_180 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 2) #define PLANE_CTL_ROTATE_270 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 3) +#define _PLANE_CTL_2_A 0x70280 +#define _PLANE_CTL_1_B 0x71180 +#define _PLANE_CTL_2_B 0x71280 +#define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B) +#define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B) +#define PLANE_CTL(pipe, plane) _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe)) + #define _PLANE_STRIDE_1_A 0x70188 -#define _PLANE_STRIDE_2_A 0x70288 -#define _PLANE_STRIDE_3_A 0x70388 #define PLANE_STRIDE__MASK REG_GENMASK(11, 0) #define PLANE_STRIDE_(stride) REG_FIELD_PREP(PLANE_STRIDE__MASK, (stride)) +#define _PLANE_STRIDE_2_A 0x70288 +#define _PLANE_STRIDE_1_B 0x71188 +#define _PLANE_STRIDE_2_B 0x71288 +#define _PLANE_STRIDE_1(pipe) _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B) +#define _PLANE_STRIDE_2(pipe) _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B) +#define PLANE_STRIDE(pipe, plane) _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe)) + #define _PLANE_POS_1_A 0x7018c -#define _PLANE_POS_2_A 0x7028c -#define _PLANE_POS_3_A 0x7038c #define PLANE_POS_Y_MASK REG_GENMASK(31, 16) #define PLANE_POS_Y(y) REG_FIELD_PREP(PLANE_POS_Y_MASK, (y)) #define PLANE_POS_X_MASK REG_GENMASK(15, 0) #define PLANE_POS_X(x) REG_FIELD_PREP(PLANE_POS_X_MASK, (x)) +#define _PLANE_POS_2_A 0x7028c +#define _PLANE_POS_1_B 0x7118c +#define _PLANE_POS_2_B 0x7128c +#define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B) +#define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B) +#define PLANE_POS(pipe, plane) _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe)) + #define _PLANE_SIZE_1_A0x70190 -#define _PLANE_SIZE_2_A0x70290 -#define _PLANE_SIZE_3_A0x70390 #define PLANE_HEIGHT_MASKREG_GENMASK(31, 16) #define PLANE_HEIGHT(h) REG_FIELD_PREP(PLANE_HEIGHT_MASK, (h)) #define PLANE_WIDTH_MASK REG_GENMASK(15, 0) #define PLANE_WIDTH(w) REG_FIELD_PREP(PLANE_WIDTH_MASK, (w)) +#define _PLANE_SIZE_2_A0x70290 +#define _PLANE_SIZE_1_B0x71190 +#define _PLANE_SIZE_2_B0x71290 +#define _PLANE_SIZE_1(pipe)_PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B) +#define _PLANE_SIZE_2(pipe)_PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B) +#define PLANE_SIZE(pipe, plane)_MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe)) + +#define _PLANE_KEYVAL_1_A 0x70194 +#define _PLANE_KEYVAL_2_A 0x70294 +#define _PLANE_KEYVAL_1_B 0x71194 +#define _PLANE_KEYVAL_2_B 0x71294 +#define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B) +#define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B) +#define PLANE_KEYVAL(pipe, plane)
[PATCH 09/16] drm/i915: Drop useless PLANE_FOO_3 register defines
From: Ville Syrjälä We only need register defines for the first two planes on the first two pipes. Nuke everything else. Signed-off-by: Ville Syrjälä --- .../gpu/drm/i915/display/skl_universal_plane_regs.h | 12 1 file changed, 12 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h index d0c760e8..0558d97614e1 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h @@ -234,49 +234,38 @@ #define _PLANE_CTL_1_B 0x71180 #define _PLANE_CTL_2_B 0x71280 -#define _PLANE_CTL_3_B 0x71380 #define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B) #define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B) -#define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B) #define PLANE_CTL(pipe, plane) \ _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe)) #define _PLANE_STRIDE_1_B 0x71188 #define _PLANE_STRIDE_2_B 0x71288 -#define _PLANE_STRIDE_3_B 0x71388 #define _PLANE_STRIDE_1(pipe) \ _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B) #define _PLANE_STRIDE_2(pipe) \ _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B) -#define _PLANE_STRIDE_3(pipe) \ - _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B) #define PLANE_STRIDE(pipe, plane) \ _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe)) #define _PLANE_POS_1_B 0x7118c #define _PLANE_POS_2_B 0x7128c -#define _PLANE_POS_3_B 0x7138c #define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B) #define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B) -#define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B) #define PLANE_POS(pipe, plane) \ _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe)) #define _PLANE_SIZE_1_B0x71190 #define _PLANE_SIZE_2_B0x71290 -#define _PLANE_SIZE_3_B0x71390 #define _PLANE_SIZE_1(pipe)_PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B) #define _PLANE_SIZE_2(pipe)_PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B) -#define _PLANE_SIZE_3(pipe)_PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B) #define PLANE_SIZE(pipe, plane)\ _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe)) #define _PLANE_SURF_1_B0x7119c #define _PLANE_SURF_2_B0x7129c -#define _PLANE_SURF_3_B0x7139c #define _PLANE_SURF_1(pipe)_PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B) #define _PLANE_SURF_2(pipe)_PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B) -#define _PLANE_SURF_3(pipe)_PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B) #define PLANE_SURF(pipe, plane)\ _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe)) @@ -351,7 +340,6 @@ #define _PLANE_COLOR_CTL_1_B 0x711CC #define _PLANE_COLOR_CTL_2_B 0x712CC -#define _PLANE_COLOR_CTL_3_B 0x713CC #define _PLANE_COLOR_CTL_1(pipe) \ _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B) #define _PLANE_COLOR_CTL_2(pipe) \ -- 2.43.2
[PATCH 08/16] drm/i915/gvt: Use PLANE_CTL and PLANE_SURF defines
From: Ville Syrjälä Stop hand rolling PLANE_CTL and PLANE_SURF for the third plane and just use the real thing. Cc: Zhenyu Wang CC: Zhi Wang Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index b53c98cd6d7f..843bdb46d49c 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -1030,12 +1030,12 @@ static int iterate_skl_plus_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 1)); MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 2)); MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 3)); - MMIO_D(_MMIO(_PLANE_CTL_3_A)); - MMIO_D(_MMIO(_PLANE_CTL_3_B)); - MMIO_D(_MMIO(0x72380)); - MMIO_D(_MMIO(0x7239c)); - MMIO_D(_MMIO(_PLANE_SURF_3_A)); - MMIO_D(_MMIO(_PLANE_SURF_3_B)); + MMIO_D(PLANE_CTL(PIPE_A, 2)); + MMIO_D(PLANE_CTL(PIPE_B, 2)); + MMIO_D(PLANE_CTL(PIPE_C, 2)); + MMIO_D(PLANE_SURF(PIPE_A, 2)); + MMIO_D(PLANE_SURF(PIPE_B, 2)); + MMIO_D(PLANE_SURF(PIPE_C, 2)); MMIO_D(DMC_SSP_BASE); MMIO_D(DMC_HTP_SKL); MMIO_D(DMC_LAST_WRITE); -- 2.43.2
[PATCH 07/16] drm/i915/gvt: Use the full PLANE_KEY*() defines
From: Ville Syrjälä Stop hand rolling PLANE_KEY*() register defines and just use the real thing. Cc: Zhenyu Wang CC: Zhi Wang Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 18 +- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index ad3bf60855bc..b53c98cd6d7f 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -1075,15 +1075,15 @@ static int iterate_skl_plus_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(_MMIO(0x70034)); MMIO_D(_MMIO(0x71034)); MMIO_D(_MMIO(0x72034)); - MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A))); - MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B))); - MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C))); - MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A))); - MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B))); - MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_C))); - MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A))); - MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B))); - MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C))); + MMIO_D(PLANE_KEYVAL(PIPE_A, 0)); + MMIO_D(PLANE_KEYVAL(PIPE_B, 0)); + MMIO_D(PLANE_KEYVAL(PIPE_C, 0)); + MMIO_D(PLANE_KEYMAX(PIPE_A, 0)); + MMIO_D(PLANE_KEYMAX(PIPE_B, 0)); + MMIO_D(PLANE_KEYMAX(PIPE_C, 0)); + MMIO_D(PLANE_KEYMSK(PIPE_A, 0)); + MMIO_D(PLANE_KEYMSK(PIPE_B, 0)); + MMIO_D(PLANE_KEYMSK(PIPE_C, 0)); MMIO_D(_MMIO(0x44500)); #define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4) MMIO_RING_D(CSFE_CHICKEN1_REG); -- 2.43.2
[PATCH 06/16] drm/i915/gvt: Use the proper PLANE_AUX_OFFSET() define
From: Ville Syrjälä Stop hand rolling PLANE_AUX_OFFSET() and just use the real thing. Cc: Zhenyu Wang CC: Zhi Wang Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/gvt/handlers.c | 24 ++--- drivers/gpu/drm/i915/gvt/reg.h | 2 -- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 24 ++--- 3 files changed, 24 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index 6b02612ddef5..6f633035618e 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -2693,20 +2693,20 @@ static int init_skl_mmio_info(struct intel_gvt *gvt) MMIO_DH(PLANE_AUX_DIST(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); MMIO_DH(PLANE_AUX_DIST(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL); - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL); - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL); - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL); + MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); + MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); + MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); + MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL); - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL); - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL); - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL); + MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); + MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); + MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); + MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL); - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL); - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL); - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL); + MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); + MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); + MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); + MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); diff --git a/drivers/gpu/drm/i915/gvt/reg.h b/drivers/gpu/drm/i915/gvt/reg.h index e8a56faafe95..90d8eb1761a3 100644 --- a/drivers/gpu/drm/i915/gvt/reg.h +++ b/drivers/gpu/drm/i915/gvt/reg.h @@ -57,8 +57,6 @@ #define VGT_SPRSTRIDE(pipe)_PIPE(pipe, _SPRA_STRIDE, _PLANE_STRIDE_2_B) -#define _REG_701C4(pipe, plane) (0x701c4 + pipe * 0x1000 + (plane - 1) * 0x100) - #define SKL_FLIP_EVENT(pipe, plane) (PRIMARY_A_FLIP_DONE + (plane) * 3 + (pipe)) #define REG50080_FLIP_TYPE_MASK0x3 diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index cf45342a6db0..ad3bf60855bc 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -1018,18 +1018,18 @@ static int iterate_skl_plus_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(PLANE_AUX_DIST(PIPE_C, 1)); MMIO_D(PLANE_AUX_DIST(PIPE_C, 2)); MMIO_D(PLANE_AUX_DIST(PIPE_C, 3)); - MMIO_D(_MMIO(_REG_701C4(PIPE_A, 1))); - MMIO_D(_MMIO(_REG_701C4(PIPE_A, 2))); - MMIO_D(_MMIO(_REG_701C4(PIPE_A, 3))); - MMIO_D(_MMIO(_REG_701C4(PIPE_A, 4))); - MMIO_D(_MMIO(_REG_701C4(PIPE_B, 1))); - MMIO_D(_MMIO(_REG_701C4(PIPE_B, 2))); - MMIO_D(_MMIO(_REG_701C4(PIPE_B, 3))); - MMIO_D(_MMIO(_REG_701C4(PIPE_B, 4))); - MMIO_D(_MMIO(_REG_701C4(PIPE_C, 1))); - MMIO_D(_MMIO(_REG_701C4(PIPE_C, 2))); - MMIO_D(_MMIO(_REG_701C4(PIPE_C, 3))); - MMIO_D(_MMIO(_REG_701C4(PIPE_C, 4))); + MMIO_D(PLANE_AUX_OFFSET(PIPE_A, 0)); + MMIO_D(PLANE_AUX_OFFSET(PIPE_A, 1)); + MMIO_D(PLANE_AUX_OFFSET(PIPE_A, 2)); + MMIO_D(PLANE_AUX_OFFSET(PIPE_A, 3)); + MMIO_D(PLANE_AUX_OFFSET(PIPE_B, 0)); + MMIO_D(PLANE_AUX_OFFSET(PIPE_B, 1)); + MMIO_D(PLANE_AUX_OFFSET(PIPE_B, 2)); + MMIO_D(PLANE_AUX_OFFSET(PIPE_B, 3)); + MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 0)); + MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 1)); + MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 2)); + MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 3)); MMIO_D(_MMIO(_PLANE_CTL_3_A)); MMIO_D(_MMIO(_PLANE_CTL_3_B)); MMIO_D(_MMIO(0x72380)); -- 2.43.2
[PATCH 05/16] drm/i915/gvt: Use the proper PLANE_AUX_DIST() define
From: Ville Syrjälä Stop hand rolling PLANE_AUX_DIST() and just use the real thing. Cc: Zhenyu Wang CC: Zhi Wang Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/gvt/handlers.c | 24 ++--- drivers/gpu/drm/i915/gvt/reg.h | 1 - drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 24 ++--- 3 files changed, 24 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index 6c857beb5083..6b02612ddef5 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -2678,20 +2678,20 @@ static int init_skl_mmio_info(struct intel_gvt *gvt) MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL); - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL); - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL); - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL); + MMIO_DH(PLANE_AUX_DIST(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); + MMIO_DH(PLANE_AUX_DIST(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); + MMIO_DH(PLANE_AUX_DIST(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); + MMIO_DH(PLANE_AUX_DIST(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL); - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL); - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL); - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL); + MMIO_DH(PLANE_AUX_DIST(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); + MMIO_DH(PLANE_AUX_DIST(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); + MMIO_DH(PLANE_AUX_DIST(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); + MMIO_DH(PLANE_AUX_DIST(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL); - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL); - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL); - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL); + MMIO_DH(PLANE_AUX_DIST(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); + MMIO_DH(PLANE_AUX_DIST(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); + MMIO_DH(PLANE_AUX_DIST(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); + MMIO_DH(PLANE_AUX_DIST(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL); MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL); diff --git a/drivers/gpu/drm/i915/gvt/reg.h b/drivers/gpu/drm/i915/gvt/reg.h index d8216c63c39a..e8a56faafe95 100644 --- a/drivers/gpu/drm/i915/gvt/reg.h +++ b/drivers/gpu/drm/i915/gvt/reg.h @@ -57,7 +57,6 @@ #define VGT_SPRSTRIDE(pipe)_PIPE(pipe, _SPRA_STRIDE, _PLANE_STRIDE_2_B) -#define _REG_701C0(pipe, plane) (0x701c0 + pipe * 0x1000 + (plane - 1) * 0x100) #define _REG_701C4(pipe, plane) (0x701c4 + pipe * 0x1000 + (plane - 1) * 0x100) #define SKL_FLIP_EVENT(pipe, plane) (PRIMARY_A_FLIP_DONE + (plane) * 3 + (pipe)) diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index 3b79c1c84b79..cf45342a6db0 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -1006,18 +1006,18 @@ static int iterate_skl_plus_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(PLANE_NV12_BUF_CFG(PIPE_C, 1)); MMIO_D(PLANE_NV12_BUF_CFG(PIPE_C, 2)); MMIO_D(PLANE_NV12_BUF_CFG(PIPE_C, 3)); - MMIO_D(_MMIO(_REG_701C0(PIPE_A, 1))); - MMIO_D(_MMIO(_REG_701C0(PIPE_A, 2))); - MMIO_D(_MMIO(_REG_701C0(PIPE_A, 3))); - MMIO_D(_MMIO(_REG_701C0(PIPE_A, 4))); - MMIO_D(_MMIO(_REG_701C0(PIPE_B, 1))); - MMIO_D(_MMIO(_REG_701C0(PIPE_B, 2))); - MMIO_D(_MMIO(_REG_701C0(PIPE_B, 3))); - MMIO_D(_MMIO(_REG_701C0(PIPE_B, 4))); - MMIO_D(_MMIO(_REG_701C0(PIPE_C, 1))); - MMIO_D(_MMIO(_REG_701C0(PIPE_C, 2))); - MMIO_D(_MMIO(_REG_701C0(PIPE_C, 3))); - MMIO_D(_MMIO(_REG_701C0(PIPE_C, 4))); + MMIO_D(PLANE_AUX_DIST(PIPE_A, 0)); + MMIO_D(PLANE_AUX_DIST(PIPE_A, 1)); + MMIO_D(PLANE_AUX_DIST(PIPE_A, 2)); + MMIO_D(PLANE_AUX_DIST(PIPE_A, 3)); + MMIO_D(PLANE_AUX_DIST(PIPE_B, 0)); + MMIO_D(PLANE_AUX_DIST(PIPE_B, 1)); + MMIO_D(PLANE_AUX_DIST(PIPE_B, 2)); + MMIO_D(PLANE_AUX_DIST(PIPE_B, 3)); + MMIO_D(PLANE_AUX_DIST(PIPE_C, 0)); + MMIO_D(PLANE_AUX_DIST(PIPE_C, 1)); + MMIO_D(PLANE_AUX_DIST(PIPE_C, 2)); + MMIO_D(PLANE_AUX_DIST(PIPE_C, 3)); MMIO_D(_MMIO(_REG_701C4(PIPE_A, 1))); MMIO_D(_MMIO(_REG_701C4(PIPE_A, 2))); MMIO_D(_MMIO(_REG_701C4(PIPE_A, 3))); -- 2.43.2
[PATCH 04/16] drm/i915: Move skl+ wm/ddb registers to proper headers
From: Ville Syrjälä On SKL+ the watermark/DDB registers are proper per-plane registers. Move the definitons to their respective files. Cc: Zhenyu Wang CC: Zhi Wang Signed-off-by: Ville Syrjälä --- .../gpu/drm/i915/display/intel_cursor_regs.h | 20 + .../i915/display/skl_universal_plane_regs.h | 64 ++ drivers/gpu/drm/i915/display/skl_watermark.c | 1 + .../gpu/drm/i915/display/skl_watermark_regs.h | 83 --- drivers/gpu/drm/i915/gvt/handlers.c | 1 + 5 files changed, 86 insertions(+), 83 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h b/drivers/gpu/drm/i915/display/intel_cursor_regs.h index 62f7fb5c3f10..a478ef5787c5 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h +++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h @@ -75,4 +75,24 @@ #define CUR_CHICKEN(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_CHICKEN_A) #define CURSURFLIVE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASURFLIVE) +/* skl+ */ +#define _CUR_WM_A_00x70140 +#define _CUR_WM_B_00x71140 +#define _CUR_WM_SAGV_A 0x70158 +#define _CUR_WM_SAGV_B 0x71158 +#define _CUR_WM_SAGV_TRANS_A 0x7015C +#define _CUR_WM_SAGV_TRANS_B 0x7115C +#define _CUR_WM_TRANS_A0x70168 +#define _CUR_WM_TRANS_B0x71168 +#define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0) +#define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level))) +#define CUR_WM_SAGV(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_A, _CUR_WM_SAGV_B) +#define CUR_WM_SAGV_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_TRANS_A, _CUR_WM_SAGV_TRANS_B) +#define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A, _CUR_WM_TRANS_B) + +/* skl+ */ +#define _CUR_BUF_CFG_A 0x7017c +#define _CUR_BUF_CFG_B 0x7117c +#define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B) + #endif /* __INTEL_CURSOR_REGS_H__ */ diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h index 7e34470beb74..d0c760e8 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h @@ -402,4 +402,68 @@ (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + \ (index) * 4) +#define _PLANE_WM_1_A_00x70240 +#define _PLANE_WM_1_B_00x71240 +#define _PLANE_WM_2_A_00x70340 +#define _PLANE_WM_2_B_00x71340 +#define _PLANE_WM_SAGV_1_A 0x70258 +#define _PLANE_WM_SAGV_1_B 0x71258 +#define _PLANE_WM_SAGV_2_A 0x70358 +#define _PLANE_WM_SAGV_2_B 0x71358 +#define _PLANE_WM_SAGV_TRANS_1_A 0x7025C +#define _PLANE_WM_SAGV_TRANS_1_B 0x7125C +#define _PLANE_WM_SAGV_TRANS_2_A 0x7035C +#define _PLANE_WM_SAGV_TRANS_2_B 0x7135C +#define _PLANE_WM_TRANS_1_A0x70268 +#define _PLANE_WM_TRANS_1_B0x71268 +#define _PLANE_WM_TRANS_2_A0x70368 +#define _PLANE_WM_TRANS_2_B0x71368 +#define PLANE_WM_EN (1 << 31) +#define PLANE_WM_IGNORE_LINES(1 << 30) +#define PLANE_WM_LINES_MASK REG_GENMASK(26, 14) +#define PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0) + +#define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0) +#define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0) +#define _PLANE_WM_BASE(pipe, plane) \ + _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe)) +#define PLANE_WM(pipe, plane, level) \ + _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level))) +#define _PLANE_WM_SAGV_1(pipe) \ + _PIPE(pipe, _PLANE_WM_SAGV_1_A, _PLANE_WM_SAGV_1_B) +#define _PLANE_WM_SAGV_2(pipe) \ + _PIPE(pipe, _PLANE_WM_SAGV_2_A, _PLANE_WM_SAGV_2_B) +#define PLANE_WM_SAGV(pipe, plane) \ + _MMIO(_PLANE(plane, _PLANE_WM_SAGV_1(pipe), _PLANE_WM_SAGV_2(pipe))) +#define _PLANE_WM_SAGV_TRANS_1(pipe) \ + _PIPE(pipe, _PLANE_WM_SAGV_TRANS_1_A, _PLANE_WM_SAGV_TRANS_1_B) +#define _PLANE_WM_SAGV_TRANS_2(pipe) \ + _PIPE(pipe, _PLANE_WM_SAGV_TRANS_2_A, _PLANE_WM_SAGV_TRANS_2_B) +#define PLANE_WM_SAGV_TRANS(pipe, plane) \ + _MMIO(_PLANE(plane, _PLANE_WM_SAGV_TRANS_1(pipe), _PLANE_WM_SAGV_TRANS_2(pipe))) +#define _PLANE_WM_TRANS_1(pipe) \ + _PIPE(pipe, _PLANE_WM_TRANS_1_A, _PLANE_WM_TRANS_1_B) +#define _PLANE_WM_TRANS_2(pipe) \ + _PIPE(pipe, _PLANE_WM_TRANS_2_A, _PLANE_WM_TRANS_2_B) +#define PLANE_WM_TRANS(pipe, plane) \ + _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe))) + +#define _PLANE_BUF_CFG_1_B 0x7127c +#define _PLANE_BUF_CFG_2_B 0x7137c +#define _PLANE_BUF_CFG_1(pipe) \ + _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B) +#define _PLANE_BUF_CFG_2(pipe) \ + _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B) +#define
[PATCH 03/16] drm/i915: Extract intel_cursor_regs.h
From: Ville Syrjälä Move most cursor register definitions into their own file. Declutters i915_reg.h a bit more. Cc: Zhenyu Wang CC: Zhi Wang Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_cursor.c | 1 + .../gpu/drm/i915/display/intel_cursor_regs.h | 78 +++ drivers/gpu/drm/i915/display/intel_display.c | 1 + drivers/gpu/drm/i915/display/intel_psr.c | 1 + drivers/gpu/drm/i915/gvt/display.c| 1 + drivers/gpu/drm/i915/gvt/fb_decoder.c | 1 + drivers/gpu/drm/i915/i915_reg.h | 70 - drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 1 + 8 files changed, 84 insertions(+), 70 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_cursor_regs.h diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c index 2118b87ccb10..d2b459634732 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor.c +++ b/drivers/gpu/drm/i915/display/intel_cursor.c @@ -14,6 +14,7 @@ #include "intel_atomic.h" #include "intel_atomic_plane.h" #include "intel_cursor.h" +#include "intel_cursor_regs.h" #include "intel_de.h" #include "intel_display.h" #include "intel_display_types.h" diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h b/drivers/gpu/drm/i915/display/intel_cursor_regs.h new file mode 100644 index ..62f7fb5c3f10 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2024 Intel Corporation + */ + +#ifndef __INTEL_CURSOR_REGS_H__ +#define __INTEL_CURSOR_REGS_H__ + +#include "intel_display_reg_defs.h" + +#define _CURACNTR 0x70080 +/* Old style CUR*CNTR flags (desktop 8xx) */ +#define CURSOR_ENABLEREG_BIT(31) +#define CURSOR_PIPE_GAMMA_ENABLE REG_BIT(30) +#define CURSOR_STRIDE_MASK REG_GENMASK(29, 28) +#define CURSOR_STRIDE(stride)REG_FIELD_PREP(CURSOR_STRIDE_MASK, ffs(stride) - 9) /* 256,512,1k,2k */ +#define CURSOR_FORMAT_MASK REG_GENMASK(26, 24) +#define CURSOR_FORMAT_2C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 0) +#define CURSOR_FORMAT_3C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 1) +#define CURSOR_FORMAT_4C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 2) +#define CURSOR_FORMAT_ARGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 4) +#define CURSOR_FORMAT_XRGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 5) +/* New style CUR*CNTR flags */ +#define MCURSOR_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */ +#define MCURSOR_ARB_SLOTS(x) REG_FIELD_PREP(MCURSOR_ARB_SLOTS_MASK, (x)) /* icl+ */ +#define MCURSOR_PIPE_SEL_MASKREG_GENMASK(29, 28) +#define MCURSOR_PIPE_SEL(pipe) REG_FIELD_PREP(MCURSOR_PIPE_SEL_MASK, (pipe)) +#define MCURSOR_PIPE_GAMMA_ENABLEREG_BIT(26) +#define MCURSOR_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */ +#define MCURSOR_ROTATE_180 REG_BIT(15) +#define MCURSOR_TRICKLE_FEED_DISABLE REG_BIT(14) +#define MCURSOR_MODE_MASK0x27 +#define MCURSOR_MODE_DISABLE 0x00 +#define MCURSOR_MODE_128_32B_AX 0x02 +#define MCURSOR_MODE_256_32B_AX 0x03 +#define MCURSOR_MODE_64_2B 0x04 +#define MCURSOR_MODE_64_32B_AX 0x07 +#define MCURSOR_MODE_128_ARGB_AX (0x20 | MCURSOR_MODE_128_32B_AX) +#define MCURSOR_MODE_256_ARGB_AX (0x20 | MCURSOR_MODE_256_32B_AX) +#define MCURSOR_MODE_64_ARGB_AX (0x20 | MCURSOR_MODE_64_32B_AX) +#define _CURABASE 0x70084 +#define _CURAPOS 0x70088 +#define _CURAPOS_ERLY_TPT 0x7008c +#define CURSOR_POS_Y_SIGNREG_BIT(31) +#define CURSOR_POS_Y_MASKREG_GENMASK(30, 16) +#define CURSOR_POS_Y(y) REG_FIELD_PREP(CURSOR_POS_Y_MASK, (y)) +#define CURSOR_POS_X_SIGNREG_BIT(15) +#define CURSOR_POS_X_MASKREG_GENMASK(14, 0) +#define CURSOR_POS_X(x) REG_FIELD_PREP(CURSOR_POS_X_MASK, (x)) +#define _CURASIZE 0x700a0 /* 845/865 */ +#define CURSOR_HEIGHT_MASK REG_GENMASK(21, 12) +#define CURSOR_HEIGHT(h) REG_FIELD_PREP(CURSOR_HEIGHT_MASK, (h)) +#define CURSOR_WIDTH_MASKREG_GENMASK(9, 0) +#define CURSOR_WIDTH(w) REG_FIELD_PREP(CURSOR_WIDTH_MASK, (w)) +#define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */ +#define CUR_FBC_EN REG_BIT(31) +#define CUR_FBC_HEIGHT_MASK REG_GENMASK(7, 0) +#define CUR_FBC_HEIGHT(h)REG_FIELD_PREP(CUR_FBC_HEIGHT_MASK, (h)) +#define _CUR_CHICKEN_A 0x700a4 /* mtl+ */ +#define _CURASURFLIVE 0x700ac /* g4x+ */ +#define _CURBCNTR 0x700c0 +#define _CURBBASE 0x700c4 +#define _CURBPOS 0x700c8 + +#define _CURBCNTR_IVB 0x71080 +#define _CURBBASE_IVB 0x71084 +#define _CURBPOS_IVB 0x71088 + +#define CURCNTR(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURACNTR)
[PATCH 02/16] drm/i915: Extract skl_universal_plane_regs.h
From: Ville Syrjälä
Move most of the SKL+ universal plane register definitions
into their own file. Declutters i915_reg.h a bit more.
Cc: Zhenyu Wang
CC: Zhi Wang
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 1 +
.../gpu/drm/i915/display/intel_dpt_common.c | 1 +
.../drm/i915/display/skl_universal_plane.c| 1 +
.../i915/display/skl_universal_plane_regs.h | 405 ++
drivers/gpu/drm/i915/display/skl_watermark.c | 1 +
drivers/gpu/drm/i915/gvt/dmabuf.c | 3 +-
drivers/gpu/drm/i915/gvt/fb_decoder.c | 1 +
drivers/gpu/drm/i915/gvt/handlers.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 395 -
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 1 +
10 files changed, 414 insertions(+), 396 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index ef986b508431..a2c331c696fe 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -119,6 +119,7 @@
#include "intel_wm.h"
#include "skl_scaler.h"
#include "skl_universal_plane.h"
+#include "skl_universal_plane_regs.h"
#include "skl_watermark.h"
#include "vlv_dpio_phy_regs.h"
#include "vlv_dsi.h"
diff --git a/drivers/gpu/drm/i915/display/intel_dpt_common.c
b/drivers/gpu/drm/i915/display/intel_dpt_common.c
index cdba47165c04..573f72068899 100644
--- a/drivers/gpu/drm/i915/display/intel_dpt_common.c
+++ b/drivers/gpu/drm/i915/display/intel_dpt_common.c
@@ -7,6 +7,7 @@
#include "intel_de.h"
#include "intel_display_types.h"
#include "intel_dpt_common.h"
+#include "skl_universal_plane_regs.h"
void intel_dpt_configure(struct intel_crtc *crtc)
{
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 0a8e781a3648..ab560820bb23 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -21,6 +21,7 @@
#include "intel_psr_regs.h"
#include "skl_scaler.h"
#include "skl_universal_plane.h"
+#include "skl_universal_plane_regs.h"
#include "skl_watermark.h"
#include "pxp/intel_pxp.h"
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
new file mode 100644
index ..7e34470beb74
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
@@ -0,0 +1,405 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2024 Intel Corporation
+ */
+
+#ifndef __SKL_UNIVERSAL_PLANE_REGS_H__
+#define __SKL_UNIVERSAL_PLANE_REGS_H__
+
+#include "intel_display_reg_defs.h"
+
+#define _PLANE_CTL_1_A 0x70180
+#define _PLANE_CTL_2_A 0x70280
+#define _PLANE_CTL_3_A 0x70380
+#define PLANE_CTL_ENABLE REG_BIT(31)
+#define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */
+#define PLANE_CTL_ARB_SLOTS(x)
REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */
+#define PLANE_CTL_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-GLK */
+#define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
+/*
+ * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition
+ * expanded to include bit 23 as well. However, the shift-24 based values
+ * correctly map to the same formats in ICL, as long as bit 23 is set to 0
+ */
+#define PLANE_CTL_FORMAT_MASK_SKLREG_GENMASK(27, 24) /* pre-icl
*/
+#define PLANE_CTL_FORMAT_MASK_ICLREG_GENMASK(27, 23) /* icl+ */
+#define PLANE_CTL_FORMAT_YUV422
REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 0)
+#define PLANE_CTL_FORMAT_NV12
REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 1)
+#define PLANE_CTL_FORMAT_XRGB_2101010
REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 2)
+#define PLANE_CTL_FORMAT_P010
REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 3)
+#define PLANE_CTL_FORMAT_XRGB_
REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 4)
+#define PLANE_CTL_FORMAT_P012
REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 5)
+#define PLANE_CTL_FORMAT_XRGB_16161616F
REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 6)
+#define PLANE_CTL_FORMAT_P016
REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 7)
+#define PLANE_CTL_FORMAT_XYUV
REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 8)
+#define PLANE_CTL_FORMAT_INDEXED
REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 12)
+#define PLANE_CTL_FORMAT_RGB_565
REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 14)
+#define PLANE_CTL_FORMAT_Y210
REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 1)
+#define PLANE_CTL_FORMAT_Y212
[PATCH 01/16] drm/i915: Nuke _MMIO_PLANE_GAMC()
From: Ville Syrjälä
_MMIO_PLANE_GAMC() is some leftover macro that is never used.
Get rid of it.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 256d73c25701..0f4a2d542d81 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5151,8 +5151,6 @@ enum skl_power_gate {
#define WM_DBG_DISALLOW_MAXFIFO (1 << 1)
#define WM_DBG_DISALLOW_SPRITE(1 << 2)
-#define _MMIO_PLANE_GAMC(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) * 4)
-
/* Plane CSC Registers */
#define _PLANE_CSC_RY_GY_1_A 0x70210
#define _PLANE_CSC_RY_GY_2_A 0x70310
--
2.43.2
[PATCH 00/16] drm/i915: skl+ plane register stuff
From: Ville Syrjälä
Bunch of refactoring around skl+ plane registers.
Ville Syrjälä (16):
drm/i915: Nuke _MMIO_PLANE_GAMC()
drm/i915: Extract skl_universal_plane_regs.h
drm/i915: Extract intel_cursor_regs.h
drm/i915: Move skl+ wm/ddb registers to proper headers
drm/i915/gvt: Use the proper PLANE_AUX_DIST() define
drm/i915/gvt: Use the proper PLANE_AUX_OFFSET() define
drm/i915/gvt: Use the full PLANE_KEY*() defines
drm/i915/gvt: Use PLANE_CTL and PLANE_SURF defines
drm/i915: Drop useless PLANE_FOO_3 register defines
drm/i915: Shuffle the skl+ plane register definitions
drm/i915: Use REG_BIT for PLANE_WM bits
drm/i915: Drop a few unwanted tabs from skl+ plane reg defines
drm/i915: Refactor skl+ plane register offset calculations
drm/i915: Extract skl_plane_{wm,ddb}_reg_val()
drm/i915: Nuke skl_write_wm_level() and skl_ddb_entry_write()
drm/i915: Handle SKL+ WM/DDB registers next to all other plane
registers
drivers/gpu/drm/i915/display/intel_cursor.c | 33 ++
.../gpu/drm/i915/display/intel_cursor_regs.h | 98
drivers/gpu/drm/i915/display/intel_display.c | 2 +
.../gpu/drm/i915/display/intel_dpt_common.c | 1 +
drivers/gpu/drm/i915/display/intel_psr.c | 1 +
.../drm/i915/display/skl_universal_plane.c| 61 +++
.../drm/i915/display/skl_universal_plane.h| 5 +
.../i915/display/skl_universal_plane_regs.h | 369 ++
drivers/gpu/drm/i915/display/skl_watermark.c | 101 +---
drivers/gpu/drm/i915/display/skl_watermark.h | 13 +-
.../gpu/drm/i915/display/skl_watermark_regs.h | 83
drivers/gpu/drm/i915/gvt/display.c| 1 +
drivers/gpu/drm/i915/gvt/dmabuf.c | 3 +-
drivers/gpu/drm/i915/gvt/fb_decoder.c | 2 +
drivers/gpu/drm/i915/gvt/handlers.c | 50 +-
drivers/gpu/drm/i915/gvt/reg.h| 3 -
drivers/gpu/drm/i915/i915_reg.h | 467 --
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 80 +--
18 files changed, 654 insertions(+), 719 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_cursor_regs.h
create mode 100644 drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
--
2.43.2
[RESEND 6/6] drm/connector: update edid_blob_ptr documentation
Accessing the EDID via edid_blob_ptr causes chicken-and-egg
problems. Keep edid_blob_ptr as the userspace interface that should be
accessed via dedicated functions.
Signed-off-by: Jani Nikula
---
include/drm/drm_connector.h | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index fe88d7fc6b8f..58ee9adf9091 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -1636,8 +1636,12 @@ struct drm_connector {
/**
* @edid_blob_ptr: DRM property containing EDID if present. Protected by
-* _mode_config.mutex. This should be updated only by calling
+* _mode_config.mutex.
+*
+* This must be updated only by calling drm_edid_connector_update() or
* drm_connector_update_edid_property().
+*
+* This must not be used by drivers directly.
*/
struct drm_property_blob *edid_blob_ptr;
--
2.39.2
[RESEND 5/6] drm/edid: add a helper for EDID sysfs property show
Add a helper to get the EDID property for sysfs property show. This
hides all the edid_blob_ptr usage within drm_edid.c.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_crtc_internal.h | 2 ++
drivers/gpu/drm/drm_edid.c | 33 +
drivers/gpu/drm/drm_sysfs.c | 24 ++---
3 files changed, 37 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/drm_crtc_internal.h
b/drivers/gpu/drm/drm_crtc_internal.h
index 25aaae937ceb..20e9d7b206a2 100644
--- a/drivers/gpu/drm/drm_crtc_internal.h
+++ b/drivers/gpu/drm/drm_crtc_internal.h
@@ -303,6 +303,8 @@ const u8 *drm_edid_find_extension(const struct drm_edid
*drm_edid,
int ext_id, int *ext_index);
void drm_edid_cta_sad_get(const struct cea_sad *cta_sad, u8 *sad);
void drm_edid_cta_sad_set(struct cea_sad *cta_sad, const u8 *sad);
+ssize_t drm_edid_connector_property_show(struct drm_connector *connector,
+char *buf, loff_t off, size_t count);
/* drm_edid_load.c */
#ifdef CONFIG_DRM_LOAD_EDID_FIRMWARE
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 4f54c91b31b2..97362dd2330b 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -6969,6 +6969,39 @@ static int _drm_edid_connector_property_update(struct
drm_connector *connector,
return ret;
}
+/* For sysfs edid show implementation */
+ssize_t drm_edid_connector_property_show(struct drm_connector *connector,
+char *buf, loff_t off, size_t count)
+{
+ const void *edid;
+ size_t size;
+ ssize_t ret = 0;
+
+ mutex_lock(>dev->mode_config.mutex);
+
+ if (!connector->edid_blob_ptr)
+ goto unlock;
+
+ edid = connector->edid_blob_ptr->data;
+ size = connector->edid_blob_ptr->length;
+ if (!edid)
+ goto unlock;
+
+ if (off >= size)
+ goto unlock;
+
+ if (off + count > size)
+ count = size - off;
+
+ memcpy(buf, edid + off, count);
+
+ ret = count;
+unlock:
+ mutex_unlock(>dev->mode_config.mutex);
+
+ return ret;
+}
+
/**
* drm_edid_connector_update - Update connector information from EDID
* @connector: Connector
diff --git a/drivers/gpu/drm/drm_sysfs.c b/drivers/gpu/drm/drm_sysfs.c
index bd9b8ab4f82b..fb3bbb6adcd1 100644
--- a/drivers/gpu/drm/drm_sysfs.c
+++ b/drivers/gpu/drm/drm_sysfs.c
@@ -266,29 +266,9 @@ static ssize_t edid_show(struct file *filp, struct kobject
*kobj,
{
struct device *connector_dev = kobj_to_dev(kobj);
struct drm_connector *connector = to_drm_connector(connector_dev);
- unsigned char *edid;
- size_t size;
- ssize_t ret = 0;
+ ssize_t ret;
- mutex_lock(>dev->mode_config.mutex);
- if (!connector->edid_blob_ptr)
- goto unlock;
-
- edid = connector->edid_blob_ptr->data;
- size = connector->edid_blob_ptr->length;
- if (!edid)
- goto unlock;
-
- if (off >= size)
- goto unlock;
-
- if (off + count > size)
- count = size - off;
- memcpy(buf, edid + off, count);
-
- ret = count;
-unlock:
- mutex_unlock(>dev->mode_config.mutex);
+ ret = drm_edid_connector_property_show(connector, buf, off, count);
return ret;
}
--
2.39.2
[RESEND 4/6] drm/amdgpu: remove amdgpu_connector_edid() and stop using edid_blob_ptr
amdgpu_connector_edid() copies the EDID from edid_blob_ptr as a side
effect if amdgpu_connector->edid isn't initialized. However, everywhere
that the returned EDID is used, the EDID should have been set
beforehands.
Only the drm EDID code should look at the EDID property, anyway, so stop
using it.
Cc: Alex Deucher
Cc: Christian König
Cc: Pan, Xinhui
Cc: amd-...@lists.freedesktop.org
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c | 16
drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.h | 1 -
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 4 ++--
6 files changed, 8 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
index 9caba10315a8..cae7479c3ecf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
@@ -246,22 +246,6 @@ amdgpu_connector_find_encoder(struct drm_connector
*connector,
return NULL;
}
-struct edid *amdgpu_connector_edid(struct drm_connector *connector)
-{
- struct amdgpu_connector *amdgpu_connector =
to_amdgpu_connector(connector);
- struct drm_property_blob *edid_blob = connector->edid_blob_ptr;
-
- if (amdgpu_connector->edid) {
- return amdgpu_connector->edid;
- } else if (edid_blob) {
- struct edid *edid = kmemdup(edid_blob->data, edid_blob->length,
GFP_KERNEL);
-
- if (edid)
- amdgpu_connector->edid = edid;
- }
- return amdgpu_connector->edid;
-}
-
static struct edid *
amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev)
{
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.h
index 61fcef15ad72..eff833b6ed31 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.h
@@ -24,7 +24,6 @@
#ifndef __AMDGPU_CONNECTORS_H__
#define __AMDGPU_CONNECTORS_H__
-struct edid *amdgpu_connector_edid(struct drm_connector *connector);
void amdgpu_connector_hotplug(struct drm_connector *connector);
int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector);
u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector
*connector);
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index b44fce44c066..dddb5fe16f2c 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -1299,7 +1299,7 @@ static void
dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder
return;
}
- sad_count =
drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), );
+ sad_count = drm_edid_to_speaker_allocation(amdgpu_connector->edid,
);
if (sad_count < 0) {
DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n",
sad_count);
sad_count = 0;
@@ -1369,7 +1369,7 @@ static void dce_v10_0_audio_write_sad_regs(struct
drm_encoder *encoder)
return;
}
- sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), );
+ sad_count = drm_edid_to_sad(amdgpu_connector->edid, );
if (sad_count < 0)
DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
if (sad_count <= 0)
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index 80b2e7f79acf..11780e4d7e9f 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -1331,7 +1331,7 @@ static void
dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder
return;
}
- sad_count =
drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), );
+ sad_count = drm_edid_to_speaker_allocation(amdgpu_connector->edid,
);
if (sad_count < 0) {
DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n",
sad_count);
sad_count = 0;
@@ -1401,7 +1401,7 @@ static void dce_v11_0_audio_write_sad_regs(struct
drm_encoder *encoder)
return;
}
- sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), );
+ sad_count = drm_edid_to_sad(amdgpu_connector->edid, );
if (sad_count < 0)
DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
if (sad_count <= 0)
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index db20012600f5..05c0df97f01d 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -1217,7 +1217,7 @@ static void
dce_v6_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
return;
[RESEND 3/6] drm/radeon: remove radeon_connector_edid() and stop using edid_blob_ptr
radeon_connector_edid() copies the EDID from edid_blob_ptr as a side
effect if radeon_connector->edid isn't initialized. However, everywhere
that the returned EDID is used, the EDID should have been set
beforehands.
Only the drm EDID code should look at the EDID property, anyway, so stop
using it.
Cc: Alex Deucher
Cc: Christian König
Cc: Pan, Xinhui
Cc: amd-...@lists.freedesktop.org
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/radeon/radeon_audio.c | 7 ---
drivers/gpu/drm/radeon/radeon_connectors.c | 15 ---
drivers/gpu/drm/radeon/radeon_mode.h | 2 --
3 files changed, 4 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_audio.c
b/drivers/gpu/drm/radeon/radeon_audio.c
index 16c10db3ce6f..0bcd767b9f47 100644
--- a/drivers/gpu/drm/radeon/radeon_audio.c
+++ b/drivers/gpu/drm/radeon/radeon_audio.c
@@ -303,6 +303,7 @@ void radeon_audio_endpoint_wreg(struct radeon_device *rdev,
u32 offset,
static void radeon_audio_write_sad_regs(struct drm_encoder *encoder)
{
struct drm_connector *connector =
radeon_get_connector_for_encoder(encoder);
+ struct radeon_connector *radeon_connector =
to_radeon_connector(connector);
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
struct cea_sad *sads;
int sad_count;
@@ -310,7 +311,7 @@ static void radeon_audio_write_sad_regs(struct drm_encoder
*encoder)
if (!connector)
return;
- sad_count = drm_edid_to_sad(radeon_connector_edid(connector), );
+ sad_count = drm_edid_to_sad(radeon_connector->edid, );
if (sad_count < 0)
DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
if (sad_count <= 0)
@@ -326,6 +327,7 @@ static void radeon_audio_write_sad_regs(struct drm_encoder
*encoder)
static void radeon_audio_write_speaker_allocation(struct drm_encoder *encoder)
{
struct drm_connector *connector =
radeon_get_connector_for_encoder(encoder);
+ struct radeon_connector *radeon_connector =
to_radeon_connector(connector);
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
u8 *sadb = NULL;
int sad_count;
@@ -333,8 +335,7 @@ static void radeon_audio_write_speaker_allocation(struct
drm_encoder *encoder)
if (!connector)
return;
- sad_count =
drm_edid_to_speaker_allocation(radeon_connector_edid(connector),
- );
+ sad_count = drm_edid_to_speaker_allocation(radeon_connector->edid,
);
if (sad_count < 0) {
DRM_DEBUG("Couldn't read Speaker Allocation Data Block: %d\n",
sad_count);
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c
b/drivers/gpu/drm/radeon/radeon_connectors.c
index 81b5c3c8f658..80879e946342 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -255,21 +255,6 @@ static struct drm_encoder *radeon_find_encoder(struct
drm_connector *connector,
return NULL;
}
-struct edid *radeon_connector_edid(struct drm_connector *connector)
-{
- struct radeon_connector *radeon_connector =
to_radeon_connector(connector);
- struct drm_property_blob *edid_blob = connector->edid_blob_ptr;
-
- if (radeon_connector->edid) {
- return radeon_connector->edid;
- } else if (edid_blob) {
- struct edid *edid = kmemdup(edid_blob->data, edid_blob->length,
GFP_KERNEL);
- if (edid)
- radeon_connector->edid = edid;
- }
- return radeon_connector->edid;
-}
-
static void radeon_connector_get_edid(struct drm_connector *connector)
{
struct drm_device *dev = connector->dev;
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h
b/drivers/gpu/drm/radeon/radeon_mode.h
index 546381a5c918..e0a5af180801 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -701,8 +701,6 @@ extern u16
radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connecto
extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector);
extern int radeon_get_monitor_bpc(struct drm_connector *connector);
-extern struct edid *radeon_connector_edid(struct drm_connector *connector);
-
extern void radeon_connector_hotplug(struct drm_connector *connector);
extern int radeon_dp_mode_valid_helper(struct drm_connector *connector,
struct drm_display_mode *mode);
--
2.39.2
[RESEND 2/6] drm/radeon: convert to using is_hdmi and has_audio from display info
Prefer the parsed results for is_hdmi and has_audio in display info over
calling drm_detect_hdmi_monitor() and drm_detect_monitor_audio(),
respectively.
Cc: Alex Deucher
Cc: Christian König
Cc: Pan, Xinhui
Cc: amd-...@lists.freedesktop.org
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/radeon/atombios_encoders.c | 10 +-
drivers/gpu/drm/radeon/evergreen_hdmi.c| 5 ++---
drivers/gpu/drm/radeon/radeon_audio.c | 6 +++---
drivers/gpu/drm/radeon/radeon_connectors.c | 12 ++--
drivers/gpu/drm/radeon/radeon_display.c| 2 +-
drivers/gpu/drm/radeon/radeon_encoders.c | 4 ++--
6 files changed, 19 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c
b/drivers/gpu/drm/radeon/atombios_encoders.c
index 2bff0d9e20f5..0aa395fac36f 100644
--- a/drivers/gpu/drm/radeon/atombios_encoders.c
+++ b/drivers/gpu/drm/radeon/atombios_encoders.c
@@ -701,7 +701,7 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
if (radeon_connector->use_digital &&
(radeon_connector->audio == RADEON_AUDIO_ENABLE))
return ATOM_ENCODER_MODE_HDMI;
- else if
(drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
+ else if (connector->display_info.is_hdmi &&
(radeon_connector->audio == RADEON_AUDIO_AUTO))
return ATOM_ENCODER_MODE_HDMI;
else if (radeon_connector->use_digital)
@@ -720,7 +720,7 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
if (radeon_audio != 0) {
if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
return ATOM_ENCODER_MODE_HDMI;
- else if
(drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
+ else if (connector->display_info.is_hdmi &&
(radeon_connector->audio == RADEON_AUDIO_AUTO))
return ATOM_ENCODER_MODE_HDMI;
else
@@ -737,14 +737,14 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
if ((dig_connector->dp_sink_type ==
CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
(dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
if (radeon_audio != 0 &&
-
drm_detect_monitor_audio(radeon_connector_edid(connector)) &&
+ connector->display_info.has_audio &&
ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
return ATOM_ENCODER_MODE_DP_AUDIO;
return ATOM_ENCODER_MODE_DP;
} else if (radeon_audio != 0) {
if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
return ATOM_ENCODER_MODE_HDMI;
- else if
(drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
+ else if (connector->display_info.is_hdmi &&
(radeon_connector->audio == RADEON_AUDIO_AUTO))
return ATOM_ENCODER_MODE_HDMI;
else
@@ -755,7 +755,7 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
break;
case DRM_MODE_CONNECTOR_eDP:
if (radeon_audio != 0 &&
- drm_detect_monitor_audio(radeon_connector_edid(connector))
&&
+ connector->display_info.has_audio &&
ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
return ATOM_ENCODER_MODE_DP_AUDIO;
return ATOM_ENCODER_MODE_DP;
diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c
b/drivers/gpu/drm/radeon/evergreen_hdmi.c
index 681119c91d94..09dda114e218 100644
--- a/drivers/gpu/drm/radeon/evergreen_hdmi.c
+++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c
@@ -412,7 +412,7 @@ void evergreen_hdmi_enable(struct drm_encoder *encoder,
bool enable)
if (enable) {
struct drm_connector *connector =
radeon_get_connector_for_encoder(encoder);
- if (connector &&
drm_detect_monitor_audio(radeon_connector_edid(connector))) {
+ if (connector && connector->display_info.has_audio) {
WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset,
HDMI_AVI_INFO_SEND | /* enable AVI info frames */
HDMI_AVI_INFO_CONT | /* required for audio info
values to be updated */
@@ -450,8 +450,7 @@ void evergreen_dp_enable(struct drm_encoder *encoder, bool
enable)
if (!dig || !dig->afmt)
return;
- if (enable && connector &&
- drm_detect_monitor_audio(radeon_connector_edid(connector))) {
+ if (enable && connector && connector->display_info.has_audio) {
[RESEND 1/6] drm/nouveau: convert to using is_hdmi and has_audio from display info
Prefer the parsed results for is_hdmi and has_audio in display info over
calling drm_detect_hdmi_monitor() and drm_detect_monitor_audio(),
respectively.
Conveniently, this also removes the need to use edid_blob_ptr.
v2: Reverse a backwards if condition (Ilia)
Cc: Karol Herbst
Cc: Lyude Paul
Cc: Danilo Krummrich
Cc: nouv...@lists.freedesktop.org
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/nouveau/dispnv50/disp.c | 8
drivers/gpu/drm/nouveau/dispnv50/head.c | 8 +---
drivers/gpu/drm/nouveau/nouveau_connector.c | 2 +-
3 files changed, 6 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c
b/drivers/gpu/drm/nouveau/dispnv50/disp.c
index 0c3d88ad0b0e..168c27213287 100644
--- a/drivers/gpu/drm/nouveau/dispnv50/disp.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c
@@ -751,7 +751,7 @@ nv50_audio_enable(struct drm_encoder *encoder, struct
nouveau_crtc *nv_crtc,
struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
struct nvif_outp *outp = _encoder->outp;
- if (!nv50_audio_supported(encoder) ||
!drm_detect_monitor_audio(nv_connector->edid))
+ if (!nv50_audio_supported(encoder) ||
!nv_connector->base.display_info.has_audio)
return;
mutex_lock(>audio.lock);
@@ -1765,7 +1765,7 @@ nv50_sor_atomic_enable(struct drm_encoder *encoder,
struct drm_atomic_state *sta
if ((disp->disp->object.oclass == GT214_DISP ||
disp->disp->object.oclass >= GF110_DISP) &&
nv_encoder->dcb->type != DCB_OUTPUT_LVDS &&
- drm_detect_monitor_audio(nv_connector->edid))
+ nv_connector->base.display_info.has_audio)
hda = true;
if (!nvif_outp_acquired(outp))
@@ -1774,7 +1774,7 @@ nv50_sor_atomic_enable(struct drm_encoder *encoder,
struct drm_atomic_state *sta
switch (nv_encoder->dcb->type) {
case DCB_OUTPUT_TMDS:
if (disp->disp->object.oclass != NV50_DISP &&
- drm_detect_hdmi_monitor(nv_connector->edid))
+ nv_connector->base.display_info.is_hdmi)
nv50_hdmi_enable(encoder, nv_crtc, nv_connector, state,
mode, hda);
if (nv_encoder->outp.or.link & 1) {
@@ -1787,7 +1787,7 @@ nv50_sor_atomic_enable(struct drm_encoder *encoder,
struct drm_atomic_state *sta
*/
if (mode->clock >= 165000 &&
nv_encoder->dcb->duallink_possible &&
- !drm_detect_hdmi_monitor(nv_connector->edid))
+ !nv_connector->base.display_info.is_hdmi)
proto =
NV507D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS;
} else {
proto = NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B;
diff --git a/drivers/gpu/drm/nouveau/dispnv50/head.c
b/drivers/gpu/drm/nouveau/dispnv50/head.c
index 83355dbc15ee..d7c74cc43ba5 100644
--- a/drivers/gpu/drm/nouveau/dispnv50/head.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/head.c
@@ -127,14 +127,8 @@ nv50_head_atomic_check_view(struct nv50_head_atom *armh,
struct drm_display_mode *omode = >state.adjusted_mode;
struct drm_display_mode *umode = >state.mode;
int mode = asyc->scaler.mode;
- struct edid *edid;
int umode_vdisplay, omode_hdisplay, omode_vdisplay;
- if (connector->edid_blob_ptr)
- edid = (struct edid *)connector->edid_blob_ptr->data;
- else
- edid = NULL;
-
if (!asyc->scaler.full) {
if (mode == DRM_MODE_SCALE_NONE)
omode = umode;
@@ -162,7 +156,7 @@ nv50_head_atomic_check_view(struct nv50_head_atom *armh,
*/
if ((asyc->scaler.underscan.mode == UNDERSCAN_ON ||
(asyc->scaler.underscan.mode == UNDERSCAN_AUTO &&
-drm_detect_hdmi_monitor(edid {
+connector->display_info.is_hdmi))) {
u32 bX = asyc->scaler.underscan.hborder;
u32 bY = asyc->scaler.underscan.vborder;
u32 r = (asyh->view.oH << 19) / asyh->view.oW;
diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c
b/drivers/gpu/drm/nouveau/nouveau_connector.c
index 856b3ef5edb8..938832a6af15 100644
--- a/drivers/gpu/drm/nouveau/nouveau_connector.c
+++ b/drivers/gpu/drm/nouveau/nouveau_connector.c
@@ -1034,7 +1034,7 @@ get_tmds_link_bandwidth(struct drm_connector *connector)
unsigned duallink_scale =
nouveau_duallink && nv_encoder->dcb->duallink_possible ? 2 : 1;
- if (drm_detect_hdmi_monitor(nv_connector->edid)) {
+ if (nv_connector->base.display_info.is_hdmi) {
info = _connector->base.display_info;
duallink_scale = 1;
}
--
2.39.2
[RESEND 0/6] drm, nouveau/radeon/amdpgu: edid_blob_ptr cleanups
I've sent this some moths ago, let's try again... BR, Jani. Jani Nikula (6): drm/nouveau: convert to using is_hdmi and has_audio from display info drm/radeon: convert to using is_hdmi and has_audio from display info drm/radeon: remove radeon_connector_edid() and stop using edid_blob_ptr drm/amdgpu: remove amdgpu_connector_edid() and stop using edid_blob_ptr drm/edid: add a helper for EDID sysfs property show drm/connector: update edid_blob_ptr documentation .../gpu/drm/amd/amdgpu/amdgpu_connectors.c| 16 - .../gpu/drm/amd/amdgpu/amdgpu_connectors.h| 1 - drivers/gpu/drm/amd/amdgpu/dce_v10_0.c| 4 +-- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c| 4 +-- drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 4 +-- drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 4 +-- drivers/gpu/drm/drm_crtc_internal.h | 2 ++ drivers/gpu/drm/drm_edid.c| 33 +++ drivers/gpu/drm/drm_sysfs.c | 24 ++ drivers/gpu/drm/nouveau/dispnv50/disp.c | 8 ++--- drivers/gpu/drm/nouveau/dispnv50/head.c | 8 + drivers/gpu/drm/nouveau/nouveau_connector.c | 2 +- drivers/gpu/drm/radeon/atombios_encoders.c| 10 +++--- drivers/gpu/drm/radeon/evergreen_hdmi.c | 5 ++- drivers/gpu/drm/radeon/radeon_audio.c | 13 drivers/gpu/drm/radeon/radeon_connectors.c| 27 --- drivers/gpu/drm/radeon/radeon_display.c | 2 +- drivers/gpu/drm/radeon/radeon_encoders.c | 4 +-- drivers/gpu/drm/radeon/radeon_mode.h | 2 -- include/drm/drm_connector.h | 6 +++- 20 files changed, 79 insertions(+), 100 deletions(-) -- 2.39.2
Re: PR for BMG DMC v2.06
Merged and pushed out. https://gitlab.com/kernel-firmware/linux-firmware/-/merge_requests/210 josh On Thu, May 9, 2024 at 1:47 PM Gustavo Sousa wrote: > > The following changes since commit 93f329774542b9b7d57abb18ea8b6542f2d8feac: > > Merge branch 'robot/pr-0-1709214990' into 'main' (2024-02-29 14:10:53 +) > > are available in the Git repository at: > > https://gitlab.freedesktop.org/drm/firmware.git tags/intel-2024-05-09 > > for you to fetch changes up to 8724b227b8999e11cf89601fec9f6f80795d8fa8: > > i915: Add BMG DMC v2.06 (2024-05-09 15:10:44 -0300) > > > Intel DRM firmware intel-2024-05-09 > > > Daniele Ceraolo Spurio (1): > i915: Add DG2 HuC 7.10.15 > > Dnyaneshwar Bhadane (1): > i915: Update Xe2LPD DMC to v2.20 > > Gustavo Sousa (1): > i915: Add BMG DMC v2.06 > > WHENCE | 7 +-- > i915/bmg_dmc.bin | Bin 0 -> 45964 bytes > i915/dg2_huc_gsc.bin | Bin 622592 -> 630784 bytes > i915/xe2lpd_dmc.bin | Bin 61208 -> 59284 bytes > 4 files changed, 5 insertions(+), 2 deletions(-) > create mode 100644 i915/bmg_dmc.bin > mode change 100755 => 100644 i915/dg2_huc_gsc.bin
✓ Fi.CI.BAT: success for drm/i915/bmg: Load DMC
== Series Details == Series: drm/i915/bmg: Load DMC URL : https://patchwork.freedesktop.org/series/133452/ State : success == Summary == CI Bug Log - changes from CI_DRM_14747 -> Patchwork_133452v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133452v1/index.html Participating hosts (42 -> 40) -- Additional (3): fi-glk-j4005 bat-mtlp-8 fi-kbl-8809g Missing(5): fi-kbl-7567u fi-snb-2520m fi-elk-e7500 bat-dg2-11 bat-arls-3 Known issues Here are the changes found in Patchwork_133452v1 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-mtlp-8: NOTRUN -> [SKIP][1] ([i915#9318]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133452v1/bat-mtlp-8/igt@debugfs_t...@basic-hwmon.html * igt@gem_huc_copy@huc-copy: - fi-kbl-8809g: NOTRUN -> [SKIP][2] ([i915#2190]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133452v1/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html - fi-glk-j4005: NOTRUN -> [SKIP][3] ([i915#2190]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133452v1/fi-glk-j4005/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-glk-j4005: NOTRUN -> [SKIP][4] ([i915#4613]) +3 other tests skip [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133452v1/fi-glk-j4005/igt@gem_lmem_swapp...@basic.html - fi-kbl-8809g: NOTRUN -> [SKIP][5] ([i915#4613]) +3 other tests skip [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133452v1/fi-kbl-8809g/igt@gem_lmem_swapp...@basic.html * igt@gem_lmem_swapping@verify-random: - bat-mtlp-8: NOTRUN -> [SKIP][6] ([i915#4613]) +3 other tests skip [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133452v1/bat-mtlp-8/igt@gem_lmem_swapp...@verify-random.html * igt@gem_mmap@basic: - bat-mtlp-8: NOTRUN -> [SKIP][7] ([i915#4083]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133452v1/bat-mtlp-8/igt@gem_m...@basic.html * igt@gem_mmap_gtt@basic: - bat-mtlp-8: NOTRUN -> [SKIP][8] ([i915#4077]) +2 other tests skip [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133452v1/bat-mtlp-8/igt@gem_mmap_...@basic.html * igt@gem_render_tiled_blits@basic: - bat-mtlp-8: NOTRUN -> [SKIP][9] ([i915#4079]) +1 other test skip [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133452v1/bat-mtlp-8/igt@gem_render_tiled_bl...@basic.html * igt@i915_pm_rps@basic-api: - bat-mtlp-8: NOTRUN -> [SKIP][10] ([i915#6621]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133452v1/bat-mtlp-8/igt@i915_pm_...@basic-api.html * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: - bat-mtlp-8: NOTRUN -> [SKIP][11] ([i915#5190]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133452v1/bat-mtlp-8/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html * igt@kms_addfb_basic@basic-y-tiled-legacy: - bat-mtlp-8: NOTRUN -> [SKIP][12] ([i915#4212]) +8 other tests skip [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133452v1/bat-mtlp-8/igt@kms_addfb_ba...@basic-y-tiled-legacy.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-glk-j4005: NOTRUN -> [SKIP][13] +10 other tests skip [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133452v1/fi-glk-j4005/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - bat-mtlp-8: NOTRUN -> [SKIP][14] ([i915#4213]) +1 other test skip [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133452v1/bat-mtlp-8/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html * igt@kms_dsc@dsc-basic: - bat-mtlp-8: NOTRUN -> [SKIP][15] ([i915#3555] / [i915#3840] / [i915#9159]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133452v1/bat-mtlp-8/igt@kms_...@dsc-basic.html * igt@kms_force_connector_basic@force-load-detect: - fi-kbl-8809g: NOTRUN -> [SKIP][16] +30 other tests skip [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133452v1/fi-kbl-8809g/igt@kms_force_connector_ba...@force-load-detect.html - bat-mtlp-8: NOTRUN -> [SKIP][17] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133452v1/bat-mtlp-8/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_force_connector_basic@prune-stale-modes: - bat-mtlp-8: NOTRUN -> [SKIP][18] ([i915#5274]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133452v1/bat-mtlp-8/igt@kms_force_connector_ba...@prune-stale-modes.html * igt@kms_psr@psr-primary-mmap-gtt@edp-1: - bat-mtlp-8: NOTRUN -> [SKIP][19] ([i915#4077] / [i915#9688]) [19]:
[PATCH] drm/i915/bmg: Load DMC
Load Battlemage's DMC. We re-use XELPDP_DMC_MAX_FW_SIZE since BMG's
display is a derivative of Xe_LPD+ and has the same MMIO offset limits.
Signed-off-by: Gustavo Sousa
---
drivers/gpu/drm/i915/display/intel_dmc.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
b/drivers/gpu/drm/i915/display/intel_dmc.c
index cbd2ac5671b1..63fccdda56c0 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -115,6 +115,9 @@ static bool dmc_firmware_param_disabled(struct
drm_i915_private *i915)
#define XE2LPD_DMC_PATHDMC_PATH(xe2lpd)
MODULE_FIRMWARE(XE2LPD_DMC_PATH);
+#define BMG_DMC_PATH DMC_PATH(bmg)
+MODULE_FIRMWARE(BMG_DMC_PATH);
+
#define MTL_DMC_PATH DMC_PATH(mtl)
MODULE_FIRMWARE(MTL_DMC_PATH);
@@ -166,6 +169,9 @@ static const char *dmc_firmware_default(struct
drm_i915_private *i915, u32 *size
if (DISPLAY_VER_FULL(i915) == IP_VER(20, 0)) {
fw_path = XE2LPD_DMC_PATH;
max_fw_size = XE2LPD_DMC_MAX_FW_SIZE;
+ } else if (DISPLAY_VER_FULL(i915) == IP_VER(14, 1)) {
+ fw_path = BMG_DMC_PATH;
+ max_fw_size = XELPDP_DMC_MAX_FW_SIZE;
} else if (DISPLAY_VER_FULL(i915) == IP_VER(14, 0)) {
fw_path = MTL_DMC_PATH;
max_fw_size = XELPDP_DMC_MAX_FW_SIZE;
--
2.45.0
Re: [PATCH 0/8] drm/i915/pciids: PCI ID macro cleanups
On Fri, 10 May 2024, Jani Nikula wrote: > This is a spin-off from [1], including just the PCI ID macro cleanups, > as well as adding a bunch more cleanups. > > BR, > Jani. > > [1] https://lore.kernel.org/all/cover.1715086509.git.jani.nik...@intel.com/ > > > Jani Nikula (8): > drm/i915/pciids: add INTEL_PNV_IDS(), use acronym > drm/i915/pciids: add INTEL_ILK_IDS(), use acronym > drm/i915/pciids: add INTEL_SNB_IDS() > drm/i915/pciids: add INTEL_IVB_IDS() > drm/i915/pciids: don't include WHL/CML PCI IDs in CFL > drm/i915/pciids: remove 11 from INTEL_ICL_IDS() > drm/i915/pciids: remove 12 from INTEL_TGL_IDS() > drm/i915/pciids: don't include RPL-U PCI IDs in RPL-P > > arch/x86/kernel/early-quirks.c| 19 +++--- Bjorn, ack for merging this via drm-intel-next? BR, Jani. > .../drm/i915/display/intel_display_device.c | 20 +++--- > drivers/gpu/drm/i915/i915_pci.c | 13 ++-- > drivers/gpu/drm/i915/intel_device_info.c | 3 +- > include/drm/i915_pciids.h | 67 --- > 5 files changed, 71 insertions(+), 51 deletions(-) -- Jani Nikula, Intel
Re: [PATCH 7/8] drm/i915/pciids: remove 12 from INTEL_TGL_IDS()
On Fri, May 10, 2024 at 02:22:20PM +0300, Jani Nikula wrote:
> Most other PCI ID macros do not encode the gen in the name. Follow suit
> for TGL.
Reviewed-by: Rodrigo Vivi
>
> Cc: Bjorn Helgaas
> Cc: linux-...@vger.kernel.org
> Signed-off-by: Jani Nikula
> ---
> arch/x86/kernel/early-quirks.c | 2 +-
> drivers/gpu/drm/i915/display/intel_display_device.c | 2 +-
> drivers/gpu/drm/i915/i915_pci.c | 2 +-
> drivers/gpu/drm/i915/intel_device_info.c| 2 +-
> include/drm/i915_pciids.h | 10 +-
> 5 files changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
> index c150bb6f1a39..b2b9cc3b9545 100644
> --- a/arch/x86/kernel/early-quirks.c
> +++ b/arch/x86/kernel/early-quirks.c
> @@ -550,7 +550,7 @@ static const struct pci_device_id intel_early_ids[]
> __initconst = {
> INTEL_ICL_IDS(_early_ops),
> INTEL_EHL_IDS(_early_ops),
> INTEL_JSL_IDS(_early_ops),
> - INTEL_TGL_12_IDS(_early_ops),
> + INTEL_TGL_IDS(_early_ops),
> INTEL_RKL_IDS(_early_ops),
> INTEL_ADLS_IDS(_early_ops),
> INTEL_ADLP_IDS(_early_ops),
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
> b/drivers/gpu/drm/i915/display/intel_display_device.c
> index e47896002c13..fb4c4054207e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> @@ -834,7 +834,7 @@ static const struct {
> INTEL_ICL_IDS(_display),
> INTEL_EHL_IDS(_ehl_display),
> INTEL_JSL_IDS(_ehl_display),
> - INTEL_TGL_12_IDS(_display),
> + INTEL_TGL_IDS(_display),
> INTEL_DG1_IDS(_display),
> INTEL_RKL_IDS(_display),
> INTEL_ADLS_IDS(_s_display),
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 06b1d50ae47c..fa56113ed1ce 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -860,7 +860,7 @@ static const struct pci_device_id pciidlist[] = {
> INTEL_ICL_IDS(_info),
> INTEL_EHL_IDS(_info),
> INTEL_JSL_IDS(_info),
> - INTEL_TGL_12_IDS(_info),
> + INTEL_TGL_IDS(_info),
> INTEL_RKL_IDS(_info),
> INTEL_ADLS_IDS(_s_info),
> INTEL_ADLP_IDS(_p_info),
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> b/drivers/gpu/drm/i915/intel_device_info.c
> index a0a43ea07f11..64651a54a245 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -173,7 +173,7 @@ static const u16 subplatform_portf_ids[] = {
> };
>
> static const u16 subplatform_uy_ids[] = {
> - INTEL_TGL_12_GT2_IDS(0),
> + INTEL_TGL_GT2_IDS(0),
> };
>
> static const u16 subplatform_n_ids[] = {
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index ecfd7f71e2e7..42913d2eb655 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -620,12 +620,12 @@
> INTEL_VGA_DEVICE(0x4E71, info)
>
> /* TGL */
> -#define INTEL_TGL_12_GT1_IDS(info) \
> +#define INTEL_TGL_GT1_IDS(info) \
> INTEL_VGA_DEVICE(0x9A60, info), \
> INTEL_VGA_DEVICE(0x9A68, info), \
> INTEL_VGA_DEVICE(0x9A70, info)
>
> -#define INTEL_TGL_12_GT2_IDS(info) \
> +#define INTEL_TGL_GT2_IDS(info) \
> INTEL_VGA_DEVICE(0x9A40, info), \
> INTEL_VGA_DEVICE(0x9A49, info), \
> INTEL_VGA_DEVICE(0x9A59, info), \
> @@ -635,9 +635,9 @@
> INTEL_VGA_DEVICE(0x9AD9, info), \
> INTEL_VGA_DEVICE(0x9AF8, info)
>
> -#define INTEL_TGL_12_IDS(info) \
> - INTEL_TGL_12_GT1_IDS(info), \
> - INTEL_TGL_12_GT2_IDS(info)
> +#define INTEL_TGL_IDS(info) \
> + INTEL_TGL_GT1_IDS(info), \
> + INTEL_TGL_GT2_IDS(info)
>
> /* RKL */
> #define INTEL_RKL_IDS(info) \
> --
> 2.39.2
>
Re: [PATCH 6/8] drm/i915/pciids: remove 11 from INTEL_ICL_IDS()
On Fri, May 10, 2024 at 02:22:19PM +0300, Jani Nikula wrote:
> Most other PCI ID macros do not encode the gen in the name. Follow suit
> for ICL.
Reviewed-by: Rodrigo Vivi
>
> Cc: Bjorn Helgaas
> Cc: linux-...@vger.kernel.org
> Signed-off-by: Jani Nikula
> ---
> arch/x86/kernel/early-quirks.c | 2 +-
> drivers/gpu/drm/i915/display/intel_display_device.c | 2 +-
> drivers/gpu/drm/i915/i915_pci.c | 2 +-
> include/drm/i915_pciids.h | 2 +-
> 4 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
> index 2b698a3f56ef..c150bb6f1a39 100644
> --- a/arch/x86/kernel/early-quirks.c
> +++ b/arch/x86/kernel/early-quirks.c
> @@ -547,7 +547,7 @@ static const struct pci_device_id intel_early_ids[]
> __initconst = {
> INTEL_CML_IDS(_early_ops),
> INTEL_GLK_IDS(_early_ops),
> INTEL_CNL_IDS(_early_ops),
> - INTEL_ICL_11_IDS(_early_ops),
> + INTEL_ICL_IDS(_early_ops),
> INTEL_EHL_IDS(_early_ops),
> INTEL_JSL_IDS(_early_ops),
> INTEL_TGL_12_IDS(_early_ops),
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
> b/drivers/gpu/drm/i915/display/intel_display_device.c
> index 23909a8e2dc8..e47896002c13 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> @@ -831,7 +831,7 @@ static const struct {
> INTEL_CFL_IDS(_display),
> INTEL_WHL_IDS(_display),
> INTEL_CML_IDS(_display),
> - INTEL_ICL_11_IDS(_display),
> + INTEL_ICL_IDS(_display),
> INTEL_EHL_IDS(_ehl_display),
> INTEL_JSL_IDS(_ehl_display),
> INTEL_TGL_12_IDS(_display),
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index d85f023afebe..06b1d50ae47c 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -857,7 +857,7 @@ static const struct pci_device_id pciidlist[] = {
> INTEL_CML_GT2_IDS(_gt2_info),
> INTEL_CML_U_GT1_IDS(_gt1_info),
> INTEL_CML_U_GT2_IDS(_gt2_info),
> - INTEL_ICL_11_IDS(_info),
> + INTEL_ICL_IDS(_info),
> INTEL_EHL_IDS(_info),
> INTEL_JSL_IDS(_info),
> INTEL_TGL_12_IDS(_info),
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index 0c5a20d59801..ecfd7f71e2e7 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -597,7 +597,7 @@
> INTEL_VGA_DEVICE(0x8A70, info), \
> INTEL_VGA_DEVICE(0x8A71, info)
>
> -#define INTEL_ICL_11_IDS(info) \
> +#define INTEL_ICL_IDS(info) \
> INTEL_ICL_PORT_F_IDS(info), \
> INTEL_VGA_DEVICE(0x8A51, info), \
> INTEL_VGA_DEVICE(0x8A5D, info)
> --
> 2.39.2
>
Re: [PATCH 5/8] drm/i915/pciids: don't include WHL/CML PCI IDs in CFL
On Fri, May 10, 2024 at 02:22:18PM +0300, Jani Nikula wrote:
> It's confusing for INTEL_CFL_IDS() to include all WHL and CML PCI
> IDs. Even if we treat them the same in a lot of places, CML is a
> platform of its own, and the lists of PCI IDs should not conflate them.
>
> Largely go by the idea that if a platform has a name, group its PCI IDs
> together.
>
> That said, AML is special, having both KBL and CFL variants. Leave that
> alone.
fine by me, and thanks for the CML WHL.
Reviewed-by: Rodrigo Vivi
>
> v2: Also split out WHL not just CML (Rodrigo)
>
> Cc: Bjorn Helgaas
> Cc: linux-...@vger.kernel.org
> Signed-off-by: Jani Nikula
> ---
> arch/x86/kernel/early-quirks.c| 2 ++
> .../drm/i915/display/intel_display_device.c | 2 ++
> include/drm/i915_pciids.h | 30 +++
> 3 files changed, 21 insertions(+), 13 deletions(-)
>
> diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
> index 6549507003ec..2b698a3f56ef 100644
> --- a/arch/x86/kernel/early-quirks.c
> +++ b/arch/x86/kernel/early-quirks.c
> @@ -543,6 +543,8 @@ static const struct pci_device_id intel_early_ids[]
> __initconst = {
> INTEL_BXT_IDS(_early_ops),
> INTEL_KBL_IDS(_early_ops),
> INTEL_CFL_IDS(_early_ops),
> + INTEL_WHL_IDS(_early_ops),
> + INTEL_CML_IDS(_early_ops),
> INTEL_GLK_IDS(_early_ops),
> INTEL_CNL_IDS(_early_ops),
> INTEL_ICL_11_IDS(_early_ops),
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
> b/drivers/gpu/drm/i915/display/intel_display_device.c
> index bb681c8ed8a0..23909a8e2dc8 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> @@ -829,6 +829,8 @@ static const struct {
> INTEL_GLK_IDS(_display),
> INTEL_KBL_IDS(_display),
> INTEL_CFL_IDS(_display),
> + INTEL_WHL_IDS(_display),
> + INTEL_CML_IDS(_display),
> INTEL_ICL_11_IDS(_display),
> INTEL_EHL_IDS(_ehl_display),
> INTEL_JSL_IDS(_ehl_display),
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index 16778d92346b..0c5a20d59801 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -488,6 +488,12 @@
> INTEL_VGA_DEVICE(0x9BCA, info), \
> INTEL_VGA_DEVICE(0x9BCC, info)
>
> +#define INTEL_CML_IDS(info) \
> + INTEL_CML_GT1_IDS(info), \
> + INTEL_CML_GT2_IDS(info), \
> + INTEL_CML_U_GT1_IDS(info), \
> + INTEL_CML_U_GT2_IDS(info)
> +
> #define INTEL_KBL_IDS(info) \
> INTEL_KBL_GT1_IDS(info), \
> INTEL_KBL_GT2_IDS(info), \
> @@ -527,6 +533,15 @@
> INTEL_VGA_DEVICE(0x3EA7, info), /* ULT GT3 */ \
> INTEL_VGA_DEVICE(0x3EA8, info) /* ULT GT3 */
>
> +#define INTEL_CFL_IDS(info) \
> + INTEL_CFL_S_GT1_IDS(info), \
> + INTEL_CFL_S_GT2_IDS(info), \
> + INTEL_CFL_H_GT1_IDS(info), \
> + INTEL_CFL_H_GT2_IDS(info), \
> + INTEL_CFL_U_GT2_IDS(info), \
> + INTEL_CFL_U_GT3_IDS(info), \
> + INTEL_AML_CFL_GT2_IDS(info)
> +
> /* WHL/CFL U GT1 */
> #define INTEL_WHL_U_GT1_IDS(info) \
> INTEL_VGA_DEVICE(0x3EA1, info), \
> @@ -541,21 +556,10 @@
> #define INTEL_WHL_U_GT3_IDS(info) \
> INTEL_VGA_DEVICE(0x3EA2, info)
>
> -#define INTEL_CFL_IDS(info) \
> - INTEL_CFL_S_GT1_IDS(info), \
> - INTEL_CFL_S_GT2_IDS(info), \
> - INTEL_CFL_H_GT1_IDS(info), \
> - INTEL_CFL_H_GT2_IDS(info), \
> - INTEL_CFL_U_GT2_IDS(info), \
> - INTEL_CFL_U_GT3_IDS(info), \
> +#define INTEL_WHL_IDS(info) \
> INTEL_WHL_U_GT1_IDS(info), \
> INTEL_WHL_U_GT2_IDS(info), \
> - INTEL_WHL_U_GT3_IDS(info), \
> - INTEL_AML_CFL_GT2_IDS(info), \
> - INTEL_CML_GT1_IDS(info), \
> - INTEL_CML_GT2_IDS(info), \
> - INTEL_CML_U_GT1_IDS(info), \
> - INTEL_CML_U_GT2_IDS(info)
> + INTEL_WHL_U_GT3_IDS(info)
>
> /* CNL */
> #define INTEL_CNL_PORT_F_IDS(info) \
> --
> 2.39.2
>
Re: [PATCH 4/8] drm/i915/pciids: add INTEL_IVB_IDS()
On Fri, May 10, 2024 at 02:22:17PM +0300, Jani Nikula wrote:
> Add INTEL_IVB_IDS() to identify all IVBs except IVB Q transcode.
>
Reviewed-by: Rodrigo Vivi
> Cc: Bjorn Helgaas
> Cc: linux-...@vger.kernel.org
> Signed-off-by: Jani Nikula
> ---
> arch/x86/kernel/early-quirks.c | 3 +--
> drivers/gpu/drm/i915/display/intel_display_device.c | 3 +--
> include/drm/i915_pciids.h | 4
> 3 files changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
> index 23ded9260302..6549507003ec 100644
> --- a/arch/x86/kernel/early-quirks.c
> +++ b/arch/x86/kernel/early-quirks.c
> @@ -535,8 +535,7 @@ static const struct pci_device_id intel_early_ids[]
> __initconst = {
> INTEL_G45_IDS(_early_ops),
> INTEL_ILK_IDS(_early_ops),
> INTEL_SNB_IDS(_early_ops),
> - INTEL_IVB_M_IDS(_early_ops),
> - INTEL_IVB_D_IDS(_early_ops),
> + INTEL_IVB_IDS(_early_ops),
> INTEL_HSW_IDS(_early_ops),
> INTEL_BDW_IDS(_early_ops),
> INTEL_CHV_IDS(_early_ops),
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
> b/drivers/gpu/drm/i915/display/intel_display_device.c
> index c40d12ca386a..bb681c8ed8a0 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> @@ -819,8 +819,7 @@ static const struct {
> INTEL_ILK_D_IDS(_d_display),
> INTEL_ILK_M_IDS(_m_display),
> INTEL_SNB_IDS(_display),
> - INTEL_IVB_M_IDS(_display),
> - INTEL_IVB_D_IDS(_display),
> + INTEL_IVB_IDS(_display),
> INTEL_HSW_IDS(_display),
> INTEL_VLV_IDS(_display),
> INTEL_BDW_IDS(_display),
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index 0d48c493dcce..16778d92346b 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -177,6 +177,10 @@
> INTEL_IVB_D_GT1_IDS(info), \
> INTEL_IVB_D_GT2_IDS(info)
>
> +#define INTEL_IVB_IDS(info) \
> + INTEL_IVB_M_IDS(info), \
> + INTEL_IVB_D_IDS(info)
> +
> #define INTEL_IVB_Q_IDS(info) \
> INTEL_QUANTA_VGA_DEVICE(info) /* Quanta transcode */
>
> --
> 2.39.2
>
Re: [PATCH 3/8] drm/i915/pciids: add INTEL_SNB_IDS()
On Fri, May 10, 2024 at 02:22:16PM +0300, Jani Nikula wrote:
> Add INTEL_SNB_IDS() to identify all SNBs.
Reviewed-by: Rodrigo Vivi
>
> Cc: Bjorn Helgaas
> Cc: linux-...@vger.kernel.org
> Signed-off-by: Jani Nikula
> ---
> arch/x86/kernel/early-quirks.c | 3 +--
> drivers/gpu/drm/i915/display/intel_display_device.c | 3 +--
> include/drm/i915_pciids.h | 4
> 3 files changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
> index d8419d310091..23ded9260302 100644
> --- a/arch/x86/kernel/early-quirks.c
> +++ b/arch/x86/kernel/early-quirks.c
> @@ -534,8 +534,7 @@ static const struct pci_device_id intel_early_ids[]
> __initconst = {
> INTEL_GM45_IDS(_early_ops),
> INTEL_G45_IDS(_early_ops),
> INTEL_ILK_IDS(_early_ops),
> - INTEL_SNB_D_IDS(_early_ops),
> - INTEL_SNB_M_IDS(_early_ops),
> + INTEL_SNB_IDS(_early_ops),
> INTEL_IVB_M_IDS(_early_ops),
> INTEL_IVB_D_IDS(_early_ops),
> INTEL_HSW_IDS(_early_ops),
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
> b/drivers/gpu/drm/i915/display/intel_display_device.c
> index 052fd1c290c3..c40d12ca386a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> @@ -818,8 +818,7 @@ static const struct {
> INTEL_PNV_IDS(_display),
> INTEL_ILK_D_IDS(_d_display),
> INTEL_ILK_M_IDS(_m_display),
> - INTEL_SNB_D_IDS(_display),
> - INTEL_SNB_M_IDS(_display),
> + INTEL_SNB_IDS(_display),
> INTEL_IVB_M_IDS(_display),
> INTEL_IVB_D_IDS(_display),
> INTEL_HSW_IDS(_display),
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index 05f466ca8ce2..0d48c493dcce 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -151,6 +151,10 @@
> INTEL_SNB_M_GT1_IDS(info), \
> INTEL_SNB_M_GT2_IDS(info)
>
> +#define INTEL_SNB_IDS(info) \
> + INTEL_SNB_D_IDS(info), \
> + INTEL_SNB_M_IDS(info)
> +
> #define INTEL_IVB_M_GT1_IDS(info) \
> INTEL_VGA_DEVICE(0x0156, info) /* GT1 mobile */
>
> --
> 2.39.2
>
Re: [PATCH 2/8] drm/i915/pciids: add INTEL_ILK_IDS(), use acronym
On Fri, May 10, 2024 at 02:22:15PM +0300, Jani Nikula wrote:
> Most other PCI ID macros use platform acronyms. Follow suit for ILK. Add
> INTEL_ILK_IDS() to identify all ILKs.
Reviewed-by: Rodrigo Vivi
>
> Cc: Bjorn Helgaas
> Cc: linux-...@vger.kernel.org
> Signed-off-by: Jani Nikula
> ---
> arch/x86/kernel/early-quirks.c | 3 +--
> drivers/gpu/drm/i915/display/intel_display_device.c | 4 ++--
> drivers/gpu/drm/i915/i915_pci.c | 4 ++--
> include/drm/i915_pciids.h | 8 ++--
> 4 files changed, 11 insertions(+), 8 deletions(-)
>
> diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
> index f50394a00fca..d8419d310091 100644
> --- a/arch/x86/kernel/early-quirks.c
> +++ b/arch/x86/kernel/early-quirks.c
> @@ -533,8 +533,7 @@ static const struct pci_device_id intel_early_ids[]
> __initconst = {
> INTEL_I965GM_IDS(_early_ops),
> INTEL_GM45_IDS(_early_ops),
> INTEL_G45_IDS(_early_ops),
> - INTEL_IRONLAKE_D_IDS(_early_ops),
> - INTEL_IRONLAKE_M_IDS(_early_ops),
> + INTEL_ILK_IDS(_early_ops),
> INTEL_SNB_D_IDS(_early_ops),
> INTEL_SNB_M_IDS(_early_ops),
> INTEL_IVB_M_IDS(_early_ops),
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
> b/drivers/gpu/drm/i915/display/intel_display_device.c
> index 0e0f5a36507d..052fd1c290c3 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> @@ -816,8 +816,8 @@ static const struct {
> INTEL_GM45_IDS(_display),
> INTEL_G45_IDS(_display),
> INTEL_PNV_IDS(_display),
> - INTEL_IRONLAKE_D_IDS(_d_display),
> - INTEL_IRONLAKE_M_IDS(_m_display),
> + INTEL_ILK_D_IDS(_d_display),
> + INTEL_ILK_M_IDS(_m_display),
> INTEL_SNB_D_IDS(_display),
> INTEL_SNB_M_IDS(_display),
> INTEL_IVB_M_IDS(_display),
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index aa8593d73198..d85f023afebe 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -812,8 +812,8 @@ static const struct pci_device_id pciidlist[] = {
> INTEL_G45_IDS(_info),
> INTEL_PNV_G_IDS(_g_info),
> INTEL_PNV_M_IDS(_m_info),
> - INTEL_IRONLAKE_D_IDS(_d_info),
> - INTEL_IRONLAKE_M_IDS(_m_info),
> + INTEL_ILK_D_IDS(_d_info),
> + INTEL_ILK_M_IDS(_m_info),
> INTEL_SNB_D_GT1_IDS(_d_gt1_info),
> INTEL_SNB_D_GT2_IDS(_d_gt2_info),
> INTEL_SNB_M_GT1_IDS(_m_gt1_info),
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index 21942a3c823b..05f466ca8ce2 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -118,12 +118,16 @@
> INTEL_PNV_G_IDS(info), \
> INTEL_PNV_M_IDS(info)
>
> -#define INTEL_IRONLAKE_D_IDS(info) \
> +#define INTEL_ILK_D_IDS(info) \
> INTEL_VGA_DEVICE(0x0042, info)
>
> -#define INTEL_IRONLAKE_M_IDS(info) \
> +#define INTEL_ILK_M_IDS(info) \
> INTEL_VGA_DEVICE(0x0046, info)
>
> +#define INTEL_ILK_IDS(info) \
> + INTEL_ILK_D_IDS(info), \
> + INTEL_ILK_M_IDS(info)
> +
> #define INTEL_SNB_D_GT1_IDS(info) \
> INTEL_VGA_DEVICE(0x0102, info), \
> INTEL_VGA_DEVICE(0x010A, info)
> --
> 2.39.2
>
Re: [PATCH 1/8] drm/i915/pciids: add INTEL_PNV_IDS(), use acronym
On Fri, May 10, 2024 at 02:22:14PM +0300, Jani Nikula wrote:
> Most other PCI ID macros use platform acronyms. Follow suit for PNV. Add
> INTEL_PNV_IDS() to identify all PNVs.
>
> Cc: Bjorn Helgaas
> Cc: linux-...@vger.kernel.org
> Signed-off-by: Jani Nikula
Reviewed-by: Rodrigo Vivi
> ---
> arch/x86/kernel/early-quirks.c | 3 +--
> drivers/gpu/drm/i915/display/intel_display_device.c | 3 +--
> drivers/gpu/drm/i915/i915_pci.c | 4 ++--
> include/drm/i915_pciids.h | 8 ++--
> 4 files changed, 10 insertions(+), 8 deletions(-)
>
> diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
> index 59f4aefc6bc1..f50394a00fca 100644
> --- a/arch/x86/kernel/early-quirks.c
> +++ b/arch/x86/kernel/early-quirks.c
> @@ -527,8 +527,7 @@ static const struct pci_device_id intel_early_ids[]
> __initconst = {
> INTEL_I945G_IDS(_early_ops),
> INTEL_I945GM_IDS(_early_ops),
> INTEL_VLV_IDS(_early_ops),
> - INTEL_PINEVIEW_G_IDS(_early_ops),
> - INTEL_PINEVIEW_M_IDS(_early_ops),
> + INTEL_PNV_IDS(_early_ops),
> INTEL_I965G_IDS(_early_ops),
> INTEL_G33_IDS(_early_ops),
> INTEL_I965GM_IDS(_early_ops),
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
> b/drivers/gpu/drm/i915/display/intel_display_device.c
> index 56a2e17d7d9e..0e0f5a36507d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> @@ -815,8 +815,7 @@ static const struct {
> INTEL_I965GM_IDS(_display),
> INTEL_GM45_IDS(_display),
> INTEL_G45_IDS(_display),
> - INTEL_PINEVIEW_G_IDS(_display),
> - INTEL_PINEVIEW_M_IDS(_display),
> + INTEL_PNV_IDS(_display),
> INTEL_IRONLAKE_D_IDS(_d_display),
> INTEL_IRONLAKE_M_IDS(_m_display),
> INTEL_SNB_D_IDS(_display),
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index b5a056c9cb79..aa8593d73198 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -810,8 +810,8 @@ static const struct pci_device_id pciidlist[] = {
> INTEL_I965GM_IDS(_info),
> INTEL_GM45_IDS(_info),
> INTEL_G45_IDS(_info),
> - INTEL_PINEVIEW_G_IDS(_g_info),
> - INTEL_PINEVIEW_M_IDS(_m_info),
> + INTEL_PNV_G_IDS(_g_info),
> + INTEL_PNV_M_IDS(_m_info),
> INTEL_IRONLAKE_D_IDS(_d_info),
> INTEL_IRONLAKE_M_IDS(_m_info),
> INTEL_SNB_D_GT1_IDS(_d_gt1_info),
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index 85ce33ad6e26..21942a3c823b 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -108,12 +108,16 @@
> INTEL_VGA_DEVICE(0x2e42, info), /* B43_G */ \
> INTEL_VGA_DEVICE(0x2e92, info) /* B43_G.1 */
>
> -#define INTEL_PINEVIEW_G_IDS(info) \
> +#define INTEL_PNV_G_IDS(info) \
> INTEL_VGA_DEVICE(0xa001, info)
>
> -#define INTEL_PINEVIEW_M_IDS(info) \
> +#define INTEL_PNV_M_IDS(info) \
> INTEL_VGA_DEVICE(0xa011, info)
>
> +#define INTEL_PNV_IDS(info) \
> + INTEL_PNV_G_IDS(info), \
> + INTEL_PNV_M_IDS(info)
> +
> #define INTEL_IRONLAKE_D_IDS(info) \
> INTEL_VGA_DEVICE(0x0042, info)
>
> --
> 2.39.2
>
✓ Fi.CI.BAT: success for drm/i915/pciids: PCI ID macro cleanups
== Series Details == Series: drm/i915/pciids: PCI ID macro cleanups URL : https://patchwork.freedesktop.org/series/133444/ State : success == Summary == CI Bug Log - changes from CI_DRM_14747 -> Patchwork_133444v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133444v1/index.html Participating hosts (42 -> 42) -- Additional (2): fi-glk-j4005 bat-mtlp-8 Missing(2): fi-snb-2520m bat-arls-3 Known issues Here are the changes found in Patchwork_133444v1 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-mtlp-8: NOTRUN -> [SKIP][1] ([i915#9318]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133444v1/bat-mtlp-8/igt@debugfs_t...@basic-hwmon.html * igt@gem_huc_copy@huc-copy: - fi-glk-j4005: NOTRUN -> [SKIP][2] ([i915#2190]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133444v1/fi-glk-j4005/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@parallel-random-engines: - bat-mtlp-8: NOTRUN -> [SKIP][3] ([i915#4613]) +3 other tests skip [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133444v1/bat-mtlp-8/igt@gem_lmem_swapp...@parallel-random-engines.html - fi-glk-j4005: NOTRUN -> [SKIP][4] ([i915#4613]) +3 other tests skip [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133444v1/fi-glk-j4005/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_mmap@basic: - bat-mtlp-8: NOTRUN -> [SKIP][5] ([i915#4083]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133444v1/bat-mtlp-8/igt@gem_m...@basic.html * igt@gem_render_tiled_blits@basic: - bat-mtlp-8: NOTRUN -> [SKIP][6] ([i915#4079]) +1 other test skip [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133444v1/bat-mtlp-8/igt@gem_render_tiled_bl...@basic.html * igt@gem_tiled_fence_blits@basic: - bat-mtlp-8: NOTRUN -> [SKIP][7] ([i915#4077]) +2 other tests skip [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133444v1/bat-mtlp-8/igt@gem_tiled_fence_bl...@basic.html * igt@i915_pm_rps@basic-api: - bat-mtlp-8: NOTRUN -> [SKIP][8] ([i915#6621]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133444v1/bat-mtlp-8/igt@i915_pm_...@basic-api.html * igt@i915_selftest@live@gt_lrc: - bat-adlp-6: [PASS][9] -> [INCOMPLETE][10] ([i915#10886]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14747/bat-adlp-6/igt@i915_selftest@live@gt_lrc.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133444v1/bat-adlp-6/igt@i915_selftest@live@gt_lrc.html * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: - bat-mtlp-8: NOTRUN -> [SKIP][11] ([i915#5190]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133444v1/bat-mtlp-8/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html * igt@kms_addfb_basic@basic-y-tiled-legacy: - bat-mtlp-8: NOTRUN -> [SKIP][12] ([i915#4212]) +8 other tests skip [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133444v1/bat-mtlp-8/igt@kms_addfb_ba...@basic-y-tiled-legacy.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - bat-mtlp-8: NOTRUN -> [SKIP][13] ([i915#4213]) +1 other test skip [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133444v1/bat-mtlp-8/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html * igt@kms_dsc@dsc-basic: - bat-mtlp-8: NOTRUN -> [SKIP][14] ([i915#3555] / [i915#3840] / [i915#9159]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133444v1/bat-mtlp-8/igt@kms_...@dsc-basic.html * igt@kms_force_connector_basic@force-load-detect: - bat-mtlp-8: NOTRUN -> [SKIP][15] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133444v1/bat-mtlp-8/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_force_connector_basic@prune-stale-modes: - bat-mtlp-8: NOTRUN -> [SKIP][16] ([i915#5274]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133444v1/bat-mtlp-8/igt@kms_force_connector_ba...@prune-stale-modes.html * igt@kms_psr@psr-primary-mmap-gtt@edp-1: - bat-mtlp-8: NOTRUN -> [SKIP][17] ([i915#4077] / [i915#9688]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133444v1/bat-mtlp-8/igt@kms_psr@psr-primary-mmap-...@edp-1.html * igt@kms_psr@psr-primary-page-flip: - fi-glk-j4005: NOTRUN -> [SKIP][18] +10 other tests skip [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133444v1/fi-glk-j4005/igt@kms_...@psr-primary-page-flip.html * igt@kms_setmode@basic-clone-single-crtc: - bat-mtlp-8: NOTRUN -> [SKIP][19] ([i915#3555] / [i915#8809]) [19]:
✗ Fi.CI.CHECKPATCH: warning for drm/i915/pciids: PCI ID macro cleanups
== Series Details == Series: drm/i915/pciids: PCI ID macro cleanups URL : https://patchwork.freedesktop.org/series/133444/ State : warning == Summary == Error: dim checkpatch failed 74c4a4b08b9b drm/i915/pciids: add INTEL_PNV_IDS(), use acronym -:72: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #72: FILE: include/drm/i915_pciids.h:117: +#define INTEL_PNV_IDS(info) \ + INTEL_PNV_G_IDS(info), \ + INTEL_PNV_M_IDS(info) -:72: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects? #72: FILE: include/drm/i915_pciids.h:117: +#define INTEL_PNV_IDS(info) \ + INTEL_PNV_G_IDS(info), \ + INTEL_PNV_M_IDS(info) total: 1 errors, 0 warnings, 1 checks, 46 lines checked ec59b5b635f2 drm/i915/pciids: add INTEL_ILK_IDS(), use acronym -:73: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #73: FILE: include/drm/i915_pciids.h:127: +#define INTEL_ILK_IDS(info) \ + INTEL_ILK_D_IDS(info), \ + INTEL_ILK_M_IDS(info) -:73: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects? #73: FILE: include/drm/i915_pciids.h:127: +#define INTEL_ILK_IDS(info) \ + INTEL_ILK_D_IDS(info), \ + INTEL_ILK_M_IDS(info) total: 1 errors, 0 warnings, 1 checks, 47 lines checked 36178b28f831 drm/i915/pciids: add INTEL_SNB_IDS() -:48: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #48: FILE: include/drm/i915_pciids.h:154: +#define INTEL_SNB_IDS(info) \ + INTEL_SNB_D_IDS(info), \ + INTEL_SNB_M_IDS(info) -:48: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects? #48: FILE: include/drm/i915_pciids.h:154: +#define INTEL_SNB_IDS(info) \ + INTEL_SNB_D_IDS(info), \ + INTEL_SNB_M_IDS(info) total: 1 errors, 0 warnings, 1 checks, 28 lines checked 05d3be80584d drm/i915/pciids: add INTEL_IVB_IDS() -:48: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #48: FILE: include/drm/i915_pciids.h:180: +#define INTEL_IVB_IDS(info) \ + INTEL_IVB_M_IDS(info), \ + INTEL_IVB_D_IDS(info) -:48: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects? #48: FILE: include/drm/i915_pciids.h:180: +#define INTEL_IVB_IDS(info) \ + INTEL_IVB_M_IDS(info), \ + INTEL_IVB_D_IDS(info) total: 1 errors, 0 warnings, 1 checks, 28 lines checked b960793f2bf0 drm/i915/pciids: don't include WHL/CML PCI IDs in CFL -:56: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #56: FILE: include/drm/i915_pciids.h:491: +#define INTEL_CML_IDS(info) \ + INTEL_CML_GT1_IDS(info), \ + INTEL_CML_GT2_IDS(info), \ + INTEL_CML_U_GT1_IDS(info), \ + INTEL_CML_U_GT2_IDS(info) -:56: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects? #56: FILE: include/drm/i915_pciids.h:491: +#define INTEL_CML_IDS(info) \ + INTEL_CML_GT1_IDS(info), \ + INTEL_CML_GT2_IDS(info), \ + INTEL_CML_U_GT1_IDS(info), \ + INTEL_CML_U_GT2_IDS(info) -:69: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #69: FILE: include/drm/i915_pciids.h:536: +#define INTEL_CFL_IDS(info) \ + INTEL_CFL_S_GT1_IDS(info), \ + INTEL_CFL_S_GT2_IDS(info), \ + INTEL_CFL_H_GT1_IDS(info), \ + INTEL_CFL_H_GT2_IDS(info), \ + INTEL_CFL_U_GT2_IDS(info), \ + INTEL_CFL_U_GT3_IDS(info), \ + INTEL_AML_CFL_GT2_IDS(info) -:69: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects? #69: FILE: include/drm/i915_pciids.h:536: +#define INTEL_CFL_IDS(info) \ + INTEL_CFL_S_GT1_IDS(info), \ + INTEL_CFL_S_GT2_IDS(info), \ + INTEL_CFL_H_GT1_IDS(info), \ + INTEL_CFL_H_GT2_IDS(info), \ + INTEL_CFL_U_GT2_IDS(info), \ + INTEL_CFL_U_GT3_IDS(info), \ + INTEL_AML_CFL_GT2_IDS(info) -:92: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #92: FILE: include/drm/i915_pciids.h:559: +#define INTEL_WHL_IDS(info) \ INTEL_WHL_U_GT1_IDS(info), \ INTEL_WHL_U_GT2_IDS(info), \ + INTEL_WHL_U_GT3_IDS(info) -:92: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects? #92: FILE: include/drm/i915_pciids.h:559: +#define INTEL_WHL_IDS(info) \ INTEL_WHL_U_GT1_IDS(info), \ INTEL_WHL_U_GT2_IDS(info), \ + INTEL_WHL_U_GT3_IDS(info) total: 3 errors, 0 warnings, 3 checks, 66 lines checked 765c60a9fc28 drm/i915/pciids: remove 11 from INTEL_ICL_IDS() -:61: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #61: FILE: include/drm/i915_pciids.h:600: +#define INTEL_ICL_IDS(info) \ INTEL_ICL_PORT_F_IDS(info), \ INTEL_VGA_DEVICE(0x8A51, info), \ INTEL_VGA_DEVICE(0x8A5D, info) -:61: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects? #61: FILE: include/drm/i915_pciids.h:600:
Re: [PATCH 2/2] drm/i915/display: Remove uhbr13.5 pll state values
On Thu, 09 May 2024, Arun R Murthy wrote:
> uhbr13.5 is not supported on dg2/mtl. This patch removes the pll state
> table for synps and c20 PHY.
>
> Signed-off-by: Arun R Murthy
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 26 --
> drivers/gpu/drm/i915/display/intel_dp.c | 2 --
> drivers/gpu/drm/i915/display/intel_snps_phy.c | 35 ---
> 3 files changed, 63 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 8e3b13884bb8..fb07d14d9a7a 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -885,31 +885,6 @@ static const struct intel_c20pll_state mtl_c20_dp_uhbr10
> = {
> },
> };
>
> -static const struct intel_c20pll_state mtl_c20_dp_uhbr13_5 = {
> - .clock = 135, /* 13.5 Gbps */
> - .tx = { 0xbea0, /* tx cfg0 */
> - 0x4800, /* tx cfg1 */
> - 0x, /* tx cfg2 */
> - },
> - .cmn = {0x0500, /* cmn cfg0*/
> - 0x0005, /* cmn cfg1 */
> - 0x, /* cmn cfg2 */
> - 0x, /* cmn cfg3 */
> - },
> - .mpllb = { 0x015f, /* mpllb cfg0 */
> - 0x2205, /* mpllb cfg1 */
> - 0x1b17, /* mpllb cfg2 */
> - 0xffc1, /* mpllb cfg3 */
> - 0xe100, /* mpllb cfg4 */
> - 0xbd00, /* mpllb cfg5 */
> - 0x2000, /* mpllb cfg6 */
> - 0x0001, /* mpllb cfg7 */
> - 0x4800, /* mpllb cfg8 */
> - 0x, /* mpllb cfg9 */
> - 0x, /* mpllb cfg10 */
> - },
> -};
> -
> static const struct intel_c20pll_state mtl_c20_dp_uhbr20 = {
> .clock = 200, /* 20 Gbps */
> .tx = { 0xbe20, /* tx cfg0 */
> @@ -940,7 +915,6 @@ static const struct intel_c20pll_state * const
> mtl_c20_dp_tables[] = {
> _c20_dp_hbr2,
> _c20_dp_hbr3,
> _c20_dp_uhbr10,
> - _c20_dp_uhbr13_5,
> _c20_dp_uhbr20,
> NULL,
> };
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 7098ca65701f..a9c17c6d8d77 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -247,8 +247,6 @@ static void intel_dp_set_dpcd_sink_rates(struct intel_dp
> *intel_dp)
>
> if (uhbr_rates & DP_UHBR10)
> intel_dp->sink_rates[i++] = 100;
> - if (uhbr_rates & DP_UHBR13_5)
> - intel_dp->sink_rates[i++] = 135;
This is about the sink, not the source. We'll want to keep this.
BR,
Jani.
> if (uhbr_rates & DP_UHBR20)
> intel_dp->sink_rates[i++] = 200;
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c
> b/drivers/gpu/drm/i915/display/intel_snps_phy.c
> index e6df1f92def5..6b1eda0d73d8 100644
> --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
> @@ -213,47 +213,12 @@ static const struct intel_mpllb_state dg2_dp_uhbr10_100
> = {
> REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 76101),
> };
>
> -static const struct intel_mpllb_state dg2_dp_uhbr13_100 = {
> - .clock = 135,
> - .ref_control =
> - REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
> - .mpllb_cp =
> - REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
> - REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 45) |
> - REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
> - REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
> - .mpllb_div =
> - REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
> - REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_CLK_EN, 1) |
> - REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_MULTIPLIER, 8) |
> - REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
> - REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) |
> - REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) |
> - REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 3),
> - .mpllb_div2 =
> - REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
> - REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 508),
> - .mpllb_fracn1 =
> - REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
> - REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
> -
> - /*
> - * SSC will be enabled, DP UHBR has a minimum SSC requirement.
> - */
> - .mpllb_sscen =
> - REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
> - REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 79626),
> - .mpllb_sscstep =
> - REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 102737),
> -};
> -
> static const struct intel_mpllb_state * const dg2_dp_100_tables[] = {
> _dp_rbr_100,
>
✓ Fi.CI.BAT: success for drm/i915: Plane fb refactoring (rev3)
== Series Details == Series: drm/i915: Plane fb refactoring (rev3) URL : https://patchwork.freedesktop.org/series/133231/ State : success == Summary == CI Bug Log - changes from CI_DRM_14747 -> Patchwork_133231v3 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133231v3/index.html Participating hosts (42 -> 36) -- Additional (1): fi-glk-j4005 Missing(7): fi-kbl-7567u bat-kbl-2 fi-bsw-n3050 fi-snb-2520m fi-elk-e7500 bat-jsl-1 bat-mtlp-6 Known issues Here are the changes found in Patchwork_133231v3 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-arls-3: NOTRUN -> [SKIP][1] ([i915#9318]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133231v3/bat-arls-3/igt@debugfs_t...@basic-hwmon.html * igt@gem_huc_copy@huc-copy: - fi-glk-j4005: NOTRUN -> [SKIP][2] ([i915#2190]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133231v3/fi-glk-j4005/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-glk-j4005: NOTRUN -> [SKIP][3] ([i915#4613]) +3 other tests skip [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133231v3/fi-glk-j4005/igt@gem_lmem_swapp...@basic.html * igt@gem_lmem_swapping@basic@lmem0: - bat-dg2-9: [PASS][4] -> [FAIL][5] ([i915#10378]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14747/bat-dg2-9/igt@gem_lmem_swapping@ba...@lmem0.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133231v3/bat-dg2-9/igt@gem_lmem_swapping@ba...@lmem0.html * igt@gem_lmem_swapping@parallel-random-engines: - bat-arls-3: NOTRUN -> [SKIP][6] ([i915#10213]) +3 other tests skip [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133231v3/bat-arls-3/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_mmap@basic: - bat-arls-3: NOTRUN -> [SKIP][7] ([i915#4083]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133231v3/bat-arls-3/igt@gem_m...@basic.html * igt@gem_render_tiled_blits@basic: - bat-arls-3: NOTRUN -> [SKIP][8] ([i915#10197] / [i915#10211] / [i915#4079]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133231v3/bat-arls-3/igt@gem_render_tiled_bl...@basic.html * igt@gem_tiled_blits@basic: - bat-arls-3: NOTRUN -> [SKIP][9] ([i915#10196] / [i915#4077]) +2 other tests skip [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133231v3/bat-arls-3/igt@gem_tiled_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-arls-3: NOTRUN -> [SKIP][10] ([i915#10206] / [i915#4079]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133231v3/bat-arls-3/igt@gem_tiled_pread_basic.html * igt@i915_pm_rps@basic-api: - bat-arls-3: NOTRUN -> [SKIP][11] ([i915#10209]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133231v3/bat-arls-3/igt@i915_pm_...@basic-api.html * igt@kms_addfb_basic@addfb25-x-tiled-legacy: - bat-arls-3: NOTRUN -> [SKIP][12] ([i915#10200]) +9 other tests skip [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133231v3/bat-arls-3/igt@kms_addfb_ba...@addfb25-x-tiled-legacy.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-glk-j4005: NOTRUN -> [SKIP][13] +10 other tests skip [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133231v3/fi-glk-j4005/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html - bat-arls-3: NOTRUN -> [SKIP][14] ([i915#10202]) +1 other test skip [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133231v3/bat-arls-3/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html * igt@kms_dsc@dsc-basic: - bat-arls-3: NOTRUN -> [SKIP][15] ([i915#9886]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133231v3/bat-arls-3/igt@kms_...@dsc-basic.html * igt@kms_force_connector_basic@force-load-detect: - bat-arls-3: NOTRUN -> [SKIP][16] ([i915#10207]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133231v3/bat-arls-3/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_pm_backlight@basic-brightness: - bat-arls-3: NOTRUN -> [SKIP][17] ([i915#9812]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133231v3/bat-arls-3/igt@kms_pm_backli...@basic-brightness.html * igt@kms_psr@psr-primary-mmap-gtt: - bat-arls-3: NOTRUN -> [SKIP][18] ([i915#9732]) +3 other tests skip [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133231v3/bat-arls-3/igt@kms_...@psr-primary-mmap-gtt.html * igt@kms_setmode@basic-clone-single-crtc: - bat-arls-3: NOTRUN -> [SKIP][19] ([i915#10208] / [i915#8809]) [19]:
✓ Fi.CI.BAT: success for series starting with [1/2] drm/xe/display: remove unused xe->enabled_irq_mask
== Series Details == Series: series starting with [1/2] drm/xe/display: remove unused xe->enabled_irq_mask URL : https://patchwork.freedesktop.org/series/133441/ State : success == Summary == CI Bug Log - changes from CI_DRM_14747 -> Patchwork_133441v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133441v1/index.html Participating hosts (42 -> 37) -- Additional (3): fi-glk-j4005 bat-mtlp-8 fi-kbl-8809g Missing(8): fi-kbl-7567u bat-kbl-2 fi-bsw-n3050 fi-snb-2520m fi-elk-e7500 bat-dg2-11 bat-jsl-1 bat-mtlp-6 Known issues Here are the changes found in Patchwork_133441v1 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-mtlp-8: NOTRUN -> [SKIP][1] ([i915#9318]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133441v1/bat-mtlp-8/igt@debugfs_t...@basic-hwmon.html - bat-arls-3: NOTRUN -> [SKIP][2] ([i915#9318]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133441v1/bat-arls-3/igt@debugfs_t...@basic-hwmon.html * igt@gem_huc_copy@huc-copy: - fi-kbl-8809g: NOTRUN -> [SKIP][3] ([i915#2190]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133441v1/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html - fi-glk-j4005: NOTRUN -> [SKIP][4] ([i915#2190]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133441v1/fi-glk-j4005/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-glk-j4005: NOTRUN -> [SKIP][5] ([i915#4613]) +3 other tests skip [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133441v1/fi-glk-j4005/igt@gem_lmem_swapp...@basic.html - fi-kbl-8809g: NOTRUN -> [SKIP][6] ([i915#4613]) +3 other tests skip [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133441v1/fi-kbl-8809g/igt@gem_lmem_swapp...@basic.html * igt@gem_lmem_swapping@parallel-random-engines: - bat-arls-3: NOTRUN -> [SKIP][7] ([i915#10213]) +3 other tests skip [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133441v1/bat-arls-3/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_lmem_swapping@verify-random: - bat-mtlp-8: NOTRUN -> [SKIP][8] ([i915#4613]) +3 other tests skip [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133441v1/bat-mtlp-8/igt@gem_lmem_swapp...@verify-random.html * igt@gem_mmap@basic: - bat-mtlp-8: NOTRUN -> [SKIP][9] ([i915#4083]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133441v1/bat-mtlp-8/igt@gem_m...@basic.html - bat-arls-3: NOTRUN -> [SKIP][10] ([i915#4083]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133441v1/bat-arls-3/igt@gem_m...@basic.html * igt@gem_mmap_gtt@basic: - bat-mtlp-8: NOTRUN -> [SKIP][11] ([i915#4077]) +2 other tests skip [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133441v1/bat-mtlp-8/igt@gem_mmap_...@basic.html * igt@gem_render_tiled_blits@basic: - bat-mtlp-8: NOTRUN -> [SKIP][12] ([i915#4079]) +1 other test skip [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133441v1/bat-mtlp-8/igt@gem_render_tiled_bl...@basic.html - bat-arls-3: NOTRUN -> [SKIP][13] ([i915#10197] / [i915#10211] / [i915#4079]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133441v1/bat-arls-3/igt@gem_render_tiled_bl...@basic.html * igt@gem_tiled_blits@basic: - bat-arls-3: NOTRUN -> [SKIP][14] ([i915#10196] / [i915#4077]) +2 other tests skip [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133441v1/bat-arls-3/igt@gem_tiled_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-arls-3: NOTRUN -> [SKIP][15] ([i915#10206] / [i915#4079]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133441v1/bat-arls-3/igt@gem_tiled_pread_basic.html * igt@i915_pm_rps@basic-api: - bat-mtlp-8: NOTRUN -> [SKIP][16] ([i915#6621]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133441v1/bat-mtlp-8/igt@i915_pm_...@basic-api.html - bat-arls-3: NOTRUN -> [SKIP][17] ([i915#10209]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133441v1/bat-arls-3/igt@i915_pm_...@basic-api.html * igt@i915_selftest@live@mman: - bat-dg2-8: [PASS][18] -> [DMESG-WARN][19] ([i915#10014]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14747/bat-dg2-8/igt@i915_selftest@l...@mman.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133441v1/bat-dg2-8/igt@i915_selftest@l...@mman.html * igt@i915_selftest@live@requests: - bat-atsm-1: [PASS][20] -> [INCOMPLETE][21] ([i915#10975]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14747/bat-atsm-1/igt@i915_selftest@l...@requests.html [21]:
✓ Fi.CI.BAT: success for Panel replay selective update support (rev11)
== Series Details == Series: Panel replay selective update support (rev11) URL : https://patchwork.freedesktop.org/series/128193/ State : success == Summary == CI Bug Log - changes from CI_DRM_14747 -> Patchwork_128193v11 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v11/index.html Participating hosts (42 -> 40) -- Missing(2): bat-dg2-11 fi-snb-2520m Known issues Here are the changes found in Patchwork_128193v11 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-arls-3: NOTRUN -> [SKIP][1] ([i915#9318]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v11/bat-arls-3/igt@debugfs_t...@basic-hwmon.html * igt@gem_lmem_swapping@parallel-random-engines: - bat-arls-3: NOTRUN -> [SKIP][2] ([i915#10213]) +3 other tests skip [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v11/bat-arls-3/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_mmap@basic: - bat-arls-3: NOTRUN -> [SKIP][3] ([i915#4083]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v11/bat-arls-3/igt@gem_m...@basic.html * igt@gem_render_tiled_blits@basic: - bat-arls-3: NOTRUN -> [SKIP][4] ([i915#10197] / [i915#10211] / [i915#4079]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v11/bat-arls-3/igt@gem_render_tiled_bl...@basic.html * igt@gem_tiled_blits@basic: - bat-arls-3: NOTRUN -> [SKIP][5] ([i915#10196] / [i915#4077]) +2 other tests skip [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v11/bat-arls-3/igt@gem_tiled_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-arls-3: NOTRUN -> [SKIP][6] ([i915#10206] / [i915#4079]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v11/bat-arls-3/igt@gem_tiled_pread_basic.html * igt@i915_pm_rps@basic-api: - bat-arls-3: NOTRUN -> [SKIP][7] ([i915#10209]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v11/bat-arls-3/igt@i915_pm_...@basic-api.html * igt@kms_addfb_basic@addfb25-x-tiled-legacy: - bat-arls-3: NOTRUN -> [SKIP][8] ([i915#10200]) +9 other tests skip [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v11/bat-arls-3/igt@kms_addfb_ba...@addfb25-x-tiled-legacy.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - bat-arls-3: NOTRUN -> [SKIP][9] ([i915#10202]) +1 other test skip [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v11/bat-arls-3/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html * igt@kms_dsc@dsc-basic: - bat-arls-3: NOTRUN -> [SKIP][10] ([i915#9886]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v11/bat-arls-3/igt@kms_...@dsc-basic.html * igt@kms_force_connector_basic@force-load-detect: - bat-arls-3: NOTRUN -> [SKIP][11] ([i915#10207]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v11/bat-arls-3/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_pm_backlight@basic-brightness: - bat-arls-3: NOTRUN -> [SKIP][12] ([i915#9812]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v11/bat-arls-3/igt@kms_pm_backli...@basic-brightness.html * igt@kms_psr@psr-primary-mmap-gtt: - bat-arls-3: NOTRUN -> [SKIP][13] ([i915#9732]) +3 other tests skip [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v11/bat-arls-3/igt@kms_...@psr-primary-mmap-gtt.html * igt@kms_setmode@basic-clone-single-crtc: - bat-arls-3: NOTRUN -> [SKIP][14] ([i915#10208] / [i915#8809]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v11/bat-arls-3/igt@kms_setm...@basic-clone-single-crtc.html * igt@prime_vgem@basic-fence-mmap: - bat-arls-3: NOTRUN -> [SKIP][15] ([i915#10196] / [i915#3708] / [i915#4077]) +1 other test skip [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v11/bat-arls-3/igt@prime_v...@basic-fence-mmap.html * igt@prime_vgem@basic-fence-read: - bat-arls-3: NOTRUN -> [SKIP][16] ([i915#10212] / [i915#3708]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v11/bat-arls-3/igt@prime_v...@basic-fence-read.html * igt@prime_vgem@basic-read: - bat-arls-3: NOTRUN -> [SKIP][17] ([i915#10214] / [i915#3708]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v11/bat-arls-3/igt@prime_v...@basic-read.html * igt@prime_vgem@basic-write: - bat-arls-3: NOTRUN -> [SKIP][18] ([i915#10216] / [i915#3708]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_128193v11/bat-arls-3/igt@prime_v...@basic-write.html Possible fixes * igt@i915_module_load@load: -
✗ Fi.CI.SPARSE: warning for Panel replay selective update support (rev11)
== Series Details == Series: Panel replay selective update support (rev11) URL : https://patchwork.freedesktop.org/series/128193/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
✗ Fi.CI.CHECKPATCH: warning for Panel replay selective update support (rev11)
== Series Details == Series: Panel replay selective update support (rev11) URL : https://patchwork.freedesktop.org/series/128193/ State : warning == Summary == Error: dim checkpatch failed 4ce3205a70e0 drm/i915/psr: Rename has_psr2 as has_sel_update 2d9a71ec0767 drm/i915/display: Do not print "psr: enabled" for on Panel Replay fd10a5f63290 drm/i915/dp: Use always vsc revision 0x6 for Panel Replay 5da53bb16ef9 drm/i915/psr: Rename psr2_enabled as sel_update_enabled a750aa2295aa drm/panelreplay: dpcd register definition for panelreplay SU 899dcfa4aa4c drm/i915/psr: Detect panel replay selective update support 10f32fac4141 drm/i915/psr: Modify intel_dp_get_su_granularity to support panel replay faeda725bae0 drm/i915/psr: Panel replay uses SRD_STATUS to track it's status c7a19e73dbc5 drm/i915/psr: Do not apply workarounds in case of panel replay a8852b585617 drm/i915/psr: Update PSR module parameter descriptions 3b4207204223 drm/i915/psr: Split intel_psr2_config_valid for panel replay ae3d249115ce drm/i915/psr: Add panel replay sel update support to debugfs interface -:13: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line (possible unwrapped commit description?) #13: Sink support: PSR = no, Panel Replay = yes, Panel Replay Selective Update = yes total: 0 errors, 1 warnings, 0 checks, 22 lines checked
Re: [PATCH 9/9] drm/i915: Rename the fb pinning functions to indicate the address space
On Mon, 06 May 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Rename the fb pinning functions such that their name directly
> informs us what gets pinned into which address space.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_dpt.c | 6 +--
> drivers/gpu/drm/i915/display/intel_dpt.h | 6 +--
> drivers/gpu/drm/i915/display/intel_fb_pin.c | 46 +--
> drivers/gpu/drm/i915/display/intel_fb_pin.h | 12 ++---
> drivers/gpu/drm/i915/display/intel_fbdev.c| 8 ++--
> drivers/gpu/drm/xe/display/xe_fb_pin.c| 12 ++---
> drivers/gpu/drm/xe/display/xe_plane_initial.c | 4 +-
> 7 files changed, 47 insertions(+), 47 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c
> b/drivers/gpu/drm/i915/display/intel_dpt.c
> index 786d3f2e94c7..73a1918e2537 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpt.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpt.c
> @@ -121,8 +121,8 @@ static void dpt_cleanup(struct i915_address_space *vm)
> i915_gem_object_put(dpt->obj);
> }
>
> -struct i915_vma *intel_dpt_pin(struct i915_address_space *vm,
> -unsigned int alignment)
> +struct i915_vma *intel_dpt_pin_to_ggtt(struct i915_address_space *vm,
> +unsigned int alignment)
> {
> struct drm_i915_private *i915 = vm->i915;
> struct i915_dpt *dpt = i915_vm_to_dpt(vm);
> @@ -173,7 +173,7 @@ struct i915_vma *intel_dpt_pin(struct i915_address_space
> *vm,
> return err ? ERR_PTR(err) : vma;
> }
>
> -void intel_dpt_unpin(struct i915_address_space *vm)
> +void intel_dpt_unpin_from_ggtt(struct i915_address_space *vm)
> {
> struct i915_dpt *dpt = i915_vm_to_dpt(vm);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpt.h
> b/drivers/gpu/drm/i915/display/intel_dpt.h
> index f467578a4950..ff18a525bfbe 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpt.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpt.h
> @@ -13,9 +13,9 @@ struct i915_vma;
> struct intel_framebuffer;
>
> void intel_dpt_destroy(struct i915_address_space *vm);
> -struct i915_vma *intel_dpt_pin(struct i915_address_space *vm,
> -unsigned int alignment);
> -void intel_dpt_unpin(struct i915_address_space *vm);
> +struct i915_vma *intel_dpt_pin_to_ggtt(struct i915_address_space *vm,
> +unsigned int alignment);
> +void intel_dpt_unpin_from_ggtt(struct i915_address_space *vm);
> void intel_dpt_suspend(struct drm_i915_private *i915);
> void intel_dpt_resume(struct drm_i915_private *i915);
> struct i915_address_space *
> diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c
> b/drivers/gpu/drm/i915/display/intel_fb_pin.c
> index 7971656982a6..1acc11fa19f4 100644
> --- a/drivers/gpu/drm/i915/display/intel_fb_pin.c
> +++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c
> @@ -18,11 +18,11 @@
> #include "intel_fb_pin.h"
>
> static struct i915_vma *
> -intel_pin_fb_obj_dpt(const struct drm_framebuffer *fb,
> - const struct i915_gtt_view *view,
> - unsigned int alignment,
> - unsigned long *out_flags,
> - struct i915_address_space *vm)
> +intel_fb_pin_to_dpt(const struct drm_framebuffer *fb,
> + const struct i915_gtt_view *view,
> + unsigned int alignment,
> + unsigned long *out_flags,
> + struct i915_address_space *vm)
> {
> struct drm_device *dev = fb->dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> @@ -102,11 +102,11 @@ intel_pin_fb_obj_dpt(const struct drm_framebuffer *fb,
> }
>
> struct i915_vma *
> -intel_pin_and_fence_fb_obj(const struct drm_framebuffer *fb,
> -bool phys_cursor,
> -const struct i915_gtt_view *view,
> -bool uses_fence,
> -unsigned long *out_flags)
> +intel_fb_pin_to_ggtt(const struct drm_framebuffer *fb,
> + bool phys_cursor,
> + const struct i915_gtt_view *view,
> + bool uses_fence,
> + unsigned long *out_flags)
> {
> struct drm_device *dev = fb->dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> @@ -226,7 +226,7 @@ intel_pin_and_fence_fb_obj(const struct drm_framebuffer
> *fb,
> return vma;
> }
>
> -void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
> +void intel_fb_unpin_vma(struct i915_vma *vma, unsigned long flags)
> {
> if (flags & PLANE_HAS_FENCE)
> i915_vma_unpin_fence(vma);
> @@ -242,10 +242,10 @@ int intel_plane_pin_fb(struct intel_plane_state
> *plane_state)
> struct i915_vma *vma;
>
> if (!intel_fb_uses_dpt(>base)) {
> - vma = intel_pin_and_fence_fb_obj(>base,
> intel_plane_needs_physical(plane),
> -
Re: [PATCH v2 8/9] drm/i915: Cleanup fbdev fb setup
On Fri, 10 May 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> We use a mix of 'intel_fb' vs. 'ifbdev->fb' in the same function.
> Both should be pointing at the same thing. Make things less
> confusing by just getting existing fb from 'ifbdev->fb' at the
> start and then sticking with the local 'fb' (renamed from the
> 'intel_fb') until the very end.
>
> v2: rebase
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_fbdev.c | 38 --
> 1 file changed, 20 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c
> b/drivers/gpu/drm/i915/display/intel_fbdev.c
> index 4bbbf481bb3a..e898018ab76a 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbdev.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
> @@ -175,7 +175,7 @@ static int intelfb_create(struct drm_fb_helper *helper,
> struct drm_fb_helper_surface_size *sizes)
> {
> struct intel_fbdev *ifbdev = to_intel_fbdev(helper);
> - struct intel_framebuffer *intel_fb = ifbdev->fb;
> + struct intel_framebuffer *fb = ifbdev->fb;
> struct drm_device *dev = helper->dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> const struct i915_gtt_view view = {
> @@ -195,29 +195,30 @@ static int intelfb_create(struct drm_fb_helper *helper,
> if (ret)
> return ret;
>
> - if (intel_fb &&
> - (sizes->fb_width > intel_fb->base.width ||
> - sizes->fb_height > intel_fb->base.height)) {
> + ifbdev->fb = NULL;
> +
> + if (fb &&
> + (sizes->fb_width > fb->base.width ||
> + sizes->fb_height > fb->base.height)) {
> drm_dbg_kms(_priv->drm,
> "BIOS fb too small (%dx%d), we require (%dx%d),"
> " releasing it\n",
> - intel_fb->base.width, intel_fb->base.height,
> + fb->base.width, fb->base.height,
> sizes->fb_width, sizes->fb_height);
> - drm_framebuffer_put(_fb->base);
> - intel_fb = ifbdev->fb = NULL;
> + drm_framebuffer_put(>base);
> + fb = NULL;
> }
> - if (!intel_fb || drm_WARN_ON(dev, !intel_fb_obj(_fb->base))) {
> + if (!fb || drm_WARN_ON(dev, !intel_fb_obj(>base))) {
> drm_dbg_kms(_priv->drm,
> "no BIOS fb, allocating a new one\n");
> - intel_fb = intel_fbdev_fb_alloc(helper, sizes);
> - if (IS_ERR(intel_fb))
> - return PTR_ERR(intel_fb);
> - ifbdev->fb = intel_fb;
> + fb = intel_fbdev_fb_alloc(helper, sizes);
> + if (IS_ERR(fb))
> + return PTR_ERR(fb);
> } else {
> drm_dbg_kms(_priv->drm, "re-using BIOS fb\n");
> prealloc = true;
> - sizes->fb_width = intel_fb->base.width;
> - sizes->fb_height = intel_fb->base.height;
> + sizes->fb_width = fb->base.width;
> + sizes->fb_height = fb->base.height;
> }
>
> wakeref = intel_runtime_pm_get(_priv->runtime_pm);
> @@ -226,7 +227,7 @@ static int intelfb_create(struct drm_fb_helper *helper,
>* This also validates that any existing fb inherited from the
>* BIOS is suitable for own access.
>*/
> - vma = intel_pin_and_fence_fb_obj(>fb->base, false,
> + vma = intel_pin_and_fence_fb_obj(>base, false,
>, false, );
> if (IS_ERR(vma)) {
> ret = PTR_ERR(vma);
> @@ -240,11 +241,11 @@ static int intelfb_create(struct drm_fb_helper *helper,
> goto out_unpin;
> }
>
> - ifbdev->helper.fb = >fb->base;
> + ifbdev->helper.fb = >base;
>
> info->fbops = _ops;
>
> - obj = intel_fb_obj(_fb->base);
> + obj = intel_fb_obj(>base);
>
> ret = intel_fbdev_fb_fill_info(dev_priv, info, obj, vma);
> if (ret)
> @@ -262,8 +263,9 @@ static int intelfb_create(struct drm_fb_helper *helper,
> /* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */
>
> drm_dbg_kms(_priv->drm, "allocated %dx%d fb: 0x%08x\n",
> - ifbdev->fb->base.width, ifbdev->fb->base.height,
> + fb->base.width, fb->base.height,
> i915_ggtt_offset(vma));
> + ifbdev->fb = fb;
> ifbdev->vma = vma;
> ifbdev->vma_flags = flags;
--
Jani Nikula, Intel
Re: [PATCH v2 7/9] drm/i915: Change intel_fbdev_fb_alloc() return type
On Fri, 10 May 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Change intel_fbdev_fb_alloc() to return struct intel_fb instead
> of struct drm_framebuffer. Let's us eliminate some annoying
> aliasing variables in the fbdev setup code.
>
> v2: Assing the results to the correct variable (Jani)
> Fix xe's copy
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_fbdev.c| 9 -
> drivers/gpu/drm/i915/display/intel_fbdev_fb.c | 6 +++---
> drivers/gpu/drm/i915/display/intel_fbdev_fb.h | 4 ++--
> drivers/gpu/drm/xe/display/intel_fbdev_fb.c | 9 +
> 4 files changed, 14 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c
> b/drivers/gpu/drm/i915/display/intel_fbdev.c
> index bda702c2cab8..4bbbf481bb3a 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbdev.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
> @@ -207,13 +207,12 @@ static int intelfb_create(struct drm_fb_helper *helper,
> intel_fb = ifbdev->fb = NULL;
> }
> if (!intel_fb || drm_WARN_ON(dev, !intel_fb_obj(_fb->base))) {
> - struct drm_framebuffer *fb;
> drm_dbg_kms(_priv->drm,
> "no BIOS fb, allocating a new one\n");
> - fb = intel_fbdev_fb_alloc(helper, sizes);
> - if (IS_ERR(fb))
> - return PTR_ERR(fb);
> - intel_fb = ifbdev->fb = to_intel_framebuffer(fb);
> + intel_fb = intel_fbdev_fb_alloc(helper, sizes);
> + if (IS_ERR(intel_fb))
> + return PTR_ERR(intel_fb);
> + ifbdev->fb = intel_fb;
> } else {
> drm_dbg_kms(_priv->drm, "re-using BIOS fb\n");
> prealloc = true;
> diff --git a/drivers/gpu/drm/i915/display/intel_fbdev_fb.c
> b/drivers/gpu/drm/i915/display/intel_fbdev_fb.c
> index 0665f943f65f..497525ef9668 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbdev_fb.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbdev_fb.c
> @@ -11,8 +11,8 @@
> #include "intel_display_types.h"
> #include "intel_fbdev_fb.h"
>
> -struct drm_framebuffer *intel_fbdev_fb_alloc(struct drm_fb_helper *helper,
> - struct drm_fb_helper_surface_size
> *sizes)
> +struct intel_framebuffer *intel_fbdev_fb_alloc(struct drm_fb_helper *helper,
> +struct
> drm_fb_helper_surface_size *sizes)
> {
> struct drm_framebuffer *fb;
> struct drm_device *dev = helper->dev;
> @@ -63,7 +63,7 @@ struct drm_framebuffer *intel_fbdev_fb_alloc(struct
> drm_fb_helper *helper,
> fb = intel_framebuffer_create(obj, _cmd);
> i915_gem_object_put(obj);
>
> - return fb;
> + return to_intel_framebuffer(fb);
> }
>
> int intel_fbdev_fb_fill_info(struct drm_i915_private *i915, struct fb_info
> *info,
> diff --git a/drivers/gpu/drm/i915/display/intel_fbdev_fb.h
> b/drivers/gpu/drm/i915/display/intel_fbdev_fb.h
> index a395b2c65d33..4832fe688fbf 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbdev_fb.h
> +++ b/drivers/gpu/drm/i915/display/intel_fbdev_fb.h
> @@ -13,8 +13,8 @@ struct drm_i915_private;
> struct fb_info;
> struct i915_vma;
>
> -struct drm_framebuffer *intel_fbdev_fb_alloc(struct drm_fb_helper *helper,
> - struct drm_fb_helper_surface_size
> *sizes);
> +struct intel_framebuffer *intel_fbdev_fb_alloc(struct drm_fb_helper *helper,
> +struct
> drm_fb_helper_surface_size *sizes);
> int intel_fbdev_fb_fill_info(struct drm_i915_private *i915, struct fb_info
> *info,
>struct drm_i915_gem_object *obj, struct i915_vma
> *vma);
>
> diff --git a/drivers/gpu/drm/xe/display/intel_fbdev_fb.c
> b/drivers/gpu/drm/xe/display/intel_fbdev_fb.c
> index 9e4bcfdbc7e5..f6bf5896ff1b 100644
> --- a/drivers/gpu/drm/xe/display/intel_fbdev_fb.c
> +++ b/drivers/gpu/drm/xe/display/intel_fbdev_fb.c
> @@ -13,8 +13,8 @@
> #include "i915_drv.h"
> #include "intel_display_types.h"
>
> -struct drm_framebuffer *intel_fbdev_fb_alloc(struct drm_fb_helper *helper,
> - struct drm_fb_helper_surface_size *sizes)
> +struct intel_framebuffer *intel_fbdev_fb_alloc(struct drm_fb_helper *helper,
> +struct
> drm_fb_helper_surface_size *sizes)
> {
> struct drm_framebuffer *fb;
> struct drm_device *dev = helper->dev;
> @@ -70,10 +70,11 @@ struct drm_framebuffer *intel_fbdev_fb_alloc(struct
> drm_fb_helper *helper,
> }
>
> drm_gem_object_put(intel_bo_to_drm_bo(obj));
> - return fb;
> +
> + return to_intel_framebuffer(fb);
>
> err:
> - return fb;
> + return ERR_CAST(fb);
> }
>
> int intel_fbdev_fb_fill_info(struct drm_i915_private *i915, struct fb_info
> *info,
--
Jani Nikula, Intel
Re: [PATCH 1/2] drm/xe/display: remove unused xe->enabled_irq_mask
On 10-05-2024 15:13, Jani Nikula wrote:
The xe->enabled_irq_mask member has never been used for anything.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/xe/display/xe_display.c | 1 -
drivers/gpu/drm/xe/xe_device_types.h| 2 --
2 files changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/xe/display/xe_display.c
b/drivers/gpu/drm/xe/display/xe_display.c
index 0de0566e5b39..fbe2c2eddea9 100644
--- a/drivers/gpu/drm/xe/display/xe_display.c
+++ b/drivers/gpu/drm/xe/display/xe_display.c
@@ -97,7 +97,6 @@ int xe_display_create(struct xe_device *xe)
xe->display.hotplug.dp_wq = alloc_ordered_workqueue("xe-dp", 0);
drmm_mutex_init(>drm, >sb_lock);
- xe->enabled_irq_mask = ~0;
LGTM
Reviewed-by: Himal Prasad Ghimiray
Thanks
return drmm_add_action_or_reset(>drm, display_destroy, NULL);
}
diff --git a/drivers/gpu/drm/xe/xe_device_types.h
b/drivers/gpu/drm/xe/xe_device_types.h
index 906b98fb973b..b78223e3baab 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -517,8 +517,6 @@ struct xe_device {
/* only to allow build, not used functionally */
u32 irq_mask;
- u32 enabled_irq_mask;
-
struct intel_uncore {
spinlock_t lock;
} uncore;
Re: [PATCH 2/2] drm/xe/display: remove unused xe->sb_lock
On 10-05-2024 15:13, Jani Nikula wrote:
Nothing in xe needs xe->sb_lock. None of the i915 display code using
->sb_lock gets built with xe, and in any case that would be wrong as xe
uses gt->pcode.lock for this.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/xe/display/xe_display.c | 2 --
drivers/gpu/drm/xe/xe_device_types.h| 3 ---
2 files changed, 5 deletions(-)
diff --git a/drivers/gpu/drm/xe/display/xe_display.c
b/drivers/gpu/drm/xe/display/xe_display.c
index fbe2c2eddea9..a2c39bcc7677 100644
--- a/drivers/gpu/drm/xe/display/xe_display.c
+++ b/drivers/gpu/drm/xe/display/xe_display.c
@@ -96,8 +96,6 @@ int xe_display_create(struct xe_device *xe)
xe->display.hotplug.dp_wq = alloc_ordered_workqueue("xe-dp", 0);
- drmm_mutex_init(>drm, >sb_lock);
-
return drmm_add_action_or_reset(>drm, display_destroy, NULL);
}
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index b78223e3baab..5c5e36de452a 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -511,9 +511,6 @@ struct xe_device {
/* To shut up runtime pm macros.. */
struct xe_runtime_pm {} runtime_pm;
- /* For pcode */
- struct mutex sb_lock;
-
LGTM
Reviewed-by: Himal Prasad Ghimiray
A patch
[https://lore.kernel.org/all/buobxdew2jnbfblawfvnzwntexvhxkslqstsgp3xsxpexdtdem@gwnlli47tdkc/
] was introduced that added handling for the return value of
|drmm_mutex_init|for various display locks. As part of further
cleanup's, other locks initialization apart from |sb->lock|were
relocated to the display code. The current patch ensures we don't need
to address it anymore.
/* only to allow build, not used functionally */
u32 irq_mask;
Re: [PATCH 1/5] drm/i915: don't include CML PCI IDs in CFL
On Fri, 10 May 2024, Ville Syrjälä wrote:
> On Fri, May 10, 2024 at 01:24:12PM +0300, Jani Nikula wrote:
>> On Wed, 08 May 2024, Ville Syrjälä wrote:
>> > On Wed, May 08, 2024 at 02:45:10PM +0300, Jani Nikula wrote:
>> >> On Wed, 08 May 2024, Ville Syrjälä wrote:
>> >> > On Tue, May 07, 2024 at 09:47:16AM -0400, Rodrigo Vivi wrote:
>> >> >> On Tue, May 07, 2024 at 03:56:48PM +0300, Jani Nikula wrote:
>> >> >> > It's confusing for INTEL_CFL_IDS() to include all CML PCI IDs. Even
>> >> >> > if
>> >> >> > we treat them the same in a lot of places, CML is a platform of its
>> >> >> > own,
>> >> >> > and the lists of PCI IDs should not conflate them.
>>
>> [snip]
>>
>> >> >> Why only CML and not AML and WHL as well?
>> >> >
>> >> > Why do we even have CML as a separate platform? The only difference
>> >> > I can see is is that we do allow_read_ctx_timestamp() for CML but
>> >> > not for CFL. Does that even make sense?
>> >>
>> >> git blame tells me:
>> >>
>> >> 5f4ae2704d59 ("drm/i915: Identify Cometlake platform")
>> >> dbc7e72897a4 ("drm/i915/gt: Make the CTX_TIMESTAMP readable on !rcs")
>> >
>> > Right. That explains why we need it on CML+. But is there some reason
>> > we can't just do it on CFL as well, even if not strictly necessary?
>> > I would assume that setting FORCE_TO_NONPRIV on an already
>> > non-privileged register should be totally fine.
>>
>> I have absolutely no idea.
>>
>> I'm somewhat thinking "CML being a separate platform" is a separate
>> problem from "CFL PCI ID macros including CML".
>>
>> I'm starting to think the PCI ID macros should be grouped by "does the
>> platform have a name of its own",
>
> That and/or "does bspec have a separate 'Confgurations ' page?"
>
>> not by how those macros are actually
>> used by the driver. Keeping them separate at the PCI ID macro level just
>> reduces the pain in maintaining the PCI IDs, and lets us wiggle stuff
>> around in the driver how we see fit.
>
> Aye.
>
>>
>> And that spins back to Rodrigo's question, "Why only CML and not AML and
>> WHL as well?". Yeah, indeed.
>>
>> If we decide to stop treating CML as a separate platform in the
>> *driver*, that's another matter.
>
> Sure. Seeing it just got me wondering...
I sent a new series with just the PCI ID macro cleanups [1]. I meant to
Cc: you and Rodrigo, but forgot. :(
BR,
Jani.
[1] https://patchwork.freedesktop.org/series/133444/
--
Jani Nikula, Intel
[PATCH 8/8] drm/i915/pciids: don't include RPL-U PCI IDs in RPL-P
It's confusing for INTEL_RPLP_IDS() to include INTEL_RPLU_IDS(). Even if
we treat them the same elsewhere, the lists of PCI IDs should not.
Cc: Bjorn Helgaas
Cc: linux-...@vger.kernel.org
Reviewed-by: Rodrigo Vivi
Signed-off-by: Jani Nikula
---
arch/x86/kernel/early-quirks.c | 1 +
drivers/gpu/drm/i915/display/intel_display_device.c | 1 +
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/intel_device_info.c| 1 +
include/drm/i915_pciids.h | 1 -
5 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index b2b9cc3b9545..fd74d7f26f01 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -556,6 +556,7 @@ static const struct pci_device_id intel_early_ids[]
__initconst = {
INTEL_ADLP_IDS(_early_ops),
INTEL_ADLN_IDS(_early_ops),
INTEL_RPLS_IDS(_early_ops),
+ INTEL_RPLU_IDS(_early_ops),
INTEL_RPLP_IDS(_early_ops),
};
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
b/drivers/gpu/drm/i915/display/intel_display_device.c
index fb4c4054207e..89069cff06b4 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -841,6 +841,7 @@ static const struct {
INTEL_RPLS_IDS(_s_display),
INTEL_ADLP_IDS(_lpd_display),
INTEL_ADLN_IDS(_lpd_display),
+ INTEL_RPLU_IDS(_lpd_display),
INTEL_RPLP_IDS(_lpd_display),
INTEL_DG2_IDS(_hpd_display),
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index fa56113ed1ce..74202925d13f 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -867,6 +867,7 @@ static const struct pci_device_id pciidlist[] = {
INTEL_ADLN_IDS(_p_info),
INTEL_DG1_IDS(_info),
INTEL_RPLS_IDS(_s_info),
+ INTEL_RPLU_IDS(_p_info),
INTEL_RPLP_IDS(_p_info),
INTEL_DG2_IDS(_info),
INTEL_ATS_M_IDS(_m_info),
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index 64651a54a245..a39497971994 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -182,6 +182,7 @@ static const u16 subplatform_n_ids[] = {
static const u16 subplatform_rpl_ids[] = {
INTEL_RPLS_IDS(0),
+ INTEL_RPLU_IDS(0),
INTEL_RPLP_IDS(0),
};
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 42913d2eb655..04f6ca3dc5c1 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -717,7 +717,6 @@
/* RPL-P */
#define INTEL_RPLP_IDS(info) \
- INTEL_RPLU_IDS(info), \
INTEL_VGA_DEVICE(0xA720, info), \
INTEL_VGA_DEVICE(0xA7A0, info), \
INTEL_VGA_DEVICE(0xA7A8, info), \
--
2.39.2
[PATCH 7/8] drm/i915/pciids: remove 12 from INTEL_TGL_IDS()
Most other PCI ID macros do not encode the gen in the name. Follow suit
for TGL.
Cc: Bjorn Helgaas
Cc: linux-...@vger.kernel.org
Signed-off-by: Jani Nikula
---
arch/x86/kernel/early-quirks.c | 2 +-
drivers/gpu/drm/i915/display/intel_display_device.c | 2 +-
drivers/gpu/drm/i915/i915_pci.c | 2 +-
drivers/gpu/drm/i915/intel_device_info.c| 2 +-
include/drm/i915_pciids.h | 10 +-
5 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index c150bb6f1a39..b2b9cc3b9545 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -550,7 +550,7 @@ static const struct pci_device_id intel_early_ids[]
__initconst = {
INTEL_ICL_IDS(_early_ops),
INTEL_EHL_IDS(_early_ops),
INTEL_JSL_IDS(_early_ops),
- INTEL_TGL_12_IDS(_early_ops),
+ INTEL_TGL_IDS(_early_ops),
INTEL_RKL_IDS(_early_ops),
INTEL_ADLS_IDS(_early_ops),
INTEL_ADLP_IDS(_early_ops),
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
b/drivers/gpu/drm/i915/display/intel_display_device.c
index e47896002c13..fb4c4054207e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -834,7 +834,7 @@ static const struct {
INTEL_ICL_IDS(_display),
INTEL_EHL_IDS(_ehl_display),
INTEL_JSL_IDS(_ehl_display),
- INTEL_TGL_12_IDS(_display),
+ INTEL_TGL_IDS(_display),
INTEL_DG1_IDS(_display),
INTEL_RKL_IDS(_display),
INTEL_ADLS_IDS(_s_display),
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 06b1d50ae47c..fa56113ed1ce 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -860,7 +860,7 @@ static const struct pci_device_id pciidlist[] = {
INTEL_ICL_IDS(_info),
INTEL_EHL_IDS(_info),
INTEL_JSL_IDS(_info),
- INTEL_TGL_12_IDS(_info),
+ INTEL_TGL_IDS(_info),
INTEL_RKL_IDS(_info),
INTEL_ADLS_IDS(_s_info),
INTEL_ADLP_IDS(_p_info),
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index a0a43ea07f11..64651a54a245 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -173,7 +173,7 @@ static const u16 subplatform_portf_ids[] = {
};
static const u16 subplatform_uy_ids[] = {
- INTEL_TGL_12_GT2_IDS(0),
+ INTEL_TGL_GT2_IDS(0),
};
static const u16 subplatform_n_ids[] = {
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index ecfd7f71e2e7..42913d2eb655 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -620,12 +620,12 @@
INTEL_VGA_DEVICE(0x4E71, info)
/* TGL */
-#define INTEL_TGL_12_GT1_IDS(info) \
+#define INTEL_TGL_GT1_IDS(info) \
INTEL_VGA_DEVICE(0x9A60, info), \
INTEL_VGA_DEVICE(0x9A68, info), \
INTEL_VGA_DEVICE(0x9A70, info)
-#define INTEL_TGL_12_GT2_IDS(info) \
+#define INTEL_TGL_GT2_IDS(info) \
INTEL_VGA_DEVICE(0x9A40, info), \
INTEL_VGA_DEVICE(0x9A49, info), \
INTEL_VGA_DEVICE(0x9A59, info), \
@@ -635,9 +635,9 @@
INTEL_VGA_DEVICE(0x9AD9, info), \
INTEL_VGA_DEVICE(0x9AF8, info)
-#define INTEL_TGL_12_IDS(info) \
- INTEL_TGL_12_GT1_IDS(info), \
- INTEL_TGL_12_GT2_IDS(info)
+#define INTEL_TGL_IDS(info) \
+ INTEL_TGL_GT1_IDS(info), \
+ INTEL_TGL_GT2_IDS(info)
/* RKL */
#define INTEL_RKL_IDS(info) \
--
2.39.2
[PATCH 6/8] drm/i915/pciids: remove 11 from INTEL_ICL_IDS()
Most other PCI ID macros do not encode the gen in the name. Follow suit
for ICL.
Cc: Bjorn Helgaas
Cc: linux-...@vger.kernel.org
Signed-off-by: Jani Nikula
---
arch/x86/kernel/early-quirks.c | 2 +-
drivers/gpu/drm/i915/display/intel_display_device.c | 2 +-
drivers/gpu/drm/i915/i915_pci.c | 2 +-
include/drm/i915_pciids.h | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index 2b698a3f56ef..c150bb6f1a39 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -547,7 +547,7 @@ static const struct pci_device_id intel_early_ids[]
__initconst = {
INTEL_CML_IDS(_early_ops),
INTEL_GLK_IDS(_early_ops),
INTEL_CNL_IDS(_early_ops),
- INTEL_ICL_11_IDS(_early_ops),
+ INTEL_ICL_IDS(_early_ops),
INTEL_EHL_IDS(_early_ops),
INTEL_JSL_IDS(_early_ops),
INTEL_TGL_12_IDS(_early_ops),
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
b/drivers/gpu/drm/i915/display/intel_display_device.c
index 23909a8e2dc8..e47896002c13 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -831,7 +831,7 @@ static const struct {
INTEL_CFL_IDS(_display),
INTEL_WHL_IDS(_display),
INTEL_CML_IDS(_display),
- INTEL_ICL_11_IDS(_display),
+ INTEL_ICL_IDS(_display),
INTEL_EHL_IDS(_ehl_display),
INTEL_JSL_IDS(_ehl_display),
INTEL_TGL_12_IDS(_display),
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index d85f023afebe..06b1d50ae47c 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -857,7 +857,7 @@ static const struct pci_device_id pciidlist[] = {
INTEL_CML_GT2_IDS(_gt2_info),
INTEL_CML_U_GT1_IDS(_gt1_info),
INTEL_CML_U_GT2_IDS(_gt2_info),
- INTEL_ICL_11_IDS(_info),
+ INTEL_ICL_IDS(_info),
INTEL_EHL_IDS(_info),
INTEL_JSL_IDS(_info),
INTEL_TGL_12_IDS(_info),
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 0c5a20d59801..ecfd7f71e2e7 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -597,7 +597,7 @@
INTEL_VGA_DEVICE(0x8A70, info), \
INTEL_VGA_DEVICE(0x8A71, info)
-#define INTEL_ICL_11_IDS(info) \
+#define INTEL_ICL_IDS(info) \
INTEL_ICL_PORT_F_IDS(info), \
INTEL_VGA_DEVICE(0x8A51, info), \
INTEL_VGA_DEVICE(0x8A5D, info)
--
2.39.2
[PATCH 5/8] drm/i915/pciids: don't include WHL/CML PCI IDs in CFL
It's confusing for INTEL_CFL_IDS() to include all WHL and CML PCI
IDs. Even if we treat them the same in a lot of places, CML is a
platform of its own, and the lists of PCI IDs should not conflate them.
Largely go by the idea that if a platform has a name, group its PCI IDs
together.
That said, AML is special, having both KBL and CFL variants. Leave that
alone.
v2: Also split out WHL not just CML (Rodrigo)
Cc: Bjorn Helgaas
Cc: linux-...@vger.kernel.org
Signed-off-by: Jani Nikula
---
arch/x86/kernel/early-quirks.c| 2 ++
.../drm/i915/display/intel_display_device.c | 2 ++
include/drm/i915_pciids.h | 30 +++
3 files changed, 21 insertions(+), 13 deletions(-)
diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index 6549507003ec..2b698a3f56ef 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -543,6 +543,8 @@ static const struct pci_device_id intel_early_ids[]
__initconst = {
INTEL_BXT_IDS(_early_ops),
INTEL_KBL_IDS(_early_ops),
INTEL_CFL_IDS(_early_ops),
+ INTEL_WHL_IDS(_early_ops),
+ INTEL_CML_IDS(_early_ops),
INTEL_GLK_IDS(_early_ops),
INTEL_CNL_IDS(_early_ops),
INTEL_ICL_11_IDS(_early_ops),
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
b/drivers/gpu/drm/i915/display/intel_display_device.c
index bb681c8ed8a0..23909a8e2dc8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -829,6 +829,8 @@ static const struct {
INTEL_GLK_IDS(_display),
INTEL_KBL_IDS(_display),
INTEL_CFL_IDS(_display),
+ INTEL_WHL_IDS(_display),
+ INTEL_CML_IDS(_display),
INTEL_ICL_11_IDS(_display),
INTEL_EHL_IDS(_ehl_display),
INTEL_JSL_IDS(_ehl_display),
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 16778d92346b..0c5a20d59801 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -488,6 +488,12 @@
INTEL_VGA_DEVICE(0x9BCA, info), \
INTEL_VGA_DEVICE(0x9BCC, info)
+#define INTEL_CML_IDS(info) \
+ INTEL_CML_GT1_IDS(info), \
+ INTEL_CML_GT2_IDS(info), \
+ INTEL_CML_U_GT1_IDS(info), \
+ INTEL_CML_U_GT2_IDS(info)
+
#define INTEL_KBL_IDS(info) \
INTEL_KBL_GT1_IDS(info), \
INTEL_KBL_GT2_IDS(info), \
@@ -527,6 +533,15 @@
INTEL_VGA_DEVICE(0x3EA7, info), /* ULT GT3 */ \
INTEL_VGA_DEVICE(0x3EA8, info) /* ULT GT3 */
+#define INTEL_CFL_IDS(info) \
+ INTEL_CFL_S_GT1_IDS(info), \
+ INTEL_CFL_S_GT2_IDS(info), \
+ INTEL_CFL_H_GT1_IDS(info), \
+ INTEL_CFL_H_GT2_IDS(info), \
+ INTEL_CFL_U_GT2_IDS(info), \
+ INTEL_CFL_U_GT3_IDS(info), \
+ INTEL_AML_CFL_GT2_IDS(info)
+
/* WHL/CFL U GT1 */
#define INTEL_WHL_U_GT1_IDS(info) \
INTEL_VGA_DEVICE(0x3EA1, info), \
@@ -541,21 +556,10 @@
#define INTEL_WHL_U_GT3_IDS(info) \
INTEL_VGA_DEVICE(0x3EA2, info)
-#define INTEL_CFL_IDS(info) \
- INTEL_CFL_S_GT1_IDS(info), \
- INTEL_CFL_S_GT2_IDS(info), \
- INTEL_CFL_H_GT1_IDS(info), \
- INTEL_CFL_H_GT2_IDS(info), \
- INTEL_CFL_U_GT2_IDS(info), \
- INTEL_CFL_U_GT3_IDS(info), \
+#define INTEL_WHL_IDS(info) \
INTEL_WHL_U_GT1_IDS(info), \
INTEL_WHL_U_GT2_IDS(info), \
- INTEL_WHL_U_GT3_IDS(info), \
- INTEL_AML_CFL_GT2_IDS(info), \
- INTEL_CML_GT1_IDS(info), \
- INTEL_CML_GT2_IDS(info), \
- INTEL_CML_U_GT1_IDS(info), \
- INTEL_CML_U_GT2_IDS(info)
+ INTEL_WHL_U_GT3_IDS(info)
/* CNL */
#define INTEL_CNL_PORT_F_IDS(info) \
--
2.39.2
[PATCH 3/8] drm/i915/pciids: add INTEL_SNB_IDS()
Add INTEL_SNB_IDS() to identify all SNBs.
Cc: Bjorn Helgaas
Cc: linux-...@vger.kernel.org
Signed-off-by: Jani Nikula
---
arch/x86/kernel/early-quirks.c | 3 +--
drivers/gpu/drm/i915/display/intel_display_device.c | 3 +--
include/drm/i915_pciids.h | 4
3 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index d8419d310091..23ded9260302 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -534,8 +534,7 @@ static const struct pci_device_id intel_early_ids[]
__initconst = {
INTEL_GM45_IDS(_early_ops),
INTEL_G45_IDS(_early_ops),
INTEL_ILK_IDS(_early_ops),
- INTEL_SNB_D_IDS(_early_ops),
- INTEL_SNB_M_IDS(_early_ops),
+ INTEL_SNB_IDS(_early_ops),
INTEL_IVB_M_IDS(_early_ops),
INTEL_IVB_D_IDS(_early_ops),
INTEL_HSW_IDS(_early_ops),
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
b/drivers/gpu/drm/i915/display/intel_display_device.c
index 052fd1c290c3..c40d12ca386a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -818,8 +818,7 @@ static const struct {
INTEL_PNV_IDS(_display),
INTEL_ILK_D_IDS(_d_display),
INTEL_ILK_M_IDS(_m_display),
- INTEL_SNB_D_IDS(_display),
- INTEL_SNB_M_IDS(_display),
+ INTEL_SNB_IDS(_display),
INTEL_IVB_M_IDS(_display),
INTEL_IVB_D_IDS(_display),
INTEL_HSW_IDS(_display),
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 05f466ca8ce2..0d48c493dcce 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -151,6 +151,10 @@
INTEL_SNB_M_GT1_IDS(info), \
INTEL_SNB_M_GT2_IDS(info)
+#define INTEL_SNB_IDS(info) \
+ INTEL_SNB_D_IDS(info), \
+ INTEL_SNB_M_IDS(info)
+
#define INTEL_IVB_M_GT1_IDS(info) \
INTEL_VGA_DEVICE(0x0156, info) /* GT1 mobile */
--
2.39.2
[PATCH 4/8] drm/i915/pciids: add INTEL_IVB_IDS()
Add INTEL_IVB_IDS() to identify all IVBs except IVB Q transcode.
Cc: Bjorn Helgaas
Cc: linux-...@vger.kernel.org
Signed-off-by: Jani Nikula
---
arch/x86/kernel/early-quirks.c | 3 +--
drivers/gpu/drm/i915/display/intel_display_device.c | 3 +--
include/drm/i915_pciids.h | 4
3 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index 23ded9260302..6549507003ec 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -535,8 +535,7 @@ static const struct pci_device_id intel_early_ids[]
__initconst = {
INTEL_G45_IDS(_early_ops),
INTEL_ILK_IDS(_early_ops),
INTEL_SNB_IDS(_early_ops),
- INTEL_IVB_M_IDS(_early_ops),
- INTEL_IVB_D_IDS(_early_ops),
+ INTEL_IVB_IDS(_early_ops),
INTEL_HSW_IDS(_early_ops),
INTEL_BDW_IDS(_early_ops),
INTEL_CHV_IDS(_early_ops),
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
b/drivers/gpu/drm/i915/display/intel_display_device.c
index c40d12ca386a..bb681c8ed8a0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -819,8 +819,7 @@ static const struct {
INTEL_ILK_D_IDS(_d_display),
INTEL_ILK_M_IDS(_m_display),
INTEL_SNB_IDS(_display),
- INTEL_IVB_M_IDS(_display),
- INTEL_IVB_D_IDS(_display),
+ INTEL_IVB_IDS(_display),
INTEL_HSW_IDS(_display),
INTEL_VLV_IDS(_display),
INTEL_BDW_IDS(_display),
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 0d48c493dcce..16778d92346b 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -177,6 +177,10 @@
INTEL_IVB_D_GT1_IDS(info), \
INTEL_IVB_D_GT2_IDS(info)
+#define INTEL_IVB_IDS(info) \
+ INTEL_IVB_M_IDS(info), \
+ INTEL_IVB_D_IDS(info)
+
#define INTEL_IVB_Q_IDS(info) \
INTEL_QUANTA_VGA_DEVICE(info) /* Quanta transcode */
--
2.39.2
[PATCH 2/8] drm/i915/pciids: add INTEL_ILK_IDS(), use acronym
Most other PCI ID macros use platform acronyms. Follow suit for ILK. Add
INTEL_ILK_IDS() to identify all ILKs.
Cc: Bjorn Helgaas
Cc: linux-...@vger.kernel.org
Signed-off-by: Jani Nikula
---
arch/x86/kernel/early-quirks.c | 3 +--
drivers/gpu/drm/i915/display/intel_display_device.c | 4 ++--
drivers/gpu/drm/i915/i915_pci.c | 4 ++--
include/drm/i915_pciids.h | 8 ++--
4 files changed, 11 insertions(+), 8 deletions(-)
diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index f50394a00fca..d8419d310091 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -533,8 +533,7 @@ static const struct pci_device_id intel_early_ids[]
__initconst = {
INTEL_I965GM_IDS(_early_ops),
INTEL_GM45_IDS(_early_ops),
INTEL_G45_IDS(_early_ops),
- INTEL_IRONLAKE_D_IDS(_early_ops),
- INTEL_IRONLAKE_M_IDS(_early_ops),
+ INTEL_ILK_IDS(_early_ops),
INTEL_SNB_D_IDS(_early_ops),
INTEL_SNB_M_IDS(_early_ops),
INTEL_IVB_M_IDS(_early_ops),
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
b/drivers/gpu/drm/i915/display/intel_display_device.c
index 0e0f5a36507d..052fd1c290c3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -816,8 +816,8 @@ static const struct {
INTEL_GM45_IDS(_display),
INTEL_G45_IDS(_display),
INTEL_PNV_IDS(_display),
- INTEL_IRONLAKE_D_IDS(_d_display),
- INTEL_IRONLAKE_M_IDS(_m_display),
+ INTEL_ILK_D_IDS(_d_display),
+ INTEL_ILK_M_IDS(_m_display),
INTEL_SNB_D_IDS(_display),
INTEL_SNB_M_IDS(_display),
INTEL_IVB_M_IDS(_display),
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index aa8593d73198..d85f023afebe 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -812,8 +812,8 @@ static const struct pci_device_id pciidlist[] = {
INTEL_G45_IDS(_info),
INTEL_PNV_G_IDS(_g_info),
INTEL_PNV_M_IDS(_m_info),
- INTEL_IRONLAKE_D_IDS(_d_info),
- INTEL_IRONLAKE_M_IDS(_m_info),
+ INTEL_ILK_D_IDS(_d_info),
+ INTEL_ILK_M_IDS(_m_info),
INTEL_SNB_D_GT1_IDS(_d_gt1_info),
INTEL_SNB_D_GT2_IDS(_d_gt2_info),
INTEL_SNB_M_GT1_IDS(_m_gt1_info),
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 21942a3c823b..05f466ca8ce2 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -118,12 +118,16 @@
INTEL_PNV_G_IDS(info), \
INTEL_PNV_M_IDS(info)
-#define INTEL_IRONLAKE_D_IDS(info) \
+#define INTEL_ILK_D_IDS(info) \
INTEL_VGA_DEVICE(0x0042, info)
-#define INTEL_IRONLAKE_M_IDS(info) \
+#define INTEL_ILK_M_IDS(info) \
INTEL_VGA_DEVICE(0x0046, info)
+#define INTEL_ILK_IDS(info) \
+ INTEL_ILK_D_IDS(info), \
+ INTEL_ILK_M_IDS(info)
+
#define INTEL_SNB_D_GT1_IDS(info) \
INTEL_VGA_DEVICE(0x0102, info), \
INTEL_VGA_DEVICE(0x010A, info)
--
2.39.2
[PATCH 1/8] drm/i915/pciids: add INTEL_PNV_IDS(), use acronym
Most other PCI ID macros use platform acronyms. Follow suit for PNV. Add
INTEL_PNV_IDS() to identify all PNVs.
Cc: Bjorn Helgaas
Cc: linux-...@vger.kernel.org
Signed-off-by: Jani Nikula
---
arch/x86/kernel/early-quirks.c | 3 +--
drivers/gpu/drm/i915/display/intel_display_device.c | 3 +--
drivers/gpu/drm/i915/i915_pci.c | 4 ++--
include/drm/i915_pciids.h | 8 ++--
4 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index 59f4aefc6bc1..f50394a00fca 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -527,8 +527,7 @@ static const struct pci_device_id intel_early_ids[]
__initconst = {
INTEL_I945G_IDS(_early_ops),
INTEL_I945GM_IDS(_early_ops),
INTEL_VLV_IDS(_early_ops),
- INTEL_PINEVIEW_G_IDS(_early_ops),
- INTEL_PINEVIEW_M_IDS(_early_ops),
+ INTEL_PNV_IDS(_early_ops),
INTEL_I965G_IDS(_early_ops),
INTEL_G33_IDS(_early_ops),
INTEL_I965GM_IDS(_early_ops),
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
b/drivers/gpu/drm/i915/display/intel_display_device.c
index 56a2e17d7d9e..0e0f5a36507d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -815,8 +815,7 @@ static const struct {
INTEL_I965GM_IDS(_display),
INTEL_GM45_IDS(_display),
INTEL_G45_IDS(_display),
- INTEL_PINEVIEW_G_IDS(_display),
- INTEL_PINEVIEW_M_IDS(_display),
+ INTEL_PNV_IDS(_display),
INTEL_IRONLAKE_D_IDS(_d_display),
INTEL_IRONLAKE_M_IDS(_m_display),
INTEL_SNB_D_IDS(_display),
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index b5a056c9cb79..aa8593d73198 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -810,8 +810,8 @@ static const struct pci_device_id pciidlist[] = {
INTEL_I965GM_IDS(_info),
INTEL_GM45_IDS(_info),
INTEL_G45_IDS(_info),
- INTEL_PINEVIEW_G_IDS(_g_info),
- INTEL_PINEVIEW_M_IDS(_m_info),
+ INTEL_PNV_G_IDS(_g_info),
+ INTEL_PNV_M_IDS(_m_info),
INTEL_IRONLAKE_D_IDS(_d_info),
INTEL_IRONLAKE_M_IDS(_m_info),
INTEL_SNB_D_GT1_IDS(_d_gt1_info),
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 85ce33ad6e26..21942a3c823b 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -108,12 +108,16 @@
INTEL_VGA_DEVICE(0x2e42, info), /* B43_G */ \
INTEL_VGA_DEVICE(0x2e92, info) /* B43_G.1 */
-#define INTEL_PINEVIEW_G_IDS(info) \
+#define INTEL_PNV_G_IDS(info) \
INTEL_VGA_DEVICE(0xa001, info)
-#define INTEL_PINEVIEW_M_IDS(info) \
+#define INTEL_PNV_M_IDS(info) \
INTEL_VGA_DEVICE(0xa011, info)
+#define INTEL_PNV_IDS(info) \
+ INTEL_PNV_G_IDS(info), \
+ INTEL_PNV_M_IDS(info)
+
#define INTEL_IRONLAKE_D_IDS(info) \
INTEL_VGA_DEVICE(0x0042, info)
--
2.39.2
[PATCH 0/8] drm/i915/pciids: PCI ID macro cleanups
This is a spin-off from [1], including just the PCI ID macro cleanups, as well as adding a bunch more cleanups. BR, Jani. [1] https://lore.kernel.org/all/cover.1715086509.git.jani.nik...@intel.com/ Jani Nikula (8): drm/i915/pciids: add INTEL_PNV_IDS(), use acronym drm/i915/pciids: add INTEL_ILK_IDS(), use acronym drm/i915/pciids: add INTEL_SNB_IDS() drm/i915/pciids: add INTEL_IVB_IDS() drm/i915/pciids: don't include WHL/CML PCI IDs in CFL drm/i915/pciids: remove 11 from INTEL_ICL_IDS() drm/i915/pciids: remove 12 from INTEL_TGL_IDS() drm/i915/pciids: don't include RPL-U PCI IDs in RPL-P arch/x86/kernel/early-quirks.c| 19 +++--- .../drm/i915/display/intel_display_device.c | 20 +++--- drivers/gpu/drm/i915/i915_pci.c | 13 ++-- drivers/gpu/drm/i915/intel_device_info.c | 3 +- include/drm/i915_pciids.h | 67 --- 5 files changed, 71 insertions(+), 51 deletions(-) -- 2.39.2
RE: [PATCH v10 08/12] drm/i915/psr: Panel replay uses SRD_STATUS to track it's status
> -Original Message-
> From: Hogander, Jouni
> Sent: Friday, May 10, 2024 3:08 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Hogander, Jouni
>
> Subject: [PATCH v10 08/12] drm/i915/psr: Panel replay uses SRD_STATUS to
> track it's status
>
> DP Panel replay uses SRD_STATUS to track it's status despite selective update
> mode.
>
> Bspec: 53370, 68920
>
> v4:
> - use PSR2_STATUS for eDP Panel Replay
> - handle intel_psr_wait_exit_locked as well
> v3:
> - do not use PSR2_STATUS for PSR1
> v2:
> - use intel_dp_is_edp to differentiate
> - modify debugfs status as well
>
> Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 20
> 1 file changed, 16 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 6d1f442f3d14..532a80a3eeea 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -2111,7 +2111,8 @@ static void intel_psr_wait_exit_locked(struct
> intel_dp *intel_dp)
> i915_reg_t psr_status;
> u32 psr_status_mask;
>
> - if (intel_dp->psr.sel_update_enabled) {
> + if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled
> ||
> + intel_dp-
> >psr.panel_replay_enabled)) {
> psr_status = EDP_PSR2_STATUS(dev_priv, cpu_transcoder);
> psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
> } else {
> @@ -2849,6 +2850,13 @@ static int
> _psr1_ready_for_pipe_update_locked(struct intel_dp *intel_dp)
> EDP_PSR_STATUS_STATE_MASK, 50); }
>
> +static int _panel_replay_ready_for_pipe_update_locked(struct intel_dp
> +*intel_dp) {
> + return intel_dp_is_edp(intel_dp) ?
> + _psr2_ready_for_pipe_update_locked(intel_dp) :
> + _psr1_ready_for_pipe_update_locked(intel_dp);
> +}
> +
> /**
> * intel_psr_wait_for_idle_locked - wait for PSR be ready for a pipe update
> * @new_crtc_state: new CRTC state
> @@ -2874,7 +2882,9 @@ void intel_psr_wait_for_idle_locked(const struct
> intel_crtc_state *new_crtc_stat
> if (!intel_dp->psr.enabled)
> continue;
>
> - if (intel_dp->psr.sel_update_enabled)
> + if (intel_dp->psr.panel_replay_enabled)
> + ret =
> _panel_replay_ready_for_pipe_update_locked(intel_dp);
> + else if (intel_dp->psr.sel_update_enabled)
> ret =
> _psr2_ready_for_pipe_update_locked(intel_dp);
> else
> ret =
> _psr1_ready_for_pipe_update_locked(intel_dp);
> @@ -2895,7 +2905,8 @@ static bool __psr_wait_for_idle_locked(struct
> intel_dp *intel_dp)
> if (!intel_dp->psr.enabled)
> return false;
>
> - if (intel_dp->psr.sel_update_enabled) {
> + if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled
> ||
> + intel_dp-
> >psr.panel_replay_enabled)) {
> reg = EDP_PSR2_STATUS(dev_priv, cpu_transcoder);
> mask = EDP_PSR2_STATUS_STATE_MASK;
> } else {
> @@ -3517,7 +3528,8 @@ psr_source_status(struct intel_dp *intel_dp, struct
> seq_file *m)
> const char *status = "unknown";
> u32 val, status_val;
>
> - if (intel_dp->psr.sel_update_enabled) {
> + if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled
> ||
> + intel_dp-
> >psr.panel_replay_enabled)) {
> static const char * const live_status[] = {
> "IDLE",
> "CAPTURE",
> --
> 2.34.1
✓ Fi.CI.BAT: success for Documentation/i915: remove kernel-doc for DMC wakelocks
== Series Details == Series: Documentation/i915: remove kernel-doc for DMC wakelocks URL : https://patchwork.freedesktop.org/series/133435/ State : success == Summary == CI Bug Log - changes from CI_DRM_14746 -> Patchwork_133435v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133435v1/index.html Participating hosts (40 -> 38) -- Additional (1): fi-kbl-8809g Missing(3): bat-dg1-7 bat-dg2-11 fi-snb-2520m Known issues Here are the changes found in Patchwork_133435v1 that come from known issues: ### IGT changes ### Issues hit * igt@gem_huc_copy@huc-copy: - fi-kbl-8809g: NOTRUN -> [SKIP][1] ([i915#2190]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133435v1/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-kbl-8809g: NOTRUN -> [SKIP][2] ([i915#4613]) +3 other tests skip [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133435v1/fi-kbl-8809g/igt@gem_lmem_swapp...@basic.html * igt@kms_force_connector_basic@force-load-detect: - fi-kbl-8809g: NOTRUN -> [SKIP][3] +30 other tests skip [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133435v1/fi-kbl-8809g/igt@kms_force_connector_ba...@force-load-detect.html Possible fixes * igt@gem_lmem_swapping@basic@lmem0: - bat-atsm-1: [FAIL][4] ([i915#10378]) -> [PASS][5] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14746/bat-atsm-1/igt@gem_lmem_swapping@ba...@lmem0.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133435v1/bat-atsm-1/igt@gem_lmem_swapping@ba...@lmem0.html [i915#10378]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10378 [i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190 [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613 Build changes - * Linux: CI_DRM_14746 -> Patchwork_133435v1 CI-20190529: 20190529 CI_DRM_14746: 0c99ca6cc719cf585be5945a455b68b66313b427 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7846: 4a5fd4e7cb2798636f6464e2bd61399f3242b322 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_133435v1: 0c99ca6cc719cf585be5945a455b68b66313b427 @ git://anongit.freedesktop.org/gfx-ci/linux == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133435v1/index.html
Re: [PATCH 1/5] drm/i915: don't include CML PCI IDs in CFL
On Fri, May 10, 2024 at 01:24:12PM +0300, Jani Nikula wrote:
> On Wed, 08 May 2024, Ville Syrjälä wrote:
> > On Wed, May 08, 2024 at 02:45:10PM +0300, Jani Nikula wrote:
> >> On Wed, 08 May 2024, Ville Syrjälä wrote:
> >> > On Tue, May 07, 2024 at 09:47:16AM -0400, Rodrigo Vivi wrote:
> >> >> On Tue, May 07, 2024 at 03:56:48PM +0300, Jani Nikula wrote:
> >> >> > It's confusing for INTEL_CFL_IDS() to include all CML PCI IDs. Even if
> >> >> > we treat them the same in a lot of places, CML is a platform of its
> >> >> > own,
> >> >> > and the lists of PCI IDs should not conflate them.
>
> [snip]
>
> >> >> Why only CML and not AML and WHL as well?
> >> >
> >> > Why do we even have CML as a separate platform? The only difference
> >> > I can see is is that we do allow_read_ctx_timestamp() for CML but
> >> > not for CFL. Does that even make sense?
> >>
> >> git blame tells me:
> >>
> >> 5f4ae2704d59 ("drm/i915: Identify Cometlake platform")
> >> dbc7e72897a4 ("drm/i915/gt: Make the CTX_TIMESTAMP readable on !rcs")
> >
> > Right. That explains why we need it on CML+. But is there some reason
> > we can't just do it on CFL as well, even if not strictly necessary?
> > I would assume that setting FORCE_TO_NONPRIV on an already
> > non-privileged register should be totally fine.
>
> I have absolutely no idea.
>
> I'm somewhat thinking "CML being a separate platform" is a separate
> problem from "CFL PCI ID macros including CML".
>
> I'm starting to think the PCI ID macros should be grouped by "does the
> platform have a name of its own",
That and/or "does bspec have a separate 'Confgurations ' page?"
> not by how those macros are actually
> used by the driver. Keeping them separate at the PCI ID macro level just
> reduces the pain in maintaining the PCI IDs, and lets us wiggle stuff
> around in the driver how we see fit.
Aye.
>
> And that spins back to Rodrigo's question, "Why only CML and not AML and
> WHL as well?". Yeah, indeed.
>
> If we decide to stop treating CML as a separate platform in the
> *driver*, that's another matter.
Sure. Seeing it just got me wondering...
--
Ville Syrjälä
Intel
Re: [PATCH v10 05/12] drm/panelreplay: dpcd register definition for panelreplay SU
On Fri, 2024-05-10 at 12:45 +0300, Jani Nikula wrote: > On Fri, 10 May 2024, Jouni Högander wrote: > > Add definitions for panel replay selective update > > > > v2: Remove unnecessary Cc from commit message > > > > Signed-off-by: Jouni Högander > > Reviewed-by: Animesh Manna > > Needs to be Cc: dri-devel. Just sent it separately. Thank you for pointing this out. BR, Jouni Högander > > > --- > > include/drm/display/drm_dp.h | 6 ++ > > 1 file changed, 6 insertions(+) > > > > diff --git a/include/drm/display/drm_dp.h > > b/include/drm/display/drm_dp.h > > index 0b032faa8cf2..906949ca3cee 100644 > > --- a/include/drm/display/drm_dp.h > > +++ b/include/drm/display/drm_dp.h > > @@ -548,6 +548,12 @@ > > # define DP_PANEL_REPLAY_SUPPORT (1 << 0) > > # define DP_PANEL_REPLAY_SU_SUPPORT (1 << 1) > > > > +#define DP_PANEL_PANEL_REPLAY_CAPABILITY 0xb1 > > +# define DP_PANEL_PANEL_REPLAY_SU_GRANULARITY_REQUIRED (1 << 5) > > + > > +#define DP_PANEL_PANEL_REPLAY_X_GRANULARITY0xb2 > > +#define DP_PANEL_PANEL_REPLAY_Y_GRANULARITY0xb4 > > + > > /* Link Configuration */ > > #defineDP_LINK_BW_SET 0x100 > > # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */ >
Re: [PATCH 1/5] drm/i915: don't include CML PCI IDs in CFL
On Wed, 08 May 2024, Ville Syrjälä wrote:
> On Wed, May 08, 2024 at 02:45:10PM +0300, Jani Nikula wrote:
>> On Wed, 08 May 2024, Ville Syrjälä wrote:
>> > On Tue, May 07, 2024 at 09:47:16AM -0400, Rodrigo Vivi wrote:
>> >> On Tue, May 07, 2024 at 03:56:48PM +0300, Jani Nikula wrote:
>> >> > It's confusing for INTEL_CFL_IDS() to include all CML PCI IDs. Even if
>> >> > we treat them the same in a lot of places, CML is a platform of its own,
>> >> > and the lists of PCI IDs should not conflate them.
[snip]
>> >> Why only CML and not AML and WHL as well?
>> >
>> > Why do we even have CML as a separate platform? The only difference
>> > I can see is is that we do allow_read_ctx_timestamp() for CML but
>> > not for CFL. Does that even make sense?
>>
>> git blame tells me:
>>
>> 5f4ae2704d59 ("drm/i915: Identify Cometlake platform")
>> dbc7e72897a4 ("drm/i915/gt: Make the CTX_TIMESTAMP readable on !rcs")
>
> Right. That explains why we need it on CML+. But is there some reason
> we can't just do it on CFL as well, even if not strictly necessary?
> I would assume that setting FORCE_TO_NONPRIV on an already
> non-privileged register should be totally fine.
I have absolutely no idea.
I'm somewhat thinking "CML being a separate platform" is a separate
problem from "CFL PCI ID macros including CML".
I'm starting to think the PCI ID macros should be grouped by "does the
platform have a name of its own", not by how those macros are actually
used by the driver. Keeping them separate at the PCI ID macro level just
reduces the pain in maintaining the PCI IDs, and lets us wiggle stuff
around in the driver how we see fit.
And that spins back to Rodrigo's question, "Why only CML and not AML and
WHL as well?". Yeah, indeed.
If we decide to stop treating CML as a separate platform in the
*driver*, that's another matter.
BR,
Jani.
--
Jani Nikula, Intel
[PATCH v2 8/9] drm/i915: Cleanup fbdev fb setup
From: Ville Syrjälä
We use a mix of 'intel_fb' vs. 'ifbdev->fb' in the same function.
Both should be pointing at the same thing. Make things less
confusing by just getting existing fb from 'ifbdev->fb' at the
start and then sticking with the local 'fb' (renamed from the
'intel_fb') until the very end.
v2: rebase
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fbdev.c | 38 --
1 file changed, 20 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c
b/drivers/gpu/drm/i915/display/intel_fbdev.c
index 4bbbf481bb3a..e898018ab76a 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -175,7 +175,7 @@ static int intelfb_create(struct drm_fb_helper *helper,
struct drm_fb_helper_surface_size *sizes)
{
struct intel_fbdev *ifbdev = to_intel_fbdev(helper);
- struct intel_framebuffer *intel_fb = ifbdev->fb;
+ struct intel_framebuffer *fb = ifbdev->fb;
struct drm_device *dev = helper->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
const struct i915_gtt_view view = {
@@ -195,29 +195,30 @@ static int intelfb_create(struct drm_fb_helper *helper,
if (ret)
return ret;
- if (intel_fb &&
- (sizes->fb_width > intel_fb->base.width ||
-sizes->fb_height > intel_fb->base.height)) {
+ ifbdev->fb = NULL;
+
+ if (fb &&
+ (sizes->fb_width > fb->base.width ||
+sizes->fb_height > fb->base.height)) {
drm_dbg_kms(_priv->drm,
"BIOS fb too small (%dx%d), we require (%dx%d),"
" releasing it\n",
- intel_fb->base.width, intel_fb->base.height,
+ fb->base.width, fb->base.height,
sizes->fb_width, sizes->fb_height);
- drm_framebuffer_put(_fb->base);
- intel_fb = ifbdev->fb = NULL;
+ drm_framebuffer_put(>base);
+ fb = NULL;
}
- if (!intel_fb || drm_WARN_ON(dev, !intel_fb_obj(_fb->base))) {
+ if (!fb || drm_WARN_ON(dev, !intel_fb_obj(>base))) {
drm_dbg_kms(_priv->drm,
"no BIOS fb, allocating a new one\n");
- intel_fb = intel_fbdev_fb_alloc(helper, sizes);
- if (IS_ERR(intel_fb))
- return PTR_ERR(intel_fb);
- ifbdev->fb = intel_fb;
+ fb = intel_fbdev_fb_alloc(helper, sizes);
+ if (IS_ERR(fb))
+ return PTR_ERR(fb);
} else {
drm_dbg_kms(_priv->drm, "re-using BIOS fb\n");
prealloc = true;
- sizes->fb_width = intel_fb->base.width;
- sizes->fb_height = intel_fb->base.height;
+ sizes->fb_width = fb->base.width;
+ sizes->fb_height = fb->base.height;
}
wakeref = intel_runtime_pm_get(_priv->runtime_pm);
@@ -226,7 +227,7 @@ static int intelfb_create(struct drm_fb_helper *helper,
* This also validates that any existing fb inherited from the
* BIOS is suitable for own access.
*/
- vma = intel_pin_and_fence_fb_obj(>fb->base, false,
+ vma = intel_pin_and_fence_fb_obj(>base, false,
, false, );
if (IS_ERR(vma)) {
ret = PTR_ERR(vma);
@@ -240,11 +241,11 @@ static int intelfb_create(struct drm_fb_helper *helper,
goto out_unpin;
}
- ifbdev->helper.fb = >fb->base;
+ ifbdev->helper.fb = >base;
info->fbops = _ops;
- obj = intel_fb_obj(_fb->base);
+ obj = intel_fb_obj(>base);
ret = intel_fbdev_fb_fill_info(dev_priv, info, obj, vma);
if (ret)
@@ -262,8 +263,9 @@ static int intelfb_create(struct drm_fb_helper *helper,
/* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */
drm_dbg_kms(_priv->drm, "allocated %dx%d fb: 0x%08x\n",
- ifbdev->fb->base.width, ifbdev->fb->base.height,
+ fb->base.width, fb->base.height,
i915_ggtt_offset(vma));
+ ifbdev->fb = fb;
ifbdev->vma = vma;
ifbdev->vma_flags = flags;
--
2.43.2
[PATCH v2 7/9] drm/i915: Change intel_fbdev_fb_alloc() return type
From: Ville Syrjälä
Change intel_fbdev_fb_alloc() to return struct intel_fb instead
of struct drm_framebuffer. Let's us eliminate some annoying
aliasing variables in the fbdev setup code.
v2: Assing the results to the correct variable (Jani)
Fix xe's copy
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fbdev.c| 9 -
drivers/gpu/drm/i915/display/intel_fbdev_fb.c | 6 +++---
drivers/gpu/drm/i915/display/intel_fbdev_fb.h | 4 ++--
drivers/gpu/drm/xe/display/intel_fbdev_fb.c | 9 +
4 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c
b/drivers/gpu/drm/i915/display/intel_fbdev.c
index bda702c2cab8..4bbbf481bb3a 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -207,13 +207,12 @@ static int intelfb_create(struct drm_fb_helper *helper,
intel_fb = ifbdev->fb = NULL;
}
if (!intel_fb || drm_WARN_ON(dev, !intel_fb_obj(_fb->base))) {
- struct drm_framebuffer *fb;
drm_dbg_kms(_priv->drm,
"no BIOS fb, allocating a new one\n");
- fb = intel_fbdev_fb_alloc(helper, sizes);
- if (IS_ERR(fb))
- return PTR_ERR(fb);
- intel_fb = ifbdev->fb = to_intel_framebuffer(fb);
+ intel_fb = intel_fbdev_fb_alloc(helper, sizes);
+ if (IS_ERR(intel_fb))
+ return PTR_ERR(intel_fb);
+ ifbdev->fb = intel_fb;
} else {
drm_dbg_kms(_priv->drm, "re-using BIOS fb\n");
prealloc = true;
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev_fb.c
b/drivers/gpu/drm/i915/display/intel_fbdev_fb.c
index 0665f943f65f..497525ef9668 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev_fb.c
@@ -11,8 +11,8 @@
#include "intel_display_types.h"
#include "intel_fbdev_fb.h"
-struct drm_framebuffer *intel_fbdev_fb_alloc(struct drm_fb_helper *helper,
-struct drm_fb_helper_surface_size
*sizes)
+struct intel_framebuffer *intel_fbdev_fb_alloc(struct drm_fb_helper *helper,
+ struct
drm_fb_helper_surface_size *sizes)
{
struct drm_framebuffer *fb;
struct drm_device *dev = helper->dev;
@@ -63,7 +63,7 @@ struct drm_framebuffer *intel_fbdev_fb_alloc(struct
drm_fb_helper *helper,
fb = intel_framebuffer_create(obj, _cmd);
i915_gem_object_put(obj);
- return fb;
+ return to_intel_framebuffer(fb);
}
int intel_fbdev_fb_fill_info(struct drm_i915_private *i915, struct fb_info
*info,
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev_fb.h
b/drivers/gpu/drm/i915/display/intel_fbdev_fb.h
index a395b2c65d33..4832fe688fbf 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev_fb.h
+++ b/drivers/gpu/drm/i915/display/intel_fbdev_fb.h
@@ -13,8 +13,8 @@ struct drm_i915_private;
struct fb_info;
struct i915_vma;
-struct drm_framebuffer *intel_fbdev_fb_alloc(struct drm_fb_helper *helper,
-struct drm_fb_helper_surface_size
*sizes);
+struct intel_framebuffer *intel_fbdev_fb_alloc(struct drm_fb_helper *helper,
+ struct
drm_fb_helper_surface_size *sizes);
int intel_fbdev_fb_fill_info(struct drm_i915_private *i915, struct fb_info
*info,
struct drm_i915_gem_object *obj, struct i915_vma
*vma);
diff --git a/drivers/gpu/drm/xe/display/intel_fbdev_fb.c
b/drivers/gpu/drm/xe/display/intel_fbdev_fb.c
index 9e4bcfdbc7e5..f6bf5896ff1b 100644
--- a/drivers/gpu/drm/xe/display/intel_fbdev_fb.c
+++ b/drivers/gpu/drm/xe/display/intel_fbdev_fb.c
@@ -13,8 +13,8 @@
#include "i915_drv.h"
#include "intel_display_types.h"
-struct drm_framebuffer *intel_fbdev_fb_alloc(struct drm_fb_helper *helper,
-struct drm_fb_helper_surface_size *sizes)
+struct intel_framebuffer *intel_fbdev_fb_alloc(struct drm_fb_helper *helper,
+ struct
drm_fb_helper_surface_size *sizes)
{
struct drm_framebuffer *fb;
struct drm_device *dev = helper->dev;
@@ -70,10 +70,11 @@ struct drm_framebuffer *intel_fbdev_fb_alloc(struct
drm_fb_helper *helper,
}
drm_gem_object_put(intel_bo_to_drm_bo(obj));
- return fb;
+
+ return to_intel_framebuffer(fb);
err:
- return fb;
+ return ERR_CAST(fb);
}
int intel_fbdev_fb_fill_info(struct drm_i915_private *i915, struct fb_info
*info,
--
2.43.2
Re: [PATCH v10 05/12] drm/panelreplay: dpcd register definition for panelreplay SU
On Fri, 10 May 2024, Jouni Högander wrote: > Add definitions for panel replay selective update > > v2: Remove unnecessary Cc from commit message > > Signed-off-by: Jouni Högander > Reviewed-by: Animesh Manna Needs to be Cc: dri-devel. > --- > include/drm/display/drm_dp.h | 6 ++ > 1 file changed, 6 insertions(+) > > diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h > index 0b032faa8cf2..906949ca3cee 100644 > --- a/include/drm/display/drm_dp.h > +++ b/include/drm/display/drm_dp.h > @@ -548,6 +548,12 @@ > # define DP_PANEL_REPLAY_SUPPORT(1 << 0) > # define DP_PANEL_REPLAY_SU_SUPPORT (1 << 1) > > +#define DP_PANEL_PANEL_REPLAY_CAPABILITY 0xb1 > +# define DP_PANEL_PANEL_REPLAY_SU_GRANULARITY_REQUIRED (1 << 5) > + > +#define DP_PANEL_PANEL_REPLAY_X_GRANULARITY 0xb2 > +#define DP_PANEL_PANEL_REPLAY_Y_GRANULARITY 0xb4 > + > /* Link Configuration */ > #define DP_LINK_BW_SET 0x100 > # define DP_LINK_RATE_TABLE 0x00/* eDP 1.4 */ -- Jani Nikula, Intel
[PATCH 2/2] drm/xe/display: remove unused xe->sb_lock
Nothing in xe needs xe->sb_lock. None of the i915 display code using
->sb_lock gets built with xe, and in any case that would be wrong as xe
uses gt->pcode.lock for this.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/xe/display/xe_display.c | 2 --
drivers/gpu/drm/xe/xe_device_types.h| 3 ---
2 files changed, 5 deletions(-)
diff --git a/drivers/gpu/drm/xe/display/xe_display.c
b/drivers/gpu/drm/xe/display/xe_display.c
index fbe2c2eddea9..a2c39bcc7677 100644
--- a/drivers/gpu/drm/xe/display/xe_display.c
+++ b/drivers/gpu/drm/xe/display/xe_display.c
@@ -96,8 +96,6 @@ int xe_display_create(struct xe_device *xe)
xe->display.hotplug.dp_wq = alloc_ordered_workqueue("xe-dp", 0);
- drmm_mutex_init(>drm, >sb_lock);
-
return drmm_add_action_or_reset(>drm, display_destroy, NULL);
}
diff --git a/drivers/gpu/drm/xe/xe_device_types.h
b/drivers/gpu/drm/xe/xe_device_types.h
index b78223e3baab..5c5e36de452a 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -511,9 +511,6 @@ struct xe_device {
/* To shut up runtime pm macros.. */
struct xe_runtime_pm {} runtime_pm;
- /* For pcode */
- struct mutex sb_lock;
-
/* only to allow build, not used functionally */
u32 irq_mask;
--
2.39.2
[PATCH 1/2] drm/xe/display: remove unused xe->enabled_irq_mask
The xe->enabled_irq_mask member has never been used for anything.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/xe/display/xe_display.c | 1 -
drivers/gpu/drm/xe/xe_device_types.h| 2 --
2 files changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/xe/display/xe_display.c
b/drivers/gpu/drm/xe/display/xe_display.c
index 0de0566e5b39..fbe2c2eddea9 100644
--- a/drivers/gpu/drm/xe/display/xe_display.c
+++ b/drivers/gpu/drm/xe/display/xe_display.c
@@ -97,7 +97,6 @@ int xe_display_create(struct xe_device *xe)
xe->display.hotplug.dp_wq = alloc_ordered_workqueue("xe-dp", 0);
drmm_mutex_init(>drm, >sb_lock);
- xe->enabled_irq_mask = ~0;
return drmm_add_action_or_reset(>drm, display_destroy, NULL);
}
diff --git a/drivers/gpu/drm/xe/xe_device_types.h
b/drivers/gpu/drm/xe/xe_device_types.h
index 906b98fb973b..b78223e3baab 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -517,8 +517,6 @@ struct xe_device {
/* only to allow build, not used functionally */
u32 irq_mask;
- u32 enabled_irq_mask;
-
struct intel_uncore {
spinlock_t lock;
} uncore;
--
2.39.2
[PATCH v10 11/12] drm/i915/psr: Split intel_psr2_config_valid for panel replay
Part of intel_psr2_config_valid is valid for panel replay. rename it as
intel_sel_update_config_valid. Split psr2 specific part and name it as
intel_psr2_config_valid.
v3:
- move early transport check to psr2 specific check
- check intel_psr2_config_valid only for non-Panel Replay case
v2:
- use psr2_global_enabled for panel replay as well
- goto unsupported instead of return when global enabled check fails
Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_psr.c | 76 ++--
1 file changed, 46 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 0d90c49d2233..12ddf84e8d02 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1147,9 +1147,6 @@ static bool intel_psr2_sel_fetch_config_valid(struct
intel_dp *intel_dp,
return false;
}
- if (psr2_su_region_et_valid(intel_dp))
- crtc_state->enable_psr2_su_region_et = true;
-
return crtc_state->enable_psr2_sel_fetch = true;
}
@@ -1520,11 +1517,6 @@ static bool intel_psr2_config_valid(struct intel_dp
*intel_dp,
return false;
}
- if (!psr2_global_enabled(intel_dp)) {
- drm_dbg_kms(_priv->drm, "PSR2 disabled by flag\n");
- return false;
- }
-
/*
* DSC and PSR2 cannot be enabled simultaneously. If a requested
* resolution requires DSC to be enabled, priority is given to DSC
@@ -1537,12 +1529,6 @@ static bool intel_psr2_config_valid(struct intel_dp
*intel_dp,
return false;
}
- if (crtc_state->crc_enabled) {
- drm_dbg_kms(_priv->drm,
- "PSR2 not enabled because it would inhibit pipe CRC
calculation\n");
- return false;
- }
-
if (DISPLAY_VER(dev_priv) >= 12) {
psr_max_h = 5120;
psr_max_v = 3200;
@@ -1593,30 +1579,60 @@ static bool intel_psr2_config_valid(struct intel_dp
*intel_dp,
return false;
}
- if (HAS_PSR2_SEL_FETCH(dev_priv)) {
- if (!intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) &&
- !HAS_PSR_HW_TRACKING(dev_priv)) {
- drm_dbg_kms(_priv->drm,
- "PSR2 not enabled, selective fetch not
valid and no HW tracking available\n");
- return false;
- }
- }
-
- if (!psr2_granularity_check(intel_dp, crtc_state)) {
- drm_dbg_kms(_priv->drm, "PSR2 not enabled, SU granularity
not compatible\n");
- goto unsupported;
- }
-
if (!crtc_state->enable_psr2_sel_fetch &&
(crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v)) {
drm_dbg_kms(_priv->drm,
"PSR2 not enabled, resolution %dx%d > max supported
%dx%d\n",
crtc_hdisplay, crtc_vdisplay,
psr_max_h, psr_max_v);
- goto unsupported;
+ return false;
}
tgl_dc3co_exitline_compute_config(intel_dp, crtc_state);
+
+ if (psr2_su_region_et_valid(intel_dp))
+ crtc_state->enable_psr2_su_region_et = true;
+
+ return true;
+}
+
+static bool intel_sel_update_config_valid(struct intel_dp *intel_dp,
+ struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+ if (HAS_PSR2_SEL_FETCH(dev_priv) &&
+ !intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) &&
+ !HAS_PSR_HW_TRACKING(dev_priv)) {
+ drm_dbg_kms(_priv->drm,
+ "Selective update not enabled, selective fetch not
valid and no HW tracking available\n");
+ goto unsupported;
+ }
+
+ if (!psr2_global_enabled(intel_dp)) {
+ drm_dbg_kms(_priv->drm, "Selective update disabled by
flag\n");
+ goto unsupported;
+ }
+
+ if (!crtc_state->has_panel_replay && !intel_psr2_config_valid(intel_dp,
crtc_state))
+ goto unsupported;
+
+ if (crtc_state->has_panel_replay && (DISPLAY_VER(dev_priv) < 14 ||
+
!intel_dp->psr.sink_panel_replay_su_support))
+ goto unsupported;
+
+ if (crtc_state->crc_enabled) {
+ drm_dbg_kms(_priv->drm,
+ "Selective update not enabled because it would
inhibit pipe CRC calculation\n");
+ goto unsupported;
+ }
+
+ if (!psr2_granularity_check(intel_dp, crtc_state)) {
+ drm_dbg_kms(_priv->drm,
+ "Selective update not enabled, SU granularity not
compatible\n");
+ goto unsupported;
+
[PATCH v10 12/12] drm/i915/psr: Add panel replay sel update support to debugfs interface
Add panel replay selective update support to debugfs status interface. In case of sink supporting panel replay we will print out: Sink support: PSR = no, Panel Replay = yes, Panel Replay Selective Update = yes and PSR mode will look like this if printing out enabled panel replay selective update: PSR mode: Panel Replay Selective Update Enabled Current PSR and panel replay printouts remain same. Cc: Kunal Joshi Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna --- drivers/gpu/drm/i915/display/intel_psr.c | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 12ddf84e8d02..2514ac48312b 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -3603,7 +3603,9 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp) if (psr->sink_support) seq_printf(m, " [0x%02x]", intel_dp->psr_dpcd[0]); - seq_printf(m, ", Panel Replay = %s\n", str_yes_no(psr->sink_panel_replay_support)); + seq_printf(m, ", Panel Replay = %s", str_yes_no(psr->sink_panel_replay_support)); + seq_printf(m, ", Panel Replay Selective Update = %s\n", + str_yes_no(psr->sink_panel_replay_su_support)); if (!(psr->sink_support || psr->sink_panel_replay_support)) return 0; @@ -3612,9 +3614,10 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp) mutex_lock(>lock); if (psr->panel_replay_enabled) - status = "Panel Replay Enabled"; + status = psr->sel_update_enabled ? "Panel Replay Selective Update Enabled" : + "Panel Replay Enabled"; else if (psr->enabled) - status = psr->sel_update_enabled ? "PSR2 enabled" : "PSR1 enabled"; + status = psr->sel_update_enabled ? "PSR2" : "PSR1"; else status = "disabled"; seq_printf(m, "PSR mode: %s\n", status); -- 2.34.1
[PATCH v10 10/12] drm/i915/psr: Update PSR module parameter descriptions
We are re-using PSR module parameters for panel replay. Update module parameter descriptions with panel replay information: enable_psr: -1 (default) == follow what is in VBT 0 == disable PSR/PR 1 == Allow PSR1 and PR full frame update 2 == allow PSR1/PSR2 and PR Selective Update enable_psr2_sel_fetch 0 == disable selective fetch for PSR and PR 1 (default) == allow selective fetch for PSR PR Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna --- drivers/gpu/drm/i915/display/intel_display_params.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c b/drivers/gpu/drm/i915/display/intel_display_params.c index 1799a6643128..aebdb7b59dbf 100644 --- a/drivers/gpu/drm/i915/display/intel_display_params.c +++ b/drivers/gpu/drm/i915/display/intel_display_params.c @@ -106,7 +106,8 @@ intel_display_param_named_unsafe(enable_fbc, int, 0400, intel_display_param_named_unsafe(enable_psr, int, 0400, "Enable PSR " - "(0=disabled, 1=enable up to PSR1, 2=enable up to PSR2) " + "(0=disabled, 1=enable up to PSR1 and Panel Replay full frame update, " + "2=enable up to PSR2 and Panel Replay Selective Update) " "Default: -1 (use per-chip default)"); intel_display_param_named(psr_safest_params, bool, 0400, @@ -116,7 +117,7 @@ intel_display_param_named(psr_safest_params, bool, 0400, "Default: 0"); intel_display_param_named_unsafe(enable_psr2_sel_fetch, bool, 0400, - "Enable PSR2 selective fetch " + "Enable PSR2 and Panel Replay selective fetch " "(0=disabled, 1=enabled) " "Default: 1"); -- 2.34.1
[PATCH v10 09/12] drm/i915/psr: Do not apply workarounds in case of panel replay
There are some workarounds that are not applicable for panel replay. Do not
apply these if panel replay is used.
Bspec: 66624, 50422
Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_fbc.c | 5 +++--
drivers/gpu/drm/i915/display/intel_hdmi.c | 3 ++-
drivers/gpu/drm/i915/display/intel_psr.c | 16 ++--
3 files changed, 15 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display/intel_fbc.c
index 984f13d8c0c8..50dd8eb9012e 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -1251,7 +1251,8 @@ static int intel_fbc_check_plane(struct
intel_atomic_state *state,
* Recommendation is to keep this combination disabled
* Bspec: 50422 HSD: 14010260002
*/
- if (IS_DISPLAY_VER(i915, 12, 14) && crtc_state->has_sel_update) {
+ if (IS_DISPLAY_VER(i915, 12, 14) && crtc_state->has_sel_update &&
+ !crtc_state->has_panel_replay) {
plane_state->no_fbc_reason = "PSR2 enabled";
return 0;
}
@@ -1259,7 +1260,7 @@ static int intel_fbc_check_plane(struct
intel_atomic_state *state,
/* Wa_14016291713 */
if ((IS_DISPLAY_VER(i915, 12, 13) ||
IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_C0)) &&
- crtc_state->has_psr) {
+ crtc_state->has_psr && !crtc_state->has_panel_replay) {
plane_state->no_fbc_reason = "PSR1 enabled (Wa_14016291713)";
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 5f6deceaf8ba..0faf2afa1c09 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -532,7 +532,8 @@ void hsw_write_infoframe(struct intel_encoder *encoder,
0);
/* Wa_14013475917 */
- if (!(IS_DISPLAY_VER(dev_priv, 13, 14) && crtc_state->has_psr && type
== DP_SDP_VSC))
+ if (!(IS_DISPLAY_VER(dev_priv, 13, 14) && crtc_state->has_psr &&
+ !crtc_state->has_panel_replay && type == DP_SDP_VSC))
val |= hsw_infoframe_enable(type);
if (type == DP_SDP_VSC)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 532a80a3eeea..0d90c49d2233 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1970,13 +1970,15 @@ static void intel_psr_enable_source(struct intel_dp
*intel_dp,
* All supported adlp panels have 1-based X granularity, this
may
* cause issues if non-supported panels are used.
*/
- if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0,
STEP_B0) ||
- IS_ALDERLAKE_P(dev_priv))
+ if (!intel_dp->psr.panel_replay_enabled &&
+ (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0,
STEP_B0) ||
+IS_ALDERLAKE_P(dev_priv)))
intel_de_rmw(dev_priv, hsw_chicken_trans_reg(dev_priv,
cpu_transcoder),
0, ADLP_1_BASED_X_GRANULARITY);
/* Wa_16012604467:adlp,mtl[a0,b0] */
- if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0,
STEP_B0))
+ if (!intel_dp->psr.panel_replay_enabled &&
+ IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0,
STEP_B0))
intel_de_rmw(dev_priv,
MTL_CLKGATE_DIS_TRANS(cpu_transcoder), 0,
MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS);
@@ -2155,7 +2157,8 @@ static void intel_psr_disable_locked(struct intel_dp
*intel_dp)
if (intel_dp->psr.sel_update_enabled) {
/* Wa_16012604467:adlp,mtl[a0,b0] */
- if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0,
STEP_B0))
+ if (!intel_dp->psr.panel_replay_enabled &&
+ IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0,
STEP_B0))
intel_de_rmw(dev_priv,
MTL_CLKGATE_DIS_TRANS(cpu_transcoder),
MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0);
@@ -2642,8 +2645,9 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state
*state,
goto skip_sel_fetch_set_loop;
/* Wa_14014971492 */
- if ((IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0) ||
-IS_ALDERLAKE_P(dev_priv) || IS_TIGERLAKE(dev_priv)) &&
+ if (!crtc_state->has_panel_replay &&
+ ((IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0) ||
+ IS_ALDERLAKE_P(dev_priv) || IS_TIGERLAKE(dev_priv))) &&
crtc_state->splitter.enable)
crtc_state->psr2_su_area.y1 = 0;
--
[PATCH v10 08/12] drm/i915/psr: Panel replay uses SRD_STATUS to track it's status
DP Panel replay uses SRD_STATUS to track it's status despite selective
update mode.
Bspec: 53370, 68920
v4:
- use PSR2_STATUS for eDP Panel Replay
- handle intel_psr_wait_exit_locked as well
v3:
- do not use PSR2_STATUS for PSR1
v2:
- use intel_dp_is_edp to differentiate
- modify debugfs status as well
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_psr.c | 20
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 6d1f442f3d14..532a80a3eeea 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -2111,7 +2111,8 @@ static void intel_psr_wait_exit_locked(struct intel_dp
*intel_dp)
i915_reg_t psr_status;
u32 psr_status_mask;
- if (intel_dp->psr.sel_update_enabled) {
+ if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled ||
+ intel_dp->psr.panel_replay_enabled)) {
psr_status = EDP_PSR2_STATUS(dev_priv, cpu_transcoder);
psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
} else {
@@ -2849,6 +2850,13 @@ static int _psr1_ready_for_pipe_update_locked(struct
intel_dp *intel_dp)
EDP_PSR_STATUS_STATE_MASK, 50);
}
+static int _panel_replay_ready_for_pipe_update_locked(struct intel_dp
*intel_dp)
+{
+ return intel_dp_is_edp(intel_dp) ?
+ _psr2_ready_for_pipe_update_locked(intel_dp) :
+ _psr1_ready_for_pipe_update_locked(intel_dp);
+}
+
/**
* intel_psr_wait_for_idle_locked - wait for PSR be ready for a pipe update
* @new_crtc_state: new CRTC state
@@ -2874,7 +2882,9 @@ void intel_psr_wait_for_idle_locked(const struct
intel_crtc_state *new_crtc_stat
if (!intel_dp->psr.enabled)
continue;
- if (intel_dp->psr.sel_update_enabled)
+ if (intel_dp->psr.panel_replay_enabled)
+ ret =
_panel_replay_ready_for_pipe_update_locked(intel_dp);
+ else if (intel_dp->psr.sel_update_enabled)
ret = _psr2_ready_for_pipe_update_locked(intel_dp);
else
ret = _psr1_ready_for_pipe_update_locked(intel_dp);
@@ -2895,7 +2905,8 @@ static bool __psr_wait_for_idle_locked(struct intel_dp
*intel_dp)
if (!intel_dp->psr.enabled)
return false;
- if (intel_dp->psr.sel_update_enabled) {
+ if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled ||
+ intel_dp->psr.panel_replay_enabled)) {
reg = EDP_PSR2_STATUS(dev_priv, cpu_transcoder);
mask = EDP_PSR2_STATUS_STATE_MASK;
} else {
@@ -3517,7 +3528,8 @@ psr_source_status(struct intel_dp *intel_dp, struct
seq_file *m)
const char *status = "unknown";
u32 val, status_val;
- if (intel_dp->psr.sel_update_enabled) {
+ if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled ||
+ intel_dp->psr.panel_replay_enabled)) {
static const char * const live_status[] = {
"IDLE",
"CAPTURE",
--
2.34.1
[PATCH v10 07/12] drm/i915/psr: Modify intel_dp_get_su_granularity to support panel replay
Currently intel_dp_get_su_granularity doesn't support panel replay.
This fix modifies it to support panel replay as well.
v4:
- use drm_dp_dpcd_readb instead of drm_dp_dpcd_read
- ensure return value is 0 if drm_dp_dpcd_readb fails
v3: use correct offset for DP_PANEL_PANEL_REPLAY_CAPABILITY
v2: rely on PSR definitions on common bits
Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_psr.c | 62 +---
1 file changed, 55 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 0a5ce29f09d1..6d1f442f3d14 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -468,6 +468,40 @@ static u8 intel_dp_get_sink_sync_latency(struct intel_dp
*intel_dp)
return val;
}
+static u8 intel_dp_get_su_capability(struct intel_dp *intel_dp)
+{
+ u8 su_capability = 0;
+
+ if (intel_dp->psr.sink_panel_replay_su_support)
+ drm_dp_dpcd_readb(_dp->aux,
+ DP_PANEL_PANEL_REPLAY_CAPABILITY,
+ _capability);
+ else
+ su_capability = intel_dp->psr_dpcd[1];
+
+ return su_capability;
+}
+
+static unsigned int
+intel_dp_get_su_x_granularity_offset(struct intel_dp *intel_dp)
+{
+ return intel_dp->psr.sink_panel_replay_su_support ?
+ DP_PANEL_PANEL_REPLAY_X_GRANULARITY :
+ DP_PSR2_SU_X_GRANULARITY;
+}
+
+static unsigned int
+intel_dp_get_su_y_granularity_offset(struct intel_dp *intel_dp)
+{
+ return intel_dp->psr.sink_panel_replay_su_support ?
+ DP_PANEL_PANEL_REPLAY_Y_GRANULARITY :
+ DP_PSR2_SU_Y_GRANULARITY;
+}
+
+/*
+ * Note: Bits related to granularity are same in panel replay and psr
+ * registers. Rely on PSR definitions on these "common" bits.
+ */
static void intel_dp_get_su_granularity(struct intel_dp *intel_dp)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
@@ -475,18 +509,29 @@ static void intel_dp_get_su_granularity(struct intel_dp
*intel_dp)
u16 w;
u8 y;
- /* If sink don't have specific granularity requirements set legacy ones
*/
- if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) {
+ /*
+* TODO: Do we need to take into account panel supporting both PSR and
+* Panel replay?
+*/
+
+ /*
+* If sink don't have specific granularity requirements set legacy
+* ones.
+*/
+ if (!(intel_dp_get_su_capability(intel_dp) &
+ DP_PSR2_SU_GRANULARITY_REQUIRED)) {
/* As PSR2 HW sends full lines, we do not care about x
granularity */
w = 4;
y = 4;
goto exit;
}
- r = drm_dp_dpcd_read(_dp->aux, DP_PSR2_SU_X_GRANULARITY, , 2);
+ r = drm_dp_dpcd_read(_dp->aux,
+intel_dp_get_su_x_granularity_offset(intel_dp),
+, 2);
if (r != 2)
drm_dbg_kms(>drm,
- "Unable to read DP_PSR2_SU_X_GRANULARITY\n");
+ "Unable to read selective update x granularity\n");
/*
* Spec says that if the value read is 0 the default granularity should
* be used instead.
@@ -494,10 +539,12 @@ static void intel_dp_get_su_granularity(struct intel_dp
*intel_dp)
if (r != 2 || w == 0)
w = 4;
- r = drm_dp_dpcd_read(_dp->aux, DP_PSR2_SU_Y_GRANULARITY, , 1);
+ r = drm_dp_dpcd_read(_dp->aux,
+intel_dp_get_su_y_granularity_offset(intel_dp),
+, 1);
if (r != 1) {
drm_dbg_kms(>drm,
- "Unable to read DP_PSR2_SU_Y_GRANULARITY\n");
+ "Unable to read selective update y granularity\n");
y = 4;
}
if (y == 0)
@@ -590,7 +637,8 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
if (intel_dp->psr_dpcd[0])
_psr_init_dpcd(intel_dp);
- if (intel_dp->psr.sink_psr2_support)
+ if (intel_dp->psr.sink_psr2_support ||
+ intel_dp->psr.sink_panel_replay_su_support)
intel_dp_get_su_granularity(intel_dp);
}
--
2.34.1
[PATCH v10 06/12] drm/i915/psr: Detect panel replay selective update support
Add new boolean to store panel replay selective update support of sink into
intel_psr struct. Detect panel replay selective update support and store
it into this new boolean.
v3: Clear sink_panel_replay_su_support in intel_dp_detect
v2: Merge adding new boolean into this patch
Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/intel_dp.c| 1 +
drivers/gpu/drm/i915/display/intel_psr.c | 10 --
3 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 69ce0ff286f7..e1c44e2a07f2 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1719,6 +1719,7 @@ struct intel_psr {
u16 su_y_granularity;
bool source_panel_replay_support;
bool sink_panel_replay_support;
+ bool sink_panel_replay_su_support;
bool panel_replay_enabled;
u32 dc3co_exitline;
u32 dc3co_exit_delay;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 303376d3aff2..1cb9909a3cff 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5861,6 +5861,7 @@ intel_dp_detect(struct drm_connector *connector,
memset(_dp->compliance, 0, sizeof(intel_dp->compliance));
memset(intel_connector->dp.dsc_dpcd, 0,
sizeof(intel_connector->dp.dsc_dpcd));
intel_dp->psr.sink_panel_replay_support = false;
+ intel_dp->psr.sink_panel_replay_su_support = false;
intel_dp_mst_disconnect(intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 820499f420ba..0a5ce29f09d1 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -522,9 +522,15 @@ static void _panel_replay_init_dpcd(struct intel_dp
*intel_dp)
return;
}
- drm_dbg_kms(>drm,
- "Panel replay is supported by panel\n");
intel_dp->psr.sink_panel_replay_support = true;
+
+ if (pr_dpcd & DP_PANEL_REPLAY_SU_SUPPORT)
+ intel_dp->psr.sink_panel_replay_su_support = true;
+
+ drm_dbg_kms(>drm,
+ "Panel replay %sis supported by panel\n",
+ intel_dp->psr.sink_panel_replay_su_support ?
+ "selective_update " : "");
}
static void _psr_init_dpcd(struct intel_dp *intel_dp)
--
2.34.1
[PATCH v10 02/12] drm/i915/display: Do not print "psr: enabled" for on Panel Replay
After setting has_psr for panel replay as well crtc state dump is
improperly printing "psr: enabled" for Panel Replay as well. Fix this by
checking also has_panel_replay.
Fixes: 5afa6e496098 ("drm/i915/psr: Set intel_crtc_state->has_psr on panel
replay as well")
Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index 1da4c122c52e..bddcc9edeab4 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -252,7 +252,8 @@ void intel_crtc_state_dump(const struct intel_crtc_state
*pipe_config,
str_enabled_disabled(pipe_config->sdp_split_enable));
drm_printf(, "psr: %s, selective update: %s, panel replay:
%s, selective fetch: %s\n",
- str_enabled_disabled(pipe_config->has_psr),
+ str_enabled_disabled(pipe_config->has_psr &&
+ !pipe_config->has_panel_replay),
str_enabled_disabled(pipe_config->has_sel_update),
str_enabled_disabled(pipe_config->has_panel_replay),
str_enabled_disabled(pipe_config->enable_psr2_sel_fetch));
--
2.34.1
[PATCH v10 05/12] drm/panelreplay: dpcd register definition for panelreplay SU
Add definitions for panel replay selective update v2: Remove unnecessary Cc from commit message Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna --- include/drm/display/drm_dp.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h index 0b032faa8cf2..906949ca3cee 100644 --- a/include/drm/display/drm_dp.h +++ b/include/drm/display/drm_dp.h @@ -548,6 +548,12 @@ # define DP_PANEL_REPLAY_SUPPORT(1 << 0) # define DP_PANEL_REPLAY_SU_SUPPORT (1 << 1) +#define DP_PANEL_PANEL_REPLAY_CAPABILITY 0xb1 +# define DP_PANEL_PANEL_REPLAY_SU_GRANULARITY_REQUIRED (1 << 5) + +#define DP_PANEL_PANEL_REPLAY_X_GRANULARITY0xb2 +#define DP_PANEL_PANEL_REPLAY_Y_GRANULARITY0xb4 + /* Link Configuration */ #defineDP_LINK_BW_SET 0x100 # define DP_LINK_RATE_TABLE0x00/* eDP 1.4 */ -- 2.34.1
[PATCH v10 03/12] drm/i915/dp: Use always vsc revision 0x6 for Panel Replay
We are about to enable Panel Replay Selective update mode. Vsc revision 0x6
for Panel Replay no matter if it is selective update or full frame update
mode. Take this into account when preparing VSC SDP package.
Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dp.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index f87af83c9bd1..303376d3aff2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2663,14 +2663,6 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp
*intel_dp,
if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
vsc);
- } else if (crtc_state->has_sel_update) {
- /*
-* [PSR2 without colorimetry]
-* Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
-* 3D stereo + PSR/PSR2 + Y-coordinate.
-*/
- vsc->revision = 0x4;
- vsc->length = 0xe;
} else if (crtc_state->has_panel_replay) {
/*
* [Panel Replay without colorimetry info]
@@ -2679,6 +2671,14 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp
*intel_dp,
*/
vsc->revision = 0x6;
vsc->length = 0x10;
+ } else if (crtc_state->has_sel_update) {
+ /*
+* [PSR2 without colorimetry]
+* Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
+* 3D stereo + PSR/PSR2 + Y-coordinate.
+*/
+ vsc->revision = 0x4;
+ vsc->length = 0xe;
} else {
/*
* [PSR1]
--
2.34.1
[PATCH v10 01/12] drm/i915/psr: Rename has_psr2 as has_sel_update
We are going to reuse has_psr2 for panel_replay as well. Rename it
as has_sel_update to avoid confusion.
v3: do not add has_psr check into psr2 case in intel_dp_compute_vsc_sdp
v2: Rebase
Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 4 ++--
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_display_types.h | 2 +-
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
drivers/gpu/drm/i915/display/intel_fbc.c | 2 +-
drivers/gpu/drm/i915/display/intel_psr.c | 10 +-
6 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index ccaa4cb2809b..1da4c122c52e 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -251,9 +251,9 @@ void intel_crtc_state_dump(const struct intel_crtc_state
*pipe_config,
drm_printf(, "sdp split: %s\n",
str_enabled_disabled(pipe_config->sdp_split_enable));
- drm_printf(, "psr: %s, psr2: %s, panel replay: %s, selective
fetch: %s\n",
+ drm_printf(, "psr: %s, selective update: %s, panel replay:
%s, selective fetch: %s\n",
str_enabled_disabled(pipe_config->has_psr),
- str_enabled_disabled(pipe_config->has_psr2),
+ str_enabled_disabled(pipe_config->has_sel_update),
str_enabled_disabled(pipe_config->has_panel_replay),
str_enabled_disabled(pipe_config->enable_psr2_sel_fetch));
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index ef986b508431..4035b3ec311d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5320,7 +5320,7 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
*/
if (current_config->has_panel_replay || pipe_config->has_panel_replay) {
PIPE_CONF_CHECK_BOOL(has_psr);
- PIPE_CONF_CHECK_BOOL(has_psr2);
+ PIPE_CONF_CHECK_BOOL(has_sel_update);
PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
PIPE_CONF_CHECK_BOOL(enable_psr2_su_region_et);
PIPE_CONF_CHECK_BOOL(has_panel_replay);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index a06a154d587b..3a213e72f5f4 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1189,7 +1189,7 @@ struct intel_crtc_state {
/* PSR is supported but might not be enabled due the lack of enabled
planes */
bool has_psr;
- bool has_psr2;
+ bool has_sel_update;
bool enable_psr2_sel_fetch;
bool enable_psr2_su_region_et;
bool req_psr2_sdp_prior_scanline;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 486361eb0070..f87af83c9bd1 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2663,7 +2663,7 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp
*intel_dp,
if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
vsc);
- } else if (crtc_state->has_psr2) {
+ } else if (crtc_state->has_sel_update) {
/*
* [PSR2 without colorimetry]
* Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display/intel_fbc.c
index 151dcd0c45b6..984f13d8c0c8 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -1251,7 +1251,7 @@ static int intel_fbc_check_plane(struct
intel_atomic_state *state,
* Recommendation is to keep this combination disabled
* Bspec: 50422 HSD: 14010260002
*/
- if (IS_DISPLAY_VER(i915, 12, 14) && crtc_state->has_psr2) {
+ if (IS_DISPLAY_VER(i915, 12, 14) && crtc_state->has_sel_update) {
plane_state->no_fbc_reason = "PSR2 enabled";
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 595eb1b3b6c6..74e2ee9a48fa 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -653,7 +653,7 @@ void intel_psr_enable_sink(struct intel_dp *intel_dp,
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
u8 dpcd_val = DP_PSR_ENABLE;
- if
[PATCH v10 04/12] drm/i915/psr: Rename psr2_enabled as sel_update_enabled
We are about to reuse psr2_enabled for panel replay as well. Rename
it as sel_update_enabled to avoid confusion.
v3: Rebase
v2: Rebase
Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
---
.../drm/i915/display/intel_display_types.h| 2 +-
drivers/gpu/drm/i915/display/intel_psr.c | 52 +--
2 files changed, 27 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 3a213e72f5f4..69ce0ff286f7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1695,7 +1695,7 @@ struct intel_psr {
unsigned int busy_frontbuffer_bits;
bool sink_psr2_support;
bool link_standby;
- bool psr2_enabled;
+ bool sel_update_enabled;
bool psr2_sel_fetch_enabled;
bool psr2_sel_fetch_cff_enabled;
bool req_psr2_sdp_prior_scanline;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 74e2ee9a48fa..820499f420ba 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -356,12 +356,12 @@ static void psr_irq_control(struct intel_dp *intel_dp)
}
static void psr_event_print(struct drm_i915_private *i915,
- u32 val, bool psr2_enabled)
+ u32 val, bool sel_update_enabled)
{
drm_dbg_kms(>drm, "PSR exit events: 0x%x\n", val);
if (val & PSR_EVENT_PSR2_WD_TIMER_EXPIRE)
drm_dbg_kms(>drm, "\tPSR2 watchdog timer expired\n");
- if ((val & PSR_EVENT_PSR2_DISABLED) && psr2_enabled)
+ if ((val & PSR_EVENT_PSR2_DISABLED) && sel_update_enabled)
drm_dbg_kms(>drm, "\tPSR2 disabled\n");
if (val & PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN)
drm_dbg_kms(>drm, "\tSU dirty FIFO underrun\n");
@@ -389,7 +389,7 @@ static void psr_event_print(struct drm_i915_private *i915,
drm_dbg_kms(>drm, "\tVBI enabled\n");
if (val & PSR_EVENT_LPSP_MODE_EXIT)
drm_dbg_kms(>drm, "\tLPSP mode exited\n");
- if ((val & PSR_EVENT_PSR_DISABLE) && !psr2_enabled)
+ if ((val & PSR_EVENT_PSR_DISABLE) && !sel_update_enabled)
drm_dbg_kms(>drm, "\tPSR disabled\n");
}
@@ -419,7 +419,7 @@ void intel_psr_irq_handler(struct intel_dp *intel_dp, u32
psr_iir)
PSR_EVENT(dev_priv, cpu_transcoder),
0, 0);
- psr_event_print(dev_priv, val,
intel_dp->psr.psr2_enabled);
+ psr_event_print(dev_priv, val,
intel_dp->psr.sel_update_enabled);
}
}
@@ -1677,10 +1677,10 @@ void intel_psr_get_config(struct intel_encoder *encoder,
pipe_config->has_psr = true;
}
- pipe_config->has_sel_update = intel_dp->psr.psr2_enabled;
+ pipe_config->has_sel_update = intel_dp->psr.sel_update_enabled;
pipe_config->infoframes.enable |=
intel_hdmi_infoframe_enable(DP_SDP_VSC);
- if (!intel_dp->psr.psr2_enabled)
+ if (!intel_dp->psr.sel_update_enabled)
goto unlock;
if (HAS_PSR2_SEL_FETCH(dev_priv)) {
@@ -1718,7 +1718,7 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
/* psr1, psr2 and panel-replay are mutually exclusive.*/
if (intel_dp->psr.panel_replay_enabled)
dg2_activate_panel_replay(intel_dp);
- else if (intel_dp->psr.psr2_enabled)
+ else if (intel_dp->psr.sel_update_enabled)
hsw_activate_psr2(intel_dp);
else
hsw_activate_psr1(intel_dp);
@@ -1777,7 +1777,7 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp)
struct intel_psr *psr = _dp->psr;
u32 alpm_ctl;
- if (DISPLAY_VER(dev_priv) < 20 || (!intel_dp->psr.psr2_enabled &&
+ if (DISPLAY_VER(dev_priv) < 20 || (!intel_dp->psr.sel_update_enabled &&
!intel_dp_is_edp(intel_dp)))
return;
@@ -1905,7 +1905,7 @@ static void intel_psr_enable_source(struct intel_dp
*intel_dp,
*/
wm_optimization_wa(intel_dp, crtc_state);
- if (intel_dp->psr.psr2_enabled) {
+ if (intel_dp->psr.sel_update_enabled) {
if (DISPLAY_VER(dev_priv) == 9)
intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0,
PSR2_VSC_ENABLE_PROG_HEADER |
@@ -1971,7 +1971,7 @@ static void intel_psr_enable_locked(struct intel_dp
*intel_dp,
drm_WARN_ON(_priv->drm, intel_dp->psr.enabled);
- intel_dp->psr.psr2_enabled = crtc_state->has_sel_update;
+ intel_dp->psr.sel_update_enabled = crtc_state->has_sel_update;
intel_dp->psr.panel_replay_enabled = crtc_state->has_panel_replay;
[PATCH v10 00/12] Panel replay selective update support
This patch set is implementing panel replay selective update support for Intel hardware. v10: - use always PSR2_STATUS for eDP Panel Replay - handle SRD_STATUS vs. PSR2_STATUS in intel_psr_wait_exit_locked as well v9: - do not add has_psr check into psr2 case in intel_dp_compute_vsc_sdp - use drm_dp_dpcd_readb instead of drm_dp_dpcd_read in intel_dp_get_su_capability - ensure intel_dp_get_su_capability returns 0 if drm_dp_dpcd_readb fails v8: - use correct offset for DP_PANEL_PANEL_REPLAY_CAPABILITY v7: - use always vsc revision 0x6 for Panel Replay v6: - fixes split to separate patch set v5: - do not use PSR2_STATUS for PSR1 v4: - do not rename intel_psr_enabled - do not add sel_update_et_enabled into struct intel_psr v3: - do not disable panel replay by default - set has_psr for panel replay as well - enable sink before link training - do not apply all PSR workarounds for panel replay - do not write/read registers/bits not applicable for panel replay - use psr bit definitions in granularity configuration as well - goto unsupported instead of return when global enabled check fails - update module parameter descriptions. v2: - make psr pause/resume to work for panel replay as well Jouni Högander (12): drm/i915/psr: Rename has_psr2 as has_sel_update drm/i915/display: Do not print "psr: enabled" for on Panel Replay drm/i915/dp: Use always vsc revision 0x6 for Panel Replay drm/i915/psr: Rename psr2_enabled as sel_update_enabled drm/panelreplay: dpcd register definition for panelreplay SU drm/i915/psr: Detect panel replay selective update support drm/i915/psr: Modify intel_dp_get_su_granularity to support panel replay drm/i915/psr: Panel replay uses SRD_STATUS to track it's status drm/i915/psr: Do not apply workarounds in case of panel replay drm/i915/psr: Update PSR module parameter descriptions drm/i915/psr: Split intel_psr2_config_valid for panel replay drm/i915/psr: Add panel replay sel update support to debugfs interface .../drm/i915/display/intel_crtc_state_dump.c | 7 +- drivers/gpu/drm/i915/display/intel_display.c | 2 +- .../drm/i915/display/intel_display_params.c | 5 +- .../drm/i915/display/intel_display_types.h| 5 +- drivers/gpu/drm/i915/display/intel_dp.c | 17 +- drivers/gpu/drm/i915/display/intel_fbc.c | 5 +- drivers/gpu/drm/i915/display/intel_hdmi.c | 3 +- drivers/gpu/drm/i915/display/intel_psr.c | 237 -- include/drm/display/drm_dp.h | 6 + 9 files changed, 194 insertions(+), 93 deletions(-) -- 2.34.1
Re: [PATCH] drm/xe: Nuke xe's copy of intel_fbdev_fb.h
On Wed, 08 May 2024, Ville Syrjälä wrote: > On Tue, May 07, 2024 at 11:53:40AM +0300, Jani Nikula wrote: >> On Mon, 06 May 2024, Ville Syrjala wrote: >> > From: Ville Syrjälä >> > >> > For some reason xe and i915 each have an identical (fortunately) >> > copy of intel_fbdev_fb.h. The xe copy actually only gets included >> > by xe's intel_fbdev_fb.c, and the i915 copy by everyone else, >> > include intel_fbdev.c which is the actual caller of the >> > functions declared in the header. >> > >> > This means the xe and i915 headers are free to define/declare >> > completely incompatible things and the build would still succeed >> > as long as the symbol names match. >> > >> > That is not a good thing, so let's nuke xe's copy of the header >> > so that everyone will use the same header, and be forced to >> > agree on the same API/ABI. >> > >> > Signed-off-by: Ville Syrjälä >> >> Reviewed-by: Jani Nikula > > Thanks. > > I was going to push this to drm-xe-next, but I should actually > push it to drm-intel-next since I'll be massaging this stuff > there. Yeah, things often run more smoothly if we merge xe/display/ changes via drm-intel-next. It can take a while to merge stuff to drm-next and backmerge to respective drivers to sync it all up. BR, Jani. > > xe maintainers, ack for merging via drm-intel-next? > >> >> > --- >> > drivers/gpu/drm/xe/display/intel_fbdev_fb.h | 21 - >> > 1 file changed, 21 deletions(-) >> > delete mode 100644 drivers/gpu/drm/xe/display/intel_fbdev_fb.h >> > >> > diff --git a/drivers/gpu/drm/xe/display/intel_fbdev_fb.h >> > b/drivers/gpu/drm/xe/display/intel_fbdev_fb.h >> > deleted file mode 100644 >> > index ea186772e0bb.. >> > --- a/drivers/gpu/drm/xe/display/intel_fbdev_fb.h >> > +++ /dev/null >> > @@ -1,21 +0,0 @@ >> > -/* SPDX-License-Identifier: MIT */ >> > -/* >> > - * Copyright © 2023 Intel Corporation >> > - */ >> > - >> > -#ifndef __INTEL_FBDEV_FB_H__ >> > -#define __INTEL_FBDEV_FB_H__ >> > - >> > -struct drm_fb_helper; >> > -struct drm_fb_helper_surface_size; >> > -struct drm_i915_gem_object; >> > -struct drm_i915_private; >> > -struct fb_info; >> > -struct i915_vma; >> > - >> > -struct drm_framebuffer *intel_fbdev_fb_alloc(struct drm_fb_helper *helper, >> > - struct drm_fb_helper_surface_size *sizes); >> > -int intel_fbdev_fb_fill_info(struct drm_i915_private *i915, struct >> > fb_info *info, >> > -struct drm_i915_gem_object *obj, struct i915_vma >> > *vma); >> > - >> > -#endif >> >> -- >> Jani Nikula, Intel -- Jani Nikula, Intel
RE: [PATCH] drm/mst: Fix NULL pointer dereference at drm_dp_add_payload_part2
On Fri, 10 May 2024, "Lin, Wayne" wrote:
> [Public]
>
>> -Original Message-
>> From: Limonciello, Mario
>> Sent: Friday, May 10, 2024 3:18 AM
>> To: Linux regressions mailing list ; Wentland,
>> Harry
>> ; Lin, Wayne
>> Cc: ly...@redhat.com; imre.d...@intel.com; Leon Weiß > bochum.de>; sta...@vger.kernel.org; dri-de...@lists.freedesktop.org; amd-
>> g...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
>> Subject: Re: [PATCH] drm/mst: Fix NULL pointer dereference at
>> drm_dp_add_payload_part2
>>
>> On 5/9/2024 07:43, Linux regression tracking (Thorsten Leemhuis) wrote:
>> > On 18.04.24 21:43, Harry Wentland wrote:
>> >> On 2024-03-07 01:29, Wayne Lin wrote:
>> >>> [Why]
>> >>> Commit:
>> >>> - commit 5aa1dfcdf0a4 ("drm/mst: Refactor the flow for payload
>> >>> allocation/removement") accidently overwrite the commit
>> >>> - commit 54d217406afe ("drm: use mgr->dev in drm_dbg_kms in
>> >>> drm_dp_add_payload_part2") which cause regression.
>> >>>
>> >>> [How]
>> >>> Recover the original NULL fix and remove the unnecessary input
>> >>> parameter 'state' for drm_dp_add_payload_part2().
>> >>>
>> >>> Fixes: 5aa1dfcdf0a4 ("drm/mst: Refactor the flow for payload
>> >>> allocation/removement")
>> >>> Reported-by: Leon Weiß
>> >>> Link:
>> >>> https://lore.kernel.org/r/38c253ea42072cc825dc969ac4e6b9b600371cc8.c
>> >>> a...@ruhr-uni-bochum.de/
>> >>> Cc: ly...@redhat.com
>> >>> Cc: imre.d...@intel.com
>> >>> Cc: sta...@vger.kernel.org
>> >>> Cc: regressi...@lists.linux.dev
>> >>> Signed-off-by: Wayne Lin
>> >>
>> >> I haven't been deep in MST code in a while but this all looks pretty
>> >> straightforward and good.
>> >>
>> >> Reviewed-by: Harry Wentland
>> >
>> > Hmmm, that was three weeks ago, but it seems since then nothing
>> > happened to fix the linked regression through this or some other
>> > patch. Is there a reason? The build failure report from the CI maybe?
>>
>> It touches files outside of amd but only has an ack from AMD. I think we
>> /probably/ want an ack from i915 and nouveau to take it through.
>
> Thanks, Mario!
>
> Hi Thorsten,
> Yeah, like what Mario said. Would also like to have ack from i915 and nouveau.
It usually works better if you Cc the folks you want an ack from! ;)
Acked-by: Jani Nikula
>
>>
>> >
>> > Wayne Lin, do you know what's up?
>> >
>> > Ciao, Thorsten
>> >
>> >>> ---
>> >>> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 2 +-
>> >>> drivers/gpu/drm/display/drm_dp_mst_topology.c | 4 +---
>> >>> drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
>> >>> drivers/gpu/drm/nouveau/dispnv50/disp.c | 2 +-
>> >>> include/drm/display/drm_dp_mst_helper.h | 1 -
>> >>> 5 files changed, 4 insertions(+), 7 deletions(-)
>> >>>
>> >>> diff --git
>> >>> a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
>> >>> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
>> >>> index c27063305a13..2c36f3d00ca2 100644
>> >>> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
>> >>> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
>> >>> @@ -363,7 +363,7 @@ void dm_helpers_dp_mst_send_payload_allocation(
>> >>> mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state);
>> >>> new_payload = drm_atomic_get_mst_payload_state(mst_state,
>> >>> aconnector->mst_output_port);
>> >>>
>> >>> - ret = drm_dp_add_payload_part2(mst_mgr, mst_state->base.state,
>> new_payload);
>> >>> + ret = drm_dp_add_payload_part2(mst_mgr, new_payload);
>> >>>
>> >>> if (ret) {
>> >>> amdgpu_dm_set_mst_status(>mst_status,
>> >>> diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c
>> >>> b/drivers/gpu/drm/display/drm_dp_mst_topology.c
>> >>> index 03d528209426..95fd18f24e94 100644
>> >>> --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
>> >>> +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
>> >>> @@ -3421,7 +3421,6 @@
>> EXPORT_SYMBOL(drm_dp_remove_payload_part2);
>> >>> /**
>> >>>* drm_dp_add_payload_part2() - Execute payload update part 2
>> >>>* @mgr: Manager to use.
>> >>> - * @state: The global atomic state
>> >>>* @payload: The payload to update
>> >>>*
>> >>>* If @payload was successfully assigned a starting time slot by
>> >>> drm_dp_add_payload_part1(), this @@ -3430,14 +3429,13 @@
>> EXPORT_SYMBOL(drm_dp_remove_payload_part2);
>> >>>* Returns: 0 on success, negative error code on failure.
>> >>>*/
>> >>> int drm_dp_add_payload_part2(struct drm_dp_mst_topology_mgr *mgr,
>> >>> - struct drm_atomic_state *state,
>> >>>struct drm_dp_mst_atomic_payload *payload)
>> >>> {
>> >>> int ret = 0;
>> >>>
>> >>> /* Skip failed payloads */
>> >>> if (payload->payload_allocation_status !=
>> DRM_DP_MST_PAYLOAD_ALLOCATION_DFP) {
>> >>> - drm_dbg_kms(state->dev, "Part 1 of payload creation for %s
>>
Re: [PATCH] Documentation/i915: remove kernel-doc for DMC wakelocks
On Fri, 2024-05-10 at 12:21 +0300, Jani Nikula wrote: > On Fri, 10 May 2024, Luca Coelho wrote: > > The function descriptions are optional and have not yet been added to > > the DMC wakelock code, so we shouldn't try to use it. Since this is a > > regression, remove the kernel-doc entry for DMC wakelocks for now. > > The proper documentation will be added in a future patch. > > I don't really think the kernel-doc documentation is necessary for > internal interfaces. I mean adding brief comments is fine, but no need > for this stuff to show up at docs.kernel.org. Good, one more thing out of my TODO list. ;) > Reviewed-by: Jani Nikula Thanks for the quick review! -- Cheers, Luca.
Re: [PATCH] Documentation/i915: remove kernel-doc for DMC wakelocks
On Fri, 10 May 2024, Luca Coelho wrote:
> The function descriptions are optional and have not yet been added to
> the DMC wakelock code, so we shouldn't try to use it. Since this is a
> regression, remove the kernel-doc entry for DMC wakelocks for now.
> The proper documentation will be added in a future patch.
I don't really think the kernel-doc documentation is necessary for
internal interfaces. I mean adding brief comments is fine, but no need
for this stuff to show up at docs.kernel.org.
Reviewed-by: Jani Nikula
>
> Fixes: 765425f598c2 ("drm/i915/display: add support for DMC wakelocks")
> Signed-off-by: Luca Coelho
> ---
> Documentation/gpu/i915.rst | 3 ---
> 1 file changed, 3 deletions(-)
>
> diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
> index 17261ba18313..3113e36f14cf 100644
> --- a/Documentation/gpu/i915.rst
> +++ b/Documentation/gpu/i915.rst
> @@ -210,9 +210,6 @@ DMC wakelock support
> .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc_wl.c
> :doc: DMC wakelock support
>
> -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc_wl.c
> - :internal:
> -
> Video BIOS Table (VBT)
> --
--
Jani Nikula, Intel
[PATCH] Documentation/i915: remove kernel-doc for DMC wakelocks
The function descriptions are optional and have not yet been added to
the DMC wakelock code, so we shouldn't try to use it. Since this is a
regression, remove the kernel-doc entry for DMC wakelocks for now.
The proper documentation will be added in a future patch.
Fixes: 765425f598c2 ("drm/i915/display: add support for DMC wakelocks")
Signed-off-by: Luca Coelho
---
Documentation/gpu/i915.rst | 3 ---
1 file changed, 3 deletions(-)
diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index 17261ba18313..3113e36f14cf 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -210,9 +210,6 @@ DMC wakelock support
.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc_wl.c
:doc: DMC wakelock support
-.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc_wl.c
- :internal:
-
Video BIOS Table (VBT)
--
--
2.39.2
Re: [PATCH 04/10] drm/i915: pass dev_priv explicitly to TRANS_VRR_VMAXSHIFT
On Thu, 09 May 2024, Rodrigo Vivi wrote: > On Wed, May 08, 2024 at 06:47:50PM +0300, Jani Nikula wrote: >> Avoid the implicit dev_priv local variable use, and pass dev_priv >> explicitly to the TRANS_VRR_VMAXSHIFT register macro. >> >> Signed-off-by: Jani Nikula >> --- >> drivers/gpu/drm/i915/i915_reg.h | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h >> b/drivers/gpu/drm/i915/i915_reg.h >> index 775c878ca72f..9739ef525e13 100644 >> --- a/drivers/gpu/drm/i915/i915_reg.h >> +++ b/drivers/gpu/drm/i915/i915_reg.h >> @@ -1261,7 +1261,7 @@ >> #define _TRANS_VRR_VMAXSHIFT_B 0x61428 >> #define _TRANS_VRR_VMAXSHIFT_C 0x62428 >> #define _TRANS_VRR_VMAXSHIFT_D 0x63428 >> -#define TRANS_VRR_VMAXSHIFT(trans) _MMIO_TRANS2(dev_priv, trans, \ >> +#define TRANS_VRR_VMAXSHIFT(dev_priv, trans)_MMIO_TRANS2(dev_priv, >> trans, \ > > unused? should we remove? > or one of those with wip around that is going to get used soon? > if so, VRR is new-ish, so I decided to keep these even though I don't know for sure that they will be used soon. > Reviewed-by: Rodrigo Vivi Thanks for the review, series pushed to din. BR, Jani. > >> _TRANS_VRR_VMAXSHIFT_A) >> #define VRR_VMAXSHIFT_DEC_MASKREG_GENMASK(29, 16) >> #define VRR_VMAXSHIFT_DEC REG_BIT(16) >> -- >> 2.39.2 >> -- Jani Nikula, Intel
[PULL] drm-misc-fixes
Hi Dave, Sima, this is the weekly drm-misc-fixes PR. Sorry for being late. Best regards Thomas drm-misc-fixes-2024-05-10: Short summary of fixes pull: core: - fix connector debugging output meson: - dw-hdmi: power-up fixes - dw-hdmi: add badngap setting for g12 The following changes since commit da85f0aaa9f21999753b01d45c0343f885a8f905: drm/panel: ili9341: Use predefined error codes (2024-05-02 09:41:27 +0200) are available in the Git repository at: https://gitlab.freedesktop.org/drm/misc/kernel.git tags/drm-misc-fixes-2024-05-10 for you to fetch changes up to 6897204ea3df808d342c8e4613135728bc538bcd: drm/connector: Add \n to message about demoting connector force-probes (2024-05-07 09:17:07 -0700) Short summary of fixes pull: core: - fix connector debugging output meson: - dw-hdmi: power-up fixes - dw-hdmi: add badngap setting for g12 Douglas Anderson (1): drm/connector: Add \n to message about demoting connector force-probes Jerome Brunet (2): drm/meson: dw-hdmi: power up phy on device init drm/meson: dw-hdmi: add bandgap setting for g12 drivers/gpu/drm/drm_connector.c | 2 +- drivers/gpu/drm/meson/meson_dw_hdmi.c | 70 --- 2 files changed, 32 insertions(+), 40 deletions(-) -- Thomas Zimmermann Graphics Driver Developer SUSE Software Solutions Germany GmbH Frankenstrasse 146, 90461 Nuernberg, Germany GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman HRB 36809 (AG Nuernberg)
