✗ Fi.CI.IGT: failure for drm/i915: skl+ plane register stuff (rev6)
== Series Details == Series: drm/i915: skl+ plane register stuff (rev6) URL : https://patchwork.freedesktop.org/series/133458/ State : failure == Summary == CI Bug Log - changes from CI_DRM_14756_full -> Patchwork_133458v6_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_133458v6_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_133458v6_full, please notify your bug team (i915-ci-in...@lists.freedesktop.org) to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (9 -> 9) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_133458v6_full: ### IGT changes ### Possible regressions * igt@drm_read@short-buffer-wakeup: - shard-dg2: NOTRUN -> [INCOMPLETE][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-2/igt@drm_r...@short-buffer-wakeup.html Known issues Here are the changes found in Patchwork_133458v6_full that come from known issues: ### IGT changes ### Issues hit * igt@drm_fdinfo@virtual-busy-all: - shard-mtlp: NOTRUN -> [SKIP][2] ([i915#8414]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-mtlp-7/igt@drm_fdi...@virtual-busy-all.html * igt@drm_fdinfo@virtual-busy-hang-all: - shard-dg2: NOTRUN -> [SKIP][3] ([i915#8414]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-6/igt@drm_fdi...@virtual-busy-hang-all.html * igt@gem_busy@close-race: - shard-mtlp: [PASS][4] -> [ABORT][5] ([i915#10182]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14756/shard-mtlp-2/igt@gem_b...@close-race.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-mtlp-3/igt@gem_b...@close-race.html * igt@gem_ccs@ctrl-surf-copy: - shard-mtlp: NOTRUN -> [SKIP][6] ([i915#3555] / [i915#9323]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-mtlp-7/igt@gem_...@ctrl-surf-copy.html * igt@gem_create@create-ext-cpu-access-big: - shard-dg2: NOTRUN -> [INCOMPLETE][7] ([i915#9364]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-6/igt@gem_cre...@create-ext-cpu-access-big.html * igt@gem_ctx_exec@basic-nohangcheck: - shard-tglu: [PASS][8] -> [FAIL][9] ([i915#6268]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14756/shard-tglu-4/igt@gem_ctx_e...@basic-nohangcheck.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-tglu-7/igt@gem_ctx_e...@basic-nohangcheck.html * igt@gem_ctx_persistence@engines-mixed-process: - shard-snb: NOTRUN -> [SKIP][10] ([i915#1099]) +1 other test skip [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-snb2/igt@gem_ctx_persiste...@engines-mixed-process.html * igt@gem_ctx_persistence@saturated-hostile-nopreempt@ccs0: - shard-dg2: NOTRUN -> [SKIP][11] ([i915#5882]) +6 other tests skip [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-6/igt@gem_ctx_persistence@saturated-hostile-nopree...@ccs0.html * igt@gem_exec_balancer@bonded-false-hang: - shard-mtlp: NOTRUN -> [SKIP][12] ([i915#4812]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-mtlp-7/igt@gem_exec_balan...@bonded-false-hang.html * igt@gem_exec_balancer@bonded-semaphore: - shard-dg2: NOTRUN -> [SKIP][13] ([i915#4812]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-6/igt@gem_exec_balan...@bonded-semaphore.html * igt@gem_exec_balancer@invalid-bonds: - shard-dg2: NOTRUN -> [SKIP][14] ([i915#4036]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-dg2-6/igt@gem_exec_balan...@invalid-bonds.html * igt@gem_exec_balancer@noheartbeat: - shard-mtlp: NOTRUN -> [SKIP][15] ([i915#8555]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-mtlp-7/igt@gem_exec_balan...@noheartbeat.html * igt@gem_exec_capture@capture-invisible@smem0: - shard-glk: NOTRUN -> [SKIP][16] ([i915#6334]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-glk3/igt@gem_exec_capture@capture-invisi...@smem0.html * igt@gem_exec_capture@many-4k-zero: - shard-glk: NOTRUN -> [FAIL][17] ([i915#9606]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/shard-glk1/igt@gem_exec_capt...@many-4k-zero.html * igt@gem_exec_fair@basic-none-rrul@rcs0: - shard-glk: NOTRUN -> [FAIL][18] ([i915#2842]) [18]:
✓ Fi.CI.BAT: success for drm/edid: remove drm_do_get_edid()
== Series Details ==
Series: drm/edid: remove drm_do_get_edid()
URL : https://patchwork.freedesktop.org/series/133569/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14757 -> Patchwork_133569v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133569v1/index.html
Participating hosts (41 -> 40)
--
Additional (1): bat-mtlp-8
Missing(2): fi-snb-2520m fi-kbl-8809g
Known issues
Here are the changes found in Patchwork_133569v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@debugfs_test@basic-hwmon:
- bat-mtlp-8: NOTRUN -> [SKIP][1] ([i915#9318])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133569v1/bat-mtlp-8/igt@debugfs_t...@basic-hwmon.html
* igt@gem_lmem_swapping@verify-random:
- bat-mtlp-8: NOTRUN -> [SKIP][2] ([i915#4613]) +3 other tests skip
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133569v1/bat-mtlp-8/igt@gem_lmem_swapp...@verify-random.html
* igt@gem_mmap@basic:
- bat-mtlp-8: NOTRUN -> [SKIP][3] ([i915#4083])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133569v1/bat-mtlp-8/igt@gem_m...@basic.html
* igt@gem_mmap_gtt@basic:
- bat-mtlp-8: NOTRUN -> [SKIP][4] ([i915#4077]) +2 other tests skip
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133569v1/bat-mtlp-8/igt@gem_mmap_...@basic.html
* igt@gem_render_tiled_blits@basic:
- bat-mtlp-8: NOTRUN -> [SKIP][5] ([i915#4079]) +1 other test skip
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133569v1/bat-mtlp-8/igt@gem_render_tiled_bl...@basic.html
* igt@i915_pm_rps@basic-api:
- bat-mtlp-8: NOTRUN -> [SKIP][6] ([i915#6621])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133569v1/bat-mtlp-8/igt@i915_pm_...@basic-api.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-mtlp-8: NOTRUN -> [SKIP][7] ([i915#5190])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133569v1/bat-mtlp-8/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html
* igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-mtlp-8: NOTRUN -> [SKIP][8] ([i915#4212]) +8 other tests skip
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133569v1/bat-mtlp-8/igt@kms_addfb_ba...@basic-y-tiled-legacy.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-mtlp-8: NOTRUN -> [SKIP][9] ([i915#4213]) +1 other test skip
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133569v1/bat-mtlp-8/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html
* igt@kms_dsc@dsc-basic:
- bat-mtlp-8: NOTRUN -> [SKIP][10] ([i915#3555] / [i915#3840] /
[i915#9159])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133569v1/bat-mtlp-8/igt@kms_...@dsc-basic.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-mtlp-8: NOTRUN -> [SKIP][11]
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133569v1/bat-mtlp-8/igt@kms_force_connector_ba...@force-load-detect.html
* igt@kms_force_connector_basic@prune-stale-modes:
- bat-mtlp-8: NOTRUN -> [SKIP][12] ([i915#5274])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133569v1/bat-mtlp-8/igt@kms_force_connector_ba...@prune-stale-modes.html
* igt@kms_psr@psr-primary-mmap-gtt@edp-1:
- bat-mtlp-8: NOTRUN -> [SKIP][13] ([i915#4077] / [i915#9688])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133569v1/bat-mtlp-8/igt@kms_psr@psr-primary-mmap-...@edp-1.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-mtlp-8: NOTRUN -> [SKIP][14] ([i915#3555] / [i915#8809])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133569v1/bat-mtlp-8/igt@kms_setm...@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-mmap:
- bat-mtlp-8: NOTRUN -> [SKIP][15] ([i915#3708] / [i915#4077]) +1
other test skip
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133569v1/bat-mtlp-8/igt@prime_v...@basic-fence-mmap.html
* igt@prime_vgem@basic-fence-read:
- bat-mtlp-8: NOTRUN -> [SKIP][16] ([i915#3708]) +1 other test skip
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133569v1/bat-mtlp-8/igt@prime_v...@basic-fence-read.html
* igt@prime_vgem@basic-write:
- bat-mtlp-8: NOTRUN -> [SKIP][17] ([i915#10216] / [i915#3708])
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133569v1/bat-mtlp-8/igt@prime_v...@basic-write.html
Possible fixes
* igt@gem_wait@busy@all-engines:
- {bat-apl-1}:[ABORT][18] -> [PASS][19]
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14757/bat-apl-1/igt@gem_wait@b...@all-engines.html
[19]:
Re: [PATCH 16/16] drm/i915: Handle SKL+ WM/DDB registers next to all other plane registers
On Fri, 10 May 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Having the plane WM/DDB regitster write functions in skl_watermarks.c
> is rather annoying when trying to implement DSB based plane updates.
> Move them into the respective files that handle all other plane
> register writes. Less places where I need to worry about the DSB
> vs. MMIO decisions.
>
> The downside is that we spread the wm struct details a bit further
> afield. But if that becomes too annoying we can probably abstract
> things a bit more with a few extra functions.
>
> Signed-off-by: Ville Syrjälä
[snip]
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.h
> b/drivers/gpu/drm/i915/display/skl_universal_plane.h
> index e92e00c01b29..8eb4521ee851 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.h
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.h
> @@ -12,6 +12,8 @@ struct drm_i915_private;
> struct intel_crtc;
> struct intel_initial_plane_config;
> struct intel_plane_state;
> +struct skl_ddb_entry;
> +struct skl_wm_level;
>
> enum pipe;
> enum plane_id;
> @@ -35,4 +37,7 @@ bool icl_is_nv12_y_plane(struct drm_i915_private *dev_priv,
> u8 icl_hdr_plane_mask(void);
> bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id
> plane_id);
>
> +u32 skl_plane_ddb_reg_val(const struct skl_ddb_entry *entry);
> +u32 skl_plane_wm_reg_val(const struct skl_wm_level *level);
Yeah, I don't much like interfaces that return register values for
registers that aren't even known... but let's see how this pans out. It
does what it says on the box.
Reviewed-by: Jani Nikula
> +
> #endif
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
> b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 1daceb8ef9de..2064f72da675 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -1396,7 +1396,7 @@ skl_total_relative_data_rate(const struct
> intel_crtc_state *crtc_state)
> return data_rate;
> }
>
> -static const struct skl_wm_level *
> +const struct skl_wm_level *
> skl_plane_wm_level(const struct skl_pipe_wm *pipe_wm,
> enum plane_id plane_id,
> int level)
> @@ -1409,7 +1409,7 @@ skl_plane_wm_level(const struct skl_pipe_wm *pipe_wm,
> return >wm[level];
> }
>
> -static const struct skl_wm_level *
> +const struct skl_wm_level *
> skl_plane_trans_wm(const struct skl_pipe_wm *pipe_wm,
> enum plane_id plane_id)
> {
> @@ -2365,97 +2365,6 @@ static int skl_build_pipe_wm(struct intel_atomic_state
> *state,
> return skl_wm_check_vblank(crtc_state);
> }
>
> -static u32 skl_plane_ddb_reg_val(const struct skl_ddb_entry *entry)
> -{
> - if (!entry->end)
> - return 0;
> -
> - return PLANE_BUF_END(entry->end - 1) |
> - PLANE_BUF_START(entry->start);
> -}
> -
> -static u32 skl_plane_wm_reg_val(const struct skl_wm_level *level)
> -{
> - u32 val = 0;
> -
> - if (level->enable)
> - val |= PLANE_WM_EN;
> - if (level->ignore_lines)
> - val |= PLANE_WM_IGNORE_LINES;
> - val |= REG_FIELD_PREP(PLANE_WM_BLOCKS_MASK, level->blocks);
> - val |= REG_FIELD_PREP(PLANE_WM_LINES_MASK, level->lines);
> -
> - return val;
> -}
> -
> -void skl_write_plane_wm(struct intel_plane *plane,
> - const struct intel_crtc_state *crtc_state)
> -{
> - struct drm_i915_private *i915 = to_i915(plane->base.dev);
> - enum plane_id plane_id = plane->id;
> - enum pipe pipe = plane->pipe;
> - const struct skl_pipe_wm *pipe_wm = _state->wm.skl.optimal;
> - const struct skl_ddb_entry *ddb =
> - _state->wm.skl.plane_ddb[plane_id];
> - const struct skl_ddb_entry *ddb_y =
> - _state->wm.skl.plane_ddb_y[plane_id];
> - int level;
> -
> - for (level = 0; level < i915->display.wm.num_levels; level++)
> - intel_de_write_fw(i915, PLANE_WM(pipe, plane_id, level),
> -
> skl_plane_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));
> -
> - intel_de_write_fw(i915, PLANE_WM_TRANS(pipe, plane_id),
> - skl_plane_wm_reg_val(skl_plane_trans_wm(pipe_wm,
> plane_id)));
> -
> - if (HAS_HW_SAGV_WM(i915)) {
> - const struct skl_plane_wm *wm = _wm->planes[plane_id];
> -
> - intel_de_write_fw(i915, PLANE_WM_SAGV(pipe, plane_id),
> - skl_plane_wm_reg_val(>sagv.wm0));
> - intel_de_write_fw(i915, PLANE_WM_SAGV_TRANS(pipe, plane_id),
> - skl_plane_wm_reg_val(>sagv.trans_wm));
> - }
> -
> - intel_de_write_fw(i915, PLANE_BUF_CFG(pipe, plane_id),
> - skl_plane_ddb_reg_val(ddb));
> -
> - if (DISPLAY_VER(i915) < 11)
> - intel_de_write_fw(i915, PLANE_NV12_BUF_CFG(pipe, plane_id),
> - skl_plane_ddb_reg_val(ddb_y));
> -}
>
Re: [PATCH 15/16] drm/i915: Nuke skl_write_wm_level() and skl_ddb_entry_write()
On Fri, 10 May 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Get rid of skl_ddb_entry_write() and skl_write_wm_level() and
> just call intel_de_write_fw() directly.
>
> This is prep work towards DSB based plane updates where these
> wrappers are more of a hinderance.
>
> Done with cocci mostly:
> @@
> expression D, R, L;
> @@
> - skl_write_wm_level(D, R, L)
> + intel_de_write_fw(D, R, skl_plane_wm_reg_val(L))
>
> @@
> expression D, R, B;
> @@
> - skl_ddb_entry_write(D, R, B)
> + intel_de_write_fw(D, R, skl_plane_ddb_reg_val(B))
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/skl_watermark.c | 57
> 1 file changed, 22 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
> b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 8a0a26ab8e6a..1daceb8ef9de 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -2374,13 +2374,6 @@ static u32 skl_plane_ddb_reg_val(const struct
> skl_ddb_entry *entry)
> PLANE_BUF_START(entry->start);
> }
>
> -static void skl_ddb_entry_write(struct drm_i915_private *i915,
> - i915_reg_t reg,
> - const struct skl_ddb_entry *entry)
> -{
> - intel_de_write_fw(i915, reg, skl_plane_ddb_reg_val(entry));
> -}
> -
> static u32 skl_plane_wm_reg_val(const struct skl_wm_level *level)
> {
> u32 val = 0;
> @@ -2395,13 +2388,6 @@ static u32 skl_plane_wm_reg_val(const struct
> skl_wm_level *level)
> return val;
> }
>
> -static void skl_write_wm_level(struct drm_i915_private *i915,
> -i915_reg_t reg,
> -const struct skl_wm_level *level)
> -{
> - intel_de_write_fw(i915, reg, skl_plane_wm_reg_val(level));
> -}
> -
> void skl_write_plane_wm(struct intel_plane *plane,
> const struct intel_crtc_state *crtc_state)
> {
> @@ -2416,27 +2402,27 @@ void skl_write_plane_wm(struct intel_plane *plane,
> int level;
>
> for (level = 0; level < i915->display.wm.num_levels; level++)
> - skl_write_wm_level(i915, PLANE_WM(pipe, plane_id, level),
> -skl_plane_wm_level(pipe_wm, plane_id,
> level));
> + intel_de_write_fw(i915, PLANE_WM(pipe, plane_id, level),
> +
> skl_plane_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));
>
> - skl_write_wm_level(i915, PLANE_WM_TRANS(pipe, plane_id),
> -skl_plane_trans_wm(pipe_wm, plane_id));
> + intel_de_write_fw(i915, PLANE_WM_TRANS(pipe, plane_id),
> + skl_plane_wm_reg_val(skl_plane_trans_wm(pipe_wm,
> plane_id)));
>
> if (HAS_HW_SAGV_WM(i915)) {
> const struct skl_plane_wm *wm = _wm->planes[plane_id];
>
> - skl_write_wm_level(i915, PLANE_WM_SAGV(pipe, plane_id),
> ->sagv.wm0);
> - skl_write_wm_level(i915, PLANE_WM_SAGV_TRANS(pipe, plane_id),
> ->sagv.trans_wm);
> + intel_de_write_fw(i915, PLANE_WM_SAGV(pipe, plane_id),
> + skl_plane_wm_reg_val(>sagv.wm0));
> + intel_de_write_fw(i915, PLANE_WM_SAGV_TRANS(pipe, plane_id),
> + skl_plane_wm_reg_val(>sagv.trans_wm));
> }
>
> - skl_ddb_entry_write(i915,
> - PLANE_BUF_CFG(pipe, plane_id), ddb);
> + intel_de_write_fw(i915, PLANE_BUF_CFG(pipe, plane_id),
> + skl_plane_ddb_reg_val(ddb));
>
> if (DISPLAY_VER(i915) < 11)
> - skl_ddb_entry_write(i915,
> - PLANE_NV12_BUF_CFG(pipe, plane_id), ddb_y);
> + intel_de_write_fw(i915, PLANE_NV12_BUF_CFG(pipe, plane_id),
> + skl_plane_ddb_reg_val(ddb_y));
> }
>
> void skl_write_cursor_wm(struct intel_plane *plane,
> @@ -2451,22 +2437,23 @@ void skl_write_cursor_wm(struct intel_plane *plane,
> int level;
>
> for (level = 0; level < i915->display.wm.num_levels; level++)
> - skl_write_wm_level(i915, CUR_WM(pipe, level),
> -skl_plane_wm_level(pipe_wm, plane_id,
> level));
> + intel_de_write_fw(i915, CUR_WM(pipe, level),
> +
> skl_plane_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));
>
> - skl_write_wm_level(i915, CUR_WM_TRANS(pipe),
> -skl_plane_trans_wm(pipe_wm, plane_id));
> + intel_de_write_fw(i915, CUR_WM_TRANS(pipe),
> + skl_plane_wm_reg_val(skl_plane_trans_wm(pipe_wm,
> plane_id)));
>
> if (HAS_HW_SAGV_WM(i915)) {
> const struct skl_plane_wm *wm = _wm->planes[plane_id];
>
> - skl_write_wm_level(i915, CUR_WM_SAGV(pipe),
> -
Re: [PATCH v2 13/16] drm/i915: Refactor skl+ plane register offset calculations
On Mon, 13 May 2024, Jani Nikula wrote: > On Mon, 13 May 2024, Ville Syrjala wrote: >> From: Ville Syrjälä >> >> Currentluy every skl+ plane register defines some intermediate *Currently >> macros to calculate the final register offset. Pull all of that >> into common macros, simplifying the final register offset stuff >> into just five defines: >> - raw register offsets for the planes 1 and 2 on pipes A and B >> - the final parametrized macro >> >> v2: Rebase >> >> Signed-off-by: Ville Syrjälä > > Nice cleanup, > > Reviewed-by: Jani Nikula -- Jani Nikula, Intel
Re: [PATCH 14/16] drm/i915: Extract skl_plane_{wm,ddb}_reg_val()
On Fri, 10 May 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Extract helpers to calculate the final wm/ddb register
> values for skl+. Will allow me to more cleanly remove the
> register write wrappers for these registers.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/skl_watermark.c | 29 +---
> 1 file changed, 19 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
> b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 2a2073bf3aca..8a0a26ab8e6a 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -2365,21 +2365,23 @@ static int skl_build_pipe_wm(struct
> intel_atomic_state *state,
> return skl_wm_check_vblank(crtc_state);
> }
>
> +static u32 skl_plane_ddb_reg_val(const struct skl_ddb_entry *entry)
> +{
> + if (!entry->end)
> + return 0;
> +
> + return PLANE_BUF_END(entry->end - 1) |
> + PLANE_BUF_START(entry->start);
> +}
> +
> static void skl_ddb_entry_write(struct drm_i915_private *i915,
> i915_reg_t reg,
> const struct skl_ddb_entry *entry)
> {
> - if (entry->end)
> - intel_de_write_fw(i915, reg,
> - PLANE_BUF_END(entry->end - 1) |
> - PLANE_BUF_START(entry->start));
> - else
> - intel_de_write_fw(i915, reg, 0);
> + intel_de_write_fw(i915, reg, skl_plane_ddb_reg_val(entry));
> }
>
> -static void skl_write_wm_level(struct drm_i915_private *i915,
> -i915_reg_t reg,
> -const struct skl_wm_level *level)
> +static u32 skl_plane_wm_reg_val(const struct skl_wm_level *level)
> {
> u32 val = 0;
>
> @@ -2390,7 +2392,14 @@ static void skl_write_wm_level(struct drm_i915_private
> *i915,
> val |= REG_FIELD_PREP(PLANE_WM_BLOCKS_MASK, level->blocks);
> val |= REG_FIELD_PREP(PLANE_WM_LINES_MASK, level->lines);
>
> - intel_de_write_fw(i915, reg, val);
> + return val;
> +}
> +
> +static void skl_write_wm_level(struct drm_i915_private *i915,
> +i915_reg_t reg,
> +const struct skl_wm_level *level)
> +{
> + intel_de_write_fw(i915, reg, skl_plane_wm_reg_val(level));
> }
>
> void skl_write_plane_wm(struct intel_plane *plane,
--
Jani Nikula, Intel
Re: [PATCH v2 13/16] drm/i915: Refactor skl+ plane register offset calculations
On Mon, 13 May 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > Currentluy every skl+ plane register defines some intermediate > macros to calculate the final register offset. Pull all of that > into common macros, simplifying the final register offset stuff > into just five defines: > - raw register offsets for the planes 1 and 2 on pipes A and B > - the final parametrized macro > > v2: Rebase > > Signed-off-by: Ville Syrjälä Nice cleanup, Reviewed-by: Jani Nikula > --- > .../i915/display/skl_universal_plane_regs.h | 185 +- > 1 file changed, 93 insertions(+), 92 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h > b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h > index 0b4f97059479..cb3bdd71b6b2 100644 > --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h > @@ -8,13 +8,22 @@ > > #include "intel_display_reg_defs.h" > > +#define _SKL_PLANE(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \ > + _PLANE((plane), _PIPE((pipe), (reg_1_a), (reg_1_b)), _PIPE((pipe), > (reg_2_a), (reg_2_b))) > +#define _SKL_PLANE_DW(pipe, plane, dw, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \ > + (_SKL_PLANE((pipe), (plane), (reg_1_a), (reg_1_b), (reg_2_a), > (reg_2_b)) + (dw) * 4) > +#define _MMIO_SKL_PLANE(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \ > + _MMIO(_SKL_PLANE((pipe), (plane), (reg_1_a), (reg_1_b), (reg_2_a), > (reg_2_b))) > +#define _MMIO_SKL_PLANE_DW(pipe, plane, dw, reg_1_a, reg_1_b, reg_2_a, > reg_2_b) \ > + _MMIO(_SKL_PLANE_DW((pipe), (plane), (dw), (reg_1_a), (reg_1_b), > (reg_2_a), (reg_2_b))) > + > #define _PLANE_CTL_1_A 0x70180 > #define _PLANE_CTL_2_A 0x70280 > #define _PLANE_CTL_1_B 0x71180 > #define _PLANE_CTL_2_B 0x71280 > -#define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, > _PLANE_CTL_1_B) > -#define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, > _PLANE_CTL_2_B) > -#define PLANE_CTL(pipe, plane) _MMIO_PLANE(plane, > _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe)) > +#define PLANE_CTL(pipe, plane) _MMIO_SKL_PLANE((pipe), > (plane), \ > + _PLANE_CTL_1_A, > _PLANE_CTL_1_B, \ > + _PLANE_CTL_2_A, > _PLANE_CTL_2_B) > #define PLANE_CTL_ENABLE REG_BIT(31) > #define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */ > #define PLANE_CTL_ARB_SLOTS(x) > REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */ > @@ -83,9 +92,9 @@ > #define _PLANE_STRIDE_2_A0x70288 > #define _PLANE_STRIDE_1_B0x71188 > #define _PLANE_STRIDE_2_B0x71288 > -#define _PLANE_STRIDE_1(pipe)_PIPE(pipe, _PLANE_STRIDE_1_A, > _PLANE_STRIDE_1_B) > -#define _PLANE_STRIDE_2(pipe)_PIPE(pipe, _PLANE_STRIDE_2_A, > _PLANE_STRIDE_2_B) > -#define PLANE_STRIDE(pipe, plane)_MMIO_PLANE(plane, > _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe)) > +#define PLANE_STRIDE(pipe, plane)_MMIO_SKL_PLANE((pipe), (plane), \ > + _PLANE_STRIDE_1_A, > _PLANE_STRIDE_1_B, \ > + _PLANE_STRIDE_2_A, > _PLANE_STRIDE_2_B) > #define PLANE_STRIDE__MASK REG_GENMASK(11, 0) > #define PLANE_STRIDE_(stride) > REG_FIELD_PREP(PLANE_STRIDE__MASK, (stride)) > > @@ -93,9 +102,9 @@ > #define _PLANE_POS_2_A 0x7028c > #define _PLANE_POS_1_B 0x7118c > #define _PLANE_POS_2_B 0x7128c > -#define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, > _PLANE_POS_1_B) > -#define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, > _PLANE_POS_2_B) > -#define PLANE_POS(pipe, plane) _MMIO_PLANE(plane, > _PLANE_POS_1(pipe), _PLANE_POS_2(pipe)) > +#define PLANE_POS(pipe, plane) _MMIO_SKL_PLANE((pipe), > (plane), \ > + _PLANE_POS_1_A, > _PLANE_POS_1_B, \ > + _PLANE_POS_2_A, > _PLANE_POS_2_B) > #define PLANE_POS_Y_MASK REG_GENMASK(31, 16) > #define PLANE_POS_Y(y) > REG_FIELD_PREP(PLANE_POS_Y_MASK, (y)) > #define PLANE_POS_X_MASK REG_GENMASK(15, 0) > @@ -105,9 +114,9 @@ > #define _PLANE_SIZE_2_A 0x70290 > #define _PLANE_SIZE_1_B 0x71190 > #define _PLANE_SIZE_2_B 0x71290 > -#define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, > _PLANE_SIZE_1_B) >
Re: [PATCH v2 10/16] drm/i915: Shuffle the skl+ plane register definitions
On Mon, 13 May 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > Rearrange the plane skl+ universal plane register definitions: > - keep everything related to the same register in one place > - sort based on register offset > - unify the whitespace/etc a bit > > v2: Define register contents after all offsets (Jani) Thanks for doing this. Reviewed-by: Jani Nikula > > Cc: Jani Nikula > Signed-off-by: Ville Syrjälä > --- > .../i915/display/skl_universal_plane_regs.h | 481 -- > 1 file changed, 200 insertions(+), 281 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h > b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h > index 49278584caa7..5fcd5898af4f 100644 > --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h > @@ -10,6 +10,11 @@ > > #define _PLANE_CTL_1_A 0x70180 > #define _PLANE_CTL_2_A 0x70280 > +#define _PLANE_CTL_1_B 0x71180 > +#define _PLANE_CTL_2_B 0x71280 > +#define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, > _PLANE_CTL_1_B) > +#define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, > _PLANE_CTL_2_B) > +#define PLANE_CTL(pipe, plane) _MMIO_PLANE(plane, > _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe)) > #define PLANE_CTL_ENABLE REG_BIT(31) > #define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */ > #define PLANE_CTL_ARB_SLOTS(x) > REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */ > @@ -73,54 +78,132 @@ > #define PLANE_CTL_ROTATE_90 > REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 1) > #define PLANE_CTL_ROTATE_180 > REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 2) > #define PLANE_CTL_ROTATE_270 > REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 3) > + > #define _PLANE_STRIDE_1_A0x70188 > #define _PLANE_STRIDE_2_A0x70288 > +#define _PLANE_STRIDE_1_B0x71188 > +#define _PLANE_STRIDE_2_B0x71288 > +#define _PLANE_STRIDE_1(pipe)_PIPE(pipe, _PLANE_STRIDE_1_A, > _PLANE_STRIDE_1_B) > +#define _PLANE_STRIDE_2(pipe)_PIPE(pipe, _PLANE_STRIDE_2_A, > _PLANE_STRIDE_2_B) > +#define PLANE_STRIDE(pipe, plane)_MMIO_PLANE(plane, > _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe)) > #define PLANE_STRIDE__MASK REG_GENMASK(11, 0) > #define PLANE_STRIDE_(stride) > REG_FIELD_PREP(PLANE_STRIDE__MASK, (stride)) > + > #define _PLANE_POS_1_A 0x7018c > #define _PLANE_POS_2_A 0x7028c > +#define _PLANE_POS_1_B 0x7118c > +#define _PLANE_POS_2_B 0x7128c > +#define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, > _PLANE_POS_1_B) > +#define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, > _PLANE_POS_2_B) > +#define PLANE_POS(pipe, plane) _MMIO_PLANE(plane, > _PLANE_POS_1(pipe), _PLANE_POS_2(pipe)) > #define PLANE_POS_Y_MASK REG_GENMASK(31, 16) > #define PLANE_POS_Y(y) > REG_FIELD_PREP(PLANE_POS_Y_MASK, (y)) > #define PLANE_POS_X_MASK REG_GENMASK(15, 0) > #define PLANE_POS_X(x) > REG_FIELD_PREP(PLANE_POS_X_MASK, (x)) > + > #define _PLANE_SIZE_1_A 0x70190 > #define _PLANE_SIZE_2_A 0x70290 > +#define _PLANE_SIZE_1_B 0x71190 > +#define _PLANE_SIZE_2_B 0x71290 > +#define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, > _PLANE_SIZE_1_B) > +#define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, > _PLANE_SIZE_2_B) > +#define PLANE_SIZE(pipe, plane) _MMIO_PLANE(plane, > _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe)) > #define PLANE_HEIGHT_MASK REG_GENMASK(31, 16) > #define PLANE_HEIGHT(h) > REG_FIELD_PREP(PLANE_HEIGHT_MASK, (h)) > #define PLANE_WIDTH_MASK REG_GENMASK(15, 0) > #define PLANE_WIDTH(w) > REG_FIELD_PREP(PLANE_WIDTH_MASK, (w)) > + > +#define _PLANE_KEYVAL_1_A0x70194 > +#define _PLANE_KEYVAL_2_A0x70294 > +#define _PLANE_KEYVAL_1_B0x71194 > +#define _PLANE_KEYVAL_2_B0x71294 > +#define _PLANE_KEYVAL_1(pipe)_PIPE(pipe, _PLANE_KEYVAL_1_A, > _PLANE_KEYVAL_1_B) > +#define _PLANE_KEYVAL_2(pipe)_PIPE(pipe, _PLANE_KEYVAL_2_A, > _PLANE_KEYVAL_2_B) > +#define PLANE_KEYVAL(pipe, plane)_MMIO_PLANE(plane, > _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe)) > + > +#define
[PATCH] drm/edid: remove drm_do_get_edid()
All users of drm_do_get_edid() have been converted to
drm_edid_read_custom(). Remove the unused function to prevent new users
from creeping in.
Signed-off-by: Jani Nikula
---
Cc: Robert Foss
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: Thomas Zimmermann
---
drivers/gpu/drm/drm_edid.c | 28
include/drm/drm_edid.h | 4
2 files changed, 32 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 4f54c91b31b2..0f7c4c5b14b9 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -2464,34 +2464,6 @@ static struct edid *_drm_do_get_edid(struct
drm_connector *connector,
return NULL;
}
-/**
- * drm_do_get_edid - get EDID data using a custom EDID block read function
- * @connector: connector we're probing
- * @read_block: EDID block read function
- * @context: private data passed to the block read function
- *
- * When the I2C adapter connected to the DDC bus is hidden behind a device that
- * exposes a different interface to read EDID blocks this function can be used
- * to get EDID data using a custom block read function.
- *
- * As in the general case the DDC bus is accessible by the kernel at the I2C
- * level, drivers must make all reasonable efforts to expose it as an I2C
- * adapter and use drm_get_edid() instead of abusing this function.
- *
- * The EDID may be overridden using debugfs override_edid or firmware EDID
- * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
- * order. Having either of them bypasses actual EDID reads.
- *
- * Return: Pointer to valid EDID or NULL if we couldn't find any.
- */
-struct edid *drm_do_get_edid(struct drm_connector *connector,
-read_block_fn read_block,
-void *context)
-{
- return _drm_do_get_edid(connector, read_block, context, NULL);
-}
-EXPORT_SYMBOL_GPL(drm_do_get_edid);
-
/**
* drm_edid_raw - Get a pointer to the raw EDID data.
* @drm_edid: drm_edid container
diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h
index b085525e53e2..6bdfa254a1c1 100644
--- a/include/drm/drm_edid.h
+++ b/include/drm/drm_edid.h
@@ -423,10 +423,6 @@ static inline void drm_edid_decode_panel_id(u32 panel_id,
char vend[4], u16 *pro
}
bool drm_probe_ddc(struct i2c_adapter *adapter);
-struct edid *drm_do_get_edid(struct drm_connector *connector,
- int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
- size_t len),
- void *data);
struct edid *drm_get_edid(struct drm_connector *connector,
struct i2c_adapter *adapter);
struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
--
2.39.2
Re: [PATCH 1/2] drm/xe/display: remove unused xe->enabled_irq_mask
On Mon, 13 May 2024, Lucas De Marchi wrote:
> On Mon, May 13, 2024 at 03:10:29PM GMT, Jani Nikula wrote:
>>On Fri, 10 May 2024, Jani Nikula wrote:
>>> The xe->enabled_irq_mask member has never been used for anything.
>>>
>>> Signed-off-by: Jani Nikula
>>
>>Lucas, ack for merging these two via drm-intel-next? Even though these
>>touch struct xe_device, I presume any further cleanups touching the
>>surrounding context would have a bigger footprint in drm-intel-next.
>
>
>
> Acked-by: Lucas De Marchi
>
> for both patches
Thanks for the review and acks, pushed to drm-intel-next.
BR,
Jani.
>
> thanks,
> Lucas De Marchi
>
>>
>>BR,
>>Jani.
>>
>>> ---
>>> drivers/gpu/drm/xe/display/xe_display.c | 1 -
>>> drivers/gpu/drm/xe/xe_device_types.h| 2 --
>>> 2 files changed, 3 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/xe/display/xe_display.c
>>> b/drivers/gpu/drm/xe/display/xe_display.c
>>> index 0de0566e5b39..fbe2c2eddea9 100644
>>> --- a/drivers/gpu/drm/xe/display/xe_display.c
>>> +++ b/drivers/gpu/drm/xe/display/xe_display.c
>>> @@ -97,7 +97,6 @@ int xe_display_create(struct xe_device *xe)
>>> xe->display.hotplug.dp_wq = alloc_ordered_workqueue("xe-dp", 0);
>>>
>>> drmm_mutex_init(>drm, >sb_lock);
>>> - xe->enabled_irq_mask = ~0;
>>>
>>> return drmm_add_action_or_reset(>drm, display_destroy, NULL);
>>> }
>>> diff --git a/drivers/gpu/drm/xe/xe_device_types.h
>>> b/drivers/gpu/drm/xe/xe_device_types.h
>>> index 906b98fb973b..b78223e3baab 100644
>>> --- a/drivers/gpu/drm/xe/xe_device_types.h
>>> +++ b/drivers/gpu/drm/xe/xe_device_types.h
>>> @@ -517,8 +517,6 @@ struct xe_device {
>>> /* only to allow build, not used functionally */
>>> u32 irq_mask;
>>>
>>> - u32 enabled_irq_mask;
>>> -
>>> struct intel_uncore {
>>> spinlock_t lock;
>>> } uncore;
>>
>>--
>>Jani Nikula, Intel
--
Jani Nikula, Intel
Re: [PATCH 2/9] drm: Export drm_plane_has_format()
On Mon, 13 May 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > Export drm_plane_has_format() so that drivers can use it. > > Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/drm_crtc_internal.h | 2 -- > drivers/gpu/drm/drm_plane.c | 1 + > include/drm/drm_plane.h | 2 ++ > 3 files changed, 3 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/drm_crtc_internal.h > b/drivers/gpu/drm/drm_crtc_internal.h > index 898e0e8b51be..e207759ca045 100644 > --- a/drivers/gpu/drm/drm_crtc_internal.h > +++ b/drivers/gpu/drm/drm_crtc_internal.h > @@ -272,8 +272,6 @@ int drm_mode_atomic_ioctl(struct drm_device *dev, > /* drm_plane.c */ > int drm_plane_register_all(struct drm_device *dev); > void drm_plane_unregister_all(struct drm_device *dev); > -bool drm_plane_has_format(struct drm_plane *plane, > - u32 format, u64 modifier); > struct drm_mode_rect * > __drm_plane_get_damage_clips(const struct drm_plane_state *state); > > diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c > index 268aa2299df5..a51d4dd3f7de 100644 > --- a/drivers/gpu/drm/drm_plane.c > +++ b/drivers/gpu/drm/drm_plane.c > @@ -906,6 +906,7 @@ bool drm_plane_has_format(struct drm_plane *plane, > > return true; > } > +EXPORT_SYMBOL(drm_plane_has_format); > > static int __setplane_check(struct drm_plane *plane, > struct drm_crtc *crtc, > diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h > index 9507542121fa..dd718c62ac31 100644 > --- a/include/drm/drm_plane.h > +++ b/include/drm/drm_plane.h > @@ -972,6 +972,8 @@ static inline struct drm_plane *drm_plane_find(struct > drm_device *dev, > #define drm_for_each_plane(plane, dev) \ > list_for_each_entry(plane, &(dev)->mode_config.plane_list, head) > > +bool drm_plane_has_format(struct drm_plane *plane, > + u32 format, u64 modifier); > bool drm_any_plane_has_format(struct drm_device *dev, > u32 format, u64 modifier); -- Jani Nikula, Intel
Re: [PATCH 1/9] drm: Rename drm_plane_check_pixel_format() to drm_plane_has_format()
On Mon, 13 May 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Rename drm_plane_check_pixel_format() to drm_plane_has_format()
> and change the return type accordingly. Allows one to write
> more natural code.
>
> Also matches drm_any_plane_has_format() better.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/drm_atomic.c| 7 ++-
> drivers/gpu/drm/drm_crtc.c | 6 ++
> drivers/gpu/drm/drm_crtc_internal.h | 4 ++--
> drivers/gpu/drm/drm_plane.c | 22 ++
> 4 files changed, 16 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
> index a91737adf8e7..e22560213b8e 100644
> --- a/drivers/gpu/drm/drm_atomic.c
> +++ b/drivers/gpu/drm/drm_atomic.c
> @@ -608,7 +608,6 @@ static int drm_atomic_plane_check(const struct
> drm_plane_state *old_plane_state,
> unsigned int fb_width, fb_height;
> struct drm_mode_rect *clips;
> uint32_t num_clips;
> - int ret;
>
> /* either *both* CRTC and FB must be set, or neither */
> if (crtc && !fb) {
> @@ -635,14 +634,12 @@ static int drm_atomic_plane_check(const struct
> drm_plane_state *old_plane_state,
> }
>
> /* Check whether this plane supports the fb pixel format. */
> - ret = drm_plane_check_pixel_format(plane, fb->format->format,
> -fb->modifier);
> - if (ret) {
> + if (!drm_plane_has_format(plane, fb->format->format, fb->modifier)) {
> drm_dbg_atomic(plane->dev,
> "[PLANE:%d:%s] invalid pixel format %p4cc,
> modifier 0x%llx\n",
> plane->base.id, plane->name,
> >format->format, fb->modifier);
> - return ret;
> + return -EINVAL;
> }
>
> /* Give drivers some help against integer overflows */
> diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
> index 483969b84a30..3488ff067c69 100644
> --- a/drivers/gpu/drm/drm_crtc.c
> +++ b/drivers/gpu/drm/drm_crtc.c
> @@ -789,12 +789,10 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data,
>* case.
>*/
> if (!plane->format_default) {
> - ret = drm_plane_check_pixel_format(plane,
> -fb->format->format,
> -fb->modifier);
> - if (ret) {
> + if (!drm_plane_has_format(plane, fb->format->format,
> fb->modifier)) {
> drm_dbg_kms(dev, "Invalid pixel format %p4cc,
> modifier 0x%llx\n",
> >format->format, fb->modifier);
> + ret = -EINVAL;
> goto out;
> }
> }
> diff --git a/drivers/gpu/drm/drm_crtc_internal.h
> b/drivers/gpu/drm/drm_crtc_internal.h
> index 25aaae937ceb..898e0e8b51be 100644
> --- a/drivers/gpu/drm/drm_crtc_internal.h
> +++ b/drivers/gpu/drm/drm_crtc_internal.h
> @@ -272,8 +272,8 @@ int drm_mode_atomic_ioctl(struct drm_device *dev,
> /* drm_plane.c */
> int drm_plane_register_all(struct drm_device *dev);
> void drm_plane_unregister_all(struct drm_device *dev);
> -int drm_plane_check_pixel_format(struct drm_plane *plane,
> - u32 format, u64 modifier);
> +bool drm_plane_has_format(struct drm_plane *plane,
> + u32 format, u64 modifier);
> struct drm_mode_rect *
> __drm_plane_get_damage_clips(const struct drm_plane_state *state);
>
> diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c
> index 57662a1fd345..268aa2299df5 100644
> --- a/drivers/gpu/drm/drm_plane.c
> +++ b/drivers/gpu/drm/drm_plane.c
> @@ -877,8 +877,8 @@ int drm_mode_getplane(struct drm_device *dev, void *data,
> return 0;
> }
>
> -int drm_plane_check_pixel_format(struct drm_plane *plane,
> - u32 format, u64 modifier)
> +bool drm_plane_has_format(struct drm_plane *plane,
> + u32 format, u64 modifier)
> {
> unsigned int i;
>
> @@ -887,24 +887,24 @@ int drm_plane_check_pixel_format(struct drm_plane
> *plane,
> break;
> }
> if (i == plane->format_count)
> - return -EINVAL;
> + return false;
>
> if (plane->funcs->format_mod_supported) {
> if (!plane->funcs->format_mod_supported(plane, format,
> modifier))
> - return -EINVAL;
> + return false;
> } else {
> if (!plane->modifier_count)
> - return 0;
> + return true;
>
> for (i = 0; i < plane->modifier_count; i++) {
> if (modifier == plane->modifiers[i])
>
✗ Fi.CI.BAT: failure for drm/i915: Polish plane surface alignment handling
== Series Details == Series: drm/i915: Polish plane surface alignment handling URL : https://patchwork.freedesktop.org/series/133564/ State : failure == Summary == CI Bug Log - changes from CI_DRM_14756 -> Patchwork_133564v1 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_133564v1 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_133564v1, please notify your bug team (i915-ci-in...@lists.freedesktop.org) to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133564v1/index.html Participating hosts (42 -> 43) -- Additional (2): bat-dg2-11 fi-kbl-8809g Missing(1): fi-snb-2520m Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_133564v1: ### IGT changes ### Possible regressions * igt@gem_exec_fence@basic-await@vcs0: - bat-adln-1: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14756/bat-adln-1/igt@gem_exec_fence@basic-aw...@vcs0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133564v1/bat-adln-1/igt@gem_exec_fence@basic-aw...@vcs0.html Known issues Here are the changes found in Patchwork_133564v1 that come from known issues: ### IGT changes ### Issues hit * igt@gem_huc_copy@huc-copy: - fi-kbl-8809g: NOTRUN -> [SKIP][3] ([i915#2190]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133564v1/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@parallel-random-engines: - fi-kbl-8809g: NOTRUN -> [SKIP][4] ([i915#4613]) +3 other tests skip [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133564v1/fi-kbl-8809g/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_mmap@basic: - bat-dg2-11: NOTRUN -> [SKIP][5] ([i915#4083]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133564v1/bat-dg2-11/igt@gem_m...@basic.html * igt@gem_render_tiled_blits@basic: - bat-dg2-11: NOTRUN -> [SKIP][6] ([i915#4079]) +1 other test skip [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133564v1/bat-dg2-11/igt@gem_render_tiled_bl...@basic.html * igt@gem_tiled_fence_blits@basic: - bat-dg2-11: NOTRUN -> [SKIP][7] ([i915#4077]) +2 other tests skip [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133564v1/bat-dg2-11/igt@gem_tiled_fence_bl...@basic.html * igt@i915_pm_rps@basic-api: - bat-dg2-11: NOTRUN -> [SKIP][8] ([i915#6621]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133564v1/bat-dg2-11/igt@i915_pm_...@basic-api.html * igt@i915_selftest@live@execlists: - fi-bsw-nick:[PASS][9] -> [ABORT][10] ([i915#10594]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14756/fi-bsw-nick/igt@i915_selftest@l...@execlists.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133564v1/fi-bsw-nick/igt@i915_selftest@l...@execlists.html * igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy: - bat-dg2-11: NOTRUN -> [SKIP][11] ([i915#4212]) +7 other tests skip [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133564v1/bat-dg2-11/igt@kms_addfb_ba...@addfb25-x-tiled-mismatch-legacy.html * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: - bat-dg2-11: NOTRUN -> [SKIP][12] ([i915#5190]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133564v1/bat-dg2-11/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html * igt@kms_addfb_basic@basic-y-tiled-legacy: - bat-dg2-11: NOTRUN -> [SKIP][13] ([i915#4215] / [i915#5190]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133564v1/bat-dg2-11/igt@kms_addfb_ba...@basic-y-tiled-legacy.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - bat-dg2-11: NOTRUN -> [SKIP][14] ([i915#4103] / [i915#4213]) +1 other test skip [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133564v1/bat-dg2-11/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html * igt@kms_dsc@dsc-basic: - fi-kbl-8809g: NOTRUN -> [SKIP][15] +30 other tests skip [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133564v1/fi-kbl-8809g/igt@kms_...@dsc-basic.html - bat-dg2-11: NOTRUN -> [SKIP][16] ([i915#3555] / [i915#3840]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133564v1/bat-dg2-11/igt@kms_...@dsc-basic.html * igt@kms_force_connector_basic@force-load-detect: - bat-dg2-11: NOTRUN -> [SKIP][17] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133564v1/bat-dg2-11/igt@kms_force_connector_ba...@force-load-detect.html *
✗ Fi.CI.SPARSE: warning for drm/i915: Polish plane surface alignment handling
== Series Details == Series: drm/i915: Polish plane surface alignment handling URL : https://patchwork.freedesktop.org/series/133564/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
✓ Fi.CI.BAT: success for drm/i915: skl+ plane register stuff (rev6)
== Series Details == Series: drm/i915: skl+ plane register stuff (rev6) URL : https://patchwork.freedesktop.org/series/133458/ State : success == Summary == CI Bug Log - changes from CI_DRM_14756 -> Patchwork_133458v6 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/index.html Participating hosts (42 -> 40) -- Additional (2): bat-dg2-11 fi-elk-e7500 Missing(4): bat-dg1-7 bat-kbl-2 fi-snb-2520m bat-mtlp-6 Known issues Here are the changes found in Patchwork_133458v6 that come from known issues: ### IGT changes ### Issues hit * igt@gem_mmap@basic: - bat-dg2-11: NOTRUN -> [SKIP][1] ([i915#4083]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/bat-dg2-11/igt@gem_m...@basic.html * igt@gem_tiled_fence_blits@basic: - bat-dg2-11: NOTRUN -> [SKIP][2] ([i915#4077]) +2 other tests skip [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/bat-dg2-11/igt@gem_tiled_fence_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-dg2-11: NOTRUN -> [SKIP][3] ([i915#4079]) +1 other test skip [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/bat-dg2-11/igt@gem_tiled_pread_basic.html * igt@i915_pm_rps@basic-api: - bat-dg2-11: NOTRUN -> [SKIP][4] ([i915#6621]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/bat-dg2-11/igt@i915_pm_...@basic-api.html * igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy: - bat-dg2-11: NOTRUN -> [SKIP][5] ([i915#4212]) +7 other tests skip [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/bat-dg2-11/igt@kms_addfb_ba...@addfb25-x-tiled-mismatch-legacy.html * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: - bat-dg2-11: NOTRUN -> [SKIP][6] ([i915#5190]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/bat-dg2-11/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html * igt@kms_addfb_basic@basic-y-tiled-legacy: - bat-dg2-11: NOTRUN -> [SKIP][7] ([i915#4215] / [i915#5190]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/bat-dg2-11/igt@kms_addfb_ba...@basic-y-tiled-legacy.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - bat-dg2-11: NOTRUN -> [SKIP][8] ([i915#4103] / [i915#4213]) +1 other test skip [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/bat-dg2-11/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html * igt@kms_dsc@dsc-basic: - bat-dg2-11: NOTRUN -> [SKIP][9] ([i915#3555] / [i915#3840]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/bat-dg2-11/igt@kms_...@dsc-basic.html * igt@kms_force_connector_basic@force-load-detect: - bat-dg2-11: NOTRUN -> [SKIP][10] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/bat-dg2-11/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_force_connector_basic@prune-stale-modes: - bat-dg2-11: NOTRUN -> [SKIP][11] ([i915#5274]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/bat-dg2-11/igt@kms_force_connector_ba...@prune-stale-modes.html * igt@kms_pm_backlight@basic-brightness: - bat-dg2-11: NOTRUN -> [SKIP][12] ([i915#5354]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/bat-dg2-11/igt@kms_pm_backli...@basic-brightness.html * igt@kms_pm_rpm@basic-pci-d3-state: - fi-elk-e7500: NOTRUN -> [SKIP][13] +24 other tests skip [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/fi-elk-e7500/igt@kms_pm_...@basic-pci-d3-state.html * igt@kms_psr@psr-sprite-plane-onoff: - bat-dg2-11: NOTRUN -> [SKIP][14] ([i915#1072] / [i915#9732]) +3 other tests skip [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/bat-dg2-11/igt@kms_...@psr-sprite-plane-onoff.html * igt@kms_setmode@basic-clone-single-crtc: - bat-dg2-11: NOTRUN -> [SKIP][15] ([i915#3555]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/bat-dg2-11/igt@kms_setm...@basic-clone-single-crtc.html * igt@prime_vgem@basic-fence-flip: - bat-dg2-11: NOTRUN -> [SKIP][16] ([i915#3708]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/bat-dg2-11/igt@prime_v...@basic-fence-flip.html * igt@prime_vgem@basic-fence-mmap: - bat-dg2-11: NOTRUN -> [SKIP][17] ([i915#3708] / [i915#4077]) +1 other test skip [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133458v6/bat-dg2-11/igt@prime_v...@basic-fence-mmap.html * igt@prime_vgem@basic-read: - bat-dg2-11: NOTRUN -> [SKIP][18] ([i915#3291] / [i915#3708]) +2 other tests skip [18]:
✗ Fi.CI.CHECKPATCH: warning for drm/i915: skl+ plane register stuff (rev6)
== Series Details == Series: drm/i915: skl+ plane register stuff (rev6) URL : https://patchwork.freedesktop.org/series/133458/ State : warning == Summary == Error: dim checkpatch failed 6783d48ac30b drm/i915: Nuke _MMIO_PLANE_GAMC() 6d5c913cfe2c drm/i915: Extract skl_universal_plane_regs.h -:54: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #54: new file mode 100644 -:74: WARNING:LONG_LINE_COMMENT: line length of 104 exceeds 100 columns #74: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:16: +#define PLANE_CTL_ARB_SLOTS(x) REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */ -:238: WARNING:LONG_LINE: line length of 102 exceeds 100 columns #238: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:180: +#define _PLANE_CC_VAL_1(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B) + (dw) * 4) -:239: WARNING:LONG_LINE: line length of 102 exceeds 100 columns #239: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:181: +#define _PLANE_CC_VAL_2(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B) + (dw) * 4) -:240: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects? #240: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:182: +#define PLANE_CC_VAL(pipe, plane, dw) \ + _MMIO_PLANE((plane), _PLANE_CC_VAL_1((pipe), (dw)), _PLANE_CC_VAL_2((pipe), (dw))) -:240: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dw' - possible side-effects? #240: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:182: +#define PLANE_CC_VAL(pipe, plane, dw) \ + _MMIO_PLANE((plane), _PLANE_CC_VAL_1((pipe), (dw)), _PLANE_CC_VAL_2((pipe), (dw))) -:257: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects? #257: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:199: +#define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \ + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \ + _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4) -:257: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'index' - possible side-effects? #257: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:199: +#define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \ + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \ + _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4) -:273: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects? #273: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:215: +#define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \ + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \ + _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4) -:273: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'index' - possible side-effects? #273: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:215: +#define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \ + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \ + _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4) -:289: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects? #289: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:231: +#define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index)\ + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \ + _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4) -:289: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'index' - possible side-effects? #289: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:231: +#define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index)\ + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \ + _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4) -:299: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects? #299: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:241: +#define PLANE_CTL(pipe, plane) \ + _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe)) -:311: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects? #311: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:253: +#define PLANE_STRIDE(pipe, plane) \ + _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe)) -:320: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects? #320: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:262: +#define PLANE_POS(pipe, plane) \ + _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe)) -:329: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects? #329: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:271: +#define PLANE_SIZE(pipe, plane)\ + _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe)) -:338:
✗ Fi.CI.SPARSE: warning for drm/i915: skl+ plane register stuff (rev6)
== Series Details == Series: drm/i915: skl+ plane register stuff (rev6) URL : https://patchwork.freedesktop.org/series/133458/ State : warning == Summary == Error: dim sparse failed Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return' +./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
[PATCH 9/9] drm/i915: Nuke the TGL+ chroma plane tile row alignment stuff
From: Ville Syrjälä
I don't think the display hardware really has such chroma
plane tile row alignment requirements as outlined in
commit d156135e6a54 ("drm/i915/tgl: Make sure a semiplanar
UV plane is tile row size aligned")
Bspec had the same exact thing to say about earlier hardware
as well, but we never cared and things work just fine.
The one thing mentioned in that commit that is definitely
true however is the fence alignment issue. But we don't
deal with that on earlier hardware either. We do have code
to deal with that issue for the first color plane, but not
the chroma planes. So I think if we did want to check this
more extensively we should do it in the same places where
we already check the first color plane (namely
convert_plane_offset_to_xy() and intel_fb_bo_framebuffer_init()).
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fb.c| 12 +---
drivers/gpu/drm/i915/display/intel_fb.h| 1 -
drivers/gpu/drm/i915/display/skl_universal_plane.c | 11 ---
3 files changed, 1 insertion(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
b/drivers/gpu/drm/i915/display/intel_fb.c
index c80f866f3fb6..fc18da3106fd 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -584,12 +584,6 @@ static bool is_gen12_ccs_cc_plane(const struct
drm_framebuffer *fb, int color_pl
return intel_fb_rc_ccs_cc_plane(fb) == color_plane;
}
-bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane)
-{
- return intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
- color_plane == 1;
-}
-
bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane)
{
return fb->modifier == DRM_FORMAT_MOD_LINEAR ||
@@ -1019,11 +1013,7 @@ static int intel_fb_offset_to_xy(int *x, int *y,
struct drm_i915_private *i915 = to_i915(fb->dev);
unsigned int height, alignment, unused;
- if (DISPLAY_VER(i915) >= 12 &&
- !intel_fb_needs_pot_stride_remap(to_intel_framebuffer(fb)) &&
- is_semiplanar_uv_plane(fb, color_plane))
- alignment = intel_tile_row_size(fb, color_plane);
- else if (fb->modifier != DRM_FORMAT_MOD_LINEAR)
+ if (fb->modifier != DRM_FORMAT_MOD_LINEAR)
alignment = intel_tile_size(i915);
else
alignment = 0;
diff --git a/drivers/gpu/drm/i915/display/intel_fb.h
b/drivers/gpu/drm/i915/display/intel_fb.h
index 1b1fef2dc39a..6dee0c8b7f22 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.h
+++ b/drivers/gpu/drm/i915/display/intel_fb.h
@@ -34,7 +34,6 @@ bool intel_fb_is_ccs_modifier(u64 modifier);
bool intel_fb_is_rc_ccs_cc_modifier(u64 modifier);
bool intel_fb_is_mc_ccs_modifier(u64 modifier);
-bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane);
bool intel_fb_is_ccs_aux_plane(const struct drm_framebuffer *fb, int
color_plane);
int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb);
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index ca7fc9fae990..476f5b7d9497 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -514,17 +514,6 @@ static u32 tgl_plane_min_alignment(struct intel_plane
*plane,
if (intel_fb_is_ccs_aux_plane(fb, color_plane))
return mult * 4 * 1024;
- if (is_semiplanar_uv_plane(fb, color_plane)) {
- /*
-* TODO: cross-check wrt. the bspec stride in bytes * 64 bytes
-* alignment for linear UV planes on all platforms.
-*/
- if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
- return 256 * 1024;
-
- return intel_tile_row_size(fb, color_plane);
- }
-
switch (fb->modifier) {
case DRM_FORMAT_MOD_LINEAR:
case I915_FORMAT_MOD_X_TILED:
--
2.43.2
[PATCH 8/9] drm/i915: Update plane alignment requirements for TGL+
From: Ville Syrjälä
Currently we still use the SKL+ PLANE_SURF alignment even
for TGL+ even though the hardware no longer needs it.
Introduce a separate tgl_plane_min_alignment() and update
it to more accurately reflect the hardware requirements.
Signed-off-by: Ville Syrjälä
---
.../drm/i915/display/skl_universal_plane.c| 103 ++
1 file changed, 55 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 1ecd7c691317..ca7fc9fae990 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -502,75 +502,79 @@ skl_plane_max_stride(struct intel_plane *plane,
max_pixels, max_bytes);
}
-static unsigned int skl_plane_min_alignment(struct intel_plane *plane,
- const struct drm_framebuffer *fb,
- int color_plane)
+static u32 tgl_plane_min_alignment(struct intel_plane *plane,
+ const struct drm_framebuffer *fb,
+ int color_plane)
{
- struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
-
- if (intel_fb_uses_dpt(fb)) {
- /* AUX_DIST needs only 4K alignment */
- if (intel_fb_is_ccs_aux_plane(fb, color_plane))
- return 512 * 4096;
-
- /*
-* FIXME ADL sees GGTT/DMAR faults with async
-* flips unless we align to 16k at least.
-* Figure out what's going on here...
-*/
- if (IS_ALDERLAKE_P(dev_priv) &&
- !intel_fb_is_ccs_modifier(fb->modifier) &&
- HAS_ASYNC_FLIPS(dev_priv))
- return 512 * 16 * 1024;
-
- return 512 * 4096;
- }
+ struct drm_i915_private *i915 = to_i915(plane->base.dev);
+ /* PLANE_SURF GGTT -> DPT alignment */
+ int mult = intel_fb_uses_dpt(fb) ? 512 : 1;
/* AUX_DIST needs only 4K alignment */
if (intel_fb_is_ccs_aux_plane(fb, color_plane))
- return 4096;
+ return mult * 4 * 1024;
if (is_semiplanar_uv_plane(fb, color_plane)) {
/*
* TODO: cross-check wrt. the bspec stride in bytes * 64 bytes
* alignment for linear UV planes on all platforms.
*/
- if (DISPLAY_VER(dev_priv) >= 12) {
- if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
- return 256 * 1024;
-
- return intel_tile_row_size(fb, color_plane);
- }
-
- return 4096;
- }
-
- drm_WARN_ON(_priv->drm, color_plane != 0);
-
- switch (fb->modifier) {
- case DRM_FORMAT_MOD_LINEAR:
- return 256 * 1024;
- case I915_FORMAT_MOD_X_TILED:
- if (HAS_ASYNC_FLIPS(dev_priv))
+ if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
return 256 * 1024;
- return 0;
+
+ return intel_tile_row_size(fb, color_plane);
+ }
+
+ switch (fb->modifier) {
+ case DRM_FORMAT_MOD_LINEAR:
+ case I915_FORMAT_MOD_X_TILED:
+ case I915_FORMAT_MOD_Y_TILED:
+ case I915_FORMAT_MOD_4_TILED:
+ /*
+* FIXME ADL sees GGTT/DMAR faults with async
+* flips unless we align to 16k at least.
+* Figure out what's going on here...
+*/
+ if (IS_ALDERLAKE_P(i915) && HAS_ASYNC_FLIPS(i915))
+ return mult * 16 * 1024;
+ return mult * 4 * 1024;
case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
+ case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
+ case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
+ case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS:
case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS:
case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC:
- return 16 * 1024;
+ /* 4x1 main surface tiles (16K) match 64B of AUX */
+ return max(mult * 4 * 1024, 16 * 1024);
+ default:
+ MISSING_CASE(fb->modifier);
+ return 0;
+ }
+}
+
+static u32 skl_plane_min_alignment(struct intel_plane *plane,
+ const struct drm_framebuffer *fb,
+ int color_plane)
+{
+ /*
+* AUX_DIST needs only 4K alignment,
+* as does ICL UV PLANE_SURF.
+*/
+ if (color_plane != 0)
+ return 4 * 1024;
+
+ switch (fb->modifier) {
+ case DRM_FORMAT_MOD_LINEAR:
+ case
[PATCH 7/9] drm/i915: Move intel_surf_alignment() into skl_univerals_plane.c
From: Ville Syrjälä
Now that all pre-skl platforms have their own .min_alignment()
functions the remainder of intel_surf_alignment() can be hoisted
into skl_univerals_plane.c (and renamed appropriately).
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_fb.c | 77 +--
drivers/gpu/drm/i915/display/intel_fb.h | 4 +-
.../drm/i915/display/skl_universal_plane.c| 77 ++-
3 files changed, 78 insertions(+), 80 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
b/drivers/gpu/drm/i915/display/intel_fb.c
index eea93d84a16e..c80f866f3fb6 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -584,7 +584,7 @@ static bool is_gen12_ccs_cc_plane(const struct
drm_framebuffer *fb, int color_pl
return intel_fb_rc_ccs_cc_plane(fb) == color_plane;
}
-static bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int
color_plane)
+bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane)
{
return intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
color_plane == 1;
@@ -776,81 +776,6 @@ bool intel_fb_uses_dpt(const struct drm_framebuffer *fb)
intel_fb_modifier_uses_dpt(to_i915(fb->dev), fb->modifier);
}
-unsigned int intel_surf_alignment(struct intel_plane *plane,
- const struct drm_framebuffer *fb,
- int color_plane)
-{
- struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
-
- if (intel_fb_uses_dpt(fb)) {
- /* AUX_DIST needs only 4K alignment */
- if (intel_fb_is_ccs_aux_plane(fb, color_plane))
- return 512 * 4096;
-
- /*
-* FIXME ADL sees GGTT/DMAR faults with async
-* flips unless we align to 16k at least.
-* Figure out what's going on here...
-*/
- if (IS_ALDERLAKE_P(dev_priv) &&
- !intel_fb_is_ccs_modifier(fb->modifier) &&
- HAS_ASYNC_FLIPS(dev_priv))
- return 512 * 16 * 1024;
-
- return 512 * 4096;
- }
-
- /* AUX_DIST needs only 4K alignment */
- if (intel_fb_is_ccs_aux_plane(fb, color_plane))
- return 4096;
-
- if (is_semiplanar_uv_plane(fb, color_plane)) {
- /*
-* TODO: cross-check wrt. the bspec stride in bytes * 64 bytes
-* alignment for linear UV planes on all platforms.
-*/
- if (DISPLAY_VER(dev_priv) >= 12) {
- if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
- return 256 * 1024;
-
- return intel_tile_row_size(fb, color_plane);
- }
-
- return 4096;
- }
-
- drm_WARN_ON(_priv->drm, color_plane != 0);
-
- switch (fb->modifier) {
- case DRM_FORMAT_MOD_LINEAR:
- return 256 * 1024;
- case I915_FORMAT_MOD_X_TILED:
- if (HAS_ASYNC_FLIPS(dev_priv))
- return 256 * 1024;
- return 0;
- case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
- case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
- case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
- case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS:
- case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS:
- case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC:
- return 16 * 1024;
- case I915_FORMAT_MOD_Y_TILED_CCS:
- case I915_FORMAT_MOD_Yf_TILED_CCS:
- case I915_FORMAT_MOD_Y_TILED:
- case I915_FORMAT_MOD_4_TILED:
- case I915_FORMAT_MOD_Yf_TILED:
- return 1 * 1024 * 1024;
- case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
- case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
- case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
- return 16 * 1024;
- default:
- MISSING_CASE(fb->modifier);
- return 0;
- }
-}
-
void intel_fb_plane_get_subsampling(int *hsub, int *vsub,
const struct drm_framebuffer *fb,
int color_plane)
diff --git a/drivers/gpu/drm/i915/display/intel_fb.h
b/drivers/gpu/drm/i915/display/intel_fb.h
index 16ebb573643f..1b1fef2dc39a 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.h
+++ b/drivers/gpu/drm/i915/display/intel_fb.h
@@ -34,6 +34,7 @@ bool intel_fb_is_ccs_modifier(u64 modifier);
bool intel_fb_is_rc_ccs_cc_modifier(u64 modifier);
bool intel_fb_is_mc_ccs_modifier(u64 modifier);
+bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane);
bool intel_fb_is_ccs_aux_plane(const struct drm_framebuffer *fb, int
color_plane);
int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb);
@@ -60,9 +61,6 @@ unsigned int intel_tile_height(const struct drm_framebuffer
[PATCH 6/9] drm/i915: Split pre-skl platforms out from intel_surf_alignment()
From: Ville Syrjälä
Extract the necessary chunks from intel_surf_alignment()
into per-platform variants for all pre-skl primary/sprite
planes.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 69 -
drivers/gpu/drm/i915/display/intel_fb.c | 17 +
drivers/gpu/drm/i915/display/intel_sprite.c | 28 -
3 files changed, 96 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 85dbf5b950e2..0d64176c1e6f 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -762,6 +762,66 @@ i8xx_plane_max_stride(struct intel_plane *plane,
return 8 * 1024;
}
+static unsigned int vlv_primary_min_alignment(struct intel_plane *plane,
+ const struct drm_framebuffer *fb,
+ int color_plane)
+{
+ struct drm_i915_private *i915 = to_i915(plane->base.dev);
+
+ switch (fb->modifier) {
+ case I915_FORMAT_MOD_X_TILED:
+ if (HAS_ASYNC_FLIPS(i915))
+ return 256 * 1024;
+ return 4 * 1024;
+ case DRM_FORMAT_MOD_LINEAR:
+ return 128 * 1024;
+ default:
+ MISSING_CASE(fb->modifier);
+ return 0;
+ }
+}
+
+static unsigned int g4x_primary_min_alignment(struct intel_plane *plane,
+ const struct drm_framebuffer *fb,
+ int color_plane)
+{
+ struct drm_i915_private *i915 = to_i915(plane->base.dev);
+
+ switch (fb->modifier) {
+ case I915_FORMAT_MOD_X_TILED:
+ if (HAS_ASYNC_FLIPS(i915))
+ return 256 * 1024;
+ return 4 * 1024;
+ case DRM_FORMAT_MOD_LINEAR:
+ return 4 * 1024;
+ default:
+ MISSING_CASE(fb->modifier);
+ return 0;
+ }
+}
+
+static unsigned int i965_plane_min_alignment(struct intel_plane *plane,
+const struct drm_framebuffer *fb,
+int color_plane)
+{
+ switch (fb->modifier) {
+ case I915_FORMAT_MOD_X_TILED:
+ return 4 * 1024;
+ case DRM_FORMAT_MOD_LINEAR:
+ return 128 * 1024;
+ default:
+ MISSING_CASE(fb->modifier);
+ return 0;
+ }
+}
+
+static unsigned int i9xx_plane_min_alignment(struct intel_plane *plane,
+const struct drm_framebuffer *fb,
+int color_plane)
+{
+ return 0;
+}
+
static const struct drm_plane_funcs i965_plane_funcs = {
.update_plane = drm_atomic_helper_update_plane,
.disable_plane = drm_atomic_helper_disable_plane,
@@ -867,7 +927,14 @@ intel_primary_plane_create(struct drm_i915_private
*dev_priv, enum pipe pipe)
plane->max_stride = ilk_primary_max_stride;
}
- plane->min_alignment = intel_surf_alignment;
+ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
+ plane->min_alignment = vlv_primary_min_alignment;
+ else if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))
+ plane->min_alignment = g4x_primary_min_alignment;
+ else if (DISPLAY_VER(dev_priv) == 4)
+ plane->min_alignment = i965_plane_min_alignment;
+ else
+ plane->min_alignment = i9xx_plane_min_alignment;
if (IS_I830(dev_priv) || IS_I845G(dev_priv)) {
plane->update_arm = i830_plane_update_arm;
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
b/drivers/gpu/drm/i915/display/intel_fb.c
index c84ecae3a57c..eea93d84a16e 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -776,19 +776,6 @@ bool intel_fb_uses_dpt(const struct drm_framebuffer *fb)
intel_fb_modifier_uses_dpt(to_i915(fb->dev), fb->modifier);
}
-static unsigned int intel_linear_alignment(const struct drm_i915_private
*dev_priv)
-{
- if (DISPLAY_VER(dev_priv) >= 9)
- return 256 * 1024;
- else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
-IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- return 128 * 1024;
- else if (DISPLAY_VER(dev_priv) >= 4)
- return 4 * 1024;
- else
- return 0;
-}
-
unsigned int intel_surf_alignment(struct intel_plane *plane,
const struct drm_framebuffer *fb,
int color_plane)
@@ -824,7 +811,7 @@ unsigned int intel_surf_alignment(struct intel_plane *plane,
*/
if (DISPLAY_VER(dev_priv) >= 12) {
if (fb->modifier ==
[PATCH 5/9] drm/i915: Split cursor alignment to per-platform vfuncs
From: Ville Syrjälä
Split intel_cursor_alignment() into per-platform variants.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cursor.c | 40 +++--
drivers/gpu/drm/i915/display/intel_fb.c | 16 -
drivers/gpu/drm/i915/display/intel_fb.h | 3 --
3 files changed, 38 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c
b/drivers/gpu/drm/i915/display/intel_cursor.c
index 026975f569a7..737d53c50901 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -193,6 +193,13 @@ i845_cursor_max_stride(struct intel_plane *plane,
return 2048;
}
+static unsigned int i845_cursor_min_alignment(struct intel_plane *plane,
+ const struct drm_framebuffer *fb,
+ int color_plane)
+{
+ return 32;
+}
+
static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
{
u32 cntl = 0;
@@ -343,6 +350,28 @@ i9xx_cursor_max_stride(struct intel_plane *plane,
return plane->base.dev->mode_config.cursor_width * 4;
}
+static unsigned int i830_cursor_min_alignment(struct intel_plane *plane,
+ const struct drm_framebuffer *fb,
+ int color_plane)
+{
+ /* "AlmadorM Errata – Requires 32-bpp cursor data to be 16KB aligned."
*/
+ return 16 * 1024; /* physical */
+}
+
+static unsigned int i85x_cursor_min_alignment(struct intel_plane *plane,
+ const struct drm_framebuffer *fb,
+ int color_plane)
+{
+ return 256; /* physical */
+}
+
+static unsigned int i9xx_cursor_min_alignment(struct intel_plane *plane,
+ const struct drm_framebuffer *fb,
+ int color_plane)
+{
+ return 4 * 1024; /* physical for i915/i945 */
+}
+
static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -884,20 +913,27 @@ intel_cursor_plane_create(struct drm_i915_private
*dev_priv,
if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
cursor->max_stride = i845_cursor_max_stride;
+ cursor->min_alignment = i845_cursor_min_alignment;
cursor->update_arm = i845_cursor_update_arm;
cursor->disable_arm = i845_cursor_disable_arm;
cursor->get_hw_state = i845_cursor_get_hw_state;
cursor->check_plane = i845_check_cursor;
} else {
cursor->max_stride = i9xx_cursor_max_stride;
+
+ if (IS_I830(dev_priv))
+ cursor->min_alignment = i830_cursor_min_alignment;
+ else if (IS_I85X(dev_priv))
+ cursor->min_alignment = i85x_cursor_min_alignment;
+ else
+ cursor->min_alignment = i9xx_cursor_min_alignment;
+
cursor->update_arm = i9xx_cursor_update_arm;
cursor->disable_arm = i9xx_cursor_disable_arm;
cursor->get_hw_state = i9xx_cursor_get_hw_state;
cursor->check_plane = i9xx_check_cursor;
}
- cursor->min_alignment = intel_cursor_alignment;
-
cursor->cursor.base = ~0;
cursor->cursor.cntl = ~0;
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
b/drivers/gpu/drm/i915/display/intel_fb.c
index c5bae05cbbc3..c84ecae3a57c 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -776,22 +776,6 @@ bool intel_fb_uses_dpt(const struct drm_framebuffer *fb)
intel_fb_modifier_uses_dpt(to_i915(fb->dev), fb->modifier);
}
-unsigned int intel_cursor_alignment(struct intel_plane *plane,
- const struct drm_framebuffer *fb,
- int color_plane)
-{
- struct drm_i915_private *i915 = to_i915(plane->base.dev);
-
- if (IS_I830(i915))
- return 16 * 1024;
- else if (IS_I85X(i915))
- return 256;
- else if (IS_I845G(i915) || IS_I865G(i915))
- return 32;
- else
- return 4 * 1024;
-}
-
static unsigned int intel_linear_alignment(const struct drm_i915_private
*dev_priv)
{
if (DISPLAY_VER(dev_priv) >= 9)
diff --git a/drivers/gpu/drm/i915/display/intel_fb.h
b/drivers/gpu/drm/i915/display/intel_fb.h
index 86c01a3ce81e..16ebb573643f 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.h
+++ b/drivers/gpu/drm/i915/display/intel_fb.h
@@ -60,9 +60,6 @@ unsigned int intel_tile_height(const struct drm_framebuffer
*fb, int color_plane
unsigned int intel_tile_row_size(const struct drm_framebuffer *fb, int
color_plane);
unsigned int
[PATCH 4/9] drm/i915: Introduce fb->min_alignment
From: Ville Syrjälä
Different planes could have different alignment requirements
even for the same format/modifier. Collect the alignment
requirements across all planes capable of scanning out the
fb such that the alignment used when pinning the normal ggtt
view is satisfactory to all those planes.
When pinning per-plane views we only have to satisfy the
alignment requirements of the specific plane.
Signed-off-by: Ville Syrjälä
---
.../drm/i915/display/intel_display_types.h| 2 ++
drivers/gpu/drm/i915/display/intel_fb.c | 23
drivers/gpu/drm/i915/display/intel_fb_pin.c | 27 +--
drivers/gpu/drm/i915/display/intel_fbdev.c| 18 +
4 files changed, 51 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 40d6e5f4c350..58bb65832adf 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -145,6 +145,8 @@ struct intel_framebuffer {
};
struct i915_address_space *dpt_vm;
+
+ unsigned int min_alignment;
};
enum intel_hotplug_state {
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
b/drivers/gpu/drm/i915/display/intel_fb.c
index 3f3a9cd534f4..c5bae05cbbc3 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -10,6 +10,7 @@
#include
#include "i915_drv.h"
+#include "intel_atomic_plane.h"
#include "intel_display.h"
#include "intel_display_types.h"
#include "intel_dpt.h"
@@ -1616,6 +1617,26 @@ bool intel_fb_supports_90_270_rotation(const struct
intel_framebuffer *fb)
fb->base.modifier == I915_FORMAT_MOD_Yf_TILED;
}
+static unsigned int intel_fb_min_alignment(const struct drm_framebuffer *fb)
+{
+ struct drm_i915_private *i915 = to_i915(fb->dev);
+ struct intel_plane *plane;
+ unsigned int min_alignment = 0;
+
+ for_each_intel_plane(>drm, plane) {
+ if (!drm_plane_has_format(>base, fb->format->format,
fb->modifier))
+ continue;
+
+ if (intel_plane_needs_physical(plane))
+ continue;
+
+ min_alignment = max(min_alignment,
+ plane->min_alignment(plane, fb, 0));
+ }
+
+ return min_alignment;
+}
+
int intel_fill_fb_info(struct drm_i915_private *i915, struct intel_framebuffer
*fb)
{
struct drm_i915_gem_object *obj = intel_fb_obj(>base);
@@ -1698,6 +1719,8 @@ int intel_fill_fb_info(struct drm_i915_private *i915,
struct intel_framebuffer *
return -EINVAL;
}
+ fb->min_alignment = intel_fb_min_alignment(>base);
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c
b/drivers/gpu/drm/i915/display/intel_fb_pin.c
index 9b0f1ea41b70..1ae02de906f5 100644
--- a/drivers/gpu/drm/i915/display/intel_fb_pin.c
+++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c
@@ -230,13 +230,36 @@ void intel_fb_unpin_vma(struct i915_vma *vma, unsigned
long flags)
i915_vma_put(vma);
}
+static bool gtt_view_is_per_plane(const struct intel_plane_state *plane_state)
+{
+ const struct intel_framebuffer *fb =
to_intel_framebuffer(plane_state->hw.fb);
+
+ if (plane_state->view.gtt.type == I915_GTT_VIEW_REMAPPED &&
+ intel_fb_needs_pot_stride_remap(fb))
+ return false;
+
+ return plane_state->view.gtt.type != I915_GTT_VIEW_NORMAL;
+}
+
static unsigned int
intel_plane_fb_min_alignment(const struct intel_plane_state *plane_state)
{
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
- const struct drm_framebuffer *fb = plane_state->hw.fb;
+ const struct intel_framebuffer *fb =
to_intel_framebuffer(plane_state->hw.fb);
- return plane->min_alignment(plane, fb, 0);
+ /*
+* Only use plane specific alignment for binding
+* a per-plane gtt view (remapped or rotated),
+* otherwise make sure the alignment is suitable
+* for all planes.
+*/
+ if (!gtt_view_is_per_plane(plane_state))
+ return fb->min_alignment;
+
+ if (intel_plane_needs_physical(plane))
+ return 0;
+
+ return plane->min_alignment(plane, >base, 0);
}
static unsigned int
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c
b/drivers/gpu/drm/i915/display/intel_fbdev.c
index ff685aebbd1a..124aac172acb 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -46,7 +46,6 @@
#include "gem/i915_gem_mman.h"
#include "i915_drv.h"
-#include "intel_crtc.h"
#include "intel_display_types.h"
#include "intel_fb.h"
#include "intel_fb_pin.h"
@@ -172,21 +171,6 @@ static const struct fb_ops intelfb_ops = {
__diag_pop();
-static unsigned int intel_fbdev_min_alignment(const struct drm_framebuffer *fb)
-{
-
[PATCH 3/9] drm/i915: Introduce plane->min_alignment() vfunc
From: Ville Syrjälä
Different hardware generations have different scanout alignment
requirements. Introduce a new vfunc that will allow us to
make that distinction without horrible if-ladders.
For now we directly plug in the existing intel_surf_alignment()
and intel_cursor_alignment() functions.
For fbdev we (temporarily) introduce intel_fbdev_min_alignment()
that simply queries the alignment from the primary plane of
the first crtc.
TODO: someone will need to fix xe's alignment handling
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 8 ++--
drivers/gpu/drm/i915/display/intel_cursor.c | 2 +
.../drm/i915/display/intel_display_types.h| 3 ++
drivers/gpu/drm/i915/display/intel_fb.c | 22 +-
drivers/gpu/drm/i915/display/intel_fb.h | 7 +++-
drivers/gpu/drm/i915/display/intel_fb_pin.c | 40 ++-
drivers/gpu/drm/i915/display/intel_fb_pin.h | 3 +-
drivers/gpu/drm/i915/display/intel_fbdev.c| 21 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 2 +
.../drm/i915/display/skl_universal_plane.c| 11 +++--
drivers/gpu/drm/xe/display/xe_fb_pin.c| 3 +-
drivers/gpu/drm/xe/display/xe_plane_initial.c | 4 +-
12 files changed, 89 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
b/drivers/gpu/drm/i915/display/i9xx_plane.c
index ea4d8ba55ad8..85dbf5b950e2 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -224,8 +224,8 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state
*crtc_state,
int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
{
- struct drm_i915_private *dev_priv =
- to_i915(plane_state->uapi.plane->dev);
+ struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
+ struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
const struct drm_framebuffer *fb = plane_state->hw.fb;
int src_x, src_y, src_w;
u32 offset;
@@ -266,7 +266,7 @@ int i9xx_check_plane_surface(struct intel_plane_state
*plane_state)
* despite them not using the linear offset anymore.
*/
if (DISPLAY_VER(dev_priv) >= 4 && fb->modifier ==
I915_FORMAT_MOD_X_TILED) {
- unsigned int alignment = intel_surf_alignment(fb, 0);
+ unsigned int alignment = plane->min_alignment(plane, fb, 0);
int cpp = fb->format->cpp[0];
while ((src_x + src_w) * cpp >
plane_state->view.color_plane[0].mapping_stride) {
@@ -867,6 +867,8 @@ intel_primary_plane_create(struct drm_i915_private
*dev_priv, enum pipe pipe)
plane->max_stride = ilk_primary_max_stride;
}
+ plane->min_alignment = intel_surf_alignment;
+
if (IS_I830(dev_priv) || IS_I845G(dev_priv)) {
plane->update_arm = i830_plane_update_arm;
} else {
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c
b/drivers/gpu/drm/i915/display/intel_cursor.c
index 2118b87ccb10..026975f569a7 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -896,6 +896,8 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
cursor->check_plane = i9xx_check_cursor;
}
+ cursor->min_alignment = intel_cursor_alignment;
+
cursor->cursor.base = ~0;
cursor->cursor.cntl = ~0;
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index fec3de25ea54..40d6e5f4c350 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1550,6 +1550,9 @@ struct intel_plane {
int (*max_height)(const struct drm_framebuffer *fb,
int color_plane,
unsigned int rotation);
+ unsigned int (*min_alignment)(struct intel_plane *plane,
+ const struct drm_framebuffer *fb,
+ int color_plane);
unsigned int (*max_stride)(struct intel_plane *plane,
u32 pixel_format, u64 modifier,
unsigned int rotation);
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
b/drivers/gpu/drm/i915/display/intel_fb.c
index b6638726949d..3f3a9cd534f4 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -775,8 +775,12 @@ bool intel_fb_uses_dpt(const struct drm_framebuffer *fb)
intel_fb_modifier_uses_dpt(to_i915(fb->dev), fb->modifier);
}
-unsigned int intel_cursor_alignment(const struct drm_i915_private *i915)
+unsigned int intel_cursor_alignment(struct intel_plane *plane,
+ const struct drm_framebuffer *fb,
+ int color_plane)
{
+ struct
[PATCH 1/9] drm: Rename drm_plane_check_pixel_format() to drm_plane_has_format()
From: Ville Syrjälä
Rename drm_plane_check_pixel_format() to drm_plane_has_format()
and change the return type accordingly. Allows one to write
more natural code.
Also matches drm_any_plane_has_format() better.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_atomic.c| 7 ++-
drivers/gpu/drm/drm_crtc.c | 6 ++
drivers/gpu/drm/drm_crtc_internal.h | 4 ++--
drivers/gpu/drm/drm_plane.c | 22 ++
4 files changed, 16 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index a91737adf8e7..e22560213b8e 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -608,7 +608,6 @@ static int drm_atomic_plane_check(const struct
drm_plane_state *old_plane_state,
unsigned int fb_width, fb_height;
struct drm_mode_rect *clips;
uint32_t num_clips;
- int ret;
/* either *both* CRTC and FB must be set, or neither */
if (crtc && !fb) {
@@ -635,14 +634,12 @@ static int drm_atomic_plane_check(const struct
drm_plane_state *old_plane_state,
}
/* Check whether this plane supports the fb pixel format. */
- ret = drm_plane_check_pixel_format(plane, fb->format->format,
- fb->modifier);
- if (ret) {
+ if (!drm_plane_has_format(plane, fb->format->format, fb->modifier)) {
drm_dbg_atomic(plane->dev,
"[PLANE:%d:%s] invalid pixel format %p4cc,
modifier 0x%llx\n",
plane->base.id, plane->name,
>format->format, fb->modifier);
- return ret;
+ return -EINVAL;
}
/* Give drivers some help against integer overflows */
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 483969b84a30..3488ff067c69 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -789,12 +789,10 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data,
* case.
*/
if (!plane->format_default) {
- ret = drm_plane_check_pixel_format(plane,
- fb->format->format,
- fb->modifier);
- if (ret) {
+ if (!drm_plane_has_format(plane, fb->format->format,
fb->modifier)) {
drm_dbg_kms(dev, "Invalid pixel format %p4cc,
modifier 0x%llx\n",
>format->format, fb->modifier);
+ ret = -EINVAL;
goto out;
}
}
diff --git a/drivers/gpu/drm/drm_crtc_internal.h
b/drivers/gpu/drm/drm_crtc_internal.h
index 25aaae937ceb..898e0e8b51be 100644
--- a/drivers/gpu/drm/drm_crtc_internal.h
+++ b/drivers/gpu/drm/drm_crtc_internal.h
@@ -272,8 +272,8 @@ int drm_mode_atomic_ioctl(struct drm_device *dev,
/* drm_plane.c */
int drm_plane_register_all(struct drm_device *dev);
void drm_plane_unregister_all(struct drm_device *dev);
-int drm_plane_check_pixel_format(struct drm_plane *plane,
-u32 format, u64 modifier);
+bool drm_plane_has_format(struct drm_plane *plane,
+ u32 format, u64 modifier);
struct drm_mode_rect *
__drm_plane_get_damage_clips(const struct drm_plane_state *state);
diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c
index 57662a1fd345..268aa2299df5 100644
--- a/drivers/gpu/drm/drm_plane.c
+++ b/drivers/gpu/drm/drm_plane.c
@@ -877,8 +877,8 @@ int drm_mode_getplane(struct drm_device *dev, void *data,
return 0;
}
-int drm_plane_check_pixel_format(struct drm_plane *plane,
-u32 format, u64 modifier)
+bool drm_plane_has_format(struct drm_plane *plane,
+ u32 format, u64 modifier)
{
unsigned int i;
@@ -887,24 +887,24 @@ int drm_plane_check_pixel_format(struct drm_plane *plane,
break;
}
if (i == plane->format_count)
- return -EINVAL;
+ return false;
if (plane->funcs->format_mod_supported) {
if (!plane->funcs->format_mod_supported(plane, format,
modifier))
- return -EINVAL;
+ return false;
} else {
if (!plane->modifier_count)
- return 0;
+ return true;
for (i = 0; i < plane->modifier_count; i++) {
if (modifier == plane->modifiers[i])
break;
}
if (i == plane->modifier_count)
- return -EINVAL;
+ return false;
}
- return 0;
+
[PATCH 2/9] drm: Export drm_plane_has_format()
From: Ville Syrjälä Export drm_plane_has_format() so that drivers can use it. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/drm_crtc_internal.h | 2 -- drivers/gpu/drm/drm_plane.c | 1 + include/drm/drm_plane.h | 2 ++ 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_crtc_internal.h b/drivers/gpu/drm/drm_crtc_internal.h index 898e0e8b51be..e207759ca045 100644 --- a/drivers/gpu/drm/drm_crtc_internal.h +++ b/drivers/gpu/drm/drm_crtc_internal.h @@ -272,8 +272,6 @@ int drm_mode_atomic_ioctl(struct drm_device *dev, /* drm_plane.c */ int drm_plane_register_all(struct drm_device *dev); void drm_plane_unregister_all(struct drm_device *dev); -bool drm_plane_has_format(struct drm_plane *plane, - u32 format, u64 modifier); struct drm_mode_rect * __drm_plane_get_damage_clips(const struct drm_plane_state *state); diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c index 268aa2299df5..a51d4dd3f7de 100644 --- a/drivers/gpu/drm/drm_plane.c +++ b/drivers/gpu/drm/drm_plane.c @@ -906,6 +906,7 @@ bool drm_plane_has_format(struct drm_plane *plane, return true; } +EXPORT_SYMBOL(drm_plane_has_format); static int __setplane_check(struct drm_plane *plane, struct drm_crtc *crtc, diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h index 9507542121fa..dd718c62ac31 100644 --- a/include/drm/drm_plane.h +++ b/include/drm/drm_plane.h @@ -972,6 +972,8 @@ static inline struct drm_plane *drm_plane_find(struct drm_device *dev, #define drm_for_each_plane(plane, dev) \ list_for_each_entry(plane, &(dev)->mode_config.plane_list, head) +bool drm_plane_has_format(struct drm_plane *plane, + u32 format, u64 modifier); bool drm_any_plane_has_format(struct drm_device *dev, u32 format, u64 modifier); -- 2.43.2
[PATCH 0/9] drm/i915: Polish plane surface alignment handling
From: Ville Syrjälä intel_surf_alignment() in particular has devolved into a complete mess. Redesign the code so that we can handle alignment restrictions in a nicer. Also adjust alignment for TGL+ to actually match the hardware requirements. Ville Syrjälä (9): drm: Rename drm_plane_check_pixel_format() to drm_plane_has_format() drm: Export drm_plane_has_format() drm/i915: Introduce plane->min_alignment() vfunc drm/i915: Introduce fb->min_alignment drm/i915: Split cursor alignment to per-platform vfuncs drm/i915: Split pre-skl platforms out from intel_surf_alignment() drm/i915: Move intel_surf_alignment() into skl_univerals_plane.c drm/i915: Update plane alignment requirements for TGL+ drm/i915: Nuke the TGL+ chroma plane tile row alignment stuff drivers/gpu/drm/drm_atomic.c | 7 +- drivers/gpu/drm/drm_crtc.c| 6 +- drivers/gpu/drm/drm_crtc_internal.h | 2 - drivers/gpu/drm/drm_plane.c | 23 ++- drivers/gpu/drm/i915/display/i9xx_plane.c | 75 - drivers/gpu/drm/i915/display/intel_cursor.c | 38 + .../drm/i915/display/intel_display_types.h| 5 + drivers/gpu/drm/i915/display/intel_fb.c | 145 -- drivers/gpu/drm/i915/display/intel_fb.h | 3 - drivers/gpu/drm/i915/display/intel_fb_pin.c | 63 ++-- drivers/gpu/drm/i915/display/intel_fb_pin.h | 3 +- drivers/gpu/drm/i915/display/intel_fbdev.c| 5 +- drivers/gpu/drm/i915/display/intel_sprite.c | 26 .../drm/i915/display/skl_universal_plane.c| 82 +- drivers/gpu/drm/xe/display/xe_fb_pin.c| 3 +- drivers/gpu/drm/xe/display/xe_plane_initial.c | 4 +- include/drm/drm_plane.h | 2 + 17 files changed, 324 insertions(+), 168 deletions(-) -- 2.43.2
Re: [RESEND 4/6] drm/amdgpu: remove amdgpu_connector_edid() and stop using edid_blob_ptr
On Fri, May 10, 2024 at 5:09 PM Jani Nikula wrote:
>
> amdgpu_connector_edid() copies the EDID from edid_blob_ptr as a side
> effect if amdgpu_connector->edid isn't initialized. However, everywhere
> that the returned EDID is used, the EDID should have been set
> beforehands.
>
> Only the drm EDID code should look at the EDID property, anyway, so stop
> using it.
>
> Cc: Alex Deucher
> Cc: Christian König
> Cc: Pan, Xinhui
> Cc: amd-...@lists.freedesktop.org
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c | 16
> drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.h | 1 -
> drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 4 ++--
> 6 files changed, 8 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
> index 9caba10315a8..cae7479c3ecf 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
> @@ -246,22 +246,6 @@ amdgpu_connector_find_encoder(struct drm_connector
> *connector,
> return NULL;
> }
>
> -struct edid *amdgpu_connector_edid(struct drm_connector *connector)
> -{
> - struct amdgpu_connector *amdgpu_connector =
> to_amdgpu_connector(connector);
> - struct drm_property_blob *edid_blob = connector->edid_blob_ptr;
> -
> - if (amdgpu_connector->edid) {
> - return amdgpu_connector->edid;
> - } else if (edid_blob) {
> - struct edid *edid = kmemdup(edid_blob->data,
> edid_blob->length, GFP_KERNEL);
> -
> - if (edid)
> - amdgpu_connector->edid = edid;
> - }
> - return amdgpu_connector->edid;
> -}
> -
> static struct edid *
> amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev)
> {
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.h
> index 61fcef15ad72..eff833b6ed31 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.h
> @@ -24,7 +24,6 @@
> #ifndef __AMDGPU_CONNECTORS_H__
> #define __AMDGPU_CONNECTORS_H__
>
> -struct edid *amdgpu_connector_edid(struct drm_connector *connector);
> void amdgpu_connector_hotplug(struct drm_connector *connector);
> int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector);
> u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector
> *connector);
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> index b44fce44c066..dddb5fe16f2c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> @@ -1299,7 +1299,7 @@ static void
> dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder
> return;
> }
>
> - sad_count =
> drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), );
> + sad_count = drm_edid_to_speaker_allocation(amdgpu_connector->edid,
> );
> if (sad_count < 0) {
> DRM_ERROR("Couldn't read Speaker Allocation Data Block:
> %d\n", sad_count);
> sad_count = 0;
> @@ -1369,7 +1369,7 @@ static void dce_v10_0_audio_write_sad_regs(struct
> drm_encoder *encoder)
> return;
> }
>
> - sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), );
> + sad_count = drm_edid_to_sad(amdgpu_connector->edid, );
> if (sad_count < 0)
> DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
> if (sad_count <= 0)
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> index 80b2e7f79acf..11780e4d7e9f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> @@ -1331,7 +1331,7 @@ static void
> dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder
> return;
> }
>
> - sad_count =
> drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), );
> + sad_count = drm_edid_to_speaker_allocation(amdgpu_connector->edid,
> );
> if (sad_count < 0) {
> DRM_ERROR("Couldn't read Speaker Allocation Data Block:
> %d\n", sad_count);
> sad_count = 0;
> @@ -1401,7 +1401,7 @@ static void dce_v11_0_audio_write_sad_regs(struct
> drm_encoder *encoder)
> return;
> }
>
> - sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), );
> + sad_count = drm_edid_to_sad(amdgpu_connector->edid, );
> if (sad_count < 0)
> DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
> if (sad_count <= 0)
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
>
[PATCH v2 13/16] drm/i915: Refactor skl+ plane register offset calculations
From: Ville Syrjälä Currentluy every skl+ plane register defines some intermediate macros to calculate the final register offset. Pull all of that into common macros, simplifying the final register offset stuff into just five defines: - raw register offsets for the planes 1 and 2 on pipes A and B - the final parametrized macro v2: Rebase Signed-off-by: Ville Syrjälä --- .../i915/display/skl_universal_plane_regs.h | 185 +- 1 file changed, 93 insertions(+), 92 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h index 0b4f97059479..cb3bdd71b6b2 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h @@ -8,13 +8,22 @@ #include "intel_display_reg_defs.h" +#define _SKL_PLANE(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \ + _PLANE((plane), _PIPE((pipe), (reg_1_a), (reg_1_b)), _PIPE((pipe), (reg_2_a), (reg_2_b))) +#define _SKL_PLANE_DW(pipe, plane, dw, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \ + (_SKL_PLANE((pipe), (plane), (reg_1_a), (reg_1_b), (reg_2_a), (reg_2_b)) + (dw) * 4) +#define _MMIO_SKL_PLANE(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \ + _MMIO(_SKL_PLANE((pipe), (plane), (reg_1_a), (reg_1_b), (reg_2_a), (reg_2_b))) +#define _MMIO_SKL_PLANE_DW(pipe, plane, dw, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \ + _MMIO(_SKL_PLANE_DW((pipe), (plane), (dw), (reg_1_a), (reg_1_b), (reg_2_a), (reg_2_b))) + #define _PLANE_CTL_1_A 0x70180 #define _PLANE_CTL_2_A 0x70280 #define _PLANE_CTL_1_B 0x71180 #define _PLANE_CTL_2_B 0x71280 -#define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B) -#define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B) -#define PLANE_CTL(pipe, plane) _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe)) +#define PLANE_CTL(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ + _PLANE_CTL_1_A, _PLANE_CTL_1_B, \ + _PLANE_CTL_2_A, _PLANE_CTL_2_B) #define PLANE_CTL_ENABLE REG_BIT(31) #define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */ #define PLANE_CTL_ARB_SLOTS(x) REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */ @@ -83,9 +92,9 @@ #define _PLANE_STRIDE_2_A 0x70288 #define _PLANE_STRIDE_1_B 0x71188 #define _PLANE_STRIDE_2_B 0x71288 -#define _PLANE_STRIDE_1(pipe) _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B) -#define _PLANE_STRIDE_2(pipe) _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B) -#define PLANE_STRIDE(pipe, plane) _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe)) +#define PLANE_STRIDE(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ + _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B, \ + _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B) #define PLANE_STRIDE__MASK REG_GENMASK(11, 0) #define PLANE_STRIDE_(stride) REG_FIELD_PREP(PLANE_STRIDE__MASK, (stride)) @@ -93,9 +102,9 @@ #define _PLANE_POS_2_A 0x7028c #define _PLANE_POS_1_B 0x7118c #define _PLANE_POS_2_B 0x7128c -#define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B) -#define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B) -#define PLANE_POS(pipe, plane) _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe)) +#define PLANE_POS(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ + _PLANE_POS_1_A, _PLANE_POS_1_B, \ + _PLANE_POS_2_A, _PLANE_POS_2_B) #define PLANE_POS_Y_MASK REG_GENMASK(31, 16) #define PLANE_POS_Y(y) REG_FIELD_PREP(PLANE_POS_Y_MASK, (y)) #define PLANE_POS_X_MASK REG_GENMASK(15, 0) @@ -105,9 +114,9 @@ #define _PLANE_SIZE_2_A0x70290 #define _PLANE_SIZE_1_B0x71190 #define _PLANE_SIZE_2_B0x71290 -#define _PLANE_SIZE_1(pipe)_PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B) -#define _PLANE_SIZE_2(pipe)_PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B) -#define PLANE_SIZE(pipe, plane)_MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe)) +#define PLANE_SIZE(pipe, plane)_MMIO_SKL_PLANE((pipe), (plane), \ +
[PATCH v2 12/16] drm/i915: Drop a few unwanted tabs from skl+ plane reg defines
From: Ville Syrjälä A few extra tabs have snuck into the skl+ plane register bit definitions. Remove them. v2: Rebase Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/skl_universal_plane_regs.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h index e8d399592fd3..0b4f97059479 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h @@ -205,17 +205,17 @@ #define _PLANE_CUS_CTL_2(pipe) _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B) #define PLANE_CUS_CTL(pipe, plane) _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe)) #define PLANE_CUS_ENABLE REG_BIT(31) -#define PLANE_CUS_Y_PLANE_MASK REG_BIT(30) +#define PLANE_CUS_Y_PLANE_MASK REG_BIT(30) #define PLANE_CUS_Y_PLANE_4_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0) #define PLANE_CUS_Y_PLANE_5_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1) #define PLANE_CUS_Y_PLANE_6_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0) #define PLANE_CUS_Y_PLANE_7_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1) -#define PLANE_CUS_HPHASE_SIGN_NEGATIVE REG_BIT(19) +#define PLANE_CUS_HPHASE_SIGN_NEGATIVE REG_BIT(19) #define PLANE_CUS_HPHASE_MASKREG_GENMASK(17, 16) #define PLANE_CUS_HPHASE_0 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 0) #define PLANE_CUS_HPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 1) #define PLANE_CUS_HPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 2) -#define PLANE_CUS_VPHASE_SIGN_NEGATIVE REG_BIT(15) +#define PLANE_CUS_VPHASE_SIGN_NEGATIVE REG_BIT(15) #define PLANE_CUS_VPHASE_MASKREG_GENMASK(13, 12) #define PLANE_CUS_VPHASE_0 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 0) #define PLANE_CUS_VPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 1) -- 2.43.2
[PATCH v2 11/16] drm/i915: Use REG_BIT for PLANE_WM bits
From: Ville Syrjälä A couple of PLANE_WM bits were still using the hand rolled (1< Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/skl_universal_plane_regs.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h index 5fcd5898af4f..e8d399592fd3 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h @@ -307,8 +307,8 @@ #define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0) #define _PLANE_WM_BASE(pipe, plane)_PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe)) #define PLANE_WM(pipe, plane, level) _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level))) -#define PLANE_WM_EN (1 << 31) -#define PLANE_WM_IGNORE_LINES(1 << 30) +#define PLANE_WM_EN REG_BIT(31) +#define PLANE_WM_IGNORE_LINESREG_BIT(30) #define PLANE_WM_LINES_MASK REG_GENMASK(26, 14) #define PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0) -- 2.43.2
Re: [RESEND 3/6] drm/radeon: remove radeon_connector_edid() and stop using edid_blob_ptr
On Fri, May 10, 2024 at 5:08 PM Jani Nikula wrote:
>
> radeon_connector_edid() copies the EDID from edid_blob_ptr as a side
> effect if radeon_connector->edid isn't initialized. However, everywhere
> that the returned EDID is used, the EDID should have been set
> beforehands.
>
> Only the drm EDID code should look at the EDID property, anyway, so stop
> using it.
>
> Cc: Alex Deucher
> Cc: Christian König
> Cc: Pan, Xinhui
> Cc: amd-...@lists.freedesktop.org
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/radeon/radeon_audio.c | 7 ---
> drivers/gpu/drm/radeon/radeon_connectors.c | 15 ---
> drivers/gpu/drm/radeon/radeon_mode.h | 2 --
> 3 files changed, 4 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/radeon_audio.c
> b/drivers/gpu/drm/radeon/radeon_audio.c
> index 16c10db3ce6f..0bcd767b9f47 100644
> --- a/drivers/gpu/drm/radeon/radeon_audio.c
> +++ b/drivers/gpu/drm/radeon/radeon_audio.c
> @@ -303,6 +303,7 @@ void radeon_audio_endpoint_wreg(struct radeon_device
> *rdev, u32 offset,
> static void radeon_audio_write_sad_regs(struct drm_encoder *encoder)
> {
> struct drm_connector *connector =
> radeon_get_connector_for_encoder(encoder);
> + struct radeon_connector *radeon_connector =
> to_radeon_connector(connector);
> struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
> struct cea_sad *sads;
> int sad_count;
> @@ -310,7 +311,7 @@ static void radeon_audio_write_sad_regs(struct
> drm_encoder *encoder)
> if (!connector)
> return;
>
> - sad_count = drm_edid_to_sad(radeon_connector_edid(connector), );
> + sad_count = drm_edid_to_sad(radeon_connector->edid, );
> if (sad_count < 0)
> DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
> if (sad_count <= 0)
> @@ -326,6 +327,7 @@ static void radeon_audio_write_sad_regs(struct
> drm_encoder *encoder)
> static void radeon_audio_write_speaker_allocation(struct drm_encoder
> *encoder)
> {
> struct drm_connector *connector =
> radeon_get_connector_for_encoder(encoder);
> + struct radeon_connector *radeon_connector =
> to_radeon_connector(connector);
> struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
> u8 *sadb = NULL;
> int sad_count;
> @@ -333,8 +335,7 @@ static void radeon_audio_write_speaker_allocation(struct
> drm_encoder *encoder)
> if (!connector)
> return;
>
> - sad_count =
> drm_edid_to_speaker_allocation(radeon_connector_edid(connector),
> - );
> + sad_count = drm_edid_to_speaker_allocation(radeon_connector->edid,
> );
> if (sad_count < 0) {
> DRM_DEBUG("Couldn't read Speaker Allocation Data Block: %d\n",
> sad_count);
> diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c
> b/drivers/gpu/drm/radeon/radeon_connectors.c
> index 81b5c3c8f658..80879e946342 100644
> --- a/drivers/gpu/drm/radeon/radeon_connectors.c
> +++ b/drivers/gpu/drm/radeon/radeon_connectors.c
> @@ -255,21 +255,6 @@ static struct drm_encoder *radeon_find_encoder(struct
> drm_connector *connector,
> return NULL;
> }
>
> -struct edid *radeon_connector_edid(struct drm_connector *connector)
> -{
> - struct radeon_connector *radeon_connector =
> to_radeon_connector(connector);
> - struct drm_property_blob *edid_blob = connector->edid_blob_ptr;
> -
> - if (radeon_connector->edid) {
> - return radeon_connector->edid;
> - } else if (edid_blob) {
> - struct edid *edid = kmemdup(edid_blob->data,
> edid_blob->length, GFP_KERNEL);
> - if (edid)
> - radeon_connector->edid = edid;
> - }
> - return radeon_connector->edid;
> -}
> -
> static void radeon_connector_get_edid(struct drm_connector *connector)
> {
> struct drm_device *dev = connector->dev;
> diff --git a/drivers/gpu/drm/radeon/radeon_mode.h
> b/drivers/gpu/drm/radeon/radeon_mode.h
> index 546381a5c918..e0a5af180801 100644
> --- a/drivers/gpu/drm/radeon/radeon_mode.h
> +++ b/drivers/gpu/drm/radeon/radeon_mode.h
> @@ -701,8 +701,6 @@ extern u16
> radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connecto
> extern bool radeon_connector_is_dp12_capable(struct drm_connector
> *connector);
> extern int radeon_get_monitor_bpc(struct drm_connector *connector);
>
> -extern struct edid *radeon_connector_edid(struct drm_connector *connector);
> -
> extern void radeon_connector_hotplug(struct drm_connector *connector);
> extern int radeon_dp_mode_valid_helper(struct drm_connector *connector,
>struct drm_display_mode *mode);
> --
> 2.39.2
>
Reviewed-by: Robert Foss
[PATCH v2 10/16] drm/i915: Shuffle the skl+ plane register definitions
From: Ville Syrjälä Rearrange the plane skl+ universal plane register definitions: - keep everything related to the same register in one place - sort based on register offset - unify the whitespace/etc a bit v2: Define register contents after all offsets (Jani) Cc: Jani Nikula Signed-off-by: Ville Syrjälä --- .../i915/display/skl_universal_plane_regs.h | 481 -- 1 file changed, 200 insertions(+), 281 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h index 49278584caa7..5fcd5898af4f 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h @@ -10,6 +10,11 @@ #define _PLANE_CTL_1_A 0x70180 #define _PLANE_CTL_2_A 0x70280 +#define _PLANE_CTL_1_B 0x71180 +#define _PLANE_CTL_2_B 0x71280 +#define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B) +#define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B) +#define PLANE_CTL(pipe, plane) _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe)) #define PLANE_CTL_ENABLE REG_BIT(31) #define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */ #define PLANE_CTL_ARB_SLOTS(x) REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */ @@ -73,54 +78,132 @@ #define PLANE_CTL_ROTATE_90 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 1) #define PLANE_CTL_ROTATE_180 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 2) #define PLANE_CTL_ROTATE_270 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 3) + #define _PLANE_STRIDE_1_A 0x70188 #define _PLANE_STRIDE_2_A 0x70288 +#define _PLANE_STRIDE_1_B 0x71188 +#define _PLANE_STRIDE_2_B 0x71288 +#define _PLANE_STRIDE_1(pipe) _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B) +#define _PLANE_STRIDE_2(pipe) _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B) +#define PLANE_STRIDE(pipe, plane) _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe)) #define PLANE_STRIDE__MASK REG_GENMASK(11, 0) #define PLANE_STRIDE_(stride) REG_FIELD_PREP(PLANE_STRIDE__MASK, (stride)) + #define _PLANE_POS_1_A 0x7018c #define _PLANE_POS_2_A 0x7028c +#define _PLANE_POS_1_B 0x7118c +#define _PLANE_POS_2_B 0x7128c +#define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B) +#define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B) +#define PLANE_POS(pipe, plane) _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe)) #define PLANE_POS_Y_MASK REG_GENMASK(31, 16) #define PLANE_POS_Y(y) REG_FIELD_PREP(PLANE_POS_Y_MASK, (y)) #define PLANE_POS_X_MASK REG_GENMASK(15, 0) #define PLANE_POS_X(x) REG_FIELD_PREP(PLANE_POS_X_MASK, (x)) + #define _PLANE_SIZE_1_A0x70190 #define _PLANE_SIZE_2_A0x70290 +#define _PLANE_SIZE_1_B0x71190 +#define _PLANE_SIZE_2_B0x71290 +#define _PLANE_SIZE_1(pipe)_PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B) +#define _PLANE_SIZE_2(pipe)_PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B) +#define PLANE_SIZE(pipe, plane)_MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe)) #define PLANE_HEIGHT_MASKREG_GENMASK(31, 16) #define PLANE_HEIGHT(h) REG_FIELD_PREP(PLANE_HEIGHT_MASK, (h)) #define PLANE_WIDTH_MASK REG_GENMASK(15, 0) #define PLANE_WIDTH(w) REG_FIELD_PREP(PLANE_WIDTH_MASK, (w)) + +#define _PLANE_KEYVAL_1_A 0x70194 +#define _PLANE_KEYVAL_2_A 0x70294 +#define _PLANE_KEYVAL_1_B 0x71194 +#define _PLANE_KEYVAL_2_B 0x71294 +#define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B) +#define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B) +#define PLANE_KEYVAL(pipe, plane) _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe)) + +#define _PLANE_KEYMSK_1_A 0x70198 +#define _PLANE_KEYMSK_2_A 0x70298 +#define _PLANE_KEYMSK_1_B 0x71198 +#define _PLANE_KEYMSK_2_B 0x71298 +#define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B) +#define _PLANE_KEYMSK_2(pipe)
[PATCH v2 09/16] drm/i915: Drop useless PLANE_FOO_3 register defines
From: Ville Syrjälä We only need register defines for the first two planes on the first two pipes. Nuke everything else. v2: Drop a few more that snuck through Reviewed-by: Jani Nikula #v1 Signed-off-by: Ville Syrjälä --- .../i915/display/skl_universal_plane_regs.h | 19 --- 1 file changed, 19 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h index d0c760e8..49278584caa7 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h @@ -10,7 +10,6 @@ #define _PLANE_CTL_1_A 0x70180 #define _PLANE_CTL_2_A 0x70280 -#define _PLANE_CTL_3_A 0x70380 #define PLANE_CTL_ENABLE REG_BIT(31) #define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */ #define PLANE_CTL_ARB_SLOTS(x) REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */ @@ -76,31 +75,26 @@ #define PLANE_CTL_ROTATE_270 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 3) #define _PLANE_STRIDE_1_A 0x70188 #define _PLANE_STRIDE_2_A 0x70288 -#define _PLANE_STRIDE_3_A 0x70388 #define PLANE_STRIDE__MASK REG_GENMASK(11, 0) #define PLANE_STRIDE_(stride) REG_FIELD_PREP(PLANE_STRIDE__MASK, (stride)) #define _PLANE_POS_1_A 0x7018c #define _PLANE_POS_2_A 0x7028c -#define _PLANE_POS_3_A 0x7038c #define PLANE_POS_Y_MASK REG_GENMASK(31, 16) #define PLANE_POS_Y(y) REG_FIELD_PREP(PLANE_POS_Y_MASK, (y)) #define PLANE_POS_X_MASK REG_GENMASK(15, 0) #define PLANE_POS_X(x) REG_FIELD_PREP(PLANE_POS_X_MASK, (x)) #define _PLANE_SIZE_1_A0x70190 #define _PLANE_SIZE_2_A0x70290 -#define _PLANE_SIZE_3_A0x70390 #define PLANE_HEIGHT_MASKREG_GENMASK(31, 16) #define PLANE_HEIGHT(h) REG_FIELD_PREP(PLANE_HEIGHT_MASK, (h)) #define PLANE_WIDTH_MASK REG_GENMASK(15, 0) #define PLANE_WIDTH(w) REG_FIELD_PREP(PLANE_WIDTH_MASK, (w)) #define _PLANE_SURF_1_A0x7019c #define _PLANE_SURF_2_A0x7029c -#define _PLANE_SURF_3_A0x7039c #define PLANE_SURF_ADDR_MASK REG_GENMASK(31, 12) #define PLANE_SURF_DECRYPT REG_BIT(2) #define _PLANE_OFFSET_1_A 0x701a4 #define _PLANE_OFFSET_2_A 0x702a4 -#define _PLANE_OFFSET_3_A 0x703a4 #define PLANE_OFFSET_Y_MASK REG_GENMASK(31, 16) #define PLANE_OFFSET_Y(y) REG_FIELD_PREP(PLANE_OFFSET_Y_MASK, (y)) #define PLANE_OFFSET_X_MASK REG_GENMASK(15, 0) @@ -145,7 +139,6 @@ #define PLANE_CUS_VPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 2) #define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */ #define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */ -#define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */ #define PLANE_COLOR_PIPE_GAMMA_ENABLEREG_BIT(30) /* Pre-ICL */ #define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28) #define PLANE_COLOR_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-ICL */ @@ -234,49 +227,38 @@ #define _PLANE_CTL_1_B 0x71180 #define _PLANE_CTL_2_B 0x71280 -#define _PLANE_CTL_3_B 0x71380 #define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B) #define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B) -#define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B) #define PLANE_CTL(pipe, plane) \ _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe)) #define _PLANE_STRIDE_1_B 0x71188 #define _PLANE_STRIDE_2_B 0x71288 -#define _PLANE_STRIDE_3_B 0x71388 #define _PLANE_STRIDE_1(pipe) \ _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B) #define _PLANE_STRIDE_2(pipe) \ _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B) -#define _PLANE_STRIDE_3(pipe) \ - _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B) #define PLANE_STRIDE(pipe, plane) \ _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe)) #define _PLANE_POS_1_B 0x7118c #define _PLANE_POS_2_B 0x7128c -#define _PLANE_POS_3_B
Re: [RESEND 2/6] drm/radeon: convert to using is_hdmi and has_audio from display info
On Fri, May 10, 2024 at 5:08 PM Jani Nikula wrote:
>
> Prefer the parsed results for is_hdmi and has_audio in display info over
> calling drm_detect_hdmi_monitor() and drm_detect_monitor_audio(),
> respectively.
>
> Cc: Alex Deucher
> Cc: Christian König
> Cc: Pan, Xinhui
> Cc: amd-...@lists.freedesktop.org
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/radeon/atombios_encoders.c | 10 +-
> drivers/gpu/drm/radeon/evergreen_hdmi.c| 5 ++---
> drivers/gpu/drm/radeon/radeon_audio.c | 6 +++---
> drivers/gpu/drm/radeon/radeon_connectors.c | 12 ++--
> drivers/gpu/drm/radeon/radeon_display.c| 2 +-
> drivers/gpu/drm/radeon/radeon_encoders.c | 4 ++--
> 6 files changed, 19 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c
> b/drivers/gpu/drm/radeon/atombios_encoders.c
> index 2bff0d9e20f5..0aa395fac36f 100644
> --- a/drivers/gpu/drm/radeon/atombios_encoders.c
> +++ b/drivers/gpu/drm/radeon/atombios_encoders.c
> @@ -701,7 +701,7 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
> if (radeon_connector->use_digital &&
> (radeon_connector->audio == RADEON_AUDIO_ENABLE))
> return ATOM_ENCODER_MODE_HDMI;
> - else if
> (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
> + else if (connector->display_info.is_hdmi &&
> (radeon_connector->audio ==
> RADEON_AUDIO_AUTO))
> return ATOM_ENCODER_MODE_HDMI;
> else if (radeon_connector->use_digital)
> @@ -720,7 +720,7 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
> if (radeon_audio != 0) {
> if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
> return ATOM_ENCODER_MODE_HDMI;
> - else if
> (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
> + else if (connector->display_info.is_hdmi &&
> (radeon_connector->audio ==
> RADEON_AUDIO_AUTO))
> return ATOM_ENCODER_MODE_HDMI;
> else
> @@ -737,14 +737,14 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
> if ((dig_connector->dp_sink_type ==
> CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
> (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
> {
> if (radeon_audio != 0 &&
> -
> drm_detect_monitor_audio(radeon_connector_edid(connector)) &&
> + connector->display_info.has_audio &&
> ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
> return ATOM_ENCODER_MODE_DP_AUDIO;
> return ATOM_ENCODER_MODE_DP;
> } else if (radeon_audio != 0) {
> if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
> return ATOM_ENCODER_MODE_HDMI;
> - else if
> (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
> + else if (connector->display_info.is_hdmi &&
> (radeon_connector->audio ==
> RADEON_AUDIO_AUTO))
> return ATOM_ENCODER_MODE_HDMI;
> else
> @@ -755,7 +755,7 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
> break;
> case DRM_MODE_CONNECTOR_eDP:
> if (radeon_audio != 0 &&
> -
> drm_detect_monitor_audio(radeon_connector_edid(connector)) &&
> + connector->display_info.has_audio &&
> ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
> return ATOM_ENCODER_MODE_DP_AUDIO;
> return ATOM_ENCODER_MODE_DP;
> diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c
> b/drivers/gpu/drm/radeon/evergreen_hdmi.c
> index 681119c91d94..09dda114e218 100644
> --- a/drivers/gpu/drm/radeon/evergreen_hdmi.c
> +++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c
> @@ -412,7 +412,7 @@ void evergreen_hdmi_enable(struct drm_encoder *encoder,
> bool enable)
> if (enable) {
> struct drm_connector *connector =
> radeon_get_connector_for_encoder(encoder);
>
> - if (connector &&
> drm_detect_monitor_audio(radeon_connector_edid(connector))) {
> + if (connector && connector->display_info.has_audio) {
> WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset,
>HDMI_AVI_INFO_SEND | /* enable AVI info frames
> */
>HDMI_AVI_INFO_CONT | /* required for audio
> info values to be updated */
> @@ -450,8 +450,7 @@ void evergreen_dp_enable(struct drm_encoder *encoder,
> bool enable)
>
Re: [PATCH 10/16] drm/i915: Shuffle the skl+ plane register definitions
On Mon, May 13, 2024 at 02:28:11PM +0300, Jani Nikula wrote: > On Fri, 10 May 2024, Ville Syrjala wrote: > > From: Ville Syrjälä > > > > Rearrange the plane skl+ universal plane register definitions: > > - keep everything related to the same register in one place > > - sort based on register offset > > - unify the whitespace/etc a bit > > > > Signed-off-by: Ville Syrjälä > > --- > > .../i915/display/skl_universal_plane_regs.h | 502 -- > > 1 file changed, 207 insertions(+), 295 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h > > b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h > > index 0558d97614e1..0ad14727e334 100644 > > --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h > > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h > > @@ -9,8 +9,6 @@ > > #include "intel_display_reg_defs.h" > > > > #define _PLANE_CTL_1_A 0x70180 > > -#define _PLANE_CTL_2_A 0x70280 > > -#define _PLANE_CTL_3_A 0x70380 > > #define PLANE_CTL_ENABLE REG_BIT(31) > > #define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */ > > #define PLANE_CTL_ARB_SLOTS(x) > > REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */ > > @@ -74,59 +72,132 @@ > > #define PLANE_CTL_ROTATE_90 > > REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 1) > > #define PLANE_CTL_ROTATE_180 > > REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 2) > > #define PLANE_CTL_ROTATE_270 > > REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 3) > > This is a painful patch to review (in part because some newline removals > throw off --color-moved) so I want to check something first. > > Shouldn't the above register *content* definitions be... > > > +#define _PLANE_CTL_2_A 0x70280 > > +#define _PLANE_CTL_1_B 0x71180 > > +#define _PLANE_CTL_2_B 0x71280 > > +#define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, > > _PLANE_CTL_1_B) > > +#define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, > > _PLANE_CTL_2_B) > > +#define PLANE_CTL(pipe, plane) _MMIO_PLANE(plane, > > _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe)) > > ...here after all the register *offset* definitions, not right after the > plane 1 / pipe A register offset macro? Ditto for a bunch of the other > changes here. Shrug. I don't think we have any real consistency in how these things are laid out. Sometimes the bits are defined after the _FOO_A, sometimes after all the _FOO_?, and sometimes after FOO(). I guess we should try to standardize on one of those. And I suppose it should be that last option of those three (which is what you suggest as well) since we don't always have any intermediate _FOO defines at all. I can respin with that. -- Ville Syrjälä Intel
Re: [PATCH] drm/i915/gem/i915_gem_ttm_move: Fix typo
On Mon, May 13, 2024 at 02:14:51AM -0400, Deming Wang wrote: > The mapings should be replaced by mappings. > > Signed-off-by: Deming Wang Reviewed-by: Rodrigo Vivi and pushed to drm-intel-gt-next thanks for the patch > --- > drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c > b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c > index 7078af2f8f79..03b00a03a634 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c > +++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c > @@ -155,7 +155,7 @@ void i915_ttm_adjust_gem_after_move(struct > drm_i915_gem_object *obj) > * @bo: The ttm buffer object. > * > * This function prepares an object for move by removing all GPU bindings, > - * removing all CPU mapings and finally releasing the pages sg-table. > + * removing all CPU mappings and finally releasing the pages sg-table. > * > * Return: 0 if successful, negative error code on error. > */ > -- > 2.31.1 >
RE: [v4] drm/i915: Implement Audio WA_14020863754
> -Original Message-
> From: Shankar, Uma
> Sent: Thursday, May 9, 2024 11:05 AM
> To: intel-gfx@lists.freedesktop.org; intel...@lists.freedesktop.org
> Cc: Borah, Chaitanya Kumar ;
> jani.nik...@linux.intel.com; Roper, Matthew D ;
> Shankar, Uma
> Subject: [v4] drm/i915: Implement Audio WA_14020863754
>
> WA_14020863754: Corner case with Min Hblank Fix can cause audio hang
>
> Issue: Previously a fix was made to avoid issues with extremely small hblanks,
> called the "Min Hblank Fix". However, this can potentially cause an audio
> hang.
>
> Workaround :
> During "Audio Programming Sequence" Audio Enabling - When DP mode is
> enabled Set mmio offset 0x65F1C bit 18 = 1b, before step #1 "Enable audio
> Presence Detect"
>
> During "Audio Programming Sequence" Audio Disabling - When DP mode is
> enabled Clear mmio offset 0x65F1C bit 18 = 0b, after step #6 "Disable Audio PD
> (Presence Detect)"
> If not clearing PD bit, must also not clear 0x65F1C bit 18 (leave = 1b)
>
> v2: Update the platform checks (Jani Nikula)
>
> v3: Limited the WA to LNL and BMG, added a helper (Matt Roper)
>
> v4: Updated the bit naming, fixed redundant if statement
Pushed to drm-intel-next. Thanks for the reviews.
Regards,
Uma Shankar
> Signed-off-by: Uma Shankar
> Reviewed-by: Chaitanya Kumar Borah
> ---
> drivers/gpu/drm/i915/display/intel_audio.c | 15 +++
> drivers/gpu/drm/i915/display/intel_audio_regs.h | 3 +++
> 2 files changed, 18 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
> b/drivers/gpu/drm/i915/display/intel_audio.c
> index ed81e1466c4b..adde87900557 100644
> --- a/drivers/gpu/drm/i915/display/intel_audio.c
> +++ b/drivers/gpu/drm/i915/display/intel_audio.c
> @@ -183,6 +183,15 @@ static const struct hdmi_aud_ncts
> hdmi_aud_ncts_36bpp[] = {
> { 192000, TMDS_445_5M, 20480, 371250 }, };
>
> +/*
> + * WA_14020863754: Implement Audio Workaround
> + * Corner case with Min Hblank Fix can cause audio hang */ static bool
> +needs_wa_14020863754(struct drm_i915_private *i915) {
> + return (DISPLAY_VER(i915) == 20 || IS_BATTLEMAGE(i915)); }
> +
> /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ static u32
> audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state) {
> @@ -
> 415,6 +424,9 @@ static void hsw_audio_codec_disable(struct intel_encoder
> *encoder,
> intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD,
>AUDIO_OUTPUT_ENABLE(cpu_transcoder), 0);
>
> + if (needs_wa_14020863754(i915))
> + intel_de_rmw(i915, AUD_CHICKENBIT_REG3,
> DACBE_DISABLE_MIN_HBLANK_FIX,
> +0);
> +
> mutex_unlock(>display.audio.mutex);
> }
>
> @@ -540,6 +552,9 @@ static void hsw_audio_codec_enable(struct
> intel_encoder *encoder,
> if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP))
> enable_audio_dsc_wa(encoder, crtc_state);
>
> + if (needs_wa_14020863754(i915))
> + intel_de_rmw(i915, AUD_CHICKENBIT_REG3, 0,
> +DACBE_DISABLE_MIN_HBLANK_FIX);
> +
> /* Enable audio presence detect */
> intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD,
>0, AUDIO_OUTPUT_ENABLE(cpu_transcoder));
> diff --git a/drivers/gpu/drm/i915/display/intel_audio_regs.h
> b/drivers/gpu/drm/i915/display/intel_audio_regs.h
> index 88ea2740365d..4c31844d21df 100644
> --- a/drivers/gpu/drm/i915/display/intel_audio_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_audio_regs.h
> @@ -164,4 +164,7 @@
>
> _VLV_AUD_PORT_EN_D_DBG)
> #define VLV_AMP_MUTE (1 << 1)
>
> +#define AUD_CHICKENBIT_REG3 _MMIO(0x65F1C)
> +#define DACBE_DISABLE_MIN_HBLANK_FIXREG_BIT(18)
> +
> #endif /* __INTEL_AUDIO_REGS_H__ */
> --
> 2.42.0
Re: [PATCH 1/2] drm/xe/display: remove unused xe->enabled_irq_mask
On Mon, May 13, 2024 at 03:10:29PM GMT, Jani Nikula wrote:
On Fri, 10 May 2024, Jani Nikula wrote:
The xe->enabled_irq_mask member has never been used for anything.
Signed-off-by: Jani Nikula
Lucas, ack for merging these two via drm-intel-next? Even though these
touch struct xe_device, I presume any further cleanups touching the
surrounding context would have a bigger footprint in drm-intel-next.
Acked-by: Lucas De Marchi
for both patches
thanks,
Lucas De Marchi
BR,
Jani.
---
drivers/gpu/drm/xe/display/xe_display.c | 1 -
drivers/gpu/drm/xe/xe_device_types.h| 2 --
2 files changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/xe/display/xe_display.c
b/drivers/gpu/drm/xe/display/xe_display.c
index 0de0566e5b39..fbe2c2eddea9 100644
--- a/drivers/gpu/drm/xe/display/xe_display.c
+++ b/drivers/gpu/drm/xe/display/xe_display.c
@@ -97,7 +97,6 @@ int xe_display_create(struct xe_device *xe)
xe->display.hotplug.dp_wq = alloc_ordered_workqueue("xe-dp", 0);
drmm_mutex_init(>drm, >sb_lock);
- xe->enabled_irq_mask = ~0;
return drmm_add_action_or_reset(>drm, display_destroy, NULL);
}
diff --git a/drivers/gpu/drm/xe/xe_device_types.h
b/drivers/gpu/drm/xe/xe_device_types.h
index 906b98fb973b..b78223e3baab 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -517,8 +517,6 @@ struct xe_device {
/* only to allow build, not used functionally */
u32 irq_mask;
- u32 enabled_irq_mask;
-
struct intel_uncore {
spinlock_t lock;
} uncore;
--
Jani Nikula, Intel
✓ Fi.CI.BAT: success for drm/i915/gem/i915_gem_ttm_move: Fix typo
== Series Details ==
Series: drm/i915/gem/i915_gem_ttm_move: Fix typo
URL : https://patchwork.freedesktop.org/series/133540/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14754 -> Patchwork_133540v1
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133540v1/index.html
Participating hosts (43 -> 40)
--
Missing(3): bat-arls-2 bat-jsl-1 fi-snb-2520m
Known issues
Here are the changes found in Patchwork_133540v1 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@gt_engines:
- bat-adls-6: [PASS][1] -> [TIMEOUT][2] ([i915#10026] /
[i915#10134])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14754/bat-adls-6/igt@i915_selftest@live@gt_engines.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133540v1/bat-adls-6/igt@i915_selftest@live@gt_engines.html
Possible fixes
* igt@gem_lmem_swapping@basic@lmem0:
- bat-dg2-9: [FAIL][3] ([i915#10378]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14754/bat-dg2-9/igt@gem_lmem_swapping@ba...@lmem0.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133540v1/bat-dg2-9/igt@gem_lmem_swapping@ba...@lmem0.html
* igt@i915_selftest@live@execlists:
- fi-bsw-n3050: [ABORT][5] ([i915#10594]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14754/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133540v1/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#10026]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10026
[i915#10134]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10134
[i915#10378]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10378
[i915#10435]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10435
[i915#10594]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10594
Build changes
-
* Linux: CI_DRM_14754 -> Patchwork_133540v1
CI-20190529: 20190529
CI_DRM_14754: 7def831e1e6b6d95c92e0a4fad9539a95141403d @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_7847: 86712f2effc8ba6690c7e165ad63904416763b75 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_133540v1: 7def831e1e6b6d95c92e0a4fad9539a95141403d @
git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133540v1/index.html
[PATCH v2] drm/i915/mtl: Update workaround 14018778641
The WA should be extended to cover VDBOX engine. We found that 28-channels 1080p VP9 encoding may hit this issue. Signed-off-by: Chen, Angus --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index d1ab560fcdfc..da0a481a375e 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1586,6 +1586,9 @@ xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) */ wa_write_or(wal, XELPMP_GSC_MOD_CTRL, FORCE_MISS_FTLB); + /* Wa_14018778641 */ + wa_write_or(wal, XELPMP_VDBX_MOD_CTRL, FORCE_MISS_FTLB); + /* Wa_22016670082 */ wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE); -- 2.34.1
✗ Fi.CI.BUILD: failure for drm/i915: Correct error handler (rev4)
== Series Details == Series: drm/i915: Correct error handler (rev4) URL : https://patchwork.freedesktop.org/series/133538/ State : failure == Summary == Error: patch https://patchwork.freedesktop.org/api/1.0/series/133538/revisions/4/mbox/ not applied Applying: drm/i915: Correct error handler error: corrupt patch at line 15 error: could not build fake ancestor hint: Use 'git am --show-current-patch=diff' to see the failed patch Patch failed at 0001 drm/i915: Correct error handler When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort". Build failed, no error log produced
Re: [RESEND 0/6] drm, nouveau/radeon/amdpgu: edid_blob_ptr cleanups
On Mon, May 13, 2024 at 8:20 AM Jani Nikula wrote: > > On Fri, 10 May 2024, Alex Deucher wrote: > > On Fri, May 10, 2024 at 11:17 AM Jani Nikula wrote: > >> > >> I've sent this some moths ago, let's try again... > >> > >> BR, > >> Jani. > >> > >> Jani Nikula (6): > >> drm/nouveau: convert to using is_hdmi and has_audio from display info > >> drm/radeon: convert to using is_hdmi and has_audio from display info > >> drm/radeon: remove radeon_connector_edid() and stop using > >> edid_blob_ptr > >> drm/amdgpu: remove amdgpu_connector_edid() and stop using > >> edid_blob_ptr > >> drm/edid: add a helper for EDID sysfs property show > >> drm/connector: update edid_blob_ptr documentation > > > > Series is: > > Acked-by: Alex Deucher > > Thanks, do you want to pick these up via your tree? And do you expect a > proper R-b before merging? Feel free to take them via drm-misc if you'd prefer to land the whole set together, otherwise, I can pick up the radeon/amdgpu patches. Alex > > BR, > Jani. > > > > > >> > >> .../gpu/drm/amd/amdgpu/amdgpu_connectors.c| 16 - > >> .../gpu/drm/amd/amdgpu/amdgpu_connectors.h| 1 - > >> drivers/gpu/drm/amd/amdgpu/dce_v10_0.c| 4 +-- > >> drivers/gpu/drm/amd/amdgpu/dce_v11_0.c| 4 +-- > >> drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 4 +-- > >> drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 4 +-- > >> drivers/gpu/drm/drm_crtc_internal.h | 2 ++ > >> drivers/gpu/drm/drm_edid.c| 33 +++ > >> drivers/gpu/drm/drm_sysfs.c | 24 ++ > >> drivers/gpu/drm/nouveau/dispnv50/disp.c | 8 ++--- > >> drivers/gpu/drm/nouveau/dispnv50/head.c | 8 + > >> drivers/gpu/drm/nouveau/nouveau_connector.c | 2 +- > >> drivers/gpu/drm/radeon/atombios_encoders.c| 10 +++--- > >> drivers/gpu/drm/radeon/evergreen_hdmi.c | 5 ++- > >> drivers/gpu/drm/radeon/radeon_audio.c | 13 > >> drivers/gpu/drm/radeon/radeon_connectors.c| 27 --- > >> drivers/gpu/drm/radeon/radeon_display.c | 2 +- > >> drivers/gpu/drm/radeon/radeon_encoders.c | 4 +-- > >> drivers/gpu/drm/radeon/radeon_mode.h | 2 -- > >> include/drm/drm_connector.h | 6 +++- > >> 20 files changed, 79 insertions(+), 100 deletions(-) > >> > >> -- > >> 2.39.2 > >> > > -- > Jani Nikula, Intel
Re: [PATCH] drm/i915: Correct error handler
Maybe the format is incorrect. I would like to use
"jiashengjiangc...@outlook.com" to resend my patch.
-Jiasheng
From: Jiasheng Jiang
Sent: Saturday, May 11, 2024 3:40
To: jani.nik...@linux.intel.com; joonas.lahti...@linux.intel.com;
rodrigo.v...@intel.com; tursu...@ursulin.net; airl...@gmail.com;
dan...@ffwll.ch; ch...@chris-wilson.co.uk
Cc: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org;
linux-ker...@vger.kernel.org
Subject: [PATCH] drm/i915: Correct error handler
Replace "slab_priorities" with "slab_dependencies" in the error handler
to avoid memory leak.
Fixes: 32eb6bcfdda9 ("drm/i915: Make request allocation caches global")
Signed-off-by: Jiasheng Jiang
---
drivers/gpu/drm/i915/i915_scheduler.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c
b/drivers/gpu/drm/i915/i915_scheduler.c
index 762127dd56c5..70a854557e6e 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -506,6 +506,6 @@ int __init i915_scheduler_module_init(void)
return 0;
err_priorities:
- kmem_cache_destroy(slab_priorities);
+ kmem_cache_destroy(slab_dependencies);
return -ENOMEM;
}
--
2.25.1
[PATCH] drm/i915: Correct error handler
Replace "slab_priorities" with "slab_dependencies" in the error handler
to avoid memory leak.
Fixes: 32eb6bcfdda9 ("drm/i915: Make request allocation caches global")
Signed-off-by: Jiasheng Jiang
---
drivers/gpu/drm/i915/i915_scheduler.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c
b/drivers/gpu/drm/i915/i915_scheduler.c
index 762127dd56c5..70a854557e6e 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -506,6 +506,6 @@ int __init i915_scheduler_module_init(void)
return 0;
err_priorities:
- kmem_cache_destroy(slab_priorities);
+ kmem_cache_destroy(slab_dependencies);
return -ENOMEM;
}
--
2.25.1
[PATCH] drm/i915: Correct error handler
From: Jiasheng Jiang
Replace "slab_priorities" with "slab_dependencies" in the error handler
to avoid memory leak.
Fixes: 32eb6bcfdda9 ("drm/i915: Make request allocation caches global")
Signed-off-by: Jiasheng Jiang
---
drivers/gpu/drm/i915/i915_scheduler.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c
b/drivers/gpu/drm/i915/i915_scheduler.c
index 762127dd56c5..70a854557e6e 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -506,6 +506,6 @@ int __init i915_scheduler_module_init(void)
return 0;
err_priorities:
- kmem_cache_destroy(slab_priorities);
+ kmem_cache_destroy(slab_dependencies);
return -ENOMEM;
}
--
2.25.1
[PATCH] drm/i915/gem/i915_gem_ttm_move: Fix typo
The mapings should be replaced by mappings. Signed-off-by: Deming Wang --- drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c index 7078af2f8f79..03b00a03a634 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c @@ -155,7 +155,7 @@ void i915_ttm_adjust_gem_after_move(struct drm_i915_gem_object *obj) * @bo: The ttm buffer object. * * This function prepares an object for move by removing all GPU bindings, - * removing all CPU mapings and finally releasing the pages sg-table. + * removing all CPU mappings and finally releasing the pages sg-table. * * Return: 0 if successful, negative error code on error. */ -- 2.31.1
[PATCH] drm/i915: Correct error handler
Replace "slab_priorities" with "slab_dependencies" in the error handler to
avoid memory leak.
Fixes: 32eb6bcfdda9 ("drm/i915: Make request allocation caches global")
Signed-off-by: Jiasheng Jiang
---
drivers/gpu/drm/i915/i915_scheduler.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c
b/drivers/gpu/drm/i915/i915_scheduler.c
index 762127dd56c5..70a854557e6e 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -506,6 +506,6 @@ int __init i915_scheduler_module_init(void)
return 0;
err_priorities:
- kmem_cache_destroy(slab_priorities);
+ kmem_cache_destroy(slab_dependencies);
return -ENOMEM;
}
--
2.25.1
[PATCH] drm/i915: Correct error handler
Replace "slab_priorities" with "slab_dependencies" in the error handler
to avoid memory leak.
Fixes: 32eb6bcfdda9 ("drm/i915: Make request allocation caches global")
Signed-off-by: Jiasheng Jiang
---
drivers/gpu/drm/i915/i915_scheduler.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c
b/drivers/gpu/drm/i915/i915_scheduler.c
index 762127dd56c5..70a854557e6e 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -506,6 +506,6 @@ int __init i915_scheduler_module_init(void)
return 0;
err_priorities:
- kmem_cache_destroy(slab_priorities);
+ kmem_cache_destroy(slab_dependencies);
return -ENOMEM;
}
--
2.25.1
[PATCH v2] drm/i915/mtl: Update workaround 14018778641
From: Angus Chen Applying it to VDBOX after recent performance data on MTL Signed-off-by: Angus Chen --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index f3332bc55b8f..8432fb4fd28d 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1695,6 +1695,9 @@ xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) */ wa_write_or(wal, XELPMP_GSC_MOD_CTRL, FORCE_MISS_FTLB); + /* Wa_14018778641 */ + wa_write_or(wal, XELPMP_VDBX_MOD_CTRL, FORCE_MISS_FTLB); + debug_dump_steering(gt); } -- 2.34.1
Re: [RESEND 0/6] drm, nouveau/radeon/amdpgu: edid_blob_ptr cleanups
On Fri, 10 May 2024, Alex Deucher wrote: > On Fri, May 10, 2024 at 11:17 AM Jani Nikula wrote: >> >> I've sent this some moths ago, let's try again... >> >> BR, >> Jani. >> >> Jani Nikula (6): >> drm/nouveau: convert to using is_hdmi and has_audio from display info >> drm/radeon: convert to using is_hdmi and has_audio from display info >> drm/radeon: remove radeon_connector_edid() and stop using >> edid_blob_ptr >> drm/amdgpu: remove amdgpu_connector_edid() and stop using >> edid_blob_ptr >> drm/edid: add a helper for EDID sysfs property show >> drm/connector: update edid_blob_ptr documentation > > Series is: > Acked-by: Alex Deucher Thanks, do you want to pick these up via your tree? And do you expect a proper R-b before merging? BR, Jani. > >> >> .../gpu/drm/amd/amdgpu/amdgpu_connectors.c| 16 - >> .../gpu/drm/amd/amdgpu/amdgpu_connectors.h| 1 - >> drivers/gpu/drm/amd/amdgpu/dce_v10_0.c| 4 +-- >> drivers/gpu/drm/amd/amdgpu/dce_v11_0.c| 4 +-- >> drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 4 +-- >> drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 4 +-- >> drivers/gpu/drm/drm_crtc_internal.h | 2 ++ >> drivers/gpu/drm/drm_edid.c| 33 +++ >> drivers/gpu/drm/drm_sysfs.c | 24 ++ >> drivers/gpu/drm/nouveau/dispnv50/disp.c | 8 ++--- >> drivers/gpu/drm/nouveau/dispnv50/head.c | 8 + >> drivers/gpu/drm/nouveau/nouveau_connector.c | 2 +- >> drivers/gpu/drm/radeon/atombios_encoders.c| 10 +++--- >> drivers/gpu/drm/radeon/evergreen_hdmi.c | 5 ++- >> drivers/gpu/drm/radeon/radeon_audio.c | 13 >> drivers/gpu/drm/radeon/radeon_connectors.c| 27 --- >> drivers/gpu/drm/radeon/radeon_display.c | 2 +- >> drivers/gpu/drm/radeon/radeon_encoders.c | 4 +-- >> drivers/gpu/drm/radeon/radeon_mode.h | 2 -- >> include/drm/drm_connector.h | 6 +++- >> 20 files changed, 79 insertions(+), 100 deletions(-) >> >> -- >> 2.39.2 >> -- Jani Nikula, Intel
Re: [RESEND 1/6] drm/nouveau: convert to using is_hdmi and has_audio from display info
On Fri, 10 May 2024, Lyude Paul wrote:
> Reviewed-by: Lyude Paul
Thanks, how do you want to handle merging this?
BR,
Jani.
>
> On Fri, 2024-05-10 at 18:08 +0300, Jani Nikula wrote:
>> Prefer the parsed results for is_hdmi and has_audio in display info
>> over
>> calling drm_detect_hdmi_monitor() and drm_detect_monitor_audio(),
>> respectively.
>>
>> Conveniently, this also removes the need to use edid_blob_ptr.
>>
>> v2: Reverse a backwards if condition (Ilia)
>>
>> Cc: Karol Herbst
>> Cc: Lyude Paul
>> Cc: Danilo Krummrich
>> Cc: nouv...@lists.freedesktop.org
>> Signed-off-by: Jani Nikula
>> ---
>> drivers/gpu/drm/nouveau/dispnv50/disp.c | 8
>> drivers/gpu/drm/nouveau/dispnv50/head.c | 8 +---
>> drivers/gpu/drm/nouveau/nouveau_connector.c | 2 +-
>> 3 files changed, 6 insertions(+), 12 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c
>> b/drivers/gpu/drm/nouveau/dispnv50/disp.c
>> index 0c3d88ad0b0e..168c27213287 100644
>> --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c
>> +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c
>> @@ -751,7 +751,7 @@ nv50_audio_enable(struct drm_encoder *encoder,
>> struct nouveau_crtc *nv_crtc,
>> struct nouveau_encoder *nv_encoder =
>> nouveau_encoder(encoder);
>> struct nvif_outp *outp = _encoder->outp;
>>
>> -if (!nv50_audio_supported(encoder) ||
>> !drm_detect_monitor_audio(nv_connector->edid))
>> +if (!nv50_audio_supported(encoder) || !nv_connector-
>> >base.display_info.has_audio)
>> return;
>>
>> mutex_lock(>audio.lock);
>> @@ -1765,7 +1765,7 @@ nv50_sor_atomic_enable(struct drm_encoder
>> *encoder, struct drm_atomic_state *sta
>> if ((disp->disp->object.oclass == GT214_DISP ||
>> disp->disp->object.oclass >= GF110_DISP) &&
>> nv_encoder->dcb->type != DCB_OUTPUT_LVDS &&
>> - drm_detect_monitor_audio(nv_connector->edid))
>> + nv_connector->base.display_info.has_audio)
>> hda = true;
>>
>> if (!nvif_outp_acquired(outp))
>> @@ -1774,7 +1774,7 @@ nv50_sor_atomic_enable(struct drm_encoder
>> *encoder, struct drm_atomic_state *sta
>> switch (nv_encoder->dcb->type) {
>> case DCB_OUTPUT_TMDS:
>> if (disp->disp->object.oclass != NV50_DISP &&
>> - drm_detect_hdmi_monitor(nv_connector->edid))
>> + nv_connector->base.display_info.is_hdmi)
>> nv50_hdmi_enable(encoder, nv_crtc,
>> nv_connector, state, mode, hda);
>>
>> if (nv_encoder->outp.or.link & 1) {
>> @@ -1787,7 +1787,7 @@ nv50_sor_atomic_enable(struct drm_encoder
>> *encoder, struct drm_atomic_state *sta
>> */
>> if (mode->clock >= 165000 &&
>> nv_encoder->dcb->duallink_possible &&
>> - !drm_detect_hdmi_monitor(nv_connector-
>> >edid))
>> + !nv_connector-
>> >base.display_info.is_hdmi)
>> proto =
>> NV507D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS;
>> } else {
>> proto =
>> NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B;
>> diff --git a/drivers/gpu/drm/nouveau/dispnv50/head.c
>> b/drivers/gpu/drm/nouveau/dispnv50/head.c
>> index 83355dbc15ee..d7c74cc43ba5 100644
>> --- a/drivers/gpu/drm/nouveau/dispnv50/head.c
>> +++ b/drivers/gpu/drm/nouveau/dispnv50/head.c
>> @@ -127,14 +127,8 @@ nv50_head_atomic_check_view(struct
>> nv50_head_atom *armh,
>> struct drm_display_mode *omode = >state.adjusted_mode;
>> struct drm_display_mode *umode = >state.mode;
>> int mode = asyc->scaler.mode;
>> -struct edid *edid;
>> int umode_vdisplay, omode_hdisplay, omode_vdisplay;
>>
>> -if (connector->edid_blob_ptr)
>> -edid = (struct edid *)connector->edid_blob_ptr-
>> >data;
>> -else
>> -edid = NULL;
>> -
>> if (!asyc->scaler.full) {
>> if (mode == DRM_MODE_SCALE_NONE)
>> omode = umode;
>> @@ -162,7 +156,7 @@ nv50_head_atomic_check_view(struct nv50_head_atom
>> *armh,
>> */
>> if ((asyc->scaler.underscan.mode == UNDERSCAN_ON ||
>> (asyc->scaler.underscan.mode == UNDERSCAN_AUTO &&
>> - drm_detect_hdmi_monitor(edid {
>> + connector->display_info.is_hdmi))) {
>> u32 bX = asyc->scaler.underscan.hborder;
>> u32 bY = asyc->scaler.underscan.vborder;
>> u32 r = (asyh->view.oH << 19) / asyh->view.oW;
>> diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c
>> b/drivers/gpu/drm/nouveau/nouveau_connector.c
>> index 856b3ef5edb8..938832a6af15 100644
>> --- a/drivers/gpu/drm/nouveau/nouveau_connector.c
>> +++ b/drivers/gpu/drm/nouveau/nouveau_connector.c
>> @@ -1034,7 +1034,7 @@ get_tmds_link_bandwidth(struct drm_connector
>> *connector)
>> unsigned duallink_scale =
>> nouveau_duallink && nv_encoder->dcb-
>> >duallink_possible ? 2 : 1;
>>
>> -if
Re: [PATCH 1/2] drm/xe/display: remove unused xe->enabled_irq_mask
On Fri, 10 May 2024, Jani Nikula wrote:
> The xe->enabled_irq_mask member has never been used for anything.
>
> Signed-off-by: Jani Nikula
Lucas, ack for merging these two via drm-intel-next? Even though these
touch struct xe_device, I presume any further cleanups touching the
surrounding context would have a bigger footprint in drm-intel-next.
BR,
Jani.
> ---
> drivers/gpu/drm/xe/display/xe_display.c | 1 -
> drivers/gpu/drm/xe/xe_device_types.h| 2 --
> 2 files changed, 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/display/xe_display.c
> b/drivers/gpu/drm/xe/display/xe_display.c
> index 0de0566e5b39..fbe2c2eddea9 100644
> --- a/drivers/gpu/drm/xe/display/xe_display.c
> +++ b/drivers/gpu/drm/xe/display/xe_display.c
> @@ -97,7 +97,6 @@ int xe_display_create(struct xe_device *xe)
> xe->display.hotplug.dp_wq = alloc_ordered_workqueue("xe-dp", 0);
>
> drmm_mutex_init(>drm, >sb_lock);
> - xe->enabled_irq_mask = ~0;
>
> return drmm_add_action_or_reset(>drm, display_destroy, NULL);
> }
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h
> b/drivers/gpu/drm/xe/xe_device_types.h
> index 906b98fb973b..b78223e3baab 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -517,8 +517,6 @@ struct xe_device {
> /* only to allow build, not used functionally */
> u32 irq_mask;
>
> - u32 enabled_irq_mask;
> -
> struct intel_uncore {
> spinlock_t lock;
> } uncore;
--
Jani Nikula, Intel
✓ Fi.CI.BAT: success for drm/i915/fbc: Add sizes to info message about reducing fb size
== Series Details == Series: drm/i915/fbc: Add sizes to info message about reducing fb size URL : https://patchwork.freedesktop.org/series/133534/ State : success == Summary == CI Bug Log - changes from CI_DRM_14752 -> Patchwork_133534v1 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133534v1/index.html Participating hosts (43 -> 40) -- Additional (1): fi-kbl-8809g Missing(4): bat-kbl-2 bat-dg2-11 bat-arls-1 fi-snb-2520m Known issues Here are the changes found in Patchwork_133534v1 that come from known issues: ### IGT changes ### Issues hit * igt@debugfs_test@basic-hwmon: - bat-arls-3: NOTRUN -> [SKIP][1] ([i915#9318]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133534v1/bat-arls-3/igt@debugfs_t...@basic-hwmon.html * igt@gem_huc_copy@huc-copy: - fi-kbl-8809g: NOTRUN -> [SKIP][2] ([i915#2190]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133534v1/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@parallel-random-engines: - bat-arls-3: NOTRUN -> [SKIP][3] ([i915#10213]) +3 other tests skip [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133534v1/bat-arls-3/igt@gem_lmem_swapp...@parallel-random-engines.html - fi-kbl-8809g: NOTRUN -> [SKIP][4] ([i915#4613]) +3 other tests skip [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133534v1/fi-kbl-8809g/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_mmap@basic: - bat-arls-3: NOTRUN -> [SKIP][5] ([i915#4083]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133534v1/bat-arls-3/igt@gem_m...@basic.html * igt@gem_render_tiled_blits@basic: - bat-arls-3: NOTRUN -> [SKIP][6] ([i915#10197] / [i915#10211] / [i915#4079]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133534v1/bat-arls-3/igt@gem_render_tiled_bl...@basic.html * igt@gem_tiled_blits@basic: - bat-arls-3: NOTRUN -> [SKIP][7] ([i915#10196] / [i915#4077]) +2 other tests skip [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133534v1/bat-arls-3/igt@gem_tiled_bl...@basic.html * igt@gem_tiled_pread_basic: - bat-arls-3: NOTRUN -> [SKIP][8] ([i915#10206] / [i915#4079]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133534v1/bat-arls-3/igt@gem_tiled_pread_basic.html * igt@i915_pm_rps@basic-api: - bat-arls-3: NOTRUN -> [SKIP][9] ([i915#10209]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133534v1/bat-arls-3/igt@i915_pm_...@basic-api.html * igt@kms_addfb_basic@basic-y-tiled-legacy: - bat-arls-3: NOTRUN -> [SKIP][10] ([i915#10200]) +9 other tests skip [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133534v1/bat-arls-3/igt@kms_addfb_ba...@basic-y-tiled-legacy.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - bat-arls-3: NOTRUN -> [SKIP][11] ([i915#10202]) +1 other test skip [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133534v1/bat-arls-3/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html * igt@kms_dsc@dsc-basic: - fi-kbl-8809g: NOTRUN -> [SKIP][12] +30 other tests skip [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133534v1/fi-kbl-8809g/igt@kms_...@dsc-basic.html - bat-arls-3: NOTRUN -> [SKIP][13] ([i915#9886]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133534v1/bat-arls-3/igt@kms_...@dsc-basic.html * igt@kms_force_connector_basic@force-load-detect: - bat-arls-3: NOTRUN -> [SKIP][14] ([i915#10207]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133534v1/bat-arls-3/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_pm_backlight@basic-brightness: - bat-arls-3: NOTRUN -> [SKIP][15] ([i915#9812]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133534v1/bat-arls-3/igt@kms_pm_backli...@basic-brightness.html * igt@kms_psr@psr-primary-mmap-gtt: - bat-arls-3: NOTRUN -> [SKIP][16] ([i915#9732]) +3 other tests skip [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133534v1/bat-arls-3/igt@kms_...@psr-primary-mmap-gtt.html * igt@kms_setmode@basic-clone-single-crtc: - bat-arls-3: NOTRUN -> [SKIP][17] ([i915#10208] / [i915#8809]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133534v1/bat-arls-3/igt@kms_setm...@basic-clone-single-crtc.html * igt@prime_vgem@basic-fence-read: - bat-arls-3: NOTRUN -> [SKIP][18] ([i915#10212] / [i915#3708]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133534v1/bat-arls-3/igt@prime_v...@basic-fence-read.html * igt@prime_vgem@basic-gtt: - bat-arls-3: NOTRUN -> [SKIP][19] ([i915#10196] / [i915#3708] / [i915#4077]) +1 other test
✗ Fi.CI.CHECKPATCH: warning for drm/i915/fbc: Add sizes to info message about reducing fb size
== Series Details == Series: drm/i915/fbc: Add sizes to info message about reducing fb size URL : https://patchwork.freedesktop.org/series/133534/ State : warning == Summary == Error: dim checkpatch failed f707833392ee drm/i915/fbc: Add sizes to info message about reducing fb size -:10: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line (possible unwrapped commit description?) #10: [drm] Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS. total: 0 errors, 1 warnings, 0 checks, 9 lines checked
RE: [PATCH v8 1/7] drm/i915: Define and compute Transcoder CMRR registers
On Mon, 13 May 2024, "Murthy, Arun R" wrote:
>> -Original Message-
>> From: Intel-gfx On Behalf Of Mitul
>> Golani
>> Sent: Thursday, May 9, 2024 1:28 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: Shankar, Uma ; Nikula, Jani
>>
>> Subject: [PATCH v8 1/7] drm/i915: Define and compute Transcoder CMRR
>> registers
>>
>> Add register definitions for Transcoder Fixed Average Vtotal mode/CMRR
>> function, with the necessary bitfields.
>> Compute these registers when CMRR is enabled, extending Adaptive refresh
>> rate capabilities.
>>
>> --v2:
>> - Use intel_de_read64_2x32 in intel_vrr_get_config. [Jani]
>> - Fix indent and order based on register offset. [Jani]
>>
>> --v3:
>> - Removing RFC tag.
>>
>> --v4:
>> - Update place holder for CMRR register definition. (Jani)
>>
>> Signed-off-by: Mitul Golani
>> ---
>> drivers/gpu/drm/i915/display/intel_display.c | 23 ++-
>> .../drm/i915/display/intel_display_types.h| 6 +
>> drivers/gpu/drm/i915/display/intel_vrr.c | 22 ++
>> drivers/gpu/drm/i915/i915_reg.h | 10
> Please create a new header file to add the CMRR related register definitions.
Or just intel_vrr_regs.h?
BR,
Jani.
>
> Thanks and Regards,
> Arun R Murthy
>
>
>> 4 files changed, 60 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>> b/drivers/gpu/drm/i915/display/intel_display.c
>> index ef986b508431..258a78447fba 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -1001,6 +1001,13 @@ static bool vrr_params_changed(const struct
>> intel_crtc_state *old_crtc_state,
>> old_crtc_state->vrr.pipeline_full != new_crtc_state-
>> >vrr.pipeline_full;
>> }
>>
>> +static bool cmrr_params_changed(const struct intel_crtc_state
>> *old_crtc_state,
>> + const struct intel_crtc_state *new_crtc_state)
>> {
>> + return old_crtc_state->cmrr.cmrr_m != new_crtc_state->cmrr.cmrr_m ||
>> + old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n; }
>> +
>> static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state,
>>const struct intel_crtc_state *new_crtc_state) { @@ -
>> 5051,6 +5058,16 @@ intel_pipe_config_compare(const struct intel_crtc_state
>> *current_config,
>> } \
>> } while (0)
>>
>> +#define PIPE_CONF_CHECK_LLI(name) do { \
>> + if (current_config->name != pipe_config->name) { \
>> + pipe_config_mismatch(, fastset, crtc, __stringify(name), \
>> + "(expected %lli, found %lli)", \
>> + current_config->name, \
>> + pipe_config->name); \
>> + ret = false; \
>> + } \
>> +} while (0)
>> +
>> #define PIPE_CONF_CHECK_BOOL(name) do { \
>> if (current_config->name != pipe_config->name) { \
>> BUILD_BUG_ON_MSG(!__same_type(current_config->name,
>> bool), \ @@ -5415,10 +5432,13 @@ intel_pipe_config_compare(const struct
>> intel_crtc_state *current_config,
>> PIPE_CONF_CHECK_I(vrr.guardband);
>> PIPE_CONF_CHECK_I(vrr.vsync_start);
>> PIPE_CONF_CHECK_I(vrr.vsync_end);
>> + PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
>> + PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
>> }
>>
>> #undef PIPE_CONF_CHECK_X
>> #undef PIPE_CONF_CHECK_I
>> +#undef PIPE_CONF_CHECK_LLI
>> #undef PIPE_CONF_CHECK_BOOL
>> #undef PIPE_CONF_CHECK_P
>> #undef PIPE_CONF_CHECK_FLAGS
>> @@ -6807,7 +6827,8 @@ static void intel_pre_update_crtc(struct
>> intel_atomic_state *state,
>> intel_crtc_needs_fastset(new_crtc_state))
>> icl_set_pipe_chicken(new_crtc_state);
>>
>> - if (vrr_params_changed(old_crtc_state, new_crtc_state))
>> + if (vrr_params_changed(old_crtc_state, new_crtc_state) ||
>> + cmrr_params_changed(old_crtc_state, new_crtc_state))
>> intel_vrr_set_transcoder_timings(new_crtc_state);
>> }
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
>> b/drivers/gpu/drm/i915/display/intel_display_types.h
>> index a06a154d587b..475fb5252dd4 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>> @@ -1396,6 +1396,12 @@ struct intel_crtc_state {
>> u32 vsync_end, vsync_start;
>> } vrr;
>>
>> + /* Content Match Refresh Rate state */
>> + struct {
>> + bool enable;
>> + u64 cmrr_n, cmrr_m;
>> + } cmrr;
>> +
>> /* Stream Splitter for eDP MSO */
>> struct {
>> bool enable;
>> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
>> b/drivers/gpu/drm/i915/display/intel_vrr.c
>> index 894ee97b3e1b..831554ea46b2 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
Re: [PATCH v8 1/7] drm/i915: Define and compute Transcoder CMRR registers
On Thu, 09 May 2024, Mitul Golani wrote: > Add register definitions for Transcoder Fixed Average > Vtotal mode/CMRR function, with the necessary bitfields. > Compute these registers when CMRR is enabled, extending > Adaptive refresh rate capabilities. > > --v2: > - Use intel_de_read64_2x32 in intel_vrr_get_config. [Jani] > - Fix indent and order based on register offset. [Jani] How does this match with... > > +#define _TRANS_CMRR_M_LO_A 0x604F0 > +#define _TRANS_CMRR_M_HI_A 0x604F4 > +#define _TRANS_CMRR_N_LO_A 0x604F8 > +#define _TRANS_CMRR_N_HI_A 0x604FC > +#define TRANS_CMRR_M_LO(trans) _MMIO_TRANS2(dev_priv, trans, > _TRANS_CMRR_M_LO_A) > +#define TRANS_CMRR_M_HI(trans) _MMIO_TRANS2(dev_priv, trans, > _TRANS_CMRR_M_HI_A) > +#define TRANS_CMRR_N_LO(trans) _MMIO_TRANS2(dev_priv, trans, > _TRANS_CMRR_N_LO_A) > +#define TRANS_CMRR_N_HI(trans) _MMIO_TRANS2(dev_priv, trans, > _TRANS_CMRR_N_HI_A) > + ...this? Please read the comment at the top of i915_reg.h BR, Jani. > /* VGA port control */ > #define ADPA _MMIO(0x61100) > #define PCH_ADPA_MMIO(0xe1100) -- Jani Nikula, Intel
Re: [PATCH 10/16] drm/i915: Shuffle the skl+ plane register definitions
On Fri, 10 May 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > Rearrange the plane skl+ universal plane register definitions: > - keep everything related to the same register in one place > - sort based on register offset > - unify the whitespace/etc a bit > > Signed-off-by: Ville Syrjälä > --- > .../i915/display/skl_universal_plane_regs.h | 502 -- > 1 file changed, 207 insertions(+), 295 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h > b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h > index 0558d97614e1..0ad14727e334 100644 > --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h > @@ -9,8 +9,6 @@ > #include "intel_display_reg_defs.h" > > #define _PLANE_CTL_1_A 0x70180 > -#define _PLANE_CTL_2_A 0x70280 > -#define _PLANE_CTL_3_A 0x70380 > #define PLANE_CTL_ENABLE REG_BIT(31) > #define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */ > #define PLANE_CTL_ARB_SLOTS(x) > REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */ > @@ -74,59 +72,132 @@ > #define PLANE_CTL_ROTATE_90 > REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 1) > #define PLANE_CTL_ROTATE_180 > REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 2) > #define PLANE_CTL_ROTATE_270 > REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 3) This is a painful patch to review (in part because some newline removals throw off --color-moved) so I want to check something first. Shouldn't the above register *content* definitions be... > +#define _PLANE_CTL_2_A 0x70280 > +#define _PLANE_CTL_1_B 0x71180 > +#define _PLANE_CTL_2_B 0x71280 > +#define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, > _PLANE_CTL_1_B) > +#define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, > _PLANE_CTL_2_B) > +#define PLANE_CTL(pipe, plane) _MMIO_PLANE(plane, > _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe)) ...here after all the register *offset* definitions, not right after the plane 1 / pipe A register offset macro? Ditto for a bunch of the other changes here. BR, Jani. > + > #define _PLANE_STRIDE_1_A0x70188 > -#define _PLANE_STRIDE_2_A0x70288 > -#define _PLANE_STRIDE_3_A0x70388 > #define PLANE_STRIDE__MASK REG_GENMASK(11, 0) > #define PLANE_STRIDE_(stride) > REG_FIELD_PREP(PLANE_STRIDE__MASK, (stride)) > +#define _PLANE_STRIDE_2_A0x70288 > +#define _PLANE_STRIDE_1_B0x71188 > +#define _PLANE_STRIDE_2_B0x71288 > +#define _PLANE_STRIDE_1(pipe)_PIPE(pipe, _PLANE_STRIDE_1_A, > _PLANE_STRIDE_1_B) > +#define _PLANE_STRIDE_2(pipe)_PIPE(pipe, _PLANE_STRIDE_2_A, > _PLANE_STRIDE_2_B) > +#define PLANE_STRIDE(pipe, plane)_MMIO_PLANE(plane, > _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe)) > + > #define _PLANE_POS_1_A 0x7018c > -#define _PLANE_POS_2_A 0x7028c > -#define _PLANE_POS_3_A 0x7038c > #define PLANE_POS_Y_MASK REG_GENMASK(31, 16) > #define PLANE_POS_Y(y) > REG_FIELD_PREP(PLANE_POS_Y_MASK, (y)) > #define PLANE_POS_X_MASK REG_GENMASK(15, 0) > #define PLANE_POS_X(x) > REG_FIELD_PREP(PLANE_POS_X_MASK, (x)) > +#define _PLANE_POS_2_A 0x7028c > +#define _PLANE_POS_1_B 0x7118c > +#define _PLANE_POS_2_B 0x7128c > +#define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, > _PLANE_POS_1_B) > +#define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, > _PLANE_POS_2_B) > +#define PLANE_POS(pipe, plane) _MMIO_PLANE(plane, > _PLANE_POS_1(pipe), _PLANE_POS_2(pipe)) > + > #define _PLANE_SIZE_1_A 0x70190 > -#define _PLANE_SIZE_2_A 0x70290 > -#define _PLANE_SIZE_3_A 0x70390 > #define PLANE_HEIGHT_MASK REG_GENMASK(31, 16) > #define PLANE_HEIGHT(h) > REG_FIELD_PREP(PLANE_HEIGHT_MASK, (h)) > #define PLANE_WIDTH_MASK REG_GENMASK(15, 0) > #define PLANE_WIDTH(w) > REG_FIELD_PREP(PLANE_WIDTH_MASK, (w)) > +#define _PLANE_SIZE_2_A 0x70290 > +#define _PLANE_SIZE_1_B 0x71190 > +#define _PLANE_SIZE_2_B 0x71290 > +#define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, > _PLANE_SIZE_1_B)
RE: [PATCH v4 4/6] drm/i915/alpm: Add compute config for lobf
> -Original Message-
> From: Hogander, Jouni
> Sent: Monday, May 13, 2024 1:02 PM
> To: Manna, Animesh ; intel-
> g...@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org; Murthy, Arun R
> ; Nikula, Jani
> Subject: Re: [PATCH v4 4/6] drm/i915/alpm: Add compute config for lobf
>
> On Thu, 2024-05-09 at 11:01 +0530, Animesh Manna wrote:
> > Link Off Between Active Frames, is a new feature for eDP that allows
> > the panel to go to lower power state after transmission of data. This
> > is a feature on top of ALPM, AS SDP.
> > Add compute config during atomic-check phase.
> >
> > v1: RFC version.
> > v2: Add separate flag for auxless-alpm. [Jani]
> > v3:
> > - intel_dp->lobf_supported replaced with crtc_state->has_lobf.
> > [Jouni]
> > - Add DISPLAY_VER() check. [Jouni]
> > - Modify function name of get_aux_less_status. [Jani]
> > v4: Add enum alpm_mode to hold the aux-wake/less capability.
> >
> > Signed-off-by: Animesh Manna
> > ---
> > drivers/gpu/drm/i915/display/intel_alpm.c | 58
> > +++
> > drivers/gpu/drm/i915/display/intel_alpm.h | 5 ++
> > .../drm/i915/display/intel_display_types.h | 11
> > drivers/gpu/drm/i915/display/intel_dp.c | 4 ++
> > 4 files changed, 78 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> > b/drivers/gpu/drm/i915/display/intel_alpm.c
> > index ee6c2a959f09..5979eab1f2e0 100644
> > --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> > +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> > @@ -11,6 +11,23 @@
> > #include "intel_dp_aux.h"
> > #include "intel_psr_regs.h"
> >
> > +enum alpm_mode intel_alpm_get_capability(struct intel_dp *intel_dp) {
> > + u8 alpm_caps = 0;
> > +
> > + if (drm_dp_dpcd_readb(_dp->aux, DP_RECEIVER_ALPM_CAP,
> > + _caps) != 1)
> > + return ALPM_INVALID;
> > +
> > + if (alpm_caps & DP_ALPM_CAP)
> > + return ALPM_AUX_WAKE;
> > +
> > + if (alpm_caps & DP_ALPM_AUX_LESS_CAP)
> > + return ALPM_AUX_LESS;
> > +
> > + return ALPM_NOT_SUPPORTED;
> > +}
>
> This will always return ALPM_AUX_WAKE if both are supported. I don't think
> this is what you want?
>
> You could add alpm_dpcd into intel_dp. Then for this purpose add
> aux_wake_supported() and aux_less_wake_supported()?
Ok, will add in next version.
Regards,
Animesh
>
> BR,
>
> Jouni Högander
>
> > +
> > /*
> > * See Bspec: 71632 for the table
> > *
> > @@ -242,6 +259,47 @@ bool intel_alpm_compute_params(struct intel_dp
> > *intel_dp,
> > return true;
> > }
> >
> > +void intel_alpm_compute_lobf_config(struct intel_dp *intel_dp,
> > + struct intel_crtc_state
> > *crtc_state,
> > + struct drm_connector_state
> > *conn_state)
> > +{
> > + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> > + struct drm_display_mode *adjusted_mode = _state-
> > >hw.adjusted_mode;
> > + int waketime_in_lines, first_sdp_position;
> > + int context_latency, guardband;
> > +
> > + if (!intel_dp_is_edp(intel_dp))
> > + return;
> > +
> > + if (DISPLAY_VER(i915) < 20)
> > + return;
> > +
> > + if (!intel_dp_as_sdp_supported(intel_dp))
> > + return;
> > +
> > + if (crtc_state->has_psr)
> > + return;
> > +
> > + if (intel_dp->alpm_parameters.mode == ALPM_INVALID ||
> > + intel_dp->alpm_parameters.mode == ALPM_NOT_SUPPORTED)
> > + return;
> > +
> > + if (!intel_alpm_compute_params(intel_dp, crtc_state))
> > + return;
> > +
> > + context_latency = adjusted_mode->crtc_vblank_start -
> > adjusted_mode->crtc_vdisplay;
> > + guardband = adjusted_mode->crtc_vtotal -
> > + adjusted_mode->crtc_vdisplay - context_latency;
> > + first_sdp_position = adjusted_mode->crtc_vtotal -
> > adjusted_mode->crtc_vsync_start;
> > + if (intel_dp->alpm_parameters.mode == ALPM_AUX_LESS)
> > + waketime_in_lines = intel_dp-
> > >alpm_parameters.io_wake_lines;
> > + else
> > + waketime_in_lines = intel_dp-
> > >alpm_parameters.fast_wake_lines;
> > +
> > + crtc_state->has_lobf = (context_latency + guardband) >
> > + (first_sdp_position + waketime_in_lines); }
> > +
> > static void lnl_alpm_configure(struct intel_dp *intel_dp)
> > {
> > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); diff
> > --git a/drivers/gpu/drm/i915/display/intel_alpm.h
> > b/drivers/gpu/drm/i915/display/intel_alpm.h
> > index c45d078e5a6b..80c8a66b34af 100644
> > --- a/drivers/gpu/drm/i915/display/intel_alpm.h
> > +++ b/drivers/gpu/drm/i915/display/intel_alpm.h
> > @@ -10,9 +10,14 @@
> >
> > struct intel_dp;
> > struct intel_crtc_state;
> > +struct drm_connector_state;
> >
> > +enum alpm_mode intel_alpm_get_capability(struct intel_dp *intel_dp);
>
RE: [PATCH] drm/i915/bmg: Load DMC
> -Original Message-
> From: Intel-xe On Behalf Of
> Gustavo Sousa
> Sent: Friday, May 10, 2024 7:36 PM
> To: intel-gfx@lists.freedesktop.org; intel...@lists.freedesktop.org
> Subject: [PATCH] drm/i915/bmg: Load DMC
>
> Load Battlemage's DMC. We re-use XELPDP_DMC_MAX_FW_SIZE since BMG's
> display is a derivative of Xe_LPD+ and has the same MMIO offset limits.
>
> Signed-off-by: Gustavo Sousa
> ---
Some CI skips/failures are in the CI result and those are not related to this
change.
LGTM.
Reviewed-by: Dnyaneshwar Bhadane
> drivers/gpu/drm/i915/display/intel_dmc.c | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
> b/drivers/gpu/drm/i915/display/intel_dmc.c
> index cbd2ac5671b1..63fccdda56c0 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -115,6 +115,9 @@ static bool dmc_firmware_param_disabled(struct
> drm_i915_private *i915)
> #define XE2LPD_DMC_PATH DMC_PATH(xe2lpd)
> MODULE_FIRMWARE(XE2LPD_DMC_PATH);
>
> +#define BMG_DMC_PATH DMC_PATH(bmg)
> +MODULE_FIRMWARE(BMG_DMC_PATH);
> +
> #define MTL_DMC_PATH DMC_PATH(mtl)
> MODULE_FIRMWARE(MTL_DMC_PATH);
>
> @@ -166,6 +169,9 @@ static const char *dmc_firmware_default(struct
> drm_i915_private *i915, u32 *size
> if (DISPLAY_VER_FULL(i915) == IP_VER(20, 0)) {
> fw_path = XE2LPD_DMC_PATH;
> max_fw_size = XE2LPD_DMC_MAX_FW_SIZE;
> + } else if (DISPLAY_VER_FULL(i915) == IP_VER(14, 1)) {
> + fw_path = BMG_DMC_PATH;
> + max_fw_size = XELPDP_DMC_MAX_FW_SIZE;
> } else if (DISPLAY_VER_FULL(i915) == IP_VER(14, 0)) {
> fw_path = MTL_DMC_PATH;
> max_fw_size = XELPDP_DMC_MAX_FW_SIZE;
> --
> 2.45.0
RE: [PATCH v8 2/7] drm/i915: Add Enable/Disable for CMRR based on VRR state
> -Original Message-
> From: Intel-gfx On Behalf Of Mitul
> Golani
> Sent: Thursday, May 9, 2024 1:28 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Shankar, Uma ; Nikula, Jani
>
> Subject: [PATCH v8 2/7] drm/i915: Add Enable/Disable for CMRR based on VRR
> state
>
> Add CMRR/Fixed Average Vtotal mode enable and disable functions based on
> change in VRR mode of operation.
> When Adaptive Sync Vtotal is enabled, Fixed Average Vtotal mode is disabled
> and vice versa. With this commit setting the stage for subsequent CMRR
> enablement.
>
> --v2:
> - Check pipe active state in cmrr enabling. [Jani]
> - Remove usage of bitwise OR on booleans. [Jani]
> - Revert unrelated changes. [Jani]
> - Update intel_vrr_enable, vrr and cmrr enable conditions. [Jani]
> - Simplify whole if-ladder in intel_vrr_enable. [Jani]
> - Revert patch restructuring mistakes in intel_vrr_get_config. [Jani]
>
> --v3:
> - Check pipe active state in cmrr disabling.[Jani]
> - Correct messed up condition in intel_vrr_enable. [Jani]
>
> --v4:
> - Removing RFC tag.
>
> --v5:
> - CMRR handling in co-existatnce of LRR and DRRS.
>
> --v7:
> - Rebase on top of AS SDP merge.
>
> Signed-off-by: Mitul Golani
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 37 ---
> drivers/gpu/drm/i915/display/intel_vrr.c | 38
> 2 files changed, 56 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 258a78447fba..4a5318ab017d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1020,6 +1020,18 @@ static bool vrr_enabling(const struct
> intel_crtc_state *old_crtc_state,
> vrr_params_changed(old_crtc_state, new_crtc_state))); }
>
Can the below functions be moved from intel_display.c to intel_vrr.c?
Thanks and Regards,
Arun R Murthy
---
> +static bool cmrr_enabling(const struct intel_crtc_state *old_crtc_state,
> + const struct intel_crtc_state *new_crtc_state) {
> + if (!new_crtc_state->hw.active)
> + return false;
> +
> + return is_enabling(cmrr.enable, old_crtc_state, new_crtc_state) ||
> + (new_crtc_state->cmrr.enable &&
> + (new_crtc_state->update_m_n || new_crtc_state->update_lrr
> ||
> + cmrr_params_changed(old_crtc_state, new_crtc_state))); }
> +
> static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state,
> const struct intel_crtc_state *new_crtc_state) { @@ -
> 1032,6 +1044,18 @@ static bool vrr_disabling(const struct intel_crtc_state
> *old_crtc_state,
> vrr_params_changed(old_crtc_state, new_crtc_state))); }
>
> +static bool cmrr_disabling(const struct intel_crtc_state *old_crtc_state,
> +const struct intel_crtc_state *new_crtc_state) {
> + if (!old_crtc_state->hw.active)
> + return false;
> +
> + return is_disabling(cmrr.enable, old_crtc_state, new_crtc_state) ||
> + (old_crtc_state->cmrr.enable &&
> + (new_crtc_state->update_m_n || new_crtc_state->update_lrr
> ||
> + cmrr_params_changed(old_crtc_state, new_crtc_state))); }
> +
> static bool audio_enabling(const struct intel_crtc_state *old_crtc_state,
> const struct intel_crtc_state *new_crtc_state) { @@
> -
> 1053,7 +1077,6 @@ static bool audio_disabling(const struct intel_crtc_state
> *old_crtc_state,
> (old_crtc_state->has_audio &&
>memcmp(old_crtc_state->eld, new_crtc_state->eld,
> MAX_ELD_BYTES) != 0); }
> -
> #undef is_disabling
> #undef is_enabling
>
> @@ -1175,7 +1198,8 @@ static void intel_pre_plane_update(struct
> intel_atomic_state *state,
> intel_atomic_get_new_crtc_state(state, crtc);
> enum pipe pipe = crtc->pipe;
>
> - if (vrr_disabling(old_crtc_state, new_crtc_state)) {
> + if (vrr_disabling(old_crtc_state, new_crtc_state) ||
> + cmrr_disabling(old_crtc_state, new_crtc_state)) {
> intel_vrr_disable(old_crtc_state);
> intel_crtc_update_active_timings(old_crtc_state, false);
> }
> @@ -6767,7 +6791,8 @@ static void commit_pipe_post_planes(struct
> intel_atomic_state *state,
> !intel_crtc_needs_modeset(new_crtc_state))
> skl_detach_scalers(new_crtc_state);
>
> - if (vrr_enabling(old_crtc_state, new_crtc_state))
> + if (vrr_enabling(old_crtc_state, new_crtc_state) ||
> + cmrr_enabling(old_crtc_state, new_crtc_state))
> intel_vrr_enable(new_crtc_state);
> }
>
> @@ -6868,9 +6893,11 @@ static void intel_update_crtc(struct
> intel_atomic_state *state,
>* FIXME Should be synchronized with the start of vblank somehow...
>*/
> if (vrr_enabling(old_crtc_state, new_crtc_state) ||
> -
[PATCH] drm/i915/fbc: Add sizes to info message about reducing fb size
The info message currently does not contain any information, how much the stolen memory size should be increased. [drm] Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS. To be more useful to the user, add the sizes to the message. Signed-off-by: Paul Menzel --- drivers/gpu/drm/i915/display/intel_fbc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index b453fcbd67da..e4a5d251013f 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -801,7 +801,8 @@ static int intel_fbc_alloc_cfb(struct intel_fbc *fbc, goto err_llb; else if (ret > min_limit) drm_info_once(>drm, - "Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n"); + "Reducing the compressed framebuffer size from %d bytes to %d bytes. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n", + min_limit, ret); fbc->limit = ret; -- 2.43.0
Re: [PATCH 12/16] drm/i915: Drop a few unwanted tabs from skl+ plane reg defines
On Fri, 10 May 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > A few extra tabs have snuck into the skl+ plane register bit > definitions. Remove them. > > Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/display/skl_universal_plane_regs.h | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h > b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h > index 8ef9bd50d021..18dbe717ea21 100644 > --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h > @@ -199,17 +199,17 @@ > > #define _PLANE_CUS_CTL_1_A 0x701c8 > #define PLANE_CUS_ENABLE REG_BIT(31) > -#define PLANE_CUS_Y_PLANE_MASK REG_BIT(30) > +#define PLANE_CUS_Y_PLANE_MASK REG_BIT(30) > #define PLANE_CUS_Y_PLANE_4_RKL > REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0) > #define PLANE_CUS_Y_PLANE_5_RKL > REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1) > #define PLANE_CUS_Y_PLANE_6_ICL > REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0) > #define PLANE_CUS_Y_PLANE_7_ICL > REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1) > -#define PLANE_CUS_HPHASE_SIGN_NEGATIVE REG_BIT(19) > +#define PLANE_CUS_HPHASE_SIGN_NEGATIVE REG_BIT(19) > #define PLANE_CUS_HPHASE_MASK REG_GENMASK(17, 16) > #define PLANE_CUS_HPHASE_0 > REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 0) > #define PLANE_CUS_HPHASE_0_25 > REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 1) > #define PLANE_CUS_HPHASE_0_5 > REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 2) > -#define PLANE_CUS_VPHASE_SIGN_NEGATIVE REG_BIT(15) > +#define PLANE_CUS_VPHASE_SIGN_NEGATIVE REG_BIT(15) > #define PLANE_CUS_VPHASE_MASK REG_GENMASK(13, 12) > #define PLANE_CUS_VPHASE_0 > REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 0) > #define PLANE_CUS_VPHASE_0_25 > REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 1) -- Jani Nikula, Intel
Re: [PATCH 11/16] drm/i915: Use REG_BIT for PLANE_WM bits
On Fri, 10 May 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > A couple of PLANE_WM bits were still using the hand > rolled (1< > Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/display/skl_universal_plane_regs.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h > b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h > index 0ad14727e334..8ef9bd50d021 100644 > --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h > @@ -300,8 +300,8 @@ > _MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + (index) * 4, > _PLANE_CSC_POSTOFF_HI_2(pipe) + (index) * 4) > > #define _PLANE_WM_1_A_0 0x70240 > -#define PLANE_WM_EN(1 << 31) > -#define PLANE_WM_IGNORE_LINES (1 << 30) > +#define PLANE_WM_ENREG_BIT(31) > +#define PLANE_WM_IGNORE_LINES REG_BIT(30) > #define PLANE_WM_LINES_MASKREG_GENMASK(26, 14) > #define PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0) > #define _PLANE_WM_1_B_0 0x71240 -- Jani Nikula, Intel
Re: [PATCH 09/16] drm/i915: Drop useless PLANE_FOO_3 register defines
On Fri, 10 May 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > We only need register defines for the first two planes > on the first two pipes. Nuke everything else. > > Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula > --- > .../gpu/drm/i915/display/skl_universal_plane_regs.h | 12 > 1 file changed, 12 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h > b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h > index d0c760e8..0558d97614e1 100644 > --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h > @@ -234,49 +234,38 @@ > > #define _PLANE_CTL_1_B 0x71180 > #define _PLANE_CTL_2_B 0x71280 > -#define _PLANE_CTL_3_B 0x71380 > #define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B) > #define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B) > -#define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B) > #define PLANE_CTL(pipe, plane) \ > _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe)) > > #define _PLANE_STRIDE_1_B0x71188 > #define _PLANE_STRIDE_2_B0x71288 > -#define _PLANE_STRIDE_3_B0x71388 > #define _PLANE_STRIDE_1(pipe)\ > _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B) > #define _PLANE_STRIDE_2(pipe)\ > _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B) > -#define _PLANE_STRIDE_3(pipe)\ > - _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B) > #define PLANE_STRIDE(pipe, plane)\ > _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe)) > > #define _PLANE_POS_1_B 0x7118c > #define _PLANE_POS_2_B 0x7128c > -#define _PLANE_POS_3_B 0x7138c > #define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B) > #define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B) > -#define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B) > #define PLANE_POS(pipe, plane) \ > _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe)) > > #define _PLANE_SIZE_1_B 0x71190 > #define _PLANE_SIZE_2_B 0x71290 > -#define _PLANE_SIZE_3_B 0x71390 > #define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B) > #define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B) > -#define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B) > #define PLANE_SIZE(pipe, plane) \ > _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe)) > > #define _PLANE_SURF_1_B 0x7119c > #define _PLANE_SURF_2_B 0x7129c > -#define _PLANE_SURF_3_B 0x7139c > #define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B) > #define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B) > -#define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B) > #define PLANE_SURF(pipe, plane) \ > _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe)) > > @@ -351,7 +340,6 @@ > > #define _PLANE_COLOR_CTL_1_B 0x711CC > #define _PLANE_COLOR_CTL_2_B 0x712CC > -#define _PLANE_COLOR_CTL_3_B 0x713CC > #define _PLANE_COLOR_CTL_1(pipe) \ > _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B) > #define _PLANE_COLOR_CTL_2(pipe) \ -- Jani Nikula, Intel
Re: [PATCH 08/16] drm/i915/gvt: Use PLANE_CTL and PLANE_SURF defines
On Fri, 10 May 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > Stop hand rolling PLANE_CTL and PLANE_SURF for the third plane > and just use the real thing. > > Cc: Zhenyu Wang > CC: Zhi Wang > Signed-off-by: Ville Syrjälä The original is a baffling mix. Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 12 ++-- > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c > b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c > index b53c98cd6d7f..843bdb46d49c 100644 > --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c > +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c > @@ -1030,12 +1030,12 @@ static int iterate_skl_plus_mmio(struct > intel_gvt_mmio_table_iter *iter) > MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 1)); > MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 2)); > MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 3)); > - MMIO_D(_MMIO(_PLANE_CTL_3_A)); > - MMIO_D(_MMIO(_PLANE_CTL_3_B)); > - MMIO_D(_MMIO(0x72380)); > - MMIO_D(_MMIO(0x7239c)); > - MMIO_D(_MMIO(_PLANE_SURF_3_A)); > - MMIO_D(_MMIO(_PLANE_SURF_3_B)); > + MMIO_D(PLANE_CTL(PIPE_A, 2)); > + MMIO_D(PLANE_CTL(PIPE_B, 2)); > + MMIO_D(PLANE_CTL(PIPE_C, 2)); > + MMIO_D(PLANE_SURF(PIPE_A, 2)); > + MMIO_D(PLANE_SURF(PIPE_B, 2)); > + MMIO_D(PLANE_SURF(PIPE_C, 2)); > MMIO_D(DMC_SSP_BASE); > MMIO_D(DMC_HTP_SKL); > MMIO_D(DMC_LAST_WRITE); -- Jani Nikula, Intel
RE: [PATCH 0/7] Enable Aux Based EDP HDR
> -Original Message- > From: Kandpal, Suraj > Sent: Tuesday, May 7, 2024 9:34 AM > To: intel-gfx@lists.freedesktop.org > Cc: Borah, Chaitanya Kumar ; Shankar, Uma > ; Nautiyal, Ankit K ; > Murthy, Arun R ; Kandpal, Suraj > > Subject: [PATCH 0/7] Enable Aux Based EDP HDR > > This series enables Aux based EDP HDR and backlight controls. > The DPCD written to are intel proprietary and are filled based on the specs > that > were provided to TCON vendors. Merged to drm-intel-next. Thanks for the patches and reviews. Regards, Uma Shankar > Signed-off-by: Suraj Kandpal > > Suraj Kandpal (7): > drm/i915/dp: Make has_gamut_metadata_dip() non static > drm/i915/dp: Rename intel struct inside intel_panel > drm/i915/dp: Add TCON HDR capability checks > drm/i915/dp: Fix Register bit naming > drm/i915/dp: Drop comments on EDP HDR DPCD registers > drm/i915/dp: Enable AUX based backlight for HDR > drm/i915/dp: Write panel override luminance values > > .../drm/i915/display/intel_display_types.h| 7 +- > drivers/gpu/drm/i915/display/intel_dp.c | 6 +- > drivers/gpu/drm/i915/display/intel_dp.h | 1 + > .../drm/i915/display/intel_dp_aux_backlight.c | 149 +++--- > 4 files changed, 140 insertions(+), 23 deletions(-) > > -- > 2.43.2
Re: [PATCH 07/16] drm/i915/gvt: Use the full PLANE_KEY*() defines
On Fri, 10 May 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > Stop hand rolling PLANE_KEY*() register defines and just > use the real thing. > > Cc: Zhenyu Wang > CC: Zhi Wang > Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 18 +- > 1 file changed, 9 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c > b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c > index ad3bf60855bc..b53c98cd6d7f 100644 > --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c > +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c > @@ -1075,15 +1075,15 @@ static int iterate_skl_plus_mmio(struct > intel_gvt_mmio_table_iter *iter) > MMIO_D(_MMIO(0x70034)); > MMIO_D(_MMIO(0x71034)); > MMIO_D(_MMIO(0x72034)); > - MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A))); > - MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B))); > - MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C))); > - MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A))); > - MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B))); > - MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_C))); > - MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A))); > - MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B))); > - MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C))); > + MMIO_D(PLANE_KEYVAL(PIPE_A, 0)); > + MMIO_D(PLANE_KEYVAL(PIPE_B, 0)); > + MMIO_D(PLANE_KEYVAL(PIPE_C, 0)); > + MMIO_D(PLANE_KEYMAX(PIPE_A, 0)); > + MMIO_D(PLANE_KEYMAX(PIPE_B, 0)); > + MMIO_D(PLANE_KEYMAX(PIPE_C, 0)); > + MMIO_D(PLANE_KEYMSK(PIPE_A, 0)); > + MMIO_D(PLANE_KEYMSK(PIPE_B, 0)); > + MMIO_D(PLANE_KEYMSK(PIPE_C, 0)); > MMIO_D(_MMIO(0x44500)); > #define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4) > MMIO_RING_D(CSFE_CHICKEN1_REG); -- Jani Nikula, Intel
Re: [PATCH 06/16] drm/i915/gvt: Use the proper PLANE_AUX_OFFSET() define
On Fri, 10 May 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > Stop hand rolling PLANE_AUX_OFFSET() and just use the real thing. > > Cc: Zhenyu Wang > CC: Zhi Wang > Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/gvt/handlers.c | 24 ++--- > drivers/gpu/drm/i915/gvt/reg.h | 2 -- > drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 24 ++--- > 3 files changed, 24 insertions(+), 26 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gvt/handlers.c > b/drivers/gpu/drm/i915/gvt/handlers.c > index 6b02612ddef5..6f633035618e 100644 > --- a/drivers/gpu/drm/i915/gvt/handlers.c > +++ b/drivers/gpu/drm/i915/gvt/handlers.c > @@ -2693,20 +2693,20 @@ static int init_skl_mmio_info(struct intel_gvt *gvt) > MMIO_DH(PLANE_AUX_DIST(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); > MMIO_DH(PLANE_AUX_DIST(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); > > - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL); > - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL); > - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL); > - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL); > + MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); > + MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); > + MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); > + MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); > > - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL); > - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL); > - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL); > - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL); > + MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); > + MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); > + MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); > + MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); > > - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL); > - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL); > - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL); > - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL); > + MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); > + MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); > + MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); > + MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); > > MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); > > diff --git a/drivers/gpu/drm/i915/gvt/reg.h b/drivers/gpu/drm/i915/gvt/reg.h > index e8a56faafe95..90d8eb1761a3 100644 > --- a/drivers/gpu/drm/i915/gvt/reg.h > +++ b/drivers/gpu/drm/i915/gvt/reg.h > @@ -57,8 +57,6 @@ > > #define VGT_SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _PLANE_STRIDE_2_B) > > -#define _REG_701C4(pipe, plane) (0x701c4 + pipe * 0x1000 + (plane - 1) * > 0x100) > - > #define SKL_FLIP_EVENT(pipe, plane) (PRIMARY_A_FLIP_DONE + (plane) * 3 + > (pipe)) > > #define REG50080_FLIP_TYPE_MASK 0x3 > diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c > b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c > index cf45342a6db0..ad3bf60855bc 100644 > --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c > +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c > @@ -1018,18 +1018,18 @@ static int iterate_skl_plus_mmio(struct > intel_gvt_mmio_table_iter *iter) > MMIO_D(PLANE_AUX_DIST(PIPE_C, 1)); > MMIO_D(PLANE_AUX_DIST(PIPE_C, 2)); > MMIO_D(PLANE_AUX_DIST(PIPE_C, 3)); > - MMIO_D(_MMIO(_REG_701C4(PIPE_A, 1))); > - MMIO_D(_MMIO(_REG_701C4(PIPE_A, 2))); > - MMIO_D(_MMIO(_REG_701C4(PIPE_A, 3))); > - MMIO_D(_MMIO(_REG_701C4(PIPE_A, 4))); > - MMIO_D(_MMIO(_REG_701C4(PIPE_B, 1))); > - MMIO_D(_MMIO(_REG_701C4(PIPE_B, 2))); > - MMIO_D(_MMIO(_REG_701C4(PIPE_B, 3))); > - MMIO_D(_MMIO(_REG_701C4(PIPE_B, 4))); > - MMIO_D(_MMIO(_REG_701C4(PIPE_C, 1))); > - MMIO_D(_MMIO(_REG_701C4(PIPE_C, 2))); > - MMIO_D(_MMIO(_REG_701C4(PIPE_C, 3))); > - MMIO_D(_MMIO(_REG_701C4(PIPE_C, 4))); > + MMIO_D(PLANE_AUX_OFFSET(PIPE_A, 0)); > + MMIO_D(PLANE_AUX_OFFSET(PIPE_A, 1)); > + MMIO_D(PLANE_AUX_OFFSET(PIPE_A, 2)); > + MMIO_D(PLANE_AUX_OFFSET(PIPE_A, 3)); > + MMIO_D(PLANE_AUX_OFFSET(PIPE_B, 0)); > + MMIO_D(PLANE_AUX_OFFSET(PIPE_B, 1)); > + MMIO_D(PLANE_AUX_OFFSET(PIPE_B, 2)); > + MMIO_D(PLANE_AUX_OFFSET(PIPE_B, 3)); > + MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 0)); > + MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 1)); > + MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 2)); > + MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 3)); > MMIO_D(_MMIO(_PLANE_CTL_3_A)); > MMIO_D(_MMIO(_PLANE_CTL_3_B)); > MMIO_D(_MMIO(0x72380)); -- Jani Nikula, Intel
Re: [PATCH 05/16] drm/i915/gvt: Use the proper PLANE_AUX_DIST() define
On Fri, 10 May 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > Stop hand rolling PLANE_AUX_DIST() and just use the real thing. > > Cc: Zhenyu Wang > CC: Zhi Wang > Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/gvt/handlers.c | 24 ++--- > drivers/gpu/drm/i915/gvt/reg.h | 1 - > drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 24 ++--- > 3 files changed, 24 insertions(+), 25 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gvt/handlers.c > b/drivers/gpu/drm/i915/gvt/handlers.c > index 6c857beb5083..6b02612ddef5 100644 > --- a/drivers/gpu/drm/i915/gvt/handlers.c > +++ b/drivers/gpu/drm/i915/gvt/handlers.c > @@ -2678,20 +2678,20 @@ static int init_skl_mmio_info(struct intel_gvt *gvt) > MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); > MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); > > - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL); > - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL); > - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL); > - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL); > + MMIO_DH(PLANE_AUX_DIST(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); > + MMIO_DH(PLANE_AUX_DIST(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); > + MMIO_DH(PLANE_AUX_DIST(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); > + MMIO_DH(PLANE_AUX_DIST(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); > > - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL); > - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL); > - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL); > - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL); > + MMIO_DH(PLANE_AUX_DIST(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); > + MMIO_DH(PLANE_AUX_DIST(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); > + MMIO_DH(PLANE_AUX_DIST(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); > + MMIO_DH(PLANE_AUX_DIST(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); > > - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL); > - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL); > - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL); > - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL); > + MMIO_DH(PLANE_AUX_DIST(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); > + MMIO_DH(PLANE_AUX_DIST(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); > + MMIO_DH(PLANE_AUX_DIST(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); > + MMIO_DH(PLANE_AUX_DIST(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); > > MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL); > MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL); > diff --git a/drivers/gpu/drm/i915/gvt/reg.h b/drivers/gpu/drm/i915/gvt/reg.h > index d8216c63c39a..e8a56faafe95 100644 > --- a/drivers/gpu/drm/i915/gvt/reg.h > +++ b/drivers/gpu/drm/i915/gvt/reg.h > @@ -57,7 +57,6 @@ > > #define VGT_SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _PLANE_STRIDE_2_B) > > -#define _REG_701C0(pipe, plane) (0x701c0 + pipe * 0x1000 + (plane - 1) * > 0x100) > #define _REG_701C4(pipe, plane) (0x701c4 + pipe * 0x1000 + (plane - 1) * > 0x100) > > #define SKL_FLIP_EVENT(pipe, plane) (PRIMARY_A_FLIP_DONE + (plane) * 3 + > (pipe)) > diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c > b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c > index 3b79c1c84b79..cf45342a6db0 100644 > --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c > +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c > @@ -1006,18 +1006,18 @@ static int iterate_skl_plus_mmio(struct > intel_gvt_mmio_table_iter *iter) > MMIO_D(PLANE_NV12_BUF_CFG(PIPE_C, 1)); > MMIO_D(PLANE_NV12_BUF_CFG(PIPE_C, 2)); > MMIO_D(PLANE_NV12_BUF_CFG(PIPE_C, 3)); > - MMIO_D(_MMIO(_REG_701C0(PIPE_A, 1))); > - MMIO_D(_MMIO(_REG_701C0(PIPE_A, 2))); > - MMIO_D(_MMIO(_REG_701C0(PIPE_A, 3))); > - MMIO_D(_MMIO(_REG_701C0(PIPE_A, 4))); > - MMIO_D(_MMIO(_REG_701C0(PIPE_B, 1))); > - MMIO_D(_MMIO(_REG_701C0(PIPE_B, 2))); > - MMIO_D(_MMIO(_REG_701C0(PIPE_B, 3))); > - MMIO_D(_MMIO(_REG_701C0(PIPE_B, 4))); > - MMIO_D(_MMIO(_REG_701C0(PIPE_C, 1))); > - MMIO_D(_MMIO(_REG_701C0(PIPE_C, 2))); > - MMIO_D(_MMIO(_REG_701C0(PIPE_C, 3))); > - MMIO_D(_MMIO(_REG_701C0(PIPE_C, 4))); > + MMIO_D(PLANE_AUX_DIST(PIPE_A, 0)); > + MMIO_D(PLANE_AUX_DIST(PIPE_A, 1)); > + MMIO_D(PLANE_AUX_DIST(PIPE_A, 2)); > + MMIO_D(PLANE_AUX_DIST(PIPE_A, 3)); > + MMIO_D(PLANE_AUX_DIST(PIPE_B, 0)); > + MMIO_D(PLANE_AUX_DIST(PIPE_B, 1)); > + MMIO_D(PLANE_AUX_DIST(PIPE_B, 2)); > + MMIO_D(PLANE_AUX_DIST(PIPE_B, 3)); > + MMIO_D(PLANE_AUX_DIST(PIPE_C, 0)); > + MMIO_D(PLANE_AUX_DIST(PIPE_C, 1)); > + MMIO_D(PLANE_AUX_DIST(PIPE_C, 2)); > + MMIO_D(PLANE_AUX_DIST(PIPE_C, 3)); > MMIO_D(_MMIO(_REG_701C4(PIPE_A, 1))); > MMIO_D(_MMIO(_REG_701C4(PIPE_A, 2))); >
Re: [PATCH 04/16] drm/i915: Move skl+ wm/ddb registers to proper headers
On Fri, 10 May 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > On SKL+ the watermark/DDB registers are proper per-plane > registers. Move the definitons to their respective files. > > Cc: Zhenyu Wang > CC: Zhi Wang > Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula > --- > .../gpu/drm/i915/display/intel_cursor_regs.h | 20 + > .../i915/display/skl_universal_plane_regs.h | 64 ++ > drivers/gpu/drm/i915/display/skl_watermark.c | 1 + > .../gpu/drm/i915/display/skl_watermark_regs.h | 83 --- > drivers/gpu/drm/i915/gvt/handlers.c | 1 + > 5 files changed, 86 insertions(+), 83 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h > b/drivers/gpu/drm/i915/display/intel_cursor_regs.h > index 62f7fb5c3f10..a478ef5787c5 100644 > --- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h > @@ -75,4 +75,24 @@ > #define CUR_CHICKEN(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_CHICKEN_A) > #define CURSURFLIVE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASURFLIVE) > > +/* skl+ */ > +#define _CUR_WM_A_0 0x70140 > +#define _CUR_WM_B_0 0x71140 > +#define _CUR_WM_SAGV_A 0x70158 > +#define _CUR_WM_SAGV_B 0x71158 > +#define _CUR_WM_SAGV_TRANS_A 0x7015C > +#define _CUR_WM_SAGV_TRANS_B 0x7115C > +#define _CUR_WM_TRANS_A 0x70168 > +#define _CUR_WM_TRANS_B 0x71168 > +#define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0) > +#define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level))) > +#define CUR_WM_SAGV(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_A, _CUR_WM_SAGV_B) > +#define CUR_WM_SAGV_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_TRANS_A, > _CUR_WM_SAGV_TRANS_B) > +#define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A, _CUR_WM_TRANS_B) > + > +/* skl+ */ > +#define _CUR_BUF_CFG_A 0x7017c > +#define _CUR_BUF_CFG_B 0x7117c > +#define CUR_BUF_CFG(pipe)_MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B) > + > #endif /* __INTEL_CURSOR_REGS_H__ */ > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h > b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h > index 7e34470beb74..d0c760e8 100644 > --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h > @@ -402,4 +402,68 @@ > (index) * 4, > _PLANE_CSC_POSTOFF_HI_2(pipe) + \ > (index) * 4) > > +#define _PLANE_WM_1_A_0 0x70240 > +#define _PLANE_WM_1_B_0 0x71240 > +#define _PLANE_WM_2_A_0 0x70340 > +#define _PLANE_WM_2_B_0 0x71340 > +#define _PLANE_WM_SAGV_1_A 0x70258 > +#define _PLANE_WM_SAGV_1_B 0x71258 > +#define _PLANE_WM_SAGV_2_A 0x70358 > +#define _PLANE_WM_SAGV_2_B 0x71358 > +#define _PLANE_WM_SAGV_TRANS_1_A 0x7025C > +#define _PLANE_WM_SAGV_TRANS_1_B 0x7125C > +#define _PLANE_WM_SAGV_TRANS_2_A 0x7035C > +#define _PLANE_WM_SAGV_TRANS_2_B 0x7135C > +#define _PLANE_WM_TRANS_1_A 0x70268 > +#define _PLANE_WM_TRANS_1_B 0x71268 > +#define _PLANE_WM_TRANS_2_A 0x70368 > +#define _PLANE_WM_TRANS_2_B 0x71368 > +#define PLANE_WM_EN(1 << 31) > +#define PLANE_WM_IGNORE_LINES (1 << 30) > +#define PLANE_WM_LINES_MASKREG_GENMASK(26, 14) > +#define PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0) > + > +#define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0) > +#define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0) > +#define _PLANE_WM_BASE(pipe, plane) \ > + _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe)) > +#define PLANE_WM(pipe, plane, level) \ > + _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level))) > +#define _PLANE_WM_SAGV_1(pipe) \ > + _PIPE(pipe, _PLANE_WM_SAGV_1_A, _PLANE_WM_SAGV_1_B) > +#define _PLANE_WM_SAGV_2(pipe) \ > + _PIPE(pipe, _PLANE_WM_SAGV_2_A, _PLANE_WM_SAGV_2_B) > +#define PLANE_WM_SAGV(pipe, plane) \ > + _MMIO(_PLANE(plane, _PLANE_WM_SAGV_1(pipe), _PLANE_WM_SAGV_2(pipe))) > +#define _PLANE_WM_SAGV_TRANS_1(pipe) \ > + _PIPE(pipe, _PLANE_WM_SAGV_TRANS_1_A, _PLANE_WM_SAGV_TRANS_1_B) > +#define _PLANE_WM_SAGV_TRANS_2(pipe) \ > + _PIPE(pipe, _PLANE_WM_SAGV_TRANS_2_A, _PLANE_WM_SAGV_TRANS_2_B) > +#define PLANE_WM_SAGV_TRANS(pipe, plane) \ > + _MMIO(_PLANE(plane, _PLANE_WM_SAGV_TRANS_1(pipe), > _PLANE_WM_SAGV_TRANS_2(pipe))) > +#define _PLANE_WM_TRANS_1(pipe) \ > + _PIPE(pipe, _PLANE_WM_TRANS_1_A, _PLANE_WM_TRANS_1_B) > +#define _PLANE_WM_TRANS_2(pipe) \ > + _PIPE(pipe, _PLANE_WM_TRANS_2_A, _PLANE_WM_TRANS_2_B) > +#define PLANE_WM_TRANS(pipe, plane) \ > + _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe))) > + > +#define _PLANE_BUF_CFG_1_B 0x7127c > +#define
Re: [PATCH 03/16] drm/i915: Extract intel_cursor_regs.h
On Fri, 10 May 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > Move most cursor register definitions into their own file. > Declutters i915_reg.h a bit more. > > Cc: Zhenyu Wang > CC: Zhi Wang > Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/display/intel_cursor.c | 1 + > .../gpu/drm/i915/display/intel_cursor_regs.h | 78 +++ > drivers/gpu/drm/i915/display/intel_display.c | 1 + > drivers/gpu/drm/i915/display/intel_psr.c | 1 + > drivers/gpu/drm/i915/gvt/display.c| 1 + > drivers/gpu/drm/i915/gvt/fb_decoder.c | 1 + > drivers/gpu/drm/i915/i915_reg.h | 70 - > drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 1 + > 8 files changed, 84 insertions(+), 70 deletions(-) > create mode 100644 drivers/gpu/drm/i915/display/intel_cursor_regs.h > > diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c > b/drivers/gpu/drm/i915/display/intel_cursor.c > index 2118b87ccb10..d2b459634732 100644 > --- a/drivers/gpu/drm/i915/display/intel_cursor.c > +++ b/drivers/gpu/drm/i915/display/intel_cursor.c > @@ -14,6 +14,7 @@ > #include "intel_atomic.h" > #include "intel_atomic_plane.h" > #include "intel_cursor.h" > +#include "intel_cursor_regs.h" > #include "intel_de.h" > #include "intel_display.h" > #include "intel_display_types.h" > diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h > b/drivers/gpu/drm/i915/display/intel_cursor_regs.h > new file mode 100644 > index ..62f7fb5c3f10 > --- /dev/null > +++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h > @@ -0,0 +1,78 @@ > +/* SPDX-License-Identifier: MIT */ > +/* > + * Copyright © 2024 Intel Corporation > + */ > + > +#ifndef __INTEL_CURSOR_REGS_H__ > +#define __INTEL_CURSOR_REGS_H__ > + > +#include "intel_display_reg_defs.h" > + > +#define _CURACNTR0x70080 > +/* Old style CUR*CNTR flags (desktop 8xx) */ > +#define CURSOR_ENABLE REG_BIT(31) > +#define CURSOR_PIPE_GAMMA_ENABLE REG_BIT(30) > +#define CURSOR_STRIDE_MASK REG_GENMASK(29, 28) > +#define CURSOR_STRIDE(stride) REG_FIELD_PREP(CURSOR_STRIDE_MASK, > ffs(stride) - 9) /* 256,512,1k,2k */ > +#define CURSOR_FORMAT_MASK REG_GENMASK(26, 24) > +#define CURSOR_FORMAT_2C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 0) > +#define CURSOR_FORMAT_3C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 1) > +#define CURSOR_FORMAT_4C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 2) > +#define CURSOR_FORMAT_ARGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 4) > +#define CURSOR_FORMAT_XRGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 5) > +/* New style CUR*CNTR flags */ > +#define MCURSOR_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */ > +#define MCURSOR_ARB_SLOTS(x) > REG_FIELD_PREP(MCURSOR_ARB_SLOTS_MASK, (x)) /* icl+ */ > +#define MCURSOR_PIPE_SEL_MASK REG_GENMASK(29, 28) > +#define MCURSOR_PIPE_SEL(pipe) REG_FIELD_PREP(MCURSOR_PIPE_SEL_MASK, > (pipe)) > +#define MCURSOR_PIPE_GAMMA_ENABLE REG_BIT(26) > +#define MCURSOR_PIPE_CSC_ENABLEREG_BIT(24) /* ilk+ */ > +#define MCURSOR_ROTATE_180 REG_BIT(15) > +#define MCURSOR_TRICKLE_FEED_DISABLE REG_BIT(14) > +#define MCURSOR_MODE_MASK 0x27 > +#define MCURSOR_MODE_DISABLE 0x00 > +#define MCURSOR_MODE_128_32B_AX0x02 > +#define MCURSOR_MODE_256_32B_AX0x03 > +#define MCURSOR_MODE_64_2B 0x04 > +#define MCURSOR_MODE_64_32B_AX 0x07 > +#define MCURSOR_MODE_128_ARGB_AX (0x20 | MCURSOR_MODE_128_32B_AX) > +#define MCURSOR_MODE_256_ARGB_AX (0x20 | MCURSOR_MODE_256_32B_AX) > +#define MCURSOR_MODE_64_ARGB_AX(0x20 | MCURSOR_MODE_64_32B_AX) > +#define _CURABASE0x70084 > +#define _CURAPOS 0x70088 > +#define _CURAPOS_ERLY_TPT0x7008c > +#define CURSOR_POS_Y_SIGN REG_BIT(31) > +#define CURSOR_POS_Y_MASK REG_GENMASK(30, 16) > +#define CURSOR_POS_Y(y)REG_FIELD_PREP(CURSOR_POS_Y_MASK, (y)) > +#define CURSOR_POS_X_SIGN REG_BIT(15) > +#define CURSOR_POS_X_MASK REG_GENMASK(14, 0) > +#define CURSOR_POS_X(x)REG_FIELD_PREP(CURSOR_POS_X_MASK, (x)) > +#define _CURASIZE0x700a0 /* 845/865 */ > +#define CURSOR_HEIGHT_MASK REG_GENMASK(21, 12) > +#define CURSOR_HEIGHT(h) REG_FIELD_PREP(CURSOR_HEIGHT_MASK, (h)) > +#define CURSOR_WIDTH_MASK REG_GENMASK(9, 0) > +#define CURSOR_WIDTH(w)REG_FIELD_PREP(CURSOR_WIDTH_MASK, (w)) > +#define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */ > +#define CUR_FBC_EN REG_BIT(31) > +#define CUR_FBC_HEIGHT_MASKREG_GENMASK(7, 0) > +#define CUR_FBC_HEIGHT(h) REG_FIELD_PREP(CUR_FBC_HEIGHT_MASK, (h)) > +#define _CUR_CHICKEN_A 0x700a4 /* mtl+ */ > +#define _CURASURFLIVE0x700ac /* g4x+ */ > +#define _CURBCNTR0x700c0 > +#define _CURBBASE0x700c4
Re: [PATCH 02/16] drm/i915: Extract skl_universal_plane_regs.h
On Fri, 10 May 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Move most of the SKL+ universal plane register definitions
> into their own file. Declutters i915_reg.h a bit more.
>
> Cc: Zhenyu Wang
> CC: Zhi Wang
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 1 +
> .../gpu/drm/i915/display/intel_dpt_common.c | 1 +
> .../drm/i915/display/skl_universal_plane.c| 1 +
> .../i915/display/skl_universal_plane_regs.h | 405 ++
> drivers/gpu/drm/i915/display/skl_watermark.c | 1 +
> drivers/gpu/drm/i915/gvt/dmabuf.c | 3 +-
> drivers/gpu/drm/i915/gvt/fb_decoder.c | 1 +
> drivers/gpu/drm/i915/gvt/handlers.c | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 395 -
> drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 1 +
> 10 files changed, 414 insertions(+), 396 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index ef986b508431..a2c331c696fe 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -119,6 +119,7 @@
> #include "intel_wm.h"
> #include "skl_scaler.h"
> #include "skl_universal_plane.h"
> +#include "skl_universal_plane_regs.h"
> #include "skl_watermark.h"
> #include "vlv_dpio_phy_regs.h"
> #include "vlv_dsi.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_dpt_common.c
> b/drivers/gpu/drm/i915/display/intel_dpt_common.c
> index cdba47165c04..573f72068899 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpt_common.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpt_common.c
> @@ -7,6 +7,7 @@
> #include "intel_de.h"
> #include "intel_display_types.h"
> #include "intel_dpt_common.h"
> +#include "skl_universal_plane_regs.h"
>
> void intel_dpt_configure(struct intel_crtc *crtc)
> {
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 0a8e781a3648..ab560820bb23 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -21,6 +21,7 @@
> #include "intel_psr_regs.h"
> #include "skl_scaler.h"
> #include "skl_universal_plane.h"
> +#include "skl_universal_plane_regs.h"
> #include "skl_watermark.h"
> #include "pxp/intel_pxp.h"
>
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> new file mode 100644
> index ..7e34470beb74
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> @@ -0,0 +1,405 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2024 Intel Corporation
> + */
> +
> +#ifndef __SKL_UNIVERSAL_PLANE_REGS_H__
> +#define __SKL_UNIVERSAL_PLANE_REGS_H__
> +
> +#include "intel_display_reg_defs.h"
> +
> +#define _PLANE_CTL_1_A 0x70180
> +#define _PLANE_CTL_2_A 0x70280
> +#define _PLANE_CTL_3_A 0x70380
> +#define PLANE_CTL_ENABLE REG_BIT(31)
> +#define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */
> +#define PLANE_CTL_ARB_SLOTS(x)
> REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */
> +#define PLANE_CTL_PIPE_GAMMA_ENABLEREG_BIT(30) /* Pre-GLK
> */
> +#define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
> +/*
> + * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition
> + * expanded to include bit 23 as well. However, the shift-24 based values
> + * correctly map to the same formats in ICL, as long as bit 23 is set to 0
> + */
> +#define PLANE_CTL_FORMAT_MASK_SKL REG_GENMASK(27, 24) /* pre-icl
> */
> +#define PLANE_CTL_FORMAT_MASK_ICL REG_GENMASK(27, 23) /* icl+ */
> +#define PLANE_CTL_FORMAT_YUV422
> REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 0)
> +#define PLANE_CTL_FORMAT_NV12
> REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 1)
> +#define PLANE_CTL_FORMAT_XRGB_2101010
> REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 2)
> +#define PLANE_CTL_FORMAT_P010
> REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 3)
> +#define PLANE_CTL_FORMAT_XRGB_
> REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 4)
> +#define PLANE_CTL_FORMAT_P012
> REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 5)
> +#define PLANE_CTL_FORMAT_XRGB_16161616F
> REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 6)
> +#define PLANE_CTL_FORMAT_P016
> REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 7)
> +#define PLANE_CTL_FORMAT_XYUV
> REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 8)
> +#define PLANE_CTL_FORMAT_INDEXED
>
Re: [PATCH 01/16] drm/i915: Nuke _MMIO_PLANE_GAMC()
On Fri, 10 May 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> _MMIO_PLANE_GAMC() is some leftover macro that is never used.
> Get rid of it.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 256d73c25701..0f4a2d542d81 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5151,8 +5151,6 @@ enum skl_power_gate {
> #define WM_DBG_DISALLOW_MAXFIFO (1 << 1)
> #define WM_DBG_DISALLOW_SPRITE (1 << 2)
>
> -#define _MMIO_PLANE_GAMC(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) * 4)
> -
> /* Plane CSC Registers */
> #define _PLANE_CSC_RY_GY_1_A 0x70210
> #define _PLANE_CSC_RY_GY_2_A 0x70310
--
Jani Nikula, Intel
Re: ✗ Fi.CI.IGT: failure for drm/i915/gt: Disarm breadcrumbs if engines are already idle (rev4)
On Friday, 10 May 2024 08:12:02 GMT+2 Patchwork wrote: > == Series Details == > > Series: drm/i915/gt: Disarm breadcrumbs if engines are already idle (rev4) > URL : https://patchwork.freedesktop.org/series/132786/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_14738_full -> Patchwork_132786v4_full > > > Summary > --- > > **FAILURE** > > Serious unknown changes coming with Patchwork_132786v4_full absolutely need > to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_132786v4_full, please notify your bug team > (i915-ci-in...@lists.freedesktop.org) to allow them > to document this new failure mode, which will reduce false positives in CI. > > > > Participating hosts (9 -> 10) > -- > > Additional (1): shard-snb-0 > > Possible new issues > --- > > Here are the unknown changes that may have been introduced in > Patchwork_132786v4_full: > > ### IGT changes ### > > Possible regressions > > * igt@core_getversion@basic: > - shard-glk: NOTRUN -> [CRASH][1] >[1]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132786v4/shard-glk6/igt@core_getvers...@basic.html Reported for all post-merge runs by all machines since IGT_7841 / CI_DRM_14731, fixed in CI_DRM_14749 -- not a regression caused by my patch. > > * igt@device_reset@cold-reset-bound: > - shard-dg2: NOTRUN -> [SKIP][2] >[2]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132786v4/shard-dg2-6/igt@device_re...@cold-reset-bound.html Always skips, on all machines, at least recently, since IGT_7828 till IGT_7847: https://intel-gfx-ci.01.org/tree/drm-tip/igt@device_re...@cold-reset-bound.html I have no idea why this has been reported as a regression. > > * igt@kms_atomic@plane-immutable-zpos@pipe-a-edp-1: > - shard-mtlp: [PASS][3] -> [FAIL][4] >[3]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14738/shard-mtlp-1/igt@kms_atomic@plane-immutable-z...@pipe-a-edp-1.html >[4]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132786v4/shard-mtlp-4/igt@kms_atomic@plane-immutable-z...@pipe-a-edp-1.html The same happened already twice for recent post-merge runs, runconfigs CI_DRM_14743 and CI_DRM_14749: https://gfx-ci.igk.intel.com/cibuglog-ng/testresult/1778568997 https://gfx-ci.igk.intel.com/cibuglog-ng/testresult/1779321094 Not a regression caused by my patch. i915-ci-in...@lists.freedesktop.org, please update filters and re-report. Thanks, Janusz > > > Known issues > > > Here are the changes found in Patchwork_132786v4_full that come from known > issues: > > ### IGT changes ### > > Issues hit > > * igt@api_intel_bb@blit-reloc-purge-cache: > - shard-rkl: NOTRUN -> [SKIP][5] ([i915#8411]) >[5]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132786v4/shard-rkl-6/igt@api_intel...@blit-reloc-purge-cache.html > > * igt@drm_fdinfo@busy-idle-check-all@vcs1: > - shard-dg1: NOTRUN -> [SKIP][6] ([i915#8414]) +9 other tests > skip >[6]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132786v4/shard-dg1-18/igt@drm_fdinfo@busy-idle-check-...@vcs1.html > > * igt@drm_fdinfo@isolation@rcs0: > - shard-mtlp: NOTRUN -> [SKIP][7] ([i915#8414]) +5 other tests > skip >[7]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132786v4/shard-mtlp-4/igt@drm_fdinfo@isolat...@rcs0.html > > * igt@drm_fdinfo@most-busy-idle-check-all@rcs0: > - shard-rkl: NOTRUN -> [FAIL][8] ([i915#7742]) >[8]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132786v4/shard-rkl-6/igt@drm_fdinfo@most-busy-idle-check-...@rcs0.html > > * igt@drm_fdinfo@virtual-busy-idle-all: > - shard-dg2: NOTRUN -> [SKIP][9] ([i915#8414]) >[9]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132786v4/shard-dg2-6/igt@drm_fdi...@virtual-busy-idle-all.html > > * igt@drm_fdinfo@virtual-idle: > - shard-rkl: [PASS][10] -> [FAIL][11] ([i915#7742]) >[10]: > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14738/shard-rkl-4/igt@drm_fdi...@virtual-idle.html >[11]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132786v4/shard-rkl-4/igt@drm_fdi...@virtual-idle.html > > * igt@gem_ccs@block-copy-compressed: > - shard-dg1: NOTRUN -> [SKIP][12] ([i915#3555] / [i915#9323]) >[12]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132786v4/shard-dg1-18/igt@gem_...@block-copy-compressed.html > > * igt@gem_ccs@block-multicopy-inplace: > - shard-rkl: NOTRUN -> [SKIP][13] ([i915#3555] / [i915#9323]) >[13]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132786v4/shard-rkl-5/igt@gem_...@block-multicopy-inplace.html > > * igt@gem_ccs@suspend-resume: > - shard-rkl:
Re: ✗ Fi.CI.IGT: failure for Documentation/i915: remove kernel-doc for DMC wakelocks
Hi,
There is no way that the tests that are failing in the shards have
anything to do with the small documentation change that is in my patch.
Can you please re-report?
Thanks!
--
Cheers,
Luca.
On Sat, 2024-05-11 at 01:02 +, Patchwork wrote:
> Patch Details
> Series:Documentation/i915: remove kernel-doc for DMC wakelocks
> URL:https://patchwork.freedesktop.org/series/133435/
> State:failure
> Details:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133435v1/index.html
> CI Bug Log - changes from CI_DRM_14746_full ->
> Patchwork_133435v1_fullSummaryFAILURE
> Serious unknown changes coming with Patchwork_133435v1_full
> absolutely need to be
> verified manually.
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_133435v1_full, please notify your bug team
> ('i915-ci-in...@lists.freedesktop.org') to allow them
> to document this new failure mode, which will reduce false positives
> in CI.
> Participating hosts (9 -> 9)No changes in participating hosts
> Possible new issuesHere are the unknown changes that may have been introduced
> in
> Patchwork_133435v1_full:
> IGT changesPossible regressions * igt@gem_eio@in-flight-10ms:shard-dg1:
> NOTRUN -> INCOMPLETE
> * igt@kms_flip@flip-vs-panning-vs-hang@c-hdmi-a1:shard-glk: NOTRUN ->
>INCOMPLETE
> Known issuesHere are the changes found in Patchwork_133435v1_full that come
> from
> known issues:
> IGT changesIssues hit * igt@debugfs_test@basic-hwmon:shard-rkl: NOTRUN ->
> SKIP (i915#9318)
> * igt@drm_fdinfo@busy-idle@vcs1:shard-dg1: NOTRUN -> SKIP (i915#8414)
>+4 other tests skip
> * igt@gem_bad_reloc@negative-reloc-bltcopy:shard-dg2: NOTRUN -> SKIP
>(i915#3281) +1 other test skip
> * igt@gem_ccs@block-multicopy-compressed:shard-rkl: NOTRUN -> SKIP
>(i915#9323)
> * igt@gem_ccs@suspend-resume:shard-dg1: NOTRUN -> SKIP (i915#9323) +1
>other test skip
> * igt@gem_ctx_persistence@heartbeat-close:shard-dg1: NOTRUN -> SKIP
>(i915#8555)
> * igt@gem_ctx_sseu@engines:shard-dg2: NOTRUN -> SKIP (i915#280)
> * igt@gem_ctx_sseu@mmap-args:shard-tglu: NOTRUN -> SKIP (i915#280)
> * igt@gem_exec_balancer@bonded-sync:shard-dg1: NOTRUN -> SKIP
>(i915#4771)
> * igt@gem_exec_balancer@parallel-bb-first:shard-rkl: NOTRUN -> SKIP
>(i915#4525)
> * igt@gem_exec_fair@basic-pace:shard-dg1: NOTRUN -> SKIP (i915#3539)
> * igt@gem_exec_fair@basic-pace@rcs0:shard-rkl: PASS -> FAIL
>(i915#2842) +2 other tests fail
> * igt@gem_exec_fence@submit67:shard-dg2: NOTRUN -> SKIP (i915#4812)
> * igt@gem_exec_flush@basic-batch-kernel-default-wb:shard-dg1: NOTRUN -
>> SKIP (i915#3539 / i915#4852) +2 other tests skip
> * igt@gem_exec_flush@basic-uc-pro-default:shard-dg2: NOTRUN -> SKIP
>(i915#3539 / i915#4852)
> * igt@gem_exec_reloc@basic-gtt-wc-active:shard-rkl: NOTRUN -> SKIP
>(i915#3281) +6 other tests skip
> * igt@gem_exec_reloc@basic-wc-gtt-noreloc:shard-dg1: NOTRUN -> SKIP
>(i915#3281) +3 other tests skip
> * igt@gem_fence_thrash@bo-copy:shard-dg2: NOTRUN -> SKIP (i915#4860)
>+1 other test skip
> * igt@gem_lmem_swapping@heavy-verify-multi-ccs:shard-mtlp: NOTRUN ->
>SKIP (i915#4613)
> * igt@gem_lmem_swapping@heavy-verify-random-ccs@lmem0:shard-dg2: PASS
>-> FAIL (i915#10378)
> * igt@gem_lmem_swapping@heavy-verify-random@lmem0:shard-dg1: PASS ->
>INCOMPLETE (i915#10317 / i915#1982)
> * igt@gem_lmem_swapping@massive:shard-tglu: NOTRUN -> SKIP (i915#4613)
> * igt@gem_lmem_swapping@parallel-multi:shard-rkl: NOTRUN -> SKIP
>(i915#4613) +2 other tests skip
> * igt@gem_lmem_swapping@random:shard-glk: NOTRUN -> SKIP (i915#4613)
> * igt@gem_lmem_swapping@smem-oom@lmem0:shard-dg2: PASS -> TIMEOUT
>(i915#5493)
> * igt@gem_mmap_gtt@basic-small-copy-odd:shard-dg1: NOTRUN -> SKIP
>(i915#4077) +5 other tests skip
> * igt@gem_mmap_gtt@basic-write-read-distinct:shard-dg2: NOTRUN -> SKIP
>(i915#4077) +1 other test skip
> * igt@gem_mmap_wc@write-read:shard-dg1: NOTRUN -> SKIP (i915#4083) +4
>other tests skip
> * igt@gem_partial_pwrite_pread@writes-after-reads-display:shard-dg2:
>NOTRUN -> SKIP (i915#3282) +2 other tests skip
> * igt@gem_pxp@reject-modify-context-protection-off-3:shard-dg1: NOTRUN
>-> SKIP (i915#4270) +2 other tests skip
> * igt@gem_pxp@verify-pxp-execution-after-suspend-resume:shard-dg2:
>NOTRUN -> SKIP (i915#4270)
> * igt@gem_pxp@verify-pxp-stale-buf-optout-execution:shard-rkl: NOTRUN
>-> SKIP (i915#4270) +2 other tests skip
> * igt@gem_readwrite@read-bad-handle:shard-rkl: NOTRUN -> SKIP
>(i915#3282) +4 other tests skip
> * igt@gem_readwrite@write-bad-handle:shard-dg1: NOTRUN -> SKIP
>(i915#3282)
> * igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled:shard-dg2:
>NOTRUN -> SKIP (i915#5190 / i915#8428) +1 other test skip
> * igt@gem_unfence_active_buffers:shard-dg1: NOTRUN -> SKIP (i915#4879)
> * igt@gem_userptr_blits@dmabuf-unsync:shard-dg1: NOTRUN -> SKIP
>(i915#3297)
> *
Re: [PATCH v4 4/6] drm/i915/alpm: Add compute config for lobf
On Thu, 2024-05-09 at 11:01 +0530, Animesh Manna wrote:
> Link Off Between Active Frames, is a new feature for eDP
> that allows the panel to go to lower power state after
> transmission of data. This is a feature on top of ALPM, AS SDP.
> Add compute config during atomic-check phase.
>
> v1: RFC version.
> v2: Add separate flag for auxless-alpm. [Jani]
> v3:
> - intel_dp->lobf_supported replaced with crtc_state->has_lobf.
> [Jouni]
> - Add DISPLAY_VER() check. [Jouni]
> - Modify function name of get_aux_less_status. [Jani]
> v4: Add enum alpm_mode to hold the aux-wake/less capability.
>
> Signed-off-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_alpm.c | 58
> +++
> drivers/gpu/drm/i915/display/intel_alpm.h | 5 ++
> .../drm/i915/display/intel_display_types.h | 11
> drivers/gpu/drm/i915/display/intel_dp.c | 4 ++
> 4 files changed, 78 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> b/drivers/gpu/drm/i915/display/intel_alpm.c
> index ee6c2a959f09..5979eab1f2e0 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -11,6 +11,23 @@
> #include "intel_dp_aux.h"
> #include "intel_psr_regs.h"
>
> +enum alpm_mode intel_alpm_get_capability(struct intel_dp *intel_dp)
> +{
> + u8 alpm_caps = 0;
> +
> + if (drm_dp_dpcd_readb(_dp->aux, DP_RECEIVER_ALPM_CAP,
> + _caps) != 1)
> + return ALPM_INVALID;
> +
> + if (alpm_caps & DP_ALPM_CAP)
> + return ALPM_AUX_WAKE;
> +
> + if (alpm_caps & DP_ALPM_AUX_LESS_CAP)
> + return ALPM_AUX_LESS;
> +
> + return ALPM_NOT_SUPPORTED;
> +}
This will always return ALPM_AUX_WAKE if both are supported. I don't
think this is what you want?
You could add alpm_dpcd into intel_dp. Then for this purpose add
aux_wake_supported() and aux_less_wake_supported()?
BR,
Jouni Högander
> +
> /*
> * See Bspec: 71632 for the table
> *
> @@ -242,6 +259,47 @@ bool intel_alpm_compute_params(struct intel_dp
> *intel_dp,
> return true;
> }
>
> +void intel_alpm_compute_lobf_config(struct intel_dp *intel_dp,
> + struct intel_crtc_state
> *crtc_state,
> + struct drm_connector_state
> *conn_state)
> +{
> + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> + struct drm_display_mode *adjusted_mode = _state-
> >hw.adjusted_mode;
> + int waketime_in_lines, first_sdp_position;
> + int context_latency, guardband;
> +
> + if (!intel_dp_is_edp(intel_dp))
> + return;
> +
> + if (DISPLAY_VER(i915) < 20)
> + return;
> +
> + if (!intel_dp_as_sdp_supported(intel_dp))
> + return;
> +
> + if (crtc_state->has_psr)
> + return;
> +
> + if (intel_dp->alpm_parameters.mode == ALPM_INVALID ||
> + intel_dp->alpm_parameters.mode == ALPM_NOT_SUPPORTED)
> + return;
> +
> + if (!intel_alpm_compute_params(intel_dp, crtc_state))
> + return;
> +
> + context_latency = adjusted_mode->crtc_vblank_start -
> adjusted_mode->crtc_vdisplay;
> + guardband = adjusted_mode->crtc_vtotal -
> + adjusted_mode->crtc_vdisplay - context_latency;
> + first_sdp_position = adjusted_mode->crtc_vtotal -
> adjusted_mode->crtc_vsync_start;
> + if (intel_dp->alpm_parameters.mode == ALPM_AUX_LESS)
> + waketime_in_lines = intel_dp-
> >alpm_parameters.io_wake_lines;
> + else
> + waketime_in_lines = intel_dp-
> >alpm_parameters.fast_wake_lines;
> +
> + crtc_state->has_lobf = (context_latency + guardband) >
> + (first_sdp_position + waketime_in_lines);
> +}
> +
> static void lnl_alpm_configure(struct intel_dp *intel_dp)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h
> b/drivers/gpu/drm/i915/display/intel_alpm.h
> index c45d078e5a6b..80c8a66b34af 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.h
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.h
> @@ -10,9 +10,14 @@
>
> struct intel_dp;
> struct intel_crtc_state;
> +struct drm_connector_state;
>
> +enum alpm_mode intel_alpm_get_capability(struct intel_dp *intel_dp);
> bool intel_alpm_compute_params(struct intel_dp *intel_dp,
> struct intel_crtc_state *crtc_state);
> +void intel_alpm_compute_lobf_config(struct intel_dp *intel_dp,
> + struct intel_crtc_state
> *crtc_state,
> + struct drm_connector_state
> *conn_state);
> void intel_alpm_configure(struct intel_dp *intel_dp);
>
> #endif
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index e81fd71ce57b..79e9e543020b 100644
>
Re: [PATCH] drm/i915: Correct error handler
On 5/11/2024 5:48 PM, Jiasheng Jiang wrote:
Replace "slab_priorities" with "slab_dependencies" in the error handler to
avoid memory leak.
Nice catch. I would make the subject more like:
drm/i915: Fix memory leak by correcting cache object name in error handler
Fixes: 32eb6bcfdda9 ("drm/i915: Make request allocation caches global")
Also need Cc: # v5.2+
With those:
Reviewed-by: Nirmoy Das
Nirmoy
Signed-off-by: Jiasheng Jiang
---
drivers/gpu/drm/i915/i915_scheduler.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_scheduler.c
b/drivers/gpu/drm/i915/i915_scheduler.c
index 762127dd56c5..70a854557e6e 100644
--- a/drivers/gpu/drm/i915/i915_scheduler.c
+++ b/drivers/gpu/drm/i915/i915_scheduler.c
@@ -506,6 +506,6 @@ int __init i915_scheduler_module_init(void)
return 0;
err_priorities:
- kmem_cache_destroy(slab_priorities);
+ kmem_cache_destroy(slab_dependencies);
return -ENOMEM;
}
RE: [PATCH v8 1/7] drm/i915: Define and compute Transcoder CMRR registers
> -Original Message-
> From: Intel-gfx On Behalf Of Mitul
> Golani
> Sent: Thursday, May 9, 2024 1:28 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Shankar, Uma ; Nikula, Jani
>
> Subject: [PATCH v8 1/7] drm/i915: Define and compute Transcoder CMRR
> registers
>
> Add register definitions for Transcoder Fixed Average Vtotal mode/CMRR
> function, with the necessary bitfields.
> Compute these registers when CMRR is enabled, extending Adaptive refresh
> rate capabilities.
>
> --v2:
> - Use intel_de_read64_2x32 in intel_vrr_get_config. [Jani]
> - Fix indent and order based on register offset. [Jani]
>
> --v3:
> - Removing RFC tag.
>
> --v4:
> - Update place holder for CMRR register definition. (Jani)
>
> Signed-off-by: Mitul Golani
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 23 ++-
> .../drm/i915/display/intel_display_types.h| 6 +
> drivers/gpu/drm/i915/display/intel_vrr.c | 22 ++
> drivers/gpu/drm/i915/i915_reg.h | 10
Please create a new header file to add the CMRR related register definitions.
Thanks and Regards,
Arun R Murthy
> 4 files changed, 60 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index ef986b508431..258a78447fba 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1001,6 +1001,13 @@ static bool vrr_params_changed(const struct
> intel_crtc_state *old_crtc_state,
> old_crtc_state->vrr.pipeline_full != new_crtc_state-
> >vrr.pipeline_full;
> }
>
> +static bool cmrr_params_changed(const struct intel_crtc_state
> *old_crtc_state,
> + const struct intel_crtc_state *new_crtc_state) {
> + return old_crtc_state->cmrr.cmrr_m != new_crtc_state->cmrr.cmrr_m ||
> + old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n; }
> +
> static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state,
>const struct intel_crtc_state *new_crtc_state) { @@ -
> 5051,6 +5058,16 @@ intel_pipe_config_compare(const struct intel_crtc_state
> *current_config,
> } \
> } while (0)
>
> +#define PIPE_CONF_CHECK_LLI(name) do { \
> + if (current_config->name != pipe_config->name) { \
> + pipe_config_mismatch(, fastset, crtc, __stringify(name), \
> + "(expected %lli, found %lli)", \
> + current_config->name, \
> + pipe_config->name); \
> + ret = false; \
> + } \
> +} while (0)
> +
> #define PIPE_CONF_CHECK_BOOL(name) do { \
> if (current_config->name != pipe_config->name) { \
> BUILD_BUG_ON_MSG(!__same_type(current_config->name,
> bool), \ @@ -5415,10 +5432,13 @@ intel_pipe_config_compare(const struct
> intel_crtc_state *current_config,
> PIPE_CONF_CHECK_I(vrr.guardband);
> PIPE_CONF_CHECK_I(vrr.vsync_start);
> PIPE_CONF_CHECK_I(vrr.vsync_end);
> + PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
> + PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
> }
>
> #undef PIPE_CONF_CHECK_X
> #undef PIPE_CONF_CHECK_I
> +#undef PIPE_CONF_CHECK_LLI
> #undef PIPE_CONF_CHECK_BOOL
> #undef PIPE_CONF_CHECK_P
> #undef PIPE_CONF_CHECK_FLAGS
> @@ -6807,7 +6827,8 @@ static void intel_pre_update_crtc(struct
> intel_atomic_state *state,
> intel_crtc_needs_fastset(new_crtc_state))
> icl_set_pipe_chicken(new_crtc_state);
>
> - if (vrr_params_changed(old_crtc_state, new_crtc_state))
> + if (vrr_params_changed(old_crtc_state, new_crtc_state) ||
> + cmrr_params_changed(old_crtc_state, new_crtc_state))
> intel_vrr_set_transcoder_timings(new_crtc_state);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index a06a154d587b..475fb5252dd4 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1396,6 +1396,12 @@ struct intel_crtc_state {
> u32 vsync_end, vsync_start;
> } vrr;
>
> + /* Content Match Refresh Rate state */
> + struct {
> + bool enable;
> + u64 cmrr_n, cmrr_m;
> + } cmrr;
> +
> /* Stream Splitter for eDP MSO */
> struct {
> bool enable;
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
> b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 894ee97b3e1b..831554ea46b2 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -217,6 +217,19 @@ void intel_vrr_set_transcoder_timings(const struct
> intel_crtc_state *crtc_state)
> return;
> }
>
> + if
