Re: [Intel-gfx] [PATCH 2/2] drm/i915/edp/jsl: Update vswing table for HBR and HBR2

[James Ausmus]

On Mon, Sep 28, 2020 at 04:43:11PM +0300, Jani Nikula wrote:
> On Mon, 28 Sep 2020, Tejas Upadhyay 
>  wrote:
> > JSL has update in vswing table for eDP
> 
> I've thought the TLA for Jasper Lake is JSP, not JSL. At least we have
> PCH_JSP for Jasper Lake PCH.

JSP == Point (the PCH), JSL == Lake

-James

> 
> >
> > BSpec: 21257
> > Signed-off-by: Tejas Upadhyay 
> > ---
> >  drivers/gpu/drm/i915/display/intel_ddi.c | 67 ++--
> >  1 file changed, 64 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 4d06178cd76c..fa08463bcf2e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -582,6 +582,34 @@ static const struct cnl_ddi_buf_trans 
> > ehl_combo_phy_ddi_translations_dp[] = {
> > { 0x6, 0x7F, 0x3F, 0x00, 0x00 },/* 900   900  0.0   */
> >  };
> >  
> > +static const struct cnl_ddi_buf_trans 
> > jsl_combo_phy_ddi_translations_edp_hbr[] = {
> > +   /* NT mV Trans mV db*/
> > +   { 0x8, 0x7F, 0x3F, 0x00, 0x00 },/* 200   200  0.0   */
> > +   { 0x8, 0x7F, 0x38, 0x00, 0x07 },/* 200   250  1.9   */
> > +   { 0x1, 0x7F, 0x33, 0x00, 0x0C },/* 200   300  3.5   */
> > +   { 0xA, 0x35, 0x36, 0x00, 0x09 },/* 200   350  4.9   */
> > +   { 0x8, 0x7F, 0x3F, 0x00, 0x00 },/* 250   250  0.0   */
> > +   { 0x1, 0x7F, 0x38, 0x00, 0x07 },/* 250   300  1.6   */
> > +   { 0xA, 0x35, 0x35, 0x00, 0x0A },/* 250   350  2.9   */
> > +   { 0x1, 0x7F, 0x3F, 0x00, 0x00 },/* 300   300  0.0   */
> > +   { 0xA, 0x35, 0x38, 0x00, 0x07 },/* 300   350  1.3   */
> > +   { 0xA, 0x35, 0x3F, 0x00, 0x00 },/* 350   350  0.0   */
> > +};
> > +
> > +static const struct cnl_ddi_buf_trans 
> > jsl_combo_phy_ddi_translations_edp_hbr2[] = {
> > +   /* NT mV Trans mV db*/
> > +   { 0x8, 0x7F, 0x3F, 0x00, 0x00 },/* 200   200  0.0   */
> > +   { 0x8, 0x7F, 0x3F, 0x00, 0x00 },/* 200   250  1.9   */
> > +   { 0x1, 0x7F, 0x3D, 0x00, 0x02 },/* 200   300  3.5   */
> > +   { 0xA, 0x35, 0x38, 0x00, 0x07 },/* 200   350  4.9   */
> > +   { 0x8, 0x7F, 0x3F, 0x00, 0x00 },/* 250   250  0.0   */
> > +   { 0x1, 0x7F, 0x3F, 0x00, 0x00 },/* 250   300  1.6   */
> > +   { 0xA, 0x35, 0x3A, 0x00, 0x05 },/* 250   350  2.9   */
> > +   { 0x1, 0x7F, 0x3F, 0x00, 0x00 },/* 300   300  0.0   */
> > +   { 0xA, 0x35, 0x38, 0x00, 0x07 },/* 300   350  1.3   */
> > +   { 0xA, 0x35, 0x3F, 0x00, 0x00 },/* 350   350  0.0   */
> > +};
> > +
> >  struct icl_mg_phy_ddi_buf_trans {
> > u32 cri_txdeemph_override_11_6;
> > u32 cri_txdeemph_override_5_0;
> > @@ -1069,7 +1097,6 @@ icl_get_mg_buf_trans(struct intel_encoder *encoder, 
> > int type, int rate,
> > *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_rbr_hbr);
> > return icl_mg_phy_ddi_translations_rbr_hbr;
> >  }
> > -
> >  static const struct cnl_ddi_buf_trans *
> >  ehl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
> > int *n_entries)
> > @@ -1098,6 +1125,34 @@ ehl_get_combo_buf_trans(struct intel_encoder 
> > *encoder, int type, int rate,
> > }
> >  }
> >  
> > +static const struct cnl_ddi_buf_trans *
> > +jsl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
> > +   int *n_entries)
> > +{
> > +   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > +
> > +   switch (type) {
> > +   case INTEL_OUTPUT_HDMI:
> > +   *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
> > +   return icl_combo_phy_ddi_translations_hdmi;
> > +   case INTEL_OUTPUT_EDP:
> > +   if (dev_priv->vbt.edp.low_vswing) {
> > +   if (rate > 27) {
> > +   *n_entries = 
> > ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr2);
> > +   return jsl_combo_phy_ddi_translations_edp_hbr2;
> > +   } else {
> > +   *n_entries = 
> > ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr);
> > +   return jsl_combo_phy_ddi_translations_edp_hbr;
> > +   }
> > +   }
> > +   /* fall through */
> > +   default:
> > +   /* All combo DP and eDP ports that do not support low_vswing */
> > +   *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
> > +   return icl_combo_phy_ddi_translations_dp_hbr2;
> > +   }
> > +}
> > +
> >  static const struct cnl_ddi_buf_trans *
> >  tgl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
> > int *n_entries)
> > @@ -2265,9 +2320,12 @@ static u8 

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gt: Implement WA_1406941453 (rev2)

[James Ausmus]

On Thu, Aug 06, 2020 at 12:09:53AM +, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915/gt: Implement WA_1406941453 (rev2)
> URL   : https://patchwork.freedesktop.org/series/78243/
> State : failure
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_8846 -> Patchwork_18312
> 
> 
> Summary
> ---
> 
>   **FAILURE**
> 
>   Serious unknown changes coming with Patchwork_18312 absolutely need to be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the changes
>   introduced in Patchwork_18312, please notify your bug team to allow them
>   to document this new failure mode, which will reduce false positives in CI.
> 
>   External URL: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18312/index.html
> 
> Possible new issues
> ---
> 
>   Here are the unknown changes that may have been introduced in 
> Patchwork_18312:
> 
> ### IGT changes ###
> 
>  Possible regressions 
> 
>   * igt@kms_chamelium@hdmi-hpd-fast:
> - fi-icl-u2:  [PASS][1] -> [DMESG-WARN][2] +1 similar issue
>[1]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8846/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html
>[2]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18312/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html

This isn't related - Lakshmi, can you re-report?

Thanks!

-James

> 
>   
> Known issues
> 
> 
>   Here are the changes found in Patchwork_18312 that come from known issues:
> 
> ### IGT changes ###
> 
>  Issues hit 
> 
>   * igt@i915_selftest@live@execlists:
> - fi-icl-y:   [PASS][3] -> [INCOMPLETE][4] ([i915#2276])
>[3]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8846/fi-icl-y/igt@i915_selftest@l...@execlists.html
>[4]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18312/fi-icl-y/igt@i915_selftest@l...@execlists.html
> 
>   * igt@kms_cursor_legacy@basic-flip-after-cursor-atomic:
> - fi-icl-u2:  [PASS][5] -> [DMESG-WARN][6] ([i915#1982]) +2 
> similar issues
>[5]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8846/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-after-cursor-atomic.html
>[6]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18312/fi-icl-u2/igt@kms_cursor_leg...@basic-flip-after-cursor-atomic.html
> 
>   
>  Possible fixes 
> 
>   * igt@i915_module_load@reload:
> - fi-apl-guc: [DMESG-WARN][7] ([i915#1635] / [i915#1982]) -> 
> [PASS][8]
>[7]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8846/fi-apl-guc/igt@i915_module_l...@reload.html
>[8]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18312/fi-apl-guc/igt@i915_module_l...@reload.html
> 
>   * igt@i915_pm_rpm@basic-pci-d3-state:
> - fi-byt-j1900:   [DMESG-WARN][9] ([i915#1982]) -> [PASS][10]
>[9]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8846/fi-byt-j1900/igt@i915_pm_...@basic-pci-d3-state.html
>[10]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18312/fi-byt-j1900/igt@i915_pm_...@basic-pci-d3-state.html
> 
>   * igt@i915_pm_rpm@module-reload:
> - fi-bsw-kefka:   [INCOMPLETE][11] ([i915#151] / [i915#1844] / 
> [i915#1909] / [i915#392]) -> [PASS][12]
>[11]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8846/fi-bsw-kefka/igt@i915_pm_...@module-reload.html
>[12]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18312/fi-bsw-kefka/igt@i915_pm_...@module-reload.html
> 
>   * igt@i915_selftest@live@gt_lrc:
> - fi-tgl-u2:  [DMESG-FAIL][13] ([i915#1233]) -> [PASS][14]
>[13]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8846/fi-tgl-u2/igt@i915_selftest@live@gt_lrc.html
>[14]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18312/fi-tgl-u2/igt@i915_selftest@live@gt_lrc.html
> 
>   * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
> - fi-icl-u2:  [DMESG-WARN][15] ([i915#1982]) -> [PASS][16] +1 
> similar issue
>[15]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8846/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html
>[16]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18312/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html
> 
>   
>  Warnings 
> 
>   * igt@gem_exec_suspend@basic-s0:
> - fi-kbl-x1275:   [DMESG-WARN][17] ([i915#62] / [i915#92]) -> 
> [DMESG-WARN][18] ([i915#62] / [i915#92] / [i915#95]) +4 similar issues
>[17]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8846/fi-kbl-x1275/igt@gem_exec_susp...@basic-s0.html
>[18]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18312/fi-kbl-x1275/igt@gem_exec_susp...@basic-s0.html
> 
>   * igt@i915_pm_rpm@module-reload:
> - fi-kbl-guc: [DMESG-FAIL][19] ([i915#2203]) -> [DMESG-WARN][20] 
> ([i915#2203])
>[19]: 
> 

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gt: Implement WA_1406941453

[James Ausmus]

On Fri, Jun 12, 2020 at 12:04:35AM +, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915/gt: Implement WA_1406941453
> URL   : https://patchwork.freedesktop.org/series/78243/
> State : failure
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_8618 -> Patchwork_17931
> 
> 
> Summary
> ---
> 
>   **FAILURE**
> 
>   Serious unknown changes coming with Patchwork_17931 absolutely need to be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the changes
>   introduced in Patchwork_17931, please notify your bug team to allow them
>   to document this new failure mode, which will reduce false positives in CI.
> 
>   External URL: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/index.html
> 
> Possible new issues
> ---
> 
>   Here are the unknown changes that may have been introduced in 
> Patchwork_17931:
> 
> ### IGT changes ###
> 
>  Possible regressions 
> 
>   * igt@runner@aborted:
> - fi-bdw-5557u:   NOTRUN -> [FAIL][1]
>[1]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/fi-bdw-5557u/igt@run...@aborted.html

Lakshmi - this failure isn't related - can you re-report?

Thanks!

-James

> 
>   
> Known issues
> 
> 
>   Here are the changes found in Patchwork_17931 that come from known issues:
> 
> ### IGT changes ###
> 
>  Issues hit 
> 
>   * igt@gem_exec_suspend@basic-s0:
> - fi-tgl-u2:  [PASS][2] -> [FAIL][3] ([i915#1888])
>[2]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-tgl-u2/igt@gem_exec_susp...@basic-s0.html
>[3]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/fi-tgl-u2/igt@gem_exec_susp...@basic-s0.html
> 
>   * igt@gem_sync@basic-all:
> - fi-icl-guc: [PASS][4] -> [DMESG-WARN][5] ([i915#1982])
>[4]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-icl-guc/igt@gem_s...@basic-all.html
>[5]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/fi-icl-guc/igt@gem_s...@basic-all.html
> 
>   * igt@i915_module_load@reload:
> - fi-tgl-u2:  [PASS][6] -> [DMESG-WARN][7] ([i915#1982])
>[6]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-tgl-u2/igt@i915_module_l...@reload.html
>[7]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/fi-tgl-u2/igt@i915_module_l...@reload.html
> 
>   * igt@i915_pm_rpm@basic-pci-d3-state:
> - fi-bsw-kefka:   [PASS][8] -> [DMESG-WARN][9] ([i915#1982])
>[8]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-bsw-kefka/igt@i915_pm_...@basic-pci-d3-state.html
>[9]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/fi-bsw-kefka/igt@i915_pm_...@basic-pci-d3-state.html
> 
>   * igt@kms_flip@basic-flip-vs-wf_vblank@b-edp1:
> - fi-icl-u2:  [PASS][10] -> [DMESG-WARN][11] ([i915#1982]) +1 
> similar issue
>[10]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vbl...@b-edp1.html
>[11]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vbl...@b-edp1.html
> 
>   
>  Possible fixes 
> 
>   * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
> - fi-byt-j1900:   [DMESG-WARN][12] ([i915#1982]) -> [PASS][13]
>[12]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-byt-j1900/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
>[13]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/fi-byt-j1900/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-atomic.html
> 
>   * igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
> - fi-tgl-u2:  [DMESG-WARN][14] ([i915#402]) -> [PASS][15]
>[14]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-tgl-u2/igt@kms_pipe_crc_ba...@read-crc-pipe-a-frame-sequence.html
>[15]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/fi-tgl-u2/igt@kms_pipe_crc_ba...@read-crc-pipe-a-frame-sequence.html
> 
>   
>  Warnings 
> 
>   * igt@gem_exec_suspend@basic-s0:
> - fi-kbl-x1275:   [DMESG-WARN][16] ([i915#62] / [i915#92] / 
> [i915#95]) -> [DMESG-WARN][17] ([i915#62] / [i915#92]) +2 similar issues
>[16]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-kbl-x1275/igt@gem_exec_susp...@basic-s0.html
>[17]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/fi-kbl-x1275/igt@gem_exec_susp...@basic-s0.html
> 
>   * igt@kms_flip@basic-flip-vs-modeset@a-dp1:
> - fi-kbl-x1275:   [DMESG-WARN][18] ([i915#62] / [i915#92]) -> 
> [DMESG-WARN][19] ([i915#62] / [i915#92] / [i915#95]) +4 similar issues
>[18]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8618/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-mode...@a-dp1.html
>[19]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17931/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-mode...@a-dp1.html
> 
>   
>   [i915#1888]: 

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/5] drm: Add __drm_atomic_helper_crtc_state_reset() & co. (rev3)

[James Ausmus]

(+Lakshmi)

On Tue, Dec 17, 2019 at 06:33:58PM +, Souza, Jose wrote:
> On Tue, 2019-12-17 at 18:10 +, Patchwork wrote:
> > == Series Details ==
> > 
> > Series: series starting with [1/5] drm: Add
> > __drm_atomic_helper_crtc_state_reset() & co. (rev3)
> > URL   : https://patchwork.freedesktop.org/series/69129/
> > State : failure
> > 
> > == Summary ==
> > 
> > CI Bug Log - changes from CI_DRM_7578_full -> Patchwork_15797_full
> > 
> > 
> > Summary
> > ---
> > 
> >   **FAILURE**
> > 
> >   Serious unknown changes coming with Patchwork_15797_full absolutely
> > need to be
> >   verified manually.
> >   
> >   If you think the reported changes have nothing to do with the
> > changes
> >   introduced in Patchwork_15797_full, please notify your bug team to
> > allow them
> >   to document this new failure mode, which will reduce false
> > positives in CI.
> > 
> >   
> > 
> > Possible new issues
> > ---
> > 
> >   Here are the unknown changes that may have been introduced in
> > Patchwork_15797_full:
> > 
> > ### IGT changes ###
> > 
> >  Possible regressions 
> > 
> >   * igt@kms_big_fb@linear-16bpp-rotate-180:
> > - shard-tglb: [PASS][1] -> [DMESG-WARN][2]
> >[1]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-tglb5/igt@kms_big...@linear-16bpp-rotate-180.html
> >[2]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15797/shard-tglb3/igt@kms_big...@linear-16bpp-rotate-180.html
> 
> This one is not related to the changes in this series
> 
> > 
> >   * igt@kms_frontbuffer_tracking@basic:
> > - shard-skl:  [PASS][3] -> ([INCOMPLETE][4], [PASS][5])
> >[3]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7578/shard-skl4/igt@kms_frontbuffer_track...@basic.html
> >[4]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15797/shard-skl10/igt@kms_frontbuffer_track...@basic.html
> >[5]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15797/shard-skl7/igt@kms_frontbuffer_track...@basic.html
> > 
> 
> Getting AccessDenied when trying to access the error reports
> 
> >   
> > 
> > ### Piglit changes ###
> > 
> >  Possible regressions 
> > 
> >   * spec@arb_texture_barrier@arb_texture_barrier-blending-in-shader
> > 512 1 8 128 3 (NEW):
> > - {pig-hsw-4770r}:NOTRUN -> [FAIL][6] +20 similar issues
> >[6]: None
> > 
> >   
> > New tests
> > -
> > 
> >   New tests have been introduced between CI_DRM_7578_full and
> > Patchwork_15797_full:
> > 
> > ### New Piglit tests (21) ###
> > 
> >   * object namespace pollution@texture with glgetteximage-compressed:
> > - Statuses : 1 fail(s)
> > - Exec time: [0.13] s
> > 
> >   * object namespace pollution@texture with gltexsubimage2d:
> > - Statuses : 1 fail(s)
> > - Exec time: [0.15] s
> > 
> >   * spec@arb_gpu_shader5@texturegather@vs-rgb-0-float-cube:
> > - Statuses : 1 fail(s)
> > - Exec time: [1.83] s
> > 
> >   * spec@arb_query_buffer_object@coherency:
> > - Statuses : 1 fail(s)
> > - Exec time: [0.22] s
> > 
> >   * spec@arb_shader_image_load_store@host-mem-barrier:
> > - Statuses : 1 fail(s)
> > - Exec time: [5.66] s
> > 
> >   * spec@arb_shader_image_load_store@layer:
> > - Statuses : 1 fail(s)
> > - Exec time: [0.31] s
> > 
> >   * spec@arb_shader_image_load_store@level:
> > - Statuses : 1 fail(s)
> > - Exec time: [0.27] s
> > 
> >   * spec@arb_shader_image_load_store@semantics:
> > - Statuses : 1 fail(s)
> > - Exec time: [0.53] s
> > 
> >   * spec@arb_shader_image_load_store@unused:
> > - Statuses : 1 fail(s)
> > - Exec time: [0.16] s
> > 
> >   * spec@arb_texture_barrier@arb_texture_barrier-blending-in-shader
> > 32 1 8 128 2:
> > - Statuses : 1 fail(s)
> > - Exec time: [0.13] s
> > 
> >   * spec@arb_texture_barrier@arb_texture_barrier-blending-in-shader
> > 32 42 1 128 4:
> > - Statuses : 1 fail(s)
> > - Exec time: [0.08] s
> > 
> >   * spec@arb_texture_barrier@arb_texture_barrier-blending-in-shader
> > 32 42 8 128 2:
> > - Statuses : 1 fail(s)
> > - Exec time: [0.10] s
> > 
> >   * spec@arb_texture_barrier@arb_texture_barrier-blending-in-shader
> > 32 42 8 128 3:
> > - Statuses : 1 fail(s)
> > - Exec time: [0.12] s
> > 
> >   * spec@arb_texture_barrier@arb_texture_barrier-blending-in-shader
> > 512 1 8 128 3:
> > - Statuses : 1 fail(s)
> > - Exec time: [0.24] s
> > 
> >   * spec@arb_texture_barrier@arb_texture_barrier-blending-in-shader
> > 512 1 8 128 4:
> > - Statuses : 1 fail(s)
> > - Exec time: [0.27] s
> > 
> >   * spec@arb_texture_barrier@arb_texture_barrier-blending-in-shader
> > 512 1 8 128 8:
> > - Statuses : 1 fail(s)
> > - Exec time: [0.26] s
> > 
> >   * spec@arb_texture_barrier@arb_texture_barrier-blending-in-shader
> > 512 42 1 128 8:
> > - Statuses : 1 fail(s)
> > - Exec time: [0.19] s
> > 
> >   * 

Re: [Intel-gfx] [PATCH 3/4] drm/i915/dp: Fix MST disable sequences

[James Ausmus]

On Tue, Dec 10, 2019 at 11:38:50PM +0200, Ville Syrjälä wrote:
> On Fri, Dec 06, 2019 at 05:18:31PM -0800, José Roberto de Souza wrote:
> > The disable sequence after wait for transcoder off was not correctly
> > implemented.
> > The MST disable sequence is basically the same for HSW, SKL, ICL and
> > TGL, with just minor changes for TGL.
> > 
> > So here calling a new MST function to do the MST sequences, most of
> > the steps just moved from the post disable hook.
> > 
> > With this last patch we finally fixed the hotplugs triggered by MST
> > sinks during the disable/enable sequence, those were causing source
> > to try to do a link training while it was not ready causing CPU pipe
> > FIFO underrrus on TGL.
> > 
> > BSpec: 4231
> > BSpec: 4163
> > BSpec: 22243
> > BSpec: 49190
> > Cc: Lucas De Marchi 
> > Signed-off-by: José Roberto de Souza 
> > ---
> >  drivers/gpu/drm/i915/display/intel_ddi.c | 17 +++--
> >  drivers/gpu/drm/i915/display/intel_display.c |  2 +
> >  drivers/gpu/drm/i915/display/intel_dp_mst.c  | 79 
> >  drivers/gpu/drm/i915/display/intel_dp_mst.h  |  1 +
> >  4 files changed, 79 insertions(+), 20 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index be5bc506d4d3..f06c6dfec888 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -34,6 +34,7 @@
> >  #include "intel_ddi.h"
> >  #include "intel_display_types.h"
> >  #include "intel_dp.h"
> > +#include "intel_dp_mst.h"
> >  #include "intel_dp_link_training.h"
> >  #include "intel_dpio_phy.h"
> >  #include "intel_dsi.h"
> > @@ -1953,17 +1954,19 @@ void intel_ddi_disable_transcoder_func(const struct 
> > intel_crtc_state *crtc_state
> > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > -   i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
> > -   u32 val = I915_READ(reg);
> > +   u32 val;
> > +
> > +   val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
> > +   val &= ~TRANS_DDI_FUNC_ENABLE;
> >  
> > if (INTEL_GEN(dev_priv) >= 12) {
> > -   val &= ~(TRANS_DDI_FUNC_ENABLE | TGL_TRANS_DDI_PORT_MASK |
> > -TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
> > +   if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) ||
> > +   intel_dp_mst_is_slave_trans(crtc_state))
> > +   val &= ~TGL_TRANS_DDI_PORT_MASK;
> > } else {
> > -   val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK |
> > -TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
> > +   val &= ~TRANS_DDI_PORT_MASK;
> > }
> > -   I915_WRITE(reg, val);
> > +   I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), val);
> >  
> > if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
> > intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 2f74c0bfb2a8..d3eefb271fa4 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -6776,6 +6776,8 @@ static void haswell_crtc_disable(struct 
> > intel_atomic_state *state,
> > if (!transcoder_is_dsi(cpu_transcoder))
> > intel_disable_pipe(old_crtc_state);
> >  
> > +   intel_dp_mst_post_trans_disabled(old_crtc_state);
> > +
> 
> Basically a new ad-hoc encoder hook :(
> 
> I think we either want to suck in more crap from the crtc_enable/disable
> into the encoder hooks, or we try to move everything from the current
> .post_disable() into .post_pll_disable() and relocate .post_disabel()
> to a better place in the sequence. Though the whole .post_pll_disable()
> is a farily poor match for these platforms as there's nothing to do after
> disabling the PLL. So from the hook naming POV I'd kinda want move things
> the other way.
> 
> So I think moving more things into the encoder hooks sounds like a
> better plan. Eg. in this case I think we could probably shovel everything
> after intel_pipe_disable() into .post_disable(). Would also help us
> eliminate some of those 'if !dsi' things.
> 
> I'm also thinking intel_disable_ddi_buf() should be split up and
> just inlined into the proper place(s). Would help in making the sequence
> more easily comparable with the spec.

Does this refactoring and cleanup need to happen for the immediate goal
of fixing MST, or can it land as a cleanup after we get this series
merged and MST is functional?

Thanks!

-James

> 
> 
> > if (INTEL_GEN(dev_priv) >= 11)
> > icl_disable_transcoder_port_sync(old_crtc_state);
> >  
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c 
> > b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > index 49f1518e3ab9..3c98a25e6308 100644
> > --- 

Re: [Intel-gfx] [PATCH] drm/i915/tgl: Add second TGL PCH ID

[James Ausmus]

On Wed, Nov 06, 2019 at 04:25:27PM -0800, Lucas De Marchi wrote:
> On Tue, Nov 05, 2019 at 05:13:29PM -0800, Jose Souza wrote:
> >On Tue, 2019-11-05 at 16:55 -0800, James Ausmus wrote:
> >> Another TGP ID has shown up, so let's add it to avoid South Display
> >> breakage on systems that have this ID.
> >>
> >
> >Reviewed-by: José Roberto de Souza 
> 
> and pushed, thanks

Thanks Lucas!

-James

> 
> Lucas De Marchi
> 
> >
> >> Cc: Lucas De Marchi 
> >> Cc: José Roberto de Souza 
> >> Signed-off-by: James Ausmus 
> >> ---
> >>  drivers/gpu/drm/i915/intel_pch.c | 1 +
> >>  drivers/gpu/drm/i915/intel_pch.h | 1 +
> >>  2 files changed, 2 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/i915/intel_pch.c
> >> b/drivers/gpu/drm/i915/intel_pch.c
> >> index 000ba43e2c02..fd22355b9a96 100644
> >> --- a/drivers/gpu/drm/i915/intel_pch.c
> >> +++ b/drivers/gpu/drm/i915/intel_pch.c
> >> @@ -85,6 +85,7 @@ intel_pch_type(const struct drm_i915_private
> >> *dev_priv, unsigned short id)
> >>WARN_ON(!IS_ELKHARTLAKE(dev_priv));
> >>return PCH_MCC;
> >>case INTEL_PCH_TGP_DEVICE_ID_TYPE:
> >> +  case INTEL_PCH_TGP2_DEVICE_ID_TYPE:
> >>DRM_DEBUG_KMS("Found Tiger Lake LP PCH\n");
> >>WARN_ON(!IS_TIGERLAKE(dev_priv));
> >>return PCH_TGP;
> >> diff --git a/drivers/gpu/drm/i915/intel_pch.h
> >> b/drivers/gpu/drm/i915/intel_pch.h
> >> index 1115c6a0522c..52d145dcdb15 100644
> >> --- a/drivers/gpu/drm/i915/intel_pch.h
> >> +++ b/drivers/gpu/drm/i915/intel_pch.h
> >> @@ -47,6 +47,7 @@ enum intel_pch {
> >>  #define INTEL_PCH_ICP_DEVICE_ID_TYPE  0x3480
> >>  #define INTEL_PCH_MCC_DEVICE_ID_TYPE  0x4B00
> >>  #define INTEL_PCH_TGP_DEVICE_ID_TYPE  0xA080
> >> +#define INTEL_PCH_TGP2_DEVICE_ID_TYPE 0x4380
> >>  #define INTEL_PCH_JSP_DEVICE_ID_TYPE  0x4D80
> >>  #define INTEL_PCH_JSP2_DEVICE_ID_TYPE 0x3880
> >>  #define INTEL_PCH_P2X_DEVICE_ID_TYPE  0x7100
___
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Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/tgl: Add second TGL PCH ID

[James Ausmus]

On Wed, Nov 06, 2019 at 10:26:10PM +, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915/tgl: Add second TGL PCH ID
> URL   : https://patchwork.freedesktop.org/series/69023/
> State : success
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_7264_full -> Patchwork_15140_full
> 
> 
> Summary
> ---
> 
>   **SUCCESS**
> 
>   No regressions found.

\o/

Anyone willing to merge? :D

-James

> 
>   
> 
> Known issues
> 
> 
>   Here are the changes found in Patchwork_15140_full that come from known 
> issues:
> 
> ### IGT changes ###
> 
>  Issues hit 
> 
>   * igt@gem_busy@busy-vcs1:
> - shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#112080]) +18 similar 
> issues
>[1]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-iclb2/igt@gem_b...@busy-vcs1.html
>[2]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15140/shard-iclb5/igt@gem_b...@busy-vcs1.html
> 
>   * igt@gem_ctx_isolation@rcs0-s3:
> - shard-kbl:  [PASS][3] -> [DMESG-WARN][4] ([fdo#108566]) +3 
> similar issues
>[3]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-kbl3/igt@gem_ctx_isolat...@rcs0-s3.html
>[4]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15140/shard-kbl7/igt@gem_ctx_isolat...@rcs0-s3.html
> 
>   * igt@gem_ctx_isolation@vcs1-clean:
> - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#109276] / 
> [fdo#112080]) +1 similar issue
>[5]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-iclb4/igt@gem_ctx_isolat...@vcs1-clean.html
>[6]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15140/shard-iclb7/igt@gem_ctx_isolat...@vcs1-clean.html
> 
>   * igt@gem_ctx_shared@exec-single-timeline-bsd:
> - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#110841])
>[7]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-iclb5/igt@gem_ctx_sha...@exec-single-timeline-bsd.html
>[8]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15140/shard-iclb4/igt@gem_ctx_sha...@exec-single-timeline-bsd.html
> 
>   * igt@gem_eio@unwedge-stress:
> - shard-snb:  [PASS][9] -> [FAIL][10] ([fdo#109661])
>[9]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-snb1/igt@gem_...@unwedge-stress.html
>[10]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15140/shard-snb1/igt@gem_...@unwedge-stress.html
> 
>   * igt@gem_exec_schedule@preempt-contexts-bsd2:
> - shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109276]) +25 similar 
> issues
>[11]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-iclb1/igt@gem_exec_sched...@preempt-contexts-bsd2.html
>[12]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15140/shard-iclb6/igt@gem_exec_sched...@preempt-contexts-bsd2.html
> 
>   * igt@gem_exec_schedule@wide-bsd:
> - shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#112146]) +5 similar 
> issues
>[13]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-iclb7/igt@gem_exec_sched...@wide-bsd.html
>[14]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15140/shard-iclb1/igt@gem_exec_sched...@wide-bsd.html
> 
>   * igt@gem_userptr_blits@sync-unmap:
> - shard-snb:  [PASS][15] -> [DMESG-WARN][16] ([fdo#111870])
>[15]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-snb1/igt@gem_userptr_bl...@sync-unmap.html
>[16]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15140/shard-snb1/igt@gem_userptr_bl...@sync-unmap.html
> 
>   * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
> - shard-hsw:  [PASS][17] -> [FAIL][18] ([fdo#105767])
>[17]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-hsw5/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-legacy.html
>[18]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15140/shard-hsw4/igt@kms_cursor_leg...@2x-long-cursor-vs-flip-legacy.html
> 
>   * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
> - shard-glk:  [PASS][19] -> [FAIL][20] ([fdo#104873])
>[19]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-glk8/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-atomic.html
>[20]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15140/shard-glk4/igt@kms_cursor_leg...@2x-long-flip-vs-cursor-atomic.html
> 
>   * igt@kms_frontbuffer_tracking@fbc-tilingchange:
> - shard-iclb: [PASS][21] -> [FAIL][22] ([fdo#103167]) +7 similar 
> issues
>[21]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7264/shard-iclb1/igt@kms_frontbuffer_track...@fbc-tilingchange.html
>[22]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15140/shard-iclb2/igt@kms_frontbuffer_track...@fbc-tilingchange.html
> 
>   * igt@kms_plane_lowres@pipe-a-tiling-y:
> - shard-iclb: [PASS][23] -> [FAIL][24] ([fdo#103166])
>[23]: 
> 

[Intel-gfx] [PATCH] drm/i915/tgl: Add second TGL PCH ID

[James Ausmus]

Another TGP ID has shown up, so let's add it to avoid South Display
breakage on systems that have this ID.

Cc: Lucas De Marchi 
Cc: José Roberto de Souza 
Signed-off-by: James Ausmus 
---
 drivers/gpu/drm/i915/intel_pch.c | 1 +
 drivers/gpu/drm/i915/intel_pch.h | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c
index 000ba43e2c02..fd22355b9a96 100644
--- a/drivers/gpu/drm/i915/intel_pch.c
+++ b/drivers/gpu/drm/i915/intel_pch.c
@@ -85,6 +85,7 @@ intel_pch_type(const struct drm_i915_private *dev_priv, 
unsigned short id)
WARN_ON(!IS_ELKHARTLAKE(dev_priv));
return PCH_MCC;
case INTEL_PCH_TGP_DEVICE_ID_TYPE:
+   case INTEL_PCH_TGP2_DEVICE_ID_TYPE:
DRM_DEBUG_KMS("Found Tiger Lake LP PCH\n");
WARN_ON(!IS_TIGERLAKE(dev_priv));
return PCH_TGP;
diff --git a/drivers/gpu/drm/i915/intel_pch.h b/drivers/gpu/drm/i915/intel_pch.h
index 1115c6a0522c..52d145dcdb15 100644
--- a/drivers/gpu/drm/i915/intel_pch.h
+++ b/drivers/gpu/drm/i915/intel_pch.h
@@ -47,6 +47,7 @@ enum intel_pch {
 #define INTEL_PCH_ICP_DEVICE_ID_TYPE   0x3480
 #define INTEL_PCH_MCC_DEVICE_ID_TYPE   0x4B00
 #define INTEL_PCH_TGP_DEVICE_ID_TYPE   0xA080
+#define INTEL_PCH_TGP2_DEVICE_ID_TYPE  0x4380
 #define INTEL_PCH_JSP_DEVICE_ID_TYPE   0x4D80
 #define INTEL_PCH_JSP2_DEVICE_ID_TYPE  0x3880
 #define INTEL_PCH_P2X_DEVICE_ID_TYPE   0x7100
-- 
2.23.0

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Re: [Intel-gfx] [PATCH v9 2/2] drm/i915: Restrict qgv points which don't have enough bandwidth.

[James Ausmus]

On Tue, Oct 29, 2019 at 06:12:26PM +0200, Stanislav Lisovskiy wrote:
> According to BSpec 53998, we should try to
> restrict qgv points, which can't provide
> enough bandwidth for desired display configuration.
> 
> Currently we are just comparing against all of
> those and take minimum(worst case).
> 
> v2: Fixed wrong PCode reply mask, removed hardcoded
> values.
> 
> v3: Forbid simultaneous legacy SAGV PCode requests and
> restricting qgv points. Put the actual restriction
> to commit function, added serialization(thanks to Ville)
> to prevent commit being applied out of order in case of
> nonblocking and/or nomodeset commits.
> 
> v4:
>     - Minor code refactoring, fixed few typos(thanks to James Ausmus)
> - Change the naming of qgv point
>   masking/unmasking functions(James Ausmus).
> - Simplify the masking/unmasking operation itself,
>   as we don't need to mask only single point per request(James Ausmus)
> - Reject and stick to highest bandwidth point if SAGV
>   can't be enabled(BSpec)
> 
> v5:
> - Add new mailbox reply codes, which seems to happen during boot
>   time for TGL and indicate that QGV setting is not yet available.
> 
> v6:
>     - Increase number of supported QGV points to be in sync with BSpec.
> 
> Reviewed-by: James Ausmus 
> Signed-off-by: Stanislav Lisovskiy 
> Cc: Ville Syrjälä 
> Cc: James Ausmus 
> ---
>  drivers/gpu/drm/i915/display/intel_atomic.c   |  16 +++
>  drivers/gpu/drm/i915/display/intel_atomic.h   |   3 +
>  drivers/gpu/drm/i915/display/intel_bw.c   | 111 ++
>  drivers/gpu/drm/i915/display/intel_bw.h   |   2 +
>  drivers/gpu/drm/i915/display/intel_display.c  |  57 -
>  .../drm/i915/display/intel_display_types.h|   3 +
>  drivers/gpu/drm/i915/i915_drv.h   |   2 +
>  drivers/gpu/drm/i915/i915_reg.h   |   5 +
>  drivers/gpu/drm/i915/intel_sideband.c |  27 -
>  9 files changed, 198 insertions(+), 28 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c 
> b/drivers/gpu/drm/i915/display/intel_atomic.c
> index c5a552a69752..b3f4f02f380b 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> @@ -207,6 +207,22 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
>   return _state->base;
>  }
>  
> +int intel_atomic_serialize_global_state(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_crtc *crtc;
> +
> + for_each_intel_crtc(_priv->drm, crtc) {
> + struct intel_crtc_state *crtc_state;
> +
> + crtc_state = intel_atomic_get_crtc_state(>base, crtc);
> + if (IS_ERR(crtc_state))
> + return PTR_ERR(crtc_state);
> + }
> +
> + return 0;
> +}
> +
>  /**
>   * intel_crtc_destroy_state - destroy crtc state
>   * @crtc: drm crtc
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h 
> b/drivers/gpu/drm/i915/display/intel_atomic.h
> index 58065d3161a3..fd17b3ca257f 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.h
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.h
> @@ -7,6 +7,7 @@
>  #define __INTEL_ATOMIC_H__
>  
>  #include 
> +#include "intel_display_types.h"
>  
>  struct drm_atomic_state;
>  struct drm_connector;
> @@ -38,6 +39,8 @@ void intel_crtc_destroy_state(struct drm_crtc *crtc,
>  struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
>  void intel_atomic_state_clear(struct drm_atomic_state *state);
>  
> +int intel_atomic_serialize_global_state(struct intel_atomic_state *state);
> +
>  struct intel_crtc_state *
>  intel_atomic_get_crtc_state(struct drm_atomic_state *state,
>   struct intel_crtc *crtc);
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c 
> b/drivers/gpu/drm/i915/display/intel_bw.c
> index 22e83f857de8..60249d9776d1 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -8,14 +8,20 @@
>  #include "intel_bw.h"
>  #include "intel_display_types.h"
>  #include "intel_sideband.h"
> +#include "intel_atomic.h"
> +#include "intel_pm.h"
>  
>  /* Parameters for Qclk Geyserville (QGV) */
>  struct intel_qgv_point {
>   u16 dclk, t_rp, t_rdpre, t_rc, t_ras, t_rcd;
>  };
>  
> +
> +/* BSpec precisely defines this */
> +#define NUM_SAGV_POINTS 4

As noted before, this should be 8, and should be defined in the .h file.

With that addressed, my R-b sticks for

Re: [Intel-gfx] [PATCH v8 2/2] drm/i915: Restrict qgv points which don't have enough bandwidth.

[James Ausmus]

On Fri, Oct 25, 2019 at 12:53:52PM +0300, Stanislav Lisovskiy wrote:
> According to BSpec 53998, we should try to
> restrict qgv points, which can't provide
> enough bandwidth for desired display configuration.
> 
> Currently we are just comparing against all of
> those and take minimum(worst case).
> 
> v2: Fixed wrong PCode reply mask, removed hardcoded
> values.
> 
> v3: Forbid simultaneous legacy SAGV PCode requests and
> restricting qgv points. Put the actual restriction
> to commit function, added serialization(thanks to Ville)
> to prevent commit being applied out of order in case of
> nonblocking and/or nomodeset commits.
> 
> v4:
>     - Minor code refactoring, fixed few typos(thanks to James Ausmus)
> - Change the naming of qgv point
>   masking/unmasking functions(James Ausmus).
> - Simplify the masking/unmasking operation itself,
>   as we don't need to mask only single point per request(James Ausmus)
> - Reject and stick to highest bandwidth point if SAGV
>   can't be enabled(BSpec)
> 
> v5:
> - Add new mailbox reply codes, which seems to happen during boot
>   time for TGL and indicate that QGV setting is not yet available.
> 
> v6:
>     - Increase number of supported QGV points to be in sync with BSpec.
> 
> Reviewed-by: James Ausmus 
> Signed-off-by: Stanislav Lisovskiy 
> Cc: Ville Syrjälä 
> Cc: James Ausmus 
> ---
>  drivers/gpu/drm/i915/display/intel_atomic.c   |  16 +++
>  drivers/gpu/drm/i915/display/intel_atomic.h   |   3 +
>  drivers/gpu/drm/i915/display/intel_bw.c   | 111 ++
>  drivers/gpu/drm/i915/display/intel_bw.h   |   2 +
>  drivers/gpu/drm/i915/display/intel_display.c  |  57 -
>  .../drm/i915/display/intel_display_types.h|   3 +
>  drivers/gpu/drm/i915/i915_drv.h   |   2 +
>  drivers/gpu/drm/i915/i915_reg.h   |   5 +
>  drivers/gpu/drm/i915/intel_sideband.c |  27 -
>  9 files changed, 198 insertions(+), 28 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c 
> b/drivers/gpu/drm/i915/display/intel_atomic.c
> index c5a552a69752..b3f4f02f380b 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> @@ -207,6 +207,22 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
>   return _state->base;
>  }
>  
> +int intel_atomic_serialize_global_state(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_crtc *crtc;
> +
> + for_each_intel_crtc(_priv->drm, crtc) {
> + struct intel_crtc_state *crtc_state;
> +
> + crtc_state = intel_atomic_get_crtc_state(>base, crtc);
> + if (IS_ERR(crtc_state))
> + return PTR_ERR(crtc_state);
> + }
> +
> + return 0;
> +}
> +
>  /**
>   * intel_crtc_destroy_state - destroy crtc state
>   * @crtc: drm crtc
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h 
> b/drivers/gpu/drm/i915/display/intel_atomic.h
> index 58065d3161a3..fd17b3ca257f 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.h
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.h
> @@ -7,6 +7,7 @@
>  #define __INTEL_ATOMIC_H__
>  
>  #include 
> +#include "intel_display_types.h"
>  
>  struct drm_atomic_state;
>  struct drm_connector;
> @@ -38,6 +39,8 @@ void intel_crtc_destroy_state(struct drm_crtc *crtc,
>  struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
>  void intel_atomic_state_clear(struct drm_atomic_state *state);
>  
> +int intel_atomic_serialize_global_state(struct intel_atomic_state *state);
> +
>  struct intel_crtc_state *
>  intel_atomic_get_crtc_state(struct drm_atomic_state *state,
>   struct intel_crtc *crtc);
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c 
> b/drivers/gpu/drm/i915/display/intel_bw.c
> index 22e83f857de8..60249d9776d1 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -8,14 +8,20 @@
>  #include "intel_bw.h"
>  #include "intel_display_types.h"
>  #include "intel_sideband.h"
> +#include "intel_atomic.h"
> +#include "intel_pm.h"
>  
>  /* Parameters for Qclk Geyserville (QGV) */
>  struct intel_qgv_point {
>   u16 dclk, t_rp, t_rdpre, t_rc, t_ras, t_rcd;
>  };
>  
> +
> +/* BSpec precisely defines this */
> +#define NUM_SAGV_POINTS 4

Shouldn't this be defined in intel_bw.h?

From what I'm seeing in BSpec 53998 (Gen12), in the
MAILBOX_GTDRIVER_CMD_SAGV_DE_MEM_SS_CONFIG 

Re: [Intel-gfx] [PATCH v4] drm/i915/cml: Remove unsupport PCI ID

[James Ausmus]

On Sat, Oct 26, 2019 at 04:32:25AM +0800, Lee Shawn C wrote:
> commit 'a7b4deeb02b9 ("drm/i915/cml: Add CML PCI IDS)'
> introduced new PCI ID that CML support. But some sku
> is not support yet so remove them.

A better description would be that some PCI IDs were removed from the
CML IDs in BSpec. The "not support yet" implies some i915 driver
problem, when this is just a sync w/ BSpec updates.

Thanks!

-James

> 
> v2: remove some inaccurate descriptions.
> v3: fix typo.
> v4: add missing version number.
> 
> Cc: Rodrigo Vivi 
> Cc: Jani Nikula 
> Cc: Lucas De Marchi 
> Cc: Anusha Srivatsa 
> Cc: Cooper Chiou 
> Signed-off-by: Lee Shawn C 
> ---
>  include/drm/i915_pciids.h | 4 
>  1 file changed, 4 deletions(-)
> 
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index a70c982ddff9..56e823cdc717 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -448,9 +448,7 @@
>  #define INTEL_CML_GT1_IDS(info)  \
>   INTEL_VGA_DEVICE(0x9B21, info), \
>   INTEL_VGA_DEVICE(0x9BAA, info), \
> - INTEL_VGA_DEVICE(0x9BAB, info), \
>   INTEL_VGA_DEVICE(0x9BAC, info), \
> - INTEL_VGA_DEVICE(0x9BA0, info), \
>   INTEL_VGA_DEVICE(0x9BA5, info), \
>   INTEL_VGA_DEVICE(0x9BA8, info), \
>   INTEL_VGA_DEVICE(0x9BA4, info), \
> @@ -460,9 +458,7 @@
>  #define INTEL_CML_GT2_IDS(info)  \
>   INTEL_VGA_DEVICE(0x9B41, info), \
>   INTEL_VGA_DEVICE(0x9BCA, info), \
> - INTEL_VGA_DEVICE(0x9BCB, info), \
>   INTEL_VGA_DEVICE(0x9BCC, info), \
> - INTEL_VGA_DEVICE(0x9BC0, info), \
>   INTEL_VGA_DEVICE(0x9BC5, info), \
>   INTEL_VGA_DEVICE(0x9BC8, info), \
>   INTEL_VGA_DEVICE(0x9BC4, info), \
> -- 
> 2.17.1
> 
> ___
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [PATCH v6 1/2] drm/i915: Refactor intel_can_enable_sagv

[James Ausmus]

On Wed, Oct 23, 2019 at 12:08:03PM +0300, Stanislav Lisovskiy wrote:
> Currently intel_can_enable_sagv function contains
> a mix of workarounds for different platforms
> some of them are not valid for gens >= 11 already,
> so lets split it into separate functions.
> 
> v2:
> - Rework watermark calculation algorithm to
>   attempt to calculate Level 0 watermark
>   with added sagv block time latency and
>   check if it fits in DBuf in order to
>   determine if SAGV can be enabled already
>   at this stage, just as BSpec 49325 states.
>   if that fails rollback to usual Level 0
>   latency and disable SAGV.
> - Remove unneeded tabs(James Ausmus)
> 
> v3: Rebased the patch
> 
> Signed-off-by: Stanislav Lisovskiy 
> Cc: Ville Syrjälä 
> Cc: James Ausmus 
> ---
>  .../drm/i915/display/intel_display_types.h|   8 +
>  drivers/gpu/drm/i915/intel_pm.c   | 228 +-
>  2 files changed, 228 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h 
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 8358152e403e..f09c80c96470 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -490,6 +490,13 @@ struct intel_atomic_state {
>*/
>   u8 active_pipe_changes;
>  
> + /*
> +  * For Gen12 only after calculating watermarks with
> +  * additional latency, we can determine if SAGV can be enabled
> +  * or not for that particular configuration.
> +  */
> + bool gen12_can_sagv;
> +
>   u8 active_pipes;
>   /* minimum acceptable cdclk for each pipe */
>   int min_cdclk[I915_MAX_PIPES];
> @@ -642,6 +649,7 @@ struct skl_plane_wm {
>   struct skl_wm_level wm[8];
>   struct skl_wm_level uv_wm[8];
>   struct skl_wm_level trans_wm;
> + struct skl_wm_level sagv_wm_l0;
>   bool is_planar;
>  };
>  
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 362234449087..c0419e4d83de 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3751,7 +3751,7 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
>   return 0;
>  }
>  
> -bool intel_can_enable_sagv(struct intel_atomic_state *state)
> +bool skl_can_enable_sagv(struct intel_atomic_state *state)
>  {
>   struct drm_device *dev = state->base.dev;
>   struct drm_i915_private *dev_priv = to_i915(dev);
> @@ -3817,6 +3817,75 @@ bool intel_can_enable_sagv(struct intel_atomic_state 
> *state)
>   return true;
>  }
>  
> +bool icl_can_enable_sagv(struct intel_atomic_state *state)
> +{
> + struct drm_device *dev = state->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + struct intel_crtc *crtc;
> + struct intel_crtc_state *new_crtc_state;
> + int level, latency;
> + int i;
> + int plane_id;
> +
> + if (!intel_has_sagv(dev_priv))
> + return false;
> +
> + /*
> +  * If there are no active CRTCs, no additional checks need be performed
> +  */
> + if (hweight8(state->active_pipes) == 0)
> + return true;
> +
> + for_each_new_intel_crtc_in_state(state, crtc,
> +  new_crtc_state, i) {
> +
> + if (crtc->base.state->adjusted_mode.flags & 
> DRM_MODE_FLAG_INTERLACE)
> + return false;
> +
> + if (!new_crtc_state->base.enable)
> + continue;
> +
> + for_each_plane_id_on_crtc(crtc, plane_id) {
> + struct skl_plane_wm *wm =
> + 
> _crtc_state->wm.skl.optimal.planes[plane_id];
> +
> + /* Skip this plane if it's not enabled */
> + if (!wm->wm[0].plane_en)
> + continue;
> +
> + /* Find the highest enabled wm level for this plane */
> + for (level = ilk_wm_max_level(dev_priv);
> +  !wm->wm[level].plane_en; --level)
> +  { }
> +
> + latency = dev_priv->wm.skl_latency[level];
> +
> + /*
> +  * If any of the planes on this pipe don't enable wm 
> levels that
> +  * incur memory latencies higher than 
> sagv_block_time_us we
> +  * can't enable SAGV.
> +  */
> + if (latency < dev_priv->sagv_block_time_us)
> +   

Re: [Intel-gfx] [PATCH v4 1/2] drm/i915: Refactor intel_can_enable_sagv

[James Ausmus]

On Fri, Oct 18, 2019 at 01:34:35AM -0700, Lisovskiy, Stanislav wrote:
> On Thu, 2019-10-17 at 14:53 -0700, James Ausmus wrote:
> > On Tue, Oct 15, 2019 at 04:50:12PM +0300, Stanislav Lisovskiy wrote:
> > > Currently intel_can_enable_sagv function contains
> > > a mix of workarounds for different platforms
> > > some of them are not valid for gens >= 11 already,
> > > so lets split it into separate functions.
> > > 
> > > Signed-off-by: Stanislav Lisovskiy 
> > > Cc: Ville Syrjälä 
> > > Cc: James Ausmus 
> > > ---
> > >  drivers/gpu/drm/i915/intel_pm.c | 73
> > > +++--
> > >  1 file changed, 70 insertions(+), 3 deletions(-)
> > > 
> > > +bool icl_can_enable_sagv(struct intel_atomic_state *state)
> > > +{
> > > + struct drm_device *dev = state->base.dev;
> > > + struct drm_i915_private *dev_priv = to_i915(dev);
> > > + struct intel_crtc *crtc;
> > > + struct intel_crtc_state *new_crtc_state;
> > > + int level, latency;
> > > + int i;
> > > + int plane_id;
> > > +
> > > + if (!intel_has_sagv(dev_priv))
> > > + return false;
> > > +
> > > + /*
> > > +  * If there are no active CRTCs, no additional checks need be
> > > performed
> > > +  */
> > > + if (hweight8(state->active_pipes) == 0)
> > > + return true;
> > > +
> > > + for_each_new_intel_crtc_in_state(state, crtc,
> > > +  new_crtc_state, i) {
> > > +
> > > + if (crtc->base.state->adjusted_mode.flags &
> > > DRM_MODE_FLAG_INTERLACE)
> > > + return false;
> > > +
> > > + if (!new_crtc_state->base.enable)
> > > + continue;
> > > +
> > > + for_each_plane_id_on_crtc(crtc, plane_id) {
> > > + struct skl_plane_wm *wm =
> > > + _crtc_state-
> > > >wm.skl.optimal.planes[plane_id];
> > > +
> > > + /* Skip this plane if it's not enabled */
> > > + if (!wm->wm[0].plane_en)
> > > + continue;
> > > +
> > > + /* Find the highest enabled wm level for this
> > > plane */
> > > + for (level = ilk_wm_max_level(dev_priv);
> > > +  !wm->wm[level].plane_en; --level)
> > > +  { }
> > > +
> > > + latency = dev_priv->wm.skl_latency[level];
> > 
> > This isn't exactly the same for TGL. From BSpec 49325, "Calculate
> > watermark level 0 with level 0 latency + SAGV block time. If the
> > result
> > can be supported (does not exceed maximum), then the plane can
> > tolerate
> > SAGV", so I think it can be simplified for Gen12+ by not having to
> > loop
> > through all the wm levels.
> > 
> > -James
> 
> Yes, we discussed that with Ville as I understood, properly doing
> that for TGL requires changes to watermark/ddb allocation algorithm,
> so that we check if dbuf can fit Level 0 watermark increased by SAGV
> block time. I was not sure whether should I add this patch to this
> series or proceed with that separately, probably this is worth adding
> here - however then it would require changes to watermark algorithm,
> as we need to recalculate min_ddb_alloc for Level 0 latency + SAGV
> and then check if we fit into DBuf again.
> So basically we'll have to calculate watermark level 0 twice - once for
> SAGV enabled and once for SAGV disabled case, I would probably do it 
> already during watermark calculations not when checking bandwidth and
> then set some "SAGV can enable" flag, which will be then used by
> intel_can_enable_sagv, so that we act accordingly when
> bandwidth check and restricting qgv points happens. For pre-gen 12 it
> will otherwise use the old algorithm.

OK, that works then. With the whitespace fix added:

Reviewed-by: James Ausmus 

> 
> > 
> > > +
> > > + /*
> > > +  * If any of the planes on this pipe don't
> > > enable wm levels that
> > > +  * incur memory latencies higher than
> > > sagv_block_time_us we
> > > +  * can't enable SAGV.
> > > +  */
> > > + if (latency < dev_priv->sagv_block_time_us)
> > > + return false;
> > > + }
> > > + }
> > > +
> > > + return true;
> > > +}
> > > +
> > > +bool intel_can_enable_sagv(struct intel_atomic_state *state)
> > > +{
> > > + struct drm_device *dev = state->base.dev;
> > > + struct drm_i915_private *dev_priv = to_i915(dev);
> > > +
> > > + if (INTEL_GEN(dev_priv) >= 11)
> > > + return icl_can_enable_sagv(state);
> > > +
> > > + return skl_can_enable_sagv(state);
> > > +}
> > > +
> > >  static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
> > > const struct intel_crtc_state
> > > *crtc_state,
> > > const u64 total_data_rate,
> > > -- 
> > > 2.17.1
> > > 
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Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/aml: Allow SPT PCH for all AML devices (rev2)

[James Ausmus]

On Fri, Oct 18, 2019 at 08:20:44AM +, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915/aml: Allow SPT PCH for all AML devices (rev2)
> URL   : https://patchwork.freedesktop.org/series/68176/
> State : success
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_7125_full -> Patchwork_14872_full
> 
> 
> Summary
> ---
> 
>   **SUCCESS**
> 
>   No regressions found.
> 

Anyone mind merging? :)

Thanks!

-James

>   
> 
> Possible new issues
> ---
> 
>   Here are the unknown changes that may have been introduced in 
> Patchwork_14872_full:
> 
> ### IGT changes ###
> 
>  Suppressed 
> 
>   The following results come from untrusted machines, tests, or statuses.
>   They do not affect the overall result.
> 
>   * igt@gem_render_copy@yf-tiled-ccs-to-x-tiled:
> - {shard-tglb}:   NOTRUN -> [INCOMPLETE][1] +1 similar issue
>[1]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14872/shard-tglb2/igt@gem_render_c...@yf-tiled-ccs-to-x-tiled.html
> 
>   * igt@kms_color@pipe-d-ctm-0-25:
> - {shard-tglb}:   NOTRUN -> [FAIL][2]
>[2]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14872/shard-tglb6/igt@kms_co...@pipe-d-ctm-0-25.html
> 
>   * {igt@kms_cursor_crc@pipe-d-cursor-512x512-onscreen}:
> - {shard-tglb}:   NOTRUN -> [SKIP][3] +3 similar issues
>[3]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14872/shard-tglb2/igt@kms_cursor_...@pipe-d-cursor-512x512-onscreen.html
> 
>   
> Known issues
> 
> 
>   Here are the changes found in Patchwork_14872_full that come from known 
> issues:
> 
> ### IGT changes ###
> 
>  Issues hit 
> 
>   * igt@gem_exec_schedule@preemptive-hang-bsd:
> - shard-iclb: [PASS][4] -> [SKIP][5] ([fdo#111325]) +3 similar 
> issues
>[4]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/shard-iclb8/igt@gem_exec_sched...@preemptive-hang-bsd.html
>[5]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14872/shard-iclb4/igt@gem_exec_sched...@preemptive-hang-bsd.html
> 
>   * igt@gem_exec_schedule@promotion-bsd1:
> - shard-iclb: [PASS][6] -> [SKIP][7] ([fdo#109276]) +5 similar 
> issues
>[6]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/shard-iclb2/igt@gem_exec_sched...@promotion-bsd1.html
>[7]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14872/shard-iclb6/igt@gem_exec_sched...@promotion-bsd1.html
> 
>   * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup:
> - shard-snb:  [PASS][8] -> [DMESG-WARN][9] ([fdo#111870])
>[8]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/shard-snb1/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy-gup.html
>[9]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14872/shard-snb1/igt@gem_userptr_bl...@map-fixed-invalidate-overlap-busy-gup.html
> 
>   * igt@gem_workarounds@suspend-resume:
> - shard-skl:  [PASS][10] -> [INCOMPLETE][11] ([fdo#104108])
>[10]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/shard-skl7/igt@gem_workarou...@suspend-resume.html
>[11]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14872/shard-skl6/igt@gem_workarou...@suspend-resume.html
> 
>   * igt@gem_workarounds@suspend-resume-context:
> - shard-apl:  [PASS][12] -> [DMESG-WARN][13] ([fdo#108566]) +3 
> similar issues
>[12]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/shard-apl8/igt@gem_workarou...@suspend-resume-context.html
>[13]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14872/shard-apl6/igt@gem_workarou...@suspend-resume-context.html
> 
>   * igt@i915_pm_rc6_residency@rc6-accuracy:
> - shard-kbl:  [PASS][14] -> [SKIP][15] ([fdo#109271])
>[14]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/shard-kbl3/igt@i915_pm_rc6_reside...@rc6-accuracy.html
>[15]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14872/shard-kbl7/igt@i915_pm_rc6_reside...@rc6-accuracy.html
> 
>   * igt@kms_cursor_crc@pipe-a-cursor-128x42-sliding:
> - shard-iclb: [PASS][16] -> [INCOMPLETE][17] ([fdo#107713])
>[16]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/shard-iclb1/igt@kms_cursor_...@pipe-a-cursor-128x42-sliding.html
>[17]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14872/shard-iclb7/igt@kms_cursor_...@pipe-a-cursor-128x42-sliding.html
> 
>   * igt@kms_flip@flip-vs-expired-vblank-interruptible:
> - shard-glk:  [PASS][18] -> [FAIL][19] ([fdo#105363])
>[18]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/shard-glk7/igt@kms_f...@flip-vs-expired-vblank-interruptible.html
>[19]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14872/shard-glk9/igt@kms_f...@flip-vs-expired-vblank-interruptible.html
> 
>   * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite:
> - shard-iclb: [PASS][20] -> [FAIL][21] ([fdo#103167]) +5 similar 

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/aml: Allow SPT PCH for all AML devices

[James Ausmus]

On Fri, Oct 18, 2019 at 01:00:59AM +, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915/aml: Allow SPT PCH for all AML devices
> URL   : https://patchwork.freedesktop.org/series/68176/
> State : failure
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_7125 -> Patchwork_14867
> 
> 
> Summary
> ---
> 
>   **FAILURE**
> 
>   Serious unknown changes coming with Patchwork_14867 absolutely need to be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the changes
>   introduced in Patchwork_14867, please notify your bug team to allow them
>   to document this new failure mode, which will reduce false positives in CI.
> 
>   External URL: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14867/index.html
> 
> Possible new issues
> ---
> 
>   Here are the unknown changes that may have been introduced in 
> Patchwork_14867:
> 
> ### IGT changes ###
> 
>  Possible regressions 
> 
>   * igt@i915_selftest@live_execlists:
> - fi-icl-u3:  NOTRUN -> [DMESG-FAIL][1]
>[1]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14867/fi-icl-u3/igt@i915_selftest@live_execlists.html
> - fi-skl-6600u:   [PASS][2] -> [DMESG-FAIL][3]
>[2]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-skl-6600u/igt@i915_selftest@live_execlists.html
>[3]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14867/fi-skl-6600u/igt@i915_selftest@live_execlists.html

Not related at all to this patch, hitting the retest button...

-James

> 
>   
> Known issues
> 
> 
>   Here are the changes found in Patchwork_14867 that come from known issues:
> 
> ### IGT changes ###
> 
>  Issues hit 
> 
>   * igt@gem_mmap_gtt@basic-read-write:
> - fi-icl-u3:  [PASS][4] -> [DMESG-WARN][5] ([fdo#107724])
>[4]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-u3/igt@gem_mmap_...@basic-read-write.html
>[5]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14867/fi-icl-u3/igt@gem_mmap_...@basic-read-write.html
> 
>   
>  Possible fixes 
> 
>   * igt@gem_mmap_gtt@basic-small-bo:
> - fi-icl-u3:  [DMESG-WARN][6] ([fdo#107724]) -> [PASS][7]
>[6]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-u3/igt@gem_mmap_...@basic-small-bo.html
>[7]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14867/fi-icl-u3/igt@gem_mmap_...@basic-small-bo.html
> 
>   * igt@i915_selftest@live_execlists:
> - fi-icl-u2:  [INCOMPLETE][8] ([fdo#107713]) -> [PASS][9]
>[8]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-u2/igt@i915_selftest@live_execlists.html
>[9]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14867/fi-icl-u2/igt@i915_selftest@live_execlists.html
> - fi-apl-guc: [DMESG-FAIL][10] -> [PASS][11]
>[10]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-apl-guc/igt@i915_selftest@live_execlists.html
>[11]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14867/fi-apl-guc/igt@i915_selftest@live_execlists.html
> - fi-skl-6260u:   [DMESG-FAIL][12] -> [PASS][13]
>[12]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-skl-6260u/igt@i915_selftest@live_execlists.html
>[13]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14867/fi-skl-6260u/igt@i915_selftest@live_execlists.html
> 
>   * igt@i915_selftest@live_hangcheck:
> - fi-icl-u3:  [INCOMPLETE][14] ([fdo#107713] / [fdo#108569]) -> 
> [PASS][15]
>[14]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
>[15]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14867/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
> - {fi-icl-u4}:[INCOMPLETE][16] ([fdo#107713] / [fdo#108569]) -> 
> [PASS][17]
>[16]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-u4/igt@i915_selftest@live_hangcheck.html
>[17]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14867/fi-icl-u4/igt@i915_selftest@live_hangcheck.html
> 
>   * igt@kms_chamelium@common-hpd-after-suspend:
> - fi-icl-u2:  [DMESG-WARN][18] ([fdo#102505] / [fdo#110390]) -> 
> [PASS][19]
>[18]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html
>[19]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14867/fi-icl-u2/igt@kms_chamel...@common-hpd-after-suspend.html
> 
>   
>  Warnings 
> 
>   * igt@kms_chamelium@common-hpd-after-suspend:
> - fi-kbl-7500u:   [DMESG-WARN][20] ([fdo#102505] / [fdo#103558] / 
> [fdo#105079] / [fdo#105602]) -> [DMESG-FAIL][21] ([fdo#102505] / [fdo#103375] 
> / [fdo#105079])
>[20]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7125/fi-kbl-7500u/igt@kms_chamel...@common-hpd-after-suspend.html
>[21]: 
> 

Re: [Intel-gfx] [PATCH v4 2/2] drm/i915: Restrict qgv points which don't have enough bandwidth.

[James Ausmus]

On Tue, Oct 15, 2019 at 04:50:13PM +0300, Stanislav Lisovskiy wrote:
> According to BSpec 53998, we should try to
> restrict qgv points, which can't provide
> enough bandwidth for desired display configuration.
> 
> Currently we are just comparing against all of
> those and take minimum(worst case).
> 
> v2: Fixed wrong PCode reply mask, removed hardcoded
> values.
> 
> v3: Forbid simultaneous legacy SAGV PCode requests and
> restricting qgv points. Put the actual restriction
> to commit function, added serialization(thanks to Ville)
> to prevent commit being applied out of order in case of
> nonblocking and/or nomodeset commits.
> 
> v4:
>     - Minor code refactoring, fixed few typos(thanks to James Ausmus)
> - Change the naming of qgv point
>   masking/unmasking functions(James Ausmus).
> - Simplify the masking/unmasking operation itself,
>   as we don't need to mask only single point per request(James Ausmus)
> - Reject and stick to highest bandwidth point if SAGV
>   can't be enabled(BSpec)
> 
> Signed-off-by: Stanislav Lisovskiy 
> Cc: Ville Syrjälä 
> Cc: James Ausmus 
> ---
>  drivers/gpu/drm/i915/display/intel_atomic.c   |  16 +++
>  drivers/gpu/drm/i915/display/intel_atomic.h   |   3 +
>  drivers/gpu/drm/i915/display/intel_bw.c   | 105 ++
>  drivers/gpu/drm/i915/display/intel_bw.h   |   2 +
>  drivers/gpu/drm/i915/display/intel_display.c  |  58 +-
>  .../drm/i915/display/intel_display_types.h|   3 +
>  drivers/gpu/drm/i915/i915_drv.h   |   2 +
>  drivers/gpu/drm/i915/i915_reg.h   |   3 +
>  8 files changed, 166 insertions(+), 26 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c 
> b/drivers/gpu/drm/i915/display/intel_atomic.c
> index c5a552a69752..b3f4f02f380b 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> @@ -207,6 +207,22 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
>   return _state->base;
>  }
>  
> +int intel_atomic_serialize_global_state(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_crtc *crtc;
> +
> + for_each_intel_crtc(_priv->drm, crtc) {
> + struct intel_crtc_state *crtc_state;
> +
> + crtc_state = intel_atomic_get_crtc_state(>base, crtc);
> + if (IS_ERR(crtc_state))
> + return PTR_ERR(crtc_state);
> + }
> +
> + return 0;
> +}
> +
>  /**
>   * intel_crtc_destroy_state - destroy crtc state
>   * @crtc: drm crtc
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h 
> b/drivers/gpu/drm/i915/display/intel_atomic.h
> index 58065d3161a3..fd17b3ca257f 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.h
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.h
> @@ -7,6 +7,7 @@
>  #define __INTEL_ATOMIC_H__
>  
>  #include 
> +#include "intel_display_types.h"
>  
>  struct drm_atomic_state;
>  struct drm_connector;
> @@ -38,6 +39,8 @@ void intel_crtc_destroy_state(struct drm_crtc *crtc,
>  struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
>  void intel_atomic_state_clear(struct drm_atomic_state *state);
>  
> +int intel_atomic_serialize_global_state(struct intel_atomic_state *state);
> +
>  struct intel_crtc_state *
>  intel_atomic_get_crtc_state(struct drm_atomic_state *state,
>   struct intel_crtc *crtc);
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c 
> b/drivers/gpu/drm/i915/display/intel_bw.c
> index 22e83f857de8..09f786cfdfaa 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -8,6 +8,8 @@
>  #include "intel_bw.h"
>  #include "intel_display_types.h"
>  #include "intel_sideband.h"
> +#include "intel_atomic.h"
> +#include "intel_pm.h"
>  
>  /* Parameters for Qclk Geyserville (QGV) */
>  struct intel_qgv_point {
> @@ -113,6 +115,27 @@ static int icl_pcode_read_qgv_point_info(struct 
> drm_i915_private *dev_priv,
>   return 0;
>  }
>  
> +int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
> +   u32 points_mask)
> +{
> + int ret;
> +
> + /* bspec says to keep retrying for at least 1 ms */
> + ret = skl_pcode_request(dev_priv, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
> + points_mask,
> + GEN11_PCODE_POINTS_RESTRICTED_MASK,
> + GEN11_PCODE_POINTS_RESTRICTED,
&g

Re: [Intel-gfx] [PATCH v4 1/2] drm/i915: Refactor intel_can_enable_sagv

[James Ausmus]

On Tue, Oct 15, 2019 at 04:50:12PM +0300, Stanislav Lisovskiy wrote:
> Currently intel_can_enable_sagv function contains
> a mix of workarounds for different platforms
> some of them are not valid for gens >= 11 already,
> so lets split it into separate functions.
> 
> Signed-off-by: Stanislav Lisovskiy 
> Cc: Ville Syrjälä 
> Cc: James Ausmus 
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 73 +++--
>  1 file changed, 70 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 67d171456f59..662a36ff2f43 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3750,7 +3750,7 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
>   return 0;
>  }
>  
> -bool intel_can_enable_sagv(struct intel_atomic_state *state)
> +bool skl_can_enable_sagv(struct intel_atomic_state *state)
>  {
>   struct drm_device *dev = state->base.dev;
>   struct drm_i915_private *dev_priv = to_i915(dev);
> @@ -3801,8 +3801,8 @@ bool intel_can_enable_sagv(struct intel_atomic_state 
> *state)
>  
>   if (skl_needs_memory_bw_wa(dev_priv) &&
>   plane->base.state->fb->modifier ==
> - I915_FORMAT_MOD_X_TILED)
> - latency += 15;
> + I915_FORMAT_MOD_X_TILED)
> + latency += 15;

This whitespace change doesn't look right

>  
>   /*
>* If any of the planes on this pipe don't enable wm levels that
> @@ -3816,6 +3816,73 @@ bool intel_can_enable_sagv(struct intel_atomic_state 
> *state)
>   return true;
>  }
>  
> +bool icl_can_enable_sagv(struct intel_atomic_state *state)
> +{
> + struct drm_device *dev = state->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + struct intel_crtc *crtc;
> + struct intel_crtc_state *new_crtc_state;
> + int level, latency;
> + int i;
> + int plane_id;
> +
> + if (!intel_has_sagv(dev_priv))
> + return false;
> +
> + /*
> +  * If there are no active CRTCs, no additional checks need be performed
> +  */
> + if (hweight8(state->active_pipes) == 0)
> + return true;
> +
> + for_each_new_intel_crtc_in_state(state, crtc,
> +  new_crtc_state, i) {
> +
> + if (crtc->base.state->adjusted_mode.flags & 
> DRM_MODE_FLAG_INTERLACE)
> + return false;
> +
> + if (!new_crtc_state->base.enable)
> + continue;
> +
> + for_each_plane_id_on_crtc(crtc, plane_id) {
> + struct skl_plane_wm *wm =
> + 
> _crtc_state->wm.skl.optimal.planes[plane_id];
> +
> + /* Skip this plane if it's not enabled */
> + if (!wm->wm[0].plane_en)
> + continue;
> +
> + /* Find the highest enabled wm level for this plane */
> + for (level = ilk_wm_max_level(dev_priv);
> +  !wm->wm[level].plane_en; --level)
> +  { }
> +
> + latency = dev_priv->wm.skl_latency[level];

This isn't exactly the same for TGL. From BSpec 49325, "Calculate
watermark level 0 with level 0 latency + SAGV block time. If the result
can be supported (does not exceed maximum), then the plane can tolerate
SAGV", so I think it can be simplified for Gen12+ by not having to loop
through all the wm levels.

-James

> +
> + /*
> +  * If any of the planes on this pipe don't enable wm 
> levels that
> +  * incur memory latencies higher than 
> sagv_block_time_us we
> +  * can't enable SAGV.
> +  */
> + if (latency < dev_priv->sagv_block_time_us)
> + return false;
> + }
> + }
> +
> + return true;
> +}
> +
> +bool intel_can_enable_sagv(struct intel_atomic_state *state)
> +{
> + struct drm_device *dev = state->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> +
> + if (INTEL_GEN(dev_priv) >= 11)
> + return icl_can_enable_sagv(state);
> +
> + return skl_can_enable_sagv(state);
> +}
> +
>  static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
> const struct intel_crtc_state *crtc_state,
> const u64 total_data_rate,
> -- 
> 2.17.1
> 
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[Intel-gfx] [PATCH] drm/i915/aml: Allow SPT PCH for all AML devices

[James Ausmus]

Even the AML devices that behave like CFLs can be paired with an SPT
PCH. Allow this to happen without blowing up dmesg.

BSpec: 33665

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=112013
Cc: Quanxian Wang 
Cc: Rodrigo Vivi 
Signed-off-by: James Ausmus 
---
 drivers/gpu/drm/i915/intel_pch.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c
index 1035d3d46fd8..bb1cb6f12a50 100644
--- a/drivers/gpu/drm/i915/intel_pch.c
+++ b/drivers/gpu/drm/i915/intel_pch.c
@@ -52,7 +52,8 @@ intel_pch_type(const struct drm_i915_private *dev_priv, 
unsigned short id)
return PCH_SPT;
case INTEL_PCH_SPT_LP_DEVICE_ID_TYPE:
DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
-   WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
+   WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv) &&
+   !IS_COFFEELAKE(dev_priv));
return PCH_SPT;
case INTEL_PCH_KBP_DEVICE_ID_TYPE:
DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n");
-- 
2.23.0

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Re: [Intel-gfx] [PATCH v3] drm/i915: Restrict qgv points which don't have enough bandwidth.

[James Ausmus]

On Mon, Oct 14, 2019 at 05:50:18PM +0300, Ville Syrjälä wrote:
> On Mon, Oct 14, 2019 at 02:13:31PM +0300, Lisovskiy, Stanislav wrote:
> > On Fri, 2019-10-11 at 16:49 -0700, James Ausmus wrote:
> > > > +   new_qgv_points_mask |= new_mask_bit;
> > > > +   }
> > > > +
> > > > +   ret = icl_pcode_restrict_qgv_points(dev_priv,
> > > > new_qgv_points_mask);
> > > > +   if (ret < 0)
> > > > +   DRM_DEBUG_KMS("Could not restrict required gqv
> > > > points(%d)\n", ret);
> > > 
> > > s/gqv/qgv/
> > > 
> > > 
> > > Also, if we fail masking off the qgv points that can't support our BW
> > > req, shouldn't we handle that failure somehow - maybe just disable
> > > SAGV
> > > entirely?  Better we lose power than have flickering screens...
> 
> Sounds like dead code to me. My approach is: don't deal with hw/firmware
> failures until they are proven to exist.
> 
> The debug msg should be an error so that we get a bug report if this
> ever happens.

That works - however, I think we should return the error rather than
continuing.

-James

> 
> -- 
> Ville Syrjälä
> Intel
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Re: [Intel-gfx] [PATCH v3] drm/i915: Restrict qgv points which don't have enough bandwidth.

[James Ausmus]

On Mon, Oct 14, 2019 at 04:13:31AM -0700, Lisovskiy, Stanislav wrote:
> On Fri, 2019-10-11 at 16:49 -0700, James Ausmus wrote:
> > On Wed, Sep 25, 2019 at 03:17:37PM +0300, Stanislav Lisovskiy wrote:
> > > According to BSpec 53998, we should try to
> > > restrict qgv points, which can't provide
> > > enough bandwidth for desired display configuration.
> > > 
> > > Currently we are just comparing against all of
> > > those and take minimum(worst case).
> > > 
> > > v2: Fixed wrong PCode reply mask, removed hardcoded
> > > values.
> > > 
> > > v3: Forbid simultaneous legacy SAGV PCode requests and
> > > restricting qgv points. Put the actual restriction
> > > to commit function, added serialization(thanks to Ville)
> > > to prevent commit being applied out of order in case of
> > > nonblocking and/or nomodeset commits.
> 
> Hi James,
> 
> Thank you for great review! 
> 
> While many of your comments are definitely
> good findings, still will leave reply to a few,
> just to keep things clear.
> 
> 
> > > 
> > > Signed-off-by: Stanislav Lisovskiy 
> > > Cc: Ville Syrjälä 
> > > Cc: James Ausmus 
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_atomic.c   | 16 
> > >  drivers/gpu/drm/i915/display/intel_atomic.h   |  3 +
> > >  drivers/gpu/drm/i915/display/intel_bw.c   | 79 +
> > > --
> > >  drivers/gpu/drm/i915/display/intel_bw.h   |  2 +
> > >  drivers/gpu/drm/i915/display/intel_display.c  | 78
> > > +-
> > >  .../drm/i915/display/intel_display_types.h|  3 +
> > >  drivers/gpu/drm/i915/i915_drv.h   |  2 +
> > >  drivers/gpu/drm/i915/i915_reg.h   |  3 +
> > >  8 files changed, 160 insertions(+), 26 deletions(-)
> 
> > if (max_data_rate >= data_rate)
> > allowed_points |= 1 << i;
> > DRM_DEBUG_KMS...
> > 
> > > + allowed_points |= 1 << i;
> > > + }
> > 
> > According to the BSpec page, we also need to save off the QGV point
> > that has
> > the most available bandwidth:
> > 
> > "At least one GV point must always remain unmasked. The point
> > providing the
> > highest bandwidth for display must always remain unmasked."
> > 
> > We should stash that point separately, and ensure it always remains
> > unmasked.
> > 
> > > + }
> > > +
> > > + if (allowed_points == 0) {
> > > + DRM_DEBUG_KMS("Could not find any suitable QGV
> > > points\n");
> > >   return -EINVAL;
> > >   }
> 
> This actually guarantees that, I think - we will never allow a 
> config which will require us to mask all of the points to work.

Yeah, fair enough - if *any* points allow a high enough bandwidth, then
it's certain that the *highest* BW point will be unmasked. If *no*
points allow enough BW, then it doesn't matter anyway because we're
going to fail out and not allow that config...

Thanks!

-James

> 
> > >  
> > > + state->qgv_points_mask = (~allowed_points) & ((1 <<
> > > qi.num_points) - 1);
> > > +
> > > + /*
> > > +  * If the actual mask had changed we need to make sure that
> > > +  * the commits are serialized(in case this is a nomodeset,
> > > nonblocking)
> > > +  */
> > > + if (state->qgv_points_mask != dev_priv->qgv_points_mask) {
> > > + ret = intel_atomic_serialize_global_state(state);
> > > + if (ret) {
> > > + DRM_DEBUG_KMS("Could not serialize global
> > > state\n");
> > > + return ret;
> > > + }
> > > + }
> > > +
> > >   return 0;
> > >  }
> > >  
> > > diff --git a/drivers/gpu/drm/i915/display/intel_bw.h
> > > b/drivers/gpu/drm/i915/display/intel_bw.h
> > > index 9db10af012f4..66bf9bc10b73 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_bw.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> > > @@ -28,5 +28,7 @@ int intel_bw_init(struct drm_i915_private
> > > *dev_priv);
> > >  int intel_bw_atomic_check(struct intel_atomic_state *state);
> > >  void intel_bw_crtc_update(struct intel_bw_state *bw_state,
> > > const struct intel_crtc_state *crtc_state);
> > > +int icl_pcode_restrict_qgv_points(struct drm_i915_private
> > > *dev_priv,
> >

Re: [Intel-gfx] [PATCH v3] drm/i915: Restrict qgv points which don't have enough bandwidth.

[James Ausmus]

On Wed, Sep 25, 2019 at 03:17:37PM +0300, Stanislav Lisovskiy wrote:
> According to BSpec 53998, we should try to
> restrict qgv points, which can't provide
> enough bandwidth for desired display configuration.
> 
> Currently we are just comparing against all of
> those and take minimum(worst case).
> 
> v2: Fixed wrong PCode reply mask, removed hardcoded
> values.
> 
> v3: Forbid simultaneous legacy SAGV PCode requests and
> restricting qgv points. Put the actual restriction
> to commit function, added serialization(thanks to Ville)
> to prevent commit being applied out of order in case of
> nonblocking and/or nomodeset commits.
> 
> Signed-off-by: Stanislav Lisovskiy 
> Cc: Ville Syrjälä 
> Cc: James Ausmus 
> ---
>  drivers/gpu/drm/i915/display/intel_atomic.c   | 16 
>  drivers/gpu/drm/i915/display/intel_atomic.h   |  3 +
>  drivers/gpu/drm/i915/display/intel_bw.c   | 79 +--
>  drivers/gpu/drm/i915/display/intel_bw.h   |  2 +
>  drivers/gpu/drm/i915/display/intel_display.c  | 78 +-
>  .../drm/i915/display/intel_display_types.h|  3 +
>  drivers/gpu/drm/i915/i915_drv.h   |  2 +
>  drivers/gpu/drm/i915/i915_reg.h   |  3 +
>  8 files changed, 160 insertions(+), 26 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c 
> b/drivers/gpu/drm/i915/display/intel_atomic.c
> index 698802da07b7..903537c4fb0f 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> @@ -208,6 +208,22 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
>   return _state->base;
>  }
>  
> +int intel_atomic_serialize_global_state(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_crtc *crtc;
> +
> + for_each_intel_crtc(_priv->drm, crtc) {
> + struct intel_crtc_state *crtc_state;
> +
> + crtc_state = intel_atomic_get_crtc_state(>base, crtc);
> + if (IS_ERR(crtc_state))
> + return PTR_ERR(crtc_state);
> + }
> +
> + return 0;
> +}
> +

I'll leave reviewing the atomic serialization bits to Ville and I'll
just review the rest, as I don't have a good head for atomic at this
point...


>  /**
>   * intel_crtc_destroy_state - destroy crtc state
>   * @crtc: drm crtc
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h 
> b/drivers/gpu/drm/i915/display/intel_atomic.h
> index 58065d3161a3..fd17b3ca257f 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.h
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.h
> @@ -7,6 +7,7 @@
>  #define __INTEL_ATOMIC_H__
>  
>  #include 
> +#include "intel_display_types.h"
>  
>  struct drm_atomic_state;
>  struct drm_connector;
> @@ -38,6 +39,8 @@ void intel_crtc_destroy_state(struct drm_crtc *crtc,
>  struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
>  void intel_atomic_state_clear(struct drm_atomic_state *state);
>  
> +int intel_atomic_serialize_global_state(struct intel_atomic_state *state);
> +
>  struct intel_crtc_state *
>  intel_atomic_get_crtc_state(struct drm_atomic_state *state,
>   struct intel_crtc *crtc);
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c 
> b/drivers/gpu/drm/i915/display/intel_bw.c
> index cd58e47ab7b2..81e3468306fa 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -8,6 +8,7 @@
>  #include "intel_bw.h"
>  #include "intel_display_types.h"
>  #include "intel_sideband.h"
> +#include "intel_atomic.h"
>  
>  /* Parameters for Qclk Geyserville (QGV) */
>  struct intel_qgv_point {
> @@ -90,6 +91,27 @@ static int icl_pcode_read_qgv_point_info(struct 
> drm_i915_private *dev_priv,
>   return 0;
>  }
>  
> +int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
> +   u32 points_mask)
> +{
> + int ret;
> +
> + /* bspec says to keep retrying for at least 1 ms */
> + ret = skl_pcode_request(dev_priv, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
> + points_mask,
> + GEN11_PCODE_POINTS_RESTRICTED_MASK,
> + GEN11_PCODE_POINTS_RESTRICTED,
> + 1);
> +
> + if (ret < 0) {
> + DRM_ERROR("Failed to disable qgv points (%d)\n", ret);
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +
>  static int icl_get_qgv_points(struct drm_i915_private *dev_priv,

Re: [Intel-gfx] [PATCH] drm/i915/cml: Add second PCH ID for CMP

[James Ausmus]

On Wed, Oct 09, 2019 at 01:00:07PM -0700, Rodrigo Vivi wrote:
> On Wed, Oct 09, 2019 at 10:29:43AM -0700, Matt Roper wrote:
> > On Wed, Oct 09, 2019 at 10:03:31AM +0300, Timo Aaltonen wrote:
> > > On 17.9.2019 2.32, Matt Roper wrote:
> > > > The CMP PCH ID we have in the driver is correct for the CML-U machines 
> > > > we have
> > > > in our CI system, but the CML-S and CML-H CI machines appear to use a
> > > > different PCH ID, leading our driver to detect no PCH for them.
> > > > 
> > > > Cc: Rodrigo Vivi 
> > > > Cc: Anusha Srivatsa 
> > > > References: 729ae330a0f2e2 ("drm/i915/cml: Introduce Comet Lake PCH")
> > > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111461
> > > > Signed-off-by: Matt Roper 
> > 
> > Cc: drm-intel-fi...@lists.freedesktop.org
> 
> I don't believe this list even exist anymore.
> 
> The right way would be:
> 
> Fixes: 729ae330a0f2e2 ("drm/i915/cml: Introduce Comet Lake PCH")

Hmm - just curious on the semantics, as the "Fixes" tag implies that the
original patch was broken, but it wasn't - just new PCH IDs have been
added since.

-James

> 
> instead of References
> 
> > 
> > > > ---
> > > >  drivers/gpu/drm/i915/intel_pch.c | 1 +
> > > >  drivers/gpu/drm/i915/intel_pch.h | 1 +
> > > >  2 files changed, 2 insertions(+)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/intel_pch.c 
> > > > b/drivers/gpu/drm/i915/intel_pch.c
> > > > index fa864d8f2b73..15f8bff141f9 100644
> > > > --- a/drivers/gpu/drm/i915/intel_pch.c
> > > > +++ b/drivers/gpu/drm/i915/intel_pch.c
> > > > @@ -69,6 +69,7 @@ intel_pch_type(const struct drm_i915_private 
> > > > *dev_priv, unsigned short id)
> > > > WARN_ON(!IS_CANNONLAKE(dev_priv) && 
> > > > !IS_COFFEELAKE(dev_priv));
> > > > return PCH_CNP;
> > > > case INTEL_PCH_CMP_DEVICE_ID_TYPE:
> > > > +   case INTEL_PCH_CMP2_DEVICE_ID_TYPE:
> > > > DRM_DEBUG_KMS("Found Comet Lake PCH (CMP)\n");
> > > > WARN_ON(!IS_COFFEELAKE(dev_priv));
> > > > /* CometPoint is CNP Compatible */
> > > > diff --git a/drivers/gpu/drm/i915/intel_pch.h 
> > > > b/drivers/gpu/drm/i915/intel_pch.h
> > > > index e6a2d65f19c6..c29c81ec7971 100644
> > > > --- a/drivers/gpu/drm/i915/intel_pch.h
> > > > +++ b/drivers/gpu/drm/i915/intel_pch.h
> > > > @@ -41,6 +41,7 @@ enum intel_pch {
> > > >  #define INTEL_PCH_CNP_DEVICE_ID_TYPE   0xA300
> > > >  #define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE0x9D80
> > > >  #define INTEL_PCH_CMP_DEVICE_ID_TYPE   0x0280
> > > > +#define INTEL_PCH_CMP2_DEVICE_ID_TYPE  0x0680
> > > >  #define INTEL_PCH_ICP_DEVICE_ID_TYPE   0x3480
> > > >  #define INTEL_PCH_MCC_DEVICE_ID_TYPE   0x4B00
> > > >  #define INTEL_PCH_MCC2_DEVICE_ID_TYPE  0x3880
> > > 
> > > Hi,
> > > 
> > > Please add this in -fixes so 5.4 will get it, thanks.
> > > 
> > > 
> > > -- 
> > > t
> > 
> > -- 
> > Matt Roper
> > Graphics Software Engineer
> > VTT-OSGC Platform Enablement
> > Intel Corporation
> > (916) 356-2795
> ___
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/2] drm/i915: Move SAGV block time to dev_priv

[James Ausmus]

On Wed, Oct 09, 2019 at 06:15:26PM +, Patchwork wrote:
> == Series Details ==
> 
> Series: series starting with [CI,1/2] drm/i915: Move SAGV block time to 
> dev_priv
> URL   : https://patchwork.freedesktop.org/series/67799/
> State : failure
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_7043 -> Patchwork_14730
> 
> 
> Summary
> ---
> 
>   **FAILURE**
> 
>   Serious unknown changes coming with Patchwork_14730 absolutely need to be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the changes
>   introduced in Patchwork_14730, please notify your bug team to allow them
>   to document this new failure mode, which will reduce false positives in CI.
> 
>   External URL: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14730/index.html
> 
> Possible new issues
> ---
> 
>   Here are the unknown changes that may have been introduced in 
> Patchwork_14730:
> 
> ### IGT changes ###
> 
>  Possible regressions 
> 
>   * igt@i915_selftest@live_coherency:
> - fi-glk-dsi: [PASS][1] -> [TIMEOUT][2]
>[1]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7043/fi-glk-dsi/igt@i915_selftest@live_coherency.html
>[2]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14730/fi-glk-dsi/igt@i915_selftest@live_coherency.html

This isn't related - I'll hit the retest button...

> 
>   
> Known issues
> 
> 
>   Here are the changes found in Patchwork_14730 that come from known issues:
> 
> ### IGT changes ###
> 
>  Issues hit 
> 
>   * igt@gem_close_race@basic-threads:
> - fi-bxt-dsi: [PASS][3] -> [INCOMPLETE][4] ([fdo#103927])
>[3]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7043/fi-bxt-dsi/igt@gem_close_r...@basic-threads.html
>[4]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14730/fi-bxt-dsi/igt@gem_close_r...@basic-threads.html
> 
>   * igt@gem_ctx_switch@legacy-render:
> - fi-icl-u2:  [PASS][5] -> [INCOMPLETE][6] ([fdo#107713] / 
> [fdo#111381])
>[5]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7043/fi-icl-u2/igt@gem_ctx_swi...@legacy-render.html
>[6]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14730/fi-icl-u2/igt@gem_ctx_swi...@legacy-render.html
> 
>   * igt@i915_selftest@live_hangcheck:
> - fi-bsw-kefka:   [PASS][7] -> [INCOMPLETE][8] ([fdo#105876])
>[7]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7043/fi-bsw-kefka/igt@i915_selftest@live_hangcheck.html
>[8]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14730/fi-bsw-kefka/igt@i915_selftest@live_hangcheck.html
> 
>   * igt@kms_chamelium@hdmi-hpd-fast:
> - fi-kbl-7500u:   [PASS][9] -> [FAIL][10] ([fdo#111045] / 
> [fdo#111096])
>[9]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7043/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
>[10]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14730/fi-kbl-7500u/igt@kms_chamel...@hdmi-hpd-fast.html
> 
>   
>  Possible fixes 
> 
>   * igt@gem_sync@basic-many-each:
> - {fi-tgl-u}: [INCOMPLETE][11] ([fdo#111880]) -> [PASS][12]
>[11]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7043/fi-tgl-u/igt@gem_s...@basic-many-each.html
>[12]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14730/fi-tgl-u/igt@gem_s...@basic-many-each.html
> 
>   
>   {name}: This element is suppressed. This means it is ignored when computing
>   the status of the difference (SUCCESS, WARNING, or FAILURE).
> 
>   [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
>   [fdo#105876]: https://bugs.freedesktop.org/show_bug.cgi?id=105876
>   [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
>   [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
>   [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
>   [fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
>   [fdo#111880]: https://bugs.freedesktop.org/show_bug.cgi?id=111880
> 
> 
> Participating hosts (54 -> 45)
> --
> 
>   Missing(9): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan 
> fi-byt-clapper fi-icl-u3 fi-icl-y fi-icl-dsi fi-bdw-samus 
> 
> 
> Build changes
> -
> 
>   * CI: CI-20190529 -> None
>   * Linux: CI_DRM_7043 -> Patchwork_14730
> 
>   CI-20190529: 20190529
>   CI_DRM_7043: ed6c47dff498138cd3494c95a107c5787094b0b9 @ 
> git://anongit.freedesktop.org/gfx-ci/linux
>   IGT_5219: e501741f2e2b086a8c55d9f278c630ce68ad5fe1 @ 
> git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
>   Patchwork_14730: e95a4493c64678635694717b5bfb47c04faba383 @ 
> git://anongit.freedesktop.org/gfx-ci/linux
> 
> 
> == Linux commits ==
> 
> e95a4493c646 drm/i915/tgl: Read SAGV block time from PCODE
> e6a4842921d1 drm/i915: Move SAGV block time to dev_priv
> 
> == Logs ==
> 
> For more details see: 
> 

[Intel-gfx] [CI v3 2/2] drm/i915/tgl: Read SAGV block time from PCODE

[James Ausmus]

Starting from TGL, we now need to read the SAGV block time via a PCODE
mailbox, rather than having a static value.

BSpec: 49326

v2: Fix up pcode val data type (Ville), tighten variable scope (Ville)

Cc: Ville Syrjälä 
Cc: Stanislav Lisovskiy 
Cc: Lucas De Marchi 
Signed-off-by: James Ausmus 
Reviewed-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_reg.h |  1 +
 drivers/gpu/drm/i915/intel_pm.c | 15 ++-
 2 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1dc067fc57ab..0fb9030b89f1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8878,6 +8878,7 @@ enum {
 #define GEN9_SAGV_DISABLE  0x0
 #define GEN9_SAGV_IS_DISABLED  0x1
 #define GEN9_SAGV_ENABLE   0x3
+#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US0x23
 #define GEN6_PCODE_DATA_MMIO(0x138128)
 #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT   8
 #define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0ffcafe97216..e2aca3e81d28 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3645,7 +3645,20 @@ intel_has_sagv(struct drm_i915_private *dev_priv)
 static void
 skl_setup_sagv_block_time(struct drm_i915_private *dev_priv)
 {
-   if (IS_GEN(dev_priv, 11)) {
+   if (INTEL_GEN(dev_priv) >= 12) {
+   u32 val = 0;
+   int ret;
+
+   ret = sandybridge_pcode_read(dev_priv,
+
GEN12_PCODE_READ_SAGV_BLOCK_TIME_US,
+, NULL);
+   if (!ret) {
+   dev_priv->sagv_block_time_us = val;
+   return;
+   }
+
+   DRM_DEBUG_DRIVER("Couldn't read SAGV block time!\n");
+   } else if (IS_GEN(dev_priv, 11)) {
dev_priv->sagv_block_time_us = 10;
return;
} else if (IS_GEN(dev_priv, 10)) {
-- 
2.22.1

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[Intel-gfx] [CI v3 1/2] drm/i915: Move SAGV block time to dev_priv

[James Ausmus]

In prep for newer platforms having more complicated ways to determine
the SAGV block time, move the variable to dev_priv, and extract the
setting to an initial setup function. While we're at it, update the if
ladder to follow the new gen -> old gen order preference, and warn on
any non-specified gen.

v2: Shorten the function name (Ville), return directly (Ville), move
sagv_block_time_us value to dev_priv (Ville)

v3: Change sagv_block_time_us to u32 (Lucas), Change fallback value to
-1 (Lucas), use intel_has_sagv for setup check rather than hand-rolling
(Lucas)

Cc: Ville Syrjälä 
Cc: Stanislav Lisovskiy 
Cc: Lucas De Marchi 
Signed-off-by: James Ausmus 
Reviewed-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_drv.h |  2 ++
 drivers/gpu/drm/i915/intel_pm.c | 33 -
 2 files changed, 26 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bcfb355aab4d..cb747706d469 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1266,6 +1266,8 @@ struct drm_i915_private {
I915_SAGV_NOT_CONTROLLED
} sagv_status;
 
+   u32 sagv_block_time_us;
+
struct {
/*
 * Raw watermark latency values:
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index bfcf03ab5245..0ffcafe97216 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3642,6 +3642,26 @@ intel_has_sagv(struct drm_i915_private *dev_priv)
dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
 }
 
+static void
+skl_setup_sagv_block_time(struct drm_i915_private *dev_priv)
+{
+   if (IS_GEN(dev_priv, 11)) {
+   dev_priv->sagv_block_time_us = 10;
+   return;
+   } else if (IS_GEN(dev_priv, 10)) {
+   dev_priv->sagv_block_time_us = 20;
+   return;
+   } else if (IS_GEN(dev_priv, 9)) {
+   dev_priv->sagv_block_time_us = 30;
+   return;
+   } else {
+   MISSING_CASE(INTEL_GEN(dev_priv));
+   }
+
+   /* Default to an unusable block time */
+   dev_priv->sagv_block_time_us = -1;
+}
+
 /*
  * SAGV dynamically adjusts the system agent voltage and clock frequencies
  * depending on power and performance requirements. The display engine access
@@ -3730,18 +3750,10 @@ bool intel_can_enable_sagv(struct intel_atomic_state 
*state)
struct intel_crtc_state *crtc_state;
enum pipe pipe;
int level, latency;
-   int sagv_block_time_us;
 
if (!intel_has_sagv(dev_priv))
return false;
 
-   if (IS_GEN(dev_priv, 9))
-   sagv_block_time_us = 30;
-   else if (IS_GEN(dev_priv, 10))
-   sagv_block_time_us = 20;
-   else
-   sagv_block_time_us = 10;
-
/*
 * If there are no active CRTCs, no additional checks need be performed
 */
@@ -3788,7 +3800,7 @@ bool intel_can_enable_sagv(struct intel_atomic_state 
*state)
 * incur memory latencies higher than sagv_block_time_us we
 * can't enable SAGV.
 */
-   if (latency < sagv_block_time_us)
+   if (latency < dev_priv->sagv_block_time_us)
return false;
}
 
@@ -9013,6 +9025,9 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
else if (IS_GEN(dev_priv, 5))
i915_ironlake_get_mem_freq(dev_priv);
 
+   if (intel_has_sagv(dev_priv))
+   skl_setup_sagv_block_time(dev_priv);
+
/* For FIFO watermark updates */
if (INTEL_GEN(dev_priv) >= 9) {
skl_setup_wm_latency(dev_priv);
-- 
2.22.1

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Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/tgl: Read SAGV block time from PCODE

[James Ausmus]

On Mon, Oct 07, 2019 at 01:15:24PM +0300, Ville Syrjälä wrote:
> On Fri, Oct 04, 2019 at 02:51:34PM -0700, James Ausmus wrote:
> > On Fri, Oct 04, 2019 at 01:55:46PM -0700, Lucas De Marchi wrote:
> > > On Fri, Sep 27, 2019 at 03:24:27PM -0700, James Ausmus wrote:
> > > >Starting from TGL, we now need to read the SAGV block time via a PCODE
> > > >mailbox, rather than having a static value.
> > > >
> > > >BSpec: 49326
> > > >
> > > >v2: Fix up pcode val data type (Ville), tighten variable scope (Ville)
> > > >
> > > >Cc: Ville Syrjälä 
> > > >Cc: Stanislav Lisovskiy 
> > > >Cc: Lucas De Marchi 
> > > >Signed-off-by: James Ausmus 
> > > >Reviewed-by: Ville Syrjälä 
> > > >---
> > > > drivers/gpu/drm/i915/i915_reg.h |  1 +
> > > > drivers/gpu/drm/i915/intel_pm.c | 15 ++-
> > > > 2 files changed, 15 insertions(+), 1 deletion(-)
> > > >
> > > >diff --git a/drivers/gpu/drm/i915/i915_reg.h 
> > > >b/drivers/gpu/drm/i915/i915_reg.h
> > > >index 058aa5ca8b73..6a45df9dad9c 100644
> > > >--- a/drivers/gpu/drm/i915/i915_reg.h
> > > >+++ b/drivers/gpu/drm/i915/i915_reg.h
> > > >@@ -8869,6 +8869,7 @@ enum {
> > > > #define GEN9_SAGV_DISABLE   0x0
> > > > #define GEN9_SAGV_IS_DISABLED   0x1
> > > > #define GEN9_SAGV_ENABLE0x3
> > > >+#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
> > > > #define GEN6_PCODE_DATA _MMIO(0x138128)
> > > > #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT8
> > > > #define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT  16
> > > >diff --git a/drivers/gpu/drm/i915/intel_pm.c 
> > > >b/drivers/gpu/drm/i915/intel_pm.c
> > > >index b413a7f3bc5d..13721ba44013 100644
> > > >--- a/drivers/gpu/drm/i915/intel_pm.c
> > > >+++ b/drivers/gpu/drm/i915/intel_pm.c
> > > >@@ -3645,7 +3645,20 @@ intel_has_sagv(struct drm_i915_private *dev_priv)
> > > > static void
> > > > skl_setup_sagv_block_time(struct drm_i915_private *dev_priv)
> > > > {
> > > >-if (IS_GEN(dev_priv, 11)) {
> > > >+if (INTEL_GEN(dev_priv) >= 12) {
> > > 
> > > sagv will still never be enabled for TGL. Are you going to revert 
> > > 8ffa4392a32e ("drm/i915/tgl: disable SAGV temporarily")
> > > in a separete patch?
> > 
> > Yes, that's the idea - we land these two patches, then once HSD
> > 1409542895 gets resolved, we revert 8ffa4392a32e and everything Just
> > Works. ;)
> 
> The whole sagv stuff is wrong for icl+. Stan is attempting to remedy
> that.

Well, we'll at least need to do this read of the block time - do you
think these two patches can land in the meantime, to help prep the TGL
path for actually working when Stan's work lands?

Thanks!

-James

> 
> > 
> > -James
> > 
> > > 
> > > Lucas De Marchi
> > > 
> > > >+u32 val = 0;
> > > >+int ret;
> > > >+
> > > >+ret = sandybridge_pcode_read(dev_priv,
> > > >+ 
> > > >GEN12_PCODE_READ_SAGV_BLOCK_TIME_US,
> > > >+ , NULL);
> > > >+if (!ret) {
> > > >+dev_priv->sagv_block_time_us = val;
> > > >+return;
> > > >+}
> > > >+
> > > >+DRM_DEBUG_DRIVER("Couldn't read SAGV block time!\n");
> > > >+} else if (IS_GEN(dev_priv, 11)) {
> > > > dev_priv->sagv_block_time_us = 10;
> > > > return;
> > > > } else if (IS_GEN(dev_priv, 10)) {
> > > >-- 
> > > >2.22.1
> > > >
> 
> -- 
> Ville Syrjälä
> Intel
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[Intel-gfx] [PATCH v3 2/2] drm/i915/tgl: Read SAGV block time from PCODE

[James Ausmus]

Starting from TGL, we now need to read the SAGV block time via a PCODE
mailbox, rather than having a static value.

BSpec: 49326

v2: Fix up pcode val data type (Ville), tighten variable scope (Ville)

Cc: Ville Syrjälä 
Cc: Stanislav Lisovskiy 
Cc: Lucas De Marchi 
Signed-off-by: James Ausmus 
Reviewed-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_reg.h |  1 +
 drivers/gpu/drm/i915/intel_pm.c | 15 ++-
 2 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6d67bd238cfe..030f0c37f64b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8870,6 +8870,7 @@ enum {
 #define GEN9_SAGV_DISABLE  0x0
 #define GEN9_SAGV_IS_DISABLED  0x1
 #define GEN9_SAGV_ENABLE   0x3
+#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US0x23
 #define GEN6_PCODE_DATA_MMIO(0x138128)
 #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT   8
 #define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0ffcafe97216..e2aca3e81d28 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3645,7 +3645,20 @@ intel_has_sagv(struct drm_i915_private *dev_priv)
 static void
 skl_setup_sagv_block_time(struct drm_i915_private *dev_priv)
 {
-   if (IS_GEN(dev_priv, 11)) {
+   if (INTEL_GEN(dev_priv) >= 12) {
+   u32 val = 0;
+   int ret;
+
+   ret = sandybridge_pcode_read(dev_priv,
+
GEN12_PCODE_READ_SAGV_BLOCK_TIME_US,
+, NULL);
+   if (!ret) {
+   dev_priv->sagv_block_time_us = val;
+   return;
+   }
+
+   DRM_DEBUG_DRIVER("Couldn't read SAGV block time!\n");
+   } else if (IS_GEN(dev_priv, 11)) {
dev_priv->sagv_block_time_us = 10;
return;
} else if (IS_GEN(dev_priv, 10)) {
-- 
2.22.1

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[Intel-gfx] [PATCH v3 1/2] drm/i915: Move SAGV block time to dev_priv

[James Ausmus]

In prep for newer platforms having more complicated ways to determine
the SAGV block time, move the variable to dev_priv, and extract the
setting to an initial setup function. While we're at it, update the if
ladder to follow the new gen -> old gen order preference, and warn on
any non-specified gen.

v2: Shorten the function name (Ville), return directly (Ville), move
sagv_block_time_us value to dev_priv (Ville)

v3: Change sagv_block_time_us to u32 (Lucas), Change fallback value to
-1 (Lucas), use intel_has_sagv for setup check rather than hand-rolling
(Lucas)

Cc: Ville Syrjälä 
Cc: Stanislav Lisovskiy 
Cc: Lucas De Marchi 
Signed-off-by: James Ausmus 
---
 drivers/gpu/drm/i915/i915_drv.h |  2 ++
 drivers/gpu/drm/i915/intel_pm.c | 33 -
 2 files changed, 26 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index cde4c7fb5570..1d9a9e827261 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1560,6 +1560,8 @@ struct drm_i915_private {
I915_SAGV_NOT_CONTROLLED
} sagv_status;
 
+   u32 sagv_block_time_us;
+
struct {
/*
 * Raw watermark latency values:
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index bfcf03ab5245..0ffcafe97216 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3642,6 +3642,26 @@ intel_has_sagv(struct drm_i915_private *dev_priv)
dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
 }
 
+static void
+skl_setup_sagv_block_time(struct drm_i915_private *dev_priv)
+{
+   if (IS_GEN(dev_priv, 11)) {
+   dev_priv->sagv_block_time_us = 10;
+   return;
+   } else if (IS_GEN(dev_priv, 10)) {
+   dev_priv->sagv_block_time_us = 20;
+   return;
+   } else if (IS_GEN(dev_priv, 9)) {
+   dev_priv->sagv_block_time_us = 30;
+   return;
+   } else {
+   MISSING_CASE(INTEL_GEN(dev_priv));
+   }
+
+   /* Default to an unusable block time */
+   dev_priv->sagv_block_time_us = -1;
+}
+
 /*
  * SAGV dynamically adjusts the system agent voltage and clock frequencies
  * depending on power and performance requirements. The display engine access
@@ -3730,18 +3750,10 @@ bool intel_can_enable_sagv(struct intel_atomic_state 
*state)
struct intel_crtc_state *crtc_state;
enum pipe pipe;
int level, latency;
-   int sagv_block_time_us;
 
if (!intel_has_sagv(dev_priv))
return false;
 
-   if (IS_GEN(dev_priv, 9))
-   sagv_block_time_us = 30;
-   else if (IS_GEN(dev_priv, 10))
-   sagv_block_time_us = 20;
-   else
-   sagv_block_time_us = 10;
-
/*
 * If there are no active CRTCs, no additional checks need be performed
 */
@@ -3788,7 +3800,7 @@ bool intel_can_enable_sagv(struct intel_atomic_state 
*state)
 * incur memory latencies higher than sagv_block_time_us we
 * can't enable SAGV.
 */
-   if (latency < sagv_block_time_us)
+   if (latency < dev_priv->sagv_block_time_us)
return false;
}
 
@@ -9013,6 +9025,9 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
else if (IS_GEN(dev_priv, 5))
i915_ironlake_get_mem_freq(dev_priv);
 
+   if (intel_has_sagv(dev_priv))
+   skl_setup_sagv_block_time(dev_priv);
+
/* For FIFO watermark updates */
if (INTEL_GEN(dev_priv) >= 9) {
skl_setup_wm_latency(dev_priv);
-- 
2.22.1

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Re: [Intel-gfx] [PATCH v2 1/2] drm/i915: Move SAGV block time to dev_priv

[James Ausmus]

On Fri, Oct 04, 2019 at 01:53:57PM -0700, Lucas De Marchi wrote:
> On Fri, Sep 27, 2019 at 03:24:26PM -0700, James Ausmus wrote:
> >In prep for newer platforms having more complicated ways to determine
> >the SAGV block time, move the variable to dev_priv, and extract the
> >setting to an initial setup function. While we're at it, update the if
> >ladder to follow the new gen -> old gen order preference, and warn on
> >any non-specified gen.
> >
> >v2: Shorten the function name (Ville), return directly (Ville), move
> >sagv_block_time_us value to dev_priv (Ville)
> >
> >Cc: Ville Syrjälä 
> >Cc: Stanislav Lisovskiy 
> >Cc: Lucas De Marchi 
> >Signed-off-by: James Ausmus 
> >---
> >
> >Ville - with the amount of v1..v2 change in this first patch, I wasn't
> >comfortable applying your R-b, could you take another look? Patch 2 just
> >has the trivial changes you suggested, so I kept that one.
> >
> > drivers/gpu/drm/i915/i915_drv.h |  2 ++
> > drivers/gpu/drm/i915/intel_pm.c | 33 -
> > 2 files changed, 26 insertions(+), 9 deletions(-)
> >
> >diff --git a/drivers/gpu/drm/i915/i915_drv.h 
> >b/drivers/gpu/drm/i915/i915_drv.h
> >index 337d8306416a..87a835a0210b 100644
> >--- a/drivers/gpu/drm/i915/i915_drv.h
> >+++ b/drivers/gpu/drm/i915/i915_drv.h
> >@@ -1579,6 +1579,8 @@ struct drm_i915_private {
> > I915_SAGV_NOT_CONTROLLED
> > } sagv_status;
> >
> >+int sagv_block_time_us;
> >+
> > struct {
> > /*
> >  * Raw watermark latency values:
> >diff --git a/drivers/gpu/drm/i915/intel_pm.c 
> >b/drivers/gpu/drm/i915/intel_pm.c
> >index bfcf03ab5245..b413a7f3bc5d 100644
> >--- a/drivers/gpu/drm/i915/intel_pm.c
> >+++ b/drivers/gpu/drm/i915/intel_pm.c
> >@@ -3642,6 +3642,26 @@ intel_has_sagv(struct drm_i915_private *dev_priv)
> > dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
> > }
> >
> >+static void
> >+skl_setup_sagv_block_time(struct drm_i915_private *dev_priv)
> >+{
> >+if (IS_GEN(dev_priv, 11)) {
> >+dev_priv->sagv_block_time_us = 10;
> >+return;
> >+} else if (IS_GEN(dev_priv, 10)) {
> >+dev_priv->sagv_block_time_us = 20;
> >+return;
> >+} else if (IS_GEN(dev_priv, 9)) {
> >+dev_priv->sagv_block_time_us = 30;
> >+return;
> >+} else {
> >+MISSING_CASE(INTEL_GEN(dev_priv));
> >+}
> >+
> >+/* Default to an unusable block time */
> >+dev_priv->sagv_block_time_us = 1000;
> 
> I would actually make sagv_block_time_us unsigned and assign -1 here.
> But making it unsigned would mean cascade that down to the wm
> calculations. Humn... Maybe there's a reason for that to be signed that
> I'm not seeing.

Hmm - yeah, I don't see a reason why it needs to be signed either.
Hadn't looked in to it previously, was just following the existing code.
:)

I'll switch that up and send a v3.

> 
> 
> >+}
> >+
> > /*
> >  * SAGV dynamically adjusts the system agent voltage and clock frequencies
> >  * depending on power and performance requirements. The display engine 
> > access
> >@@ -3730,18 +3750,10 @@ bool intel_can_enable_sagv(struct intel_atomic_state 
> >*state)
> > struct intel_crtc_state *crtc_state;
> > enum pipe pipe;
> > int level, latency;
> >-int sagv_block_time_us;
> >
> > if (!intel_has_sagv(dev_priv))
> > return false;
> >
> >-if (IS_GEN(dev_priv, 9))
> >-sagv_block_time_us = 30;
> >-else if (IS_GEN(dev_priv, 10))
> >-sagv_block_time_us = 20;
> >-else
> >-sagv_block_time_us = 10;
> >-
> > /*
> >  * If there are no active CRTCs, no additional checks need be performed
> >  */
> >@@ -3788,7 +3800,7 @@ bool intel_can_enable_sagv(struct intel_atomic_state 
> >*state)
> >  * incur memory latencies higher than sagv_block_time_us we
> >  * can't enable SAGV.
> >  */
> >-if (latency < sagv_block_time_us)
> >+if (latency < dev_priv->sagv_block_time_us)
> > return false;
> > }
> >
> >@@ -9013,6 +9025,9 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
> > else if (IS_GEN(dev_priv, 5))
> > i915_ironlake_get_mem_freq(dev_priv);
> >
> >+if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10)
> >+skl_setup_sagv_block_time(dev_priv);
> 
> Do we want to use intel_has_sagv() here?

Yeah, that would make sense, will fix up.


Thanks!

-James

> 
> >+
> > /* For FIFO watermark updates */
> > if (INTEL_GEN(dev_priv) >= 9) {
> > skl_setup_wm_latency(dev_priv);
> >-- 
> >2.22.1
> >
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Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/tgl: Read SAGV block time from PCODE

[James Ausmus]

On Fri, Oct 04, 2019 at 01:55:46PM -0700, Lucas De Marchi wrote:
> On Fri, Sep 27, 2019 at 03:24:27PM -0700, James Ausmus wrote:
> >Starting from TGL, we now need to read the SAGV block time via a PCODE
> >mailbox, rather than having a static value.
> >
> >BSpec: 49326
> >
> >v2: Fix up pcode val data type (Ville), tighten variable scope (Ville)
> >
> >Cc: Ville Syrjälä 
> >Cc: Stanislav Lisovskiy 
> >Cc: Lucas De Marchi 
> >Signed-off-by: James Ausmus 
> >Reviewed-by: Ville Syrjälä 
> >---
> > drivers/gpu/drm/i915/i915_reg.h |  1 +
> > drivers/gpu/drm/i915/intel_pm.c | 15 ++-
> > 2 files changed, 15 insertions(+), 1 deletion(-)
> >
> >diff --git a/drivers/gpu/drm/i915/i915_reg.h 
> >b/drivers/gpu/drm/i915/i915_reg.h
> >index 058aa5ca8b73..6a45df9dad9c 100644
> >--- a/drivers/gpu/drm/i915/i915_reg.h
> >+++ b/drivers/gpu/drm/i915/i915_reg.h
> >@@ -8869,6 +8869,7 @@ enum {
> > #define GEN9_SAGV_DISABLE   0x0
> > #define GEN9_SAGV_IS_DISABLED   0x1
> > #define GEN9_SAGV_ENABLE0x3
> >+#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
> > #define GEN6_PCODE_DATA _MMIO(0x138128)
> > #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT8
> > #define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT  16
> >diff --git a/drivers/gpu/drm/i915/intel_pm.c 
> >b/drivers/gpu/drm/i915/intel_pm.c
> >index b413a7f3bc5d..13721ba44013 100644
> >--- a/drivers/gpu/drm/i915/intel_pm.c
> >+++ b/drivers/gpu/drm/i915/intel_pm.c
> >@@ -3645,7 +3645,20 @@ intel_has_sagv(struct drm_i915_private *dev_priv)
> > static void
> > skl_setup_sagv_block_time(struct drm_i915_private *dev_priv)
> > {
> >-if (IS_GEN(dev_priv, 11)) {
> >+if (INTEL_GEN(dev_priv) >= 12) {
> 
> sagv will still never be enabled for TGL. Are you going to revert 
> 8ffa4392a32e ("drm/i915/tgl: disable SAGV temporarily")
> in a separete patch?

Yes, that's the idea - we land these two patches, then once HSD
1409542895 gets resolved, we revert 8ffa4392a32e and everything Just
Works. ;)

-James

> 
> Lucas De Marchi
> 
> >+u32 val = 0;
> >+int ret;
> >+
> >+ret = sandybridge_pcode_read(dev_priv,
> >+ 
> >GEN12_PCODE_READ_SAGV_BLOCK_TIME_US,
> >+ , NULL);
> >+if (!ret) {
> >+dev_priv->sagv_block_time_us = val;
> >+return;
> >+}
> >+
> >+DRM_DEBUG_DRIVER("Couldn't read SAGV block time!\n");
> >+} else if (IS_GEN(dev_priv, 11)) {
> > dev_priv->sagv_block_time_us = 10;
> > return;
> > } else if (IS_GEN(dev_priv, 10)) {
> >-- 
> >2.22.1
> >
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Re: [Intel-gfx] [PATCH v2 1/2] drm/i915: Move SAGV block time to dev_priv

[James Ausmus]

On Fri, Sep 27, 2019 at 03:24:26PM -0700, James Ausmus wrote:
> In prep for newer platforms having more complicated ways to determine
> the SAGV block time, move the variable to dev_priv, and extract the
> setting to an initial setup function. While we're at it, update the if
> ladder to follow the new gen -> old gen order preference, and warn on
> any non-specified gen.
> 
> v2: Shorten the function name (Ville), return directly (Ville), move
> sagv_block_time_us value to dev_priv (Ville)
> 
> Cc: Ville Syrjälä 
> Cc: Stanislav Lisovskiy 
> Cc: Lucas De Marchi 
> Signed-off-by: James Ausmus 
> ---
> 
> Ville - with the amount of v1..v2 change in this first patch, I wasn't
> comfortable applying your R-b, could you take another look? Patch 2 just
> has the trivial changes you suggested, so I kept that one.

Review ping. :)

Thanks!

-James

> 
>  drivers/gpu/drm/i915/i915_drv.h |  2 ++
>  drivers/gpu/drm/i915/intel_pm.c | 33 -
>  2 files changed, 26 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 337d8306416a..87a835a0210b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1579,6 +1579,8 @@ struct drm_i915_private {
>   I915_SAGV_NOT_CONTROLLED
>   } sagv_status;
>  
> + int sagv_block_time_us;
> +
>   struct {
>   /*
>* Raw watermark latency values:
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index bfcf03ab5245..b413a7f3bc5d 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3642,6 +3642,26 @@ intel_has_sagv(struct drm_i915_private *dev_priv)
>   dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
>  }
>  
> +static void
> +skl_setup_sagv_block_time(struct drm_i915_private *dev_priv)
> +{
> + if (IS_GEN(dev_priv, 11)) {
> + dev_priv->sagv_block_time_us = 10;
> + return;
> + } else if (IS_GEN(dev_priv, 10)) {
> + dev_priv->sagv_block_time_us = 20;
> + return;
> + } else if (IS_GEN(dev_priv, 9)) {
> + dev_priv->sagv_block_time_us = 30;
> + return;
> + } else {
> + MISSING_CASE(INTEL_GEN(dev_priv));
> + }
> +
> + /* Default to an unusable block time */
> + dev_priv->sagv_block_time_us = 1000;
> +}
> +
>  /*
>   * SAGV dynamically adjusts the system agent voltage and clock frequencies
>   * depending on power and performance requirements. The display engine access
> @@ -3730,18 +3750,10 @@ bool intel_can_enable_sagv(struct intel_atomic_state 
> *state)
>   struct intel_crtc_state *crtc_state;
>   enum pipe pipe;
>   int level, latency;
> - int sagv_block_time_us;
>  
>   if (!intel_has_sagv(dev_priv))
>   return false;
>  
> - if (IS_GEN(dev_priv, 9))
> - sagv_block_time_us = 30;
> - else if (IS_GEN(dev_priv, 10))
> - sagv_block_time_us = 20;
> - else
> - sagv_block_time_us = 10;
> -
>   /*
>* If there are no active CRTCs, no additional checks need be performed
>*/
> @@ -3788,7 +3800,7 @@ bool intel_can_enable_sagv(struct intel_atomic_state 
> *state)
>* incur memory latencies higher than sagv_block_time_us we
>* can't enable SAGV.
>*/
> - if (latency < sagv_block_time_us)
> + if (latency < dev_priv->sagv_block_time_us)
>   return false;
>   }
>  
> @@ -9013,6 +9025,9 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
>   else if (IS_GEN(dev_priv, 5))
>   i915_ironlake_get_mem_freq(dev_priv);
>  
> + if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10)
> + skl_setup_sagv_block_time(dev_priv);
> +
>   /* For FIFO watermark updates */
>   if (INTEL_GEN(dev_priv) >= 9) {
>   skl_setup_wm_latency(dev_priv);
> -- 
> 2.22.1
> 
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[Intel-gfx] [PATCH v2 2/2] drm/i915/tgl: Read SAGV block time from PCODE

[James Ausmus]

Starting from TGL, we now need to read the SAGV block time via a PCODE
mailbox, rather than having a static value.

BSpec: 49326

v2: Fix up pcode val data type (Ville), tighten variable scope (Ville)

Cc: Ville Syrjälä 
Cc: Stanislav Lisovskiy 
Cc: Lucas De Marchi 
Signed-off-by: James Ausmus 
Reviewed-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_reg.h |  1 +
 drivers/gpu/drm/i915/intel_pm.c | 15 ++-
 2 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 058aa5ca8b73..6a45df9dad9c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8869,6 +8869,7 @@ enum {
 #define GEN9_SAGV_DISABLE  0x0
 #define GEN9_SAGV_IS_DISABLED  0x1
 #define GEN9_SAGV_ENABLE   0x3
+#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US0x23
 #define GEN6_PCODE_DATA_MMIO(0x138128)
 #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT   8
 #define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b413a7f3bc5d..13721ba44013 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3645,7 +3645,20 @@ intel_has_sagv(struct drm_i915_private *dev_priv)
 static void
 skl_setup_sagv_block_time(struct drm_i915_private *dev_priv)
 {
-   if (IS_GEN(dev_priv, 11)) {
+   if (INTEL_GEN(dev_priv) >= 12) {
+   u32 val = 0;
+   int ret;
+
+   ret = sandybridge_pcode_read(dev_priv,
+
GEN12_PCODE_READ_SAGV_BLOCK_TIME_US,
+, NULL);
+   if (!ret) {
+   dev_priv->sagv_block_time_us = val;
+   return;
+   }
+
+   DRM_DEBUG_DRIVER("Couldn't read SAGV block time!\n");
+   } else if (IS_GEN(dev_priv, 11)) {
dev_priv->sagv_block_time_us = 10;
return;
} else if (IS_GEN(dev_priv, 10)) {
-- 
2.22.1

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[Intel-gfx] [CI v2 1/2] drm/i915: Move SAGV block time to dev_priv

[James Ausmus]

In prep for newer platforms having more complicated ways to determine
the SAGV block time, move the variable to dev_priv, and extract the
setting to an initial setup function. While we're at it, update the if
ladder to follow the new gen -> old gen order preference, and warn on
any non-specified gen.

v2: Shorten the function name (Ville), return directly (Ville), move
sagv_block_time_us value to dev_priv (Ville)

Cc: Ville Syrjälä 
Cc: Stanislav Lisovskiy 
Cc: Lucas De Marchi 
Signed-off-by: James Ausmus 
---

Resending for CI, as I evidently confused Patchwork...

 drivers/gpu/drm/i915/i915_drv.h |  2 ++
 drivers/gpu/drm/i915/intel_pm.c | 33 -
 2 files changed, 26 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 337d8306416a..87a835a0210b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1579,6 +1579,8 @@ struct drm_i915_private {
I915_SAGV_NOT_CONTROLLED
} sagv_status;
 
+   int sagv_block_time_us;
+
struct {
/*
 * Raw watermark latency values:
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index bfcf03ab5245..b413a7f3bc5d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3642,6 +3642,26 @@ intel_has_sagv(struct drm_i915_private *dev_priv)
dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
 }
 
+static void
+skl_setup_sagv_block_time(struct drm_i915_private *dev_priv)
+{
+   if (IS_GEN(dev_priv, 11)) {
+   dev_priv->sagv_block_time_us = 10;
+   return;
+   } else if (IS_GEN(dev_priv, 10)) {
+   dev_priv->sagv_block_time_us = 20;
+   return;
+   } else if (IS_GEN(dev_priv, 9)) {
+   dev_priv->sagv_block_time_us = 30;
+   return;
+   } else {
+   MISSING_CASE(INTEL_GEN(dev_priv));
+   }
+
+   /* Default to an unusable block time */
+   dev_priv->sagv_block_time_us = 1000;
+}
+
 /*
  * SAGV dynamically adjusts the system agent voltage and clock frequencies
  * depending on power and performance requirements. The display engine access
@@ -3730,18 +3750,10 @@ bool intel_can_enable_sagv(struct intel_atomic_state 
*state)
struct intel_crtc_state *crtc_state;
enum pipe pipe;
int level, latency;
-   int sagv_block_time_us;
 
if (!intel_has_sagv(dev_priv))
return false;
 
-   if (IS_GEN(dev_priv, 9))
-   sagv_block_time_us = 30;
-   else if (IS_GEN(dev_priv, 10))
-   sagv_block_time_us = 20;
-   else
-   sagv_block_time_us = 10;
-
/*
 * If there are no active CRTCs, no additional checks need be performed
 */
@@ -3788,7 +3800,7 @@ bool intel_can_enable_sagv(struct intel_atomic_state 
*state)
 * incur memory latencies higher than sagv_block_time_us we
 * can't enable SAGV.
 */
-   if (latency < sagv_block_time_us)
+   if (latency < dev_priv->sagv_block_time_us)
return false;
}
 
@@ -9013,6 +9025,9 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
else if (IS_GEN(dev_priv, 5))
i915_ironlake_get_mem_freq(dev_priv);
 
+   if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10)
+   skl_setup_sagv_block_time(dev_priv);
+
/* For FIFO watermark updates */
if (INTEL_GEN(dev_priv) >= 9) {
skl_setup_wm_latency(dev_priv);
-- 
2.22.1

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[Intel-gfx] [PATCH v2 1/2] drm/i915: Move SAGV block time to dev_priv

[James Ausmus]

In prep for newer platforms having more complicated ways to determine
the SAGV block time, move the variable to dev_priv, and extract the
setting to an initial setup function. While we're at it, update the if
ladder to follow the new gen -> old gen order preference, and warn on
any non-specified gen.

v2: Shorten the function name (Ville), return directly (Ville), move
sagv_block_time_us value to dev_priv (Ville)

Cc: Ville Syrjälä 
Cc: Stanislav Lisovskiy 
Cc: Lucas De Marchi 
Signed-off-by: James Ausmus 
---

Ville - with the amount of v1..v2 change in this first patch, I wasn't
comfortable applying your R-b, could you take another look? Patch 2 just
has the trivial changes you suggested, so I kept that one.

 drivers/gpu/drm/i915/i915_drv.h |  2 ++
 drivers/gpu/drm/i915/intel_pm.c | 33 -
 2 files changed, 26 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 337d8306416a..87a835a0210b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1579,6 +1579,8 @@ struct drm_i915_private {
I915_SAGV_NOT_CONTROLLED
} sagv_status;
 
+   int sagv_block_time_us;
+
struct {
/*
 * Raw watermark latency values:
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index bfcf03ab5245..b413a7f3bc5d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3642,6 +3642,26 @@ intel_has_sagv(struct drm_i915_private *dev_priv)
dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
 }
 
+static void
+skl_setup_sagv_block_time(struct drm_i915_private *dev_priv)
+{
+   if (IS_GEN(dev_priv, 11)) {
+   dev_priv->sagv_block_time_us = 10;
+   return;
+   } else if (IS_GEN(dev_priv, 10)) {
+   dev_priv->sagv_block_time_us = 20;
+   return;
+   } else if (IS_GEN(dev_priv, 9)) {
+   dev_priv->sagv_block_time_us = 30;
+   return;
+   } else {
+   MISSING_CASE(INTEL_GEN(dev_priv));
+   }
+
+   /* Default to an unusable block time */
+   dev_priv->sagv_block_time_us = 1000;
+}
+
 /*
  * SAGV dynamically adjusts the system agent voltage and clock frequencies
  * depending on power and performance requirements. The display engine access
@@ -3730,18 +3750,10 @@ bool intel_can_enable_sagv(struct intel_atomic_state 
*state)
struct intel_crtc_state *crtc_state;
enum pipe pipe;
int level, latency;
-   int sagv_block_time_us;
 
if (!intel_has_sagv(dev_priv))
return false;
 
-   if (IS_GEN(dev_priv, 9))
-   sagv_block_time_us = 30;
-   else if (IS_GEN(dev_priv, 10))
-   sagv_block_time_us = 20;
-   else
-   sagv_block_time_us = 10;
-
/*
 * If there are no active CRTCs, no additional checks need be performed
 */
@@ -3788,7 +3800,7 @@ bool intel_can_enable_sagv(struct intel_atomic_state 
*state)
 * incur memory latencies higher than sagv_block_time_us we
 * can't enable SAGV.
 */
-   if (latency < sagv_block_time_us)
+   if (latency < dev_priv->sagv_block_time_us)
return false;
}
 
@@ -9013,6 +9025,9 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
else if (IS_GEN(dev_priv, 5))
i915_ironlake_get_mem_freq(dev_priv);
 
+   if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10)
+   skl_setup_sagv_block_time(dev_priv);
+
/* For FIFO watermark updates */
if (INTEL_GEN(dev_priv) >= 9) {
skl_setup_wm_latency(dev_priv);
-- 
2.22.1

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[Intel-gfx] [PATCH v2 2/2] drm/i915/tgl: Read SAGV block time from PCODE

[James Ausmus]

Starting from TGL, we now need to read the SAGV block time via a PCODE
mailbox, rather than having a static value.

BSpec: 49326

v2: Fix up pcode val data type (Ville), tighten variable scope (Ville)

Cc: Ville Syrjälä 
Cc: Stanislav Lisovskiy 
Cc: Lucas De Marchi 
Signed-off-by: James Ausmus 
Reviewed-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/i915_reg.h |  1 +
 drivers/gpu/drm/i915/intel_pm.c | 15 ++-
 2 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 058aa5ca8b73..6a45df9dad9c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8869,6 +8869,7 @@ enum {
 #define GEN9_SAGV_DISABLE  0x0
 #define GEN9_SAGV_IS_DISABLED  0x1
 #define GEN9_SAGV_ENABLE   0x3
+#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US0x23
 #define GEN6_PCODE_DATA_MMIO(0x138128)
 #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT   8
 #define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b413a7f3bc5d..13721ba44013 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3645,7 +3645,20 @@ intel_has_sagv(struct drm_i915_private *dev_priv)
 static void
 skl_setup_sagv_block_time(struct drm_i915_private *dev_priv)
 {
-   if (IS_GEN(dev_priv, 11)) {
+   if (INTEL_GEN(dev_priv) >= 12) {
+   u32 val = 0;
+   int ret;
+
+   ret = sandybridge_pcode_read(dev_priv,
+
GEN12_PCODE_READ_SAGV_BLOCK_TIME_US,
+, NULL);
+   if (!ret) {
+   dev_priv->sagv_block_time_us = val;
+   return;
+   }
+
+   DRM_DEBUG_DRIVER("Couldn't read SAGV block time!\n");
+   } else if (IS_GEN(dev_priv, 11)) {
dev_priv->sagv_block_time_us = 10;
return;
} else if (IS_GEN(dev_priv, 10)) {
-- 
2.22.1

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Re: [Intel-gfx] [PATCH 3/3] drm/i915/tgl: Remove single pipe restriction from SAGV

[James Ausmus]

On Thu, Sep 26, 2019 at 03:34:35PM +0300, Ville Syrjälä wrote:
> On Wed, Sep 25, 2019 at 01:33:52PM -0700, James Ausmus wrote:
> > For Gen12, BSpec no longer tells us to disable SAGV when > 1 pipe is
> > active. Update intel_can_enable_sagv to allow this, and loop through all
> > active planes on all active crtcs to check against the interlaced and
> > latency restrictions.
> > 
> > BSpec: 49325
> > 
> > Cc: Ville Syrjälä 
> > Cc: Stanislav Lisovskiy 
> > Cc: Lucas De Marchi 
> > Signed-off-by: James Ausmus 
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 63 +
> >  1 file changed, 32 insertions(+), 31 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c 
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index ca2bec09edb5..cb50c697a6b8 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3775,7 +3775,6 @@ bool intel_can_enable_sagv(struct intel_atomic_state 
> > *state)
> > struct intel_crtc *crtc;
> > struct intel_plane *plane;
> > struct intel_crtc_state *crtc_state;
> > -   enum pipe pipe;
> > int level, latency;
> > int sagv_block_time_us;
> >  
> > @@ -3791,47 +3790,49 @@ bool intel_can_enable_sagv(struct 
> > intel_atomic_state *state)
> > return true;
> >  
> > /*
> > -* SKL+ workaround: bspec recommends we disable SAGV when we have
> > +* SKL-ICL workaround: bspec recommends we disable SAGV when we have
> >  * more then one pipe enabled
> >  */
> > -   if (hweight8(state->active_pipes) > 1)
> > +   if (INTEL_GEN(dev_priv) < 12 && hweight8(state->active_pipes) > 1)
> > return false;
> >  
> > -   /* Since we're now guaranteed to only have one active CRTC... */
> > -   pipe = ffs(state->active_pipes) - 1;
> > -   crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> > -   crtc_state = to_intel_crtc_state(crtc->base.state);
> > +   for_each_intel_crtc(_priv->drm, crtc) {
> > +   crtc_state = to_intel_crtc_state(crtc->base.state);
> > +   if (!crtc_state->base.active)
> > +   continue;
> >  
> > -   if (crtc->base.state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> > -   return false;
> > +   if (crtc->base.state->adjusted_mode.flags &
> > +   DRM_MODE_FLAG_INTERLACE)
> > +   return false;
> >  
> > -   for_each_intel_plane_on_crtc(dev, crtc, plane) {
> > -   struct skl_plane_wm *wm =
> > -   _state->wm.skl.optimal.planes[plane->id];
> > +   for_each_intel_plane_on_crtc(dev, crtc, plane) {
> > +   struct skl_plane_wm *wm =
> > +   _state->wm.skl.optimal.planes[plane->id];
> 
> This whole loop is bothering me. I'd much rather we move to a scheme
> where each plane computes it's SAGV friendlyness when computing the
> watermarks. We'll anyway need that since we need to caclulate the
> watermarks differently for the SAGV on vs. off cases.

Hmm, I'll have to look in to this. In the meantime, I'd like to get
patches 1 & 2 of this series moving forward, as those should be what's
really necessary to be able to turn on SAGV for TGL once we're ready, so
I'll send those as a separate series, and leave relaxing the 1 pipe
restriction as it's own work.

-James

> 
> >  
> > -   /* Skip this plane if it's not enabled */
> > -   if (!wm->wm[0].plane_en)
> > -   continue;
> > +   /* Skip this plane if it's not enabled */
> > +   if (!wm->wm[0].plane_en)
> > +   continue;
> >  
> > -   /* Find the highest enabled wm level for this plane */
> > -   for (level = ilk_wm_max_level(dev_priv);
> > -!wm->wm[level].plane_en; --level)
> > -{ }
> > +   /* Find the highest enabled wm level for this plane */
> > +   for (level = ilk_wm_max_level(dev_priv);
> > +!wm->wm[level].plane_en; --level)
> > +{ }
> >  
> > -   latency = dev_priv->wm.skl_latency[level];
> > +   latency = dev_priv->wm.skl_latency[level];
> >  
> > -   if (skl_needs_memory_bw_wa(dev_priv) &&
> > -   plane->base.state->fb->modifi

Re: [Intel-gfx] [PATCH v2] drm/i915/tgl: Add memory type decoding for bandwidth checking

[James Ausmus]

On Wed, Sep 25, 2019 at 03:35:28PM -0700, Summers, Stuart wrote:
> On Wed, 2019-09-25 at 08:35 -0700, James Ausmus wrote:
> > On Wed, Sep 25, 2019 at 07:33:38AM -0700, Summers, Stuart wrote:
> > > On Tue, 2019-09-24 at 15:28 -0700, James Ausmus wrote:
> > > > The memory type values have changed in TGL, so we need to
> > > > translate
> > > > them
> > > > differently than ICL. While we're moving it, fix up the ICL
> > > > translation
> > > > for LPDDR4.
> > > > 
> > > > BSpec: 53998
> > > > 
> > > > v2: Fix up ICL LPDDR4 entry (Ville); Drop unused values from TGL
> > > > (Ville)
> > > > 
> > > > Cc: Ville Syrjälä 
> > > > Cc: Stanislav Lisovskiy 
> > > > Signed-off-by: James Ausmus 
> > > > Reviewed-by: Ville Syrjälä 
> > > > ---
> > > >  drivers/gpu/drm/i915/display/intel_bw.c | 55 ++-
> > > > 
> > > > --
> > > >  1 file changed, 39 insertions(+), 16 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> > > > b/drivers/gpu/drm/i915/display/intel_bw.c
> > > > index cd58e47ab7b2..22e83f857de8 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_bw.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> > > > @@ -35,22 +35,45 @@ static int
> > > > icl_pcode_read_mem_global_info(struct
> > > > drm_i915_private *dev_priv,
> > > > if (ret)
> > > > return ret;
> > > >  
> > > > -   switch (val & 0xf) {
> > > > -   case 0:
> > > > -   qi->dram_type = INTEL_DRAM_DDR4;
> > > > -   break;
> > > > -   case 1:
> > > > -   qi->dram_type = INTEL_DRAM_DDR3;
> > > > -   break;
> > > > -   case 2:
> > > > -   qi->dram_type = INTEL_DRAM_LPDDR3;
> > > > -   break;
> > > > -   case 3:
> > > > -   qi->dram_type = INTEL_DRAM_LPDDR3;
> > > > -   break;
> > > > -   default:
> > > > -   MISSING_CASE(val & 0xf);
> > > > -   break;
> > > > +   if (IS_GEN(dev_priv, 12)) {
> > > > +   switch (val & 0xf) {
> > > > +   case 0:
> > > > +   qi->dram_type = INTEL_DRAM_DDR4;
> > > > +   break;
> > > > +   case 3:
> > > > +   qi->dram_type = INTEL_DRAM_LPDDR4;
> > > > +   break;
> > > > +   case 4:
> > > > +   qi->dram_type = INTEL_DRAM_DDR3;
> > > > +   break;
> > > > +   case 5:
> > > > +   qi->dram_type = INTEL_DRAM_LPDDR3;
> > > > +   break;
> > > > +   default:
> > > > +   MISSING_CASE(val & 0xf);
> > > > +   break;
> > > > +   }
> > > > +   } else if (IS_GEN(dev_priv, 11)) {
> > > > +   switch (val & 0xf) {
> > > > +   case 0:
> > > > +   qi->dram_type = INTEL_DRAM_DDR4;
> > > > +   break;
> > > > +   case 1:
> > > > +   qi->dram_type = INTEL_DRAM_DDR3;
> > > > +   break;
> > > > +   case 2:
> > > > +   qi->dram_type = INTEL_DRAM_LPDDR3;
> > > > +   break;
> > > > +   case 3:
> > > > +   qi->dram_type = INTEL_DRAM_LPDDR4;
> > > > +   break;
> > > > +   default:
> > > > +   MISSING_CASE(val & 0xf);
> > > > +   break;
> > > 
> > > James, is there a reason we can't just combine these two conditions
> > > into one switch statement? At initial glance it looks like the
> > > cases
> > > are the same for the common ones and the only real difference is
> > > the
> > > supported bits.
> > 
> > The info I got from the HW guys indicat

[Intel-gfx] [PATCH 3/3] drm/i915/tgl: Remove single pipe restriction from SAGV

[James Ausmus]

For Gen12, BSpec no longer tells us to disable SAGV when > 1 pipe is
active. Update intel_can_enable_sagv to allow this, and loop through all
active planes on all active crtcs to check against the interlaced and
latency restrictions.

BSpec: 49325

Cc: Ville Syrjälä 
Cc: Stanislav Lisovskiy 
Cc: Lucas De Marchi 
Signed-off-by: James Ausmus 
---
 drivers/gpu/drm/i915/intel_pm.c | 63 +
 1 file changed, 32 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ca2bec09edb5..cb50c697a6b8 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3775,7 +3775,6 @@ bool intel_can_enable_sagv(struct intel_atomic_state 
*state)
struct intel_crtc *crtc;
struct intel_plane *plane;
struct intel_crtc_state *crtc_state;
-   enum pipe pipe;
int level, latency;
int sagv_block_time_us;
 
@@ -3791,47 +3790,49 @@ bool intel_can_enable_sagv(struct intel_atomic_state 
*state)
return true;
 
/*
-* SKL+ workaround: bspec recommends we disable SAGV when we have
+* SKL-ICL workaround: bspec recommends we disable SAGV when we have
 * more then one pipe enabled
 */
-   if (hweight8(state->active_pipes) > 1)
+   if (INTEL_GEN(dev_priv) < 12 && hweight8(state->active_pipes) > 1)
return false;
 
-   /* Since we're now guaranteed to only have one active CRTC... */
-   pipe = ffs(state->active_pipes) - 1;
-   crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
-   crtc_state = to_intel_crtc_state(crtc->base.state);
+   for_each_intel_crtc(_priv->drm, crtc) {
+   crtc_state = to_intel_crtc_state(crtc->base.state);
+   if (!crtc_state->base.active)
+   continue;
 
-   if (crtc->base.state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
-   return false;
+   if (crtc->base.state->adjusted_mode.flags &
+   DRM_MODE_FLAG_INTERLACE)
+   return false;
 
-   for_each_intel_plane_on_crtc(dev, crtc, plane) {
-   struct skl_plane_wm *wm =
-   _state->wm.skl.optimal.planes[plane->id];
+   for_each_intel_plane_on_crtc(dev, crtc, plane) {
+   struct skl_plane_wm *wm =
+   _state->wm.skl.optimal.planes[plane->id];
 
-   /* Skip this plane if it's not enabled */
-   if (!wm->wm[0].plane_en)
-   continue;
+   /* Skip this plane if it's not enabled */
+   if (!wm->wm[0].plane_en)
+   continue;
 
-   /* Find the highest enabled wm level for this plane */
-   for (level = ilk_wm_max_level(dev_priv);
-!wm->wm[level].plane_en; --level)
-{ }
+   /* Find the highest enabled wm level for this plane */
+   for (level = ilk_wm_max_level(dev_priv);
+!wm->wm[level].plane_en; --level)
+{ }
 
-   latency = dev_priv->wm.skl_latency[level];
+   latency = dev_priv->wm.skl_latency[level];
 
-   if (skl_needs_memory_bw_wa(dev_priv) &&
-   plane->base.state->fb->modifier ==
-   I915_FORMAT_MOD_X_TILED)
-   latency += 15;
+   if (skl_needs_memory_bw_wa(dev_priv) &&
+   plane->base.state->fb->modifier ==
+   I915_FORMAT_MOD_X_TILED)
+   latency += 15;
 
-   /*
-* If any of the planes on this pipe don't enable wm levels that
-* incur memory latencies higher than sagv_block_time_us we
-* can't enable SAGV.
-*/
-   if (latency < sagv_block_time_us)
-   return false;
+   /*
+* If any of the planes on this pipe don't enable wm
+* levels that incur memory latencies higher than
+* sagv_block_time_us we can't enable SAGV.
+*/
+   if (latency < sagv_block_time_us)
+   return false;
+   }
}
 
return true;
-- 
2.22.1

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[Intel-gfx] [PATCH 2/3] drm/i915/tgl: Read SAGV block time from PCODE

[James Ausmus]

Starting from TGL, we now need to read the SAGV block time via a PCODE
mailbox, rather than having a static value.

BSpec: 49326

Cc: Ville Syrjälä 
Cc: Stanislav Lisovskiy 
Cc: Lucas De Marchi 
Signed-off-by: James Ausmus 
---
 drivers/gpu/drm/i915/i915_reg.h |  1 +
 drivers/gpu/drm/i915/intel_pm.c | 20 +++-
 2 files changed, 16 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e752de9470bd..84ae6553485b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8865,6 +8865,7 @@ enum {
 #define GEN9_SAGV_DISABLE  0x0
 #define GEN9_SAGV_IS_DISABLED  0x1
 #define GEN9_SAGV_ENABLE   0x3
+#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US0x23
 #define GEN6_PCODE_DATA_MMIO(0x138128)
 #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT   8
 #define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5ad72dcb0faa..ca2bec09edb5 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3665,16 +3665,26 @@ intel_has_sagv(struct drm_i915_private *dev_priv)
 static int
 intel_get_sagv_block_time_us(struct drm_i915_private *dev_priv)
 {
-   int sagv_block_time_us = 1000; /* Default to unusable block time */
+   uint val = 0;
+   int ret, sagv_block_time_us = 1000; /* Default to unusable block time */
 
-   if (IS_GEN(dev_priv, 11))
+   if (INTEL_GEN(dev_priv) >= 12) {
+   ret = sandybridge_pcode_read(dev_priv,
+
GEN12_PCODE_READ_SAGV_BLOCK_TIME_US,
+, NULL);
+   if (!ret)
+   sagv_block_time_us = val;
+   else
+   DRM_DEBUG_DRIVER("Couldn't read SAGV block time!\n");
+   } else if (IS_GEN(dev_priv, 11)) {
sagv_block_time_us = 10;
-   else if (IS_GEN(dev_priv, 10))
+   } else if (IS_GEN(dev_priv, 10)) {
sagv_block_time_us = 20;
-   else if (IS_GEN(dev_priv, 9))
+   } else if (IS_GEN(dev_priv, 9)) {
sagv_block_time_us = 30;
-   else
+   } else {
MISSING_CASE(INTEL_GEN(dev_priv));
+   }
 
return sagv_block_time_us;
 }
-- 
2.22.1

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[Intel-gfx] [PATCH 1/3] drm/i915: Extract SAGV block time function

[James Ausmus]

In prep for newer platforms having more complicated ways to determine
the SAGV block time, extract the setting to a separate function. While
we're at it, update the if ladder to follow the new gen -> old gen order
preference, and warn on any non-specified gen.

Cc: Ville Syrjälä 
Cc: Stanislav Lisovskiy 
Cc: Lucas De Marchi 
Signed-off-by: James Ausmus 
---
 drivers/gpu/drm/i915/intel_pm.c | 24 ++--
 1 file changed, 18 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6bed2ed14574..5ad72dcb0faa 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3662,6 +3662,23 @@ intel_has_sagv(struct drm_i915_private *dev_priv)
dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
 }
 
+static int
+intel_get_sagv_block_time_us(struct drm_i915_private *dev_priv)
+{
+   int sagv_block_time_us = 1000; /* Default to unusable block time */
+
+   if (IS_GEN(dev_priv, 11))
+   sagv_block_time_us = 10;
+   else if (IS_GEN(dev_priv, 10))
+   sagv_block_time_us = 20;
+   else if (IS_GEN(dev_priv, 9))
+   sagv_block_time_us = 30;
+   else
+   MISSING_CASE(INTEL_GEN(dev_priv));
+
+   return sagv_block_time_us;
+}
+
 /*
  * SAGV dynamically adjusts the system agent voltage and clock frequencies
  * depending on power and performance requirements. The display engine access
@@ -3755,12 +3772,7 @@ bool intel_can_enable_sagv(struct intel_atomic_state 
*state)
if (!intel_has_sagv(dev_priv))
return false;
 
-   if (IS_GEN(dev_priv, 9))
-   sagv_block_time_us = 30;
-   else if (IS_GEN(dev_priv, 10))
-   sagv_block_time_us = 20;
-   else
-   sagv_block_time_us = 10;
+   sagv_block_time_us = intel_get_sagv_block_time_us(dev_priv);
 
/*
 * If there are no active CRTCs, no additional checks need be performed
-- 
2.22.1

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[Intel-gfx] Add support for TGL in SAGV code paths

[James Ausmus]

Even though we can't actually turn on SAGV for TGL until HSDES
1409542895 is resolved, these patches prepare the code for enabling
SAGV, so that once the HSDES is resolved, all we have to do is revert
8ffa4392a32e ("drm/i915/tgl: disable SAGV temporarily") to turn it on.


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Re: [Intel-gfx] [PATCH v2] drm/i915/tgl: Add memory type decoding for bandwidth checking

[James Ausmus]

On Wed, Sep 25, 2019 at 07:33:38AM -0700, Summers, Stuart wrote:
> On Tue, 2019-09-24 at 15:28 -0700, James Ausmus wrote:
> > The memory type values have changed in TGL, so we need to translate
> > them
> > differently than ICL. While we're moving it, fix up the ICL
> > translation
> > for LPDDR4.
> > 
> > BSpec: 53998
> > 
> > v2: Fix up ICL LPDDR4 entry (Ville); Drop unused values from TGL
> > (Ville)
> > 
> > Cc: Ville Syrjälä 
> > Cc: Stanislav Lisovskiy 
> > Signed-off-by: James Ausmus 
> > Reviewed-by: Ville Syrjälä 
> > ---
> >  drivers/gpu/drm/i915/display/intel_bw.c | 55 ++-
> > --
> >  1 file changed, 39 insertions(+), 16 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> > b/drivers/gpu/drm/i915/display/intel_bw.c
> > index cd58e47ab7b2..22e83f857de8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bw.c
> > +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> > @@ -35,22 +35,45 @@ static int icl_pcode_read_mem_global_info(struct
> > drm_i915_private *dev_priv,
> > if (ret)
> > return ret;
> >  
> > -   switch (val & 0xf) {
> > -   case 0:
> > -   qi->dram_type = INTEL_DRAM_DDR4;
> > -   break;
> > -   case 1:
> > -   qi->dram_type = INTEL_DRAM_DDR3;
> > -   break;
> > -   case 2:
> > -   qi->dram_type = INTEL_DRAM_LPDDR3;
> > -   break;
> > -   case 3:
> > -   qi->dram_type = INTEL_DRAM_LPDDR3;
> > -   break;
> > -   default:
> > -   MISSING_CASE(val & 0xf);
> > -   break;
> > +   if (IS_GEN(dev_priv, 12)) {
> > +   switch (val & 0xf) {
> > +   case 0:
> > +   qi->dram_type = INTEL_DRAM_DDR4;
> > +   break;
> > +   case 3:
> > +   qi->dram_type = INTEL_DRAM_LPDDR4;
> > +   break;
> > +   case 4:
> > +   qi->dram_type = INTEL_DRAM_DDR3;
> > +   break;
> > +   case 5:
> > +   qi->dram_type = INTEL_DRAM_LPDDR3;
> > +   break;
> > +   default:
> > +   MISSING_CASE(val & 0xf);
> > +   break;
> > +   }
> > +   } else if (IS_GEN(dev_priv, 11)) {
> > +   switch (val & 0xf) {
> > +   case 0:
> > +   qi->dram_type = INTEL_DRAM_DDR4;
> > +   break;
> > +   case 1:
> > +   qi->dram_type = INTEL_DRAM_DDR3;
> > +   break;
> > +   case 2:
> > +   qi->dram_type = INTEL_DRAM_LPDDR3;
> > +   break;
> > +   case 3:
> > +   qi->dram_type = INTEL_DRAM_LPDDR4;
> > +   break;
> > +   default:
> > +   MISSING_CASE(val & 0xf);
> > +   break;
> 
> James, is there a reason we can't just combine these two conditions
> into one switch statement? At initial glance it looks like the cases
> are the same for the common ones and the only real difference is the
> supported bits.

The info I got from the HW guys indicates that the same values are very
likely to have different meanings for different gens, and likely to even
have different values for variants of a single gen, so as more platforms
are added in the future, a single switch would get very messy. Even now,
I think it would be fairly ugly, as it would look something like:

switch (val) {
case 0:
DDR4;
case 1:
if (GEN == 11)
DDR3;
else
MISSING_CASE(val);
case 2:
if (GEN == 11)
LPDDR3;
else
MISSING_CASE(val);
case 3:
LPDDR4;
case 4:
if (GEN == 12)
DDR3;
else
MISSING_CASE(val);
case 5:
if (GEN == 12)
LPDDR3;
else
MISSING_CASE(val);
}

And then start adding special cases for variants within a gen, as well
as additional gen checks, and I think it starts looking fairly
spaghetti. :)

-James

> 
> Thanks,
> Stuart
> 
> > +   }
> > +   } else {
> > +   MISSING_CASE(INTEL_GEN(dev_priv));
> > +   qi->dram_type = INTEL_DRAM_LPDDR3; /* Conservative
> > default */
> > }
> >  
> > qi->num_channels = (val & 0xf0) >> 4;


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[Intel-gfx] [PATCH v2] drm/i915/tgl: Add memory type decoding for bandwidth checking

[James Ausmus]

The memory type values have changed in TGL, so we need to translate them
differently than ICL. While we're moving it, fix up the ICL translation
for LPDDR4.

BSpec: 53998

v2: Fix up ICL LPDDR4 entry (Ville); Drop unused values from TGL (Ville)

Cc: Ville Syrjälä 
Cc: Stanislav Lisovskiy 
Signed-off-by: James Ausmus 
Reviewed-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_bw.c | 55 ++---
 1 file changed, 39 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c 
b/drivers/gpu/drm/i915/display/intel_bw.c
index cd58e47ab7b2..22e83f857de8 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -35,22 +35,45 @@ static int icl_pcode_read_mem_global_info(struct 
drm_i915_private *dev_priv,
if (ret)
return ret;
 
-   switch (val & 0xf) {
-   case 0:
-   qi->dram_type = INTEL_DRAM_DDR4;
-   break;
-   case 1:
-   qi->dram_type = INTEL_DRAM_DDR3;
-   break;
-   case 2:
-   qi->dram_type = INTEL_DRAM_LPDDR3;
-   break;
-   case 3:
-   qi->dram_type = INTEL_DRAM_LPDDR3;
-   break;
-   default:
-   MISSING_CASE(val & 0xf);
-   break;
+   if (IS_GEN(dev_priv, 12)) {
+   switch (val & 0xf) {
+   case 0:
+   qi->dram_type = INTEL_DRAM_DDR4;
+   break;
+   case 3:
+   qi->dram_type = INTEL_DRAM_LPDDR4;
+   break;
+   case 4:
+   qi->dram_type = INTEL_DRAM_DDR3;
+   break;
+   case 5:
+   qi->dram_type = INTEL_DRAM_LPDDR3;
+   break;
+   default:
+   MISSING_CASE(val & 0xf);
+   break;
+   }
+   } else if (IS_GEN(dev_priv, 11)) {
+   switch (val & 0xf) {
+   case 0:
+   qi->dram_type = INTEL_DRAM_DDR4;
+   break;
+   case 1:
+   qi->dram_type = INTEL_DRAM_DDR3;
+   break;
+   case 2:
+   qi->dram_type = INTEL_DRAM_LPDDR3;
+   break;
+   case 3:
+   qi->dram_type = INTEL_DRAM_LPDDR4;
+   break;
+   default:
+   MISSING_CASE(val & 0xf);
+   break;
+   }
+   } else {
+   MISSING_CASE(INTEL_GEN(dev_priv));
+   qi->dram_type = INTEL_DRAM_LPDDR3; /* Conservative default */
}
 
qi->num_channels = (val & 0xf0) >> 4;
-- 
2.22.1

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Re: [Intel-gfx] [v2][PATCH] drm/i915: Add Pipe D cursor ctrl register for Gen12

[James Ausmus]

On Tue, Sep 24, 2019 at 01:01:52PM +0530, Nautiyal, Ankit K wrote:
> From: Ankit Nautiyal 

Just a nit: Can you modify the subject to be "drm/i915/tgl" to make it
easier for backporters to identify?

> 
> Currently the offset for PIPE D cursor control register is missing in
> i915_reg.h due to which the cursor plane cannot be enabled for Pipe D.
> This also causes kernel Warning, when a user requests to enable cursor
> plane for PIPE D for Gen 12 platforms.
> 
> This patch adds the CURSOR_CTL_D register in the i915_reg.h.
> 
> v2: Rebase
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111640
> Signed-off-by: Ankit Nautiyal 
> ---
>  drivers/gpu/drm/i915/i915_pci.c | 10 ++
>  drivers/gpu/drm/i915/i915_reg.h |  1 +
>  2 files changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index c2faa67..dc048d9 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -118,6 +118,15 @@
>   [PIPE_C] = IVB_CURSOR_C_OFFSET, \
>   }
>  
> +#define TGL_CURSOR_OFFSETS \
> + .cursor_offsets = { \
> + [PIPE_A] = CURSOR_A_OFFSET, \
> + [PIPE_B] = IVB_CURSOR_B_OFFSET, \
> + [PIPE_C] = IVB_CURSOR_C_OFFSET, \
> + [PIPE_D] = TGL_CURSOR_D_OFFSET, \
> + }
> +
> +
>  #define I9XX_COLORS \
>   .color = { .gamma_lut_size = 256 }
>  #define I965_COLORS \
> @@ -787,6 +796,7 @@ static const struct intel_device_info 
> intel_elkhartlake_info = {
>   [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
>   [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
>   }, \
> + TGL_CURSOR_OFFSETS, \
>   .has_global_mocs = 1, \
>   .display.has_dsb = 1
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a69c19a..28c483a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6240,6 +6240,7 @@ enum {
>  #define CHV_CURSOR_C_OFFSET 0x700e0
>  #define IVB_CURSOR_B_OFFSET 0x71080
>  #define IVB_CURSOR_C_OFFSET 0x72080
> +#define TGL_CURSOR_D_OFFSET 0x73080
>  
>  /* Display A control */
>  #define _DSPACNTR0x70180
> -- 
> 2.7.4
> 
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Re: [Intel-gfx] [PATCH] drm/i915/tgl: Add memory type decoding for bandwidth checking

[James Ausmus]

On Fri, Sep 20, 2019 at 03:29:06PM +0300, Ville Syrjälä wrote:
> On Thu, Sep 19, 2019 at 03:16:40PM -0700, James Ausmus wrote:
> > The memory type values have changed in TGL, so we need to translate them
> > differently than ICL.
> > 
> > BSpec: 53998
> > 
> > Cc: Ville Syrjälä 
> > Cc: Stanislav Lisovskiy 
> > Signed-off-by: James Ausmus 
> > ---
> >  drivers/gpu/drm/i915/display/intel_bw.c | 59 ++---
> >  1 file changed, 43 insertions(+), 16 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c 
> > b/drivers/gpu/drm/i915/display/intel_bw.c
> > index 688858ebe4d0..11224d9a6752 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bw.c
> > +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> > @@ -35,22 +35,49 @@ static int icl_pcode_read_mem_global_info(struct 
> > drm_i915_private *dev_priv,
> > if (ret)
> > return ret;
> >  
> > -   switch (val & 0xf) {
> > -   case 0:
> > -   qi->dram_type = INTEL_DRAM_DDR4;
> > -   break;
> > -   case 1:
> > -   qi->dram_type = INTEL_DRAM_DDR3;
> > -   break;
> > -   case 2:
> > -   qi->dram_type = INTEL_DRAM_LPDDR3;
> > -   break;
> > -   case 3:
> > -   qi->dram_type = INTEL_DRAM_LPDDR3;
> 
> This should be LPDDR4 actually. Doesn't really matter but would be nice
> to fix as well.

Either my git send-email config or the ML seems to be eating my original
patch mail, and it's not hitting the list, patchwork, or CI, so will
have to send a v2 anyway and I will fix this up in that.

> 
> > -   break;
> > -   default:
> > -   MISSING_CASE(val & 0xf);
> > -   break;
> > +   if (IS_GEN(dev_priv, 12)) {
> > +   switch (val & 0xf) {
> > +   case 0:
> > +   qi->dram_type = INTEL_DRAM_DDR4;
> > +   break;
> > +   case 3:
> > +   qi->dram_type = INTEL_DRAM_LPDDR4;
> > +   break;
> > +   case 4:
> > +   qi->dram_type = INTEL_DRAM_DDR3;
> > +   break;
> > +   case 5:
> > +   qi->dram_type = INTEL_DRAM_LPDDR3;
> > +   break;
> > +   case 1:
> > +   case 2:
> > +   /* Unimplemented */
> 
> Seems pointless to list these.

Will drop in v2.

> 
> The numbers match bspec. Unfortunatley I can't get tgl
> configdb to cooperate so can't double check against the
> MC register definition.
> 
> Reviewed-by: Ville Syrjälä 

Thanks!

-James

> 
> > +   /* fall through */
> > +   default:
> > +   MISSING_CASE(val & 0xf);
> > +   break;
> > +   }
> > +   } else if (IS_GEN(dev_priv, 11)) {
> > +   switch (val & 0xf) {
> > +   case 0:
> > +   qi->dram_type = INTEL_DRAM_DDR4;
> > +   break;
> > +   case 1:
> > +   qi->dram_type = INTEL_DRAM_DDR3;
> > +   break;
> > +   case 2:
> > +   qi->dram_type = INTEL_DRAM_LPDDR3;
> > +   break;
> > +   case 3:
> > +   qi->dram_type = INTEL_DRAM_LPDDR3;
> > +   break;
> > +   default:
> > +   MISSING_CASE(val & 0xf);
> > +   break;
> > +   }
> > +   } else {
> > +   MISSING_CASE(INTEL_GEN(dev_priv));
> > +   qi->dram_type = INTEL_DRAM_LPDDR3; /* Conservative default */
> > }
> >  
> > qi->num_channels = (val & 0xf0) >> 4;
> > -- 
> > 2.22.1
> 
> -- 
> Ville Syrjälä
> Intel
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Re: [Intel-gfx] [PATCH v3] drm/i915: Add TigerLake bandwidth checking

[James Ausmus]

On Wed, Sep 18, 2019 at 04:34:45PM +0300, Stanislav Lisovskiy wrote:
> Added bandwidth calculation algorithm and checks,
> similar way as it was done for ICL, some constants
> were corrected according to BSpec.

BSpec: 53998

> 
> Signed-off-by: Stanislav Lisovskiy 

S-o-b should be last tag, so after the version changelog and the
Bugzilla tag

> 
> v2: Start using same icl_get_bw_info function to avoid
> code duplication. Moved mpagesize to memory info
> related structure as it is now dependant on memory type.
> Fixed qi.t_bl field assignment.
> 
> v3: Removed mpagesize as unused. Duplicate code and redundant blankline
> fixed.
> 
> Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=111600

This should be 

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111600

> ---
>  drivers/gpu/drm/i915/display/intel_bw.c | 25 ++---
>  1 file changed, 18 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c 
> b/drivers/gpu/drm/i915/display/intel_bw.c
> index 688858ebe4d0..7080ec73d33c 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -56,7 +56,11 @@ static int icl_pcode_read_mem_global_info(struct 
> drm_i915_private *dev_priv,
>   qi->num_channels = (val & 0xf0) >> 4;
>   qi->num_points = (val & 0xf00) >> 8;
>  
> - qi->t_bl = qi->dram_type == INTEL_DRAM_DDR4 ? 4 : 8;
> + if (IS_GEN(dev_priv, 11)) {
> + qi->t_bl = qi->dram_type == INTEL_DRAM_DDR4 ? 4 : 8;
> + } else if (IS_GEN(dev_priv, 12)) {

Preferred style is to have gen checks ordered from newest to oldest


> + qi->t_bl = qi->dram_type == INTEL_DRAM_DDR4 ? 4 : 16;
> + }
>  
>   return 0;
>  }
> @@ -132,20 +136,25 @@ static int icl_sagv_max_dclk(const struct 
> intel_qgv_info *qi)
>  }
>  
>  struct intel_sa_info {
> - u8 deburst, mpagesize, deprogbwlimit, displayrtids;
> + u16 displayrtids;
> + u8 deburst, deprogbwlimit;
>  };
>  
>  static const struct intel_sa_info icl_sa_info = {
>   .deburst = 8,
> - .mpagesize = 16,
>   .deprogbwlimit = 25, /* GB/s */
>   .displayrtids = 128,
>  };
>  
> -static int icl_get_bw_info(struct drm_i915_private *dev_priv)
> +static const struct intel_sa_info tgl_sa_info = {
> + .deburst = 16,
> + .deprogbwlimit = 34, /* GB/s */
> + .displayrtids = 256,
> +};
> +
> +static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct 
> intel_sa_info *sa)
>  {
>   struct intel_qgv_info qi = {};
> - const struct intel_sa_info *sa = _sa_info;
>   bool is_y_tile = true; /* assume y tile may be used */
>   int num_channels;
>   int deinterleave;
> @@ -234,13 +243,15 @@ static unsigned int icl_max_bw(struct drm_i915_private 
> *dev_priv,
>  void intel_bw_init_hw(struct drm_i915_private *dev_priv)
>  {
>   if (IS_GEN(dev_priv, 11))
> - icl_get_bw_info(dev_priv);
> + icl_get_bw_info(dev_priv, _sa_info);
> + else if (IS_GEN(dev_priv, 12))

Same comment here


> + icl_get_bw_info(dev_priv, _sa_info);
>  }
>  
>  static unsigned int intel_max_data_rate(struct drm_i915_private *dev_priv,
>   int num_planes)
>  {
> - if (IS_GEN(dev_priv, 11))
> + if (IS_GEN(dev_priv, 11) || IS_GEN(dev_priv, 12))

It would be good to future proof this - if (INTEL_GEN(dev_priv) >= 11)


With the above fixed up,

Reviewed-by: James Ausmus 

>   /*
>* FIXME with SAGV disabled maybe we can assume
>* point 1 will always be used? Seems to match
> -- 
> 2.17.1
> 
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Re: [Intel-gfx] [PATCH v1] drm/i915: Add TigerLake bandwidth checking

[James Ausmus]

On Tue, Sep 17, 2019 at 04:00:57PM +0300, Stanislav Lisovskiy wrote:
> Added bandwidth calculation algorithm and checks,
> similar way as it was done for ICL, some constants
> were corrected according to BSpec.

Heh - I'd been working in this same area, and had some code written up,
but your patch made it to the list first. :)

> 
> Signed-off-by: Stanislav Lisovskiy 
> 
> Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=111600
> ---
>  drivers/gpu/drm/i915/display/intel_bw.c | 108 +++-
>  1 file changed, 107 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c 
> b/drivers/gpu/drm/i915/display/intel_bw.c
> index 688858ebe4d0..e97d083f4f2a 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -132,7 +132,8 @@ static int icl_sagv_max_dclk(const struct intel_qgv_info 
> *qi)
>  }
>  
>  struct intel_sa_info {
> - u8 deburst, mpagesize, deprogbwlimit, displayrtids;
> + u8 deburst, mpagesize, deprogbwlimit;
> + u16 displayrtids;
>  };
>  
>  static const struct intel_sa_info icl_sa_info = {
> @@ -142,6 +143,14 @@ static const struct intel_sa_info icl_sa_info = {
>   .displayrtids = 128,
>  };
>  
> +static const struct intel_sa_info tgl_sa_info = {
> + .deburst = 16,
> + .mpagesize = 16,

This should be 16 only for DDR4, and 32 otherwise - however, it's not
actually used anywhere, so it doesn't matter, but a comment (in case it
needs to be used in the future) would be good.

> + .deprogbwlimit = 34, /* GB/s */
> + .displayrtids = 256,
> +};
> +
> +
>  static int icl_get_bw_info(struct drm_i915_private *dev_priv)
>  {
>   struct intel_qgv_info qi = {};
> @@ -208,6 +217,74 @@ static int icl_get_bw_info(struct drm_i915_private 
> *dev_priv)
>   return 0;
>  }
>  
> +static int tgl_get_bw_info(struct drm_i915_private *dev_priv)
> +{
> + struct intel_qgv_info qi = {};
> + const struct intel_sa_info *sa = _sa_info;
> + bool is_y_tile = true; /* assume y tile may be used */
> + int num_channels;
> + int deinterleave;
> + int ipqdepth, ipqdepthpch;
> + int dclk_max;
> + int maxdebw;
> + int c3_derating = 10;
> + int c25_deprogbwpclimit = 60;
> + int i, ret;
> +
> + ret = icl_get_qgv_points(dev_priv, );
> + if (ret) {
> + DRM_DEBUG_KMS("Failed to get memory subsystem information, 
> ignoring bandwidth limits");
> + return ret;
> + }
> + num_channels = qi.num_channels;
> +
> + deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);
> + dclk_max = icl_sagv_max_dclk();
> +
> + ipqdepthpch = 16;
> +
> + maxdebw = min(sa->deprogbwlimit * 1000,
> +   icl_calc_bw(dclk_max, 16 * c25_deprogbwpclimit, 100)); /* 
> 60% */
> + ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
> +
> + for (i = 0; i < ARRAY_SIZE(dev_priv->max_bw); i++) {
> + struct intel_bw_info *bi = _priv->max_bw[i];
> + int clpchgroup;
> + int j;
> +
> + clpchgroup = (sa->deburst * deinterleave / num_channels) << i;
> + bi->num_planes = (ipqdepth - clpchgroup) / clpchgroup;
> +
> + bi->num_qgv_points = qi.num_points;
> +
> + for (j = 0; j < qi.num_points; j++) {
> + const struct intel_qgv_point *sp = [j];
> + int ct, bw;
> +
> + /*
> +  * Max row cycle time
> +  *
> +  * FIXME what is the logic behind the
> +  * assumed burst length?
> +  */
> + ct = max_t(int, sp->t_rc, sp->t_rp + sp->t_rcd +
> +(clpchgroup - 1) * qi.t_bl + sp->t_rdpre);

qi.t_bl also needs to be set dynamically based on memory type - for
DDR4, 4, otherwise 16


-James

> + bw = icl_calc_bw(sp->dclk, clpchgroup * 32 * 
> num_channels, ct);
> +
> + bi->deratedbw[j] = min(maxdebw,
> +bw * (100 - c3_derating) / 100); 
> /* 90% */
> +
> + DRM_DEBUG_KMS("BW%d / QGV %d: num_planes=%d 
> deratedbw=%u\n",
> +   i, j, bi->num_planes, bi->deratedbw[j]);
> + }
> +
> + if (bi->num_planes == 1)
> + break;
> + }
> +
> + return 0;
> +}
> +
>  static unsigned int icl_max_bw(struct drm_i915_private *dev_priv,
>  int num_planes, int qgv_point)
>  {
> @@ -231,10 +308,35 @@ static unsigned int icl_max_bw(struct drm_i915_private 
> *dev_priv,
>   return 0;
>  }
>  
> +static unsigned int tgl_max_bw(struct drm_i915_private *dev_priv,
> +int num_planes, int qgv_point)
> +{
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(dev_priv->max_bw); i++) {
> + const struct intel_bw_info 

Re: [Intel-gfx] [PATCH 22/22] drm/i915/mst: Do not hardcoded the crtcs that encoder can connect

[James Ausmus]

On Thu, Jul 18, 2019 at 04:10:13PM +0300, Ville Syrjälä wrote:
> On Fri, Jul 12, 2019 at 06:09:40PM -0700, Lucas De Marchi wrote:
> > From: José Roberto de Souza 
> > 
> > Tiger Lake has up to 4 pipes so the mask would need to be 0xf instead of
> > 0x7. Do not hardcode the mask so it allows the fake MST encoders to
> > connect to all pipes no matter how many the platform has.
> > 
> > Iterating over all pipes to keep consistent with intel_ddi_init().
> > 
> > Cc: Lucas De Marchi 
> > Cc: Ville Syrjälä 
> > Signed-off-by: José Roberto de Souza 
> > Signed-off-by: Lucas De Marchi 
> > ---
> >  drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 -
> >  1 file changed, 4 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c 
> > b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > index 60652ebbdf61..1b79b6befa92 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > @@ -586,6 +586,8 @@ intel_dp_create_fake_mst_encoder(struct 
> > intel_digital_port *intel_dig_port, enum
> > struct intel_dp_mst_encoder *intel_mst;
> > struct intel_encoder *intel_encoder;
> > struct drm_device *dev = intel_dig_port->base.base.dev;
> > +   struct drm_i915_private *dev_priv = to_i915(dev);
> > +   enum pipe pipe_iter;
> >  
> > intel_mst = kzalloc(sizeof(*intel_mst), GFP_KERNEL);
> >  
> > @@ -602,8 +604,9 @@ intel_dp_create_fake_mst_encoder(struct 
> > intel_digital_port *intel_dig_port, enum
> > intel_encoder->type = INTEL_OUTPUT_DP_MST;
> > intel_encoder->power_domain = intel_dig_port->base.power_domain;
> > intel_encoder->port = intel_dig_port->base.port;
> > -   intel_encoder->crtc_mask = 0x7;
> > intel_encoder->cloneable = 0;
> > +   for_each_pipe(dev_priv, pipe_iter)
> > +   intel_encoder->crtc_mask |= BIT(pipe_iter);
> 
> https://patchwork.freedesktop.org/patch/316555/?series=63399=1

Would it make sense to bring this patch in for now for TGL MST, until
that larger series can land?

-James

> 
> >  
> > intel_encoder->compute_config = intel_dp_mst_compute_config;
> > intel_encoder->disable = intel_mst_disable_dp;
> > -- 
> > 2.21.0
> 
> -- 
> Ville Syrjälä
> Intel
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Re: [Intel-gfx] [PATCH] drm/i915/icl: Enable DC9 as lowest possible state during screen-off

[James Ausmus]

On Tue, Oct 23, 2018 at 01:34:54PM -0700, Rodrigo Vivi wrote:
> On Tue, Oct 23, 2018 at 01:01:11PM -0700, James Ausmus wrote:
> > On Tue, Oct 23, 2018 at 11:52:31AM -0700, Rodrigo Vivi wrote:
> > > On Tue, Oct 23, 2018 at 11:32:21AM -0700, Anusha Srivatsa wrote:
> > > > From: Animesh Manna 
> > > > 
> > > > ICL supports DC5, DC6, and DC9. Enable DC9 during screen-off, and enable
> > > > DC5/6 when appropriate.
> > > > 
> > > > v2: (James Ausmus)
> > > >  - Also handle ICL as GEN9_LP in i915_drm_suspend_late and
> > > >i915_drm_suspend_early
> > > >  - Add DC9 to gen9_dc_mask for ICL
> > > >  - Re-order GEN checks for newest platform first
> > > >  - Use INTEL_GEN instead of INTEL_INFO->gen
> > > >  - Use INTEL_GEN >= 11 instead of IS_ICELAKE
> > > >  - Consolidate GEN checks
> > > > 
> > > > v3: (James Ausmus)
> > > >  - Also allow DC6 for ICL (Imre, Art)
> > > >  - Simplify !(GEN >= 11) to GEN < 11 (Imre)
> > > > 
> > > > v4: (James Ausmus)
> > > >  - Don't call intel_power_sequencer_reset after DC9 for Gen11+, as the
> > > >PPS regs are Always On
> > > >  - Rebase against upstream changes
> > > > 
> > > > v5: (Anusha Srivatsa)
> > > > - rebased against the latest upstream changes.
> > > > 
> > > > v6: (Anusha Srivatsa)
> > > > - rebased.Use INTEL_GEN consistently.
> > > > - Simplify the code (Rodrigo)
> > > > 
> > > > v7: rebased. Change order according to platforms(Jyoti)
> > > > 
> > > > Cc: Imre Deak 
> > > > Cc: Rodrigo Vivi 
> > > > Signed-off-by: Animesh Manna 
> > > > Signed-off-by: James Ausmus 
> > > > Signed-off-by: Anusha Srivatsa 
> > > > ---
> > > >  drivers/gpu/drm/i915/i915_drv.c | 20 +++---
> > > >  drivers/gpu/drm/i915/intel_drv.h|  3 +++
> > > >  drivers/gpu/drm/i915/intel_runtime_pm.c | 27 +++--
> > > >  3 files changed, 36 insertions(+), 14 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/i915_drv.c 
> > > > b/drivers/gpu/drm/i915/i915_drv.c
> > > > index baac35f698f9..6691b9ee95db 100644
> > > > --- a/drivers/gpu/drm/i915/i915_drv.c
> > > > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > > > @@ -2156,7 +2156,7 @@ static int i915_drm_resume_early(struct 
> > > > drm_device *dev)
> > > >  
> > > > intel_uncore_resume_early(dev_priv);
> > > >  
> > > > -   if (IS_GEN9_LP(dev_priv)) {
> > > > +   if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv)) {
> > > > gen9_sanitize_dc_state(dev_priv);
> > > > bxt_disable_dc9(dev_priv);
> > > > } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> > > > @@ -2923,7 +2923,10 @@ static int intel_runtime_suspend(struct device 
> > > > *kdev)
> > > > intel_uncore_suspend(dev_priv);
> > > >  
> > > > ret = 0;
> > > > -   if (IS_GEN9_LP(dev_priv)) {
> > > > +   if (INTEL_GEN(dev_priv) >= 11) {
> > > > +   icl_display_core_uninit(dev_priv);
> > > > +   bxt_enable_dc9(dev_priv);
> > > > +   } else if (IS_GEN9_LP(dev_priv)) {
> > > > bxt_display_core_uninit(dev_priv);
> > > > bxt_enable_dc9(dev_priv);
> > > > } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> > > > @@ -3008,7 +3011,18 @@ static int intel_runtime_resume(struct device 
> > > > *kdev)
> > > > if (intel_uncore_unclaimed_mmio(dev_priv))
> > > > DRM_DEBUG_DRIVER("Unclaimed access during suspend, 
> > > > bios?\n");
> > > >  
> > > > -   if (IS_GEN9_LP(dev_priv)) {
> > > > +   if (INTEL_GEN(dev_priv) >= 11) {
> > > > +   bxt_disable_dc9(dev_priv);
> > > > +   icl_display_core_init(dev_priv, true);
> > > > +   if (dev_priv->csr.dmc_payload) {
> > > > +   if (dev_priv->csr.allowed_dc_mask &
> > > > +   DC_STATE_EN_UPTO_DC6)
> > > > +   skl_enable_dc6(dev_priv);
&

Re: [Intel-gfx] [PATCH] drm/i915/icl: Enable DC9 as lowest possible state during screen-off

[James Ausmus]

On Tue, Oct 23, 2018 at 11:52:31AM -0700, Rodrigo Vivi wrote:
> On Tue, Oct 23, 2018 at 11:32:21AM -0700, Anusha Srivatsa wrote:
> > From: Animesh Manna 
> > 
> > ICL supports DC5, DC6, and DC9. Enable DC9 during screen-off, and enable
> > DC5/6 when appropriate.
> > 
> > v2: (James Ausmus)
> >  - Also handle ICL as GEN9_LP in i915_drm_suspend_late and
> >i915_drm_suspend_early
> >  - Add DC9 to gen9_dc_mask for ICL
> >  - Re-order GEN checks for newest platform first
> >  - Use INTEL_GEN instead of INTEL_INFO->gen
> >  - Use INTEL_GEN >= 11 instead of IS_ICELAKE
> >  - Consolidate GEN checks
> > 
> > v3: (James Ausmus)
> >  - Also allow DC6 for ICL (Imre, Art)
> >  - Simplify !(GEN >= 11) to GEN < 11 (Imre)
> > 
> > v4: (James Ausmus)
> >  - Don't call intel_power_sequencer_reset after DC9 for Gen11+, as the
> >PPS regs are Always On
> >  - Rebase against upstream changes
> > 
> > v5: (Anusha Srivatsa)
> > - rebased against the latest upstream changes.
> > 
> > v6: (Anusha Srivatsa)
> > - rebased.Use INTEL_GEN consistently.
> > - Simplify the code (Rodrigo)
> > 
> > v7: rebased. Change order according to platforms(Jyoti)
> > 
> > Cc: Imre Deak 
> > Cc: Rodrigo Vivi 
> > Signed-off-by: Animesh Manna 
> > Signed-off-by: James Ausmus 
> > Signed-off-by: Anusha Srivatsa 
> > ---
> >  drivers/gpu/drm/i915/i915_drv.c | 20 +++---
> >  drivers/gpu/drm/i915/intel_drv.h|  3 +++
> >  drivers/gpu/drm/i915/intel_runtime_pm.c | 27 +++--
> >  3 files changed, 36 insertions(+), 14 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.c 
> > b/drivers/gpu/drm/i915/i915_drv.c
> > index baac35f698f9..6691b9ee95db 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.c
> > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > @@ -2156,7 +2156,7 @@ static int i915_drm_resume_early(struct drm_device 
> > *dev)
> >  
> > intel_uncore_resume_early(dev_priv);
> >  
> > -   if (IS_GEN9_LP(dev_priv)) {
> > +   if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv)) {
> > gen9_sanitize_dc_state(dev_priv);
> > bxt_disable_dc9(dev_priv);
> > } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> > @@ -2923,7 +2923,10 @@ static int intel_runtime_suspend(struct device *kdev)
> > intel_uncore_suspend(dev_priv);
> >  
> > ret = 0;
> > -   if (IS_GEN9_LP(dev_priv)) {
> > +   if (INTEL_GEN(dev_priv) >= 11) {
> > +   icl_display_core_uninit(dev_priv);
> > +   bxt_enable_dc9(dev_priv);
> > +   } else if (IS_GEN9_LP(dev_priv)) {
> > bxt_display_core_uninit(dev_priv);
> > bxt_enable_dc9(dev_priv);
> > } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> > @@ -3008,7 +3011,18 @@ static int intel_runtime_resume(struct device *kdev)
> > if (intel_uncore_unclaimed_mmio(dev_priv))
> > DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
> >  
> > -   if (IS_GEN9_LP(dev_priv)) {
> > +   if (INTEL_GEN(dev_priv) >= 11) {
> > +   bxt_disable_dc9(dev_priv);
> > +   icl_display_core_init(dev_priv, true);
> > +   if (dev_priv->csr.dmc_payload) {
> > +   if (dev_priv->csr.allowed_dc_mask &
> > +   DC_STATE_EN_UPTO_DC6)
> > +   skl_enable_dc6(dev_priv);
> > +   else if (dev_priv->csr.allowed_dc_mask &
> > +DC_STATE_EN_UPTO_DC5)
> > +   gen9_enable_dc5(dev_priv);
> > +   }
> > +   } else if (IS_GEN9_LP(dev_priv)) {
> > bxt_disable_dc9(dev_priv);
> > bxt_display_core_init(dev_priv, true);
> > if (dev_priv->csr.dmc_payload &&
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h 
> > b/drivers/gpu/drm/i915/intel_drv.h
> > index 0e9a926fca04..529ff19a5e48 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -1640,6 +1640,7 @@ void bxt_enable_dc9(struct drm_i915_private 
> > *dev_priv);
> >  void bxt_disable_dc9(struct drm_i915_private *dev_priv);
> >  void gen9_enable_dc5(struct drm_i915_private *dev_priv);
> >  unsigned int skl_cdclk_get_vco(unsigned int freq);
> > +void skl_enable_dc6(struct drm_i915_private *dev_priv);
> >  void intel_dp_get_m_n(struct intel_crtc *crtc,
> > 

Re: [Intel-gfx] [PATCH 27/24] drm/i915/dp: Add support for HBR3 and TPS4 during link training

[James Ausmus]

On Thu, May 24, 2018 at 04:42:38PM -0700, Paulo Zanoni wrote:
> From: Manasi Navare <manasi.d.nav...@intel.com>
> 
> DP spec 1.4 supports training pattern set 4 (TPS4) for HBR3 link
> rate. This will be used in link training's channel equalization
> phase if supported by both source and sink.
> This patch adds the helpers to check if HBR3 is supported and uses
> TPS4 in training pattern selection during link training.
> 
> Cc: James Ausmus <james.aus...@intel.com>
> Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
> Cc: Jani Nikula <jani.nik...@linux.intel.com>
> Signed-off-by: Manasi Navare <manasi.d.nav...@intel.com>

Reviewed-by: James Ausmus <james.aus...@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h   |  1 +
>  drivers/gpu/drm/i915/intel_dp.c   | 17 +---
>  drivers/gpu/drm/i915/intel_dp_link_training.c | 39 
> +++
>  drivers/gpu/drm/i915/intel_drv.h  |  1 +
>  4 files changed, 44 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e48b717769b2..ae7070c0806d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8791,6 +8791,7 @@ enum skl_power_gate {
>  #define  DP_TP_CTL_LINK_TRAIN_PAT1   (0<<8)
>  #define  DP_TP_CTL_LINK_TRAIN_PAT2   (1<<8)
>  #define  DP_TP_CTL_LINK_TRAIN_PAT3   (4<<8)
> +#define  DP_TP_CTL_LINK_TRAIN_PAT4   (5<<8)
>  #define  DP_TP_CTL_LINK_TRAIN_IDLE   (2<<8)
>  #define  DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8)
>  #define  DP_TP_CTL_SCRAMBLE_DISABLE  (1<<7)
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 3ee8e74cf2b8..bcc3f330b301 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1721,6 +1721,13 @@ bool intel_dp_source_supports_hbr2(struct intel_dp 
> *intel_dp)
>   return max_rate >= 54;
>  }
>  
> +bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp)
> +{
> + int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
> +
> + return max_rate >= 81;
> +}
> +
>  static void
>  intel_dp_set_clock(struct intel_encoder *encoder,
>  struct intel_crtc_state *pipe_config)
> @@ -3046,10 +3053,11 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
>   struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
>   struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>   enum port port = intel_dig_port->base.port;
> + uint8_t train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
>  
> - if (dp_train_pat & DP_TRAINING_PATTERN_MASK)
> + if (dp_train_pat & train_pat_mask)
>   DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
> -   dp_train_pat & DP_TRAINING_PATTERN_MASK);
> +   dp_train_pat & train_pat_mask);
>  
>   if (HAS_DDI(dev_priv)) {
>   uint32_t temp = I915_READ(DP_TP_CTL(port));
> @@ -3060,7 +3068,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
>   temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
>  
>   temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
> - switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
> + switch (dp_train_pat & train_pat_mask) {
>   case DP_TRAINING_PATTERN_DISABLE:
>   temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
>  
> @@ -3074,6 +3082,9 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
>   case DP_TRAINING_PATTERN_3:
>   temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
>   break;
> + case DP_TRAINING_PATTERN_4:
> + temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
> + break;
>   }
>   I915_WRITE(DP_TP_CTL(port), temp);
>  
> diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c 
> b/drivers/gpu/drm/i915/intel_dp_link_training.c
> index 3fcaa98b9055..4da6e33c7fa1 100644
> --- a/drivers/gpu/drm/i915/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
> @@ -219,14 +219,30 @@ intel_dp_link_training_clock_recovery(struct intel_dp 
> *intel_dp)
>  }
>  
>  /*
> - * Pick training pattern for channel equalization. Training Pattern 3 for 
> HBR2
> + * Pick training pattern for channel equalization. Training pattern 4 for 
> HBR3
> + * or for 1.4 devices that support it, training Pattern 3 for HBR2
>   * or 1.2 devices that support i

Re: [Intel-gfx] [PATCH 26/24] drm/i915/icl: Add allowed DP rates for Icelake

[James Ausmus]

On Thu, May 24, 2018 at 04:42:37PM -0700, Paulo Zanoni wrote:
> From: Manasi Navare <manasi.d.nav...@intel.com>
> 
> For ICL, on Combo PHY the allowed max rates are:
>  - HBR3 8.1 eDP (DDIA)
>  - HBR2 5.4 DisplayPort (DDIB)
> and for MG PHY/TC DDI Ports allowed DP rates are:
>  - HBR3 8.1 DisplayPort (DP alternate mode, DP over TBT,
>  - DP on legacy connector - DDIC/D/E/F)
> 
> Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
> Cc: Jani Nikula <jani.nik...@linux.intel.com>
> Cc: James Ausmus <james.aus...@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.nav...@intel.com>
> Signed-off-by: James Ausmus <james.aus...@intel.com>

Reviewed-by: James Ausmus <james.aus...@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_dp.c | 21 +++--
>  1 file changed, 19 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 5109023abe28..3ee8e74cf2b8 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -419,6 +419,20 @@ static int cnl_max_source_rate(struct intel_dp *intel_dp)
>   return 81;
>  }
>  
> +static int icl_max_source_rate(struct intel_dp *intel_dp)
> +{
> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> + enum port port = dig_port->base.port;
> +
> + /* On Combo PHY port A max speed is HBR3 for all Vccio voltages
> +  * and on Combo PHY Port B the maximum supported is HBR2.
> +  */
> + if (port == PORT_B)
> + return 54;
> +
> + return 81;
> +}
> +
>  static void
>  intel_dp_set_source_rates(struct intel_dp *intel_dp)
>  {
> @@ -448,10 +462,13 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
>   /* This should only be done once */
>   WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
>  
> - if (IS_CANNONLAKE(dev_priv)) {
> + if (INTEL_GEN(dev_priv) >= 10) {
>   source_rates = cnl_rates;
>   size = ARRAY_SIZE(cnl_rates);
> - max_rate = cnl_max_source_rate(intel_dp);
> + if (IS_ICELAKE(dev_priv))
> + max_rate = icl_max_source_rate(intel_dp);
> + else
> + max_rate = cnl_max_source_rate(intel_dp);
>   } else if (IS_GEN9_LP(dev_priv)) {
>   source_rates = bxt_rates;
>   size = ARRAY_SIZE(bxt_rates);
> -- 
> 2.14.3
> 
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Re: [Intel-gfx] [PATCH 08/24] drm/i915/icl: Map VBT DDC Pin to BSpec DDC Pin

[James Ausmus]

On Mon, May 21, 2018 at 05:25:42PM -0700, Paulo Zanoni wrote:
> From: "Sripada, Radhakrishna" <radhakrishna.srip...@intel.com>
> 
> On ICL we need to map VBT DDC Pin to BSpec DDC Pin.
> Adding ICL Pin Values.
> 
> According to VBT
> Block 2 (General Bytes Definition)
> DDC Bus
> 
> +--+---++
> | DDI Type | VBT Value | BSpec Mapped Value |
> +--+---++
> | DDI-A| 0x1   | 0x1|
> | DDI-B| 0x2   | 0x2|
> | PORT-1   | 0x4   | 0x9|
> | PORT-2   | 0x5   | 0xA|
> | PORT-3   | 0x6   | 0xB|
> | PORT-4   | 0x7   | 0xC    |
> +--+---++
> 
> Cc: James Ausmus <james.aus...@intel.com>
> Cc: Jani Nikula <jani.nik...@intel.com>
> Cc: Anusha Srivatsa <anusha.sriva...@intel.com>
> Cc: Clinton Taylor <clinton.a.tay...@intel.com>
> Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
> Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
> Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.srip...@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.v...@intel.com>
> [Paulo: checkpatch fixes.]
> Signed-off-by: Paulo Zanoni <paulo.r.zan...@intel.com>

Matches BSpec, looks good!

Reviewed-by: James Ausmus <james.aus...@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_bios.c | 35 
> +++
>  drivers/gpu/drm/i915/intel_vbt_defs.h |  6 ++
>  2 files changed, 33 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_bios.c 
> b/drivers/gpu/drm/i915/intel_bios.c
> index 54270bdde100..34e9bca36c14 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -1197,18 +1197,37 @@ static const u8 cnp_ddc_pin_map[] = {
>   [DDC_BUS_DDI_F] = GMBUS_PIN_3_BXT, /* sic */
>  };
>  
> +static const u8 icp_ddc_pin_map[] = {
> + [ICL_DDC_BUS_DDI_A] = GMBUS_PIN_1_BXT,
> + [ICL_DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT,
> + [ICL_DDC_BUS_PORT_1] = GMBUS_PIN_9_TC1_ICP,
> + [ICL_DDC_BUS_PORT_2] = GMBUS_PIN_10_TC2_ICP,
> + [ICL_DDC_BUS_PORT_3] = GMBUS_PIN_11_TC3_ICP,
> + [ICL_DDC_BUS_PORT_4] = GMBUS_PIN_12_TC4_ICP,
> +};
> +
>  static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
>  {
> - if (HAS_PCH_CNP(dev_priv)) {
> - if (vbt_pin < ARRAY_SIZE(cnp_ddc_pin_map)) {
> - return cnp_ddc_pin_map[vbt_pin];
> - } else {
> - DRM_DEBUG_KMS("Ignoring alternate pin: VBT claims DDC 
> pin %d, which is not valid for this platform\n", vbt_pin);
> - return 0;
> - }
> + const u8 *ddc_pin_map;
> + int n_entries;
> +
> + if (HAS_PCH_ICP(dev_priv)) {
> + ddc_pin_map = icp_ddc_pin_map;
> + n_entries = ARRAY_SIZE(icp_ddc_pin_map);
> + } else if (HAS_PCH_CNP(dev_priv)) {
> + ddc_pin_map = cnp_ddc_pin_map;
> + n_entries = ARRAY_SIZE(cnp_ddc_pin_map);
> + } else {
> + /* Assuming direct map */
> + return vbt_pin;
>   }
>  
> - return vbt_pin;
> + if (vbt_pin < n_entries && ddc_pin_map[vbt_pin] != 0)
> + return ddc_pin_map[vbt_pin];
> +
> + DRM_DEBUG_KMS("Ignoring alternate pin: VBT claims DDC pin %d, which is 
> not valid for this platform\n",
> +   vbt_pin);
> + return 0;
>  }
>  
>  static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port,
> diff --git a/drivers/gpu/drm/i915/intel_vbt_defs.h 
> b/drivers/gpu/drm/i915/intel_vbt_defs.h
> index 458468237b5f..7c798c18600e 100644
> --- a/drivers/gpu/drm/i915/intel_vbt_defs.h
> +++ b/drivers/gpu/drm/i915/intel_vbt_defs.h
> @@ -318,6 +318,12 @@ enum vbt_gmbus_ddi {
>   DDC_BUS_DDI_C,
>   DDC_BUS_DDI_D,
>   DDC_BUS_DDI_F,
> + ICL_DDC_BUS_DDI_A = 0x1,
> + ICL_DDC_BUS_DDI_B,
> + ICL_DDC_BUS_PORT_1 = 0x4,
> + ICL_DDC_BUS_PORT_2,
> + ICL_DDC_BUS_PORT_3,
> + ICL_DDC_BUS_PORT_4,
>  };
>  
>  #define VBT_DP_MAX_LINK_RATE_HBR30
> -- 
> 2.14.3
> 
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Re: [Intel-gfx] [PATCH 3/8] drm/i915/icl: add basic support for the ICL clocks

[James Ausmus]

On Fri, Apr 27, 2018 at 04:14:36PM -0700, Paulo Zanoni wrote:
> This commit introduces the definitions for the ICL clocks and adds the
> basic functions to the shared DPLL framework. It adds code for the
> Enable and Disable sequences for some PLLs, but it does not have the
> code to compute the actual PLL values, which are marked as TODO
> comments and should be introduced as separate commits.
> 
> Special thanks to James Ausmus for investigating and fixing a bug with
> the placement of icl_unmap_plls_to_ports() function.
> 
> v2:
>  - Rebase around dpll_lock changes.
> v3:
>  - The spec now says what the timeouts should be.
>  - Touch DPCLKA_CFGCR0_ICL at the appropriate time so we don't freeze
>the machine.
>  - Checkpatch found a white space problem.
>  - Small adjustments before upstreaming.
> v4:
>  - Move the ICL checks out of the *map_plls_to_ports() functions
>   (James)
>  - Add extra encoder check (James)
>  - Call icl_unmap_plls_to_ports() later (James)
> v5:
>  - Rebase after the pll struct changes.
> v6:
>  - Properly make the unmap function based on encoders_post_disable()
>with regarding to checks and iterators.
>  - Address checkpatch comment on "min = max = x()".
> 
> Cc: James Ausmus <james.aus...@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zan...@intel.com>

Reviewed-by: James Ausmus <james.aus...@intel.com>


> ---
>  drivers/gpu/drm/i915/i915_debugfs.c   |  22 +++
>  drivers/gpu/drm/i915/intel_ddi.c  |  98 ++-
>  drivers/gpu/drm/i915/intel_display.c  |  16 ++
>  drivers/gpu/drm/i915/intel_dpll_mgr.c | 313 
> +-
>  drivers/gpu/drm/i915/intel_dpll_mgr.h |  41 +
>  drivers/gpu/drm/i915/intel_drv.h  |   6 +
>  6 files changed, 491 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index cb1a804bf72e..ba8927cb1dcc 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -3365,6 +3365,28 @@ static int i915_shared_dplls_info(struct seq_file *m, 
> void *unused)
>   seq_printf(m, " fp0: 0x%08x\n", pll->state.hw_state.fp0);
>   seq_printf(m, " fp1: 0x%08x\n", pll->state.hw_state.fp1);
>   seq_printf(m, " wrpll:   0x%08x\n", pll->state.hw_state.wrpll);
> + seq_printf(m, " cfgcr0:  0x%08x\n", pll->state.hw_state.cfgcr0);
> + seq_printf(m, " cfgcr1:  0x%08x\n", pll->state.hw_state.cfgcr1);
> + seq_printf(m, " mg_refclkin_ctl:0x%08x\n",
> +pll->state.hw_state.mg_refclkin_ctl);
> + seq_printf(m, " mg_clktop2_coreclkctl1: 0x%08x\n",
> +pll->state.hw_state.mg_clktop2_coreclkctl1);
> + seq_printf(m, " mg_clktop2_hsclkctl:0x%08x\n",
> +pll->state.hw_state.mg_clktop2_hsclkctl);
> + seq_printf(m, " mg_pll_div0:  0x%08x\n",
> +pll->state.hw_state.mg_pll_div0);
> + seq_printf(m, " mg_pll_div1:  0x%08x\n",
> +pll->state.hw_state.mg_pll_div1);
> + seq_printf(m, " mg_pll_lf:0x%08x\n",
> +pll->state.hw_state.mg_pll_lf);
> + seq_printf(m, " mg_pll_frac_lock: 0x%08x\n",
> +pll->state.hw_state.mg_pll_frac_lock);
> + seq_printf(m, " mg_pll_ssc:   0x%08x\n",
> +pll->state.hw_state.mg_pll_ssc);
> + seq_printf(m, " mg_pll_bias:  0x%08x\n",
> +pll->state.hw_state.mg_pll_bias);
> + seq_printf(m, " mg_pll_tdc_coldst_bias: 0x%08x\n",
> +pll->state.hw_state.mg_pll_tdc_coldst_bias);
>   }
>   drm_modeset_unlock_all(dev);
>  
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 92cb26b18a9b..178a7b0d0149 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1013,6 +1013,25 @@ static uint32_t hsw_pll_to_ddi_pll_sel(const struct 
> intel_shared_dpll *pll)
>   }
>  }
>  
> +static uint32_t icl_pll_to_ddi_pll_sel(struct intel_encoder *encoder,
> +const struct intel_shared_dpll *pll)
> +{
> + const enum intel_dpll_id id = pll->info->id;
> +
> + switch (id) {
> + default:
> + MISSING_CASE(id);
> + case DPLL_ID_ICL_DPLL0:
> + case DPLL

Re: [Intel-gfx] [PATCH 2/8] drm/i915/icl: add definitions for the ICL PLL registers

[James Ausmus]

On Wed, Mar 28, 2018 at 02:57:57PM -0700, Paulo Zanoni wrote:
> There's a lot of code for the PLL enabling, so let's first only
> introduce the register definitions in order to make patch reviewing a
> little easier.
> 
> v2: Coding style (Jani).
> v3: Preparation for upstreaming.
> v4: Fix MG_CLKTOP2_CORECLKCTL1 address and random typos (James).
> 
> Cc: James Ausmus <james.aus...@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zan...@intel.com>

Reviewed-by: James Ausmus <james.aus...@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 149 
> 
>  1 file changed, 149 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 250ff271bcf1..b79b2a8930da 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8701,6 +8701,12 @@ enum skl_power_gate {
>  #define  PORT_CLK_SEL_NONE   (7<<29)
>  #define  PORT_CLK_SEL_MASK   (7<<29)
>  
> +/* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */
> +#define DDI_CLK_SEL(port)PORT_CLK_SEL(port)
> +#define  DDI_CLK_SEL_NONE(0x0 << 28)
> +#define  DDI_CLK_SEL_MG  (0x8 << 28)
> +#define  DDI_CLK_SEL_MASK(0xF << 28)
> +
>  /* Transcoder clock selection */
>  #define _TRANS_CLK_SEL_A 0x46140
>  #define _TRANS_CLK_SEL_B 0x46144
> @@ -8831,6 +8837,7 @@ enum skl_power_gate {
>   * CNL Clocks
>   */
>  #define DPCLKA_CFGCR0_MMIO(0x6C200)
> +#define DPCLKA_CFGCR0_ICL_MMIO(0x164280)
>  #define  DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) ==  PORT_F ? 23 : 
> \
> (port)+10))
>  #define  DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)   ((port) == PORT_F ? 21 
> : \
> @@ -8847,10 +8854,141 @@ enum skl_power_gate {
>  #define  PLL_POWER_STATE (1 << 26)
>  #define CNL_DPLL_ENABLE(pll) _MMIO_PLL(pll, DPLL0_ENABLE, DPLL1_ENABLE)
>  
> +#define _MG_PLL1_ENABLE  0x46030
> +#define _MG_PLL2_ENABLE  0x46034
> +#define _MG_PLL3_ENABLE  0x46038
> +#define _MG_PLL4_ENABLE  0x4603C
> +/* Bits are the same as DPLL0_ENABLE */
> +#define MG_PLL_ENABLE(port)  _MMIO_PORT((port) - PORT_C, _MG_PLL1_ENABLE, \
> +_MG_PLL2_ENABLE)
> +
> +#define _MG_REFCLKIN_CTL_PORT1   0x16892C
> +#define _MG_REFCLKIN_CTL_PORT2   0x16992C
> +#define _MG_REFCLKIN_CTL_PORT3   0x16A92C
> +#define _MG_REFCLKIN_CTL_PORT4   0x16B92C
> +#define   MG_REFCLKIN_CTL_OD_2_MUX(x)((x) << 8)
> +#define MG_REFCLKIN_CTL(port) _MMIO_PORT((port) - PORT_C, \
> +  _MG_REFCLKIN_CTL_PORT1, \
> +  _MG_REFCLKIN_CTL_PORT2)
> +
> +#define _MG_CLKTOP2_CORECLKCTL1_PORT10x1688D8
> +#define _MG_CLKTOP2_CORECLKCTL1_PORT20x1698D8
> +#define _MG_CLKTOP2_CORECLKCTL1_PORT30x16A8D8
> +#define _MG_CLKTOP2_CORECLKCTL1_PORT40x16B8D8
> +#define   MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO(x)   ((x) << 16)
> +#define   MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(x)   ((x) << 8)
> +#define MG_CLKTOP2_CORECLKCTL1(port) _MMIO_PORT((port) - PORT_C, \
> + _MG_CLKTOP2_CORECLKCTL1_PORT1, \
> + _MG_CLKTOP2_CORECLKCTL1_PORT2)
> +
> +#define _MG_CLKTOP2_HSCLKCTL_PORT1   0x1688D4
> +#define _MG_CLKTOP2_HSCLKCTL_PORT2   0x1698D4
> +#define _MG_CLKTOP2_HSCLKCTL_PORT3   0x16A8D4
> +#define _MG_CLKTOP2_HSCLKCTL_PORT4   0x16B8D4
> +#define   MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(x)   ((x) << 16)
> +#define   MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(x) ((x) << 14)
> +#define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO(x) ((x) << 12)
> +#define   MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x) ((x) << 8)
> +#define MG_CLKTOP2_HSCLKCTL(port) _MMIO_PORT((port) - PORT_C, \
> +  _MG_CLKTOP2_HSCLKCTL_PORT1, \
> +  _MG_CLKTOP2_HSCLKCTL_PORT2)
> +
> +#define _MG_PLL_DIV0_PORT1   0x168A00
> +#define _MG_PLL_DIV0_PORT2   0x169A00
> +#define _MG_PLL_DIV0_PORT3  

Re: [Intel-gfx] [PATCH 3/8] drm/i915/icl: add basic support for the ICL clocks

[James Ausmus]

On Wed, Mar 28, 2018 at 02:57:58PM -0700, Paulo Zanoni wrote:
> This commit introduces the definitions for the ICL clocks and adds the
> basic functions to the shared DPLL framework. It adds code for the
> Enable and Disable sequences for some PLLs, but it does not have the
> code to compute the actual PLL values, which are marked as TODO
> comments and should be introduced as separate commits.
> 
> Special thanks to James Ausmus for investigating and fixing a bug with
> the placement of icl_unmap_plls_to_ports() function.
> 
> v2:
>  - Rebase around dpll_lock changes.
> v3:
>  - The spec now says what the timeouts should be.
>  - Touch DPCLKA_CFGCR0_ICL at the appropriate time so we don't freeze
>the machine.
>  - Checkpatch found a white space problem.
>  - Small adjustments before upstreaming.
> v4:
>  - Move the ICL checks out of the *map_plls_to_ports() functions
>   (James)
>  - Add extra encoder check (James)
>  - Call icl_unmap_plls_to_ports() later (James)
> v5:
>  - Rebase after the pll struct changes.
> 
> Cc: James Ausmus <james.aus...@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zan...@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c   |  22 +++
>  drivers/gpu/drm/i915/intel_ddi.c  |  98 ++-
>  drivers/gpu/drm/i915/intel_display.c  |  16 ++
>  drivers/gpu/drm/i915/intel_dpll_mgr.c | 312 
> +-
>  drivers/gpu/drm/i915/intel_dpll_mgr.h |  41 +
>  drivers/gpu/drm/i915/intel_drv.h  |   6 +
>  6 files changed, 490 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index ff90577da450..43a805c39b0a 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -3296,6 +3296,28 @@ static int i915_shared_dplls_info(struct seq_file *m, 
> void *unused)
>   seq_printf(m, " fp0: 0x%08x\n", pll->state.hw_state.fp0);
>   seq_printf(m, " fp1: 0x%08x\n", pll->state.hw_state.fp1);
>   seq_printf(m, " wrpll:   0x%08x\n", pll->state.hw_state.wrpll);
> + seq_printf(m, " cfgcr0:  0x%08x\n", pll->state.hw_state.cfgcr0);
> + seq_printf(m, " cfgcr1:  0x%08x\n", pll->state.hw_state.cfgcr1);
> + seq_printf(m, " mg_refclkin_ctl:0x%08x\n",
> +pll->state.hw_state.mg_refclkin_ctl);
> + seq_printf(m, " mg_clktop2_coreclkctl1: 0x%08x\n",
> +pll->state.hw_state.mg_clktop2_coreclkctl1);
> + seq_printf(m, " mg_clktop2_hsclkctl:0x%08x\n",
> +pll->state.hw_state.mg_clktop2_hsclkctl);
> + seq_printf(m, " mg_pll_div0:  0x%08x\n",
> +pll->state.hw_state.mg_pll_div0);
> + seq_printf(m, " mg_pll_div1:  0x%08x\n",
> +pll->state.hw_state.mg_pll_div1);
> + seq_printf(m, " mg_pll_lf:0x%08x\n",
> +pll->state.hw_state.mg_pll_lf);
> + seq_printf(m, " mg_pll_frac_lock: 0x%08x\n",
> +pll->state.hw_state.mg_pll_frac_lock);
> + seq_printf(m, " mg_pll_ssc:   0x%08x\n",
> +pll->state.hw_state.mg_pll_ssc);
> + seq_printf(m, " mg_pll_bias:  0x%08x\n",
> +pll->state.hw_state.mg_pll_bias);
> + seq_printf(m, " mg_pll_tdc_coldst_bias: 0x%08x\n",
> +pll->state.hw_state.mg_pll_tdc_coldst_bias);
>   }
>   drm_modeset_unlock_all(dev);
>  
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> b/drivers/gpu/drm/i915/intel_ddi.c
> index a6672a9abd85..10223ffcceab 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1013,6 +1013,25 @@ static uint32_t hsw_pll_to_ddi_pll_sel(const struct 
> intel_shared_dpll *pll)
>   }
>  }
>  
> +static uint32_t icl_pll_to_ddi_pll_sel(struct intel_encoder *encoder,
> +const struct intel_shared_dpll *pll)
> +{
> + const enum intel_dpll_id id = pll->info->id;
> +
> + switch (id) {
> + default:
> + MISSING_CASE(id);
> + case DPLL_ID_ICL_DPLL0:
> + case DPLL_ID_ICL_DPLL1:
> + return DDI_CLK_SEL_NONE;
> + case DPLL_ID_ICL_MGPLL1:
> + case DPLL_ID_ICL_MGPLL2:
> + case DPLL_ID_ICL_MGPLL3:
> + case DPLL_ID_ICL_MGPLL4:
> + return DDI_CLK_SEL_M

Re: [Intel-gfx] [PATCH 04/17] drm/i915/icl: compute the combo PHY (DPLL) DP registers

[James Ausmus]

On Thu, Feb 22, 2018 at 12:55:06AM -0300, Paulo Zanoni wrote:
> Just use the hardcoded tables provided by our spec.
> 
> v2: Rebase.
> 
> Signed-off-by: Paulo Zanoni <paulo.r.zan...@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dpll_mgr.c | 86 
> ++-
>  1 file changed, 85 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c 
> b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 4d9265d14661..5d7bacc80688 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -2389,6 +2389,90 @@ static const struct intel_dpll_mgr cnl_pll_mgr = {
>   .dump_hw_state = cnl_dump_hw_state,
>  };
>  
> +/*
> + * These values alrea already adjusted: they're the bits we write to the
> + * registers, not the logical values.
> + */
> +static const struct skl_wrpll_params icl_dp_combo_pll_24MHz_values[] = {
> + { .dco_integer = 0x151, .dco_fraction = 0x4000, /* [0]: 5.4 */
> +   .pdiv = 0x2 /* 3 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0},
> + { .dco_integer = 0x151, .dco_fraction = 0x4000, /* [1]: 2.7 */
> +   .pdiv = 0x2 /* 3 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0},
> + { .dco_integer = 0x151, .dco_fraction = 0x4000, /* [2]: 1.62 */
> +   .pdiv = 0x4 /* 5 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0},
> + { .dco_integer = 0x151, .dco_fraction = 0x4000, /* [3]: 3.24 */
> +   .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0},
> + { .dco_integer = 0x168, .dco_fraction = 0x, /* [4]: 2.16 */
> +   .pdiv = 0x1 /* 2 */, .kdiv = 2, .qdiv_mode = 1, .qdiv_ratio = 2},
> + { .dco_integer = 0x168, .dco_fraction = 0x, /* [5]: 4.32 */
> +   .pdiv = 0x1 /* 2 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0},
> + { .dco_integer = 0x195, .dco_fraction = 0x, /* [6]: 6.48 */
> +   .pdiv = 0x2 /* 3 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0},
> + { .dco_integer = 0x151, .dco_fraction = 0x4000, /* [7]: 8.1 */
> +   .pdiv = 0x1 /* 2 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0},
> +};
> +

Maybe:

/* Also used for 38.4MHz values */

Either way -

Reviewed-by: James Ausmus <james.aus...@intel.com>

> +static const struct skl_wrpll_params icl_dp_combo_pll_19_2MHz_values[] = {
> + { .dco_integer = 0x1A5, .dco_fraction = 0x7000, /* [0]: 5.4 */
> +   .pdiv = 0x2 /* 3 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0},
> + { .dco_integer = 0x1A5, .dco_fraction = 0x7000, /* [1]: 2.7 */
> +   .pdiv = 0x2 /* 3 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0},
> + { .dco_integer = 0x1A5, .dco_fraction = 0x7000, /* [2]: 1.62 */
> +   .pdiv = 0x4 /* 5 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0},
> + { .dco_integer = 0x1A5, .dco_fraction = 0x7000, /* [3]: 3.24 */
> +   .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0},
> + { .dco_integer = 0x1C2, .dco_fraction = 0x, /* [4]: 2.16 */
> +   .pdiv = 0x1 /* 2 */, .kdiv = 2, .qdiv_mode = 1, .qdiv_ratio = 2},
> + { .dco_integer = 0x1C2, .dco_fraction = 0x, /* [5]: 4.32 */
> +   .pdiv = 0x1 /* 2 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0},
> + { .dco_integer = 0x1FA, .dco_fraction = 0x2000, /* [6]: 6.48 */
> +   .pdiv = 0x2 /* 3 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0},
> + { .dco_integer = 0x1A5, .dco_fraction = 0x7000, /* [7]: 8.1 */
> +   .pdiv = 0x1 /* 2 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0},
> +};
> +
> +static bool icl_calc_dp_combo_pll(struct drm_i915_private *dev_priv, int 
> clock,
> +   struct skl_wrpll_params *pll_params)
> +{
> + const struct skl_wrpll_params *params;
> +
> + params = dev_priv->cdclk.hw.ref == 24000 ?
> + icl_dp_combo_pll_24MHz_values :
> + icl_dp_combo_pll_19_2MHz_values;
> +
> + switch (clock) {
> + case 54:
> + *pll_params = params[0];
> + break;
> + case 27:
> + *pll_params = params[1];
> + break;
> + case 162000:
> + *pll_params = params[2];
> + break;
> + case 324000:
> + *pll_params = params[3];
> + break;
> + case 216000:
> + *pll_params = params[4];
> + break;
> + case 432000:
> + *pll_params = params[5];
> + break;
> + case 648000:
> + *pll_params = params[6];
> + break;
> + case 81:
> + *pll_params = params

Re: [Intel-gfx] [PATCH 03/17] drm/i915/icl: compute the combo PHY (DPLL) HDMI registers

[James Ausmus]

On Thu, Feb 22, 2018 at 12:55:05AM -0300, Paulo Zanoni wrote:
> HDMI mode DPLL programming on ICL is the same as CNL, so just reuse
> the CNL code.
> 
> v2:
>  - Properly detect HDMI crtcs.
>  - Rebase after changes to the cnl function (clock * 1000).
> 
> Signed-off-by: Paulo Zanoni <paulo.r.zan...@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dpll_mgr.c | 34 +++---
>  1 file changed, 31 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c 
> b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 8520a1b0279f..4d9265d14661 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -2203,6 +2203,7 @@ cnl_ddi_calculate_wrpll(int clock,
>   struct skl_wrpll_params *wrpll_params)
>  {
>   u32 afe_clock = clock * 5;
> + uint32_t ref_clock;
>   u32 dco_min = 7998000;
>   u32 dco_max = 1000;
>   u32 dco_mid = (dco_min + dco_max) / 2;
> @@ -2235,8 +2236,12 @@ cnl_ddi_calculate_wrpll(int clock,
>  
>   cnl_wrpll_get_multipliers(best_div, , , );
>  
> - cnl_wrpll_params_populate(wrpll_params, best_dco,
> -   dev_priv->cdclk.hw.ref, pdiv, qdiv, kdiv);
> + ref_clock = dev_priv->cdclk.hw.ref;
> + if (IS_ICELAKE(dev_priv) && ref_clock == 38400)

This could use a comment - something like

/* 
 * ICL BSpec states "If reference frequency is 38.4, use 19.2 because
 * the DPLL automatically divides that by 2."
 */


With that -

Reviewed-by: James Ausmus <james.aus...@intel.com>

> + ref_clock = 19200;
> +
> + cnl_wrpll_params_populate(wrpll_params, best_dco, ref_clock, pdiv, qdiv,
> +   kdiv);
>  
>   return true;
>  }
> @@ -2388,7 +2393,30 @@ static bool icl_calc_dpll_state(struct 
> intel_crtc_state *crtc_state,
>   struct intel_encoder *encoder, int clock,
>   struct intel_dpll_hw_state *pll_state)
>  {
> - /* TODO */
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + uint32_t cfgcr0, cfgcr1;
> + struct skl_wrpll_params pll_params = { 0 };
> + bool ret;
> +
> + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> + ret = cnl_ddi_calculate_wrpll(clock, dev_priv, _params);
> + else
> + ret = false; /* TODO */
> +
> + if (!ret)
> + return false;
> +
> + cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(pll_params.dco_fraction) |
> +  pll_params.dco_integer;
> +
> + cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(pll_params.qdiv_ratio) |
> +  DPLL_CFGCR1_QDIV_MODE(pll_params.qdiv_mode) |
> +  DPLL_CFGCR1_KDIV(pll_params.kdiv) |
> +  DPLL_CFGCR1_PDIV(pll_params.pdiv) |
> +  DPLL_CFGCR1_CENTRAL_FREQ_8400;
> +
> + pll_state->cfgcr0 = cfgcr0;
> + pll_state->cfgcr1 = cfgcr1;
>   return true;
>  }
>  
> -- 
> 2.14.3
> 
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Re: [Intel-gfx] [PATCH 02/17] drm/i915/icl: add basic support for the ICL clocks

[James Ausmus]

 struct intel_crtc_state *crtc_state,
> +struct drm_atomic_state *old_state)
> +{
> + struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> + struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> + struct drm_connector_state *conn_state;
> + struct drm_connector *conn;
> + int i;
> +
> + if (!IS_ICELAKE(dev_priv))
> + return;
> +
> + for_each_new_connector_in_state(old_state, conn, conn_state, i) {
> + struct intel_encoder *encoder =
> + to_intel_encoder(conn_state->best_encoder);
> + enum port port = encoder->port;
> + uint32_t val;
> +
> + if (conn_state->crtc != crtc)
> + continue;
> +
> + mutex_lock(_priv->dpll_lock);
> +
> + val = I915_READ(DPCLKA_CFGCR0_ICL);
> + WARN_ON((val & DPCLKA_CFGCR0_DDI_CLK_OFF(port)) == 0);
> +
> + if (port == PORT_A || port == PORT_B) {
> + val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
> + val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->id, port);
> + I915_WRITE(DPCLKA_CFGCR0_ICL, val);
> + POSTING_READ(DPCLKA_CFGCR0_ICL);
> + }
> +
> + val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
> + I915_WRITE(DPCLKA_CFGCR0_ICL, val);
> +
> + mutex_unlock(_priv->dpll_lock);
> + }
> +}
> +
> +void icl_unmap_plls_to_ports(struct drm_crtc *crtc,
> +  struct intel_crtc_state *crtc_state,
> +  struct drm_atomic_state *old_state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> + struct drm_connector_state *conn_state;
> + struct drm_connector *conn;
> + int i;
> +
> + if (!IS_ICELAKE(dev_priv))
> + return;
> +
> + for_each_new_connector_in_state(old_state, conn, conn_state, i) {
> + struct intel_encoder *encoder =
> + to_intel_encoder(conn_state->best_encoder);
> + enum port port = encoder->port;
> +
> + if (conn_state->crtc != crtc)
> + continue;
> +
> + mutex_lock(_priv->dpll_lock);
> + I915_WRITE(DPCLKA_CFGCR0_ICL,
> +I915_READ(DPCLKA_CFGCR0_ICL) |
> +DPCLKA_CFGCR0_DDI_CLK_OFF(port));
> + mutex_unlock(_priv->dpll_lock);
> + }
> +}
> +
>  static void intel_ddi_clk_select(struct intel_encoder *encoder,
>const struct intel_shared_dpll *pll)
>  {
> @@ -2126,7 +2212,11 @@ static void intel_ddi_clk_select(struct intel_encoder 
> *encoder,
>  
>   mutex_lock(_priv->dpll_lock);
>  
> - if (IS_CANNONLAKE(dev_priv)) {
> + if (IS_ICELAKE(dev_priv)) {
> + if (port >= PORT_C)
> + I915_WRITE(DDI_CLK_SEL(port),
> +icl_pll_to_ddi_pll_sel(encoder, pll));
> + } else if (IS_CANNONLAKE(dev_priv)) {
>   /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
>   val = I915_READ(DPCLKA_CFGCR0);
>   val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
> @@ -2164,14 +2254,18 @@ static void intel_ddi_clk_disable(struct 
> intel_encoder *encoder)
>   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>   enum port port = encoder->port;
>  
> - if (IS_CANNONLAKE(dev_priv))
> + if (IS_ICELAKE(dev_priv)) {
> + if (port >= PORT_C)
> + I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
> + } else if (IS_CANNONLAKE(dev_priv)) {
>   I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
>  DPCLKA_CFGCR0_DDI_CLK_OFF(port));
> - else if (IS_GEN9_BC(dev_priv))
> + } else if (IS_GEN9_BC(dev_priv)) {
>   I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
>  DPLL_CTRL2_DDI_CLK_OFF(port));
> - else if (INTEL_GEN(dev_priv) < 9)
> + } else if (INTEL_GEN(dev_priv) < 9) {
>   I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
> + }
>  }
>  
>  static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index 5d46771d58f6..bc4131a36c10 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5472,6 +5472,8 @@ static void haswell_crtc_enable(struct intel_crtc_state 
> *pipe_config,
>   if (inte

Re: [Intel-gfx] [PATCH 01/17] drm/i915/icl: add definitions for the ICL PLL registers

[James Ausmus]

On Thu, Feb 22, 2018 at 12:55:03AM -0300, Paulo Zanoni wrote:
> There's a lot of code for the PLL enabling, so let's first only
> introduce the register definitions in order to make patch reviewing a
> little easier.
> 
> v2: Coding style (Jani).
> v3: Preparation for upstreaming.
> 
> Signed-off-by: Paulo Zanoni 
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 149 
> 
>  1 file changed, 149 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1412abcb27d4..f62335c4a748 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8783,6 +8783,12 @@ enum skl_power_gate {
>  #define  PORT_CLK_SEL_NONE   (7<<29)
>  #define  PORT_CLK_SEL_MASK   (7<<29)
>  
> +/* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */
> +#define DDI_CLK_SEL(port)PORT_CLK_SEL(port)
> +#define  DDI_CLK_SEL_NONE(0x0 << 28)
> +#define  DDI_CLK_SEL_MG  (0x8 << 28)
> +#define  DDI_CLK_SEL_MASK(0xF << 28)
> +
>  /* Transcoder clock selection */
>  #define _TRANS_CLK_SEL_A 0x46140
>  #define _TRANS_CLK_SEL_B 0x46144
> @@ -8913,6 +8919,7 @@ enum skl_power_gate {
>   * CNL Clocks
>   */
>  #define DPCLKA_CFGCR0_MMIO(0x6C200)
> +#define DPCLKA_CFGCR0_ICL_MMIO(0x164280)
>  #define  DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) ==  PORT_F ? 23 : 
> \
> (port)+10))
>  #define  DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)   ((port) == PORT_F ? 21 
> : \
> @@ -8929,10 +8936,141 @@ enum skl_power_gate {
>  #define  PLL_POWER_STATE (1 << 26)
>  #define CNL_DPLL_ENABLE(pll) _MMIO_PLL(pll, DPLL0_ENABLE, DPLL1_ENABLE)
>  
> +#define _MG_PLL1_ENABLE  0x46030
> +#define _MG_PLL2_ENABLE  0x46034
> +#define _MG_PLL3_ENABLE  0x46038
> +#define _MG_PLL4_ENABLE  0x4603C
> +/* Bits are the same as DPLL0_ENABLE */
> +#define MG_PLL_ENABLE(port)  _MMIO_PORT((port) - PORT_C, _MG_PLL1_ENABLE, \
> +_MG_PLL2_ENABLE)
> +
> +#define _MG_REFCLKIN_CTL_PORT1   0x16892C
> +#define _MG_REFCLKIN_CTL_PORT2   0x16992C
> +#define _MG_REFCLKIN_CTL_PORT3   0x16A92C
> +#define _MG_REFCLKIN_CTL_PORT4   0x16B92C
> +#define   MG_REFCLKIN_CTL_OD_2_MUX(x)((x) << 8)
> +#define MG_REFCLKIN_CTL(port) _MMIO_PORT((port) - PORT_C, \
> +  _MG_REFCLKIN_CTL_PORT1, \
> +  _MG_REFCLKIN_CTL_PORT2)
> +
> +#define _MG_CLKTOP2_CORECLKCTL1_PORT10x1690D8
> +#define _MG_CLKTOP2_CORECLKCTL1_PORT20x16B0D8
> +#define _MG_CLKTOP2_CORECLKCTL1_PORT30x16D0D8
> +#define _MG_CLKTOP2_CORECLKCTL1_PORT40x16F0D8
> +#define   MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO(x)   ((x) << 16)
> +#define   MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(x)   ((x) << 8)
> +#define MG_CLKTOP2_CORECLKCTL1(port) _MMIO_PORT((port) - PORT_C, \
> + _MG_CLKTOP2_CORECLKCTL1_PORT1, \
> + _MG_CLKTOP2_CORECLKCTL1_PORT2)

BSpec 21736 says this register is unused and pending deletion, but in 20845 it 
also
says to program this register. Art, can you shed any light here?

Hmm, on further study, it looks like the MG_CLKTOP_CORECLKCTL1 group
(21340) names the port instances as MG_CLKTOP2_CORECLKCTL1_PORTx, so it
looks like *that* is the actual register group you want (and the
register bit definitions match as well), but, in that case, the
addresses are wrong - they need to be: 0x1688D8, 0x1698D8, 0x16A8D8, and
0x16B8D8, respectively.

> +
> +#define _MG_CLKTOP2_HSCLKCTL_PORT1   0x1688D4
> +#define _MG_CLKTOP2_HSCLKCTL_PORT2   0x1698D4
> +#define _MG_CLKTOP2_HSCLKCTL_PORT3   0x16A8D4
> +#define _MG_CLKTOP2_HSCLKCTL_PORT4   0x16B8D4
> +#define   MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(x)   ((x) << 16)
> +#define   MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(x) ((x) << 14)
> +#define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO(x) ((x) << 12)
> +#define   MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x) ((x) << 8)
> +#define MG_CLKTOP2_HSCLKCTL(port) _MMIO_PORT((port) - PORT_C, \
> +  _MG_CLKTOP2_HSCLKCTL_PORT1, \
> +  _MG_CLKTOP2_HSCLKCTL_PORT2)
> +
> +#define _MG_PLL_DIV0_PORT1   0x168A00
> +#define _MG_PLL_DIV0_PORT2   0x169A00
> +#define _MG_PLL_DIV0_PORT3   0x16AA00
> +#define _MG_PLL_DIV0_PORT4  

Re: [Intel-gfx] [PATCH] drm/i915/cnl: Sync PCI ID with Spec.

[James Ausmus]

On Wed, Feb 07, 2018 at 11:32:19PM -0800, Rodrigo Vivi wrote:
> Add one missing PCI ID and sort them in a way
> that gets easier to review and compare against spec's
> table.
> 
> When trying to sync libdrm and mesa id list with kernel
> and spec I noticed something was wrong and we were missing
> a pci id. So to make our lives easier when checking against
> spec let's simplify and sort like spec does.
> 
> BSpec: 13621
> 
> Cc: Lucas De Marchi <lucas.demar...@intel.com>
> Cc: James Ausmus <james.aus...@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.v...@intel.com>

Matches BSpec.

Reviewed-by: James Ausmus <james.aus...@intel.com>

> ---
>  include/drm/i915_pciids.h | 15 ---
>  1 file changed, 8 insertions(+), 7 deletions(-)
> 
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index 9e1fe6634424..0b2ba46fa00b 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -416,18 +416,19 @@
>  
>  /* CNL */
>  #define INTEL_CNL_IDS(info) \
> - INTEL_VGA_DEVICE(0x5A52, info), \
> - INTEL_VGA_DEVICE(0x5A5A, info), \
> - INTEL_VGA_DEVICE(0x5A42, info), \
> - INTEL_VGA_DEVICE(0x5A4A, info), \
>   INTEL_VGA_DEVICE(0x5A51, info), \
>   INTEL_VGA_DEVICE(0x5A59, info), \
>   INTEL_VGA_DEVICE(0x5A41, info), \
>   INTEL_VGA_DEVICE(0x5A49, info), \
> - INTEL_VGA_DEVICE(0x5A71, info), \
> - INTEL_VGA_DEVICE(0x5A79, info), \
> + INTEL_VGA_DEVICE(0x5A52, info), \
> + INTEL_VGA_DEVICE(0x5A5A, info), \
> + INTEL_VGA_DEVICE(0x5A42, info), \
> + INTEL_VGA_DEVICE(0x5A4A, info), \
> + INTEL_VGA_DEVICE(0x5A50, info), \
> + INTEL_VGA_DEVICE(0x5A40, info), \
>   INTEL_VGA_DEVICE(0x5A54, info), \
>   INTEL_VGA_DEVICE(0x5A5C, info), \
> - INTEL_VGA_DEVICE(0x5A44, info)
> + INTEL_VGA_DEVICE(0x5A44, info), \
> + INTEL_VGA_DEVICE(0x5A4C, info)
>  
>  #endif /* _I915_PCIIDS_H */
> -- 
> 2.13.6
> 
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Re: [Intel-gfx] [PATCH] drm/i915: Fix incorrect comment

[James Ausmus]

On Fri, Feb 09, 2018 at 03:07:55PM +0200, David Weinehall wrote:
> While the comment singles out Port A or B, the code says Port A or *D*.
> Looking at the history it seems that the comment was added after the code,
> so it seems likely that the code is correct, not the comment.
> 
> CC: Jani Nikula <jani.nik...@intel.com>
> CC: Rodrigo Vivi <rodrigo.v...@intel.com>
> Signed-off-by: David Weinehall <david.weineh...@linux.intel.com>

Matches my read of BSpec.

Reviewed-by: James Ausmus <james.aus...@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_dp.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index f10a14330e7c..21d526bd4df6 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -258,7 +258,7 @@ static int cnl_max_source_rate(struct intel_dp *intel_dp)
>   if (IS_CNL_WITH_PORT_F(dev_priv))
>   return 81;
>  
> - /* For other SKUs, max rate on ports A and B is 5.4G */
> + /* For other SKUs, max rate on ports A and D is 5.4G */
>   if (port == PORT_A || port == PORT_D)
>   return 54;
>  
> -- 
> 2.16.1
> 
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Re: [Intel-gfx] [PATCH 3/5] drm/i915: Call i915_pipe_update_start with uncore.lock held.

[James Ausmus]

On Fri, Feb 09, 2018 at 10:54:02AM +0100, Maarten Lankhorst wrote:
> This requires being able to read the vblank counter with the
> uncore.lock already held. This is also a preparation for
> being able to run the entire vblank update sequence with
> the uncore lock held.
> 
> Signed-off-by: Maarten Lankhorst 
> ---
>  drivers/gpu/drm/i915/i915_irq.c | 66 
> ++---
>  drivers/gpu/drm/i915/i915_trace.h   |  5 ++-
>  drivers/gpu/drm/i915/intel_drv.h|  1 +
>  drivers/gpu/drm/i915/intel_sprite.c |  3 +-
>  4 files changed, 60 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index eda9543a0199..6c491e63e07c 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -736,13 +736,12 @@ static void i915_enable_asle_pipestat(struct 
> drm_i915_private *dev_priv)
>  /* Called from drm generic code, passed a 'crtc', which
>   * we use as a pipe index
>   */
> -static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
> +static u32 __i915_get_vblank_counter(struct intel_crtc *crtc)
>  {
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>   i915_reg_t high_frame, low_frame;
>   u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
> - const struct drm_display_mode *mode = >vblank[pipe].hwmode;
> - unsigned long irqflags;
> + const struct drm_display_mode *mode = 
> >base.dev->vblank[crtc->pipe].hwmode;
>  
>   htotal = mode->crtc_htotal;
>   hsync_start = mode->crtc_hsync_start;
> @@ -756,10 +755,8 @@ static u32 i915_get_vblank_counter(struct drm_device 
> *dev, unsigned int pipe)
>   /* Start of vblank event occurs at start of hsync */
>   vbl_start -= htotal - hsync_start;
>  
> - high_frame = PIPEFRAME(pipe);
> - low_frame = PIPEFRAMEPIXEL(pipe);
> -
> - spin_lock_irqsave(_priv->uncore.lock, irqflags);
> + high_frame = PIPEFRAME(crtc->pipe);
> + low_frame = PIPEFRAMEPIXEL(crtc->pipe);
>  
>   /*
>* High & low register fields aren't synchronized, so make sure
> @@ -772,8 +769,6 @@ static u32 i915_get_vblank_counter(struct drm_device 
> *dev, unsigned int pipe)
>   high2 = I915_READ_FW(high_frame) & PIPE_FRAME_HIGH_MASK;
>   } while (high1 != high2);
>  
> - spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
> -
>   high1 >>= PIPE_FRAME_HIGH_SHIFT;
>   pixel = low & PIPE_PIXEL_MASK;
>   low >>= PIPE_FRAME_LOW_SHIFT;
> @@ -786,11 +781,60 @@ static u32 i915_get_vblank_counter(struct drm_device 
> *dev, unsigned int pipe)
>   return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xff;
>  }
>  
> +static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
> +{
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + unsigned long irqflags;
> + u32 ret;
> +
> + spin_lock_irqsave(_priv->uncore.lock, irqflags);
> + ret = i915_get_vblank_counter(dev, pipe);

Shouldn't this be __i915_get_vblank_counter ?

> + spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
> +
> + return ret;
> +}
> +
> +static u32 __g4x_get_vblank_counter(struct intel_crtc *crtc)
> +{
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +
> + return I915_READ_FW(PIPE_FRMCOUNT_G4X(crtc->pipe));
> +}
> +
>  static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
>  {
>   struct drm_i915_private *dev_priv = to_i915(dev);
> + struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> + unsigned long irqflags;
> + u32 ret;
> +
> + spin_lock_irqsave(_priv->uncore.lock, irqflags);
> + ret = __g4x_get_vblank_counter(crtc);
> + spin_unlock_irqrestore(_priv->uncore.lock, irqflags);
> +
> + return ret;
> +}
> +
> +u32 __intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
> +{
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +
> + if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
> + return __g4x_get_vblank_counter(crtc);
> + else if (IS_GEN2(dev_priv))
> + return 0;
> + else
> + return __i915_get_vblank_counter(crtc);
> +}
> +
> +u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
> +{
> + struct drm_device *dev = crtc->base.dev;
> +
> + if (!dev->max_vblank_count)
> + return drm_crtc_accurate_vblank_count(>base);
>  
> - return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
> + return dev->driver->get_vblank_counter(dev, crtc->pipe);
>  }
>  
>  /*
> diff --git a/drivers/gpu/drm/i915/i915_trace.h 
> b/drivers/gpu/drm/i915/i915_trace.h
> index e1169c02eb2b..d4a5776282ff 100644
> --- a/drivers/gpu/drm/i915/i915_trace.h
> +++ b/drivers/gpu/drm/i915/i915_trace.h
> @@ -280,9 +280,8 @@ TRACE_EVENT(i915_pipe_update_start,
>  
>   TP_fast_assign(
>  

Re: [Intel-gfx] [PATCH 2/6] drm/i915/icl: add the main CDCLK functions

[James Ausmus]

On Tue, Feb 06, 2018 at 05:33:46PM -0200, Paulo Zanoni wrote:
> This commit adds the basic CDCLK functions, but it's still missing
> pieces of the display initialization sequence.
> 
> v2:
>  - Implement the voltage levels.
>  - Rebase.
> v3:
>  - Adjust to the new "bypass" clock (Imre).
>  - Call intel_dump_cdclk_state() too.
>  - Rename a variable to avoid confusion.
>  - Simplify the DVFS part.
> v4:
>  - Remove wrong bit definition (James).
>  - Also drive-by fix the coding style for the register definition we
>touched.
> v5:
>  - Comment style (checkpatch).
> 
> Cc: James Ausmus <james.aus...@intel.com>
> Cc: Imre Deak <imre.d...@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zan...@intel.com>

Reviewed-by: James Ausmus <james.aus...@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h|  35 +++---
>  drivers/gpu/drm/i915/intel_cdclk.c | 237 
> -
>  drivers/gpu/drm/i915/intel_drv.h   |   2 +
>  3 files changed, 257 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 58057affa133..023ecb844328 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7182,8 +7182,12 @@ enum {
>  #define SKL_DFSM_PIPE_B_DISABLE  (1 << 21)
>  #define SKL_DFSM_PIPE_C_DISABLE  (1 << 28)
>  
> -#define SKL_DSSM _MMIO(0x51004)
> -#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz  (1 << 31)
> +#define SKL_DSSM _MMIO(0x51004)
> +#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz  (1 << 31)
> +#define ICL_DSSM_CDCLK_PLL_REFCLK_MASK   (7 << 29)
> +#define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz  (0 << 29)
> +#define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz(1 << 29)
> +#define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz(2 << 29)
>  
>  #define GEN7_FF_SLICE_CS_CHICKEN1_MMIO(0x20e0)
>  #define   GEN9_FFSC_PERCTX_PREEMPT_CTRL  (1<<14)
> @@ -8816,20 +8820,21 @@ enum skl_power_gate {
>  
>  /* CDCLK_CTL */
>  #define CDCLK_CTL_MMIO(0x46000)
> -#define  CDCLK_FREQ_SEL_MASK (3<<26)
> -#define  CDCLK_FREQ_450_432  (0<<26)
> -#define  CDCLK_FREQ_540  (1<<26)
> -#define  CDCLK_FREQ_337_308  (2<<26)
> -#define  CDCLK_FREQ_675_617  (3<<26)
> -#define  BXT_CDCLK_CD2X_DIV_SEL_MASK (3<<22)
> -#define  BXT_CDCLK_CD2X_DIV_SEL_1(0<<22)
> -#define  BXT_CDCLK_CD2X_DIV_SEL_1_5  (1<<22)
> -#define  BXT_CDCLK_CD2X_DIV_SEL_2(2<<22)
> -#define  BXT_CDCLK_CD2X_DIV_SEL_4(3<<22)
> -#define  BXT_CDCLK_CD2X_PIPE(pipe)   ((pipe)<<20)
> -#define  CDCLK_DIVMUX_CD_OVERRIDE(1<<19)
> +#define  CDCLK_FREQ_SEL_MASK (3 << 26)
> +#define  CDCLK_FREQ_450_432  (0 << 26)
> +#define  CDCLK_FREQ_540  (1 << 26)
> +#define  CDCLK_FREQ_337_308  (2 << 26)
> +#define  CDCLK_FREQ_675_617  (3 << 26)
> +#define  BXT_CDCLK_CD2X_DIV_SEL_MASK (3 << 22)
> +#define  BXT_CDCLK_CD2X_DIV_SEL_1(0 << 22)
> +#define  BXT_CDCLK_CD2X_DIV_SEL_1_5  (1 << 22)
> +#define  BXT_CDCLK_CD2X_DIV_SEL_2(2 << 22)
> +#define  BXT_CDCLK_CD2X_DIV_SEL_4(3 << 22)
> +#define  BXT_CDCLK_CD2X_PIPE(pipe)   ((pipe) << 20)
> +#define  CDCLK_DIVMUX_CD_OVERRIDE(1 << 19)
>  #define  BXT_CDCLK_CD2X_PIPE_NONEBXT_CDCLK_CD2X_PIPE(3)
> -#define  BXT_CDCLK_SSA_PRECHARGE_ENABLE  (1<<16)
> +#define  ICL_CDCLK_CD2X_PIPE_NONE(7 << 19)
> +#define  BXT_CDCLK_SSA_PRECHARGE_ENABLE  (1 << 16)
>  #define  CDCLK_FREQ_DECIMAL_MASK (0x7ff)
>  
>  /* LCPLL_CTL */
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c 
> b/drivers/gpu/drm/i915/intel_cdclk.c
> index ee788d5be5e3..0256198c7519 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -1778,6 +1778,199 @@ static void cnl_sanitize_cdclk(struct 
> drm_i915_private *dev_priv)
>   dev_priv->cdclk.hw.vco = -1;
>  }
>  
> +static int icl_calc_cdclk(int min_cdclk, unsigned int ref)
> +{
> + int ranges_24[] = { 312000, 552000, 648000 };
> + int ranges_19_38[] = { 307200, 556800, 652800 };
> + int *ranges;
> +
> + switch (ref) {
> + default:
> + MISSING_CASE(ref);
> + case 24000:
> + ranges = ranges_24;
> + break;
> + case 19200:
> + case 38400:
> + ranges = ranges_19_38;
> + break;
&g

Re: [Intel-gfx] [PATCH 01/17] drm/i915/icl: add the main CDCLK functions

[James Ausmus]

On Fri, Feb 02, 2018 at 05:57:02PM -0200, Paulo Zanoni wrote:
> This commit adds the basic CDCLK functions, but it's still missing
> pieces of the display initialization sequence.
> 
> v2:
>  - Implement the voltage levels.
>  - Rebase.
> v3:
>  - Adjust to the new "bypass" clock (Imre).
>  - Call intel_dump_cdclk_state() too.
>  - Rename a variable to avoid confusion.
>  - Simplify the DVFS part.
> 
> Signed-off-by: Paulo Zanoni 
> ---
>  drivers/gpu/drm/i915/i915_reg.h|  10 +-
>  drivers/gpu/drm/i915/intel_cdclk.c | 235 
> -
>  drivers/gpu/drm/i915/intel_drv.h   |   2 +
>  3 files changed, 243 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f6e1677e8211..856e88c6ee97 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7182,8 +7182,12 @@ enum {
>  #define SKL_DFSM_PIPE_B_DISABLE  (1 << 21)
>  #define SKL_DFSM_PIPE_C_DISABLE  (1 << 28)
>  
> -#define SKL_DSSM _MMIO(0x51004)
> -#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz  (1 << 31)
> +#define SKL_DSSM _MMIO(0x51004)
> +#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz  (1 << 31)
> +#define ICL_DSSM_CDCLK_PLL_REFCLK_MASK   (7 << 29)
> +#define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz  (0 << 29)
> +#define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz(1 << 29)
> +#define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz(2 << 29)
>  
>  #define GEN7_FF_SLICE_CS_CHICKEN1_MMIO(0x20e0)
>  #define   GEN9_FFSC_PERCTX_PREEMPT_CTRL  (1<<14)
> @@ -8831,6 +8835,8 @@ enum skl_power_gate {
>  #define  BXT_CDCLK_CD2X_PIPE_NONEBXT_CDCLK_CD2X_PIPE(3)
>  #define  BXT_CDCLK_SSA_PRECHARGE_ENABLE  (1<<16)
>  #define  CDCLK_FREQ_DECIMAL_MASK (0x7ff)
> +#define  ICL_CDCLK_CD2X_PIPE(pipe)   ((pipe) << 19)

This is still wrong :)

> +#define  ICL_CDCLK_CD2X_PIPE_NONEICL_CDCLK_CD2X_PIPE(7)
>  
>  /* LCPLL_CTL */
>  #define LCPLL1_CTL   _MMIO(0x46010)
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c 
> b/drivers/gpu/drm/i915/intel_cdclk.c
> index ee788d5be5e3..52a15d0eaae9 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -1778,6 +1778,197 @@ static void cnl_sanitize_cdclk(struct 
> drm_i915_private *dev_priv)
>   dev_priv->cdclk.hw.vco = -1;
>  }
>  
> +static int icl_calc_cdclk(int min_cdclk, unsigned int ref)
> +{
> + int ranges_24[] = { 312000, 552000, 648000 };
> + int ranges_19_38[] = { 307200, 556800, 652800 };
> + int *ranges;
> +
> + switch (ref) {
> + default:
> + MISSING_CASE(ref);
> + case 24000:
> + ranges = ranges_24;
> + break;
> + case 19200:
> + case 38400:
> + ranges = ranges_19_38;
> + break;
> + }
> +
> + if (min_cdclk > ranges[1])
> + return ranges[2];
> + else if (min_cdclk > ranges[0])
> + return ranges[1];
> + else
> + return ranges[0];
> +}
> +
> +static int icl_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int 
> cdclk)
> +{
> + int ratio;
> +
> + if (cdclk == dev_priv->cdclk.hw.bypass)
> + return 0;
> +
> + switch (cdclk) {
> + default:
> + MISSING_CASE(cdclk);
> + case 307200:
> + case 556800:
> + case 652800:
> + WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
> + dev_priv->cdclk.hw.ref != 38400);
> + break;
> + case 312000:
> + case 552000:
> + case 648000:
> + WARN_ON(dev_priv->cdclk.hw.ref != 24000);
> + }
> +
> + ratio = cdclk / (dev_priv->cdclk.hw.ref / 2);
> +
> + return dev_priv->cdclk.hw.ref * ratio;
> +}
> +
> +static void icl_set_cdclk(struct drm_i915_private *dev_priv,
> +   const struct intel_cdclk_state *cdclk_state)
> +{
> + unsigned int cdclk = cdclk_state->cdclk;
> + unsigned int vco = cdclk_state->vco;
> + int ret;
> +
> + mutex_lock(_priv->pcu_lock);
> + ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
> + SKL_CDCLK_PREPARE_FOR_CHANGE,
> + SKL_CDCLK_READY_FOR_CHANGE,
> + SKL_CDCLK_READY_FOR_CHANGE, 3);
> + mutex_unlock(_priv->pcu_lock);
> + if (ret) {
> + DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
> +   ret);
> + return;
> + }
> +
> + if (dev_priv->cdclk.hw.vco != 0 &&
> + dev_priv->cdclk.hw.vco != vco)
> + cnl_cdclk_pll_disable(dev_priv);
> +
> + if (dev_priv->cdclk.hw.vco != vco)
> + cnl_cdclk_pll_enable(dev_priv, vco);
> +
> + I915_WRITE(CDCLK_CTL, ICL_CDCLK_CD2X_PIPE_NONE |
> +   skl_cdclk_decimal(cdclk));
> +
> + mutex_lock(_priv->pcu_lock);
> + /* 

Re: [Intel-gfx] [PATCH 02/17] drm/i915/icl: add ICL support to cnl_set_procmon_ref_values

[James Ausmus]

On Fri, Feb 02, 2018 at 02:23:04PM -0200, Paulo Zanoni wrote:
> On ICL we have two sets of registers: one for port A and another for
> port B. The set of port A registers is the same as the CNL registers.
> 
> Since the procmon table on ICL is the same we want to reuse the CNL
> function. To do that we add a port argument and make CNL always call
> the function passing port A. This way, we'll be able to easily reuse
> the function on ICL when we add icl_display_core_init().
> 
> v2: Don't use _PICK() when you can use a ternary operator.
> v3: Don't use a ternary operation when you can use _MMIO_PORT (Ville).
> Add an extra comment about why we're passing PORT_A (James).
> 
> Signed-off-by: Paulo Zanoni <paulo.r.zan...@intel.com>

Reviewed-by: James Ausmus <james.aus...@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 22 ++
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 22 +++---
>  2 files changed, 37 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 65ba10ad1fe5..f6e1677e8211 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2104,6 +2104,28 @@ enum i915_power_well_id {
>  #define CNL_PORT_COMP_DW9_MMIO(0x162124)
>  #define CNL_PORT_COMP_DW10   _MMIO(0x162128)
>  
> +#define _ICL_PORT_COMP_DW0_A 0x162100
> +#define _ICL_PORT_COMP_DW0_B 0x6C100
> +#define ICL_PORT_COMP_DW0(port)  _MMIO_PORT(port, 
> _ICL_PORT_COMP_DW0_A, \
> +  _ICL_PORT_COMP_DW0_B)
> +#define _ICL_PORT_COMP_DW1_A 0x162104
> +#define _ICL_PORT_COMP_DW1_B 0x6C104
> +#define ICL_PORT_COMP_DW1(port)  _MMIO_PORT(port, 
> _ICL_PORT_COMP_DW1_A, \
> +  _ICL_PORT_COMP_DW1_B)
> +#define _ICL_PORT_COMP_DW3_A 0x16210C
> +#define _ICL_PORT_COMP_DW3_B 0x6C10C
> +#define ICL_PORT_COMP_DW3(port)  _MMIO_PORT(port, 
> _ICL_PORT_COMP_DW3_A, \
> +  _ICL_PORT_COMP_DW3_B)
> +#define _ICL_PORT_COMP_DW9_A 0x162124
> +#define _ICL_PORT_COMP_DW9_B 0x6C124
> +#define ICL_PORT_COMP_DW9(port)  _MMIO_PORT(port, 
> _ICL_PORT_COMP_DW9_A, \
> +  _ICL_PORT_COMP_DW9_B)
> +#define _ICL_PORT_COMP_DW10_A0x162128
> +#define _ICL_PORT_COMP_DW10_B0x6C128
> +#define ICL_PORT_COMP_DW10(port) _MMIO_PORT(port, \
> +_ICL_PORT_COMP_DW10_A, \
> +_ICL_PORT_COMP_DW10_B)
> +
>  /* BXT PHY Ref registers */
>  #define _PORT_REF_DW3_A  0x16218C
>  #define _PORT_REF_DW3_BC 0x6C18C
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 70e659772a7a..b4ef7875f055 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -2794,12 +2794,19 @@ static const struct cnl_procmon {
>   { .dw1 = 0x0044, .dw9 = 0x9A00AB25, .dw10 = 0x8AE38FF1, },
>  };
>  
> -static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv)
> +/*
> + * CNL has just one set of registers, while ICL has two sets: one for port A 
> and
> + * the other for port B. The CNL registers are equivalent to the ICL port A
> + * registers, that's why we call the ICL macros even though the function has 
> CNL
> + * on its name.
> + */
> +static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv,
> +enum port port)
>  {
>   const struct cnl_procmon *procmon;
>   u32 val;
>  
> - val = I915_READ(CNL_PORT_COMP_DW3);
> + val = I915_READ(ICL_PORT_COMP_DW3(port));
>   switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) {
>   default:
>   MISSING_CASE(val);
> @@ -2820,13 +2827,13 @@ static void cnl_set_procmon_ref_values(struct 
> drm_i915_private *dev_priv)
>   break;
>   }
>  
> - val = I915_READ(CNL_PORT_COMP_DW1);
> + val = I915_READ(ICL_PORT_COMP_DW1(port));
>   val &= ~((0xff << 16) | 0xff);
>   val |= procmon->dw1;
> - I915_WRITE(CNL_PORT_COMP_DW1, val);
> + I915_WRITE(ICL_PORT_COMP_DW1(port), val);
>  
> - I915_WRITE(CNL_PORT_COMP_DW9, procmon->dw9);
> - I915_WRITE(CNL_PORT_COMP_DW10, procmon->dw10);
> + I915_WRITE(ICL_PORT_COMP_DW9(port), procmon->dw9);
>

Re: [Intel-gfx] [PATCH 06/17] drm/i915/icl: Do not fix dbuf block size to 512

[James Ausmus]

On Mon, Jan 29, 2018 at 09:07:30PM -0200, Paulo Zanoni wrote:
> From: Mahesh Kumar <mahesh1.ku...@intel.com>
> 
> GEN9/10 had fixed DBuf block size of 512. Dbuf block size is not a
> fixed number anymore in GEN11, it varies according to bits per pixel
> and tiling. If 8bpp & Yf-tile surface, block size = 256 else block
> size = 512
> 
> This patch addresses the same.
> 
> v2 (from Paulo):
>   - Make it compile.
>   - Fix a few coding style issues.
> v3:
>   - Rebase on top of upstream patches
> v4 (from Paulo):
>   - Bikeshed if statements (James).
> 
> Reviewed-by: Paulo Zanoni <paulo.r.zan...@intel.com>
> Signed-off-by: Mahesh Kumar <mahesh1.ku...@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zan...@intel.com>

Reviewed-by: James Ausmus <james.aus...@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h |  1 +
>  drivers/gpu/drm/i915/intel_pm.c | 24 +---
>  2 files changed, 18 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 454d8f937fae..d93e784c3f14 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1460,6 +1460,7 @@ struct skl_wm_params {
>   uint_fixed_16_16_t plane_blocks_per_line;
>   uint_fixed_16_16_t y_tile_minimum;
>   uint32_t linetime_us;
> + uint32_t dbuf_block_size;
>  };
>  
>  /*
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 11aac65d1543..985642cf1c9a 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4312,7 +4312,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
>  */
>  static uint_fixed_16_16_t
>  skl_wm_method1(const struct drm_i915_private *dev_priv, uint32_t pixel_rate,
> -uint8_t cpp, uint32_t latency)
> +uint8_t cpp, uint32_t latency, uint32_t dbuf_block_size)
>  {
>   uint32_t wm_intermediate_val;
>   uint_fixed_16_16_t ret;
> @@ -4321,7 +4321,7 @@ skl_wm_method1(const struct drm_i915_private *dev_priv, 
> uint32_t pixel_rate,
>   return FP_16_16_MAX;
>  
>   wm_intermediate_val = latency * pixel_rate * cpp;
> - ret = div_fixed16(wm_intermediate_val, 1000 * 512);
> + ret = div_fixed16(wm_intermediate_val, 1000 * dbuf_block_size);
>  
>   if (INTEL_GEN(dev_priv) >= 10)
>   ret = add_fixed16_u32(ret, 1);
> @@ -4431,6 +4431,12 @@ skl_compute_plane_wm_params(const struct 
> drm_i915_private *dev_priv,
>   wp->plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate,
>intel_pstate);
>  
> + if (INTEL_GEN(dev_priv) >= 11 &&
> + fb->modifier == I915_FORMAT_MOD_Yf_TILED && wp->cpp == 8)
> + wp->dbuf_block_size = 256;
> + else
> + wp->dbuf_block_size = 512;
> +
>   if (drm_rotation_90_or_270(pstate->rotation)) {
>  
>   switch (wp->cpp) {
> @@ -4457,7 +4463,8 @@ skl_compute_plane_wm_params(const struct 
> drm_i915_private *dev_priv,
>   wp->plane_bytes_per_line = wp->width * wp->cpp;
>   if (wp->y_tiled) {
>   interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line *
> -wp->y_min_scanlines, 512);
> +wp->y_min_scanlines,
> +wp->dbuf_block_size);
>  
>   if (INTEL_GEN(dev_priv) >= 10)
>   interm_pbpl++;
> @@ -4465,10 +4472,12 @@ skl_compute_plane_wm_params(const struct 
> drm_i915_private *dev_priv,
>   wp->plane_blocks_per_line = div_fixed16(interm_pbpl,
>   wp->y_min_scanlines);
>   } else if (wp->x_tiled && IS_GEN9(dev_priv)) {
> - interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line, 512);
> + interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line,
> +wp->dbuf_block_size);
>   wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
>   } else {
> - interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line, 512) + 1;
> + interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line,
> +wp->dbuf_block_size) + 1;
>   wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
>   }
>  
> @@ -4515,7 +4524,7 @@ static int skl_compute_plane_wm(const struct 
> drm_i915_private *dev_priv,
>   latency += 15;
> 

Re: [Intel-gfx] [PATCH 07/17] drm/i915/icl: Fail flip if ddb allocated are less than min display buffer needed

[James Ausmus]

On Tue, Jan 23, 2018 at 05:05:26PM -0200, Paulo Zanoni wrote:
> From: Mahesh Kumar <mahesh1.ku...@intel.com>
> 
> ICL require DDB allocation of plane to be more than "minimum display
> buffer needed" for each level in order to enable WM level.
> 
> This patch implements and consider the same while allocating DDB
> and enabling WM.
> 
> Changes Since V1:
>  - rebase
> Changes Since V2:
>  - Remove extra parentheses
>  - Use FP16.16 only when absolutely necessary (Paulo)
> Changes Since V3:
>  - Rebase
> Changes since v4 (from Paulo)
>  - Coding style issue.
> 
> Reviewed-by: Paulo Zanoni <paulo.r.zan...@intel.com>
> Signed-off-by: Mahesh Kumar <mahesh1.ku...@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zan...@intel.com>

Reviewed-by: James Ausmus <james.aus...@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 30 +-
>  1 file changed, 29 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 44d952a3d9a6..c6d31a5075ad 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4510,6 +4510,7 @@ static int skl_compute_plane_wm(const struct 
> drm_i915_private *dev_priv,
>   struct intel_atomic_state *state =
>   to_intel_atomic_state(cstate->base.state);
>   bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
> + uint32_t min_disp_buf_needed;
>  
>   if (latency == 0 ||
>   !intel_wm_plane_visible(cstate, intel_pstate)) {
> @@ -4568,7 +4569,34 @@ static int skl_compute_plane_wm(const struct 
> drm_i915_private *dev_priv,
>   }
>   }
>  
> - if (res_blocks >= ddb_allocation || res_lines > 31) {
> + if (INTEL_GEN(dev_priv) >= 11) {
> + if (wp->y_tiled) {
> + uint32_t extra_lines;
> + uint_fixed_16_16_t fp_min_disp_buf_needed;
> +
> + if (res_lines % wp->y_min_scanlines == 0)
> + extra_lines = wp->y_min_scanlines;
> + else
> + extra_lines = wp->y_min_scanlines * 2 -
> +   res_lines % wp->y_min_scanlines;
> +
> + fp_min_disp_buf_needed = mul_u32_fixed16(res_lines +
> + extra_lines,
> + wp->plane_blocks_per_line);
> + min_disp_buf_needed = fixed16_to_u32_round_up(
> + fp_min_disp_buf_needed);
> + } else {
> + min_disp_buf_needed = DIV_ROUND_UP(res_blocks * 11, 10);
> + }
> + } else {
> + /*
> +  * To enable a WM level ddb_allocation should be
> +  * greater than result blocks for GEN-9/10.
> +  */
> + min_disp_buf_needed = res_blocks + 1;
> + }
> +
> + if (min_disp_buf_needed > ddb_allocation || res_lines > 31) {
>   *enabled = false;
>  
>   /*
> -- 
> 2.14.3
> 
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Re: [Intel-gfx] [PATCH 03/17] drm/i915/icl: implement the display init/uninit sequences

[James Ausmus]

On Tue, Jan 23, 2018 at 05:05:22PM -0200, Paulo Zanoni wrote:
> This code is similar enough to the CNL code that I considered just
> adding ICL support to the CNL function, but I think it's still
> different enough, and having a function specific to ICL allows us to
> more easily adapt code in case the spec changes more later.
> 
> We're still missing the power wells and the mbus code, so leave those
> pieces with a FIXME comment while they're not here yet.
> 
> v2: Don't use _PICK, don't WARN_ON(1), don't forget the chicken bits.
> 
> Signed-off-by: Paulo Zanoni <paulo.r.zan...@intel.com>

Reviewed-by: James Ausmus <james.aus...@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 16 ++-
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 82 
> -
>  2 files changed, 94 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index ebf6261d30fd..979bc06a59f4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1904,6 +1904,11 @@ enum i915_power_well_id {
>  #define   CL_POWER_DOWN_ENABLE   (1 << 4)
>  #define   SUS_CLOCK_CONFIG   (3 << 0)
>  
> +#define _ICL_PORT_CL_DW5_A   0x162014
> +#define _ICL_PORT_CL_DW5_B   0x6C014
> +#define ICL_PORT_CL_DW5(port)_MMIO((port == PORT_A) ? \
> +   _ICL_PORT_CL_DW5_A : _ICL_PORT_CL_DW5_B)
> +
>  #define _PORT_CL1CM_DW9_A0x162024
>  #define _PORT_CL1CM_DW9_BC   0x6C024
>  #define   IREF0RC_OFFSET_SHIFT   8
> @@ -7126,8 +7131,9 @@ enum {
>  #define  RESET_PCH_HANDSHAKE_ENABLE  (1<<4)
>  
>  #define GEN8_CHICKEN_DCPR_1  _MMIO(0x46430)
> -#define   SKL_SELECT_ALTERNATE_DC_EXIT   (1<<30)
> -#define   MASK_WAKEMEM   (1<<13)
> +#define   SKL_SELECT_ALTERNATE_DC_EXIT   (1 << 30)
> +#define   MASK_WAKEMEM   (1 << 13)
> +#define   CNL_DDI_CLOCK_REG_ACCESS_ON(1 << 7)
>  
>  #define SKL_DFSM _MMIO(0x51000)
>  #define SKL_DFSM_CDCLK_LIMIT_MASK(3 << 23)
> @@ -9696,4 +9702,10 @@ enum skl_power_gate {
>  #define  MMCD_PCLA   (1 << 31)
>  #define  MMCD_HOTSPOT_EN (1 << 27)
>  
> +#define _ICL_PHY_MISC_A  0x64C00
> +#define _ICL_PHY_MISC_B  0x64C04
> +#define ICL_PHY_MISC(port)   _MMIO((port == PORT_A) ? \
> +   _ICL_PHY_MISC_A : _ICL_PHY_MISC_B)
> +#define  ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN(1 << 23)
> +
>  #endif /* _I915_REG_H_ */
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 73dd525d241a..2556db16c76a 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -2882,6 +2882,80 @@ static void cnl_display_core_uninit(struct 
> drm_i915_private *dev_priv)
>   I915_WRITE(CHICKEN_MISC_2, val);
>  }
>  
> +static void icl_display_core_init(struct drm_i915_private *dev_priv,
> +   bool resume)
> +{
> + enum port port;
> + u32 val;
> +
> + gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> +
> + /* 1. Enable PCH reset handshake. */
> + val = I915_READ(HSW_NDE_RSTWRN_OPT);
> + val |= RESET_PCH_HANDSHAKE_ENABLE;
> + I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
> +
> + for (port = PORT_A; port <= PORT_B; port++) {
> + /* 2. Enable DDI combo PHY comp. */
> + val = I915_READ(ICL_PHY_MISC(port));
> + val &= ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
> + I915_WRITE(ICL_PHY_MISC(port), val);
> +
> + cnl_set_procmon_ref_values(dev_priv, port);
> +
> + val = I915_READ(ICL_PORT_COMP_DW0(port));
> + val |= COMP_INIT;
> + I915_WRITE(ICL_PORT_COMP_DW0(port), val);
> +
> + /* 3. Set power down enable. */
> + val = I915_READ(ICL_PORT_CL_DW5(port));
> + val |= CL_POWER_DOWN_ENABLE;
> + I915_WRITE(ICL_PORT_CL_DW5(port), val);
> + }
> +
> + /* 4. Enable power well 1 (PG1) and aux IO power. */
> + /* FIXME: ICL power wells code not here yet. */
> +
> + /* 5. Enable CDCLK. */
> + icl_init_cdclk(dev_priv);
> +
> + /* 6. Enable DBUF. */
> + gen9_dbuf_enable(dev_priv);
> +
> + /* 7. Setup MBUS. */
> + /* FIXME: MBUS code not here yet. */
> +
> + /* 8. CHICKEN_DCPR_1 */
> + I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) |
> +  

Re: [Intel-gfx] [PATCH 01/17] drm/i915/icl: add the main CDCLK functions

[James Ausmus]

On Tue, Jan 23, 2018 at 05:05:20PM -0200, Paulo Zanoni wrote:
> This commit adds the basic CDCLK functions, but it's still missing
> pieces of the display initialization sequence.
> 
> v2:
>  - Implement the voltage levels.
>  - Rebase.
> 
> Signed-off-by: Paulo Zanoni 
> ---
>  drivers/gpu/drm/i915/i915_reg.h|  10 +-
>  drivers/gpu/drm/i915/intel_cdclk.c | 253 
> -
>  drivers/gpu/drm/i915/intel_drv.h   |   2 +
>  3 files changed, 261 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index abd9ee876186..d72e206b2b9f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7113,8 +7113,12 @@ enum {
>  #define SKL_DFSM_PIPE_B_DISABLE  (1 << 21)
>  #define SKL_DFSM_PIPE_C_DISABLE  (1 << 28)
>  
> -#define SKL_DSSM _MMIO(0x51004)
> -#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz  (1 << 31)
> +#define SKL_DSSM _MMIO(0x51004)
> +#define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz  (1 << 31)
> +#define ICL_DSSM_CDCLK_PLL_REFCLK_MASK   (7 << 29)
> +#define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz  (0 << 29)
> +#define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz(1 << 29)
> +#define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz(2 << 29)
>  
>  #define GEN7_FF_SLICE_CS_CHICKEN1_MMIO(0x20e0)
>  #define   GEN9_FFSC_PERCTX_PREEMPT_CTRL  (1<<14)
> @@ -8760,6 +8764,8 @@ enum skl_power_gate {
>  #define  BXT_CDCLK_CD2X_PIPE_NONEBXT_CDCLK_CD2X_PIPE(3)
>  #define  BXT_CDCLK_SSA_PRECHARGE_ENABLE  (1<<16)
>  #define  CDCLK_FREQ_DECIMAL_MASK (0x7ff)
> +#define  ICL_CDCLK_CD2X_PIPE(pipe)   ((pipe) << 19)

This isn't right - pipe A is (0 << 19), but pipe B is (2 << 19), and C
is (6 << 19).

> +#define  ICL_CDCLK_CD2X_PIPE_NONEICL_CDCLK_CD2X_PIPE(7)
>  
>  /* LCPLL_CTL */
>  #define LCPLL1_CTL   _MMIO(0x46010)
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c 
> b/drivers/gpu/drm/i915/intel_cdclk.c
> index c4392ea34a3d..d867956d5a9f 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -1766,6 +1766,215 @@ static void cnl_sanitize_cdclk(struct 
> drm_i915_private *dev_priv)
>   dev_priv->cdclk.hw.vco = -1;
>  }
>  
> +static int icl_calc_cdclk(int min_cdclk, unsigned int ref)
> +{
> + int ranges_24[] = { 312000, 552000, 648000 };
> + int ranges_19_38[] = { 307200, 556800, 652800 };
> + int *ranges;
> +
> + switch (ref) {
> + default:
> + MISSING_CASE(ref);
> + case 24000:
> + ranges = ranges_24;
> + break;
> + case 19200:
> + case 38400:
> + ranges = ranges_19_38;
> + break;
> + }
> +
> + if (min_cdclk > ranges[1])
> + return ranges[2];
> + else if (min_cdclk > ranges[0])
> + return ranges[1];
> + else
> + return ranges[0];
> +}
> +
> +static int icl_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int 
> cdclk)
> +{
> + int ratio;
> +
> + /* 50MHz == CDCLK PLL disabled. */
> + if (cdclk == 5)
> + return 0;
> +
> + switch (cdclk) {
> + default:
> + MISSING_CASE(cdclk);
> + case 307200:
> + case 556800:
> + case 652800:
> + WARN_ON(dev_priv->cdclk.hw.ref != 19200 &&
> + dev_priv->cdclk.hw.ref != 38400);
> + break;
> + case 312000:
> + case 552000:
> + case 648000:
> + WARN_ON(dev_priv->cdclk.hw.ref != 24000);
> + }
> +
> + ratio = cdclk / (dev_priv->cdclk.hw.ref / 2);
> +
> + return dev_priv->cdclk.hw.ref * ratio;
> +}
> +
> +static void icl_set_cdclk(struct drm_i915_private *dev_priv,
> +   const struct intel_cdclk_state *cdclk_state)
> +{
> + unsigned int cdclk = cdclk_state->cdclk;
> + unsigned int vco = cdclk_state->vco;
> + int ret;
> + u32 voltage_level;
> +
> + mutex_lock(_priv->pcu_lock);
> + ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
> + SKL_CDCLK_PREPARE_FOR_CHANGE,
> + SKL_CDCLK_READY_FOR_CHANGE,
> + SKL_CDCLK_READY_FOR_CHANGE, 3);
> + mutex_unlock(_priv->pcu_lock);
> + if (ret) {
> + DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
> +   ret);
> + return;
> + }
> +
> + /* FIXME: We should also consider the DDI clock here. */
> + switch (cdclk) {
> + case 307200:
> + case 312000:
> + voltage_level = 0;
> + break;
> + case 556800:
> + case 552000:
> + voltage_level = 1;
> + break;
> + default:
> + MISSING_CASE(cdclk);
> + case 652800:
> + case 648000:
> + voltage_level = 2;
> + break;
> + }
> +
> 

Re: [Intel-gfx] [PATCH 02/17] drm/i915/icl: add ICL support to cnl_set_procmon_ref_values

[James Ausmus]

On Fri, Jan 26, 2018 at 06:24:32PM -0200, Paulo Zanoni wrote:
> Em Ter, 2018-01-23 às 16:32 -0800, James Ausmus escreveu:
> > On Tue, Jan 23, 2018 at 05:05:21PM -0200, Paulo Zanoni wrote:
> > > On ICL we have two sets of registers: one for port A and another
> > > for
> > > port B. The set of port A registers is the same as the CNL
> > > registers.
> > > 
> > > Since the procmon table on ICL is the same we want to reuse the CNL
> > > function. To do that we add a port argument and make CNL always
> > > call
> > > the function passing port A. This way, we'll be able to easily
> > > reuse
> > > the function on ICL when we add icl_display_core_init().
> > > 
> > > v2: Don't use _PICK() when you can use a ternary operator.
> > > 
> > > Signed-off-by: Paulo Zanoni <paulo.r.zan...@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/i915_reg.h | 26
> > > ++
> > >  drivers/gpu/drm/i915/intel_runtime_pm.c | 21 ++---
> > >  2 files changed, 40 insertions(+), 7 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > b/drivers/gpu/drm/i915/i915_reg.h
> > > index d72e206b2b9f..ebf6261d30fd 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -2102,6 +2102,32 @@ enum i915_power_well_id {
> > >  #define CNL_PORT_COMP_DW9_MMIO(0x162124)
> > >  #define CNL_PORT_COMP_DW10   _MMIO(0x162128)
> > >  
> > > +#define _ICL_PORT_COMP_DW0_A 0x162100
> > > +#define _ICL_PORT_COMP_DW0_B 0x6C100
> > > +#define ICL_PORT_COMP_DW0(port)  _MMIO((port ==
> > > PORT_A) ? \
> > > +   _ICL_PORT_COMP_DW0_A
> > > : \
> > > +   _ICL_PORT_COMP_DW0_B
> > > )
> > > +#define _ICL_PORT_COMP_DW1_A 0x162104
> > > +#define _ICL_PORT_COMP_DW1_B 0x6C104
> > > +#define ICL_PORT_COMP_DW1(port)  _MMIO((port ==
> > > PORT_A) ? \
> > > +   _ICL_PORT_COMP_DW1_A
> > > : \
> > > +   _ICL_PORT_COMP_DW1_B
> > > )
> > > +#define _ICL_PORT_COMP_DW3_A 0x16210C
> > > +#define _ICL_PORT_COMP_DW3_B 0x6C10C
> > > +#define ICL_PORT_COMP_DW3(port)  _MMIO((port ==
> > > PORT_A) ? \
> > > +   _ICL_PORT_COMP_DW3_A
> > > : \
> > > +   _ICL_PORT_COMP_DW3_B
> > > )
> > > +#define _ICL_PORT_COMP_DW9_A 0x162124
> > > +#define _ICL_PORT_COMP_DW9_B 0x6C124
> > > +#define ICL_PORT_COMP_DW9(port)  _MMIO((port ==
> > > PORT_A) ? \
> > > +   _ICL_PORT_COMP_DW9_A
> > > : \
> > > +   _ICL_PORT_COMP_DW9_B
> > > )
> > > +#define _ICL_PORT_COMP_DW10_A0x162128
> > > +#define _ICL_PORT_COMP_DW10_B0x6C128
> > > +#define ICL_PORT_COMP_DW10(port) _MMIO((port == PORT_A) ?
> > > \
> > > +   _ICL_PORT_COMP_DW10_
> > > A :   \
> > > +   _ICL_PORT_COMP_DW10_
> > > B)
> > > +
> > >  /* BXT PHY Ref registers */
> > >  #define _PORT_REF_DW3_A  0x16218C
> > >  #define _PORT_REF_DW3_BC 0x6C18C
> > > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > index 5b1aa4b9c72c..73dd525d241a 100644
> > > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > @@ -2758,12 +2758,19 @@ static const struct cnl_procmon {
> > >   { .dw1 = 0x0044, .dw9 = 0x9A00AB25, .dw10 =
> > > 0x8AE38FF1, },
> > >  };
> > >  
> > > -static void cnl_set_procmon_ref_values(struct drm_i915_private
> > > *dev_priv)
> > > +/*
> > > + * CNL has just one set of registers, while ICL has two sets: one
> > > for port A and
> > > + * the other for port B. The CNL registers are equivalent to the
> > > ICL port A
> > > + * registers, that's why we call the ICL macros even though the
> > > function has CNL
> &

Re: [Intel-gfx] [PATCH 16/17] drm/i915/icl: enable SAGV for ICL platform

[James Ausmus]

On Tue, Jan 23, 2018 at 05:05:35PM -0200, Paulo Zanoni wrote:
> From: Mahesh Kumar <mahesh1.ku...@intel.com>
> 
> Enable SAGV for ICL platform.
> 
> Signed-off-by: Mahesh Kumar <mahesh1.ku...@intel.com>

Reviewed-by: James Ausmus <james.aus...@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 1edd1445ab5b..dedc76781524 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3605,7 +3605,7 @@ static bool
>  intel_has_sagv(struct drm_i915_private *dev_priv)
>  {
>   if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) ||
> - IS_CANNONLAKE(dev_priv))
> + IS_CANNONLAKE(dev_priv) || IS_ICELAKE(dev_priv))
>   return true;
>  
>   if (IS_SKYLAKE(dev_priv) &&
> -- 
> 2.14.3
> 
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Re: [Intel-gfx] [PATCH 15/17] drm/i915/gen11: fix the SAGV block time for gen11

[James Ausmus]

On Tue, Jan 23, 2018 at 05:05:34PM -0200, Paulo Zanoni wrote:
> It's 10us for gen 11.
> 
> Reviewed-by: Mahesh Kumar <mahesh1.ku...@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zan...@intel.com>

Reviewed-by: James Ausmus <james.aus...@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 9 -
>  1 file changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 84a5b13fdee2..1edd1445ab5b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3711,11 +3711,18 @@ bool intel_can_enable_sagv(struct drm_atomic_state 
> *state)
>   struct intel_crtc_state *cstate;
>   enum pipe pipe;
>   int level, latency;
> - int sagv_block_time_us = IS_GEN9(dev_priv) ? 30 : 20;
> + int sagv_block_time_us;
>  
>   if (!intel_has_sagv(dev_priv))
>   return false;
>  
> + if (IS_GEN9(dev_priv))
> + sagv_block_time_us = 30;
> + else if (IS_GEN10(dev_priv))
> + sagv_block_time_us = 20;
> + else
> + sagv_block_time_us = 10;
> +
>   /*
>* SKL+ workaround: bspec recommends we disable the SAGV when we have
>* more then one pipe enabled
> -- 
> 2.14.3
> 
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Re: [Intel-gfx] [PATCH 12/17] drm/i915/icl: track dbuf slice-2 status

[James Ausmus]

On Tue, Jan 23, 2018 at 05:05:31PM -0200, Paulo Zanoni wrote:
> From: Mahesh Kumar <mahesh1.ku...@intel.com>
> 
> This patch adds support to start tracking status of DBUF slices.
> This is foundation to introduce support for enabling/disabling second
> DBUF slice dynamically for ICL.
> 
> Signed-off-by: Mahesh Kumar <mahesh1.ku...@intel.com>

Reviewed-by: James Ausmus <james.aus...@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h |  1 +
>  drivers/gpu/drm/i915/intel_display.c|  5 +
>  drivers/gpu/drm/i915/intel_pm.c | 20 
>  drivers/gpu/drm/i915/intel_runtime_pm.c |  4 
>  4 files changed, 30 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index cc5ac327f267..eae18661eaec 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1435,6 +1435,7 @@ static inline bool skl_ddb_entry_equal(const struct 
> skl_ddb_entry *e1,
>  struct skl_ddb_allocation {
>   struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* 
> packed/uv */
>   struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
> + uint8_t enabled_slices; /* GEN11 has configurable 2 slices */
>  };
>  
>  struct skl_wm_values {
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index 0dc4ef6cd46e..bad3b112ac3e 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -11302,6 +11302,11 @@ static void verify_wm_state(struct drm_crtc *crtc,
>   skl_ddb_get_hw_state(dev_priv, _ddb);
>   sw_ddb = _priv->wm.skl_hw.ddb;
>  
> + if (INTEL_GEN(dev_priv) >= 11)
> + if (hw_ddb.enabled_slices != sw_ddb->enabled_slices)
> + DRM_ERROR("mismatch in DBUF Slices (expected %u, got 
> %u)\n",
> +   sw_ddb->enabled_slices,
> +   hw_ddb.enabled_slices);
>   /* planes */
>   for_each_universal_plane(dev_priv, pipe, plane) {
>   hw_plane_wm = _wm.planes[plane];
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 0237362ccf83..e8d98857c208 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3570,6 +3570,23 @@ bool ilk_disable_lp_wm(struct drm_device *dev)
>   return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
>  }
>  
> +static uint8_t intel_enabled_dbuf_slices_num(struct drm_i915_private 
> *dev_priv)
> +{
> + uint8_t enabled_slices;
> +
> + /* Slice 1 will always be enabled */
> + enabled_slices = 1;
> +
> + /* Gen prior to GEN11 have only one DBuf slice */
> + if (INTEL_GEN(dev_priv) < 11)
> + return enabled_slices;
> +
> + if (I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE)
> + enabled_slices++;
> +
> + return enabled_slices;
> +}
> +
>  /*
>   * FIXME: We still don't have the proper code detect if we need to apply the 
> WA,
>   * so assume we'll always need it in order to avoid underruns.
> @@ -3828,6 +3845,8 @@ void skl_ddb_get_hw_state(struct drm_i915_private 
> *dev_priv,
>  
>   memset(ddb, 0, sizeof(*ddb));
>  
> + ddb->enabled_slices = intel_enabled_dbuf_slices_num(dev_priv);
> +
>   for_each_intel_crtc(_priv->drm, crtc) {
>   enum intel_display_power_domain power_domain;
>   enum plane_id plane_id;
> @@ -5049,6 +5068,7 @@ skl_copy_wm_for_pipe(struct skl_wm_values *dst,
>  sizeof(dst->ddb.y_plane[pipe]));
>   memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
>  sizeof(dst->ddb.plane[pipe]));
> + dst->ddb.enabled_slices = src->ddb.enabled_slices;
>  }
>  
>  static void
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index a6ed01a528bd..13c8dad95b84 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -2625,6 +2625,8 @@ static void icl_dbuf_enable(struct drm_i915_private 
> *dev_priv)
>   if (!(I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) ||
>   !(I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))
>   DRM_ERROR("DBuf power enable timeout\n");
> + else
> + dev_priv->wm.skl_hw.ddb.enabled_slices = 2;
>  }
>  
>  static void icl_dbuf_disable(struct drm_i915_private *dev_priv)
> @@ -2638,6 +2640,8 @@ static void icl_dbuf_disable(struct drm_i915_private 
> *dev_priv)
>   if ((I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) ||
>   (

Re: [Intel-gfx] [PATCH 14/17] drm/i915/icl: update ddb entry start/end mask during hw ddb readout

[James Ausmus]

On Tue, Jan 23, 2018 at 05:05:33PM -0200, Paulo Zanoni wrote:
> From: Mahesh Kumar 
> 
> Gen11/ICL onward ddb entry start/end mask is increased from 10 bits to
> 11 bits. This patch make changes to use proper mask for ICL+ during
> hardware ddb value readout.
> 
> Signed-off-by: Mahesh Kumar 
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 18 ++
>  1 file changed, 14 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index d4cd631377da..84a5b13fdee2 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3860,10 +3860,18 @@ static unsigned int skl_cursor_allocation(int 
> num_active)
>   return 8;
>  }
>  
> -static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
> +static void skl_ddb_entry_init_from_hw(struct drm_i915_private *dev_priv,
> +struct skl_ddb_entry *entry, u32 reg)
>  {
> - entry->start = reg & 0x3ff;
> - entry->end = (reg >> 16) & 0x3ff;
> + uint16_t mask;
> +
> + if (INTEL_GEN(dev_priv) >= 11)
> + mask = 0x7ff;
> + else
> + mask = 0x3ff;
> + entry->start = reg & mask;
> + entry->end = (reg >> 16) & mask;

Should these be turned in to _MASK and _SHIFT defines?

> +
>   if (entry->end)
>   entry->end += 1;
>  }
> @@ -3894,7 +3902,9 @@ void skl_ddb_get_hw_state(struct drm_i915_private 
> *dev_priv,
>   else
>   val = I915_READ(CUR_BUF_CFG(pipe));
>  
> - skl_ddb_entry_init_from_hw(>plane[pipe][plane_id], 
> val);
> + skl_ddb_entry_init_from_hw(dev_priv,
> +>plane[pipe][plane_id],
> +val);
>   }
>  
>   intel_display_power_put(dev_priv, power_domain);
> -- 
> 2.14.3
> 
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Re: [Intel-gfx] [PATCH 13/17] drm/i915/icl: Enable 2nd DBuf slice only when needed

[James Ausmus]

On Tue, Jan 23, 2018 at 05:05:32PM -0200, Paulo Zanoni wrote:
> From: Mahesh Kumar 
> 
> ICL has two slices of DBuf, each slice of size 1024 blocks.
> We should not always enable slice-2. It should be enabled only if
> display total required BW is > 12GBps OR more than 1 pipes are enabled.
> 
> Changes since V1:
>  - typecast total_data_rate to u64 before multiplication to solve any
>possible overflow (Rodrigo)
>  - fix where skl_wm_get_hw_state was memsetting ddb, resulting
>enabled_slices to become zero
>  - Fix the logic of calculating ddb_size
> Changes since V2:
>  - If no-crtc is part of commit required_slices will have value "0",
>don't try to disable DBuf slice.
> 
> Signed-off-by: Mahesh Kumar 
> ---
>  drivers/gpu/drm/i915/intel_display.c| 12 +++
>  drivers/gpu/drm/i915/intel_drv.h|  6 
>  drivers/gpu/drm/i915/intel_pm.c | 64 
> +
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 47 +---
>  4 files changed, 110 insertions(+), 19 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index bad3b112ac3e..3eb2359c221b 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -12117,6 +12117,8 @@ static void skl_update_crtcs(struct drm_atomic_state 
> *state)
>   bool progress;
>   enum pipe pipe;
>   int i;
> + uint8_t hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
> + uint8_t required_slices = intel_state->wm_results.ddb.enabled_slices;
>  
>   const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
>  
> @@ -12125,6 +12127,11 @@ static void skl_update_crtcs(struct drm_atomic_state 
> *state)
>   if (new_crtc_state->active)
>   entries[i] = 
> _intel_crtc_state(old_crtc_state)->wm.skl.ddb;
>  
> + /* If 2nd DBuf slice required, enable it here */
> + if (INTEL_GEN(dev_priv) >= 11 && required_slices &&
> +  required_slices > hw_enabled_slices)
> + icl_dbuf_slices_update(dev_priv, required_slices);
> +
>   /*
>* Whenever the number of active pipes changes, we need to make sure we
>* update the pipes in the right order so that their ddb allocations
> @@ -12175,6 +12182,11 @@ static void skl_update_crtcs(struct drm_atomic_state 
> *state)
>   progress = true;
>   }
>   } while (progress);
> +
> + /* If 2nd DBuf slice is no more required disable it */
> + if (INTEL_GEN(dev_priv) >= 11 && required_slices &&
> +  required_slices < hw_enabled_slices)
> + icl_dbuf_slices_update(dev_priv, required_slices);
>  }
>  
>  static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
> diff --git a/drivers/gpu/drm/i915/intel_drv.h 
> b/drivers/gpu/drm/i915/intel_drv.h
> index c5d6092aca41..d4639a161fe3 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -140,6 +140,10 @@
>  #define KHz(x) (1000 * (x))
>  #define MHz(x) KHz(1000 * (x))
>  
> +#define KBps(x) (1000 * (x))
> +#define MBps(x) KBps(1000 * (x))
> +#define GBps(x) ((uint64_t) 1000 * MBps((x)))
> +
>  /*
>   * Display related stuff
>   */
> @@ -1890,6 +1894,8 @@ bool intel_display_power_get_if_enabled(struct 
> drm_i915_private *dev_priv,
>   enum intel_display_power_domain domain);
>  void intel_display_power_put(struct drm_i915_private *dev_priv,
>enum intel_display_power_domain domain);
> +void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
> + uint8_t req_slices);
>  
>  static inline void
>  assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index e8d98857c208..d4cd631377da 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3767,9 +3767,42 @@ bool intel_can_enable_sagv(struct drm_atomic_state 
> *state)
>   return true;
>  }
>  
> +static unsigned int intel_get_ddb_size(struct drm_i915_private *dev_priv,
> +const struct intel_crtc_state *cstate,
> +const unsigned int total_data_rate,
> +const int num_active,
> +struct skl_ddb_allocation *ddb)
> +{
> + const struct drm_display_mode *adjusted_mode;
> + u64 total_data_bw;
> + u16 ddb_size = INTEL_INFO(dev_priv)->ddb_size;
> +
> + WARN_ON(ddb_size == 0);
> +
> + if (INTEL_GEN(dev_priv) < 11)
> + return ddb_size - 4; /* 4 blocks for bypass path allocation */
> +
> + adjusted_mode = >base.adjusted_mode;
> + total_data_bw = (u64)total_data_rate * 

Re: [Intel-gfx] [PATCH 11/17] drm/i915/icl: program mbus during pipe enable

[James Ausmus]

On Tue, Jan 23, 2018 at 05:05:30PM -0200, Paulo Zanoni wrote:
> From: Mahesh Kumar <mahesh1.ku...@intel.com>
> 
> This patch program default values of MBus credit during pipe enable.
> 
> Changes since V2:
>  - We don't need to do anything when disabling the pipe
> Changes Since V1:
>  - Add WARN_ON (Paulo)
>  - Remove TODO comment
>  - Program 0 during pipe disable
>  - Rebase
> 
> Reviewed-by: Paulo Zanoni <paulo.r.zan...@intel.com>
> Signed-off-by: Mahesh Kumar <mahesh1.ku...@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zan...@intel.com>

Reviewed-by: James Ausmus <james.aus...@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_display.c | 20 
>  1 file changed, 20 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index d585ce4c8732..0dc4ef6cd46e 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5380,6 +5380,23 @@ static void glk_pipe_scaler_clock_gating_wa(struct 
> drm_i915_private *dev_priv,
>   I915_WRITE(CLKGATE_DIS_PSL(pipe), val);
>  }
>  
> +static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
> +{
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + enum pipe pipe = crtc->pipe;
> + uint32_t val;
> +
> + if (WARN_ON(INTEL_INFO(dev_priv)->num_pipes == 0))
> + return;
> +
> + val = MBUS_DBOX_BW_CREDIT(1) | MBUS_DBOX_A_CREDIT(2);
> +
> + /* Program B credit equally to all pipes */
> + val |= MBUS_DBOX_B_CREDIT(24 / INTEL_INFO(dev_priv)->num_pipes);
> +
> + I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
> +}
> +
>  static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
>   struct drm_atomic_state *old_state)
>  {
> @@ -5457,6 +5474,9 @@ static void haswell_crtc_enable(struct intel_crtc_state 
> *pipe_config,
>   if (dev_priv->display.initial_watermarks != NULL)
>   dev_priv->display.initial_watermarks(old_intel_state, 
> pipe_config);
>  
> + if (INTEL_GEN(dev_priv) >= 11)
> + icl_pipe_mbus_enable(intel_crtc);
> +
>   /* XXX: Do the pipe assertions at the right place for BXT DSI. */
>   if (!transcoder_is_dsi(cpu_transcoder))
>   intel_enable_pipe(pipe_config);
> -- 
> 2.14.3
> 
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Re: [Intel-gfx] [PATCH 10/17] drm/i915/icl: initialize MBus during display init

[James Ausmus]

On Tue, Jan 23, 2018 at 05:05:29PM -0200, Paulo Zanoni wrote:
> From: Mahesh Kumar <mahesh1.ku...@intel.com>
> 
> This patch initializes MBus during display initialization.
> 
> Changes since V2 (from Paulo):
>  - Don't forget to remove the WARN_ON(1) call.
> Changes since V1:
>  - Rebase to use function like Macros
> 
> Reviewed-by: Paulo Zanoni <paulo.r.zan...@intel.com>
> Signed-off-by: Mahesh Kumar <mahesh1.ku...@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zan...@intel.com>

Reviewed-by: James Ausmus <james.aus...@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 14 +-
>  1 file changed, 13 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 7801a425398f..a6ed01a528bd 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -2640,6 +2640,18 @@ static void icl_dbuf_disable(struct drm_i915_private 
> *dev_priv)
>   DRM_ERROR("DBuf power disable timeout!\n");
>  }
>  
> +static void icl_mbus_init(struct drm_i915_private *dev_priv)
> +{
> + uint32_t val;
> +
> + val = MBUS_ABOX_BT_CREDIT_POOL1(16) |
> +   MBUS_ABOX_BT_CREDIT_POOL2(16) |
> +   MBUS_ABOX_B_CREDIT(1) |
> +   MBUS_ABOX_BW_CREDIT(1);
> +
> + I915_WRITE(MBUS_ABOX_CTL, val);
> +}
> +
>  static void skl_display_core_init(struct drm_i915_private *dev_priv,
>  bool resume)
>  {
> @@ -2953,7 +2965,7 @@ static void icl_display_core_init(struct 
> drm_i915_private *dev_priv,
>   icl_dbuf_enable(dev_priv);
>  
>   /* 7. Setup MBUS. */
> - /* FIXME: MBUS code not here yet. */
> + icl_mbus_init(dev_priv);
>  
>   /* 8. CHICKEN_DCPR_1 */
>   I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) |
> -- 
> 2.14.3
> 
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Re: [Intel-gfx] [PATCH 09/17] drm/i915/icl: Introduce MBus related registers

[James Ausmus]

On Tue, Jan 23, 2018 at 05:05:28PM -0200, Paulo Zanoni wrote:
> From: Mahesh Kumar <mahesh1.ku...@intel.com>
> 
> This patch introduce MBus control registers and their bit-fields
> MBUS_ABOX_CTL
> MBUS_BBOX_CTL
> MBUS_DBOX_CTL
> MBUS_UBOX_CTL
> 
> Changes Since V1:
>  - Use function like macros (Paulo)
>  - fix copy-paste error (Paulo)
> 
> Reviewed-by: Paulo Zanoni <paulo.r.zan...@intel.com>
> Signed-off-by: Mahesh Kumar <mahesh1.ku...@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zan...@intel.com>

Reviewed-by: James Ausmus <james.aus...@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 25 +
>  1 file changed, 25 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1746df9a263d..0cb77cd18cdb 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2679,6 +2679,31 @@ enum i915_power_well_id {
>  #define LM_FIFO_WATERMARK   0x001F
>  #define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */
>  
> +#define MBUS_ABOX_CTL_MMIO(0x45038)
> +#define MBUS_ABOX_BW_CREDIT_MASK (3 << 20)
> +#define MBUS_ABOX_BW_CREDIT(x)   ((x) << 20)
> +#define MBUS_ABOX_B_CREDIT_MASK  (0xF << 16)
> +#define MBUS_ABOX_B_CREDIT(x)((x) << 16)
> +#define MBUS_ABOX_BT_CREDIT_POOL2_MASK   (0x1F << 8)
> +#define MBUS_ABOX_BT_CREDIT_POOL2(x) ((x) << 8)
> +#define MBUS_ABOX_BT_CREDIT_POOL1_MASK   (0x1F << 0)
> +#define MBUS_ABOX_BT_CREDIT_POOL1(x) ((x) << 0)
> +
> +#define _PIPEA_MBUS_DBOX_CTL 0x7003C
> +#define _PIPEB_MBUS_DBOX_CTL 0x7103C
> +#define PIPE_MBUS_DBOX_CTL(pipe) _MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \
> +_PIPEB_MBUS_DBOX_CTL)
> +#define MBUS_DBOX_BW_CREDIT_MASK (3 << 14)
> +#define MBUS_DBOX_BW_CREDIT(x)   ((x) << 14)
> +#define MBUS_DBOX_B_CREDIT_MASK  (0x1F << 8)
> +#define MBUS_DBOX_B_CREDIT(x)((x) << 8)
> +#define MBUS_DBOX_A_CREDIT_MASK  (0xF << 0)
> +#define MBUS_DBOX_A_CREDIT(x)((x) << 0)
> +
> +#define MBUS_UBOX_CTL_MMIO(0x4503C)
> +#define MBUS_BBOX_CTL_S1 _MMIO(0x45040)
> +#define MBUS_BBOX_CTL_S2 _MMIO(0x45044)
> +
>  /* Make render/texture TLB fetches lower priorty than associated data
>   *   fetches. This is not turned on by default
>   */
> -- 
> 2.14.3
> 
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Re: [Intel-gfx] [PATCH 08/17] drm/i915/icl: NV12 y-plane ddb is not in same plane

[James Ausmus]

On Tue, Jan 23, 2018 at 05:05:27PM -0200, Paulo Zanoni wrote:
> From: Mahesh Kumar <mahesh1.ku...@intel.com>
> 
> We don't have planar pixel format support implemented for ICL yet.
> ICL require 2 display planes to be allocated for Planar formats unlike
> previous GEN. So ICL/GEN11 doesn't require to write Y-plane ddb data in
> NV12_BUF_CFG register and PLANE_NV12_BUF_CFG register is removed in ICL.
> 
> This patch removes the PLANE_NV12_BUF_CFG write for ICL.
> 
> Changes Since V1:
>  - Improve commit message as per Paulo's comment
> 
> Reviewed-by: Paulo Zanoni <paulo.r.zan...@intel.com>
> Signed-off-by: Mahesh Kumar <mahesh1.ku...@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zan...@intel.com>

Reviewed-by: James Ausmus <james.aus...@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 6 --
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index c6d31a5075ad..0237362ccf83 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4832,8 +4832,10 @@ static void skl_write_plane_wm(struct intel_crtc 
> *intel_crtc,
>  
>   skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
>   >plane[pipe][plane_id]);
> - skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane_id),
> - >y_plane[pipe][plane_id]);
> + if (INTEL_GEN(dev_priv) < 11)
> + skl_ddb_entry_write(dev_priv,
> + PLANE_NV12_BUF_CFG(pipe, plane_id),
> + >y_plane[pipe][plane_id]);
>  }
>  
>  static void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
> -- 
> 2.14.3
> 
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Re: [Intel-gfx] [PATCH 06/17] drm/i915/icl: Do not fix dbuf block size to 512

[James Ausmus]

On Tue, Jan 23, 2018 at 05:05:25PM -0200, Paulo Zanoni wrote:
> From: Mahesh Kumar 
> 
> GEN9/10 had fixed DBuf block size of 512. Dbuf block size is not a
> fixed number anymore in GEN11, it varies according to bits per pixel
> and tiling. If 8bpp & Yf-tile surface, block size = 256 else block
> size = 512
> 
> This patch addresses the same.
> 
> v2 (from Paulo):
>   - Make it compile.
>   - Fix a few coding style issues.
> v3
>   - Rebase on top of upstream patches
> 
> Signed-off-by: Mahesh Kumar 
> Signed-off-by: Paulo Zanoni 
> ---
>  drivers/gpu/drm/i915/i915_drv.h |  1 +
>  drivers/gpu/drm/i915/intel_pm.c | 27 ---
>  2 files changed, 21 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 8333692dac5a..cc5ac327f267 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1460,6 +1460,7 @@ struct skl_wm_params {
>   uint_fixed_16_16_t plane_blocks_per_line;
>   uint_fixed_16_16_t y_tile_minimum;
>   uint32_t linetime_us;
> + uint32_t dbuf_block_size;
>  };
>  
>  /*
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 11aac65d1543..44d952a3d9a6 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4312,7 +4312,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
>  */
>  static uint_fixed_16_16_t
>  skl_wm_method1(const struct drm_i915_private *dev_priv, uint32_t pixel_rate,
> -uint8_t cpp, uint32_t latency)
> +uint8_t cpp, uint32_t latency, uint32_t dbuf_block_size)
>  {
>   uint32_t wm_intermediate_val;
>   uint_fixed_16_16_t ret;
> @@ -4321,7 +4321,7 @@ skl_wm_method1(const struct drm_i915_private *dev_priv, 
> uint32_t pixel_rate,
>   return FP_16_16_MAX;
>  
>   wm_intermediate_val = latency * pixel_rate * cpp;
> - ret = div_fixed16(wm_intermediate_val, 1000 * 512);
> + ret = div_fixed16(wm_intermediate_val, 1000 * dbuf_block_size);
>  
>   if (INTEL_GEN(dev_priv) >= 10)
>   ret = add_fixed16_u32(ret, 1);
> @@ -4431,6 +4431,15 @@ skl_compute_plane_wm_params(const struct 
> drm_i915_private *dev_priv,
>   wp->plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate,
>intel_pstate);
>  
> + if (INTEL_GEN(dev_priv) >= 11) {
> + if (fb->modifier == I915_FORMAT_MOD_Yf_TILED && wp->cpp == 8)
> + wp->dbuf_block_size = 256;
> + else
> + wp->dbuf_block_size = 512;
> + } else {
> + wp->dbuf_block_size = 512;
> + }

This could be simplified as (approximately)

wp->dbuf_block_size = 512;
if (INTEL_GEN(dev_priv) >= 11 && fb->modifier == I915_FORMAT_MOD_Yf_TILED &&
wp->cpp == 8)
wp->dbuf_block_size = 256;


> +
>   if (drm_rotation_90_or_270(pstate->rotation)) {
>  
>   switch (wp->cpp) {
> @@ -4457,7 +4466,8 @@ skl_compute_plane_wm_params(const struct 
> drm_i915_private *dev_priv,
>   wp->plane_bytes_per_line = wp->width * wp->cpp;
>   if (wp->y_tiled) {
>   interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line *
> -wp->y_min_scanlines, 512);
> +wp->y_min_scanlines,
> +wp->dbuf_block_size);
>  
>   if (INTEL_GEN(dev_priv) >= 10)
>   interm_pbpl++;
> @@ -4465,10 +4475,12 @@ skl_compute_plane_wm_params(const struct 
> drm_i915_private *dev_priv,
>   wp->plane_blocks_per_line = div_fixed16(interm_pbpl,
>   wp->y_min_scanlines);
>   } else if (wp->x_tiled && IS_GEN9(dev_priv)) {
> - interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line, 512);
> + interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line,
> +wp->dbuf_block_size);
>   wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
>   } else {
> - interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line, 512) + 1;
> + interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line,
> +wp->dbuf_block_size) + 1;
>   wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
>   }
>  
> @@ -4515,7 +4527,7 @@ static int skl_compute_plane_wm(const struct 
> drm_i915_private *dev_priv,
>   latency += 15;
>  
>   method1 = skl_wm_method1(dev_priv, wp->plane_pixel_rate,
> -  wp->cpp, latency);
> +  wp->cpp, latency, wp->dbuf_block_size);
>   method2 = skl_wm_method2(wp->plane_pixel_rate,
>cstate->base.adjusted_mode.crtc_htotal,
>   

Re: [Intel-gfx] [PATCH 05/17] drm/i915/icl: Don't allocate fixed bypass path blocks for ICL

[James Ausmus]

On Tue, Jan 23, 2018 at 05:05:24PM -0200, Paulo Zanoni wrote:
> From: Mahesh Kumar <mahesh1.ku...@intel.com>
> 
> GEN9 onwards bypass path allocation of 4 blocks was needed, as per
> hardware design. ICL doesn't require bypass path allocation of 4 DDB
> blocks, handling the same in this patch.
> 
> v2 (from Paulo):
>   - No need for a comment that says what the code already says.
> 
> Reviewed-by: Paulo Zanoni <paulo.r.zan...@intel.com>
> Signed-off-by: Mahesh Kumar <mahesh1.ku...@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zan...@intel.com>

Reviewed-by: James Ausmus <james.aus...@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 0b92ea1dbd40..11aac65d1543 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3778,7 +3778,8 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device 
> *dev,
>   ddb_size = INTEL_INFO(dev_priv)->ddb_size;
>   WARN_ON(ddb_size == 0);
>  
> - ddb_size -= 4; /* 4 blocks for bypass path allocation */
> + if (INTEL_GEN(dev_priv) < 11)
> + ddb_size -= 4; /* 4 blocks for bypass path allocation */
>  
>   /*
>* If the state doesn't change the active CRTC's, then there's
> -- 
> 2.14.3
> 
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Re: [Intel-gfx] [PATCH 04/17] drm/i915/icl: Enable both DBuf slices during init

[James Ausmus]

On Tue, Jan 23, 2018 at 05:05:23PM -0200, Paulo Zanoni wrote:
> From: Mahesh Kumar 
> 
> ICL has 2 slices of DBuf, enable both the slices during display init.
> 
> Ideally we should only enable the second slice when needed in order to
> save power, but while we're not there yet, adopt the simpler solution
> to keep us bug-free.
> 
> v2 (from Paulo):
>   - Add the TODO comment.
>   - Reorganize where things are defined.
>   - Fix indentation.
>   - Remove unnecessary POSTING_READ() calls.
>   - Improve the commit message.
> 
> Signed-off-by: Mahesh Kumar 
> Signed-off-by: Paulo Zanoni 
> ---
>  drivers/gpu/drm/i915/i915_reg.h |  2 ++
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 34 
> +++--
>  2 files changed, 34 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 979bc06a59f4..1746df9a263d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7122,6 +7122,8 @@ enum {
>  #define  DISP_DATA_PARTITION_5_6 (1<<6)
>  #define  DISP_IPC_ENABLE (1<<3)
>  #define DBUF_CTL _MMIO(0x45008)
> +#define DBUF_CTL_S1  _MMIO(0x45008)

Since it's the exact same register, is it really worth duplicating, or
should we just use the existing DBUF_CTL instead of adding DBUF_CTL_S1?


> +#define DBUF_CTL_S2  _MMIO(0x44FE8)
>  #define  DBUF_POWER_REQUEST  (1<<31)
>  #define  DBUF_POWER_STATE(1<<30)
>  #define GEN7_MSG_CTL _MMIO(0x45010)
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 2556db16c76a..7801a425398f 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -2610,6 +2610,36 @@ static void gen9_dbuf_disable(struct drm_i915_private 
> *dev_priv)
>   DRM_ERROR("DBuf power disable timeout!\n");
>  }
>  
> +/*
> + * TODO: we shouldn't always enable DBUF_CTL_S2, we should only enable it 
> when
> + * needed and keep it disabled as much as possible.
> + */
> +static void icl_dbuf_enable(struct drm_i915_private *dev_priv)
> +{
> + I915_WRITE(DBUF_CTL_S1, I915_READ(DBUF_CTL_S1) | DBUF_POWER_REQUEST);
> + I915_WRITE(DBUF_CTL_S2, I915_READ(DBUF_CTL_S2) | DBUF_POWER_REQUEST);
> + POSTING_READ(DBUF_CTL_S2);
> +
> + udelay(10);

BSpec says to poll, and timeout/fail after 10 uS, rather than
unconditionally busy wait - worth making more complex to potentially
save a few uS of busy wait?

> +
> + if (!(I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) ||
> + !(I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))
> + DRM_ERROR("DBuf power enable timeout\n");
> +}
> +
> +static void icl_dbuf_disable(struct drm_i915_private *dev_priv)
> +{
> + I915_WRITE(DBUF_CTL_S1, I915_READ(DBUF_CTL_S1) & ~DBUF_POWER_REQUEST);
> + I915_WRITE(DBUF_CTL_S2, I915_READ(DBUF_CTL_S2) & ~DBUF_POWER_REQUEST);
> + POSTING_READ(DBUF_CTL_S2);
> +
> + udelay(10);
> +
> + if ((I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) ||
> + (I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))
> + DRM_ERROR("DBuf power disable timeout!\n");
> +}
> +
>  static void skl_display_core_init(struct drm_i915_private *dev_priv,
>  bool resume)
>  {
> @@ -2920,7 +2950,7 @@ static void icl_display_core_init(struct 
> drm_i915_private *dev_priv,
>   icl_init_cdclk(dev_priv);
>  
>   /* 6. Enable DBUF. */
> - gen9_dbuf_enable(dev_priv);
> + icl_dbuf_enable(dev_priv);
>  
>   /* 7. Setup MBUS. */
>   /* FIXME: MBUS code not here yet. */
> @@ -2940,7 +2970,7 @@ static void icl_display_core_uninit(struct 
> drm_i915_private *dev_priv)
>   /* 1. Disable all display engine functions -> aready done */
>  
>   /* 2. Disable DBUF */
> - gen9_dbuf_disable(dev_priv);
> + icl_dbuf_disable(dev_priv);
>  
>   /* 3. Disable CD clock */
>   icl_uninit_cdclk(dev_priv);
> -- 
> 2.14.3
> 
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Re: [Intel-gfx] [PATCH 02/17] drm/i915/icl: add ICL support to cnl_set_procmon_ref_values

[James Ausmus]

ocmon->dw9);
> + I915_WRITE(ICL_PORT_COMP_DW10(port), procmon->dw10);
>  }
>  
>  static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool 
> resume)
> @@ -2811,7 +2818,7 @@ static void cnl_display_core_init(struct 
> drm_i915_private *dev_priv, bool resume
>   val &= ~CNL_COMP_PWR_DOWN;
>   I915_WRITE(CHICKEN_MISC_2, val);
>  
> - cnl_set_procmon_ref_values(dev_priv);
> + cnl_set_procmon_ref_values(dev_priv, PORT_A);

Maybe worth a one-line comment here about why we're passing PORT_A so
drive-by readings don't get confused on why we're only setting PORT_A?

Maybe something like

/* Dummy PORT_A to get the correct CNL register from the ICL macro */

Either way:

Reviewed-by: James Ausmus <james.aus...@intel.com>

>  
>   val = I915_READ(CNL_PORT_COMP_DW0);
>   val |= COMP_INIT;
> -- 
> 2.14.3
> 
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Re: [Intel-gfx] [PATCH 6/8] drm/i915/icp: Add backlight Support for ICP

[James Ausmus]

On Fri, Jan 19, 2018 at 09:26:02AM -0800, Anusha Srivatsa wrote:
> On Fri, Jan 19, 2018 at 02:40:41PM -0200, Paulo Zanoni wrote:
> > Em Qui, 2018-01-11 às 15:57 -0800, Rodrigo Vivi escreveu:
> > > On Thu, Jan 11, 2018 at 09:48:57PM +, James Ausmus wrote:
> > > > On Thu, Jan 11, 2018 at 04:00:08PM -0200, Paulo Zanoni wrote:
> > > > > From: Anusha Srivatsa <anusha.sriva...@intel.com>
> > > > > 
> > > > > ICP has two backlight controllers - similar to previous platforms
> > > > > like
> > > > > BXT.
> > > > > 
> > > > > v2: Remove the usage of ICP_SECOND_PPS_BACKLIGHT register.(Jani)
> > > > > Reuse BXT code since it is very similar.(Ville)
> > > > > 
> > > > > v3 (from Paulo): Rebase.
> > > > > 
> > > > > Cc: Jani Nikula <jani.nik...@intel.com>
> > > > > Cc: Ville Syrjala <ville.syrj...@linux.intel.com>
> > > > > Reviewed-by: Paulo Zanoni <paulo.r.zan...@intel.com>
> > > > > Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com>
> > > > > Signed-off-by: Paulo Zanoni <paulo.r.zan...@intel.com>
> > > > > ---
> > > > >  drivers/gpu/drm/i915/intel_panel.c | 2 +-
> > > > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > > > > 
> > > > > diff --git a/drivers/gpu/drm/i915/intel_panel.c
> > > > > b/drivers/gpu/drm/i915/intel_panel.c
> > > > > index fa6831f8c004..ad80cca8c110 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_panel.c
> > > > > +++ b/drivers/gpu/drm/i915/intel_panel.c
> > > > > @@ -1865,7 +1865,7 @@ intel_panel_init_backlight_funcs(struct
> > > > > intel_panel *panel)
> > > > >   panel->backlight.set = bxt_set_backlight;
> > > > >   panel->backlight.get = bxt_get_backlight;
> > > > >   panel->backlight.hz_to_pwm = bxt_hz_to_pwm;
> > > > > - } else if (HAS_PCH_CNP(dev_priv)) {
> > > > > + } else if (HAS_PCH_CNP(dev_priv) ||
> > > > > HAS_PCH_ICP(dev_priv)) {
> > > > 
> > > > The commit message says reuse BXT, but the code says reuse CNP -
> > > > which
> > > > one should it be?
> > > 
> > > well,
> > > CNP is like BXT, but with only one controller.
> > > ICP is like BXT, including 2 controllers.
> > > 
> > > I don't know if it makes more sense re-use the cnp or bxt functions
> > > 
> > > But one way or another we have to address these lines from cnp_setup:
> > > 
> > >  /*
> > >  * CNP has the BXT implementation of backlight, but with only
> > >  * one controller. Future platforms could have multiple
> > > controll\
> > > ers
> > >  * so let's make this extensible and prepared for the future.
> > >  */
> > > panel->backlight.controller = 0;
> > 
> > My understanding is that we're only using one of the controllers on ICP
> > on purpose, so we can perfectly reuse the CNP code.
> > 
> > But I'll let Anusha comment on this.
> 
> This is intentional. Commit message is trying to tell the similarity 
> in backlight support. But we need to reuse CNP code ultimstely.

OK - in that case, the commit message needs to get less confusing, as it
explicitly states that ICP is similar to BXT, and it explicitly states
that v2 changed the commit to reuse BXT code, but the actual code is
clearly using CNP code, and doesn't mention CNP (or the justification
for using CNP) anywhere. :)

Maybe explain that we're using CNP code intentionally, even though it
supports two BL controllers, and explain *why* we're ignoring the second
BL controller? I'm still not sure why that is myself :)

Thanks!

-James

> 
> Regards,
> Anusha 
> > > 
> > > > 
> > > > >   panel->backlight.setup = cnp_setup_backlight;
> > > > >   panel->backlight.enable = cnp_enable_backlight;
> > > > >   panel->backlight.disable =
> > > > > cnp_disable_backlight;
> > > > > --
> > > > > 2.14.3
> > > > > 
> > > > > ___
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> > > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > > > 
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> 
> -- 
> Anusha Srivatsa
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Re: [Intel-gfx] [PATCH 6/8] drm/i915/icp: Add backlight Support for ICP

[James Ausmus]

On Thu, Jan 11, 2018 at 04:00:08PM -0200, Paulo Zanoni wrote:
> From: Anusha Srivatsa 
> 
> ICP has two backlight controllers - similar to previous platforms like
> BXT.
> 
> v2: Remove the usage of ICP_SECOND_PPS_BACKLIGHT register.(Jani)
> Reuse BXT code since it is very similar.(Ville)
> 
> v3 (from Paulo): Rebase.
> 
> Cc: Jani Nikula 
> Cc: Ville Syrjala 
> Reviewed-by: Paulo Zanoni 
> Signed-off-by: Anusha Srivatsa 
> Signed-off-by: Paulo Zanoni 
> ---
>  drivers/gpu/drm/i915/intel_panel.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_panel.c 
> b/drivers/gpu/drm/i915/intel_panel.c
> index fa6831f8c004..ad80cca8c110 100644
> --- a/drivers/gpu/drm/i915/intel_panel.c
> +++ b/drivers/gpu/drm/i915/intel_panel.c
> @@ -1865,7 +1865,7 @@ intel_panel_init_backlight_funcs(struct intel_panel 
> *panel)
>   panel->backlight.set = bxt_set_backlight;
>   panel->backlight.get = bxt_get_backlight;
>   panel->backlight.hz_to_pwm = bxt_hz_to_pwm;
> - } else if (HAS_PCH_CNP(dev_priv)) {
> + } else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_ICP(dev_priv)) {

The commit message says reuse BXT, but the code says reuse CNP - which
one should it be?

>   panel->backlight.setup = cnp_setup_backlight;
>   panel->backlight.enable = cnp_enable_backlight;
>   panel->backlight.disable = cnp_disable_backlight;
> -- 
> 2.14.3
> 
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[Intel-gfx] [PATCH] drm/i915/cnl: Mask previous DDI - PLL mapping

[James Ausmus]

Without masking out the old value, we can end up pointing the DDI to a
disabled PLL, which makes the system fall over. Mask out the previous
value before setting the PLL to DDI mapping.

This can be observed by running igt/testdisplay with both an eDP and
HDMI/DP output active.

v2: Add the Bugzilla link

Fixes: 555e38d273172 ("drm/i915/cnl: DDI - PLL mapping")
Testcase: igt/testdisplay
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103997
Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Matt Atwood <matthew.s.atw...@intel.com>
Signed-off-by: James Ausmus <james.aus...@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index eff3b51872eb..123a3253453f 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2098,6 +2098,7 @@ static void intel_ddi_clk_select(struct intel_encoder 
*encoder,
if (IS_CANNONLAKE(dev_priv)) {
/* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
val = I915_READ(DPCLKA_CFGCR0);
+   val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->id, port);
I915_WRITE(DPCLKA_CFGCR0, val);
 
-- 
2.15.1

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[Intel-gfx] [PATCH] drm/i915/cnl: Mask previous DDI - PLL mapping

[James Ausmus]

Without masking out the old value, we can end up pointing the DDI to a
disabled PLL, which makes the system fall over. Mask out the previous
value before setting the PLL to DDI mapping.

This can be observed by running igt/testdisplay with both an eDP and
HDMI/DP output active.

Fixes: 555e38d273172 ("drm/i915/cnl: DDI - PLL mapping")
Testcase: igt/testdisplay
Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Matt Atwood <matthew.s.atw...@intel.com>
Signed-off-by: James Ausmus <james.aus...@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index eff3b51872eb..123a3253453f 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2098,6 +2098,7 @@ static void intel_ddi_clk_select(struct intel_encoder 
*encoder,
if (IS_CANNONLAKE(dev_priv)) {
/* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
val = I915_READ(DPCLKA_CFGCR0);
+   val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->id, port);
I915_WRITE(DPCLKA_CFGCR0, val);
 
-- 
2.15.1

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Re: [Intel-gfx] [PATCH v6 03/10] drm/i915: s/enum plane/enum i9xx_plane_id/

[James Ausmus]

On Fri, Nov 17, 2017 at 09:19:10PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrj...@linux.intel.com>
> 
> Rename enum plane to enum i9xx_plane_id to make it clear that it only
> applies to pre-SKL platforms.
> 
> enum i9xx_plane_id is a global identifier, whereas enum plane_id is
> per-pipe. We need the old global identifier to index the primary plane
> (and the pre-g4x sprite C if we ever expose it) registers on pre-SKL
> platforms.
> 
> v2: Reorder patches
> v3: s/old_plane_id/i9xx_plane_id/ (Daniel)
> Pimp the commit message a bit
> Note that i9xx_plane_id doesn't apply to SKL+
> v4: Rebase due to power domain handling in plane readout
> v5: Rebase due to crtc->dspaddr_offset removal
> v6: s/plane/i9xx_plane/ etc. (James)
> 
> Cc: James Ausmus <james.aus...@intel.com>
> Cc: Daniel Vetter <dan...@ffwll.ch>
> Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>

And here you had me hoping for plane->bikeshed ;)

Reviewed-by: James Ausmus <james.aus...@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h  |  6 +--
>  drivers/gpu/drm/i915/intel_display.c | 98 
> ++--
>  drivers/gpu/drm/i915/intel_drv.h |  6 +--
>  drivers/gpu/drm/i915/intel_fbc.c | 12 ++---
>  drivers/gpu/drm/i915/intel_sprite.c  |  2 +-
>  5 files changed, 62 insertions(+), 62 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 2158a758a17d..55dd602582cb 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -304,9 +304,9 @@ static inline bool transcoder_is_dsi(enum transcoder 
> transcoder)
>  
>  /*
>   * Global legacy plane identifier. Valid only for primary/sprite
> - * planes on pre-g4x, and only for primary planes on g4x+.
> + * planes on pre-g4x, and only for primary planes on g4x-bdw.
>   */
> -enum plane {
> +enum i9xx_plane_id {
>   PLANE_A,
>   PLANE_B,
>   PLANE_C,
> @@ -1145,7 +1145,7 @@ struct intel_fbc {
>  
>   struct {
>   enum pipe pipe;
> - enum plane plane;
> + enum i9xx_plane_id i9xx_plane;
>   unsigned int fence_y_offset;
>   } crtc;
>  
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index 91f74c5373b3..16ac86816f28 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3220,16 +3220,16 @@ int i9xx_check_plane_surface(struct intel_plane_state 
> *plane_state)
>   return 0;
>  }
>  
> -static void i9xx_update_primary_plane(struct intel_plane *primary,
> -   const struct intel_crtc_state *crtc_state,
> -   const struct intel_plane_state 
> *plane_state)
> +static void i9xx_update_plane(struct intel_plane *plane,
> +   const struct intel_crtc_state *crtc_state,
> +   const struct intel_plane_state *plane_state)
>  {
> - struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
> + struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>   const struct drm_framebuffer *fb = plane_state->base.fb;
> - enum plane plane = primary->plane;
> + enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
>   u32 linear_offset;
>   u32 dspcntr = plane_state->ctl;
> - i915_reg_t reg = DSPCNTR(plane);
> + i915_reg_t reg = DSPCNTR(i9xx_plane);
>   int x = plane_state->main.x;
>   int y = plane_state->main.y;
>   unsigned long irqflags;
> @@ -3248,34 +3248,34 @@ static void i9xx_update_primary_plane(struct 
> intel_plane *primary,
>   /* pipesrc and dspsize control the size that is scaled from,
>* which should always be the user's requested size.
>*/
> - I915_WRITE_FW(DSPSIZE(plane),
> + I915_WRITE_FW(DSPSIZE(i9xx_plane),
> ((crtc_state->pipe_src_h - 1) << 16) |
> (crtc_state->pipe_src_w - 1));
> - I915_WRITE_FW(DSPPOS(plane), 0);
> - } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
> - I915_WRITE_FW(PRIMSIZE(plane),
> + I915_WRITE_FW(DSPPOS(i9xx_plane), 0);
> + } else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
> + I915_WRITE_FW(PRIMSIZE(i9xx_plane),
> ((crtc_state->pipe_src_h - 1) << 16) |
> (crtc_state->pipe_src_w - 1));
> -

Re: [Intel-gfx] [PATCH v2 10/10] drm/i915: Add rudimentary plane state verification

[James Ausmus]

On Thu, Nov 02, 2017 at 06:38:32PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrj...@linux.intel.com>
> 
> Check that the planes are in the state we expect them to be. For
> now we can only check whether each plane is correctly enabled or
> disabled. In the future we may want to expand the plane state
> readout to support a more through verification.

s/through/thorough/

> 
> v2: Verify all planes part of the state as long as at lest

s/lest/least

> one crtc is doing a modeset (Daniel)
> 
> Cc: Daniel Vetter <daniel.vet...@ffwll.ch>
> Suggested-by: Daniel Vetter <daniel.vet...@ffwll.ch>
> Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>

With those nits fixed:

Reviewed-by: James Ausmus <james.aus...@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_display.c | 15 +++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index c23dad6d3c24..96e0a5fd69cf 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -11537,6 +11537,18 @@ verify_crtc_state(struct drm_crtc *crtc,
>  }
>  
>  static void
> +intel_verify_planes(struct intel_atomic_state *state)
> +{
> + struct intel_plane *plane;
> + const struct intel_plane_state *plane_state;
> + int i;
> +
> + for_each_new_intel_plane_in_state(state, plane,
> +   plane_state, i)
> + assert_plane(plane, plane_state->base.visible);
> +}
> +
> +static void
>  verify_single_dpll_state(struct drm_i915_private *dev_priv,
>struct intel_shared_dpll *pll,
>struct drm_crtc *crtc,
> @@ -12329,6 +12341,9 @@ static void intel_atomic_commit_tail(struct 
> drm_atomic_state *state)
>   intel_modeset_verify_crtc(crtc, state, old_crtc_state, 
> new_crtc_state);
>   }
>  
> + if (intel_state->modeset)
> + intel_verify_planes(intel_state);
> +
>   if (intel_state->modeset && intel_can_enable_sagv(state))
>   intel_enable_sagv(dev_priv);
>  
> -- 
> 2.13.6
> 
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Re: [Intel-gfx] [PATCH 09/10] drm/i915: Use plane->get_hw_state() for initial plane fb readout

[James Ausmus]

On Fri, Oct 13, 2017 at 04:58:38PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrj...@linux.intel.com>
> 
> Since we now have a ->get_hw_state() method for planes, let's use
> that during the initial plane fb readout.
> 
> Cc: Daniel Vetter <daniel.vet...@ffwll.ch>
> Suggested-by: Daniel Vetter <daniel.vet...@ffwll.ch>
> Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>

Reviewed-by: James Ausmus <james.aus...@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_display.c | 30 --
>  1 file changed, 16 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index 2da670628e35..268d320690f4 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -7465,19 +7465,20 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
>   struct drm_framebuffer *fb;
>   struct intel_framebuffer *intel_fb;
>  
> + if (!plane->get_hw_state(plane))
> + return;
> +
> + intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
> + if (!intel_fb) {
> + DRM_DEBUG_KMS("failed to alloc fb\n");
> + return;
> + }
> +
> + fb = _fb->base;
> +
> + fb->dev = dev;
> +
>   val = I915_READ(DSPCNTR(plane_id));
> - if (!(val & DISPLAY_PLANE_ENABLE))
> - return;
> -
> - intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
> - if (!intel_fb) {
> - DRM_DEBUG_KMS("failed to alloc fb\n");
> - return;
> - }
> -
> - fb = _fb->base;
> -
> - fb->dev = dev;
>  
>   if (INTEL_GEN(dev_priv) >= 4) {
>   if (val & DISPPLANE_TILED) {
> @@ -8496,6 +8497,9 @@ skylake_get_initial_plane_config(struct intel_crtc 
> *crtc,
>   struct drm_framebuffer *fb;
>   struct intel_framebuffer *intel_fb;
>  
> + if (!plane->get_hw_state(plane))
> + return;
> +
>   intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
>   if (!intel_fb) {
>   DRM_DEBUG_KMS("failed to alloc fb\n");
> @@ -8507,8 +8511,6 @@ skylake_get_initial_plane_config(struct intel_crtc 
> *crtc,
>   fb->dev = dev;
>  
>   val = I915_READ(PLANE_CTL(pipe, plane_id));
> - if (!(val & PLANE_CTL_ENABLE))
> - goto error;
>  
>   pixel_format = val & PLANE_CTL_FORMAT_MASK;
>   fourcc = skl_format_to_fourcc(pixel_format,
> -- 
> 2.13.6
> 
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Re: [Intel-gfx] [PATCH v5 03/10] drm/i915: s/enum plane/enum i9xx_plane_id/

[James Ausmus]

On Mon, Oct 23, 2017 at 05:50:32PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä 
> 
> Rename enum plane to enum i9xx_plane_id to make it clear that it only
> applies to pre-SKL platforms.
> 
> enum i9xx_plane_id is a global identifier, whereas enum plane_id is
> per-pipe. We need the old global identifier to index the primary plane
> (and the pre-g4x sprite C if we ever expose it) registers on pre-SKL
> platforms.
> 
> v2: Reorder patches
> v3: s/old_plane_id/i9xx_plane_id/ (Daniel)
> Pimp the commit message a bit
> Note that i9xx_plane_id doesn't apply to SKL+
> v4: Rebase due to power domain handling in plane readout
> v5: Rebase due to crtc->dspaddr_offset removal
> 
> Cc: Daniel Vetter 
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/i915_drv.h  |  6 +--
>  drivers/gpu/drm/i915/intel_display.c | 87 
> ++--
>  drivers/gpu/drm/i915/intel_drv.h |  6 +--
>  3 files changed, 49 insertions(+), 50 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 54b5d4c582b6..a6b912c646f9 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -305,9 +305,9 @@ static inline bool transcoder_is_dsi(enum transcoder 
> transcoder)
>  
>  /*
>   * Global legacy plane identifier. Valid only for primary/sprite
> - * planes on pre-g4x, and only for primary planes on g4x+.
> + * planes on pre-g4x, and only for primary planes on g4x-bdw.
>   */
> -enum plane {
> +enum i9xx_plane_id {
>   PLANE_A,
>   PLANE_B,
>   PLANE_C,
> @@ -1137,7 +1137,7 @@ struct intel_fbc {
>  
>   struct {
>   enum pipe pipe;
> - enum plane plane;
> + enum i9xx_plane_id plane;
>   unsigned int fence_y_offset;
>   } crtc;
>  
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index 4ea0f1ef249e..e726b65588aa 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3223,16 +3223,16 @@ int i9xx_check_plane_surface(struct intel_plane_state 
> *plane_state)
>   return 0;
>  }
>  
> -static void i9xx_update_primary_plane(struct intel_plane *primary,
> -   const struct intel_crtc_state *crtc_state,
> -   const struct intel_plane_state 
> *plane_state)
> +static void i9xx_update_plane(struct intel_plane *plane,
> +   const struct intel_crtc_state *crtc_state,
> +   const struct intel_plane_state *plane_state)
>  {
> - struct drm_i915_private *dev_priv = to_i915(primary->base.dev);
> + struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
>   const struct drm_framebuffer *fb = plane_state->base.fb;
> - enum plane plane = primary->plane;
> + enum i9xx_plane_id plane_id = plane->plane;

It feels a bit ugly and counter-intuitive to have the two "plane"s in
"plane->plane" be different types - since i9xx_plane_id is a global id,
would it make sense to change the member naming to plane_gid or some
such (both in struct intel_plane and in struct intel_fbc->crtc)? It
feels like struct intel_plane should continue to be "plane", but we need
something else for enum i9xx_plane_id just for clarity's sake.

>   u32 linear_offset;
>   u32 dspcntr = plane_state->ctl;
> - i915_reg_t reg = DSPCNTR(plane);
> + i915_reg_t reg = DSPCNTR(plane_id);
>   int x = plane_state->main.x;
>   int y = plane_state->main.y;
>   unsigned long irqflags;
> @@ -3251,34 +3251,34 @@ static void i9xx_update_primary_plane(struct 
> intel_plane *primary,
>   /* pipesrc and dspsize control the size that is scaled from,
>* which should always be the user's requested size.
>*/
> - I915_WRITE_FW(DSPSIZE(plane),
> + I915_WRITE_FW(DSPSIZE(plane_id),
> ((crtc_state->pipe_src_h - 1) << 16) |
> (crtc_state->pipe_src_w - 1));
> - I915_WRITE_FW(DSPPOS(plane), 0);
> - } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
> - I915_WRITE_FW(PRIMSIZE(plane),
> + I915_WRITE_FW(DSPPOS(plane_id), 0);
> + } else if (IS_CHERRYVIEW(dev_priv) && plane_id == PLANE_B) {
> + I915_WRITE_FW(PRIMSIZE(plane_id),
> ((crtc_state->pipe_src_h - 1) << 16) |
> (crtc_state->pipe_src_w - 1));
> - I915_WRITE_FW(PRIMPOS(plane), 0);
> - I915_WRITE_FW(PRIMCNSTALPHA(plane), 0);
> + I915_WRITE_FW(PRIMPOS(plane_id), 0);
> + I915_WRITE_FW(PRIMCNSTALPHA(plane_id), 0);
>   }
>  
>   I915_WRITE_FW(reg, dspcntr);
>  
> - I915_WRITE_FW(DSPSTRIDE(plane), 

[Intel-gfx] [PATCH v4] drm/i915/glk: Refactor handling of PLANE_COLOR_CTL for GLK+

[James Ausmus]

Since GLK, some plane configuration settings have moved to the
PLANE_COLOR_CTL register. Refactor handling of the register to work like
PLANE_CTL. This also allows us to fix the set/read of the plane Alpha
Mode for GLK+.

v2: Adjust ordering of platform checks to be newest->oldest, drop
redundant comment about alpha blending. (Ville)

v3: Move Alpha Mode bits out of skl_plane_ctl_format into
skl_plane_ctl_alpha, and drop glk_plane_ctl_format, drop initialization
of state->color_ctl on platforms that don't use it, and drop color_ctl
local var. (Ville)

v4: Consolidate skl_plane_ctl_format switch statement on formats that
return the same settings. (Ville)

Signed-off-by: James Ausmus <james.aus...@intel.com>
Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
---

NOTE: Resending without the --in-reply-to, as it seems I managed to
confuse the CI system, so v4 didn't get properly picked up for testing

 drivers/gpu/drm/i915/i915_reg.h  | 12 --
 drivers/gpu/drm/i915/intel_display.c | 73 
 drivers/gpu/drm/i915/intel_drv.h |  5 +++
 drivers/gpu/drm/i915/intel_sprite.c  | 11 +++---
 4 files changed, 76 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 05e33a41fcc7..222aea49c06a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6295,7 +6295,7 @@ enum {
 #define _PLANE_CTL_2_A 0x70280
 #define _PLANE_CTL_3_A 0x70380
 #define   PLANE_CTL_ENABLE (1 << 31)
-#define   PLANE_CTL_PIPE_GAMMA_ENABLE  (1 << 30)
+#define   PLANE_CTL_PIPE_GAMMA_ENABLE  (1 << 30)   /* Pre-GLK */
 #define   PLANE_CTL_FORMAT_MASK(0xf << 24)
 #define   PLANE_CTL_FORMAT_YUV422  (  0 << 24)
 #define   PLANE_CTL_FORMAT_NV12(  1 << 24)
@@ -6305,7 +6305,7 @@ enum {
 #define   PLANE_CTL_FORMAT_AYUV(  8 << 24)
 #define   PLANE_CTL_FORMAT_INDEXED ( 12 << 24)
 #define   PLANE_CTL_FORMAT_RGB_565 ( 14 << 24)
-#define   PLANE_CTL_PIPE_CSC_ENABLE(1 << 23)
+#define   PLANE_CTL_PIPE_CSC_ENABLE(1 << 23) /* Pre-GLK */
 #define   PLANE_CTL_KEY_ENABLE_MASK(0x3 << 21)
 #define   PLANE_CTL_KEY_ENABLE_SOURCE  (  1 << 21)
 #define   PLANE_CTL_KEY_ENABLE_DESTINATION (  2 << 21)
@@ -6318,13 +6318,13 @@ enum {
 #define   PLANE_CTL_YUV422_VYUY(  3 << 16)
 #define   PLANE_CTL_DECOMPRESSION_ENABLE   (1 << 15)
 #define   PLANE_CTL_TRICKLE_FEED_DISABLE   (1 << 14)
-#define   PLANE_CTL_PLANE_GAMMA_DISABLE(1 << 13)
+#define   PLANE_CTL_PLANE_GAMMA_DISABLE(1 << 13) /* Pre-GLK */
 #define   PLANE_CTL_TILED_MASK (0x7 << 10)
 #define   PLANE_CTL_TILED_LINEAR   (  0 << 10)
 #define   PLANE_CTL_TILED_X(  1 << 10)
 #define   PLANE_CTL_TILED_Y(  4 << 10)
 #define   PLANE_CTL_TILED_YF   (  5 << 10)
-#define   PLANE_CTL_ALPHA_MASK (0x3 << 4)
+#define   PLANE_CTL_ALPHA_MASK (0x3 << 4) /* Pre-GLK */
 #define   PLANE_CTL_ALPHA_DISABLE  (  0 << 4)
 #define   PLANE_CTL_ALPHA_SW_PREMULTIPLY   (  2 << 4)
 #define   PLANE_CTL_ALPHA_HW_PREMULTIPLY   (  3 << 4)
@@ -6364,6 +6364,10 @@ enum {
 #define   PLANE_COLOR_PIPE_GAMMA_ENABLE(1 << 30)
 #define   PLANE_COLOR_PIPE_CSC_ENABLE  (1 << 23)
 #define   PLANE_COLOR_PLANE_GAMMA_DISABLE  (1 << 13)
+#define   PLANE_COLOR_ALPHA_MASK   (0x3 << 4)
+#define   PLANE_COLOR_ALPHA_DISABLE(0 << 4)
+#define   PLANE_COLOR_ALPHA_SW_PREMULTIPLY (2 << 4)
+#define   PLANE_COLOR_ALPHA_HW_PREMULTIPLY (3 << 4)
 #define _PLANE_BUF_CFG_1_A 0x7027c
 #define _PLANE_BUF_CFG_2_A 0x7037c
 #define _PLANE_NV12_BUF_CFG_1_A0x70278
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 0ebf3f283b87..ed6a4a8d9273 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3432,20 +3432,11 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
case DRM_FORMAT_RGB565:
return PLANE_CTL_FORMAT_RGB_565;
case DRM_FORMAT_XBGR:
+   case DRM_FORMAT_ABGR:
return PLANE_CTL_FORMAT_XRGB_ | PLANE_CTL_ORDER_RGBX;
case DRM_FORMAT_XRGB:
-   return PLANE_CTL_FORMAT_XRGB_;
-   /*
-* X

[Intel-gfx] [PATCH v4] drm/i915/glk: Refactor handling of PLANE_COLOR_CTL for GLK+

[James Ausmus]

Since GLK, some plane configuration settings have moved to the
PLANE_COLOR_CTL register. Refactor handling of the register to work like
PLANE_CTL. This also allows us to fix the set/read of the plane Alpha
Mode for GLK+.

v2: Adjust ordering of platform checks to be newest->oldest, drop
redundant comment about alpha blending. (Ville)

v3: Move Alpha Mode bits out of skl_plane_ctl_format into
skl_plane_ctl_alpha, and drop glk_plane_ctl_format, drop initialization
of state->color_ctl on platforms that don't use it, and drop color_ctl
local var. (Ville)

v4: Consolidate skl_plane_ctl_format switch statement on formats that
return the same settings. (Ville)

Signed-off-by: James Ausmus <james.aus...@intel.com>
Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  | 12 --
 drivers/gpu/drm/i915/intel_display.c | 73 
 drivers/gpu/drm/i915/intel_drv.h |  5 +++
 drivers/gpu/drm/i915/intel_sprite.c  | 11 +++---
 4 files changed, 76 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6ef33422f762..8e76fb91b306 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6264,7 +6264,7 @@ enum {
 #define _PLANE_CTL_2_A 0x70280
 #define _PLANE_CTL_3_A 0x70380
 #define   PLANE_CTL_ENABLE (1 << 31)
-#define   PLANE_CTL_PIPE_GAMMA_ENABLE  (1 << 30)
+#define   PLANE_CTL_PIPE_GAMMA_ENABLE  (1 << 30)   /* Pre-GLK */
 #define   PLANE_CTL_FORMAT_MASK(0xf << 24)
 #define   PLANE_CTL_FORMAT_YUV422  (  0 << 24)
 #define   PLANE_CTL_FORMAT_NV12(  1 << 24)
@@ -6274,7 +6274,7 @@ enum {
 #define   PLANE_CTL_FORMAT_AYUV(  8 << 24)
 #define   PLANE_CTL_FORMAT_INDEXED ( 12 << 24)
 #define   PLANE_CTL_FORMAT_RGB_565 ( 14 << 24)
-#define   PLANE_CTL_PIPE_CSC_ENABLE(1 << 23)
+#define   PLANE_CTL_PIPE_CSC_ENABLE(1 << 23) /* Pre-GLK */
 #define   PLANE_CTL_KEY_ENABLE_MASK(0x3 << 21)
 #define   PLANE_CTL_KEY_ENABLE_SOURCE  (  1 << 21)
 #define   PLANE_CTL_KEY_ENABLE_DESTINATION (  2 << 21)
@@ -6287,13 +6287,13 @@ enum {
 #define   PLANE_CTL_YUV422_VYUY(  3 << 16)
 #define   PLANE_CTL_DECOMPRESSION_ENABLE   (1 << 15)
 #define   PLANE_CTL_TRICKLE_FEED_DISABLE   (1 << 14)
-#define   PLANE_CTL_PLANE_GAMMA_DISABLE(1 << 13)
+#define   PLANE_CTL_PLANE_GAMMA_DISABLE(1 << 13) /* Pre-GLK */
 #define   PLANE_CTL_TILED_MASK (0x7 << 10)
 #define   PLANE_CTL_TILED_LINEAR   (  0 << 10)
 #define   PLANE_CTL_TILED_X(  1 << 10)
 #define   PLANE_CTL_TILED_Y(  4 << 10)
 #define   PLANE_CTL_TILED_YF   (  5 << 10)
-#define   PLANE_CTL_ALPHA_MASK (0x3 << 4)
+#define   PLANE_CTL_ALPHA_MASK (0x3 << 4) /* Pre-GLK */
 #define   PLANE_CTL_ALPHA_DISABLE  (  0 << 4)
 #define   PLANE_CTL_ALPHA_SW_PREMULTIPLY   (  2 << 4)
 #define   PLANE_CTL_ALPHA_HW_PREMULTIPLY   (  3 << 4)
@@ -6333,6 +6333,10 @@ enum {
 #define   PLANE_COLOR_PIPE_GAMMA_ENABLE(1 << 30)
 #define   PLANE_COLOR_PIPE_CSC_ENABLE  (1 << 23)
 #define   PLANE_COLOR_PLANE_GAMMA_DISABLE  (1 << 13)
+#define   PLANE_COLOR_ALPHA_MASK   (0x3 << 4)
+#define   PLANE_COLOR_ALPHA_DISABLE(0 << 4)
+#define   PLANE_COLOR_ALPHA_SW_PREMULTIPLY (2 << 4)
+#define   PLANE_COLOR_ALPHA_HW_PREMULTIPLY (3 << 4)
 #define _PLANE_BUF_CFG_1_A 0x7027c
 #define _PLANE_BUF_CFG_2_A 0x7037c
 #define _PLANE_NV12_BUF_CFG_1_A0x70278
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 5c7540f3f5dc..dd552d79ebaf 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3432,20 +3432,11 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
case DRM_FORMAT_RGB565:
return PLANE_CTL_FORMAT_RGB_565;
case DRM_FORMAT_XBGR:
+   case DRM_FORMAT_ABGR:
return PLANE_CTL_FORMAT_XRGB_ | PLANE_CTL_ORDER_RGBX;
case DRM_FORMAT_XRGB:
-   return PLANE_CTL_FORMAT_XRGB_;
-   /*
-* XXX: For ARBG/ABGR formats we default to expecting scanout buffers
-* to be already pre-multiplied. We need to add a knob (o

[Intel-gfx] [CI v3] drm/i915/glk: Refactor handling of PLANE_COLOR_CTL for GLK+

[James Ausmus]

Since GLK, some plane configuration settings have moved to the
PLANE_COLOR_CTL register. Refactor handling of the register to work like
PLANE_CTL. This also allows us to fix the set/read of the plane Alpha
Mode for GLK+.

v2: Adjust ordering of platform checks to be newest->oldest, drop
redundant comment about alpha blending. (Ville)

v3: Move Alpha Mode bits out of skl_plane_ctl_format into
skl_plane_ctl_alpha, and drop glk_plane_ctl_format, drop initialization
of state->color_ctl on platforms that don't use it, and drop color_ctl
local var. (Ville)

Signed-off-by: James Ausmus <james.aus...@intel.com>
Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  | 12 --
 drivers/gpu/drm/i915/intel_display.c | 71 +---
 drivers/gpu/drm/i915/intel_drv.h |  5 +++
 drivers/gpu/drm/i915/intel_sprite.c  | 11 +++---
 4 files changed, 76 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f0f8f6059652..ecd6b236e005 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6263,7 +6263,7 @@ enum {
 #define _PLANE_CTL_2_A 0x70280
 #define _PLANE_CTL_3_A 0x70380
 #define   PLANE_CTL_ENABLE (1 << 31)
-#define   PLANE_CTL_PIPE_GAMMA_ENABLE  (1 << 30)
+#define   PLANE_CTL_PIPE_GAMMA_ENABLE  (1 << 30)   /* Pre-GLK */
 #define   PLANE_CTL_FORMAT_MASK(0xf << 24)
 #define   PLANE_CTL_FORMAT_YUV422  (  0 << 24)
 #define   PLANE_CTL_FORMAT_NV12(  1 << 24)
@@ -6273,7 +6273,7 @@ enum {
 #define   PLANE_CTL_FORMAT_AYUV(  8 << 24)
 #define   PLANE_CTL_FORMAT_INDEXED ( 12 << 24)
 #define   PLANE_CTL_FORMAT_RGB_565 ( 14 << 24)
-#define   PLANE_CTL_PIPE_CSC_ENABLE(1 << 23)
+#define   PLANE_CTL_PIPE_CSC_ENABLE(1 << 23) /* Pre-GLK */
 #define   PLANE_CTL_KEY_ENABLE_MASK(0x3 << 21)
 #define   PLANE_CTL_KEY_ENABLE_SOURCE  (  1 << 21)
 #define   PLANE_CTL_KEY_ENABLE_DESTINATION (  2 << 21)
@@ -6286,13 +6286,13 @@ enum {
 #define   PLANE_CTL_YUV422_VYUY(  3 << 16)
 #define   PLANE_CTL_DECOMPRESSION_ENABLE   (1 << 15)
 #define   PLANE_CTL_TRICKLE_FEED_DISABLE   (1 << 14)
-#define   PLANE_CTL_PLANE_GAMMA_DISABLE(1 << 13)
+#define   PLANE_CTL_PLANE_GAMMA_DISABLE(1 << 13) /* Pre-GLK */
 #define   PLANE_CTL_TILED_MASK (0x7 << 10)
 #define   PLANE_CTL_TILED_LINEAR   (  0 << 10)
 #define   PLANE_CTL_TILED_X(  1 << 10)
 #define   PLANE_CTL_TILED_Y(  4 << 10)
 #define   PLANE_CTL_TILED_YF   (  5 << 10)
-#define   PLANE_CTL_ALPHA_MASK (0x3 << 4)
+#define   PLANE_CTL_ALPHA_MASK (0x3 << 4) /* Pre-GLK */
 #define   PLANE_CTL_ALPHA_DISABLE  (  0 << 4)
 #define   PLANE_CTL_ALPHA_SW_PREMULTIPLY   (  2 << 4)
 #define   PLANE_CTL_ALPHA_HW_PREMULTIPLY   (  3 << 4)
@@ -6332,6 +6332,10 @@ enum {
 #define   PLANE_COLOR_PIPE_GAMMA_ENABLE(1 << 30)
 #define   PLANE_COLOR_PIPE_CSC_ENABLE  (1 << 23)
 #define   PLANE_COLOR_PLANE_GAMMA_DISABLE  (1 << 13)
+#define   PLANE_COLOR_ALPHA_MASK   (0x3 << 4)
+#define   PLANE_COLOR_ALPHA_DISABLE(0 << 4)
+#define   PLANE_COLOR_ALPHA_SW_PREMULTIPLY (2 << 4)
+#define   PLANE_COLOR_ALPHA_HW_PREMULTIPLY (3 << 4)
 #define _PLANE_BUF_CFG_1_A 0x7027c
 #define _PLANE_BUF_CFG_2_A 0x7037c
 #define _PLANE_NV12_BUF_CFG_1_A0x70278
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 737de251d0f8..214c0c119002 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3436,17 +3436,10 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
return PLANE_CTL_FORMAT_XRGB_ | PLANE_CTL_ORDER_RGBX;
case DRM_FORMAT_XRGB:
return PLANE_CTL_FORMAT_XRGB_;
-   /*
-* XXX: For ARBG/ABGR formats we default to expecting scanout buffers
-* to be already pre-multiplied. We need to add a knob (or a different
-* DRM_FORMAT) for user-space to configure that.
-*/
case DRM_FORMAT_ABGR:
-   return PLANE_CTL_FORMAT_XRGB_ | PLANE_CTL_ORDER_RGBX |
-   PLANE_CTL_ALPHA_SW_PREMULTIPLY;
+   return PLANE_CTL_FORMAT_XRGB_ | PLANE_CTL_

[Intel-gfx] [CI v3] drm/i915/glk: Refactor handling of PLANE_COLOR_CTL for GLK+

[James Ausmus]

Since GLK, some plane configuration settings have moved to the
PLANE_COLOR_CTL register. Refactor handling of the register to work like
PLANE_CTL. This also allows us to fix the set/read of the plane Alpha
Mode for GLK+.

v2: Adjust ordering of platform checks to be newest->oldest, drop
redundant comment about alpha blending. (Ville)

v3: Move Alpha Mode bits out of skl_plane_ctl_format into
skl_plane_ctl_alpha, and drop glk_plane_ctl_format, drop initialization
of state->color_ctl on platforms that don't use it, and drop color_ctl
local var. (Ville)

Signed-off-by: James Ausmus <james.aus...@intel.com>
Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  | 12 --
 drivers/gpu/drm/i915/intel_display.c | 71 +---
 drivers/gpu/drm/i915/intel_drv.h |  5 +++
 drivers/gpu/drm/i915/intel_sprite.c  | 11 +++---
 4 files changed, 76 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f0f8f6059652..ecd6b236e005 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6263,7 +6263,7 @@ enum {
 #define _PLANE_CTL_2_A 0x70280
 #define _PLANE_CTL_3_A 0x70380
 #define   PLANE_CTL_ENABLE (1 << 31)
-#define   PLANE_CTL_PIPE_GAMMA_ENABLE  (1 << 30)
+#define   PLANE_CTL_PIPE_GAMMA_ENABLE  (1 << 30)   /* Pre-GLK */
 #define   PLANE_CTL_FORMAT_MASK(0xf << 24)
 #define   PLANE_CTL_FORMAT_YUV422  (  0 << 24)
 #define   PLANE_CTL_FORMAT_NV12(  1 << 24)
@@ -6273,7 +6273,7 @@ enum {
 #define   PLANE_CTL_FORMAT_AYUV(  8 << 24)
 #define   PLANE_CTL_FORMAT_INDEXED ( 12 << 24)
 #define   PLANE_CTL_FORMAT_RGB_565 ( 14 << 24)
-#define   PLANE_CTL_PIPE_CSC_ENABLE(1 << 23)
+#define   PLANE_CTL_PIPE_CSC_ENABLE(1 << 23) /* Pre-GLK */
 #define   PLANE_CTL_KEY_ENABLE_MASK(0x3 << 21)
 #define   PLANE_CTL_KEY_ENABLE_SOURCE  (  1 << 21)
 #define   PLANE_CTL_KEY_ENABLE_DESTINATION (  2 << 21)
@@ -6286,13 +6286,13 @@ enum {
 #define   PLANE_CTL_YUV422_VYUY(  3 << 16)
 #define   PLANE_CTL_DECOMPRESSION_ENABLE   (1 << 15)
 #define   PLANE_CTL_TRICKLE_FEED_DISABLE   (1 << 14)
-#define   PLANE_CTL_PLANE_GAMMA_DISABLE(1 << 13)
+#define   PLANE_CTL_PLANE_GAMMA_DISABLE(1 << 13) /* Pre-GLK */
 #define   PLANE_CTL_TILED_MASK (0x7 << 10)
 #define   PLANE_CTL_TILED_LINEAR   (  0 << 10)
 #define   PLANE_CTL_TILED_X(  1 << 10)
 #define   PLANE_CTL_TILED_Y(  4 << 10)
 #define   PLANE_CTL_TILED_YF   (  5 << 10)
-#define   PLANE_CTL_ALPHA_MASK (0x3 << 4)
+#define   PLANE_CTL_ALPHA_MASK (0x3 << 4) /* Pre-GLK */
 #define   PLANE_CTL_ALPHA_DISABLE  (  0 << 4)
 #define   PLANE_CTL_ALPHA_SW_PREMULTIPLY   (  2 << 4)
 #define   PLANE_CTL_ALPHA_HW_PREMULTIPLY   (  3 << 4)
@@ -6332,6 +6332,10 @@ enum {
 #define   PLANE_COLOR_PIPE_GAMMA_ENABLE(1 << 30)
 #define   PLANE_COLOR_PIPE_CSC_ENABLE  (1 << 23)
 #define   PLANE_COLOR_PLANE_GAMMA_DISABLE  (1 << 13)
+#define   PLANE_COLOR_ALPHA_MASK   (0x3 << 4)
+#define   PLANE_COLOR_ALPHA_DISABLE(0 << 4)
+#define   PLANE_COLOR_ALPHA_SW_PREMULTIPLY (2 << 4)
+#define   PLANE_COLOR_ALPHA_HW_PREMULTIPLY (3 << 4)
 #define _PLANE_BUF_CFG_1_A 0x7027c
 #define _PLANE_BUF_CFG_2_A 0x7037c
 #define _PLANE_NV12_BUF_CFG_1_A0x70278
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 737de251d0f8..214c0c119002 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3436,17 +3436,10 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
return PLANE_CTL_FORMAT_XRGB_ | PLANE_CTL_ORDER_RGBX;
case DRM_FORMAT_XRGB:
return PLANE_CTL_FORMAT_XRGB_;
-   /*
-* XXX: For ARBG/ABGR formats we default to expecting scanout buffers
-* to be already pre-multiplied. We need to add a knob (or a different
-* DRM_FORMAT) for user-space to configure that.
-*/
case DRM_FORMAT_ABGR:
-   return PLANE_CTL_FORMAT_XRGB_ | PLANE_CTL_ORDER_RGBX |
-   PLANE_CTL_ALPHA_SW_PREMULTIPLY;
+   return PLANE_CTL_FORMAT_XRGB_ | PLANE_CTL_

[Intel-gfx] [PATCH v3] drm/i915/glk: Refactor handling of PLANE_COLOR_CTL for GLK+

[James Ausmus]

Since GLK, some plane configuration settings have moved to the
PLANE_COLOR_CTL register. Refactor handling of the register to work like
PLANE_CTL. This also allows us to fix the set/read of the plane Alpha
Mode for GLK+.

v2: Adjust ordering of platform checks to be newest->oldest, drop
redundant comment about alpha blending. (Ville)

v3: Move Alpha Mode bits out of skl_plane_ctl_format into
skl_plane_ctl_alpha, and drop glk_plane_ctl_format, drop initialization
of state->color_ctl on platforms that don't use it, and drop color_ctl
local var. (Ville)

Signed-off-by: James Ausmus <james.aus...@intel.com>
Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  | 12 --
 drivers/gpu/drm/i915/intel_display.c | 71 +---
 drivers/gpu/drm/i915/intel_drv.h |  5 +++
 drivers/gpu/drm/i915/intel_sprite.c  | 11 +++---
 4 files changed, 76 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f0f8f6059652..ecd6b236e005 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6263,7 +6263,7 @@ enum {
 #define _PLANE_CTL_2_A 0x70280
 #define _PLANE_CTL_3_A 0x70380
 #define   PLANE_CTL_ENABLE (1 << 31)
-#define   PLANE_CTL_PIPE_GAMMA_ENABLE  (1 << 30)
+#define   PLANE_CTL_PIPE_GAMMA_ENABLE  (1 << 30)   /* Pre-GLK */
 #define   PLANE_CTL_FORMAT_MASK(0xf << 24)
 #define   PLANE_CTL_FORMAT_YUV422  (  0 << 24)
 #define   PLANE_CTL_FORMAT_NV12(  1 << 24)
@@ -6273,7 +6273,7 @@ enum {
 #define   PLANE_CTL_FORMAT_AYUV(  8 << 24)
 #define   PLANE_CTL_FORMAT_INDEXED ( 12 << 24)
 #define   PLANE_CTL_FORMAT_RGB_565 ( 14 << 24)
-#define   PLANE_CTL_PIPE_CSC_ENABLE(1 << 23)
+#define   PLANE_CTL_PIPE_CSC_ENABLE(1 << 23) /* Pre-GLK */
 #define   PLANE_CTL_KEY_ENABLE_MASK(0x3 << 21)
 #define   PLANE_CTL_KEY_ENABLE_SOURCE  (  1 << 21)
 #define   PLANE_CTL_KEY_ENABLE_DESTINATION (  2 << 21)
@@ -6286,13 +6286,13 @@ enum {
 #define   PLANE_CTL_YUV422_VYUY(  3 << 16)
 #define   PLANE_CTL_DECOMPRESSION_ENABLE   (1 << 15)
 #define   PLANE_CTL_TRICKLE_FEED_DISABLE   (1 << 14)
-#define   PLANE_CTL_PLANE_GAMMA_DISABLE(1 << 13)
+#define   PLANE_CTL_PLANE_GAMMA_DISABLE(1 << 13) /* Pre-GLK */
 #define   PLANE_CTL_TILED_MASK (0x7 << 10)
 #define   PLANE_CTL_TILED_LINEAR   (  0 << 10)
 #define   PLANE_CTL_TILED_X(  1 << 10)
 #define   PLANE_CTL_TILED_Y(  4 << 10)
 #define   PLANE_CTL_TILED_YF   (  5 << 10)
-#define   PLANE_CTL_ALPHA_MASK (0x3 << 4)
+#define   PLANE_CTL_ALPHA_MASK (0x3 << 4) /* Pre-GLK */
 #define   PLANE_CTL_ALPHA_DISABLE  (  0 << 4)
 #define   PLANE_CTL_ALPHA_SW_PREMULTIPLY   (  2 << 4)
 #define   PLANE_CTL_ALPHA_HW_PREMULTIPLY   (  3 << 4)
@@ -6332,6 +6332,10 @@ enum {
 #define   PLANE_COLOR_PIPE_GAMMA_ENABLE(1 << 30)
 #define   PLANE_COLOR_PIPE_CSC_ENABLE  (1 << 23)
 #define   PLANE_COLOR_PLANE_GAMMA_DISABLE  (1 << 13)
+#define   PLANE_COLOR_ALPHA_MASK   (0x3 << 4)
+#define   PLANE_COLOR_ALPHA_DISABLE(0 << 4)
+#define   PLANE_COLOR_ALPHA_SW_PREMULTIPLY (2 << 4)
+#define   PLANE_COLOR_ALPHA_HW_PREMULTIPLY (3 << 4)
 #define _PLANE_BUF_CFG_1_A 0x7027c
 #define _PLANE_BUF_CFG_2_A 0x7037c
 #define _PLANE_NV12_BUF_CFG_1_A0x70278
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 737de251d0f8..214c0c119002 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3436,17 +3436,10 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
return PLANE_CTL_FORMAT_XRGB_ | PLANE_CTL_ORDER_RGBX;
case DRM_FORMAT_XRGB:
return PLANE_CTL_FORMAT_XRGB_;
-   /*
-* XXX: For ARBG/ABGR formats we default to expecting scanout buffers
-* to be already pre-multiplied. We need to add a knob (or a different
-* DRM_FORMAT) for user-space to configure that.
-*/
case DRM_FORMAT_ABGR:
-   return PLANE_CTL_FORMAT_XRGB_ | PLANE_CTL_ORDER_RGBX |
-   PLANE_CTL_ALPHA_SW_PREMULTIPLY;
+   return PLANE_CTL_FORMAT_XRGB_ | PLANE_CTL_

Re: [Intel-gfx] [PATCH v2] drm/i915/glk: Refactor handling of PLANE_COLOR_CTL for GLK+

[James Ausmus]

On Fri, Nov 03, 2017 at 07:31:44PM +0200, Ville Syrjälä wrote:
> On Fri, Nov 03, 2017 at 09:58:48AM -0700, James Ausmus wrote:
> > Since GLK, some plane configuration settings have moved to the
> > PLANE_COLOR_CTL register. Refactor handling of the register to work like
> > PLANE_CTL. This also allows us to fix the set/read of the plane Alpha
> > Mode for GLK+.
> > 
> > v2: Adjust ordering of platform checks to be newest->oldest, drop
> > redundant comment about alpha blending. (Ville)
> > 
> > Signed-off-by: James Ausmus <james.aus...@intel.com>
> > Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
> > Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h  | 12 +---
> >  drivers/gpu/drm/i915/intel_display.c | 55 
> > 
> >  drivers/gpu/drm/i915/intel_drv.h |  5 
> >  drivers/gpu/drm/i915/intel_sprite.c  | 14 +
> >  4 files changed, 71 insertions(+), 15 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h 
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index f0f8f6059652..ecd6b236e005 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -6263,7 +6263,7 @@ enum {
> >  #define _PLANE_CTL_2_A 0x70280
> >  #define _PLANE_CTL_3_A 0x70380
> >  #define   PLANE_CTL_ENABLE (1 << 31)
> > -#define   PLANE_CTL_PIPE_GAMMA_ENABLE  (1 << 30)
> > +#define   PLANE_CTL_PIPE_GAMMA_ENABLE  (1 << 30)   /* Pre-GLK 
> > */
> >  #define   PLANE_CTL_FORMAT_MASK(0xf << 24)
> >  #define   PLANE_CTL_FORMAT_YUV422  (  0 << 24)
> >  #define   PLANE_CTL_FORMAT_NV12(  1 << 24)
> > @@ -6273,7 +6273,7 @@ enum {
> >  #define   PLANE_CTL_FORMAT_AYUV(  8 << 24)
> >  #define   PLANE_CTL_FORMAT_INDEXED ( 12 << 24)
> >  #define   PLANE_CTL_FORMAT_RGB_565 ( 14 << 24)
> > -#define   PLANE_CTL_PIPE_CSC_ENABLE(1 << 23)
> > +#define   PLANE_CTL_PIPE_CSC_ENABLE(1 << 23) /* Pre-GLK */
> >  #define   PLANE_CTL_KEY_ENABLE_MASK(0x3 << 21)
> >  #define   PLANE_CTL_KEY_ENABLE_SOURCE  (  1 << 21)
> >  #define   PLANE_CTL_KEY_ENABLE_DESTINATION (  2 << 21)
> > @@ -6286,13 +6286,13 @@ enum {
> >  #define   PLANE_CTL_YUV422_VYUY(  3 << 16)
> >  #define   PLANE_CTL_DECOMPRESSION_ENABLE   (1 << 15)
> >  #define   PLANE_CTL_TRICKLE_FEED_DISABLE   (1 << 14)
> > -#define   PLANE_CTL_PLANE_GAMMA_DISABLE(1 << 13)
> > +#define   PLANE_CTL_PLANE_GAMMA_DISABLE(1 << 13) /* Pre-GLK */
> >  #define   PLANE_CTL_TILED_MASK (0x7 << 10)
> >  #define   PLANE_CTL_TILED_LINEAR   (  0 << 10)
> >  #define   PLANE_CTL_TILED_X(  1 << 10)
> >  #define   PLANE_CTL_TILED_Y(  4 << 10)
> >  #define   PLANE_CTL_TILED_YF   (  5 << 10)
> > -#define   PLANE_CTL_ALPHA_MASK (0x3 << 4)
> > +#define   PLANE_CTL_ALPHA_MASK (0x3 << 4) /* Pre-GLK */
> >  #define   PLANE_CTL_ALPHA_DISABLE  (  0 << 4)
> >  #define   PLANE_CTL_ALPHA_SW_PREMULTIPLY   (  2 << 4)
> >  #define   PLANE_CTL_ALPHA_HW_PREMULTIPLY   (  3 << 4)
> > @@ -6332,6 +6332,10 @@ enum {
> >  #define   PLANE_COLOR_PIPE_GAMMA_ENABLE(1 << 30)
> >  #define   PLANE_COLOR_PIPE_CSC_ENABLE  (1 << 23)
> >  #define   PLANE_COLOR_PLANE_GAMMA_DISABLE  (1 << 13)
> > +#define   PLANE_COLOR_ALPHA_MASK   (0x3 << 4)
> > +#define   PLANE_COLOR_ALPHA_DISABLE(0 << 4)
> > +#define   PLANE_COLOR_ALPHA_SW_PREMULTIPLY (2 << 4)
> > +#define   PLANE_COLOR_ALPHA_HW_PREMULTIPLY (3 << 4)
> >  #define _PLANE_BUF_CFG_1_A 0x7027c
> >  #define _PLANE_BUF_CFG_2_A 0x7037c
> >  #define _PLANE_NV12_BUF_CFG_1_A0x70278
> > diff --git a/drivers/gpu/drm/i915/intel_display.c 
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 737de251d0f8..39453276dad1 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -3466,6 +3466,23 @@ static u32 skl_plane_ctl_format(uint32_t 
> > pix

Re: [Intel-gfx] [PATCH] drm/i915/glk: Refactor handling of PLANE_COLOR_CTL for GLK+

[James Ausmus]

On Fri, Nov 03, 2017 at 12:12:09PM +0200, Ville Syrjälä wrote:
> On Thu, Nov 02, 2017 at 04:00:49PM -0700, James Ausmus wrote:
> > Since GLK, some plane configuration settings have moved to the
> > PLANE_COLOR_CTL register. Refactor handling of the register to work like
> > PLANE_CTL. This also allows us to fix the set/read of the plane Alpha
> > Mode for GLK+.
> > 
> > Signed-off-by: James Ausmus <james.aus...@intel.com>
> > Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h  | 12 +---
> >  drivers/gpu/drm/i915/intel_display.c | 60 
> > +---
> >  drivers/gpu/drm/i915/intel_drv.h |  5 +++
> >  drivers/gpu/drm/i915/intel_sprite.c  | 14 +
> >  4 files changed, 76 insertions(+), 15 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h 
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 68a58cce6ab1..520ff9a15222 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -6263,7 +6263,7 @@ enum {
> >  #define _PLANE_CTL_2_A 0x70280
> >  #define _PLANE_CTL_3_A 0x70380
> >  #define   PLANE_CTL_ENABLE (1 << 31)
> > -#define   PLANE_CTL_PIPE_GAMMA_ENABLE  (1 << 30)
> > +#define   PLANE_CTL_PIPE_GAMMA_ENABLE  (1 << 30)   /* Pre-GLK 
> > */
> >  #define   PLANE_CTL_FORMAT_MASK(0xf << 24)
> >  #define   PLANE_CTL_FORMAT_YUV422  (  0 << 24)
> >  #define   PLANE_CTL_FORMAT_NV12(  1 << 24)
> > @@ -6273,7 +6273,7 @@ enum {
> >  #define   PLANE_CTL_FORMAT_AYUV(  8 << 24)
> >  #define   PLANE_CTL_FORMAT_INDEXED ( 12 << 24)
> >  #define   PLANE_CTL_FORMAT_RGB_565 ( 14 << 24)
> > -#define   PLANE_CTL_PIPE_CSC_ENABLE(1 << 23)
> > +#define   PLANE_CTL_PIPE_CSC_ENABLE(1 << 23) /* Pre-GLK */
> >  #define   PLANE_CTL_KEY_ENABLE_MASK(0x3 << 21)
> >  #define   PLANE_CTL_KEY_ENABLE_SOURCE  (  1 << 21)
> >  #define   PLANE_CTL_KEY_ENABLE_DESTINATION (  2 << 21)
> > @@ -6286,13 +6286,13 @@ enum {
> >  #define   PLANE_CTL_YUV422_VYUY(  3 << 16)
> >  #define   PLANE_CTL_DECOMPRESSION_ENABLE   (1 << 15)
> >  #define   PLANE_CTL_TRICKLE_FEED_DISABLE   (1 << 14)
> > -#define   PLANE_CTL_PLANE_GAMMA_DISABLE(1 << 13)
> > +#define   PLANE_CTL_PLANE_GAMMA_DISABLE(1 << 13) /* Pre-GLK */
> >  #define   PLANE_CTL_TILED_MASK (0x7 << 10)
> >  #define   PLANE_CTL_TILED_LINEAR   (  0 << 10)
> >  #define   PLANE_CTL_TILED_X(  1 << 10)
> >  #define   PLANE_CTL_TILED_Y(  4 << 10)
> >  #define   PLANE_CTL_TILED_YF   (  5 << 10)
> > -#define   PLANE_CTL_ALPHA_MASK (0x3 << 4)
> > +#define   PLANE_CTL_ALPHA_MASK (0x3 << 4) /* Pre-GLK */
> >  #define   PLANE_CTL_ALPHA_DISABLE  (  0 << 4)
> >  #define   PLANE_CTL_ALPHA_SW_PREMULTIPLY   (  2 << 4)
> >  #define   PLANE_CTL_ALPHA_HW_PREMULTIPLY   (  3 << 4)
> > @@ -6332,6 +6332,10 @@ enum {
> >  #define   PLANE_COLOR_PIPE_GAMMA_ENABLE(1 << 30)
> >  #define   PLANE_COLOR_PIPE_CSC_ENABLE  (1 << 23)
> >  #define   PLANE_COLOR_PLANE_GAMMA_DISABLE  (1 << 13)
> > +#define   PLANE_COLOR_ALPHA_MASK   (0x3 << 4)
> > +#define   PLANE_COLOR_ALPHA_DISABLE(0 << 4)
> > +#define   PLANE_COLOR_ALPHA_SW_PREMULTIPLY (2 << 4)
> > +#define   PLANE_COLOR_ALPHA_HW_PREMULTIPLY (3 << 4)
> >  #define _PLANE_BUF_CFG_1_A 0x7027c
> >  #define _PLANE_BUF_CFG_2_A 0x7037c
> >  #define _PLANE_NV12_BUF_CFG_1_A0x70278
> > diff --git a/drivers/gpu/drm/i915/intel_display.c 
> > b/drivers/gpu/drm/i915/intel_display.c
> > index e2ac976844d8..0883e857dda9 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -3466,6 +3466,29 @@ static u32 skl_plane_ctl_format(uint32_t 
> > pixel_format)
> > return 0;
> >  }
> >  
> > +static u32 glk_plane_ctl_format(uint32_t pixel_format)
> > +{
> > +   /* GLK+ moves the alpha mask to a different re

[Intel-gfx] [PATCH v2] drm/i915/glk: Refactor handling of PLANE_COLOR_CTL for GLK+

[James Ausmus]

Since GLK, some plane configuration settings have moved to the
PLANE_COLOR_CTL register. Refactor handling of the register to work like
PLANE_CTL. This also allows us to fix the set/read of the plane Alpha
Mode for GLK+.

v2: Adjust ordering of platform checks to be newest->oldest, drop
redundant comment about alpha blending. (Ville)

Signed-off-by: James Ausmus <james.aus...@intel.com>
Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  | 12 +---
 drivers/gpu/drm/i915/intel_display.c | 55 
 drivers/gpu/drm/i915/intel_drv.h |  5 
 drivers/gpu/drm/i915/intel_sprite.c  | 14 +
 4 files changed, 71 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f0f8f6059652..ecd6b236e005 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6263,7 +6263,7 @@ enum {
 #define _PLANE_CTL_2_A 0x70280
 #define _PLANE_CTL_3_A 0x70380
 #define   PLANE_CTL_ENABLE (1 << 31)
-#define   PLANE_CTL_PIPE_GAMMA_ENABLE  (1 << 30)
+#define   PLANE_CTL_PIPE_GAMMA_ENABLE  (1 << 30)   /* Pre-GLK */
 #define   PLANE_CTL_FORMAT_MASK(0xf << 24)
 #define   PLANE_CTL_FORMAT_YUV422  (  0 << 24)
 #define   PLANE_CTL_FORMAT_NV12(  1 << 24)
@@ -6273,7 +6273,7 @@ enum {
 #define   PLANE_CTL_FORMAT_AYUV(  8 << 24)
 #define   PLANE_CTL_FORMAT_INDEXED ( 12 << 24)
 #define   PLANE_CTL_FORMAT_RGB_565 ( 14 << 24)
-#define   PLANE_CTL_PIPE_CSC_ENABLE(1 << 23)
+#define   PLANE_CTL_PIPE_CSC_ENABLE(1 << 23) /* Pre-GLK */
 #define   PLANE_CTL_KEY_ENABLE_MASK(0x3 << 21)
 #define   PLANE_CTL_KEY_ENABLE_SOURCE  (  1 << 21)
 #define   PLANE_CTL_KEY_ENABLE_DESTINATION (  2 << 21)
@@ -6286,13 +6286,13 @@ enum {
 #define   PLANE_CTL_YUV422_VYUY(  3 << 16)
 #define   PLANE_CTL_DECOMPRESSION_ENABLE   (1 << 15)
 #define   PLANE_CTL_TRICKLE_FEED_DISABLE   (1 << 14)
-#define   PLANE_CTL_PLANE_GAMMA_DISABLE(1 << 13)
+#define   PLANE_CTL_PLANE_GAMMA_DISABLE(1 << 13) /* Pre-GLK */
 #define   PLANE_CTL_TILED_MASK (0x7 << 10)
 #define   PLANE_CTL_TILED_LINEAR   (  0 << 10)
 #define   PLANE_CTL_TILED_X(  1 << 10)
 #define   PLANE_CTL_TILED_Y(  4 << 10)
 #define   PLANE_CTL_TILED_YF   (  5 << 10)
-#define   PLANE_CTL_ALPHA_MASK (0x3 << 4)
+#define   PLANE_CTL_ALPHA_MASK (0x3 << 4) /* Pre-GLK */
 #define   PLANE_CTL_ALPHA_DISABLE  (  0 << 4)
 #define   PLANE_CTL_ALPHA_SW_PREMULTIPLY   (  2 << 4)
 #define   PLANE_CTL_ALPHA_HW_PREMULTIPLY   (  3 << 4)
@@ -6332,6 +6332,10 @@ enum {
 #define   PLANE_COLOR_PIPE_GAMMA_ENABLE(1 << 30)
 #define   PLANE_COLOR_PIPE_CSC_ENABLE  (1 << 23)
 #define   PLANE_COLOR_PLANE_GAMMA_DISABLE  (1 << 13)
+#define   PLANE_COLOR_ALPHA_MASK   (0x3 << 4)
+#define   PLANE_COLOR_ALPHA_DISABLE(0 << 4)
+#define   PLANE_COLOR_ALPHA_SW_PREMULTIPLY (2 << 4)
+#define   PLANE_COLOR_ALPHA_HW_PREMULTIPLY (3 << 4)
 #define _PLANE_BUF_CFG_1_A 0x7027c
 #define _PLANE_BUF_CFG_2_A 0x7037c
 #define _PLANE_NV12_BUF_CFG_1_A0x70278
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 737de251d0f8..39453276dad1 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3466,6 +3466,23 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
return 0;
 }
 
+static u32 glk_plane_ctl_format(uint32_t pixel_format)
+{
+   /* GLK+ moves the alpha mask to a different register */
+   return skl_plane_ctl_format(pixel_format) & ~PLANE_CTL_ALPHA_MASK;
+}
+
+static u32 glk_plane_color_ctl_alpha(uint32_t pixel_format)
+{
+   switch (pixel_format) {
+   case DRM_FORMAT_ABGR:
+   case DRM_FORMAT_ARGB:
+   return PLANE_COLOR_ALPHA_SW_PREMULTIPLY;
+   default:
+   return PLANE_COLOR_ALPHA_DISABLE;
+   }
+}
+
 static u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
 {
switch (fb_modifier) {
@@ -3522,14 +3539,16 @@ u32 skl_plane_ctl(const struct intel_crtc_state 
*crtc_state,
 
plane_ctl = PLANE_CTL_ENABLE;
 
-   if (!IS_GEMINILAKE(dev_priv) && !IS_CANNONLAKE(