On Thu, Feb 22, 2018 at 12:55:06AM -0300, Paulo Zanoni wrote: > Just use the hardcoded tables provided by our spec. > > v2: Rebase. > > Signed-off-by: Paulo Zanoni <[email protected]> > --- > drivers/gpu/drm/i915/intel_dpll_mgr.c | 86 > ++++++++++++++++++++++++++++++++++- > 1 file changed, 85 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c > b/drivers/gpu/drm/i915/intel_dpll_mgr.c > index 4d9265d14661..5d7bacc80688 100644 > --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c > +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c > @@ -2389,6 +2389,90 @@ static const struct intel_dpll_mgr cnl_pll_mgr = { > .dump_hw_state = cnl_dump_hw_state, > }; > > +/* > + * These values alrea already adjusted: they're the bits we write to the > + * registers, not the logical values. > + */ > +static const struct skl_wrpll_params icl_dp_combo_pll_24MHz_values[] = { > + { .dco_integer = 0x151, .dco_fraction = 0x4000, /* [0]: 5.4 */ > + .pdiv = 0x2 /* 3 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0}, > + { .dco_integer = 0x151, .dco_fraction = 0x4000, /* [1]: 2.7 */ > + .pdiv = 0x2 /* 3 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0}, > + { .dco_integer = 0x151, .dco_fraction = 0x4000, /* [2]: 1.62 */ > + .pdiv = 0x4 /* 5 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0}, > + { .dco_integer = 0x151, .dco_fraction = 0x4000, /* [3]: 3.24 */ > + .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0}, > + { .dco_integer = 0x168, .dco_fraction = 0x0000, /* [4]: 2.16 */ > + .pdiv = 0x1 /* 2 */, .kdiv = 2, .qdiv_mode = 1, .qdiv_ratio = 2}, > + { .dco_integer = 0x168, .dco_fraction = 0x0000, /* [5]: 4.32 */ > + .pdiv = 0x1 /* 2 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0}, > + { .dco_integer = 0x195, .dco_fraction = 0x0000, /* [6]: 6.48 */ > + .pdiv = 0x2 /* 3 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0}, > + { .dco_integer = 0x151, .dco_fraction = 0x4000, /* [7]: 8.1 */ > + .pdiv = 0x1 /* 2 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0}, > +}; > +
Maybe: /* Also used for 38.4MHz values */ Either way - Reviewed-by: James Ausmus <[email protected]> > +static const struct skl_wrpll_params icl_dp_combo_pll_19_2MHz_values[] = { > + { .dco_integer = 0x1A5, .dco_fraction = 0x7000, /* [0]: 5.4 */ > + .pdiv = 0x2 /* 3 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0}, > + { .dco_integer = 0x1A5, .dco_fraction = 0x7000, /* [1]: 2.7 */ > + .pdiv = 0x2 /* 3 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0}, > + { .dco_integer = 0x1A5, .dco_fraction = 0x7000, /* [2]: 1.62 */ > + .pdiv = 0x4 /* 5 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0}, > + { .dco_integer = 0x1A5, .dco_fraction = 0x7000, /* [3]: 3.24 */ > + .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0}, > + { .dco_integer = 0x1C2, .dco_fraction = 0x0000, /* [4]: 2.16 */ > + .pdiv = 0x1 /* 2 */, .kdiv = 2, .qdiv_mode = 1, .qdiv_ratio = 2}, > + { .dco_integer = 0x1C2, .dco_fraction = 0x0000, /* [5]: 4.32 */ > + .pdiv = 0x1 /* 2 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0}, > + { .dco_integer = 0x1FA, .dco_fraction = 0x2000, /* [6]: 6.48 */ > + .pdiv = 0x2 /* 3 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0}, > + { .dco_integer = 0x1A5, .dco_fraction = 0x7000, /* [7]: 8.1 */ > + .pdiv = 0x1 /* 2 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0}, > +}; > + > +static bool icl_calc_dp_combo_pll(struct drm_i915_private *dev_priv, int > clock, > + struct skl_wrpll_params *pll_params) > +{ > + const struct skl_wrpll_params *params; > + > + params = dev_priv->cdclk.hw.ref == 24000 ? > + icl_dp_combo_pll_24MHz_values : > + icl_dp_combo_pll_19_2MHz_values; > + > + switch (clock) { > + case 540000: > + *pll_params = params[0]; > + break; > + case 270000: > + *pll_params = params[1]; > + break; > + case 162000: > + *pll_params = params[2]; > + break; > + case 324000: > + *pll_params = params[3]; > + break; > + case 216000: > + *pll_params = params[4]; > + break; > + case 432000: > + *pll_params = params[5]; > + break; > + case 648000: > + *pll_params = params[6]; > + break; > + case 810000: > + *pll_params = params[7]; > + break; > + default: > + MISSING_CASE(clock); > + return false; > + } > + > + return true; > +} > + > static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state, > struct intel_encoder *encoder, int clock, > struct intel_dpll_hw_state *pll_state) > @@ -2401,7 +2485,7 @@ static bool icl_calc_dpll_state(struct intel_crtc_state > *crtc_state, > if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) > ret = cnl_ddi_calculate_wrpll(clock, dev_priv, &pll_params); > else > - ret = false; /* TODO */ > + ret = icl_calc_dp_combo_pll(dev_priv, clock, &pll_params); > > if (!ret) > return false; > -- > 2.14.3 > > _______________________________________________ > Intel-gfx mailing list > [email protected] > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
