RE: [PATCH v6 3/6] drm/display: Add missing aux less alpm wake related bits
+ drm-core maintainer Hi, Could you please have a look and ack this patch. Received r-b from Jouni on 0th patch for the whole patch series. Regards, Animesh > -Original Message- > From: Intel-gfx On Behalf Of > Animesh Manna > Sent: Monday, May 27, 2024 1:57 PM > To: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org > Cc: Nikula, Jani ; Hogander, Jouni > ; Murthy, Arun R > Subject: [PATCH v6 3/6] drm/display: Add missing aux less alpm wake related > bits > > From: Jouni Högander > > eDP1.5 adds some more bits into DP_RECEIVER_ALPM_CAP and > DP_RECEIVER_ALPM_CONFIG registers. Add definitions for these. > > Signed-off-by: Jouni Högander > --- > include/drm/display/drm_dp.h | 5 - > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h > index 906949ca3cee..3317ff88ed59 100644 > --- a/include/drm/display/drm_dp.h > +++ b/include/drm/display/drm_dp.h > @@ -232,6 +232,8 @@ > > #define DP_RECEIVER_ALPM_CAP 0x02e /* eDP 1.4 */ > # define DP_ALPM_CAP (1 << 0) > +# define DP_ALPM_PM_STATE_2A_SUPPORT (1 << 1) /* eDP 1.5 */ > +# define DP_ALPM_AUX_LESS_CAP(1 << 2) /* eDP 1.5 */ > > #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f /* eDP 1.4 */ > # define DP_AUX_FRAME_SYNC_CAP (1 << 0) > @@ -683,7 +685,8 @@ > > #define DP_RECEIVER_ALPM_CONFIG 0x116 /* eDP 1.4 */ > # define DP_ALPM_ENABLE (1 << 0) > -# define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1) > +# define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1) /* eDP 1.5 */ > +# define DP_ALPM_MODE_AUX_LESS (1 << 2) /* eDP 1.5 */ > > #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117 /* eDP 1.4 */ > # define DP_AUX_FRAME_SYNC_ENABLE(1 << 0) > -- > 2.29.0
RE: [PATCH v3 05/20] drm/i915/psr: modify psr status debugfs to support eDP Panel Replay
> -Original Message-
> From: Hogander, Jouni
> Sent: Monday, May 27, 2024 12:52 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Kahola, Mika
> ; Hogander, Jouni
> Subject: [PATCH v3 05/20] drm/i915/psr: modify psr status debugfs to
> support eDP Panel Replay
>
> Some PSR2_CTL bits are applicable for eDP panel replay as well.
> Dump this register for eDP Panel Replay as well.
>
> Bspec: 68920
>
> Signed-off-by: Jouni Högander
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 11 ++-
> 1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index dfd45f6d7edd..19f8ac12f995 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -3628,7 +3628,7 @@ static int intel_psr_status(struct seq_file *m, struct
> intel_dp *intel_dp)
> struct intel_psr *psr = _dp->psr;
> intel_wakeref_t wakeref;
> bool enabled;
> - u32 val;
> + u32 val, psr2_ctl;
>
> intel_psr_sink_capability(intel_dp, m);
>
> @@ -3649,6 +3649,12 @@ static int intel_psr_status(struct seq_file *m,
> struct intel_dp *intel_dp)
>
> if (psr->panel_replay_enabled) {
> val = intel_de_read(dev_priv,
> TRANS_DP2_CTL(cpu_transcoder));
> +
> + if (intel_dp_is_edp(intel_dp))
> + psr2_ctl = intel_de_read(dev_priv,
> + EDP_PSR2_CTL(dev_priv,
> + cpu_transcoder));
> +
> enabled = val & TRANS_DP2_PANEL_REPLAY_ENABLE;
> } else if (psr->sel_update_enabled) {
> val = intel_de_read(dev_priv,
> @@ -3660,6 +3666,9 @@ static int intel_psr_status(struct seq_file *m, struct
> intel_dp *intel_dp)
> }
> seq_printf(m, "Source PSR/PanelReplay ctl: %s [0x%08x]\n",
> str_enabled_disabled(enabled), val);
> + if (psr->panel_replay_enabled && intel_dp_is_edp(intel_dp))
> + seq_printf(m, "PSR2_CTL: 0x%08x\n",
> +psr2_ctl);
Just a nitpick: A code comment describing the bitfield of PSR2_CTL register
used for validation will be helpful from code readability pov. The same maybe
applicable for psr-ctl as well.
With or without above fix.
Reviewed-by: Animesh Manna
Regards,
Animesh
> psr_source_status(intel_dp, m);
> seq_printf(m, "Busy frontbuffer bits: 0x%08x\n",
> psr->busy_frontbuffer_bits);
> --
> 2.34.1
RE: [PATCH v3 04/20] drm/i915/psr: Move printing PSR mode to own function
> -Original Message-
> From: Hogander, Jouni
> Sent: Monday, May 27, 2024 12:52 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Kahola, Mika
> ; Hogander, Jouni
> Subject: [PATCH v3 04/20] drm/i915/psr: Move printing PSR mode to own
> function
>
> intel_psr_status has grown and is about to grow even. Let's split it a bit and
> move printing PSR mode to an own function.
>
> v2: s/intel_psr_psr_mode/intel_psr_print_mode/
>
> Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 26
> 1 file changed, 17 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 943de3ca39c2..dfd45f6d7edd 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -3605,13 +3605,28 @@ static void intel_psr_sink_capability(struct
> intel_dp *intel_dp,
> str_yes_no(psr->sink_panel_replay_su_support));
> }
>
> +static void intel_psr_print_mode(struct intel_dp *intel_dp,
> + struct seq_file *m)
> +{
> + struct intel_psr *psr = _dp->psr;
> + const char *status;
> +
> + if (psr->panel_replay_enabled)
> + status = psr->sel_update_enabled ? "Panel Replay Selective
> Update Enabled" :
> + "Panel Replay Enabled";
> + else if (psr->enabled)
> + status = psr->sel_update_enabled ? "PSR2" : "PSR1";
> + else
> + status = "disabled";
> + seq_printf(m, "PSR mode: %s\n", status); }
> +
> static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp) {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
> struct intel_psr *psr = _dp->psr;
> intel_wakeref_t wakeref;
> - const char *status;
> bool enabled;
> u32 val;
>
> @@ -3623,14 +3638,7 @@ static int intel_psr_status(struct seq_file *m,
> struct intel_dp *intel_dp)
> wakeref = intel_runtime_pm_get(_priv->runtime_pm);
> mutex_lock(>lock);
>
> - if (psr->panel_replay_enabled)
> - status = psr->sel_update_enabled ? "Panel Replay Selective
> Update Enabled" :
> - "Panel Replay Enabled";
> - else if (psr->enabled)
> - status = psr->sel_update_enabled ? "PSR2" : "PSR1";
> - else
> - status = "disabled";
> - seq_printf(m, "PSR mode: %s\n", status);
> + intel_psr_print_mode(intel_dp, m);
>
> if (!psr->enabled) {
> seq_printf(m, "PSR sink not reliable: %s\n",
> --
> 2.34.1
RE: [PATCH v3 03/20] drm/i915/psr: Move printing sink PSR support to own function
> -Original Message-
> From: Hogander, Jouni
> Sent: Monday, May 27, 2024 12:52 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Kahola, Mika
> ; Hogander, Jouni
> Subject: [PATCH v3 03/20] drm/i915/psr: Move printing sink PSR support to
> own function
>
> intel_psr_status has grown and is about to grow even. Let's split it a bit and
> move printing sink psr support to an own function.
>
> Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 22 +++---
> 1 file changed, 15 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 08d3c8c81585..943de3ca39c2 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -3590,15 +3590,10 @@ psr_source_status(struct intel_dp *intel_dp,
> struct seq_file *m)
> seq_printf(m, "Source PSR/PanelReplay status: %s [0x%08x]\n",
> status, val); }
>
> -static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp)
> +static void intel_psr_sink_capability(struct intel_dp *intel_dp,
> + struct seq_file *m)
> {
> - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
> struct intel_psr *psr = _dp->psr;
> - intel_wakeref_t wakeref;
> - const char *status;
> - bool enabled;
> - u32 val;
>
> seq_printf(m, "Sink support: PSR = %s",
> str_yes_no(psr->sink_support));
> @@ -3608,6 +3603,19 @@ static int intel_psr_status(struct seq_file *m,
> struct intel_dp *intel_dp)
> seq_printf(m, ", Panel Replay = %s", str_yes_no(psr-
> >sink_panel_replay_support));
> seq_printf(m, ", Panel Replay Selective Update = %s\n",
> str_yes_no(psr->sink_panel_replay_su_support));
> +}
> +
> +static int intel_psr_status(struct seq_file *m, struct intel_dp
> +*intel_dp) {
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
> + struct intel_psr *psr = _dp->psr;
> + intel_wakeref_t wakeref;
> + const char *status;
> + bool enabled;
> + u32 val;
> +
> + intel_psr_sink_capability(intel_dp, m);
>
> if (!(psr->sink_support || psr->sink_panel_replay_support))
> return 0;
> --
> 2.34.1
RE: [PATCH v3 02/20] drm/panel replay: Add edp1.5 Panel Replay bits and register
> -Original Message- > From: Hogander, Jouni > Sent: Monday, May 27, 2024 12:52 PM > To: intel-gfx@lists.freedesktop.org > Cc: Manna, Animesh ; Kahola, Mika > ; Hogander, Jouni > Subject: [PATCH v3 02/20] drm/panel replay: Add edp1.5 Panel Replay bits > and register > > Add PANEL_REPLAY_CONFIGURATION_2 register and some missing Panel > Replay bits. > > Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna > --- > include/drm/display/drm_dp.h | 16 +--- > 1 file changed, 13 insertions(+), 3 deletions(-) > > diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h > index 906949ca3cee..79bde372b152 100644 > --- a/include/drm/display/drm_dp.h > +++ b/include/drm/display/drm_dp.h > @@ -544,9 +544,10 @@ > /* DFP Capability Extension */ > #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ > > -#define DP_PANEL_REPLAY_CAP 0x0b0 /* DP 2.0 */ > -# define DP_PANEL_REPLAY_SUPPORT(1 << 0) > -# define DP_PANEL_REPLAY_SU_SUPPORT (1 << 1) > +#define DP_PANEL_REPLAY_CAP 0x0b0 /* DP > 2.0 */ > +# define DP_PANEL_REPLAY_SUPPORT (1 << 0) > +# define DP_PANEL_REPLAY_SU_SUPPORT (1 << 1) > +# define DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT (1 << 2) /* > eDP 1.5 */ > > #define DP_PANEL_PANEL_REPLAY_CAPABILITY 0xb1 > # define DP_PANEL_PANEL_REPLAY_SU_GRANULARITY_REQUIRED (1 << > 5) > @@ -734,11 +735,20 @@ > > #define PANEL_REPLAY_CONFIG 0x1b0 /* DP 2.0 */ > # define DP_PANEL_REPLAY_ENABLE (1 << 0) > +# define DP_PANEL_REPLAY_VSC_SDP_CRC_EN (1 << 1) /* eDP 1.5 > */ > # define DP_PANEL_REPLAY_UNRECOVERABLE_ERROR_EN (1 << 3) > # define DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN (1 << 4) > # define DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN (1 << 5) > # define DP_PANEL_REPLAY_SU_ENABLE (1 << 6) > > +#define PANEL_REPLAY_CONFIG2 0x1b1 /* > eDP 1.5 */ > +# define DP_PANEL_REPLAY_SINK_REFRESH_RATE_UNLOCK_GRANTED >(1 << 0) > +# define DP_PANEL_REPLAY_CRC_VERIFICATION (1 << > 1) > +# define DP_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_EN >(1 << 2) > +# define > DP_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_VAL_SEL_SHIFT 3 # > +define DP_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_VAL_SEL_MASK > (0xf << 3) > +# define DP_PANEL_REPLAY_SU_REGION_SCANLINE_CAPTURE >(1 << 7) > + > #define DP_PAYLOAD_ALLOCATE_SET 0x1c0 > #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1 #define > DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2 > -- > 2.34.1
RE: [PATCH v3 01/20] drm/i915/psr: Store pr_dpcd in intel_dp
> -Original Message-
> From: Hogander, Jouni
> Sent: Monday, May 27, 2024 12:52 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Kahola, Mika
> ; Hogander, Jouni
> Subject: [PATCH v3 01/20] drm/i915/psr: Store pr_dpcd in intel_dp
>
> We need pr_dpcd contents for early transport validity check on eDP Panel
> Replay and in debugfs interface to dump out panel early transport capability.
> Also remove unnecessarily printing out "Panel replay is not supported by
> panel"
>
> v2: commit message modified
>
> Signed-off-by: Jouni Högander
LGTM.
Reviewed-by: Animesh Manna
> ---
> .../drm/i915/display/intel_display_types.h| 1 +
> drivers/gpu/drm/i915/display/intel_psr.c | 19 ++-
> 2 files changed, 7 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 9678c2b157f6..6fbfe8a18f45 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1743,6 +1743,7 @@ struct intel_dp {
> bool use_max_params;
> u8 dpcd[DP_RECEIVER_CAP_SIZE];
> u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
> + u8 pr_dpcd;
> u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
> u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
> u8 lttpr_common_caps[DP_LTTPR_COMMON_CAP_SIZE];
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index f59238d3d484..08d3c8c81585 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -559,20 +559,10 @@ static void intel_dp_get_su_granularity(struct
> intel_dp *intel_dp) static void _panel_replay_init_dpcd(struct intel_dp
> *intel_dp) {
> struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> - u8 pr_dpcd = 0;
> -
> - intel_dp->psr.sink_panel_replay_support = false;
> - drm_dp_dpcd_readb(_dp->aux, DP_PANEL_REPLAY_CAP,
> _dpcd);
> -
> - if (!(pr_dpcd & DP_PANEL_REPLAY_SUPPORT)) {
> - drm_dbg_kms(>drm,
> - "Panel replay is not supported by panel\n");
> - return;
> - }
>
> intel_dp->psr.sink_panel_replay_support = true;
>
> - if (pr_dpcd & DP_PANEL_REPLAY_SU_SUPPORT)
> + if (intel_dp->pr_dpcd & DP_PANEL_REPLAY_SU_SUPPORT)
> intel_dp->psr.sink_panel_replay_su_support = true;
>
> drm_dbg_kms(>drm,
> @@ -630,10 +620,13 @@ static void _psr_init_dpcd(struct intel_dp
> *intel_dp)
>
> void intel_psr_init_dpcd(struct intel_dp *intel_dp) {
> - _panel_replay_init_dpcd(intel_dp);
> -
> drm_dp_dpcd_read(_dp->aux, DP_PSR_SUPPORT, intel_dp-
> >psr_dpcd,
>sizeof(intel_dp->psr_dpcd));
> + drm_dp_dpcd_readb(_dp->aux, DP_PANEL_REPLAY_CAP,
> + _dp->pr_dpcd);
> +
> + if (intel_dp->pr_dpcd & DP_PANEL_REPLAY_SUPPORT)
> + _panel_replay_init_dpcd(intel_dp);
>
> if (intel_dp->psr_dpcd[0])
> _psr_init_dpcd(intel_dp);
> --
> 2.34.1
RE: [PATCH v2 01/17] drm/i915/psr: Store pr_dpcd in intel_dp
> -Original Message-
> From: Hogander, Jouni
> Sent: Friday, May 24, 2024 11:49 AM
> To: Manna, Animesh ; intel-
> g...@lists.freedesktop.org
> Cc: Kahola, Mika
> Subject: Re: [PATCH v2 01/17] drm/i915/psr: Store pr_dpcd in intel_dp
>
> On Fri, 2024-05-24 at 05:55 +, Manna, Animesh wrote:
> >
> >
> > > -Original Message-
> > > From: Hogander, Jouni
> > > Sent: Tuesday, May 21, 2024 2:17 PM
> > > To: intel-gfx@lists.freedesktop.org
> > > Cc: Manna, Animesh ; Kahola, Mika
> > > ; Hogander, Jouni
> > > Subject: [PATCH v2 01/17] drm/i915/psr: Store pr_dpcd in intel_dp
> > >
> > > We need pr_dpcd contents for early transport validity check on eDP
> > > Panel Replay and in debugfs interface to dump out panel early
> > > transport capability.
> > >
> > > Signed-off-by: Jouni Högander
> > > ---
> > > .../drm/i915/display/intel_display_types.h | 1 +
> > > drivers/gpu/drm/i915/display/intel_psr.c | 19 ++-
> > >
> > > 2 files changed, 7 insertions(+), 13 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index 9678c2b157f6..6fbfe8a18f45 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > @@ -1743,6 +1743,7 @@ struct intel_dp {
> > > bool use_max_params;
> > > u8 dpcd[DP_RECEIVER_CAP_SIZE];
> > > u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
> > > + u8 pr_dpcd;
> > > u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
> > > u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
> > > u8 lttpr_common_caps[DP_LTTPR_COMMON_CAP_SIZE];
> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > index d18baeb971bb..ba92f71b82d9 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > @@ -559,20 +559,10 @@ static void
> > > intel_dp_get_su_granularity(struct
> > > intel_dp *intel_dp) static void _panel_replay_init_dpcd(struct
> > > intel_dp
> > > *intel_dp) {
> > > struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> > > - u8 pr_dpcd = 0;
> > > -
> > > - intel_dp->psr.sink_panel_replay_support = false;
> > > - drm_dp_dpcd_readb(_dp->aux, DP_PANEL_REPLAY_CAP,
> > > _dpcd);
> > > -
> > > - if (!(pr_dpcd & DP_PANEL_REPLAY_SUPPORT)) {
> > > - drm_dbg_kms(>drm,
> > > - "Panel replay is not supported by
> > > panel\n");
> >
> > Panel Replat not supported print are we removing purposefully or
> > missed somehow in refactoring?
>
> I removed it purposefully. We do not have that for PSR either. I don't see
> that
> as a reasonable to printout what features panel is not supporting. Having
> debug printout saying if it's supported is enough to my opinion. Do you agree
> or do you want to keep it?
Ok for me .. maybe good to mention in commit description.
Regards,
Animesh
>
> BR,
>
> Jouni Högander
> >
> > Regards,
> > Animesh
> > > - return;
> > > - }
> > >
> > > intel_dp->psr.sink_panel_replay_support = true;
> > >
> > > - if (pr_dpcd & DP_PANEL_REPLAY_SU_SUPPORT)
> > > + if (intel_dp->pr_dpcd & DP_PANEL_REPLAY_SU_SUPPORT)
> > > intel_dp->psr.sink_panel_replay_su_support = true;
> > >
> > > drm_dbg_kms(>drm,
> > > @@ -630,10 +620,13 @@ static void _psr_init_dpcd(struct intel_dp
> > > *intel_dp)
> > >
> > > void intel_psr_init_dpcd(struct intel_dp *intel_dp) {
> > > - _panel_replay_init_dpcd(intel_dp);
> > > -
> > > drm_dp_dpcd_read(_dp->aux, DP_PSR_SUPPORT, intel_dp-
> > > > psr_dpcd,
> > > sizeof(intel_dp->psr_dpcd));
> > > + drm_dp_dpcd_readb(_dp->aux, DP_PANEL_REPLAY_CAP,
> > > + _dp->pr_dpcd);
> > > +
> > > + if (intel_dp->pr_dpcd & DP_PANEL_REPLAY_SUPPORT)
> > > + _panel_replay_init_dpcd(intel_dp);
> > >
> > > if (intel_dp->psr_dpcd[0])
> > > _psr_init_dpcd(intel_dp);
> > > --
> > > 2.34.1
> >
RE: [PATCH v2 04/17] drm/i915/psr: Move printing PSR mode to own function
> -Original Message-
> From: Hogander, Jouni
> Sent: Tuesday, May 21, 2024 2:17 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Kahola, Mika
> ; Hogander, Jouni
> Subject: [PATCH v2 04/17] drm/i915/psr: Move printing PSR mode to own
> function
>
> intel_psr_status has grown and is about to grow even. Let's split it a bit
> and move printing PSR mode to an own function.
>
> Signed-off-by: Jouni Högander
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 26
> 1 file changed, 17 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 2ae5cdca5786..de0ce5f3a32c 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -3605,13 +3605,28 @@ static void intel_psr_sink_capability(struct
> intel_dp *intel_dp,
> str_yes_no(psr->sink_panel_replay_su_support));
> }
>
> +static void intel_psr_psr_mode(struct intel_dp *intel_dp,
> +struct seq_file *m)
psr kerword repeating twice, how about intel_psr_print_mode()?
Regards,
Animesh
> +{
> + struct intel_psr *psr = _dp->psr;
> + const char *status;
> +
> + if (psr->panel_replay_enabled)
> + status = psr->sel_update_enabled ? "Panel Replay Selective
> Update Enabled" :
> + "Panel Replay Enabled";
> + else if (psr->enabled)
> + status = psr->sel_update_enabled ? "PSR2" : "PSR1";
> + else
> + status = "disabled";
> + seq_printf(m, "PSR mode: %s\n", status);
> +}
> +
> static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
> struct intel_psr *psr = _dp->psr;
> intel_wakeref_t wakeref;
> - const char *status;
> bool enabled;
> u32 val;
>
> @@ -3623,14 +3638,7 @@ static int intel_psr_status(struct seq_file *m,
> struct intel_dp *intel_dp)
> wakeref = intel_runtime_pm_get(_priv->runtime_pm);
> mutex_lock(>lock);
>
> - if (psr->panel_replay_enabled)
> - status = psr->sel_update_enabled ? "Panel Replay Selective
> Update Enabled" :
> - "Panel Replay Enabled";
> - else if (psr->enabled)
> - status = psr->sel_update_enabled ? "PSR2" : "PSR1";
> - else
> - status = "disabled";
> - seq_printf(m, "PSR mode: %s\n", status);
> + intel_psr_psr_mode(intel_dp, m);
>
> if (!psr->enabled) {
> seq_printf(m, "PSR sink not reliable: %s\n",
> --
> 2.34.1
RE: [PATCH v2 01/17] drm/i915/psr: Store pr_dpcd in intel_dp
> -Original Message-
> From: Hogander, Jouni
> Sent: Tuesday, May 21, 2024 2:17 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Kahola, Mika
> ; Hogander, Jouni
> Subject: [PATCH v2 01/17] drm/i915/psr: Store pr_dpcd in intel_dp
>
> We need pr_dpcd contents for early transport validity check on eDP Panel
> Replay and in debugfs interface to dump out panel early transport capability.
>
> Signed-off-by: Jouni Högander
> ---
> .../drm/i915/display/intel_display_types.h| 1 +
> drivers/gpu/drm/i915/display/intel_psr.c | 19 ++-
> 2 files changed, 7 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 9678c2b157f6..6fbfe8a18f45 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1743,6 +1743,7 @@ struct intel_dp {
> bool use_max_params;
> u8 dpcd[DP_RECEIVER_CAP_SIZE];
> u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
> + u8 pr_dpcd;
> u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
> u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
> u8 lttpr_common_caps[DP_LTTPR_COMMON_CAP_SIZE];
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index d18baeb971bb..ba92f71b82d9 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -559,20 +559,10 @@ static void intel_dp_get_su_granularity(struct
> intel_dp *intel_dp) static void _panel_replay_init_dpcd(struct intel_dp
> *intel_dp) {
> struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> - u8 pr_dpcd = 0;
> -
> - intel_dp->psr.sink_panel_replay_support = false;
> - drm_dp_dpcd_readb(_dp->aux, DP_PANEL_REPLAY_CAP,
> _dpcd);
> -
> - if (!(pr_dpcd & DP_PANEL_REPLAY_SUPPORT)) {
> - drm_dbg_kms(>drm,
> - "Panel replay is not supported by panel\n");
Panel Replat not supported print are we removing purposefully or missed somehow
in refactoring?
Regards,
Animesh
> - return;
> - }
>
> intel_dp->psr.sink_panel_replay_support = true;
>
> - if (pr_dpcd & DP_PANEL_REPLAY_SU_SUPPORT)
> + if (intel_dp->pr_dpcd & DP_PANEL_REPLAY_SU_SUPPORT)
> intel_dp->psr.sink_panel_replay_su_support = true;
>
> drm_dbg_kms(>drm,
> @@ -630,10 +620,13 @@ static void _psr_init_dpcd(struct intel_dp
> *intel_dp)
>
> void intel_psr_init_dpcd(struct intel_dp *intel_dp) {
> - _panel_replay_init_dpcd(intel_dp);
> -
> drm_dp_dpcd_read(_dp->aux, DP_PSR_SUPPORT, intel_dp-
> >psr_dpcd,
>sizeof(intel_dp->psr_dpcd));
> + drm_dp_dpcd_readb(_dp->aux, DP_PANEL_REPLAY_CAP,
> + _dp->pr_dpcd);
> +
> + if (intel_dp->pr_dpcd & DP_PANEL_REPLAY_SUPPORT)
> + _panel_replay_init_dpcd(intel_dp);
>
> if (intel_dp->psr_dpcd[0])
> _psr_init_dpcd(intel_dp);
> --
> 2.34.1
RE: [PATCH v2 00/17] Panel Replay eDP support
> -Original Message- > From: Hogander, Jouni > Sent: Tuesday, May 21, 2024 2:17 PM > To: intel-gfx@lists.freedesktop.org > Cc: Manna, Animesh ; Kahola, Mika > ; Hogander, Jouni > Subject: [PATCH v2 00/17] Panel Replay eDP support > > This patch set is implementing eDP1.5 Panel Replay for Intel hw. Also Region > Early Transport information is added into debugfs interface and patch to > disable Region Early Transport by default is reverted as it is needed by eDP > Panel Replay. > > v2: > - printout "Selective Update enabled (Early Transport)" instead of > "Selective Update Early Transport enabled" > - ensure that fastset is performed when the disable bit changes > > Jouni Högander (17): > drm/i915/psr: Store pr_dpcd in intel_dp > drm/panel replay: Add edp1.5 Panel Replay bits and register > drm/i915/psr: Move printing sink PSR support to own function > drm/i915/psr: Move printing PSR mode to own function > drm/i915/psr: modify psr status debugfs to support eDP Panel Replay > drm/i915/psr: Add Panel Replay support to intel_psr2_config_et_valid > drm/i915/psr: Add Early Transport into psr debugfs interface > drm/display: Add missing aux less alpm wake related bits > drm/i915/psr: Check panel ALPM capability for eDP Panel Replay > drm/i915/psr: Inform Panel Replay source support on eDP as well > drm/i915/psr: enable sink for eDP1.5 Panel Replay > drm/i915/psr: Check panel Early Transport capability for eDP PR > drm/i915/psr: Perfrom psr2 checks related to ALPM for Panel Replay > drm/i915/psr: Check Early Transport for Panel Replay as well > drm/i915/psr: Modify dg2_activate_panel_replay to support eDP > drm/i915/psr: Add new debug bit to disable Panel Replay > Revert "drm/i915/psr: Disable early transport by default" Some restrictions we may have to add for before enabling eDP Panel Replay. 1. With HDCP enable cannot enable panel replay. 2. With 8b/10b encoding only panel replay can be supported, not for 128b/132b encoding. Regards, Animesh > > .../drm/i915/display/intel_display_types.h| 2 + > drivers/gpu/drm/i915/display/intel_psr.c | 294 -- > include/drm/display/drm_dp.h | 19 +- > 3 files changed, 213 insertions(+), 102 deletions(-) > > -- > 2.34.1
RE: [PATCH v4 4/6] drm/i915/alpm: Add compute config for lobf
> -Original Message-
> From: Hogander, Jouni
> Sent: Monday, May 13, 2024 1:02 PM
> To: Manna, Animesh ; intel-
> g...@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org; Murthy, Arun R
> ; Nikula, Jani
> Subject: Re: [PATCH v4 4/6] drm/i915/alpm: Add compute config for lobf
>
> On Thu, 2024-05-09 at 11:01 +0530, Animesh Manna wrote:
> > Link Off Between Active Frames, is a new feature for eDP that allows
> > the panel to go to lower power state after transmission of data. This
> > is a feature on top of ALPM, AS SDP.
> > Add compute config during atomic-check phase.
> >
> > v1: RFC version.
> > v2: Add separate flag for auxless-alpm. [Jani]
> > v3:
> > - intel_dp->lobf_supported replaced with crtc_state->has_lobf.
> > [Jouni]
> > - Add DISPLAY_VER() check. [Jouni]
> > - Modify function name of get_aux_less_status. [Jani]
> > v4: Add enum alpm_mode to hold the aux-wake/less capability.
> >
> > Signed-off-by: Animesh Manna
> > ---
> > drivers/gpu/drm/i915/display/intel_alpm.c | 58
> > +++
> > drivers/gpu/drm/i915/display/intel_alpm.h | 5 ++
> > .../drm/i915/display/intel_display_types.h | 11
> > drivers/gpu/drm/i915/display/intel_dp.c | 4 ++
> > 4 files changed, 78 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> > b/drivers/gpu/drm/i915/display/intel_alpm.c
> > index ee6c2a959f09..5979eab1f2e0 100644
> > --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> > +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> > @@ -11,6 +11,23 @@
> > #include "intel_dp_aux.h"
> > #include "intel_psr_regs.h"
> >
> > +enum alpm_mode intel_alpm_get_capability(struct intel_dp *intel_dp) {
> > + u8 alpm_caps = 0;
> > +
> > + if (drm_dp_dpcd_readb(_dp->aux, DP_RECEIVER_ALPM_CAP,
> > + _caps) != 1)
> > + return ALPM_INVALID;
> > +
> > + if (alpm_caps & DP_ALPM_CAP)
> > + return ALPM_AUX_WAKE;
> > +
> > + if (alpm_caps & DP_ALPM_AUX_LESS_CAP)
> > + return ALPM_AUX_LESS;
> > +
> > + return ALPM_NOT_SUPPORTED;
> > +}
>
> This will always return ALPM_AUX_WAKE if both are supported. I don't think
> this is what you want?
>
> You could add alpm_dpcd into intel_dp. Then for this purpose add
> aux_wake_supported() and aux_less_wake_supported()?
Ok, will add in next version.
Regards,
Animesh
>
> BR,
>
> Jouni Högander
>
> > +
> > /*
> > * See Bspec: 71632 for the table
> > *
> > @@ -242,6 +259,47 @@ bool intel_alpm_compute_params(struct intel_dp
> > *intel_dp,
> > return true;
> > }
> >
> > +void intel_alpm_compute_lobf_config(struct intel_dp *intel_dp,
> > + struct intel_crtc_state
> > *crtc_state,
> > + struct drm_connector_state
> > *conn_state)
> > +{
> > + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> > + struct drm_display_mode *adjusted_mode = _state-
> > >hw.adjusted_mode;
> > + int waketime_in_lines, first_sdp_position;
> > + int context_latency, guardband;
> > +
> > + if (!intel_dp_is_edp(intel_dp))
> > + return;
> > +
> > + if (DISPLAY_VER(i915) < 20)
> > + return;
> > +
> > + if (!intel_dp_as_sdp_supported(intel_dp))
> > + return;
> > +
> > + if (crtc_state->has_psr)
> > + return;
> > +
> > + if (intel_dp->alpm_parameters.mode == ALPM_INVALID ||
> > + intel_dp->alpm_parameters.mode == ALPM_NOT_SUPPORTED)
> > + return;
> > +
> > + if (!intel_alpm_compute_params(intel_dp, crtc_state))
> > + return;
> > +
> > + context_latency = adjusted_mode->crtc_vblank_start -
> > adjusted_mode->crtc_vdisplay;
> > + guardband = adjusted_mode->crtc_vtotal -
> > + adjusted_mode->crtc_vdisplay - context_latency;
> > + first_sdp_position = adjusted_mode->crtc_vtotal -
> > adjusted_mode->crtc_vsync_start;
> > + if (intel_dp->alpm_parameters.mode == ALPM_AUX_LESS)
> > + waketime_in_lines = intel_dp-
> > >alpm_parameters.io_wake_lines;
> > + else
> > + waketime_in_lines = intel_dp-
> > >alpm_parameters.fast_w
RE: [PATCH v10 08/12] drm/i915/psr: Panel replay uses SRD_STATUS to track it's status
> -Original Message-
> From: Hogander, Jouni
> Sent: Friday, May 10, 2024 3:08 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Hogander, Jouni
>
> Subject: [PATCH v10 08/12] drm/i915/psr: Panel replay uses SRD_STATUS to
> track it's status
>
> DP Panel replay uses SRD_STATUS to track it's status despite selective update
> mode.
>
> Bspec: 53370, 68920
>
> v4:
> - use PSR2_STATUS for eDP Panel Replay
> - handle intel_psr_wait_exit_locked as well
> v3:
> - do not use PSR2_STATUS for PSR1
> v2:
> - use intel_dp_is_edp to differentiate
> - modify debugfs status as well
>
> Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 20
> 1 file changed, 16 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 6d1f442f3d14..532a80a3eeea 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -2111,7 +2111,8 @@ static void intel_psr_wait_exit_locked(struct
> intel_dp *intel_dp)
> i915_reg_t psr_status;
> u32 psr_status_mask;
>
> - if (intel_dp->psr.sel_update_enabled) {
> + if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled
> ||
> + intel_dp-
> >psr.panel_replay_enabled)) {
> psr_status = EDP_PSR2_STATUS(dev_priv, cpu_transcoder);
> psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
> } else {
> @@ -2849,6 +2850,13 @@ static int
> _psr1_ready_for_pipe_update_locked(struct intel_dp *intel_dp)
> EDP_PSR_STATUS_STATE_MASK, 50); }
>
> +static int _panel_replay_ready_for_pipe_update_locked(struct intel_dp
> +*intel_dp) {
> + return intel_dp_is_edp(intel_dp) ?
> + _psr2_ready_for_pipe_update_locked(intel_dp) :
> + _psr1_ready_for_pipe_update_locked(intel_dp);
> +}
> +
> /**
> * intel_psr_wait_for_idle_locked - wait for PSR be ready for a pipe update
> * @new_crtc_state: new CRTC state
> @@ -2874,7 +2882,9 @@ void intel_psr_wait_for_idle_locked(const struct
> intel_crtc_state *new_crtc_stat
> if (!intel_dp->psr.enabled)
> continue;
>
> - if (intel_dp->psr.sel_update_enabled)
> + if (intel_dp->psr.panel_replay_enabled)
> + ret =
> _panel_replay_ready_for_pipe_update_locked(intel_dp);
> + else if (intel_dp->psr.sel_update_enabled)
> ret =
> _psr2_ready_for_pipe_update_locked(intel_dp);
> else
> ret =
> _psr1_ready_for_pipe_update_locked(intel_dp);
> @@ -2895,7 +2905,8 @@ static bool __psr_wait_for_idle_locked(struct
> intel_dp *intel_dp)
> if (!intel_dp->psr.enabled)
> return false;
>
> - if (intel_dp->psr.sel_update_enabled) {
> + if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled
> ||
> + intel_dp-
> >psr.panel_replay_enabled)) {
> reg = EDP_PSR2_STATUS(dev_priv, cpu_transcoder);
> mask = EDP_PSR2_STATUS_STATE_MASK;
> } else {
> @@ -3517,7 +3528,8 @@ psr_source_status(struct intel_dp *intel_dp, struct
> seq_file *m)
> const char *status = "unknown";
> u32 val, status_val;
>
> - if (intel_dp->psr.sel_update_enabled) {
> + if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled
> ||
> + intel_dp-
> >psr.panel_replay_enabled)) {
> static const char * const live_status[] = {
> "IDLE",
> "CAPTURE",
> --
> 2.34.1
RE: [PATCH v9 12/12] drm/i915/psr: Add panel replay sel update support to debugfs interface
> -Original Message- > From: Hogander, Jouni > Sent: Friday, May 3, 2024 12:04 PM > To: intel-gfx@lists.freedesktop.org > Cc: Manna, Animesh ; Hogander, Jouni > ; Joshi, Kunal1 > Subject: [PATCH v9 12/12] drm/i915/psr: Add panel replay sel update > support to debugfs interface > > Add panel replay selective update support to debugfs status interface. In > case of sink supporting panel replay we will print out: > > Sink support: PSR = no, Panel Replay = yes, Panel Replay Selective Update = > yes > > and PSR mode will look like this if printing out enabled panel replay > selective > update: > > PSR mode: Panel Replay Selective Update Enabled > > Current PSR and panel replay printouts remain same. > > Cc: Kunal Joshi > > Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna > --- > drivers/gpu/drm/i915/display/intel_psr.c | 9 ++--- > 1 file changed, 6 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > b/drivers/gpu/drm/i915/display/intel_psr.c > index 2198448fdb27..2ad7964998e0 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -3575,7 +3575,9 @@ static int intel_psr_status(struct seq_file *m, struct > intel_dp *intel_dp) > > if (psr->sink_support) > seq_printf(m, " [0x%02x]", intel_dp->psr_dpcd[0]); > - seq_printf(m, ", Panel Replay = %s\n", str_yes_no(psr- > >sink_panel_replay_support)); > + seq_printf(m, ", Panel Replay = %s", str_yes_no(psr- > >sink_panel_replay_support)); > + seq_printf(m, ", Panel Replay Selective Update = %s\n", > +str_yes_no(psr->sink_panel_replay_su_support)); > > if (!(psr->sink_support || psr->sink_panel_replay_support)) > return 0; > @@ -3584,9 +3586,10 @@ static int intel_psr_status(struct seq_file *m, > struct intel_dp *intel_dp) > mutex_lock(>lock); > > if (psr->panel_replay_enabled) > - status = "Panel Replay Enabled"; > + status = psr->sel_update_enabled ? "Panel Replay Selective > Update Enabled" : > + "Panel Replay Enabled"; > else if (psr->enabled) > - status = psr->sel_update_enabled ? "PSR2 enabled" : "PSR1 > enabled"; > + status = psr->sel_update_enabled ? "PSR2" : "PSR1"; > else > status = "disabled"; > seq_printf(m, "PSR mode: %s\n", status); > -- > 2.34.1
RE: [PATCH v9 11/12] drm/i915/psr: Split intel_psr2_config_valid for panel replay
> -Original Message-
> From: Hogander, Jouni
> Sent: Friday, May 3, 2024 12:04 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Hogander, Jouni
>
> Subject: [PATCH v9 11/12] drm/i915/psr: Split intel_psr2_config_valid for
> panel replay
>
> Part of intel_psr2_config_valid is valid for panel replay. rename it as
> intel_sel_update_config_valid. Split psr2 specific part and name it as
> intel_psr2_config_valid.
>
> v3:
> - move early transport check to psr2 specific check
> - check intel_psr2_config_valid only for non-Panel Replay case
> v2:
> - use psr2_global_enabled for panel replay as well
> - goto unsupported instead of return when global enabled check fails
>
> Signed-off-by: Jouni Högander
LGTM.
Reviewed-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 76 ++--
> 1 file changed, 46 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index f2eca0db47fd..2198448fdb27 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1142,9 +1142,6 @@ static bool intel_psr2_sel_fetch_config_valid(struct
> intel_dp *intel_dp,
> return false;
> }
>
> - if (psr2_su_region_et_valid(intel_dp))
> - crtc_state->enable_psr2_su_region_et = true;
> -
> return crtc_state->enable_psr2_sel_fetch = true; }
>
> @@ -1515,11 +1512,6 @@ static bool intel_psr2_config_valid(struct intel_dp
> *intel_dp,
> return false;
> }
>
> - if (!psr2_global_enabled(intel_dp)) {
> - drm_dbg_kms(_priv->drm, "PSR2 disabled by flag\n");
> - return false;
> - }
> -
> /*
>* DSC and PSR2 cannot be enabled simultaneously. If a requested
>* resolution requires DSC to be enabled, priority is given to DSC @@
> -1532,12 +1524,6 @@ static bool intel_psr2_config_valid(struct intel_dp
> *intel_dp,
> return false;
> }
>
> - if (crtc_state->crc_enabled) {
> - drm_dbg_kms(_priv->drm,
> - "PSR2 not enabled because it would inhibit pipe
> CRC calculation\n");
> - return false;
> - }
> -
> if (DISPLAY_VER(dev_priv) >= 12) {
> psr_max_h = 5120;
> psr_max_v = 3200;
> @@ -1588,30 +1574,60 @@ static bool intel_psr2_config_valid(struct
> intel_dp *intel_dp,
> return false;
> }
>
> - if (HAS_PSR2_SEL_FETCH(dev_priv)) {
> - if (!intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) &&
> - !HAS_PSR_HW_TRACKING(dev_priv)) {
> - drm_dbg_kms(_priv->drm,
> - "PSR2 not enabled, selective fetch not valid
> and no HW tracking available\n");
> - return false;
> - }
> - }
> -
> - if (!psr2_granularity_check(intel_dp, crtc_state)) {
> - drm_dbg_kms(_priv->drm, "PSR2 not enabled, SU
> granularity not compatible\n");
> - goto unsupported;
> - }
> -
> if (!crtc_state->enable_psr2_sel_fetch &&
> (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v)) {
> drm_dbg_kms(_priv->drm,
> "PSR2 not enabled, resolution %dx%d > max
> supported %dx%d\n",
> crtc_hdisplay, crtc_vdisplay,
> psr_max_h, psr_max_v);
> - goto unsupported;
> + return false;
> }
>
> tgl_dc3co_exitline_compute_config(intel_dp, crtc_state);
> +
> + if (psr2_su_region_et_valid(intel_dp))
> + crtc_state->enable_psr2_su_region_et = true;
> +
> + return true;
> +}
> +
> +static bool intel_sel_update_config_valid(struct intel_dp *intel_dp,
> + struct intel_crtc_state *crtc_state) {
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +
> + if (HAS_PSR2_SEL_FETCH(dev_priv) &&
> + !intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) &&
> + !HAS_PSR_HW_TRACKING(dev_priv)) {
> + drm_dbg_kms(_priv->drm,
> + "Selective update not enabled, selective fetch not
> valid and no HW tracking available\n");
> + goto unsupported;
> + }
> +
> + if (!psr2_global_enabled(intel_dp)) {
> + drm_dbg_kms(_priv->drm
RE: [PATCH v9 09/12] drm/i915/psr: Do not apply workarounds in case of panel replay
> -Original Message-
> From: Hogander, Jouni
> Sent: Friday, May 3, 2024 12:04 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Hogander, Jouni
>
> Subject: [PATCH v9 09/12] drm/i915/psr: Do not apply workarounds in case
> of panel replay
>
> There are some workarounds that are not applicable for panel replay. Do not
> apply these if panel replay is used.
>
> Bspec: 66624, 50422
>
> Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_fbc.c | 5 +++--
> drivers/gpu/drm/i915/display/intel_hdmi.c | 3 ++-
> drivers/gpu/drm/i915/display/intel_psr.c | 16 ++--
> 3 files changed, 15 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 984f13d8c0c8..50dd8eb9012e 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -1251,7 +1251,8 @@ static int intel_fbc_check_plane(struct
> intel_atomic_state *state,
>* Recommendation is to keep this combination disabled
>* Bspec: 50422 HSD: 14010260002
>*/
> - if (IS_DISPLAY_VER(i915, 12, 14) && crtc_state->has_sel_update) {
> + if (IS_DISPLAY_VER(i915, 12, 14) && crtc_state->has_sel_update &&
> + !crtc_state->has_panel_replay) {
> plane_state->no_fbc_reason = "PSR2 enabled";
> return 0;
> }
> @@ -1259,7 +1260,7 @@ static int intel_fbc_check_plane(struct
> intel_atomic_state *state,
> /* Wa_14016291713 */
> if ((IS_DISPLAY_VER(i915, 12, 13) ||
>IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_C0)) &&
> - crtc_state->has_psr) {
> + crtc_state->has_psr && !crtc_state->has_panel_replay) {
> plane_state->no_fbc_reason = "PSR1 enabled
> (Wa_14016291713)";
> return 0;
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 5f6deceaf8ba..0faf2afa1c09 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -532,7 +532,8 @@ void hsw_write_infoframe(struct intel_encoder
> *encoder,
> 0);
>
> /* Wa_14013475917 */
> - if (!(IS_DISPLAY_VER(dev_priv, 13, 14) && crtc_state->has_psr &&
> type == DP_SDP_VSC))
> + if (!(IS_DISPLAY_VER(dev_priv, 13, 14) && crtc_state->has_psr &&
> + !crtc_state->has_panel_replay && type == DP_SDP_VSC))
> val |= hsw_infoframe_enable(type);
>
> if (type == DP_SDP_VSC)
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 8f23df5cd5a8..f2eca0db47fd 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1959,13 +1959,15 @@ static void intel_psr_enable_source(struct
> intel_dp *intel_dp,
>* All supported adlp panels have 1-based X granularity, this
> may
>* cause issues if non-supported panels are used.
>*/
> - if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0,
> STEP_B0) ||
> - IS_ALDERLAKE_P(dev_priv))
> + if (!intel_dp->psr.panel_replay_enabled &&
> + (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0,
> STEP_B0) ||
> + IS_ALDERLAKE_P(dev_priv)))
> intel_de_rmw(dev_priv,
> hsw_chicken_trans_reg(dev_priv, cpu_transcoder),
>0, ADLP_1_BASED_X_GRANULARITY);
>
> /* Wa_16012604467:adlp,mtl[a0,b0] */
> - if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0,
> STEP_B0))
> + if (!intel_dp->psr.panel_replay_enabled &&
> + IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0,
> STEP_B0))
> intel_de_rmw(dev_priv,
>
> MTL_CLKGATE_DIS_TRANS(cpu_transcoder), 0,
>
> MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS);
> @@ -2141,7 +2143,8 @@ static void intel_psr_disable_locked(struct intel_dp
> *intel_dp)
>
> if (intel_dp->psr.sel_update_enabled) {
> /* Wa_16012604467:adlp,mtl[a0,b0] */
> - if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0,
> STEP_B0))
> + if (!intel_dp->psr.panel_replay_enabled &&
> + IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0,
> STEP_B0))
>
RE: [PATCH v9 08/12] drm/i915/psr: Panel replay uses SRD_STATUS to track it's status
> -Original Message-
> From: Hogander, Jouni
> Sent: Friday, May 3, 2024 12:04 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Hogander, Jouni
>
> Subject: [PATCH v9 08/12] drm/i915/psr: Panel replay uses SRD_STATUS to
> track it's status
>
> DP Panel replay uses SRD_STATUS to track it's status despite selective update
> mode.
>
> Bspec: 53370, 68920
>
> v3:
> - do not use PSR2_STATUS for PSR1
> v2:
> - use intel_dp_is_edp to differentiate
> - modify debugfs status as well
>
> Signed-off-by: Jouni Högander
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 8 +---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 5e5ef432b931..8f23df5cd5a8 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -2860,7 +2860,8 @@ void intel_psr_wait_for_idle_locked(const struct
> intel_crtc_state *new_crtc_stat
> if (!intel_dp->psr.enabled)
> continue;
>
> - if (intel_dp->psr.sel_update_enabled)
> + if (intel_dp_is_edp(intel_dp) &&
> + intel_dp->psr.sel_update_enabled)
Why not using panel_replay_enabled check here? For edp panel replay selective
update the above condition will be true, rt?
> ret =
> _psr2_ready_for_pipe_update_locked(intel_dp);
> else
> ret =
> _psr1_ready_for_pipe_update_locked(intel_dp);
> @@ -2881,7 +2882,8 @@ static bool __psr_wait_for_idle_locked(struct
> intel_dp *intel_dp)
> if (!intel_dp->psr.enabled)
> return false;
>
> - if (intel_dp->psr.sel_update_enabled) {
> + if (!intel_dp->psr.panel_replay_enabled &&
> + intel_dp->psr.sel_update_enabled) {
> reg = EDP_PSR2_STATUS(cpu_transcoder);
> mask = EDP_PSR2_STATUS_STATE_MASK;
> } else {
> @@ -3500,7 +3502,7 @@ psr_source_status(struct intel_dp *intel_dp, struct
> seq_file *m)
> const char *status = "unknown";
> u32 val, status_val;
>
> - if (intel_dp->psr.sel_update_enabled) {
> + if (intel_dp_is_edp(intel_dp) && intel_dp->psr.sel_update_enabled) {
Same as above.
Regards,
Animesh
> static const char * const live_status[] = {
> "IDLE",
> "CAPTURE",
> --
> 2.34.1
RE: [PATCH v9 07/12] drm/i915/psr: Modify intel_dp_get_su_granularity to support panel replay
> -Original Message-
> From: Hogander, Jouni
> Sent: Friday, May 3, 2024 12:04 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Hogander, Jouni
>
> Subject: [PATCH v9 07/12] drm/i915/psr: Modify intel_dp_get_su_granularity
> to support panel replay
>
> Currently intel_dp_get_su_granularity doesn't support panel replay.
> This fix modifies it to support panel replay as well.
>
> v4:
> - use drm_dp_dpcd_readb instead of drm_dp_dpcd_read
> - ensure return value is 0 if drm_dp_dpcd_readb fails
> v3: use correct offset for DP_PANEL_PANEL_REPLAY_CAPABILITY
> v2: rely on PSR definitions on common bits
>
> Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 62 +---
> 1 file changed, 55 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index b94f8e33ed1f..5e5ef432b931 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -466,6 +466,40 @@ static u8 intel_dp_get_sink_sync_latency(struct
> intel_dp *intel_dp)
> return val;
> }
>
> +static u8 intel_dp_get_su_capability(struct intel_dp *intel_dp) {
> + u8 su_capability = 0;
> +
> + if (intel_dp->psr.sink_panel_replay_su_support)
> + drm_dp_dpcd_readb(_dp->aux,
> + DP_PANEL_PANEL_REPLAY_CAPABILITY,
> + _capability);
> + else
> + su_capability = intel_dp->psr_dpcd[1];
> +
> + return su_capability;
> +}
> +
> +static unsigned int
> +intel_dp_get_su_x_granularity_offset(struct intel_dp *intel_dp) {
> + return intel_dp->psr.sink_panel_replay_su_support ?
> + DP_PANEL_PANEL_REPLAY_X_GRANULARITY :
> + DP_PSR2_SU_X_GRANULARITY;
> +}
> +
> +static unsigned int
> +intel_dp_get_su_y_granularity_offset(struct intel_dp *intel_dp) {
> + return intel_dp->psr.sink_panel_replay_su_support ?
> + DP_PANEL_PANEL_REPLAY_Y_GRANULARITY :
> + DP_PSR2_SU_Y_GRANULARITY;
> +}
> +
> +/*
> + * Note: Bits related to granularity are same in panel replay and psr
> + * registers. Rely on PSR definitions on these "common" bits.
> + */
> static void intel_dp_get_su_granularity(struct intel_dp *intel_dp) {
> struct drm_i915_private *i915 = dp_to_i915(intel_dp); @@ -473,18
> +507,29 @@ static void intel_dp_get_su_granularity(struct intel_dp
> *intel_dp)
> u16 w;
> u8 y;
>
> - /* If sink don't have specific granularity requirements set legacy ones
> */
> - if (!(intel_dp->psr_dpcd[1] &
> DP_PSR2_SU_GRANULARITY_REQUIRED)) {
> + /*
> + * TODO: Do we need to take into account panel supporting both PSR
> and
> + * Panel replay?
> + */
> +
> + /*
> + * If sink don't have specific granularity requirements set legacy
> + * ones.
> + */
> + if (!(intel_dp_get_su_capability(intel_dp) &
> + DP_PSR2_SU_GRANULARITY_REQUIRED)) {
> /* As PSR2 HW sends full lines, we do not care about x
> granularity */
> w = 4;
> y = 4;
> goto exit;
> }
>
> - r = drm_dp_dpcd_read(_dp->aux,
> DP_PSR2_SU_X_GRANULARITY, , 2);
> + r = drm_dp_dpcd_read(_dp->aux,
> + intel_dp_get_su_x_granularity_offset(intel_dp),
> + , 2);
> if (r != 2)
> drm_dbg_kms(>drm,
> - "Unable to read
> DP_PSR2_SU_X_GRANULARITY\n");
> + "Unable to read selective update x granularity\n");
> /*
>* Spec says that if the value read is 0 the default granularity should
>* be used instead.
> @@ -492,10 +537,12 @@ static void intel_dp_get_su_granularity(struct
> intel_dp *intel_dp)
> if (r != 2 || w == 0)
> w = 4;
>
> - r = drm_dp_dpcd_read(_dp->aux,
> DP_PSR2_SU_Y_GRANULARITY, , 1);
> + r = drm_dp_dpcd_read(_dp->aux,
> + intel_dp_get_su_y_granularity_offset(intel_dp),
> + , 1);
> if (r != 1) {
> drm_dbg_kms(>drm,
> - "Unable to read
> DP_PSR2_SU_Y_GRANULARITY\n");
> + "Unable to read selective update y granularity\n");
> y = 4;
> }
> if (y == 0)
> @@ -588,7 +635,8 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
> if (intel_dp->psr_dpcd[0])
> _psr_init_dpcd(intel_dp);
>
> - if (intel_dp->psr.sink_psr2_support)
> + if (intel_dp->psr.sink_psr2_support ||
> + intel_dp->psr.sink_panel_replay_su_support)
> intel_dp_get_su_granularity(intel_dp);
> }
>
> --
> 2.34.1
RE: [PATCH v9 06/12] drm/i915/psr: Detect panel replay selective update support
> -Original Message-
> From: Hogander, Jouni
> Sent: Friday, May 3, 2024 12:04 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Hogander, Jouni
>
> Subject: [PATCH v9 06/12] drm/i915/psr: Detect panel replay selective update
> support
>
> Add new boolean to store panel replay selective update support of sink into
> intel_psr struct. Detect panel replay selective update support and store it
> into this new boolean.
>
> v3: Clear sink_panel_replay_su_support in intel_dp_detect
> v2: Merge adding new boolean into this patch
>
> Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
> drivers/gpu/drm/i915/display/intel_dp.c| 1 +
> drivers/gpu/drm/i915/display/intel_psr.c | 10 --
> 3 files changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 150e6c8e0320..a693728f8344 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1719,6 +1719,7 @@ struct intel_psr {
> u16 su_y_granularity;
> bool source_panel_replay_support;
> bool sink_panel_replay_support;
> + bool sink_panel_replay_su_support;
> bool panel_replay_enabled;
> u32 dc3co_exitline;
> u32 dc3co_exit_delay;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 5731aa84992e..180f23f7b383 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -5858,6 +5858,7 @@ intel_dp_detect(struct drm_connector *connector,
> memset(_dp->compliance, 0, sizeof(intel_dp-
> >compliance));
> memset(intel_connector->dp.dsc_dpcd, 0,
> sizeof(intel_connector->dp.dsc_dpcd));
> intel_dp->psr.sink_panel_replay_support = false;
> + intel_dp->psr.sink_panel_replay_su_support = false;
>
> intel_dp_mst_disconnect(intel_dp);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index af18728460c9..b94f8e33ed1f 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -520,9 +520,15 @@ static void _panel_replay_init_dpcd(struct intel_dp
> *intel_dp)
> return;
> }
>
> - drm_dbg_kms(>drm,
> - "Panel replay is supported by panel\n");
> intel_dp->psr.sink_panel_replay_support = true;
> +
> + if (pr_dpcd & DP_PANEL_REPLAY_SU_SUPPORT)
> + intel_dp->psr.sink_panel_replay_su_support = true;
> +
> + drm_dbg_kms(>drm,
> + "Panel replay %sis supported by panel\n",
> + intel_dp->psr.sink_panel_replay_su_support ?
> + "selective_update " : "");
> }
>
> static void _psr_init_dpcd(struct intel_dp *intel_dp)
> --
> 2.34.1
RE: [PATCH v9 03/12] drm/i915/dp: Use always vsc revision 0x6 for Panel Replay
> -Original Message-
> From: Hogander, Jouni
> Sent: Friday, May 3, 2024 12:04 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Hogander, Jouni
>
> Subject: [PATCH v9 03/12] drm/i915/dp: Use always vsc revision 0x6 for Panel
> Replay
>
> We are about to enable Panel Replay Selective update mode. Vsc revision 0x6
> for Panel Replay no matter if it is selective update or full frame update
> mode.
> Take this into account when preparing VSC SDP package.
>
> Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 16
> 1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 0755bdfc8d3d..5731aa84992e 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2660,14 +2660,6 @@ static void intel_dp_compute_vsc_sdp(struct
> intel_dp *intel_dp,
> if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
> intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
>vsc);
> - } else if (crtc_state->has_sel_update) {
> - /*
> - * [PSR2 without colorimetry]
> - * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
> - * 3D stereo + PSR/PSR2 + Y-coordinate.
> - */
> - vsc->revision = 0x4;
> - vsc->length = 0xe;
> } else if (crtc_state->has_panel_replay) {
> /*
>* [Panel Replay without colorimetry info] @@ -2676,6
> +2668,14 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp
> *intel_dp,
>*/
> vsc->revision = 0x6;
> vsc->length = 0x10;
> + } else if (crtc_state->has_sel_update) {
> + /*
> + * [PSR2 without colorimetry]
> + * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
> + * 3D stereo + PSR/PSR2 + Y-coordinate.
> + */
> + vsc->revision = 0x4;
> + vsc->length = 0xe;
> } else {
> /*
>* [PSR1]
> --
> 2.34.1
RE: [PATCH v9 02/12] drm/i915/display: Do not print "psr: enabled" for on Panel Replay
> -Original Message-
> From: Hogander, Jouni
> Sent: Friday, May 3, 2024 12:04 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Hogander, Jouni
>
> Subject: [PATCH v9 02/12] drm/i915/display: Do not print "psr: enabled" for
> on Panel Replay
>
> After setting has_psr for panel replay as well crtc state dump is improperly
> printing "psr: enabled" for Panel Replay as well. Fix this by checking also
> has_panel_replay.
>
> Fixes: 5afa6e496098 ("drm/i915/psr: Set intel_crtc_state->has_psr on panel
> replay as well")
> Signed-off-by: Jouni Högander
LGTM.
Reviewed-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> index 1da4c122c52e..bddcc9edeab4 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> @@ -252,7 +252,8 @@ void intel_crtc_state_dump(const struct
> intel_crtc_state *pipe_config,
> str_enabled_disabled(pipe_config-
> >sdp_split_enable));
>
> drm_printf(, "psr: %s, selective update: %s, panel replay:
> %s, selective fetch: %s\n",
> -str_enabled_disabled(pipe_config->has_psr),
> +str_enabled_disabled(pipe_config->has_psr &&
> + !pipe_config-
> >has_panel_replay),
> str_enabled_disabled(pipe_config-
> >has_sel_update),
> str_enabled_disabled(pipe_config-
> >has_panel_replay),
> str_enabled_disabled(pipe_config-
> >enable_psr2_sel_fetch));
> --
> 2.34.1
RE: [PATCH v9 01/12] drm/i915/psr: Rename has_psr2 as has_sel_update
> -Original Message-
> From: Hogander, Jouni
> Sent: Friday, May 3, 2024 12:04 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Hogander, Jouni
>
> Subject: [PATCH v9 01/12] drm/i915/psr: Rename has_psr2 as
> has_sel_update
>
> We are going to reuse has_psr2 for panel_replay as well. Rename it as
> has_sel_update to avoid confusion.
>
> v3: do not add has_psr check into psr2 case in intel_dp_compute_vsc_sdp
> v2: Rebase
>
> Signed-off-by: Jouni Högander
LGTM.
Reviewed-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 4 ++--
> drivers/gpu/drm/i915/display/intel_display.c | 2 +-
> drivers/gpu/drm/i915/display/intel_display_types.h | 2 +-
> drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
> drivers/gpu/drm/i915/display/intel_fbc.c | 2 +-
> drivers/gpu/drm/i915/display/intel_psr.c | 10 +-
> 6 files changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> index ccaa4cb2809b..1da4c122c52e 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> @@ -251,9 +251,9 @@ void intel_crtc_state_dump(const struct
> intel_crtc_state *pipe_config,
> drm_printf(, "sdp split: %s\n",
> str_enabled_disabled(pipe_config-
> >sdp_split_enable));
>
> - drm_printf(, "psr: %s, psr2: %s, panel replay: %s, selective
> fetch: %s\n",
> + drm_printf(, "psr: %s, selective update: %s, panel replay:
> %s,
> +selective fetch: %s\n",
> str_enabled_disabled(pipe_config->has_psr),
> -str_enabled_disabled(pipe_config->has_psr2),
> +str_enabled_disabled(pipe_config-
> >has_sel_update),
> str_enabled_disabled(pipe_config-
> >has_panel_replay),
> str_enabled_disabled(pipe_config-
> >enable_psr2_sel_fetch));
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 273323f30ae2..0ae18b07ac87 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5320,7 +5320,7 @@ intel_pipe_config_compare(const struct
> intel_crtc_state *current_config,
>*/
> if (current_config->has_panel_replay || pipe_config-
> >has_panel_replay) {
> PIPE_CONF_CHECK_BOOL(has_psr);
> - PIPE_CONF_CHECK_BOOL(has_psr2);
> + PIPE_CONF_CHECK_BOOL(has_sel_update);
> PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
> PIPE_CONF_CHECK_BOOL(enable_psr2_su_region_et);
> PIPE_CONF_CHECK_BOOL(has_panel_replay);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 62f7a30c37dc..6747c10da298 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1189,7 +1189,7 @@ struct intel_crtc_state {
>
> /* PSR is supported but might not be enabled due the lack of enabled
> planes */
> bool has_psr;
> - bool has_psr2;
> + bool has_sel_update;
> bool enable_psr2_sel_fetch;
> bool enable_psr2_su_region_et;
> bool req_psr2_sdp_prior_scanline;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index e05e25cd4a94..0755bdfc8d3d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2660,7 +2660,7 @@ static void intel_dp_compute_vsc_sdp(struct
> intel_dp *intel_dp,
> if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
> intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
>vsc);
> - } else if (crtc_state->has_psr2) {
> + } else if (crtc_state->has_sel_update) {
> /*
>* [PSR2 without colorimetry]
>* Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 151dcd0c45b6..984f13d8c0c8 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -1251,7 +1251,7 @@ static int intel_fbc_check_plane(struct
> intel_atomic_state *state,
>* Recommendation
RE: [PATCH] drm/i915/hdcp: Disable HDCP Line Rekeying for HDCP2.2 on HDMI
> -Original Message-
> From: Intel-gfx On Behalf Of Suraj
> Kandpal
> Sent: Thursday, May 2, 2024 10:11 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Borah, Chaitanya Kumar ; Shankar,
> Uma ; Nautiyal, Ankit K
> ; Kandpal, Suraj
> Subject: [PATCH] drm/i915/hdcp: Disable HDCP Line Rekeying for HDCP2.2 on
> HDMI
>
> Disable HDCP Line Rekeying when HDCP ver > 1.4 and when we are on HDMI
> TMDS operation for DISPLAY_VER >= 14.
>
> --v2
> -Wa to be mentioned in comments not in commit message [Jani] -Remove
> blankline [Jani]
>
> --v3
> -No need to write what is being done in comments when code is self
> explanatory [Jani]
>
> --v4
> -Add comment regarding need of this WA when in TMDS mode [Chaitanya] -
> Write in chicken register for MTL [CHaitanya]
>
> --v5
> -Fix comment [Chaitanya]
> -Use correct set and clear value in intel_de_rmw [Chaitanya]
>
> Bspec: 49273
> Bspec: 69964
> Signed-off-by: Suraj Kandpal
> ---
> drivers/gpu/drm/i915/display/intel_hdcp.c | 23 +++
> drivers/gpu/drm/i915/i915_reg.h | 4
> 2 files changed, 27 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index d5ed4c7dfbc0..02cbbbfd8e25 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -30,6 +30,27 @@
> #define KEY_LOAD_TRIES 5
> #define HDCP2_LC_RETRY_CNT 3
>
> +/* WA: 16022217614 */
> +static void
> +intel_hdcp_disable_hdcp_line_rekeying(struct intel_encoder *encoder,
> + struct intel_hdcp *hdcp)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +
> + /* Here we assume HDMI is in TMDS mode of operation */
> + if (encoder->type != INTEL_OUTPUT_HDMI)
> + return;
> +
> + if (DISPLAY_VER(dev_priv) >= 14) {
> + if (IS_METEORLAKE(dev_priv))
> + intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(hdcp-
> >cpu_transcoder),
> + 0, HDCP_LINE_REKEY_DISABLE);
> + else
> + intel_de_rmw(dev_priv,
> TRANS_DDI_FUNC_CTL(hdcp->cpu_transcoder),
> + 0,
> TRANS_DDI_HDCP_LINE_REKEY_DISABLE);
> + }
> +}
> +
> static int intel_conn_to_vcpi(struct intel_atomic_state *state,
> struct intel_connector *connector) { @@ -2005,6
> +2026,8 @@ static int _intel_hdcp2_enable(struct intel_atomic_state *state,
> connector->base.base.id, connector->base.name,
> hdcp->content_type);
>
> + intel_hdcp_disable_hdcp_line_rekeying(connector->encoder, hdcp);
> +
> ret = hdcp2_authenticate_and_encrypt(state, connector);
> if (ret) {
> drm_dbg_kms(>drm, "HDCP2 Type%d Enabling Failed.
> (%d)\n", diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h index e22a82a5ddd7..31338d825e34
> 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3501,6 +3501,8 @@
> [TRANSCODER_D] =
> _CHICKEN_TRANS_D))
> #define _MTL_CHICKEN_TRANS_A 0x604e0
> #define _MTL_CHICKEN_TRANS_B 0x614e0
> +#define _MTL_CHICKEN_TRANS_C 0x624e0
> +#define _MTL_CHICKEN_TRANS_D 0x634e0
No need of macro for transcoder c and d, as per transcoder it will be
calculated by _MMIO_TRANS((trans).
Regards,
Animesh
> #define MTL_CHICKEN_TRANS(trans) _MMIO_TRANS((trans), \
> _MTL_CHICKEN_TRANS_A,
> \
> _MTL_CHICKEN_TRANS_B)
> @@ -3519,6 +3521,7 @@
> #define DP_FEC_BS_JITTER_WAREG_BIT(15)
> #define PSR2_VSC_ENABLE_PROG_HEADERREG_BIT(12)
> #define DP_DSC_INSERT_SF_AT_EOL_WA REG_BIT(4)
> +#define HDCP_LINE_REKEY_DISABLEREG_BIT(0)
>
> #define DISP_ARB_CTL _MMIO(0x45000)
> #define DISP_FBC_MEMORY_WAKE REG_BIT(31)
> @@ -4520,6 +4523,7 @@ enum skl_power_gate {
> #define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12)
> #define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12)
> #define TRANS_DDI_EDP_INPUT_D_ONOFF (7 << 12)
> +#define TRANS_DDI_HDCP_LINE_REKEY_DISABLE REG_BIT(12)
> #define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(11,
> 10)
> #define TRANS_DDI_MST_TRANSPORT_SELECT(trans) \
> REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK,
> trans)
> --
> 2.43.2
RE: [PATCH v3 4/6] drm/i915/alpm: Add compute config for lobf
> -Original Message-
> From: Hogander, Jouni
> Sent: Friday, May 3, 2024 12:49 PM
> To: Manna, Animesh ; intel-
> g...@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org; Murthy, Arun R
> ; Nikula, Jani
> Subject: Re: [PATCH v3 4/6] drm/i915/alpm: Add compute config for lobf
>
> On Thu, 2024-04-25 at 00:08 +0530, Animesh Manna wrote:
> > Link Off Between Active Frames, is a new feature for eDP
> > that allows the panel to go to lower power state after
> > transmission of data. This is a feature on top of ALPM, AS SDP.
> > Add compute config during atomic-check phase.
> >
> > v1: RFC version.
> > v2: Add separate flag for auxless-alpm. [Jani]
> > v3:
> > - intel_dp->lobf_supported replaced with crtc_state->has_lobf.
> > [Jouni]
> > - Add DISPLAY_VER() check. [Jouni]
> > - Modify function name of get_aux_less_status. [Jani]
> >
> > Signed-off-by: Animesh Manna
> > ---
> > drivers/gpu/drm/i915/display/intel_alpm.c | 48
> > +++
> > drivers/gpu/drm/i915/display/intel_alpm.h | 5 ++
> > .../drm/i915/display/intel_display_types.h | 4 ++
> > drivers/gpu/drm/i915/display/intel_dp.c | 4 ++
> > 4 files changed, 61 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> > b/drivers/gpu/drm/i915/display/intel_alpm.c
> > index 13bac3e8c8fa..3bb69ed16aab 100644
> > --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> > +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> > @@ -11,6 +11,16 @@
> > #include "intel_dp_aux.h"
> > #include "intel_psr_regs.h"
> >
> > +bool intel_alpm_get_aux_less_status(struct intel_dp *intel_dp)
> > +{
> > + u8 alpm_caps = 0;
> > +
> > + if (drm_dp_dpcd_readb(_dp->aux, DP_RECEIVER_ALPM_CAP,
> > + _caps) != 1)
> > + return false;
> > + return alpm_caps & DP_ALPM_AUX_LESS_CAP;
> > +}
> > +
> > /*
> > * See Bspec: 71632 for the table
> > *
> > @@ -242,6 +252,44 @@ bool intel_alpm_compute_params(struct intel_dp
> > *intel_dp,
> > return true;
> > }
> >
> > +void intel_alpm_compute_lobf_config(struct intel_dp *intel_dp,
> > + struct intel_crtc_state
> > *crtc_state,
> > + struct drm_connector_state
> > *conn_state)
> > +{
> > + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> > + struct drm_display_mode *adjusted_mode = _state-
> > >hw.adjusted_mode;
> > + int waketime_in_lines, first_sdp_position;
> > + int context_latency, guardband;
> > +
> > + crtc_state->has_lobf = false;
>
> Drop this line. I think crtc_state is reset before doing this
> compute_config
Sure.
>
> > +
> > + if (!intel_dp_is_edp(intel_dp))
> > + return;
> > +
> > + if (DISPLAY_VER(i915) < 20)
> > + return;
> > +
> > + if (!intel_dp_as_sdp_supported(intel_dp))
> > + return;
> > +
> > + if (crtc_state->has_psr)
> > + return;
> > +
> > + if (intel_alpm_compute_params(intel_dp, crtc_state)) {
>
> I think it is easier to read and helps avoiding big if blocks if you:
>
> if (!intel_alpm_compute_params(intel_dp, crtc_state())
> return;
Ok.
>
> This actually brings up another thing: do we want to spread intel_psr.c
> pollution by continue using these boolean return values? I would prefer
> changing intel_alpm_compute_params return value to "normal" int
> approach and return 0 on success. This would mean one more patch
> changing it.
Ok.
>
> > + context_latency = adjusted_mode->crtc_vblank_start -
> > adjusted_mode->crtc_vdisplay;
> > + guardband = adjusted_mode->crtc_vtotal -
> > + adjusted_mode->crtc_vdisplay -
> > context_latency;
> > + first_sdp_position = adjusted_mode->crtc_vtotal -
> > adjusted_mode->crtc_vsync_start;
> > + if (intel_dp->alpm_parameters.auxless_alpm_supported)
> > + waketime_in_lines = intel_dp-
> > >alpm_parameters.io_wake_lines;
> > + else
> > + waketime_in_lines = intel_dp-
> > >alpm_parameters.fast_wake_lines;
> > +
> > + if ((context_latency + guardband) >
> > (first_sdp_position + waketim
RE: [PATCH v3 6/6] drm/i915/alpm: Add debugfs for LOBF
> -Original Message-
> From: Hogander, Jouni
> Sent: Friday, May 3, 2024 1:02 PM
> To: Manna, Animesh ; intel-
> g...@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org; Murthy, Arun R
> ; Nikula, Jani
> Subject: Re: [PATCH v3 6/6] drm/i915/alpm: Add debugfs for LOBF
>
> On Thu, 2024-04-25 at 00:08 +0530, Animesh Manna wrote:
> > For validation purpose add debugfs for LOBF.
> >
> > Signed-off-by: Animesh Manna
> > ---
> > drivers/gpu/drm/i915/display/intel_alpm.c | 48
> > +++
> > drivers/gpu/drm/i915/display/intel_alpm.h | 2 +
> > .../drm/i915/display/intel_display_debugfs.c | 2 +
> > 3 files changed, 52 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> > b/drivers/gpu/drm/i915/display/intel_alpm.c
> > index b08799586b58..2d3027c2fb0a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> > +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> > @@ -343,3 +343,51 @@ void intel_alpm_configure(struct intel_dp
> > *intel_dp,
> > {
> > lnl_alpm_configure(intel_dp, crtc_state);
> > }
> > +
> > +static int i915_edp_lobf_info_show(struct seq_file *m, void *data)
> > +{
> > + struct intel_connector *connector = m->private;
> > + struct drm_i915_private *dev_priv = to_i915(connector-
> > >base.dev);
> > + struct drm_crtc *crtc;
> > + struct intel_crtc_state *crtc_state;
> > + enum transcoder cpu_transcoder;
> > + bool lobf_enabled;
> > + int ret;
> > +
> > + ret = drm_modeset_lock_single_interruptible(_priv-
> > >drm.mode_config.connection_mutex);
> > + if (ret)
> > + return ret;
> > +
> > + crtc = connector->base.state->crtc;
> > + if (connector->base.status != connector_status_connected ||
> > !crtc) {
> > + ret = -ENODEV;
> > + goto out;
> > + }
> > +
> > + crtc_state = to_intel_crtc_state(crtc->state);
> > + seq_printf(m, "LOBF Criteria met: %s\n",
> > str_yes_no(crtc_state->has_lobf));
>
> I'm still not convinced on this. has_lobf ~= ALPM_CTL_LOBF_ENABLE in
> ALPM_CTL. To my opinion it is enough to dump seq_printf(m, "LOBF
> status: %s\n", str_enabled_disabled(lobf_enabled)) below. Maybe
> AUX_WAKE and AUX_LESS_WAKE could be dumped instead?
Can add aux-wake or aux-less info as well.
But as LOBF feature is dependent on adaptive sync fixed refresh rate mode
(which can be dynamic as per user input) and ALPM. I want to expose both the
conditions are satisfying or not along with status.
Regards,
Animesh
>
> BR,
>
> Jouni Högander
>
> > +
> > + cpu_transcoder = crtc_state->cpu_transcoder;
> > + lobf_enabled = intel_de_read(dev_priv,
> > ALPM_CTL(cpu_transcoder)) & ALPM_CTL_LOBF_ENABLE;
> > + seq_printf(m, "LOBF status: %s\n",
> > str_enabled_disabled(lobf_enabled));
> > +
> > +out:
> > + drm_modeset_unlock(_priv-
> > >drm.mode_config.connection_mutex);
> > +
> > + return ret;
> > +}
> > +
> > +DEFINE_SHOW_ATTRIBUTE(i915_edp_lobf_info);
> > +
> > +void intel_alpm_lobf_debugfs_add(struct intel_connector *connector)
> > +{
> > + struct drm_i915_private *i915 = to_i915(connector->base.dev);
> > + struct dentry *root = connector->base.debugfs_entry;
> > +
> > + if (DISPLAY_VER(i915) < 20 ||
> > + connector->base.connector_type !=
> DRM_MODE_CONNECTOR_eDP)
> > + return;
> > +
> > + debugfs_create_file("i915_edp_lobf_info", 0444, root,
> > + connector, _edp_lobf_info_fops);
> > +}
> > diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h
> > b/drivers/gpu/drm/i915/display/intel_alpm.h
> > index a9ca190da3e4..01fd08eb96f5 100644
> > --- a/drivers/gpu/drm/i915/display/intel_alpm.h
> > +++ b/drivers/gpu/drm/i915/display/intel_alpm.h
> > @@ -11,6 +11,7 @@
> > struct intel_dp;
> > struct intel_crtc_state;
> > struct drm_connector_state;
> > +struct intel_connector;
> >
> > bool intel_alpm_get_aux_less_status(struct intel_dp *intel_dp);
> > bool intel_alpm_compute_params(struct intel_dp *intel_dp,
> > @@ -20,4 +21,5 @@ void intel_alpm_compute_lobf_config(struct intel_dp
> > *intel_dp,
> > struct drm_connector_state
> > *conn_state);
> > void intel
RE: [PATCH v3 5/6] drm/i915/alpm: Enable lobf from source in ALPM_CTL
> -Original Message-
> From: Hogander, Jouni
> Sent: Friday, May 3, 2024 1:18 PM
> To: Manna, Animesh ; intel-
> g...@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org; Murthy, Arun R
> ; Nikula, Jani
> Subject: Re: [PATCH v3 5/6] drm/i915/alpm: Enable lobf from source in
> ALPM_CTL
>
> On Thu, 2024-04-25 at 00:08 +0530, Animesh Manna wrote:
> > Set the Link Off Between Frames Enable bit in ALPM_CTL register.
> >
> > Note: Lobf need to be enabled adaptive sync fixed refresh mode where
> > vmin = vmax = flipline, which will arise after cmmr feature
> > enablement. Will add enabling sequence in a separate patch.
>
> Is adaptive sync needed for both Aux Wake and Aux Less Wake?
AFAIK, ALPM (aux-wake/aux-less) do not have any dependency on adaptive sync.
But LOBF is dependent on ALPM (aux-wake/aux-less) and adaptive sync fixed
refresh mode.
>
> >
> > Signed-off-by: Animesh Manna
> > ---
> > drivers/gpu/drm/i915/display/intel_alpm.c | 13 +
> > drivers/gpu/drm/i915/display/intel_alpm.h | 4 ++--
> > drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
> > 3 files changed, 12 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> > b/drivers/gpu/drm/i915/display/intel_alpm.c
> > index 3bb69ed16aab..b08799586b58 100644
> > --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> > +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> > @@ -290,10 +290,11 @@ void intel_alpm_compute_lobf_config(struct
> > intel_dp *intel_dp,
> > }
> > }
> >
> > -static void lnl_alpm_configure(struct intel_dp *intel_dp)
> > +static void lnl_alpm_configure(struct intel_dp *intel_dp,
> > + const struct intel_crtc_state
> > *crtc_state)
> > {
> > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > - enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
> > + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > u32 alpm_ctl;
> >
> > if (DISPLAY_VER(dev_priv) < 20 || (!intel_dp-
> > >psr.psr2_enabled &&
> > @@ -329,12 +330,16 @@ static void lnl_alpm_configure(struct intel_dp
> > *intel_dp)
> > ALPM_CTL_EXTENDED_FAST_WAKE_TIME(intel_dp-
> > >alpm_parameters.fast_wake_lines);
> > }
> >
> > + if (crtc_state->has_lobf)
> > + alpm_ctl |= ALPM_CTL_LOBF_ENABLE;
> > +
>
> How you are planning to differentiate between AUX Wake and AUX Less
> Wake for LOBF?
LOBF can be enabled in both aux-wake or aux-less alpm. So, check for aux-wake
or aux-less is not needed.
For aux wake ALPM_CTL[ ALPM AUX Less Enable ] = 0
and for aux less ALPM_CTL[ ALPM AUX Less Enable ] = 1.
So, I am plaining to add has_lobf check and enable if needed before ALPM_CTL
register is getting programmed. Do you see any issue here?
Regards,
Animesh
>
> BR,
>
> Jouni Högander
>
> > alpm_ctl |= ALPM_CTL_ALPM_ENTRY_CHECK(intel_dp-
> > >alpm_parameters.check_entry_lines);
> >
> > intel_de_write(dev_priv, ALPM_CTL(cpu_transcoder), alpm_ctl);
> > }
> >
> > -void intel_alpm_configure(struct intel_dp *intel_dp)
> > +void intel_alpm_configure(struct intel_dp *intel_dp,
> > + const struct intel_crtc_state *crtc_state)
> > {
> > - lnl_alpm_configure(intel_dp);
> > + lnl_alpm_configure(intel_dp, crtc_state);
> > }
> > diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h
> > b/drivers/gpu/drm/i915/display/intel_alpm.h
> > index b9602b71d28f..a9ca190da3e4 100644
> > --- a/drivers/gpu/drm/i915/display/intel_alpm.h
> > +++ b/drivers/gpu/drm/i915/display/intel_alpm.h
> > @@ -18,6 +18,6 @@ bool intel_alpm_compute_params(struct intel_dp
> > *intel_dp,
> > void intel_alpm_compute_lobf_config(struct intel_dp *intel_dp,
> > struct intel_crtc_state
> > *crtc_state,
> > struct drm_connector_state
> > *conn_state); -void intel_alpm_configure(struct intel_dp *intel_dp);
> > -
> > +void intel_alpm_configure(struct intel_dp *intel_dp,
> > + const struct intel_crtc_state *crtc_state);
> > #endif
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index c4ab289dbc15..4eb45df20ad2 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -1611,7 +1611,7 @@ static void intel_psr_enable_source(struct
> > intel_dp *intel_dp,
> > IGNORE_PSR2_HW_TRACKING : 0);
> >
> > if (intel_dp_is_edp(intel_dp))
> > - intel_alpm_configure(intel_dp);
> > + intel_alpm_configure(intel_dp, crtc_state);
> >
> > /*
> > * Wa_16013835468
RE: [PATCH v8 01/11] drm/i915/psr: Rename has_psr2 as has_sel_update
> -Original Message- > From: Hogander, Jouni > Sent: Tuesday, April 30, 2024 11:52 AM > To: Manna, Animesh ; intel- > g...@lists.freedesktop.org > Subject: Re: [PATCH v8 01/11] drm/i915/psr: Rename has_psr2 as > has_sel_update > > On Mon, 2024-04-29 at 18:54 +, Manna, Animesh wrote: > > > > > > > -Original Message- > > > From: Hogander, Jouni > > > Sent: Monday, April 29, 2024 5:38 PM > > > To: intel-gfx@lists.freedesktop.org > > > Cc: Manna, Animesh ; Hogander, Jouni > > > > > > Subject: [PATCH v8 01/11] drm/i915/psr: Rename has_psr2 as > > > has_sel_update > > > > > > We are going to reuse has_psr2 for panel_replay as well. Rename it > > > as > > > has_sel_update to avoid confusion. > > > > > > v2: Rebase > > > > > > Signed-off-by: Jouni Högander > > > Reviewed-by: Animesh Manna > > > --- > > > drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 10 +--- > > > -- > > > drivers/gpu/drm/i915/display/intel_display.c | 2 +- > > > drivers/gpu/drm/i915/display/intel_display_types.h | 2 +- > > > drivers/gpu/drm/i915/display/intel_dp.c | 2 +- > > > drivers/gpu/drm/i915/display/intel_fbc.c | 2 +- > > > drivers/gpu/drm/i915/display/intel_psr.c | 10 +--- > > > -- > > > 6 files changed, 14 insertions(+), 14 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c > > > b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c > > > index ccaa4cb2809b..2c391714f28e 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c > > > +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c > > > @@ -251,11 +251,11 @@ void intel_crtc_state_dump(const struct > > > intel_crtc_state *pipe_config, > > > drm_printf(, "sdp split: %s\n", > > > str_enabled_disabled(pipe_config- > > > > sdp_split_enable)); > > > > > > - drm_printf(, "psr: %s, psr2: %s, panel replay: > > > %s, selective > > > fetch: %s\n", > > > - str_enabled_disabled(pipe_config- > > > >has_psr), > > > - str_enabled_disabled(pipe_config- > > > >has_psr2), > > > - str_enabled_disabled(pipe_config- > > > > has_panel_replay), > > > - str_enabled_disabled(pipe_config- > > > > enable_psr2_sel_fetch)); > > > + drm_printf(, "psr: %s, selective update: %s, > > > panel replay: > > > %s, selective fetch: %s\n", > > > + str_enabled_disabled(pipe_config- > > > >has_psr), > > > + str_enabled_disabled(pipe_config- > > > > has_sel_update), > > > + str_enabled_disabled(pipe_config- > > > > has_panel_replay), > > > + str_enabled_disabled(pipe_config- > > > > enable_psr2_sel_fetch)); > > > > During panel-replay has_psr flag also will be true. So will get print > > as psr enabled. > > Something below may give correct info, > > if (pipe_config->has_panel_replay) > > drm_printf(, "psr: disabled, panel replay: > > enabled"); > > else > > drm_printf(, "psr: %s, panel replay: > > disabled", > > > > str_enabled_disabled(pipe_config->has_psr)); > > > > drm_printf(, "selective update: %s, selective > > fetch: %s\n", > > > > str_enabled_disabled(pipe_config->has_sel_update), > > > > str_enabled_disabled(pipe_config->enable_psr2_sel_fetch)); > > This is actually not in scope of this patch. Would you mind if we > change this in separate patch not in this set? Yes a separate patch will be good, but need to add in same patch series to adhere to documentation of these psr/pr related flags. Regards, Animesh > > BR, > > Jouni Högander > > > > > > Regards, > > Animesh > > > > > } > > > > > > drm_printf(, "framestart delay: %d, MSA timing delay: > > > %d\n", diff > > > --git a/drivers/gpu/drm/i915/display/intel_display.c > > > b/drivers/gpu/drm/i915/display/intel_display
RE: [PATCH v8 06/11] drm/i915/psr: Modify intel_dp_get_su_granularity to support panel replay
> -Original Message-
> From: Hogander, Jouni
> Sent: Monday, April 29, 2024 5:38 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Hogander, Jouni
>
> Subject: [PATCH v8 06/11] drm/i915/psr: Modify intel_dp_get_su_granularity
> to support panel replay
>
> Currently intel_dp_get_su_granularity doesn't support panel replay.
> This fix modifies it to support panel replay as well.
>
> v3: use correct offset for DP_PANEL_PANEL_REPLAY_CAPABILITY
> v2: rely on PSR definitions on common bits
>
> Signed-off-by: Jouni Högander
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 62 +---
> 1 file changed, 55 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index b94f8e33ed1f..807423db3a13 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -466,6 +466,40 @@ static u8 intel_dp_get_sink_sync_latency(struct
> intel_dp *intel_dp)
> return val;
> }
>
> +static u8 intel_dp_get_su_capability(struct intel_dp *intel_dp) {
> + u8 su_capability;
> +
> + if (intel_dp->psr.sink_panel_replay_su_support)
> + drm_dp_dpcd_read(_dp->aux,
> + DP_PANEL_PANEL_REPLAY_CAPABILITY,
> + _capability, 1);
drm_dp_dpcd_readb() can be used here, otherwise looks good to me.
Regards,
Animesh
> + else
> + su_capability = intel_dp->psr_dpcd[1];
> +
> + return su_capability;
> +}
> +
> +static unsigned int
> +intel_dp_get_su_x_granularity_offset(struct intel_dp *intel_dp) {
> + return intel_dp->psr.sink_panel_replay_su_support ?
> + DP_PANEL_PANEL_REPLAY_X_GRANULARITY :
> + DP_PSR2_SU_X_GRANULARITY;
> +}
> +
> +static unsigned int
> +intel_dp_get_su_y_granularity_offset(struct intel_dp *intel_dp) {
> + return intel_dp->psr.sink_panel_replay_su_support ?
> + DP_PANEL_PANEL_REPLAY_Y_GRANULARITY :
> + DP_PSR2_SU_Y_GRANULARITY;
> +}
> +
> +/*
> + * Note: Bits related to granularity are same in panel replay and psr
> + * registers. Rely on PSR definitions on these "common" bits.
> + */
> static void intel_dp_get_su_granularity(struct intel_dp *intel_dp) {
> struct drm_i915_private *i915 = dp_to_i915(intel_dp); @@ -473,18
> +507,29 @@ static void intel_dp_get_su_granularity(struct intel_dp
> *intel_dp)
> u16 w;
> u8 y;
>
> - /* If sink don't have specific granularity requirements set legacy ones
> */
> - if (!(intel_dp->psr_dpcd[1] &
> DP_PSR2_SU_GRANULARITY_REQUIRED)) {
> + /*
> + * TODO: Do we need to take into account panel supporting both PSR
> and
> + * Panel replay?
> + */
> +
> + /*
> + * If sink don't have specific granularity requirements set legacy
> + * ones.
> + */
> + if (!(intel_dp_get_su_capability(intel_dp) &
> + DP_PSR2_SU_GRANULARITY_REQUIRED)) {
> /* As PSR2 HW sends full lines, we do not care about x
> granularity */
> w = 4;
> y = 4;
> goto exit;
> }
>
> - r = drm_dp_dpcd_read(_dp->aux,
> DP_PSR2_SU_X_GRANULARITY, , 2);
> + r = drm_dp_dpcd_read(_dp->aux,
> + intel_dp_get_su_x_granularity_offset(intel_dp),
> + , 2);
> if (r != 2)
> drm_dbg_kms(>drm,
> - "Unable to read
> DP_PSR2_SU_X_GRANULARITY\n");
> + "Unable to read selective update x granularity\n");
> /*
>* Spec says that if the value read is 0 the default granularity should
>* be used instead.
> @@ -492,10 +537,12 @@ static void intel_dp_get_su_granularity(struct
> intel_dp *intel_dp)
> if (r != 2 || w == 0)
> w = 4;
>
> - r = drm_dp_dpcd_read(_dp->aux,
> DP_PSR2_SU_Y_GRANULARITY, , 1);
> + r = drm_dp_dpcd_read(_dp->aux,
> + intel_dp_get_su_y_granularity_offset(intel_dp),
> + , 1);
> if (r != 1) {
> drm_dbg_kms(>drm,
> - "Unable to read
> DP_PSR2_SU_Y_GRANULARITY\n");
> + "Unable to read selective update y granularity\n");
> y = 4;
> }
> if (y == 0)
> @@ -588,7 +635,8 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
> if (intel_dp->psr_dpcd[0])
> _psr_init_dpcd(intel_dp);
>
> - if (intel_dp->psr.sink_psr2_support)
> + if (intel_dp->psr.sink_psr2_support ||
> + intel_dp->psr.sink_panel_replay_su_support)
> intel_dp_get_su_granularity(intel_dp);
> }
>
> --
> 2.34.1
RE: [PATCH v8 01/11] drm/i915/psr: Rename has_psr2 as has_sel_update
> -Original Message-
> From: Manna, Animesh
> Sent: Tuesday, April 30, 2024 12:24 AM
> To: Hogander, Jouni ; intel-
> g...@lists.freedesktop.org
> Subject: RE: [PATCH v8 01/11] drm/i915/psr: Rename has_psr2 as
> has_sel_update
>
>
>
> > -Original Message-
> > From: Hogander, Jouni
> > Sent: Monday, April 29, 2024 5:38 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Manna, Animesh ; Hogander, Jouni
> >
> > Subject: [PATCH v8 01/11] drm/i915/psr: Rename has_psr2 as
> > has_sel_update
> >
> > We are going to reuse has_psr2 for panel_replay as well. Rename it as
> > has_sel_update to avoid confusion.
> >
> > v2: Rebase
> >
> > Signed-off-by: Jouni Högander
> > Reviewed-by: Animesh Manna
> > ---
> > drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 10 +-
> > drivers/gpu/drm/i915/display/intel_display.c | 2 +-
> > drivers/gpu/drm/i915/display/intel_display_types.h | 2 +-
> > drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
> > drivers/gpu/drm/i915/display/intel_fbc.c | 2 +-
> > drivers/gpu/drm/i915/display/intel_psr.c | 10 +-
> > 6 files changed, 14 insertions(+), 14 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> > b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> > index ccaa4cb2809b..2c391714f28e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> > +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> > @@ -251,11 +251,11 @@ void intel_crtc_state_dump(const struct
> > intel_crtc_state *pipe_config,
> > drm_printf(, "sdp split: %s\n",
> >str_enabled_disabled(pipe_config-
> > >sdp_split_enable));
> >
> > - drm_printf(, "psr: %s, psr2: %s, panel replay: %s, selective
> > fetch: %s\n",
> > - str_enabled_disabled(pipe_config->has_psr),
> > - str_enabled_disabled(pipe_config->has_psr2),
> > - str_enabled_disabled(pipe_config-
> > >has_panel_replay),
> > - str_enabled_disabled(pipe_config-
> > >enable_psr2_sel_fetch));
> > + drm_printf(, "psr: %s, selective update: %s, panel replay:
> > %s, selective fetch: %s\n",
> > + str_enabled_disabled(pipe_config->has_psr),
> > + str_enabled_disabled(pipe_config-
> > >has_sel_update),
> > + str_enabled_disabled(pipe_config-
> > >has_panel_replay),
> > + str_enabled_disabled(pipe_config-
> > >enable_psr2_sel_fetch));
>
> During panel-replay has_psr flag also will be true. So will get print as psr
> enabled.
> Something below may give correct info,
> if (pipe_config->has_panel_replay)
> drm_printf(, "psr: disabled, panel replay:
> enabled");
> else
> drm_printf(, "psr: %s, panel replay: disabled",
>
> str_enabled_disabled(pipe_config->has_psr));
>
> drm_printf(, "selective update: %s, selective fetch: %s\n",
>
> str_enabled_disabled(pipe_config->has_sel_update),
> str_enabled_disabled(pipe_config-
> >enable_psr2_sel_fetch));
>
> Regards,
> Animesh
>
> > }
> >
> > drm_printf(, "framestart delay: %d, MSA timing delay: %d\n", diff
> > --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index f45e5f02096d..c1aba4e8ac54 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -5319,7 +5319,7 @@ intel_pipe_config_compare(const struct
> > intel_crtc_state *current_config,
> > */
> > if (current_config->has_panel_replay || pipe_config-
> > >has_panel_replay) {
> > PIPE_CONF_CHECK_BOOL(has_psr);
> > - PIPE_CONF_CHECK_BOOL(has_psr2);
> > + PIPE_CONF_CHECK_BOOL(has_sel_update);
> > PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
> > PIPE_CONF_CHECK_BOOL(enable_psr2_su_region_et);
> > PIPE_CONF_CHECK_BOOL(has_panel_replay);
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display
RE: [PATCH v8 01/11] drm/i915/psr: Rename has_psr2 as has_sel_update
> -Original Message-
> From: Hogander, Jouni
> Sent: Monday, April 29, 2024 5:38 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Hogander, Jouni
>
> Subject: [PATCH v8 01/11] drm/i915/psr: Rename has_psr2 as
> has_sel_update
>
> We are going to reuse has_psr2 for panel_replay as well. Rename it as
> has_sel_update to avoid confusion.
>
> v2: Rebase
>
> Signed-off-by: Jouni Högander
> Reviewed-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 10 +-
> drivers/gpu/drm/i915/display/intel_display.c | 2 +-
> drivers/gpu/drm/i915/display/intel_display_types.h | 2 +-
> drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
> drivers/gpu/drm/i915/display/intel_fbc.c | 2 +-
> drivers/gpu/drm/i915/display/intel_psr.c | 10 +-
> 6 files changed, 14 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> index ccaa4cb2809b..2c391714f28e 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> @@ -251,11 +251,11 @@ void intel_crtc_state_dump(const struct
> intel_crtc_state *pipe_config,
> drm_printf(, "sdp split: %s\n",
> str_enabled_disabled(pipe_config-
> >sdp_split_enable));
>
> - drm_printf(, "psr: %s, psr2: %s, panel replay: %s, selective
> fetch: %s\n",
> -str_enabled_disabled(pipe_config->has_psr),
> -str_enabled_disabled(pipe_config->has_psr2),
> -str_enabled_disabled(pipe_config-
> >has_panel_replay),
> -str_enabled_disabled(pipe_config-
> >enable_psr2_sel_fetch));
> + drm_printf(, "psr: %s, selective update: %s, panel replay:
> %s, selective fetch: %s\n",
> + str_enabled_disabled(pipe_config->has_psr),
> + str_enabled_disabled(pipe_config-
> >has_sel_update),
> + str_enabled_disabled(pipe_config-
> >has_panel_replay),
> + str_enabled_disabled(pipe_config-
> >enable_psr2_sel_fetch));
During panel-replay has_psr flag also will be true. So will get print as psr
enabled.
Something below may give correct info,
if (pipe_config->has_panel_replay)
drm_printf(, "psr: disabled, panel replay: enabled");
else
drm_printf(, "psr: %s, panel replay: disabled",
str_enabled_disabled(pipe_config->has_psr));
drm_printf(, "selective update: %s, selective fetch: %s\n",
str_enabled_disabled(pipe_config->has_sel_update),
str_enabled_disabled(pipe_config->enable_psr2_sel_fetch));
Regards,
Animesh
> }
>
> drm_printf(, "framestart delay: %d, MSA timing delay: %d\n", diff
> --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index f45e5f02096d..c1aba4e8ac54 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5319,7 +5319,7 @@ intel_pipe_config_compare(const struct
> intel_crtc_state *current_config,
>*/
> if (current_config->has_panel_replay || pipe_config-
> >has_panel_replay) {
> PIPE_CONF_CHECK_BOOL(has_psr);
> - PIPE_CONF_CHECK_BOOL(has_psr2);
> + PIPE_CONF_CHECK_BOOL(has_sel_update);
> PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
> PIPE_CONF_CHECK_BOOL(enable_psr2_su_region_et);
> PIPE_CONF_CHECK_BOOL(has_panel_replay);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 62f7a30c37dc..6747c10da298 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1189,7 +1189,7 @@ struct intel_crtc_state {
>
> /* PSR is supported but might not be enabled due the lack of enabled
> planes */
> bool has_psr;
> - bool has_psr2;
> + bool has_sel_update;
> bool enable_psr2_sel_fetch;
> bool enable_psr2_su_region_et;
> bool req_psr2_sdp_prior_scanline;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index e05e25cd4a94..a7c406a9
RE: [PATCH v7 06/11] drm/i915/psr: Modify intel_dp_get_su_granularity to support panel replay
> -Original Message-
> From: Manna, Animesh
> Sent: Monday, April 29, 2024 5:04 PM
> To: Hogander, Jouni ; intel-
> g...@lists.freedesktop.org
> Subject: RE: [PATCH v7 06/11] drm/i915/psr: Modify
> intel_dp_get_su_granularity to support panel replay
>
>
>
> > -Original Message-
> > From: Hogander, Jouni
> > Sent: Monday, April 29, 2024 4:46 PM
> > To: Manna, Animesh ; intel-
> > g...@lists.freedesktop.org
> > Subject: Re: [PATCH v7 06/11] drm/i915/psr: Modify
> > intel_dp_get_su_granularity to support panel replay
> >
> > On Mon, 2024-04-29 at 11:02 +, Manna, Animesh wrote:
> > >
> > >
> > > > -Original Message-
> > > > From: Hogander, Jouni
> > > > Sent: Friday, April 19, 2024 5:42 PM
> > > > To: intel-gfx@lists.freedesktop.org
> > > > Cc: Manna, Animesh ; Hogander, Jouni
> > > >
> > > > Subject: [PATCH v7 06/11] drm/i915/psr: Modify
> > > > intel_dp_get_su_granularity to support panel replay
> > > >
> > > > Currently intel_dp_get_su_granularity doesn't support panel replay.
> > > > This fix modifies it to support panel replay as well.
> > > >
> > > > v2: rely on PSR definitions on common bits
> > > >
> > > > Signed-off-by: Jouni Högander
> > > > Reviewed-by: Animesh Manna
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_psr.c | 62
> > > > +---
> > > > 1 file changed, 55 insertions(+), 7 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > index b94f8e33ed1f..29400fac13c2 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > @@ -466,6 +466,40 @@ static u8
> > > > intel_dp_get_sink_sync_latency(struct
> > > > intel_dp *intel_dp)
> > > > return val;
> > > > }
> > > >
> > > > +static u8 intel_dp_get_su_capability(struct intel_dp *intel_dp) {
> > > > + u8 su_capability;
> > > > +
> > > > + if (intel_dp->psr.sink_panel_replay_su_support)
> > >
> > > While relooking found that good to add a check for
> > > DP_PANEL_PANEL_REPLAY_SU_GRANULARITY_REQUIRED (6th bit of dpcd
> > 0xb1).
> > > What if it is zero means granularity not needed but will continue to
> > > use x-granularity and y-granularity.
> >
> > Please note it is 5th bit in 0xb1. See my further comment below...
>
> Same I was referring, 6th bit index 5 as it starts from 0.
>
> >
> > > Regards,
> > > Animesh
> > >
> > > > + drm_dp_dpcd_read(_dp->aux,
> > > > +
> > > > DP_PANEL_PANEL_REPLAY_X_GRANULARITY,
> > > > + _capability, 1);
I think instead of DP_PANEL_PANEL_REPLAY_X_GRANULARITY it should be
DP_PANEL_PANEL_REPLAY_CAPABILITY, everything else will be fine.
Regards,
Animesh
> > > > + else
> > > > + su_capability = intel_dp->psr_dpcd[1];
> > > > +
> > > > + return su_capability;
> > > > +}
> > > > +
> > > > +static unsigned int
> > > > +intel_dp_get_su_x_granularity_offset(struct intel_dp *intel_dp) {
> > > > + return intel_dp->psr.sink_panel_replay_su_support ?
> > > > + DP_PANEL_PANEL_REPLAY_X_GRANULARITY :
> > > > + DP_PSR2_SU_X_GRANULARITY; }
> > > > +
> > > > +static unsigned int
> > > > +intel_dp_get_su_y_granularity_offset(struct intel_dp *intel_dp) {
> > > > + return intel_dp->psr.sink_panel_replay_su_support ?
> > > > + DP_PANEL_PANEL_REPLAY_Y_GRANULARITY :
> > > > + DP_PSR2_SU_Y_GRANULARITY; }
> > > > +
> > > > +/*
> > > > + * Note: Bits related to granularity are same in panel replay and
> > > > psr
> > > > + * registers. Rely on PSR definitions on these "common" bits.
> > > > + */
> >
> > Check this comment. See my further comment below...
>
> Agree bit position is same.
>
> >
> > > > static void intel_dp_get_su_granularity(struct intel_dp
> > > > *intel_dp) {
> > > > struct drm_i915_private
RE: [PATCH v7 06/11] drm/i915/psr: Modify intel_dp_get_su_granularity to support panel replay
> -Original Message-
> From: Hogander, Jouni
> Sent: Monday, April 29, 2024 4:46 PM
> To: Manna, Animesh ; intel-
> g...@lists.freedesktop.org
> Subject: Re: [PATCH v7 06/11] drm/i915/psr: Modify
> intel_dp_get_su_granularity to support panel replay
>
> On Mon, 2024-04-29 at 11:02 +, Manna, Animesh wrote:
> >
> >
> > > -Original Message-
> > > From: Hogander, Jouni
> > > Sent: Friday, April 19, 2024 5:42 PM
> > > To: intel-gfx@lists.freedesktop.org
> > > Cc: Manna, Animesh ; Hogander, Jouni
> > >
> > > Subject: [PATCH v7 06/11] drm/i915/psr: Modify
> > > intel_dp_get_su_granularity
> > > to support panel replay
> > >
> > > Currently intel_dp_get_su_granularity doesn't support panel replay.
> > > This fix modifies it to support panel replay as well.
> > >
> > > v2: rely on PSR definitions on common bits
> > >
> > > Signed-off-by: Jouni Högander
> > > Reviewed-by: Animesh Manna
> > > ---
> > > drivers/gpu/drm/i915/display/intel_psr.c | 62
> > > +---
> > > 1 file changed, 55 insertions(+), 7 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > index b94f8e33ed1f..29400fac13c2 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > @@ -466,6 +466,40 @@ static u8
> > > intel_dp_get_sink_sync_latency(struct
> > > intel_dp *intel_dp)
> > > return val;
> > > }
> > >
> > > +static u8 intel_dp_get_su_capability(struct intel_dp *intel_dp) {
> > > + u8 su_capability;
> > > +
> > > + if (intel_dp->psr.sink_panel_replay_su_support)
> >
> > While relooking found that good to add a check for
> > DP_PANEL_PANEL_REPLAY_SU_GRANULARITY_REQUIRED (6th bit of dpcd
> 0xb1).
> > What if it is zero means granularity not needed but will continue to
> > use x-granularity and y-granularity.
>
> Please note it is 5th bit in 0xb1. See my further comment below...
Same I was referring, 6th bit index 5 as it starts from 0.
>
> > Regards,
> > Animesh
> >
> > > + drm_dp_dpcd_read(_dp->aux,
> > > +
> > > DP_PANEL_PANEL_REPLAY_X_GRANULARITY,
> > > + _capability, 1);
> > > + else
> > > + su_capability = intel_dp->psr_dpcd[1];
> > > +
> > > + return su_capability;
> > > +}
> > > +
> > > +static unsigned int
> > > +intel_dp_get_su_x_granularity_offset(struct intel_dp *intel_dp) {
> > > + return intel_dp->psr.sink_panel_replay_su_support ?
> > > + DP_PANEL_PANEL_REPLAY_X_GRANULARITY :
> > > + DP_PSR2_SU_X_GRANULARITY;
> > > +}
> > > +
> > > +static unsigned int
> > > +intel_dp_get_su_y_granularity_offset(struct intel_dp *intel_dp) {
> > > + return intel_dp->psr.sink_panel_replay_su_support ?
> > > + DP_PANEL_PANEL_REPLAY_Y_GRANULARITY :
> > > + DP_PSR2_SU_Y_GRANULARITY;
> > > +}
> > > +
> > > +/*
> > > + * Note: Bits related to granularity are same in panel replay and
> > > psr
> > > + * registers. Rely on PSR definitions on these "common" bits.
> > > + */
>
> Check this comment. See my further comment below...
Agree bit position is same.
>
> > > static void intel_dp_get_su_granularity(struct intel_dp
> > > *intel_dp) {
> > > struct drm_i915_private *i915 = dp_to_i915(intel_dp); @@ -
> > > 473,18
> > > +507,29 @@ static void intel_dp_get_su_granularity(struct intel_dp
> > > *intel_dp)
> > > u16 w;
> > > u8 y;
> > >
> > > - /* If sink don't have specific granularity requirements set
> > > legacy ones
> > > */
> > > - if (!(intel_dp->psr_dpcd[1] &
> > > DP_PSR2_SU_GRANULARITY_REQUIRED)) {
> > > + /*
> > > + * TODO: Do we need to take into account panel supporting
> > > both PSR
> > > and
> > > + * Panel replay?
> > > + */
> > > +
> > > + /*
> > > + * If sink don't have specific granularity requirements set
> > > legacy
> > > + * ones.
> > >
RE: [PATCH v7 06/11] drm/i915/psr: Modify intel_dp_get_su_granularity to support panel replay
> -Original Message-
> From: Hogander, Jouni
> Sent: Friday, April 19, 2024 5:42 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Hogander, Jouni
>
> Subject: [PATCH v7 06/11] drm/i915/psr: Modify intel_dp_get_su_granularity
> to support panel replay
>
> Currently intel_dp_get_su_granularity doesn't support panel replay.
> This fix modifies it to support panel replay as well.
>
> v2: rely on PSR definitions on common bits
>
> Signed-off-by: Jouni Högander
> Reviewed-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 62 +---
> 1 file changed, 55 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index b94f8e33ed1f..29400fac13c2 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -466,6 +466,40 @@ static u8 intel_dp_get_sink_sync_latency(struct
> intel_dp *intel_dp)
> return val;
> }
>
> +static u8 intel_dp_get_su_capability(struct intel_dp *intel_dp) {
> + u8 su_capability;
> +
> + if (intel_dp->psr.sink_panel_replay_su_support)
While relooking found that good to add a check for
DP_PANEL_PANEL_REPLAY_SU_GRANULARITY_REQUIRED (6th bit of dpcd 0xb1). What if
it is zero means granularity not needed but will continue to use x-granularity
and y-granularity.
Regards,
Animesh
> + drm_dp_dpcd_read(_dp->aux,
> + DP_PANEL_PANEL_REPLAY_X_GRANULARITY,
> + _capability, 1);
> + else
> + su_capability = intel_dp->psr_dpcd[1];
> +
> + return su_capability;
> +}
> +
> +static unsigned int
> +intel_dp_get_su_x_granularity_offset(struct intel_dp *intel_dp) {
> + return intel_dp->psr.sink_panel_replay_su_support ?
> + DP_PANEL_PANEL_REPLAY_X_GRANULARITY :
> + DP_PSR2_SU_X_GRANULARITY;
> +}
> +
> +static unsigned int
> +intel_dp_get_su_y_granularity_offset(struct intel_dp *intel_dp) {
> + return intel_dp->psr.sink_panel_replay_su_support ?
> + DP_PANEL_PANEL_REPLAY_Y_GRANULARITY :
> + DP_PSR2_SU_Y_GRANULARITY;
> +}
> +
> +/*
> + * Note: Bits related to granularity are same in panel replay and psr
> + * registers. Rely on PSR definitions on these "common" bits.
> + */
> static void intel_dp_get_su_granularity(struct intel_dp *intel_dp) {
> struct drm_i915_private *i915 = dp_to_i915(intel_dp); @@ -473,18
> +507,29 @@ static void intel_dp_get_su_granularity(struct intel_dp
> *intel_dp)
> u16 w;
> u8 y;
>
> - /* If sink don't have specific granularity requirements set legacy ones
> */
> - if (!(intel_dp->psr_dpcd[1] &
> DP_PSR2_SU_GRANULARITY_REQUIRED)) {
> + /*
> + * TODO: Do we need to take into account panel supporting both PSR
> and
> + * Panel replay?
> + */
> +
> + /*
> + * If sink don't have specific granularity requirements set legacy
> + * ones.
> + */
> + if (!(intel_dp_get_su_capability(intel_dp) &
> + DP_PSR2_SU_GRANULARITY_REQUIRED)) {
> /* As PSR2 HW sends full lines, we do not care about x
> granularity */
> w = 4;
> y = 4;
> goto exit;
> }
>
> - r = drm_dp_dpcd_read(_dp->aux,
> DP_PSR2_SU_X_GRANULARITY, , 2);
> + r = drm_dp_dpcd_read(_dp->aux,
> + intel_dp_get_su_x_granularity_offset(intel_dp),
> + , 2);
> if (r != 2)
> drm_dbg_kms(>drm,
> - "Unable to read
> DP_PSR2_SU_X_GRANULARITY\n");
> + "Unable to read selective update x granularity\n");
> /*
>* Spec says that if the value read is 0 the default granularity should
>* be used instead.
> @@ -492,10 +537,12 @@ static void intel_dp_get_su_granularity(struct
> intel_dp *intel_dp)
> if (r != 2 || w == 0)
> w = 4;
>
> - r = drm_dp_dpcd_read(_dp->aux,
> DP_PSR2_SU_Y_GRANULARITY, , 1);
> + r = drm_dp_dpcd_read(_dp->aux,
> + intel_dp_get_su_y_granularity_offset(intel_dp),
> + , 1);
> if (r != 1) {
> drm_dbg_kms(>drm,
> - "Unable to read
> DP_PSR2_SU_Y_GRANULARITY\n");
> + "Unable to read selective update y granularity\n");
> y = 4;
> }
> if (y == 0)
> @@ -588,7 +635,8 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
> if (intel_dp->psr_dpcd[0])
> _psr_init_dpcd(intel_dp);
>
> - if (intel_dp->psr.sink_psr2_support)
> + if (intel_dp->psr.sink_psr2_support ||
> + intel_dp->psr.sink_panel_replay_su_support)
> intel_dp_get_su_granularity(intel_dp);
> }
>
> --
> 2.34.1
RE: [PATCH v2 6/6] drm/i915/alpm: Add debugfs for LOBF
> -Original Message-
> From: Nikula, Jani
> Sent: Monday, April 15, 2024 5:23 PM
> To: Manna, Animesh ; intel-
> g...@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org; Hogander, Jouni
> ; Murthy, Arun R ;
> Manna, Animesh
> Subject: Re: [PATCH v2 6/6] drm/i915/alpm: Add debugfs for LOBF
>
> On Fri, 12 Apr 2024, Animesh Manna wrote:
> > For validation purpose add debugfs for LOBF.
> >
> > Signed-off-by: Animesh Manna
> > ---
> > drivers/gpu/drm/i915/display/intel_alpm.c | 47 +++
> > drivers/gpu/drm/i915/display/intel_alpm.h | 2 +
> > .../drm/i915/display/intel_display_debugfs.c | 2 +
> > 3 files changed, 51 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> > b/drivers/gpu/drm/i915/display/intel_alpm.c
> > index ae894c85233c..21dfc06952d7 100644
> > --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> > +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> > @@ -339,3 +339,50 @@ void intel_alpm_configure(struct intel_dp
> > *intel_dp) {
> > lnl_alpm_configure(intel_dp);
> > }
> > +
> > +static int i915_edp_lobf_support_show(struct seq_file *m, void *data)
> > +{
> > + struct intel_connector *connector = m->private;
> > + struct intel_dp *intel_dp = intel_attached_dp(connector);
> > +
> > + seq_printf(m, "LOBF support: = %s",
> > + str_yes_no(intel_dp->lobf_supported));
>
> If you have individual debugfs files, where the name tells you what it's
> about,
> what's the point in printing "LOBF support" here?
>
> Moreover, please be more careful, this now prints "LOBF support: = yes".
> And you'll want the \n in the end.
Ok.
>
> > +
> > + return 0;
> > +}
> > +
> > +DEFINE_SHOW_ATTRIBUTE(i915_edp_lobf_support);
> > +
> > +static int i915_edp_lobf_status_show(struct seq_file *m, void *data)
> > +{
> > + struct intel_connector *connector = m->private;
> > + struct intel_dp *intel_dp = intel_attached_dp(connector);
> > + const char *status;
> > +
> > + if (intel_dp->lobf_enabled)
> > + status = "enabled";
> > + else
> > + status = "disabled";
> > +
> > + seq_printf(m, "LOBF: %s\n", status);
>
> Ditto. But there's also str_enabled_disabled().
>
> I mean you could have a read-only info file which prints all of this info with
> the prefixes. But if it's one attribute per file, why have the extra prints?
> Maybe it should be just alpm info? Idk.
Sure, will go with a single debugfs entry lobf_info. Thanks for the input.
Regards,
Animesh
>
> BR,
> Jani.
>
> > +
> > + return 0;
> > +}
> > +
> > +DEFINE_SHOW_ATTRIBUTE(i915_edp_lobf_status);
> > +
> > +void intel_alpm_lobf_debugfs_add(struct intel_connector *connector) {
> > + struct drm_i915_private *i915 = to_i915(connector->base.dev);
> > + struct dentry *root = connector->base.debugfs_entry;
> > +
> > + if (DISPLAY_VER(i915) >= 20 &&
> > + connector->base.connector_type !=
> DRM_MODE_CONNECTOR_eDP)
> > + return;
> > +
> > + debugfs_create_file("i915_edp_lobf_supported", 0444, root,
> > + connector, _edp_lobf_support_fops);
> > +
> > + debugfs_create_file("i915_edp_lobf_status", 0444, root,
> > + connector, _edp_lobf_status_fops); }
> > diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h
> > b/drivers/gpu/drm/i915/display/intel_alpm.h
> > index c341d2c2b7f7..66e81ed8b2fb 100644
> > --- a/drivers/gpu/drm/i915/display/intel_alpm.h
> > +++ b/drivers/gpu/drm/i915/display/intel_alpm.h
> > @@ -11,6 +11,7 @@
> > struct intel_dp;
> > struct intel_crtc_state;
> > struct drm_connector_state;
> > +struct intel_connector;
> >
> > bool intel_dp_get_aux_less_alpm_status(struct intel_dp *intel_dp);
> > bool intel_alpm_compute_params(struct intel_dp *intel_dp, @@ -19,5
> > +20,6 @@ void intel_alpm_compute_lobf_config(struct intel_dp *intel_dp,
> > struct intel_crtc_state *crtc_state,
> > struct drm_connector_state *conn_state);
> void
> > intel_alpm_configure(struct intel_dp *intel_dp);
> > +void intel_alpm_lobf_debugfs_add(struct intel_connector *connector);
> >
> > #endif
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > b/drivers/gpu/drm/i915/display/intel_dis
RE: [PATCH v2 5/6] drm/i915/alpm: Enable lobf from source in ALPM_CTL
> -Original Message-
> From: Nikula, Jani
> Sent: Monday, April 15, 2024 5:19 PM
> To: Manna, Animesh ; intel-
> g...@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org; Hogander, Jouni
> ; Murthy, Arun R ;
> Manna, Animesh
> Subject: Re: [PATCH v2 5/6] drm/i915/alpm: Enable lobf from source in
> ALPM_CTL
>
> On Fri, 12 Apr 2024, Animesh Manna wrote:
> > Set the Link Off Between Frames Enable bit in ALPM_CTL register.
> >
> > Signed-off-by: Animesh Manna
> > ---
> > drivers/gpu/drm/i915/display/intel_alpm.c | 5 +
> > drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
> > 2 files changed, 6 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> > b/drivers/gpu/drm/i915/display/intel_alpm.c
> > index 699f2f051766..ae894c85233c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> > +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> > @@ -325,6 +325,11 @@ static void lnl_alpm_configure(struct intel_dp
> *intel_dp)
> >ALPM_CTL_EXTENDED_FAST_WAKE_TIME(intel_dp-
> >alpm_parameters.fast_wake_lines);
> > }
> >
> > + if (intel_dp->lobf_supported) {
> > + alpm_ctl |= ALPM_CTL_LOBF_ENABLE;
> > + intel_dp->lobf_enabled = true;
>
> Gut feeling says this should not be part of intel_dp but rather crtc state.
Kept with the same place with alpm parameters, will think over again.
Regards,
Animesh
>
> BR,
> Jani.
>
> > + }
> > +
> > alpm_ctl |=
> > ALPM_CTL_ALPM_ENTRY_CHECK(intel_dp-
> >alpm_parameters.check_entry_lines)
> > ;
> >
> > intel_de_write(dev_priv, ALPM_CTL(cpu_transcoder), alpm_ctl); diff
> > --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 6116c383b543..f61ba582429b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1884,6 +1884,7 @@ struct intel_dp {
> >
> > /* LOBF flags*/
> > bool lobf_supported;
> > + bool lobf_enabled;
> > };
> >
> > enum lspcon_vendor {
>
> --
> Jani Nikula, Intel
RE: [PATCH v2 4/6] drm/i915/alpm: Add compute config for lobf
> -Original Message- > From: Nikula, Jani > Sent: Monday, April 15, 2024 5:18 PM > To: Manna, Animesh ; intel- > g...@lists.freedesktop.org > Cc: dri-de...@lists.freedesktop.org; Hogander, Jouni > ; Murthy, Arun R ; > Manna, Animesh > Subject: Re: [PATCH v2 4/6] drm/i915/alpm: Add compute config for lobf > > On Fri, 12 Apr 2024, Animesh Manna wrote: > > diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h > > b/drivers/gpu/drm/i915/display/intel_alpm.h > > index c45d078e5a6b..c341d2c2b7f7 100644 > > --- a/drivers/gpu/drm/i915/display/intel_alpm.h > > +++ b/drivers/gpu/drm/i915/display/intel_alpm.h > > @@ -10,9 +10,14 @@ > > > > struct intel_dp; > > struct intel_crtc_state; > > +struct drm_connector_state; > > > > +bool intel_dp_get_aux_less_alpm_status(struct intel_dp *intel_dp); > > The names here are supposed to be intel_alpm_*. Is the function in the > wrong place or is the name wrong? Sure, will change the function name to intel_alpm_get_auxless_status(). Regards, Animesh > > BR, > Jani. > > > bool intel_alpm_compute_params(struct intel_dp *intel_dp, > >struct intel_crtc_state *crtc_state); > > +void intel_alpm_compute_lobf_config(struct intel_dp *intel_dp, > > + struct intel_crtc_state *crtc_state, > > + struct drm_connector_state *conn_state); > > void intel_alpm_configure(struct intel_dp *intel_dp); > > > > #endif > > -- > Jani Nikula, Intel
RE: [PATCH v2 2/6] drm/i915/alpm: Move alpm related code to a new file
> -Original Message- > From: Nikula, Jani > Sent: Monday, April 15, 2024 5:17 PM > To: Manna, Animesh ; intel- > g...@lists.freedesktop.org > Cc: dri-de...@lists.freedesktop.org; Hogander, Jouni > ; Murthy, Arun R ; > Manna, Animesh > Subject: Re: [PATCH v2 2/6] drm/i915/alpm: Move alpm related code to a > new file > > On Fri, 12 Apr 2024, Animesh Manna wrote: > > Move ALPM feature related code as it will be used for non-psr panel > > also thorugh LOBF feature. > > > > Signed-off-by: Animesh Manna > > --- > > drivers/gpu/drm/i915/Makefile | 1 + > > drivers/gpu/drm/i915/display/intel_alpm.c | 292 > > ++ drivers/gpu/drm/i915/display/intel_alpm.h | > > 18 ++ drivers/gpu/drm/i915/display/intel_psr.c | 280 > > + > > 4 files changed, 314 insertions(+), 277 deletions(-) create mode > > 100644 drivers/gpu/drm/i915/display/intel_alpm.c > > create mode 100644 drivers/gpu/drm/i915/display/intel_alpm.h > > > > diff --git a/drivers/gpu/drm/i915/Makefile > > b/drivers/gpu/drm/i915/Makefile index af9e871daf1d..c12b7bd98320 > > 100644 > > --- a/drivers/gpu/drm/i915/Makefile > > +++ b/drivers/gpu/drm/i915/Makefile > > @@ -246,6 +246,7 @@ i915-y += \ > > display/intel_atomic.o \ > > display/intel_atomic_plane.o \ > > display/intel_audio.o \ > > + display/intel_alpm.o \ > > display/intel_bios.o \ > > display/intel_bw.o \ > > display/intel_cdclk.o \ > > That's not sorted. Agree. Will take care in next version. Regards, Animesh > > BR, > Jani. > > > -- > Jani Nikula, Intel
RE: [PATCH v2 6/6] drm/i915/alpm: Add debugfs for LOBF
> -Original Message-
> From: Hogander, Jouni
> Sent: Monday, April 15, 2024 3:44 PM
> To: Manna, Animesh ; intel-
> g...@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org; Murthy, Arun R
> ; Nikula, Jani
> Subject: Re: [PATCH v2 6/6] drm/i915/alpm: Add debugfs for LOBF
>
> On Fri, 2024-04-12 at 21:22 +0530, Animesh Manna wrote:
> > For validation purpose add debugfs for LOBF.
> >
> > Signed-off-by: Animesh Manna
> > ---
> > drivers/gpu/drm/i915/display/intel_alpm.c | 47
> > +++
> > drivers/gpu/drm/i915/display/intel_alpm.h | 2 +
> > .../drm/i915/display/intel_display_debugfs.c | 2 +
> > 3 files changed, 51 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> > b/drivers/gpu/drm/i915/display/intel_alpm.c
> > index ae894c85233c..21dfc06952d7 100644
> > --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> > +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> > @@ -339,3 +339,50 @@ void intel_alpm_configure(struct intel_dp
> > *intel_dp)
> > {
> > lnl_alpm_configure(intel_dp);
> > }
> > +
> > +static int i915_edp_lobf_support_show(struct seq_file *m, void
> > *data)
> > +{
> > + struct intel_connector *connector = m->private;
> > + struct intel_dp *intel_dp = intel_attached_dp(connector);
> > +
> > + seq_printf(m, "LOBF support: = %s",
> > + str_yes_no(intel_dp->lobf_supported));
> > +
> > + return 0;
>
> What this debugfs is telling? Lobf may be supported by platform, but not
> enabled because PSR is enabled. Saying LOBF support = no is misleading.
How about "LOBF entry criteria met = yes/no"?
>
> > +}
> > +
> > +DEFINE_SHOW_ATTRIBUTE(i915_edp_lobf_support);
> > +
> > +static int i915_edp_lobf_status_show(struct seq_file *m, void *data)
> > +{
> > + struct intel_connector *connector = m->private;
> > + struct intel_dp *intel_dp = intel_attached_dp(connector);
> > + const char *status;
> > +
> > + if (intel_dp->lobf_enabled)
>
> I think better option is to read it from the registers.
Sure, will add.
Regards,
Animesh
>
> BR,
>
> Jouni Högander
>
> > + status = "enabled";
> > + else
> > + status = "disabled";
> > +
> > + seq_printf(m, "LOBF: %s\n", status);
> > +
> > + return 0;
> > +}
> > +
> > +DEFINE_SHOW_ATTRIBUTE(i915_edp_lobf_status);
> > +
> > +void intel_alpm_lobf_debugfs_add(struct intel_connector *connector) {
> > + struct drm_i915_private *i915 = to_i915(connector->base.dev);
> > + struct dentry *root = connector->base.debugfs_entry;
> > +
> > + if (DISPLAY_VER(i915) >= 20 &&
> > + connector->base.connector_type !=
> DRM_MODE_CONNECTOR_eDP)
> > + return;
> > +
> > + debugfs_create_file("i915_edp_lobf_supported", 0444, root,
> > + connector, _edp_lobf_support_fops);
> > +
> > + debugfs_create_file("i915_edp_lobf_status", 0444, root,
> > + connector, _edp_lobf_status_fops); }
> > diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h
> > b/drivers/gpu/drm/i915/display/intel_alpm.h
> > index c341d2c2b7f7..66e81ed8b2fb 100644
> > --- a/drivers/gpu/drm/i915/display/intel_alpm.h
> > +++ b/drivers/gpu/drm/i915/display/intel_alpm.h
> > @@ -11,6 +11,7 @@
> > struct intel_dp;
> > struct intel_crtc_state;
> > struct drm_connector_state;
> > +struct intel_connector;
> >
> > bool intel_dp_get_aux_less_alpm_status(struct intel_dp *intel_dp);
> > bool intel_alpm_compute_params(struct intel_dp *intel_dp, @@ -19,5
> > +20,6 @@ void intel_alpm_compute_lobf_config(struct intel_dp
> > *intel_dp,
> > struct intel_crtc_state
> > *crtc_state,
> > struct drm_connector_state
> > *conn_state);
> > void intel_alpm_configure(struct intel_dp *intel_dp);
> > +void intel_alpm_lobf_debugfs_add(struct intel_connector *connector);
> >
> > #endif
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > index 0feffe8d4e45..ba1530149836 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > @@ -13,6 +13,7 @@
> > #include "i915_debugfs.h"
> > #include "i915_irq.h"
> > #include "i915_reg.h"
> > +#include "intel_alpm.h"
> > #include "intel_crtc.h"
> > #include "intel_de.h"
> > #include "intel_crtc_state_dump.h"
> > @@ -1542,6 +1543,7 @@ void intel_connector_debugfs_add(struct
> > intel_connector *connector)
> > intel_drrs_connector_debugfs_add(connector);
> > intel_pps_connector_debugfs_add(connector);
> > intel_psr_connector_debugfs_add(connector);
> > + intel_alpm_lobf_debugfs_add(connector);
> >
> > if (connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
> > connector_type == DRM_MODE_CONNECTOR_HDMIA ||
RE: [PATCH v2 5/6] drm/i915/alpm: Enable lobf from source in ALPM_CTL
> -Original Message-
> From: Hogander, Jouni
> Sent: Monday, April 15, 2024 3:39 PM
> To: Manna, Animesh ; intel-
> g...@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org; Murthy, Arun R
> ; Nikula, Jani
> Subject: Re: [PATCH v2 5/6] drm/i915/alpm: Enable lobf from source in
> ALPM_CTL
>
> On Fri, 2024-04-12 at 21:22 +0530, Animesh Manna wrote:
> > Set the Link Off Between Frames Enable bit in ALPM_CTL register.
> >
> > Signed-off-by: Animesh Manna
> > ---
> > drivers/gpu/drm/i915/display/intel_alpm.c | 5 +
> > drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
> > 2 files changed, 6 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> > b/drivers/gpu/drm/i915/display/intel_alpm.c
> > index 699f2f051766..ae894c85233c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> > +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> > @@ -325,6 +325,11 @@ static void lnl_alpm_configure(struct intel_dp
> > *intel_dp)
> > ALPM_CTL_EXTENDED_FAST_WAKE_TIME(intel_dp-
> > >alpm_parameters.fast_wake_lines);
> > }
> >
> > + if (intel_dp->lobf_supported) {
> > + alpm_ctl |= ALPM_CTL_LOBF_ENABLE;
> > + intel_dp->lobf_enabled = true;
> > + }
> > +
>
> I don't see lnl_alpm_configure being called for lobf case in your patches.
Enabling/Disabling LOBF will be done along with alpm(aux-wake/aux-less)
enablement.
Here lobf_supported flag is the switch to enable LOBF or not.
Please let me know if I am missing anything.
Regards,
Animesh
>
> BR,
>
> Jouni Högander
>
> > alpm_ctl |= ALPM_CTL_ALPM_ENTRY_CHECK(intel_dp-
> > >alpm_parameters.check_entry_lines);
> >
> > intel_de_write(dev_priv, ALPM_CTL(cpu_transcoder), alpm_ctl);
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 6116c383b543..f61ba582429b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1884,6 +1884,7 @@ struct intel_dp {
> >
> > /* LOBF flags*/
> > bool lobf_supported;
> > + bool lobf_enabled;
> > };
> >
> > enum lspcon_vendor {
RE: [PATCH v2 4/6] drm/i915/alpm: Add compute config for lobf
> -Original Message-
> From: Hogander, Jouni
> Sent: Monday, April 15, 2024 3:36 PM
> To: Manna, Animesh ; intel-
> g...@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org; Murthy, Arun R
> ; Nikula, Jani
> Subject: Re: [PATCH v2 4/6] drm/i915/alpm: Add compute config for lobf
>
> On Fri, 2024-04-12 at 21:22 +0530, Animesh Manna wrote:
> > Link Off Between Active Frames, is a new feature for eDP that allows
> > the panel to go to lower power state after transmission of data. This
> > is a feature on top of ALPM, AS SDP.
> > Add compute config during atomic-check phase.
> >
> > v1: RFC version.
> > v2: Add separate flag for auxless-alpm. [Jani]
> >
> > Signed-off-by: Animesh Manna
> > ---
> > drivers/gpu/drm/i915/display/intel_alpm.c | 44
> > +++
> > drivers/gpu/drm/i915/display/intel_alpm.h | 5 +++
> > .../drm/i915/display/intel_display_types.h | 4 ++
> > drivers/gpu/drm/i915/display/intel_dp.c | 5 +++
> > 4 files changed, 58 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> > b/drivers/gpu/drm/i915/display/intel_alpm.c
> > index 13bac3e8c8fa..699f2f051766 100644
> > --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> > +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> > @@ -11,6 +11,16 @@
> > #include "intel_dp_aux.h"
> > #include "intel_psr_regs.h"
> >
> > +bool intel_dp_get_aux_less_alpm_status(struct intel_dp *intel_dp) {
> > + u8 alpm_caps = 0;
> > +
> > + if (drm_dp_dpcd_readb(_dp->aux, DP_RECEIVER_ALPM_CAP,
> > + _caps) != 1)
> > + return false;
> > + return alpm_caps & DP_ALPM_AUX_LESS_CAP; }
> > +
> > /*
> > * See Bspec: 71632 for the table
> > *
> > @@ -242,6 +252,40 @@ bool intel_alpm_compute_params(struct intel_dp
> > *intel_dp,
> > return true;
> > }
> >
> > +void intel_alpm_compute_lobf_config(struct intel_dp *intel_dp,
> > + struct intel_crtc_state
> > *crtc_state,
> > + struct drm_connector_state
> > *conn_state)
> > +{
> > + struct drm_display_mode *adjusted_mode = _state-
> > >hw.adjusted_mode;
> > + int waketime_in_lines, first_sdp_position;
> > + int context_latency, guardband;
> > +
> > + intel_dp->lobf_supported = false;
> > +
> > + if (!intel_dp_is_edp(intel_dp))
> > + return;
> > +
> > + if (!intel_dp_as_sdp_supported(intel_dp))
> > + return;
> > +
> > + if (crtc_state->has_psr2 || crtc_state->has_panel_replay)
> > + return;
>
> LOBF is not supported with PSR1? I think checking crtc_state->has_psr is
> enough. That covers PSR1/2 and Panel Replay.
Ok.
>
> > +
> > + if (intel_alpm_compute_params(intel_dp, crtc_state)) {
> > + context_latency = adjusted_mode->crtc_vblank_start -
> > adjusted_mode->crtc_vdisplay;
> > + guardband = adjusted_mode->crtc_vtotal -
> > + adjusted_mode->crtc_vdisplay -
> > context_latency;
> > + first_sdp_position = adjusted_mode->crtc_vtotal -
> > adjusted_mode->crtc_vsync_start;
> > + if (intel_dp->alpm_parameters.auxless_alpm_supported)
> > + waketime_in_lines = intel_dp-
> > >alpm_parameters.io_wake_lines;
> > + else
> > + waketime_in_lines = intel_dp-
> > >alpm_parameters.fast_wake_lines;
> > +
> > + if ((context_latency + guardband) >
> > (first_sdp_position + waketime_in_lines))
> > + intel_dp->lobf_supported = true;
> > + }
>
> You are not checking display version here. This is supported only on LNL and
> onwards.
Sure will add, thought as-sdp-support will take care, but it has display_ver >=
13.
>
> > +}
> > +
> > static void lnl_alpm_configure(struct intel_dp *intel_dp)
> > {
> > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); diff
> > --git a/drivers/gpu/drm/i915/display/intel_alpm.h
> > b/drivers/gpu/drm/i915/display/intel_alpm.h
> > index c45d078e5a6b..c341d2c2b7f7 100644
> > --- a/drivers/gpu/drm/i915/display/intel_alpm.h
> > +++ b/drivers/gpu/drm/i915/display/intel_alpm.h
> > @@ -10,9 +10,14 @@
> >
> > struct intel_dp;
RE: [PATCH] drm/i915/psr: Use crtc_state->port_clock instead of intel_dp->link_rate
> -Original Message-
> From: Hogander, Jouni
> Sent: Tuesday, April 9, 2024 2:28 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Hogander, Jouni
>
> Subject: [PATCH] drm/i915/psr: Use crtc_state->port_clock instead of
> intel_dp->link_rate
>
> Intel_dp->link_rate is not yet set at this point. Instead use crtc_state-
> >port_clock.
>
> Fixes: 0dd21f836983 ("drm/i915/psr: Silence period and lfps half cycle")
> Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 7af974bb41ca..f5b5a9ae 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1276,7 +1276,7 @@ static int
> _lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp,
> aux_less_wake_lines = intel_usecs_to_scanlines(_state-
> >hw.adjusted_mode,
> aux_less_wake_time);
>
> - if (!_lnl_get_silence_period_and_lfps_half_cycle(intel_dp->link_rate,
> + if
> +(!_lnl_get_silence_period_and_lfps_half_cycle(crtc_state->port_clock,
>_period,
>_half_cycle))
> return false;
> --
> 2.34.1
RE: [PATCH v4] drm/i915/panelreplay: Panel replay workaround with VRR
> -Original Message-
> From: Hogander, Jouni
> Sent: Wednesday, April 10, 2024 12:54 PM
> To: Manna, Animesh ; intel-
> g...@lists.freedesktop.org
> Cc: ville.syrj...@linux.intel.com; Murthy, Arun R
> Subject: Re: [PATCH v4] drm/i915/panelreplay: Panel replay workaround with
> VRR
>
> On Thu, 2024-03-28 at 10:13 +0530, Animesh Manna wrote:
> > Panel Replay VSC SDP not getting sent when VRR is enabled and W1 and
> > W2 are 0. So Program Set Context Latency in
> TRANS_SET_CONTEXT_LATENCY
> > register to at least a value of 1.
> >
> > HSD: 14015406119
> >
> > v1: Initial version.
> > v2: Update timings stored in adjusted_mode struct. [Ville]
> > v3: Add WA in compute_config(). [Ville]
> > v4:
> > - Add DISPLAY_VER() check and improve code comment. [Rodrigo]
> > - Introduce centralized intel_crtc_vblank_delay(). [Ville]
> >
> > Signed-off-by: Animesh Manna
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 17 +
> > drivers/gpu/drm/i915/display/intel_display.h | 1 +
> > drivers/gpu/drm/i915/display/intel_psr.c | 4
> > 3 files changed, 22 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 00ac65a14029..7f5c42a14196 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -3840,6 +3840,23 @@ bool intel_crtc_get_pipe_config(struct
> > intel_crtc_state *crtc_state)
> > return true;
> > }
> >
> > +void intel_crtc_vblank_delay(struct intel_crtc_state *crtc_state) {
> > + struct drm_display_mode *adjusted_mode = _state-
> > >hw.adjusted_mode;
> > +
> > + /*
> > + * wa_14015401596 for display versions >= 13.
> > + * Program Set Context Latency in TRANS_SET_CONTEXT_LATENCY
> > register
> > + * to at least a value of 1 when Panel Replay is enabled with
> > VRR.
> > + * Value for TRANS_SET_CONTEXT_LATENCY is calculated by
> > substracting
> > + * crtc_vdisplay from crtc_vblank_start, so incrementing
> > crtc_vblank_start
> > + * by 1 if both are equal.
> > + */
> > + if (crtc_state->vrr.enable && crtc_state->has_panel_replay &&
> > + adjusted_mode->crtc_vblank_start == adjusted_mode-
> > >crtc_vdisplay)
> > + adjusted_mode->crtc_vblank_start += 1; }
> > +
>
> Do you have some specific reason to have this in intel_display.c? How about
> move it to intel_psr.c? You could also use more descriptive name.
> Current name somehow made me think it is some generic function to
> calculate vblank delay. It is actually only for this workaround.
Thanks for review.
As per feedback from rev3 I have added in intel_display.c. Going forward all
vbalnk related adjustment will be added into this function.
https://patchwork.freedesktop.org/series/129632/#rev3
I can move to intel_psr.c if the current version is not acceptable.
Regards,
Animesh
>
> BR,
>
> Jouni Högander
>
>
> > int intel_dotclock_calculate(int link_freq,
> > const struct intel_link_m_n *m_n)
> > {
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.h
> > b/drivers/gpu/drm/i915/display/intel_display.h
> > index f4a0773f0fca..23315eced41e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display.h
> > @@ -413,6 +413,7 @@ bool intel_crtc_is_bigjoiner_master(const struct
> > intel_crtc_state *crtc_state);
> > u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state
> > *crtc_state);
> > struct intel_crtc *intel_master_crtc(const struct intel_crtc_state
> > *crtc_state);
> > bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state);
> > +void intel_crtc_vblank_delay(struct intel_crtc_state *crtc_state);
> > bool intel_pipe_config_compare(const struct intel_crtc_state
> > *current_config,
> > const struct intel_crtc_state
> > *pipe_config,
> > bool fastset); diff --git
> > a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 72cadad09db5..fccef5434e9c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -1430,6 +1430,10 @@ void intel_psr_compute_config(struct intel_dp
> > *intel_dp,
> > if (!(crtc_state->has_panel_replay || crtc_state->has_psr))
> > return;
> >
> > + /* wa_14015401596: display versions 13, 14 */
> > + if (DISPLAY_VER(dev_priv) >= 13)
> > + intel_crtc_vblank_delay(crtc_state);
> > +
> > crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp,
> > crtc_state);
> > }
> >
RE: [PATCH v5 08/19] drm/i915/psr: Unify panel replay enable/disable sink
> -Original Message-
> From: Hogander, Jouni
> Sent: Wednesday, April 3, 2024 2:30 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Hogander, Jouni
>
> Subject: [PATCH v5 08/19] drm/i915/psr: Unify panel replay enable/disable
> sink
>
> Unify enabling and disabling of psr/panel replay for a sink. Modify
> intel_psr_enable_sink accordingly and use it for both cases.
>
> v3:
> - move psr2_su_region_et_valid to be check for PSR2 only
> v2:
> - enable panel replay for sink before link training
> - write ALPM_CONFIG only for PSR
> - add DP_PSR_CRC_VERIFICATION only for PSR
> - take care of disable sink as well
>
> Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 11 ++---
> drivers/gpu/drm/i915/display/intel_psr.c | 60 +---
> drivers/gpu/drm/i915/display/intel_psr.h | 2 +
> 3 files changed, 50 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index a3d3d4942eb1..4cdc218653b1 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2809,15 +2809,14 @@ static void intel_ddi_pre_enable_dp(struct
> intel_atomic_state *state,
> const struct drm_connector_state
> *conn_state) {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>
> - if (HAS_DP20(dev_priv)) {
> + if (HAS_DP20(dev_priv))
> intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder),
> crtc_state);
> - if (crtc_state->has_panel_replay)
> - drm_dp_dpcd_writeb(_dp->aux,
> PANEL_REPLAY_CONFIG,
> -DP_PANEL_REPLAY_ENABLE);
> - }
> +
> + /* Panel replay has to be enabled in sink dpcd before link training. */
> + if (crtc_state->has_panel_replay)
> + intel_psr_enable_sink(enc_to_intel_dp(encoder), crtc_state);
>
> if (DISPLAY_VER(dev_priv) >= 14)
> mtl_ddi_pre_enable_dp(state, encoder, crtc_state,
> conn_state); diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index b7538a4405b8..4355fb02d8fd 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -638,40 +638,59 @@ static bool psr2_su_region_et_valid(struct intel_dp
> *intel_dp)
> return false;
> }
>
> -static void intel_psr_enable_sink(struct intel_dp *intel_dp)
> +static unsigned int intel_psr_get_enable_sink_offset(struct intel_dp
> +*intel_dp) {
> + return intel_dp->psr.panel_replay_enabled ?
> + PANEL_REPLAY_CONFIG : DP_PSR_EN_CFG;
> +}
> +
> +/*
> + * Note: Most of the bits are same in PANEL_REPLAY_CONFIG and
> +DP_PSR_EN_CFG. We
> + * are relying on PSR definitions on these "common" bits.
> + */
> +void intel_psr_enable_sink(struct intel_dp *intel_dp,
> +const struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> u8 dpcd_val = DP_PSR_ENABLE;
>
> - if (intel_dp->psr.panel_replay_enabled)
> - return;
> -
> - if (intel_dp->psr.psr2_enabled) {
> + if (crtc_state->has_psr2) {
> /* Enable ALPM at sink for psr2 */
> - drm_dp_dpcd_writeb(_dp->aux,
> DP_RECEIVER_ALPM_CONFIG,
> -DP_ALPM_ENABLE |
> -
> DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
> + if (!crtc_state->has_panel_replay) {
> + drm_dp_dpcd_writeb(_dp->aux,
> +DP_RECEIVER_ALPM_CONFIG,
> +DP_ALPM_ENABLE |
> +
> DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
> +
> + if (psr2_su_region_et_valid(intel_dp))
> + dpcd_val |=
> DP_PSR_ENABLE_SU_REGION_ET;
> + }
>
> dpcd_val |= DP_PSR_ENABLE_PSR2 |
> DP_PSR_IRQ_HPD_WITH_CRC_ERRORS;
> - if (psr2_su_region_et_valid(intel_dp))
> - dpcd_val |= DP_PSR_ENABLE_SU_REGION_ET;
> } else {
> if (intel_dp->psr.link_standby)
> dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
>
> - if (DISPLAY_VER(dev_priv) >= 8)
> + if (!crtc_state->has_panel_replay && DISPLAY_VER(dev_priv)
> >= 8)
> dpc
RE: [PATCH v5 06/19] drm/i915/psr: Do not write registers/bits not applicable for panel replay
> -Original Message-
> From: Hogander, Jouni
> Sent: Wednesday, April 3, 2024 2:30 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Hogander, Jouni
>
> Subject: [PATCH v5 06/19] drm/i915/psr: Do not write registers/bits not
> applicable for panel replay
>
> Bspec is saying this
> mask register: Only PSR_MASK[Mask FBC modify] and PSR_MASK[Mask
> Hotplug] are used in panel replay mode.
>
> Status register: Only SRD_STATUS[SRD state] field is used in panel replay
> mode.
>
> Due to this stop writing and reading registers and bits not used by panel
> replay if panel replay is used.
>
> Bspec: 53370, 68920
>
> v2:
> - use intel_dp_is_edp with PSR_MASK register
> - handle LunarLake as well
> - hanle ALPM configuration as well
>
> Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 70 +++-
> 1 file changed, 45 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index d7547eefc2fa..b7538a4405b8 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -346,6 +346,9 @@ static void psr_irq_control(struct intel_dp *intel_dp)
> enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
> u32 mask;
>
> + if (intel_dp->psr.panel_replay_enabled)
> + return;
> +
> mask = psr_irq_psr_error_bit_get(intel_dp);
> if (intel_dp->psr.debug & I915_PSR_DEBUG_IRQ)
> mask |= psr_irq_post_exit_bit_get(intel_dp) | @@ -1783,7
> +1786,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
> - u32 mask;
> + u32 mask = 0;
>
> /*
>* Only HSW and BDW have PSR AUX registers that need to be setup.
> @@ -1797,34 +1800,46 @@ static void intel_psr_enable_source(struct
> intel_dp *intel_dp,
>* mask LPSP to avoid dependency on other drivers that might block
>* runtime_pm besides preventing other hw tracking issues now we
>* can rely on frontbuffer tracking.
> + *
> + * From bspec prior LunarLake:
> + * Only PSR_MASK[Mask FBC modify] and PSR_MASK[Mask Hotplug]
> are used in
> + * panel replay mode.
> + *
> + * From bspec beyod LunarLake:
> + * Panel Replay on DP: No bits are applicable
> + * Panel Replay on eDP: All bits are applicable
>*/
> - mask = EDP_PSR_DEBUG_MASK_MEMUP |
> -EDP_PSR_DEBUG_MASK_HPD;
> + if (DISPLAY_VER(dev_priv) < 20 || intel_dp_is_edp(intel_dp))
> + mask = EDP_PSR_DEBUG_MASK_HPD;
>
> - /*
> - * For some unknown reason on HSW non-ULT (or at least on
> - * Dell Latitude E6540) external displays start to flicker
> - * when PSR is enabled on the eDP. SR/PC6 residency is much
> - * higher than should be possible with an external display.
> - * As a workaround leave LPSP unmasked to prevent PSR entry
> - * when external displays are active.
> - */
> - if (DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL_ULT(dev_priv))
> - mask |= EDP_PSR_DEBUG_MASK_LPSP;
> + if (intel_dp_is_edp(intel_dp)) {
> + mask |= EDP_PSR_DEBUG_MASK_MEMUP;
>
> - if (DISPLAY_VER(dev_priv) < 20)
> - mask |= EDP_PSR_DEBUG_MASK_MAX_SLEEP;
> + /*
> + * For some unknown reason on HSW non-ULT (or at least on
> + * Dell Latitude E6540) external displays start to flicker
> + * when PSR is enabled on the eDP. SR/PC6 residency is much
> + * higher than should be possible with an external display.
> + * As a workaround leave LPSP unmasked to prevent PSR
> entry
> + * when external displays are active.
> + */
> + if (DISPLAY_VER(dev_priv) >= 8 ||
> IS_HASWELL_ULT(dev_priv))
> + mask |= EDP_PSR_DEBUG_MASK_LPSP;
>
> - /*
> - * No separate pipe reg write mask on hsw/bdw, so have to unmask
> all
> - * registers in order to keep the CURSURFLIVE tricks working :(
> - */
> - if (IS_DISPLAY_VER(dev_priv, 9, 10))
> - mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE;
> + if (DISPLAY_VER(dev_priv) < 20)
> + mask |= EDP_PSR_DEBUG_MASK_MAX_SLEEP;
>
> - /* allow PSR with sprite enabled */
> - if (IS_HASWELL(dev_priv))
> - mask |= EDP_PSR_DEBUG_
RE: [PATCH v5 04/19] drm/i915/psr: Do not update phy power state in case of non-eDP panel replay
> -Original Message-
> From: Hogander, Jouni
> Sent: Wednesday, April 3, 2024 2:30 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Hogander, Jouni
>
> Subject: [PATCH v5 04/19] drm/i915/psr: Do not update phy power state in
> case of non-eDP panel replay
>
> Currently panel replay is supporting only main link on mode -> Do not update
> phy power state for non-eDP panel replay.
>
> Bspec: 53370
>
> v2: use intel_dp_is_edp to differentiate
>
> Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 12
> 1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index bd99b9953274..07c1ddec2d86 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1930,13 +1930,16 @@ static void intel_psr_enable_locked(struct
> intel_dp *intel_dp,
> if (!psr_interrupt_error_check(intel_dp))
> return;
>
> - if (intel_dp->psr.panel_replay_enabled)
> + if (intel_dp->psr.panel_replay_enabled) {
> drm_dbg_kms(_priv->drm, "Enabling Panel Replay\n");
> - else
> + } else {
> drm_dbg_kms(_priv->drm, "Enabling PSR%s\n",
> intel_dp->psr.psr2_enabled ? "2" : "1");
> + }
> +
> + if (intel_dp_is_edp(intel_dp))
> + intel_snps_phy_update_psr_power_state(_port->base,
> true);
>
> - intel_snps_phy_update_psr_power_state(_port->base, true);
> intel_psr_enable_sink(intel_dp);
> intel_psr_enable_source(intel_dp, crtc_state);
> intel_dp->psr.enabled = true;
> @@ -2041,7 +2044,8 @@ static void intel_psr_disable_locked(struct intel_dp
> *intel_dp)
>CLKGATE_DIS_MISC_DMASC_GATING_DIS,
> 0);
> }
>
> -
> intel_snps_phy_update_psr_power_state(_to_dig_port(intel_dp)
> ->base, false);
> + if (intel_dp_is_edp(intel_dp))
> +
> +intel_snps_phy_update_psr_power_state(_to_dig_port(intel_dp)-
> >base,
> +false);
>
> /* Panel Replay on eDP is always using ALPM aux less. */
> if (intel_dp->psr.panel_replay_enabled &&
> intel_dp_is_edp(intel_dp)) {
> --
> 2.34.1
RE: [PATCH v5 07/19] drm/i915/psr: Call intel_psr_init_dpcd in intel_dp_detect
> -Original Message- > From: Hogander, Jouni > Sent: Wednesday, April 3, 2024 2:30 PM > To: intel-gfx@lists.freedesktop.org > Cc: Manna, Animesh ; Hogander, Jouni > > Subject: [PATCH v5 07/19] drm/i915/psr: Call intel_psr_init_dpcd in > intel_dp_detect > > Currently panel replay dpcd capability isn't properly checked after plugging > in > DP panel. Fix this by calling intel_psr_init_dpcd in intel_dp_detect. > > Signed-off-by: Jouni Högander > --- > drivers/gpu/drm/i915/display/intel_dp.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > b/drivers/gpu/drm/i915/display/intel_dp.c > index b393ddbb7b35..b8976bb67510 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -5744,6 +5744,8 @@ intel_dp_detect(struct drm_connector *connector, > > intel_dp_mst_configure(intel_dp); > > + intel_psr_init_dpcd(intel_dp); > + This is fixed and merged. Regards, Animesh > /* >* TODO: Reset link params when switching to MST mode, until MST >* supports link training fallback params. > -- > 2.34.1
RE: [PATCH v3] drm/i915/panelreplay: Panel replay workaround with VRR
> -Original Message- > From: Ville Syrjälä > Sent: Thursday, February 22, 2024 2:55 AM > To: Vivi, Rodrigo > Cc: Manna, Animesh ; intel- > g...@lists.freedesktop.org; Hogander, Jouni ; > Murthy, Arun R > Subject: Re: [PATCH v3] drm/i915/panelreplay: Panel replay workaround with > VRR > > On Wed, Feb 21, 2024 at 11:08:18PM +0200, Ville Syrjälä wrote: > > On Wed, Feb 21, 2024 at 03:58:48PM -0500, Rodrigo Vivi wrote: > > > On Wed, Feb 21, 2024 at 08:19:35PM +, Manna, Animesh wrote: > > > > > > > > > > > > > -Original Message- > > > > > From: Vivi, Rodrigo > > > > > Sent: Tuesday, February 20, 2024 11:12 PM > > > > > To: Manna, Animesh > > > > > Cc: intel-gfx@lists.freedesktop.org; > > > > > ville.syrj...@linux.intel.com; Hogander, Jouni > > > > > ; Murthy, Arun R > > > > > > > > > > Subject: Re: [PATCH v3] drm/i915/panelreplay: Panel replay > > > > > workaround with VRR > > > > > > > > > > On Tue, Feb 20, 2024 at 07:49:19PM +0530, Animesh Manna wrote: > > > > > > Panel Replay VSC SDP not getting sent when VRR is enabled and > > > > > > W1 and > > > > > > W2 are 0. So Program Set Context Latency in > > > > > TRANS_SET_CONTEXT_LATENCY > > > > > > register to at least a value of 1. > > > > > > > > > > > > HSD: 14015406119 > > > > > > > > > > Unnecessary mark since the wa_name already is a pointer to the HSD. > > > > > > > > > > > > > > > > > v1: Initial version. > > > > > > v2: Update timings stored in adjusted_mode struct. [Ville] > > > > > > v3: Add WA in compute_config(). [Ville] > > > > > > > > > > > > Signed-off-by: Animesh Manna > > > > > > --- > > > > > > drivers/gpu/drm/i915/display/intel_dp.c | 12 > > > > > > 1 file changed, 12 insertions(+) > > > > > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > > > > > > b/drivers/gpu/drm/i915/display/intel_dp.c > > > > > > index 217196196e50..eb0fa513cd0f 100644 > > > > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > > > > > @@ -2948,6 +2948,18 @@ intel_dp_compute_config(struct > > > > > > intel_encoder > > > > > *encoder, > > > > > > intel_dp_compute_vsc_sdp(intel_dp, pipe_config, > conn_state); > > > > > > intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, > > > > > pipe_config, > > > > > > conn_state); > > > > > > > > > > > > + /* > > > > > > +* WA: HSD-14015406119 > > > > > > > > > > this is not the right one. You should use the lineage one and > > > > > then mark the platforms. > > > > > > > > > > /* wa_14015401596: xe_lpd, xe_hpd */ > > > > > > > > > > or perhaps > > > > > > > > > > /* wa_14015401596: display versions: 13, 14 */ > > > > > > > > > > and also add a check for the display version with it. > > > > > > > > Sure. > > > > > > > > > > > > > > > +* Program Set Context Latency in > TRANS_SET_CONTEXT_LATENCY > > > > > register > > > > > > +* to at least a value of 1 when Panel Replay is enabled with > VRR. > > > > > > +* Value for TRANS_SET_CONTEXT_LATENCY is calculated by > > > > > substracting > > > > > > +* crtc_vdisplay from crtc_vblank_start, so incrementing > > > > > crtc_vblank_start > > > > > > +* by 1 if both are equal. > > > > > > +*/ > > > > > > + if (pipe_config->vrr.enable && pipe_config- > >has_panel_replay && > > > > > > + adjusted_mode->crtc_vblank_start == adjusted_mode- > > > > > >crtc_vdisplay) > > > > > > + adjusted_mode->crtc_vblank_start += 1; > > > > > > > > > > why to mess with the vblank start instead of going to > > > > > intel_set_transcoder_timings() and
RE: [PATCH v5 0/5] ALPM AUX-Less
> -Original Message- > From: Hogander, Jouni > Sent: Friday, March 22, 2024 4:00 PM > To: intel-gfx@lists.freedesktop.org > Cc: Ville Syrjälä ; Manna, Animesh > ; Murthy, Arun R ; > Hogander, Jouni > Subject: [PATCH v5 0/5] ALPM AUX-Less > > This patch set is implementing calculation of ALPM AUX-Less parameters for > Intel HW and writing them in case of AUX-Less is enabled. It is also enabling > ALPM AUX-Less for eDP Panel Replay. Current code is not allowing Panel > Replay on eDP. Patches for this are coming later. > > This implementation is only for Panel Replay usage. LOBF (Link Off Between > Active Frames) usage needs more work. > > v5: > - mention AUX Less enable is only on source side in commit message > v4: > - drop patch adding AUX LESS dpcd defines > - re-use fast_wake_lines to store aux_less_wake_lines > - add comment explaining why AUX less is enabled on eDP panel replay > without any extra checks > v3: > - use definitions instead of numbers for max values > - do not use alpm_ctl as uninitialized variable > v2: > - use variables instead of values directly > - fix several max values > - move converting port clock to Mhz into _lnl_compute_* > - do not set AUX-Wake related bits for AUX-Less case > - do not write ALPM configuration for DP2.0 Panel Replay or PSR1 > > Jouni Högander (5): > drm/i915/psr: Add missing ALPM AUX-Less register definitions > drm/i915/psr: Calculate aux less wake time > drm/i915/psr: Silence period and lfps half cycle > drm/i915/psr: Enable ALPM on source side for eDP Panel replay > drm/i915/psr: Do not write ALPM configuration for PSR1 or DP2.0 Panel > Replay The above patches LGTM. For whole patch series: Reviewed-by: Animesh Manna > > .../drm/i915/display/intel_display_types.h| 2 + > drivers/gpu/drm/i915/display/intel_psr.c | 188 +- > drivers/gpu/drm/i915/display/intel_psr_regs.h | 12 +- > 3 files changed, 193 insertions(+), 9 deletions(-) > > -- > 2.34.1
RE: [PATCH v4 4/5] drm/i915/psr: Enable ALPM for eDP Panel replay
> -Original Message-
> From: Hogander, Jouni
> Sent: Friday, March 15, 2024 1:32 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Ville Syrjälä ; Manna, Animesh
> ; Murthy, Arun R ;
> Hogander, Jouni
> Subject: [PATCH v4 4/5] drm/i915/psr: Enable ALPM for eDP Panel replay
>
> Enable ALPM AUX-Less for Panel Replay eDP. Also write all calculated AUX-
> Less configuration values accordingly.
>
> Bspec: 71477
>
> v4:
> - add comment explaining why AUX less is enabled on eDP panel replay
> without any extra checks
> v3:
> - do not use alpm_ctl as uninitialized variable
> v2:
> - do not set AUX-Wake related bits for AUX-Less case
> - drop switch to active latency
> - add SLEEP_HOLD_TIME_50_SYMBOLS
> - add PORT_ALPM_CTL_MAX_PHY_SWING_HOLD
>
> Signed-off-by: Jouni Högander
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 47 ++--
> 1 file changed, 43 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 9429c5002986..05b30dc63b3d 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1721,14 +1721,43 @@ static void lnl_alpm_configure(struct intel_dp
> *intel_dp)
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
> struct intel_psr *psr = _dp->psr;
> + u32 alpm_ctl;
>
> if (DISPLAY_VER(dev_priv) < 20)
> return;
>
> - intel_de_write(dev_priv, ALPM_CTL(cpu_transcoder),
> -ALPM_CTL_EXTENDED_FAST_WAKE_ENABLE |
> -ALPM_CTL_ALPM_ENTRY_CHECK(psr-
> >alpm_parameters.check_entry_lines) |
> -ALPM_CTL_EXTENDED_FAST_WAKE_TIME(psr-
> >alpm_parameters.fast_wake_lines));
> + /*
> + * Panel Replay on eDP is always using ALPM aux less. I.e. no need to
> + * check panel support at this point.
> + */
> + if (intel_dp->psr.panel_replay_enabled &&
> intel_dp_is_edp(intel_dp)) {
> + alpm_ctl = ALPM_CTL_ALPM_ENABLE |
> + ALPM_CTL_ALPM_AUX_LESS_ENABLE |
> +
> ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS;
> +
> + intel_de_write(dev_priv, PORT_ALPM_CTL(cpu_transcoder),
> +PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE |
> +PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(15) |
> +PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(0) |
> +PORT_ALPM_CTL_SILENCE_PERIOD(
> +psr-
> >alpm_parameters.silence_period_sym_clocks));
> +
> + intel_de_write(dev_priv,
> PORT_ALPM_LFPS_CTL(cpu_transcoder),
> +PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(10) |
> +
> PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(
> +psr-
> >alpm_parameters.lfps_half_cycle_num_of_syms) |
> +
> PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(
> +psr-
> >alpm_parameters.lfps_half_cycle_num_of_syms) |
> +
> PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION(
> +psr-
> >alpm_parameters.lfps_half_cycle_num_of_syms));
> + } else {
> + alpm_ctl = ALPM_CTL_EXTENDED_FAST_WAKE_ENABLE |
> + ALPM_CTL_EXTENDED_FAST_WAKE_TIME(psr-
> >alpm_parameters.fast_wake_lines);
> + }
> +
> + alpm_ctl |=
> +ALPM_CTL_ALPM_ENTRY_CHECK(psr-
> >alpm_parameters.check_entry_lines);
> +
> + intel_de_write(dev_priv, ALPM_CTL(cpu_transcoder), alpm_ctl);
> }
>
> static void intel_psr_enable_source(struct intel_dp *intel_dp, @@ -1999,6
> +2028,16 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
>
> intel_snps_phy_update_psr_power_state(dev_priv, phy, false);
>
> + /* Panel Replay on eDP is always using ALPM aux less. */
> + if (intel_dp->psr.panel_replay_enabled &&
> intel_dp_is_edp(intel_dp)) {
> + intel_de_rmw(dev_priv, ALPM_CTL(cpu_transcoder),
> + ALPM_CTL_ALPM_ENABLE |
> + ALPM_CTL_ALPM_AUX_LESS_ENABLE, 0);
> +
> + intel_de_rmw(dev_priv, PORT_ALPM_CTL(cpu_transcoder),
> + PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE, 0);
> + }
This patch only enable source for aux-less alpm. Good to modify the commit
title mentioning the same or else a 'TODO:' comment can be added if sink
support enabling is planned in a separate patch.
Regards,
Animesh
> +
> /* Disable PSR on Sink */
> drm_dp_dpcd_writeb(_dp->aux, DP_PSR_EN_CFG, 0);
>
> --
> 2.34.1
RE: [PATCH v3 6/6] drm/i915/psr: Do not write ALPM configuration for PSR1 or DP2.0 Panel Replay
> -Original Message-
> From: Hogander, Jouni
> Sent: Wednesday, March 6, 2024 4:15 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Ville Syrjälä ; Manna, Animesh
> ; Murthy, Arun R ;
> Hogander, Jouni
> Subject: [PATCH v3 6/6] drm/i915/psr: Do not write ALPM configuration for
> PSR1 or DP2.0 Panel Replay
>
> No need to write ALPM configuration for DP2.0 Panel Replay or PSR1.
>
> Signed-off-by: Jouni Högander
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 4cd2bad5241f..c7bda37444f0 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1699,7 +1699,8 @@ static void lnl_alpm_configure(struct intel_dp
> *intel_dp)
> struct intel_psr *psr = _dp->psr;
> u32 alpm_ctl;
>
> - if (DISPLAY_VER(dev_priv) < 20)
> + if (DISPLAY_VER(dev_priv) < 20 || (!intel_dp->psr.psr2_enabled &&
> +!intel_dp_is_edp(intel_dp)))
This patch maybe good to squash with previous patch, not sure will there be any
negative impact if panel does not support aux-less alpm and from source side it
is enabled.
Regards,
Animesh
> return;
>
> if (intel_dp->psr.panel_replay_enabled &&
> intel_dp_is_edp(intel_dp)) {
> --
> 2.34.1
RE: [PATCH v3 5/6] drm/i915/psr: Enable ALPM for eDP Panel replay
> -Original Message-
> From: Hogander, Jouni
> Sent: Wednesday, March 6, 2024 4:15 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Ville Syrjälä ; Manna, Animesh
> ; Murthy, Arun R ;
> Hogander, Jouni
> Subject: [PATCH v3 5/6] drm/i915/psr: Enable ALPM for eDP Panel replay
>
> Enable ALPM AUX-Less for Panel Replay eDP. Also write all calculated AUX-
> Less configuration values accordingly.
>
> Bspec: 71477
>
> v3:
> - do not use alpm_ctl as uninitialized variable
> v2:
> - do not set AUX-Wake related bits for AUX-Less case
> - drop switch to active latency
> - add SLEEP_HOLD_TIME_50_SYMBOLS
> - add PORT_ALPM_CTL_MAX_PHY_SWING_HOLD
>
> Signed-off-by: Jouni Högander
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 42 +---
> 1 file changed, 38 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 738ea623a395..4cd2bad5241f 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1697,14 +1697,39 @@ static void lnl_alpm_configure(struct intel_dp
> *intel_dp)
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
> struct intel_psr *psr = _dp->psr;
> + u32 alpm_ctl;
>
> if (DISPLAY_VER(dev_priv) < 20)
> return;
>
> - intel_de_write(dev_priv, ALPM_CTL(cpu_transcoder),
> -ALPM_CTL_EXTENDED_FAST_WAKE_ENABLE |
> -ALPM_CTL_ALPM_ENTRY_CHECK(psr-
> >alpm_parameters.check_entry_lines) |
> -ALPM_CTL_EXTENDED_FAST_WAKE_TIME(psr-
> >alpm_parameters.fast_wake_lines));
> + if (intel_dp->psr.panel_replay_enabled &&
> intel_dp_is_edp(intel_dp)) {
> + alpm_ctl = ALPM_CTL_ALPM_ENABLE |
> + ALPM_CTL_ALPM_AUX_LESS_ENABLE |
> +
> ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS;
> +
> + intel_de_write(dev_priv, PORT_ALPM_CTL(cpu_transcoder),
> +PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE |
Good to add code-comments why aux-less alpm is enabled without checking panel
capability.
Same for below wherever we are setting bit for aux-less alpm.
Regards,
Animesh
> +PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(15) |
> +PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(0) |
> +PORT_ALPM_CTL_SILENCE_PERIOD(
> +psr-
> >alpm_parameters.silence_period_sym_clocks));
> +
> + intel_de_write(dev_priv,
> PORT_ALPM_LFPS_CTL(cpu_transcoder),
> +PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(10) |
> +
> PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(
> +psr-
> >alpm_parameters.lfps_half_cycle_num_of_syms) |
> +
> PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(
> +psr-
> >alpm_parameters.lfps_half_cycle_num_of_syms) |
> +
> PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION(
> +psr-
> >alpm_parameters.lfps_half_cycle_num_of_syms));
> + } else {
> + alpm_ctl = ALPM_CTL_EXTENDED_FAST_WAKE_ENABLE |
> + ALPM_CTL_EXTENDED_FAST_WAKE_TIME(psr-
> >alpm_parameters.fast_wake_lines);
> + }
> +
> + alpm_ctl |=
> +ALPM_CTL_ALPM_ENTRY_CHECK(psr-
> >alpm_parameters.check_entry_lines);
> +
> + intel_de_write(dev_priv, ALPM_CTL(cpu_transcoder), alpm_ctl);
> }
>
> static void intel_psr_enable_source(struct intel_dp *intel_dp, @@ -1975,6
> +2000,15 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
>
> intel_snps_phy_update_psr_power_state(dev_priv, phy, false);
>
> + if (intel_dp->psr.panel_replay_enabled &&
> intel_dp_is_edp(intel_dp)) {
> + intel_de_rmw(dev_priv, ALPM_CTL(cpu_transcoder),
> + ALPM_CTL_ALPM_ENABLE |
> + ALPM_CTL_ALPM_AUX_LESS_ENABLE, 0);
> +
> + intel_de_rmw(dev_priv, PORT_ALPM_CTL(cpu_transcoder),
> + PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE, 0);
> + }
> +
> /* Disable PSR on Sink */
> drm_dp_dpcd_writeb(_dp->aux, DP_PSR_EN_CFG, 0);
>
> --
> 2.34.1
RE: [PATCH v3 3/6] drm/i915/psr: Calculate aux less wake time
> -Original Message-
> From: Hogander, Jouni
> Sent: Wednesday, March 6, 2024 4:15 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Ville Syrjälä ; Manna, Animesh
> ; Murthy, Arun R ;
> Hogander, Jouni
> Subject: [PATCH v3 3/6] drm/i915/psr: Calculate aux less wake time
>
> Calculate aux less wake time and store it into alpm_params struct
>
> Bspec: 71477
>
> v3:
> - use ALPM_CTL_AUX_LESS_WAKE_TIME_MASK instead of value 63
> v2:
> - use variables instead of values directly
> - fix max value
> - move converting port clock to Mhz into
> _lnl_compute_aux_less_wake_time
>
> Signed-off-by: Jouni Högander
> ---
> .../drm/i915/display/intel_display_types.h| 1 +
> drivers/gpu/drm/i915/display/intel_psr.c | 60 +++
> 2 files changed, 61 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index e67cd5b02e84..928317acc1bd 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1737,6 +1737,7 @@ struct intel_psr {
>
> /* LNL and beyond */
> u8 check_entry_lines;
> + u8 aux_less_wake_lines;
As aux-wake or aux-less is mutually exclusive can we use existing wake-line
variable for aux-less as well.
Regards,
Animesh
> } alpm_parameters;
>
> ktime_t last_entry_attempt;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 6927785fd6ff..c545ee229684 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1126,6 +1126,63 @@ static bool
> _compute_psr2_sdp_prior_scanline_indication(struct intel_dp *intel_d
> return true;
> }
>
> +/*
> + * AUX-Less Wake Time = CEILING( ((PHY P2 to P0) + tLFPS_Period, Max+
> + * tSilence, Max+ tPHY Establishment + tCDS) / tline)
> + * For the "PHY P2 to P0" latency see the PHY Power Control page
> + * (PHY P2 to P0) :
> +https://gfxspecs.intel.com/Predator/Home/Index/68965
> + * : 12 us
> + * The tLFPS_Period, Max term is 800ns
> + * The tSilence, Max term is 180ns
> + * The tPHY Establishment (a.k.a. t1) term is 50us
> + * The tCDS term is 1 or 2 times t2
> + * t2 = Number ML_PHY_LOCK * tML_PHY_LOCK
> + * Number ML_PHY_LOCK = ( 7 + CEILING( 6.5us / tML_PHY_LOCK ) + 1)
> + * Rounding up the 6.5us padding to the next ML_PHY_LOCK boundary and
> + * adding the "+ 1" term ensures all ML_PHY_LOCK sequences that start
> + * within the CDS period complete within the CDS period regardless of
> + * entry into the period
> + * tML_PHY_LOCK = TPS4 Length * ( 10 / (Link Rate in MHz) )
> + * TPS4 Length = 252 Symbols
> + */
> +static int _lnl_compute_aux_less_wake_time(int port_clock) {
> + int tphy2_p2_to_p0 = 12 * 1000;
> + int tlfps_period_max = 800;
> + int tsilence_max = 180;
> + int t1 = 50 * 1000;
> + int tps4 = 252;
> + int tml_phy_lock = 1000 * 1000 * tps4 * 10 / port_clock;
> + int num_ml_phy_lock = 7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1;
> + int t2 = num_ml_phy_lock * tml_phy_lock;
> + int tcds = 1 * t2;
> +
> + return DIV_ROUND_UP(tphy2_p2_to_p0 + tlfps_period_max +
> tsilence_max +
> + t1 + tcds, 1000);
> +}
> +
> +static int _lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp,
> + struct intel_crtc_state
> *crtc_state)
> {
> + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> + int aux_less_wake_time, aux_less_wake_lines;
> +
> + aux_less_wake_time =
> + _lnl_compute_aux_less_wake_time(crtc_state->port_clock);
> + aux_less_wake_lines = intel_usecs_to_scanlines(_state-
> >hw.adjusted_mode,
> +aux_less_wake_time);
> +
> + if (aux_less_wake_lines > ALPM_CTL_AUX_LESS_WAKE_TIME_MASK)
> + return false;
> +
> + if (i915->display.params.psr_safest_params)
> + aux_less_wake_lines = 63;
> +
> + intel_dp->psr.alpm_parameters.aux_less_wake_lines =
> +aux_less_wake_lines;
> +
> + return true;
> +}
> +
> static bool _lnl_compute_alpm_params(struct intel_dp *intel_dp,
>struct intel_crtc_state *crtc_state) { @@
> -
> 1142,6 +1199,9 @@ static bool _lnl_compute_alpm_params(struct intel_dp
> *intel_dp,
> if (check_entry_lines > 15)
> return false;
>
> + if (!_lnl_compute_aux_less_alpm_params(intel_dp, crtc_state))
> + return false;
> +
> if (i915->display.params.psr_safest_params)
> check_entry_lines = 15;
>
> --
> 2.34.1
RE: [PATCH v3 1/6] drm/display: Add missing aux less alpm wake related bits
> -Original Message- > From: Hogander, Jouni > Sent: Wednesday, March 6, 2024 4:15 PM > To: intel-gfx@lists.freedesktop.org > Cc: Ville Syrjälä ; Manna, Animesh > ; Murthy, Arun R ; > Hogander, Jouni > Subject: [PATCH v3 1/6] drm/display: Add missing aux less alpm wake related > bits > > eDP1.5 adds some more bits into DP_RECEIVER_ALPM_CAP and > DP_RECEIVER_ALPM_CONFIG registers. Add definitions for these. Good to add this patch with the patch series where _CAP and _CONFIG registers will be used. Regards, Animesh > > Signed-off-by: Jouni Högander > --- > include/drm/display/drm_dp.h | 5 - > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h > index 4891bd916d26..651d117d636d 100644 > --- a/include/drm/display/drm_dp.h > +++ b/include/drm/display/drm_dp.h > @@ -232,6 +232,8 @@ > > #define DP_RECEIVER_ALPM_CAP 0x02e /* eDP 1.4 */ > # define DP_ALPM_CAP (1 << 0) > +# define DP_ALPM_PM_STATE_2A_SUPPORT (1 << 1) /* eDP 1.5 */ > +# define DP_ALPM_AUX_LESS_CAP(1 << 2) /* eDP 1.5 */ > > #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f /* eDP 1.4 */ > # define DP_AUX_FRAME_SYNC_CAP (1 << 0) > @@ -677,7 +679,8 @@ > > #define DP_RECEIVER_ALPM_CONFIG 0x116 /* eDP 1.4 */ > # define DP_ALPM_ENABLE (1 << 0) > -# define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1) > +# define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1) /* eDP 1.5 */ > +# define DP_ALPM_MODE_AUX_LESS (1 << 2) /* eDP 1.5 */ > > #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117 /* eDP 1.4 */ > # define DP_AUX_FRAME_SYNC_ENABLE(1 << 0) > -- > 2.34.1
RE: [PATCH 3/3] drm/i915/dsb: Always set DSB_SKIP_WAITS_EN
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: Wednesday, March 6, 2024 9:38 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [PATCH 3/3] drm/i915/dsb: Always set DSB_SKIP_WAITS_EN
>
> From: Ville Syrjälä
>
> Bspec asks us to always set the DSB_SKIP_WAITS_EN bit in DSB_CHICKEN.
> This seems to instruct DSB to skip vblank and scanline waits when PSR is
> entered.
>
> I don't think we have any cases currently where we would want to enter PSR
> while DSB is waiting for something, but let's set the bit anyway to align with
> Bspec's wishes.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_dsb.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
> b/drivers/gpu/drm/i915/display/intel_dsb.c
> index e4515bf92038..4baaa92ceaec 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> @@ -343,12 +343,13 @@ static int intel_dsb_dewake_scanline(const struct
> intel_crtc_state *crtc_state) static u32 dsb_chicken(struct intel_crtc
> *crtc) {
> if (crtc->mode_flags & I915_MODE_FLAG_VRR)
> - return DSB_CTRL_WAIT_SAFE_WINDOW |
> + return DSB_SKIP_WAITS_EN |
> + DSB_CTRL_WAIT_SAFE_WINDOW |
> DSB_CTRL_NO_WAIT_VBLANK |
> DSB_INST_WAIT_SAFE_WINDOW |
> DSB_INST_NO_WAIT_VBLANK;
> else
> - return 0;
> + return DSB_SKIP_WAITS_EN;
> }
>
> static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl,
> --
> 2.43.0
RE: [PATCH 2/3] drm/i915/dsb: Fix DSB vblank waits when using VRR
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: Wednesday, March 6, 2024 9:38 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: sta...@vger.kernel.org
> Subject: [PATCH 2/3] drm/i915/dsb: Fix DSB vblank waits when using VRR
>
> From: Ville Syrjälä
>
> Looks like the undelayed vblank gets signalled exactly when the active period
> ends. That is a problem for DSB+VRR when we are already in vblank and
> expect DSB to start executing as soon as we send the push. Instead of
> starting the DSB just keeps on waiting for the undelayed vblank which won't
> signal until the end of the next frame's active period, which is far too late.
>
> The end result is that DSB won't have even started executing by the time the
> flips/etc. have completed.
> We then wait for an extra 1ms, after which we terminate the DSB and report
> a timeout:
> [drm] *ERROR* [CRTC:80:pipe A] DSB 0 timed out waiting for idle (current
> head=0xfedf4000, head=0x0, tail=0x1080)
>
> To fix this let's configure DSB to use the so called VRR "safe window" instead
> of the undelayed vblank to trigger the DSB vblank logic, when VRR is enabled.
>
> Cc: sta...@vger.kernel.org
> Fixes: 34d8311f4a1c ("drm/i915/dsb: Re-instate DSB for LUT updates")
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9927
> Signed-off-by: Ville Syrjälä
LGTM.
Reviewed-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_dsb.c | 14 ++
> 1 file changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
> b/drivers/gpu/drm/i915/display/intel_dsb.c
> index d62e050185e7..e4515bf92038 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> @@ -340,6 +340,17 @@ static int intel_dsb_dewake_scanline(const struct
> intel_crtc_state *crtc_state)
> return max(0, vblank_start -
> intel_usecs_to_scanlines(adjusted_mode, latency)); }
>
> +static u32 dsb_chicken(struct intel_crtc *crtc) {
> + if (crtc->mode_flags & I915_MODE_FLAG_VRR)
> + return DSB_CTRL_WAIT_SAFE_WINDOW |
> + DSB_CTRL_NO_WAIT_VBLANK |
> + DSB_INST_WAIT_SAFE_WINDOW |
> + DSB_INST_NO_WAIT_VBLANK;
> + else
> + return 0;
> +}
> +
> static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl,
> int dewake_scanline)
> {
> @@ -361,6 +372,9 @@ static void _intel_dsb_commit(struct intel_dsb *dsb,
> u32 ctrl,
> intel_de_write_fw(dev_priv, DSB_CTRL(pipe, dsb->id),
> ctrl | DSB_ENABLE);
>
> + intel_de_write_fw(dev_priv, DSB_CHICKEN(pipe, dsb->id),
> + dsb_chicken(crtc));
> +
> intel_de_write_fw(dev_priv, DSB_HEAD(pipe, dsb->id),
> intel_dsb_buffer_ggtt_offset(>dsb_buf));
>
> --
> 2.43.0
RE: [PATCH 1/3] drm/i915/vrr: Generate VRR "safe window" for DSB
> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: Wednesday, March 6, 2024 9:38 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: sta...@vger.kernel.org
> Subject: [PATCH 1/3] drm/i915/vrr: Generate VRR "safe window" for DSB
>
> From: Ville Syrjälä
>
> Looks like TRANS_CHICKEN bit 31 means something totally different
> depending on the platform:
> TGL: generate VRR "safe window" for DSB
> ADL/DG2: make TRANS_SET_CONTEXT_LATENCY effective with VRR
>
> So far we've only set this on ADL/DG2, but when using DSB+VRR we also
> need to set it on TGL.
>
> And a quick test on MTL says it doesn't need this bit for either of those
> purposes, even though it's still documented as valid in bspec.
>
> Cc: sta...@vger.kernel.org
> Fixes: 34d8311f4a1c ("drm/i915/dsb: Re-instate DSB for LUT updates")
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9927
> Signed-off-by: Ville Syrjälä
LGTM.
Reviewed-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_vrr.c | 7 ---
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> 2 files changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
> b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 5d905f932cb4..eb5bd0743902 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -187,10 +187,11 @@ void intel_vrr_set_transcoder_timings(const struct
> intel_crtc_state *crtc_state)
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>
> /*
> - * TRANS_SET_CONTEXT_LATENCY with VRR enabled
> - * requires this chicken bit on ADL/DG2.
> + * This bit seems to have two meanings depending on the platform:
> + * TGL: generate VRR "safe window" for DSB vblank waits
> + * ADL/DG2: make TRANS_SET_CONTEXT_LATENCY effective with VRR
>*/
> - if (DISPLAY_VER(dev_priv) == 13)
> + if (IS_DISPLAY_VER(dev_priv, 12, 13))
> intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder),
>0, PIPE_VBLANK_WITH_DELAY);
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h index e00557e1a57f..3b2e49ce29ba
> 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4599,7 +4599,7 @@
> #define MTL_CHICKEN_TRANS(trans) _MMIO_TRANS((trans), \
> _MTL_CHICKEN_TRANS_A,
> \
> _MTL_CHICKEN_TRANS_B)
> -#define PIPE_VBLANK_WITH_DELAY REG_BIT(31) /* ADL/DG2 */
> +#define PIPE_VBLANK_WITH_DELAY REG_BIT(31) /* tgl+ */
> #define SKL_UNMASK_VBL_TO_PIPE_IN_SRD REG_BIT(30) /* skl+ */
> #define HSW_FRAME_START_DELAY_MASK REG_GENMASK(28, 27)
> #define HSW_FRAME_START_DELAY(x)
> REG_FIELD_PREP(HSW_FRAME_START_DELAY_MASK, x)
> --
> 2.43.0
RE: [RFC 2/3] drm/i915/alpm: Add compute config for lobf
> -Original Message-
> From: Jani Nikula
> Sent: Monday, March 4, 2024 11:03 PM
> To: Manna, Animesh ; intel-
> g...@lists.freedesktop.org
> Cc: Hogander, Jouni ; Murthy, Arun R
> ; Manna, Animesh
> Subject: Re: [RFC 2/3] drm/i915/alpm: Add compute config for lobf
>
> On Mon, 04 Mar 2024, Animesh Manna
> wrote:
> > Link Off Between Active Frames, is a new feature for eDP that allows
> > the panel to go to lower power state after transmission of data. This
> > is a feature on top of ALPM, AS SDP.
> > Add compute config during atomic-check phase.
> >
> > Signed-off-by: Animesh Manna
> > ---
> > .../drm/i915/display/intel_display_types.h| 3 ++
> > drivers/gpu/drm/i915/display/intel_dp.c | 1 +
> > drivers/gpu/drm/i915/display/intel_psr.c | 45 +++
> > drivers/gpu/drm/i915/display/intel_psr.h | 3 ++
> > 4 files changed, 52 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index d473d8dca90a..4d2161eeb686 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1851,6 +1851,9 @@ struct intel_dp {
> > u8 silence_period_sym_clocks;
> > u8 lfps_half_cycle_num_of_syms;
> > } alpm_parameters;
> > +
> > + /* LOBF flags*/
> > + bool lobf_supported;
> > };
> >
> > enum lspcon_vendor {
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 8304ef912767..e34b70d88b9a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -2979,6 +2979,7 @@ intel_dp_compute_config(struct intel_encoder
> *encoder,
> > intel_vrr_compute_config(pipe_config, conn_state);
> > intel_dp_compute_as_sdp(intel_dp, pipe_config, conn_state);
> > intel_psr_compute_config(intel_dp, pipe_config, conn_state);
> > + intel_psr_lobf_compute_config(intel_dp, pipe_config, conn_state);
> > intel_dp_drrs_compute_config(connector, pipe_config,
> link_bpp_x16);
> > intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
> > intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp,
> pipe_config,
> > conn_state); diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 4adcddba69c1..c08bffc2921a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -436,6 +436,16 @@ static bool intel_dp_get_alpm_status(struct
> intel_dp *intel_dp)
> > return alpm_caps & DP_ALPM_CAP;
> > }
> >
> > +static bool intel_dp_get_aux_less_alpm_status(struct intel_dp
> > +*intel_dp) {
> > + u8 alpm_caps = 0;
> > +
> > + if (drm_dp_dpcd_readb(_dp->aux, DP_RECEIVER_ALPM_CAP,
> > + _caps) != 1)
>
> The compute config path must not access the hardware.
Sure, will put in init_connector() and store in a variable.
Regards,
Animesh
>
> BR,
> Jani.
>
> > + return false;
> > + return alpm_caps & DP_ALPM_AUX_LESS_CAP; }
> > +
> > static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp)
> > {
> > struct drm_i915_private *i915 = dp_to_i915(intel_dp); @@ -1569,6
> > +1579,41 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
> > crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp,
> > crtc_state); }
> >
> > +void intel_psr_lobf_compute_config(struct intel_dp *intel_dp,
> > + struct intel_crtc_state *crtc_state,
> > + struct drm_connector_state *conn_state) {
> > + struct drm_display_mode *adjusted_mode = _state-
> >hw.adjusted_mode;
> > + int waketime_in_lines, first_sdp_position;
> > + int context_latency, guardband;
> > + bool auxless_alpm;
> > +
> > + intel_dp->lobf_supported = false;
> > +
> > + if (!intel_dp_is_edp(intel_dp))
> > + return;
> > +
> > + if (!intel_dp_as_sdp_supported(intel_dp))
> > + return;
> > +
> > + if (CAN_PSR(intel_dp) || CAN_PANEL_REPLAY(intel_dp))
> > + return;
> > +
> > + if (_compute_alpm_params(intel_dp, crtc_state)) {
> > + context_latency = adjusted_mode->crtc_vblank_start -
> adjusted_mode->crtc_vdisplay;
> > + guardband = adjuste
RE: [PATCH v2] drm/i915/panelreplay: Move out psr_init_dpcd() from init_connector()
> -Original Message-
> From: Nikula, Jani
> Sent: Thursday, February 29, 2024 4:28 PM
> To: Manna, Animesh ; intel-
> g...@lists.freedesktop.org
> Cc: ville.syrj...@linux.intel.com; Hogander, Jouni
> ; Murthy, Arun R ;
> Manna, Animesh
> Subject: Re: [PATCH v2] drm/i915/panelreplay: Move out psr_init_dpcd()
> from init_connector()
>
> On Thu, 29 Feb 2024, Animesh Manna wrote:
> > Move psr_init_dpcd() from init-connector to connector-detect function.
> > The dpcd probe for checking panel replay capability for external dp
> > connector is causing delay during boot which can be optimized by
> > moving dpcd probe to connector specific detect().
> >
> > v1: Initial version.
> > v2: Add details in commit description. [Jani]
> >
> > Suggested-by: Ville Syrjälä
> > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/10284
>
> Fixes: cceeaa312d39 ("drm/i915/panelreplay: Enable panel replay dpcd
> initialization for DP")
> Reviewed-by: Jani Nikula
Thanks for review. Pushed the change in din.
Regards,
Animesh
>
> > Signed-off-by: Animesh Manna
> > ---
> > drivers/gpu/drm/i915/display/intel_dp.c | 3 +++
> > drivers/gpu/drm/i915/display/intel_psr.c | 3 ---
> > 2 files changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 6ece2c563c7a..b485ec320085 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -5709,6 +5709,9 @@ intel_dp_detect(struct drm_connector
> *connector,
> > if (ret == 1)
> > intel_connector->base.epoch_counter++;
> >
> > + if (!intel_dp_is_edp(intel_dp))
> > + intel_psr_init_dpcd(intel_dp);
> > +
> > intel_dp_detect_dsc_caps(intel_dp, intel_connector);
> >
> > intel_dp_configure_mst(intel_dp);
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 72cadad09db5..6927785fd6ff 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -2883,9 +2883,6 @@ void intel_psr_init(struct intel_dp *intel_dp)
> > if (!(HAS_PSR(dev_priv) || HAS_DP20(dev_priv)))
> > return;
> >
> > - if (!intel_dp_is_edp(intel_dp))
> > - intel_psr_init_dpcd(intel_dp);
> > -
> > /*
> > * HSW spec explicitly says PSR is tied to port A.
> > * BDW+ platforms have a instance of PSR registers per transcoder
> > but
>
> --
> Jani Nikula, Intel
RE: [PATCH] drm/i915/panelreplay: Move out psr_init_dpcd() from init_connector()
> -Original Message- > From: Jani Nikula > Sent: Monday, February 26, 2024 11:17 PM > To: Manna, Animesh ; intel- > g...@lists.freedesktop.org > Cc: ville.syrj...@linux.intel.com; Hogander, Jouni > ; Murthy, Arun R ; > Manna, Animesh > Subject: Re: [PATCH] drm/i915/panelreplay: Move out psr_init_dpcd() from > init_connector() > > On Thu, 22 Feb 2024, Animesh Manna wrote: > > Move psr_init_dpcd() from init-connector to connector-detect function. > > Why? > > The commit message *must* *always* answer the question why, unless the > reason is completely and utterly obvious (e.g. don't need to say why typos > need to be fixed). Agree, will add. Thanks for review. Regards, Animesh > > BR, > Jani. > > > Signed-off-by: Animesh Manna > > --- > > drivers/gpu/drm/i915/display/intel_dp.c | 3 +++ > > drivers/gpu/drm/i915/display/intel_psr.c | 3 --- > > 2 files changed, 3 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > > b/drivers/gpu/drm/i915/display/intel_dp.c > > index 217196196e50..4553e1f5f1fc 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > @@ -5709,6 +5709,9 @@ intel_dp_detect(struct drm_connector > *connector, > > goto out; > > } > > > > + if (!intel_dp_is_edp(intel_dp)) > > + intel_psr_init_dpcd(intel_dp); > > + > > intel_dp_detect_dsc_caps(intel_dp, intel_connector); > > > > intel_dp_configure_mst(intel_dp); > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > > b/drivers/gpu/drm/i915/display/intel_psr.c > > index 72cadad09db5..6927785fd6ff 100644 > > --- a/drivers/gpu/drm/i915/display/intel_psr.c > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > > @@ -2883,9 +2883,6 @@ void intel_psr_init(struct intel_dp *intel_dp) > > if (!(HAS_PSR(dev_priv) || HAS_DP20(dev_priv))) > > return; > > > > - if (!intel_dp_is_edp(intel_dp)) > > - intel_psr_init_dpcd(intel_dp); > > - > > /* > > * HSW spec explicitly says PSR is tied to port A. > > * BDW+ platforms have a instance of PSR registers per transcoder > > but > > -- > Jani Nikula, Intel
RE: [PATCH v2 2/6] drm/i915/psr: Calculate aux less wake time
> -Original Message-
> From: Intel-gfx On Behalf Of Jouni
> Högander
> Sent: Tuesday, February 20, 2024 5:41 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Hogander, Jouni
> Subject: [PATCH v2 2/6] drm/i915/psr: Calculate aux less wake time
>
> Calculate aux less wake time and store it into alpm_params struct
>
> Bspec: 71477
>
> v2:
> - use variables instead of values directly
> - fix max value
> - move converting port clock to Mhz into
> _lnl_compute_aux_less_wake_time
>
> Signed-off-by: Jouni Högander
> ---
> .../drm/i915/display/intel_display_types.h| 1 +
> drivers/gpu/drm/i915/display/intel_psr.c | 60 +++
> 2 files changed, 61 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 0d4012097db1..a531c1e5af20 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1721,6 +1721,7 @@ struct intel_psr {
>
> /* LNL and beyond */
> u8 check_entry_lines;
> + u8 aux_less_wake_lines;
> } alpm_parameters;
>
> ktime_t last_entry_attempt;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 72cadad09db5..83f3cab31878 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1126,6 +1126,63 @@ static bool
> _compute_psr2_sdp_prior_scanline_indication(struct intel_dp *intel_d
> return true;
> }
>
> +/*
> + * AUX-Less Wake Time = CEILING( ((PHY P2 to P0) + tLFPS_Period, Max+
> + * tSilence, Max+ tPHY Establishment + tCDS) / tline)
> + * For the "PHY P2 to P0" latency see the PHY Power Control page
> + * (PHY P2 to P0) :
> +https://gfxspecs.intel.com/Predator/Home/Index/68965
> + * : 12 us
> + * The tLFPS_Period, Max term is 800ns
> + * The tSilence, Max term is 180ns
> + * The tPHY Establishment (a.k.a. t1) term is 50us
> + * The tCDS term is 1 or 2 times t2
> + * t2 = Number ML_PHY_LOCK * tML_PHY_LOCK
> + * Number ML_PHY_LOCK = ( 7 + CEILING( 6.5us / tML_PHY_LOCK ) + 1)
> + * Rounding up the 6.5us padding to the next ML_PHY_LOCK boundary and
> + * adding the "+ 1" term ensures all ML_PHY_LOCK sequences that start
> + * within the CDS period complete within the CDS period regardless of
> + * entry into the period
> + * tML_PHY_LOCK = TPS4 Length * ( 10 / (Link Rate in MHz) )
> + * TPS4 Length = 252 Symbols
> + */
> +static int _lnl_compute_aux_less_wake_time(int port_clock) {
> + int tphy2_p2_to_p0 = 12 * 1000;
> + int tlfps_period_max = 800;
> + int tsilence_max = 180;
> + int t1 = 50 * 1000;
> + int tps4 = 252;
> + int tml_phy_lock = 1000 * 1000 * tps4 * 10 / port_clock;
> + int num_ml_phy_lock = 7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1;
> + int t2 = num_ml_phy_lock * tml_phy_lock;
> + int tcds = 1 * t2;
> +
> + return DIV_ROUND_UP(tphy2_p2_to_p0 + tlfps_period_max +
> tsilence_max +
> + t1 + tcds, 1000);
> +}
> +
> +static int _lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp,
> + struct intel_crtc_state
> *crtc_state)
> {
> + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> + int aux_less_wake_time, aux_less_wake_lines;
> +
> + aux_less_wake_time =
> + _lnl_compute_aux_less_wake_time(crtc_state->port_clock);
> + aux_less_wake_lines = intel_usecs_to_scanlines(_state-
> >hw.adjusted_mode,
> +aux_less_wake_time);
> +
> + if (aux_less_wake_lines > 63)
> + return false;
> +
> + if (i915->display.params.psr_safest_params)
> + aux_less_wake_lines = 63;
Overall changes looks good to me, just a nitpick - good to have some macro
instead of magic number 63.
Regards,
Animesh
> +
> + intel_dp->psr.alpm_parameters.aux_less_wake_lines =
> +aux_less_wake_lines;
> +
> + return true;
> +}
> +
> static bool _lnl_compute_alpm_params(struct intel_dp *intel_dp,
>struct intel_crtc_state *crtc_state) { @@
> -
> 1142,6 +1199,9 @@ static bool _lnl_compute_alpm_params(struct intel_dp
> *intel_dp,
> if (check_entry_lines > 15)
> return false;
>
> + if (!_lnl_compute_aux_less_alpm_params(intel_dp, crtc_state))
> + return false;
> +
> if (i915->display.params.psr_safest_params)
> check_entry_lines = 15;
>
> --
> 2.34.1
RE: [PATCH v3] drm/i915/panelreplay: Panel replay workaround with VRR
> -Original Message- > From: Vivi, Rodrigo > Sent: Tuesday, February 20, 2024 11:12 PM > To: Manna, Animesh > Cc: intel-gfx@lists.freedesktop.org; ville.syrj...@linux.intel.com; Hogander, > Jouni ; Murthy, Arun R > > Subject: Re: [PATCH v3] drm/i915/panelreplay: Panel replay workaround with > VRR > > On Tue, Feb 20, 2024 at 07:49:19PM +0530, Animesh Manna wrote: > > Panel Replay VSC SDP not getting sent when VRR is enabled and W1 and > > W2 are 0. So Program Set Context Latency in > TRANS_SET_CONTEXT_LATENCY > > register to at least a value of 1. > > > > HSD: 14015406119 > > Unnecessary mark since the wa_name already is a pointer to the HSD. > > > > > v1: Initial version. > > v2: Update timings stored in adjusted_mode struct. [Ville] > > v3: Add WA in compute_config(). [Ville] > > > > Signed-off-by: Animesh Manna > > --- > > drivers/gpu/drm/i915/display/intel_dp.c | 12 > > 1 file changed, 12 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > > b/drivers/gpu/drm/i915/display/intel_dp.c > > index 217196196e50..eb0fa513cd0f 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > @@ -2948,6 +2948,18 @@ intel_dp_compute_config(struct intel_encoder > *encoder, > > intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state); > > intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, > pipe_config, > > conn_state); > > > > + /* > > +* WA: HSD-14015406119 > > this is not the right one. You should use the lineage one and then mark the > platforms. > > /* wa_14015401596: xe_lpd, xe_hpd */ > > or perhaps > > /* wa_14015401596: display versions: 13, 14 */ > > and also add a check for the display version with it. Sure. > > > +* Program Set Context Latency in TRANS_SET_CONTEXT_LATENCY > register > > +* to at least a value of 1 when Panel Replay is enabled with VRR. > > +* Value for TRANS_SET_CONTEXT_LATENCY is calculated by > substracting > > +* crtc_vdisplay from crtc_vblank_start, so incrementing > crtc_vblank_start > > +* by 1 if both are equal. > > +*/ > > + if (pipe_config->vrr.enable && pipe_config->has_panel_replay && > > + adjusted_mode->crtc_vblank_start == adjusted_mode- > >crtc_vdisplay) > > + adjusted_mode->crtc_vblank_start += 1; > > why to mess with the vblank start instead of going to > intel_set_transcoder_timings() and change directly what is getting written to > the register when the register gets written? I have done in previous version of this patch. But as per review feedback, added now here. https://patchwork.freedesktop.org/series/129632/#rev1 https://patchwork.freedesktop.org/series/129632/#rev2 > > In case the answer is becasue by then we don't have the vrr.enable or > something like that, then we should consider move around when we set that > register? This was not acceptable in earlier versions. As per feedback instead of atomic-commit need to add in compute-config phase. > > or perhaps create a specific flag? one extra variable, 3 less comment lines... The above comment is not clear to me, can you please elaborate more here. Regards, Animesh > > > + > > return 0; > > } > > > > -- > > 2.29.0 > >
RE: [PATCH v3 06/21] drm/i915/psr: Check possible errors for panel replay as well
> -Original Message-
> From: Hogander, Jouni
> Sent: Friday, February 2, 2024 1:50 PM
> To: Manna, Animesh ; intel-
> g...@lists.freedesktop.org
> Subject: Re: [PATCH v3 06/21] drm/i915/psr: Check possible errors for panel
> replay as well
>
> On Fri, 2024-02-02 at 08:10 +, Manna, Animesh wrote:
> >
> >
> > > -Original Message-
> > > From: Hogander, Jouni
> > > Sent: Friday, January 19, 2024 3:40 PM
> > > To: intel-gfx@lists.freedesktop.org
> > > Cc: Manna, Animesh ; Hogander, Jouni
> > >
> > > Subject: [PATCH v3 06/21] drm/i915/psr: Check possible errors for
> > > panel replay as well
> > >
> > > On HPD interrupt we want to check if the reason for HPD was some
> > > panel replay error detected by monitor/panel. This is already done
> > > for PSR. We want to do this for panel replay as well. Modify
> > > intel_psr_short_pulse to support panel replay as well.
> > >
> > > Signed-off-by: Jouni Högander
> > > ---
> > > drivers/gpu/drm/i915/display/intel_psr.c | 21
> > > -
> > > 1 file changed, 16 insertions(+), 5 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > index 893c72ea8cf1..6d7ef74201d2 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > @@ -2959,6 +2959,13 @@ static void
> > > psr_capability_changed_check(struct
> > > intel_dp *intel_dp)
> > > }
> > > }
> > >
> > > +/*
> > > + * On common bits:
> > > + * DP_PSR_RFB_STORAGE_ERROR ==
> > > DP_PANEL_REPLAY_RFB_STORAGE_ERROR
> > > + * DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR ==
> > > +DP_PANEL_REPLAY_VSC_SDP_UNCORRECTABLE_ERROR
> > > + * DP_PSR_LINK_CRC_ERROR == DP_PANEL_REPLAY_LINK_CRC_ERROR
> > > + * this function is relying on PSR definitions */
> > > void intel_psr_short_pulse(struct intel_dp *intel_dp) {
> > > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); @@
> > > -
> > > 2968,7 +2975,7 @@ void intel_psr_short_pulse(struct intel_dp
> > > *intel_dp)
> > > DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR |
> > > DP_PSR_LINK_CRC_ERROR;
> > >
> > > - if (!CAN_PSR(intel_dp))
> > > + if (!CAN_PSR(intel_dp) && !CAN_PANEL_REPLAY(intel_dp))
> >
> > I feel here the condition check would be:
> > if (!(CAN_PSR(intel_dp) || CAN_PANEL_REPLAY(intel_dp)))
>
> This is matter of taste. Received some time ago opposing comment. I don't
> have strong opinion on this. I.e I can change it.
>
> >
> > > return;
> > >
> > > mutex_lock(>lock);
> > > @@ -2982,12 +2989,14 @@ void intel_psr_short_pulse(struct intel_dp
> > > *intel_dp)
> > > goto exit;
> > > }
> > >
> > > - if (status == DP_PSR_SINK_INTERNAL_ERROR || (error_status &
> > > errors)) {
> > > + if ((!psr->panel_replay_enabled && status ==
> > > DP_PSR_SINK_INTERNAL_ERROR) ||
> > > + (error_status & errors)) {
> >
> > This will check only for psr, rt? .. The flag panel_replay_enabled
> > will be true and will not check for error status for panel-replay.
>
> I think DP_PSR_SINK_INTERNAL_ERROR is only in PSR status register.
> error_status bits are for both and they are still checked.
>
> >
> > > intel_psr_disable_locked(intel_dp);
> > > psr->sink_not_reliable = true;
> > > }
> > >
> > > - if (status == DP_PSR_SINK_INTERNAL_ERROR && !error_status)
> > > + if (!psr->panel_replay_enabled && status ==
> > > DP_PSR_SINK_INTERNAL_ERROR &&
> > > + !error_status)
> >
> > Same doubt as above.
>
> DP_PSR_SINK_INTERNAL_ERROR doesn't exist in Panel Replay status register.
> I.e. if panel replay is enabled do not check further for internal error or
> error
> status bits.
Ok. LGTM.
Reviewed-by: Animesh Manna
>
> BR,
>
> Jouni Högander
>
> >
> > Regards,
> > Animesh
> >
> > > drm_dbg_kms(_priv->drm,
> > > "PSR sink internal error, disabling
> > > PSR\n");
> > > if (error_status & DP_PSR_RFB_STORAGE_ERROR) @@ -3007,8
> > > +3016,10 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp)
> > > /* clear status register */
> > > drm_dp_dpcd_writeb(_dp->aux, DP_PSR_ERROR_STATUS,
> > > error_status);
> > >
> > > - psr_alpm_check(intel_dp);
> > > - psr_capability_changed_check(intel_dp);
> > > + if (!psr->panel_replay_enabled) {
> > > + psr_alpm_check(intel_dp);
> > > + psr_capability_changed_check(intel_dp);
> > > + }
> > >
> > > exit:
> > > mutex_unlock(>lock);
> > > --
> > > 2.34.1
> >
RE: [PATCH v3 04/21] drm/i915/psr: Rename intel_psr_enabled
> -Original Message-
> From: Hogander, Jouni
> Sent: Friday, February 2, 2024 1:17 PM
> To: Manna, Animesh ; intel-
> g...@lists.freedesktop.org
> Subject: Re: [PATCH v3 04/21] drm/i915/psr: Rename intel_psr_enabled
>
> On Fri, 2024-02-02 at 07:34 +, Manna, Animesh wrote:
> >
> >
> > > -Original Message-
> > > From: Hogander, Jouni
> > > Sent: Friday, January 19, 2024 3:40 PM
> > > To: intel-gfx@lists.freedesktop.org
> > > Cc: Manna, Animesh ; Hogander, Jouni
> > >
> > > Subject: [PATCH v3 04/21] drm/i915/psr: Rename intel_psr_enabled
> > >
> > > Intel_psr_enabled is now misleading name as we are using main link
> > > on with panel replay. I.e. link retraining is not controlled by
> > > hardware.
> > > Rename
> > > intel_psr_enabled as intel_psr_hw_controls_link_retrain.
> > >
> > > Signed-off-by: Jouni Högander
> > > ---
> > > drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
> > > drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
> > > drivers/gpu/drm/i915/display/intel_psr.h | 2 +-
> > > 3 files changed, 3 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > > b/drivers/gpu/drm/i915/display/intel_dp.c
> > > index ab415f41924d..e7cda3162ea2 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > @@ -4951,7 +4951,7 @@ intel_dp_needs_link_retrain(struct intel_dp
> > > *intel_dp)
> > > * Also when exiting PSR, HW will retrain the link anyways
> > > fixing
> > > * any link status error.
> > > */
> > > - if (intel_psr_enabled(intel_dp))
> > > + if (intel_psr_hw_controls_link_retrain(intel_dp))
> > > return false;
> > >
> > > if (drm_dp_dpcd_read_phy_link_status(_dp->aux,
> > > DP_PHY_DPRX, diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > index d11f8ea6e0a9..7b3290f4e0b4 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > @@ -3011,7 +3011,7 @@ void intel_psr_short_pulse(struct intel_dp
> > > *intel_dp)
> > > mutex_unlock(>lock);
> > > }
> > >
> > > -bool intel_psr_enabled(struct intel_dp *intel_dp)
> > > +bool intel_psr_hw_controls_link_retrain(struct intel_dp *intel_dp)
> >
> > Based on CAN_PSR() check the function will return early and only get
> > executed for psr. No sure still do we need to rename it?
>
> Ok. For me it was just surprice what it does and why this function exists,
> thus
> renaming. Much more descriptive. Also we will soon have main link off with
> Panel Replay as well then this is not about having PSR or Panel Replay
> enabled, but HW controlling link retraining.
>
> I'm fine with dropping the patch if you have strong opinion on this.
Do not see any value addition, though no strong objection.
Regards,
Animesh
>
> BR,
>
> Jouni Högander
>
> >
> > Regards,
> > Animesh
> > > {
> > > bool ret;
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> > > b/drivers/gpu/drm/i915/display/intel_psr.h
> > > index cde781df84d5..f7c5cc07864f 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> > > @@ -45,7 +45,7 @@ void intel_psr_get_config(struct intel_encoder
> > > *encoder, void intel_psr_irq_handler(struct intel_dp *intel_dp,
> > > u32 psr_iir);
> > > void intel_psr_short_pulse(struct intel_dp *intel_dp); void
> > > intel_psr_wait_for_idle_locked(const struct intel_crtc_state
> > > *new_crtc_state); -bool intel_psr_enabled(struct intel_dp
> > > *intel_dp);
> > > +bool intel_psr_hw_controls_link_retrain(struct intel_dp
> > > *intel_dp);
> > > int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> > > struct intel_crtc *crtc);
> > > void intel_psr2_program_trans_man_trk_ctl(const struct
> > > intel_crtc_state *crtc_state);
> > > --
> > > 2.34.1
> >
RE: [PATCH v3 19/21] drm/i915/psr: Update PSR module parameter descriptions
> -Original Message- > From: Hogander, Jouni > Sent: Friday, January 19, 2024 3:40 PM > To: intel-gfx@lists.freedesktop.org > Cc: Manna, Animesh ; Hogander, Jouni > > Subject: [PATCH v3 19/21] drm/i915/psr: Update PSR module parameter > descriptions > > We are re-using PSR module parameters for panel replay. Update module > parameter descriptions with panel replay information: > > enable_psr: > > -1 (default) == follow what is in VBT > 0 == disable PSR/PR > 1 == Allow PSR1 and PR full frame update > 2 == allow PSR1/PSR2 and PR Selective Update > > enable_psr2_sel_fetch > > 0 == disable selective fetch for PSR and PR > 1 (default) == allow selective fetch for PSR PR > > Signed-off-by: Jouni Högander LGTM. Reviewed-by: Animesh Manna > --- > drivers/gpu/drm/i915/display/intel_display_params.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c > b/drivers/gpu/drm/i915/display/intel_display_params.c > index 11e03cfb774d..1c5e20ec7f1d 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_params.c > +++ b/drivers/gpu/drm/i915/display/intel_display_params.c > @@ -102,7 +102,8 @@ intel_display_param_named_unsafe(enable_fbc, int, > 0400, > > intel_display_param_named_unsafe(enable_psr, int, 0400, > "Enable PSR " > - "(0=disabled, 1=enable up to PSR1, 2=enable up to PSR2) " > + "(0=disabled, 1=enable up to PSR1 and Panel Replay full frame > update, " > + "2=enable up to PSR2 and Panel Replay Selective Update) " > "Default: -1 (use per-chip default)"); > > intel_display_param_named(psr_safest_params, bool, 0400, @@ -112,7 > +113,7 @@ intel_display_param_named(psr_safest_params, bool, 0400, > "Default: 0"); > > intel_display_param_named_unsafe(enable_psr2_sel_fetch, bool, 0400, > - "Enable PSR2 selective fetch " > + "Enable PSR2 and Panel Replay selective fetch " > "(0=disabled, 1=enabled) " > "Default: 1"); > > -- > 2.34.1
RE: [PATCH v3 16/21] drm/i915/psr: Ensure early transport is not enabled for panel replay
> -Original Message-
> From: Hogander, Jouni
> Sent: Friday, January 19, 2024 3:40 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Hogander, Jouni
>
> Subject: [PATCH v3 16/21] drm/i915/psr: Ensure early transport is not
> enabled for panel replay
>
> Early transport is not supported by DP2.0. Ensure early transport is kept
> disabled for panel replay selective update.
>
> Signed-off-by: Jouni Högander
> ---
> .../gpu/drm/i915/display/intel_display_types.h| 1 +
> drivers/gpu/drm/i915/display/intel_psr.c | 15 +++
> 2 files changed, 12 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 1c870ff8b27e..82767751c674 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1706,6 +1706,7 @@ struct intel_psr {
> bool sink_psr2_support;
> bool link_standby;
> bool sel_update_enabled;
> + bool sel_update_et_enabled;
> bool psr2_sel_fetch_enabled;
> bool psr2_sel_fetch_cff_enabled;
> bool req_psr2_sdp_prior_scanline;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index b8367fb8b3d4..617ffd1854dc 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -677,15 +677,20 @@ static void hsw_psr_setup_aux(struct intel_dp
> *intel_dp)
> aux_ctl);
> }
>
> -static bool psr2_su_region_et_valid(struct intel_dp *intel_dp)
> +static bool psr2_su_region_et_valid(struct intel_dp *intel_dp,
> + const struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>
> + if (crtc_state->has_panel_replay)
> + goto unsupported;
> +
> if (DISPLAY_VER(i915) >= 20 &&
> intel_dp->psr_dpcd[0] ==
> DP_PSR2_WITH_Y_COORD_ET_SUPPORTED &&
> !(intel_dp->psr.debug &
> I915_PSR_DEBUG_SU_REGION_ET_DISABLE))
> return true;
>
> +unsupported:
> return false;
> }
>
> @@ -714,7 +719,7 @@ void intel_psr_enable_sink(struct intel_dp *intel_dp,
>
> DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
>
> dpcd_val |= DP_PSR_ENABLE_PSR2 |
> DP_PSR_IRQ_HPD_WITH_CRC_ERRORS;
> - if (psr2_su_region_et_valid(intel_dp))
> + if (crtc_state->enable_psr2_su_region_et)
> dpcd_val |= DP_PSR_ENABLE_SU_REGION_ET;
> } else {
> if (intel_dp->psr.link_standby)
> @@ -973,7 +978,7 @@ static void hsw_activate_psr2(struct intel_dp
> *intel_dp)
> intel_de_write(dev_priv,
> PSR2_MAN_TRK_CTL(cpu_transcoder), 0);
> }
>
> - if (psr2_su_region_et_valid(intel_dp))
> + if (intel_dp->psr.sel_update_et_enabled)
AFICU this is the only place where the sel_update_et_enabled variable is used
and calling the function psr2_su_region_et_valid() vs adding a variable in
intel_psr structure,
I feel good to go with call the function once.
Regards,
Animesh
> val |= LNL_EDP_PSR2_SU_REGION_ET_ENABLE;
>
> /*
> @@ -1138,7 +1143,7 @@ static bool intel_psr2_sel_fetch_config_valid(struct
> intel_dp *intel_dp,
> return false;
> }
>
> - if (psr2_su_region_et_valid(intel_dp))
> + if (psr2_su_region_et_valid(intel_dp, crtc_state))
> crtc_state->enable_psr2_su_region_et = true;
>
> return crtc_state->enable_psr2_sel_fetch = true; @@ -1746,6
> +1751,7 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
> drm_WARN_ON(_priv->drm, intel_dp->psr.enabled);
>
> intel_dp->psr.sel_update_enabled = crtc_state->has_sel_update;
> + intel_dp->psr.sel_update_et_enabled =
> +crtc_state->enable_psr2_su_region_et;
> intel_dp->psr.panel_replay_enabled = crtc_state->has_panel_replay;
> intel_dp->psr.busy_frontbuffer_bits = 0;
> intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
> @@ -1896,6 +1902,7 @@ static void intel_psr_disable_locked(struct intel_dp
> *intel_dp)
> intel_dp->psr.enabled = false;
> intel_dp->psr.panel_replay_enabled = false;
> intel_dp->psr.sel_update_enabled = false;
> + intel_dp->psr.sel_update_et_enabled = false;
> intel_dp->psr.psr2_sel_fetch_enabled = false;
> intel_dp->psr.psr2_sel_fetch_cff_enabled = false; }
> --
> 2.34.1
RE: [PATCH v3 15/21] drm/i915/psr: Modify intel_dp_get_su_granularity to support panel replay
> -Original Message-
> From: Hogander, Jouni
> Sent: Friday, January 19, 2024 3:40 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Hogander, Jouni
>
> Subject: [PATCH v3 15/21] drm/i915/psr: Modify intel_dp_get_su_granularity
> to support panel replay
>
> Currently intel_dp_get_su_granularity doesn't support panel replay.
> This fix modifies it to support panel replay as well.
>
> v2: rely on PSR definitions on common bits
>
> Signed-off-by: Jouni Högander
LGTM.
Reviewed-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 62 +---
> 1 file changed, 55 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 8bf6d0754c18..b8367fb8b3d4 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -466,6 +466,40 @@ static u8 intel_dp_get_sink_sync_latency(struct
> intel_dp *intel_dp)
> return val;
> }
>
> +static u8 intel_dp_get_su_capability(struct intel_dp *intel_dp) {
> + u8 su_capability;
> +
> + if (intel_dp->psr.sink_panel_replay_su_support)
> + drm_dp_dpcd_read(_dp->aux,
> + DP_PANEL_PANEL_REPLAY_X_GRANULARITY,
> + _capability, 1);
> + else
> + su_capability = intel_dp->psr_dpcd[1];
> +
> + return su_capability;
> +}
> +
> +static unsigned int
> +intel_dp_get_su_x_granularity_offset(struct intel_dp *intel_dp) {
> + return intel_dp->psr.sink_panel_replay_su_support ?
> + DP_PANEL_PANEL_REPLAY_X_GRANULARITY :
> + DP_PSR2_SU_X_GRANULARITY;
> +}
> +
> +static unsigned int
> +intel_dp_get_su_y_granularity_offset(struct intel_dp *intel_dp) {
> + return intel_dp->psr.sink_panel_replay_su_support ?
> + DP_PANEL_PANEL_REPLAY_Y_GRANULARITY :
> + DP_PSR2_SU_Y_GRANULARITY;
> +}
> +
> +/*
> + * Note: Bits related to granularity are same in panel replay and psr
> + * registers. Rely on PSR definitions on these "common" bits.
> + */
> static void intel_dp_get_su_granularity(struct intel_dp *intel_dp) {
> struct drm_i915_private *i915 = dp_to_i915(intel_dp); @@ -473,18
> +507,29 @@ static void intel_dp_get_su_granularity(struct intel_dp
> *intel_dp)
> u16 w;
> u8 y;
>
> - /* If sink don't have specific granularity requirements set legacy ones
> */
> - if (!(intel_dp->psr_dpcd[1] &
> DP_PSR2_SU_GRANULARITY_REQUIRED)) {
> + /*
> + * TODO: Do we need to take into account panel supporting both PSR
> and
> + * Panel replay?
> + */
> +
> + /*
> + * If sink don't have specific granularity requirements set legacy
> + * ones.
> + */
> + if (!(intel_dp_get_su_capability(intel_dp) &
> + DP_PSR2_SU_GRANULARITY_REQUIRED)) {
> /* As PSR2 HW sends full lines, we do not care about x
> granularity */
> w = 4;
> y = 4;
> goto exit;
> }
>
> - r = drm_dp_dpcd_read(_dp->aux,
> DP_PSR2_SU_X_GRANULARITY, , 2);
> + r = drm_dp_dpcd_read(_dp->aux,
> + intel_dp_get_su_x_granularity_offset(intel_dp),
> + , 2);
> if (r != 2)
> drm_dbg_kms(>drm,
> - "Unable to read
> DP_PSR2_SU_X_GRANULARITY\n");
> + "Unable to read selective update x granularity\n");
> /*
>* Spec says that if the value read is 0 the default granularity should
>* be used instead.
> @@ -492,10 +537,12 @@ static void intel_dp_get_su_granularity(struct
> intel_dp *intel_dp)
> if (r != 2 || w == 0)
> w = 4;
>
> - r = drm_dp_dpcd_read(_dp->aux,
> DP_PSR2_SU_Y_GRANULARITY, , 1);
> + r = drm_dp_dpcd_read(_dp->aux,
> + intel_dp_get_su_y_granularity_offset(intel_dp),
> + , 1);
> if (r != 1) {
> drm_dbg_kms(>drm,
> - "Unable to read
> DP_PSR2_SU_Y_GRANULARITY\n");
> + "Unable to read selective update y granularity\n");
> y = 4;
> }
> if (y == 0)
> @@ -588,7 +635,8 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
> if (intel_dp->psr_dpcd[0])
> _psr_init_dpcd(intel_dp);
>
> - if (intel_dp->psr.sink_psr2_support)
> + if (intel_dp->psr.sink_psr2_support ||
> + intel_dp->psr.sink_panel_replay_su_support)
> intel_dp_get_su_granularity(intel_dp);
> }
>
> --
> 2.34.1
RE: [PATCH v3 14/21] drm/i915/psr: Detect panel replay selective update support
> -Original Message-
> From: Hogander, Jouni
> Sent: Friday, January 19, 2024 3:40 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Hogander, Jouni
>
> Subject: [PATCH v3 14/21] drm/i915/psr: Detect panel replay selective update
> support
>
> Add new boolean to store panel replay selective update support of sink into
> intel_psr struct. Detect panel replay selective update support and store it
> into this new boolean.
>
> v2: Merge adding new boolean into this patch
>
> Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
> drivers/gpu/drm/i915/display/intel_psr.c | 10 --
> 2 files changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 6cef3dabcf45..1c870ff8b27e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1720,6 +1720,7 @@ struct intel_psr {
> u16 su_y_granularity;
> bool source_panel_replay_support;
> bool sink_panel_replay_support;
> + bool sink_panel_replay_su_support;
> bool panel_replay_enabled;
> u32 dc3co_exitline;
> u32 dc3co_exit_delay;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 34bc0a4c1ba2..8bf6d0754c18 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -520,9 +520,15 @@ static void _panel_replay_init_dpcd(struct intel_dp
> *intel_dp)
> return;
> }
>
> - drm_dbg_kms(>drm,
> - "Panel replay is supported by panel\n");
> intel_dp->psr.sink_panel_replay_support = true;
> +
> + if (pr_dpcd & DP_PANEL_REPLAY_SU_SUPPORT)
> + intel_dp->psr.sink_panel_replay_su_support = true;
> +
> + drm_dbg_kms(>drm,
> + "Panel replay %sis supported by panel\n",
> + intel_dp->psr.sink_panel_replay_su_support ?
> + "selective_update " : "");
> }
>
> static void _psr_init_dpcd(struct intel_dp *intel_dp)
> --
> 2.34.1
RE: [PATCH v3 13/21] drm/panelreplay: dpcd register definition for panelreplay SU
> -Original Message- > From: Hogander, Jouni > Sent: Friday, January 19, 2024 3:40 PM > To: intel-gfx@lists.freedesktop.org > Cc: Manna, Animesh ; Hogander, Jouni > > Subject: [PATCH v3 13/21] drm/panelreplay: dpcd register definition for > panelreplay SU > > Add definitions for panel replay selective update > > v2: Remove unnecessary Cc from commit message > > Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna > --- > include/drm/display/drm_dp.h | 6 ++ > 1 file changed, 6 insertions(+) > > diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h > index 281afff6ee4e..4ebf79948c7f 100644 > --- a/include/drm/display/drm_dp.h > +++ b/include/drm/display/drm_dp.h > @@ -548,6 +548,12 @@ > # define DP_PANEL_REPLAY_SUPPORT(1 << 0) > # define DP_PANEL_REPLAY_SU_SUPPORT (1 << 1) > > +#define DP_PANEL_PANEL_REPLAY_CAPABILITY 0xb1 > +# define DP_PANEL_PANEL_REPLAY_SU_GRANULARITY_REQUIRED (1 << > 5) > + > +#define DP_PANEL_PANEL_REPLAY_X_GRANULARITY 0xb2 > +#define DP_PANEL_PANEL_REPLAY_Y_GRANULARITY 0xb4 > + > /* Link Configuration */ > #define DP_LINK_BW_SET 0x100 > # define DP_LINK_RATE_TABLE 0x00/* eDP 1.4 */ > -- > 2.34.1
RE: [PATCH v3 11/21] drm/i915/psr: Modify VSC SDP calculation to support panel replay + su
> -Original Message-
> From: Hogander, Jouni
> Sent: Friday, January 19, 2024 3:40 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Hogander, Jouni
>
> Subject: [PATCH v3 11/21] drm/i915/psr: Modify VSC SDP calculation to
> support panel replay + su
>
> Current VSC SDP calculation doesn't support panel replay + su. Change it to
> support this combination as well.
>
> Signed-off-by: Jouni Högander
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 16
> 1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 4e01182662ff..ae368db4 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2633,14 +2633,6 @@ static void intel_dp_compute_vsc_sdp(struct
> intel_dp *intel_dp,
> if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
> intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
>vsc);
> - } else if (crtc_state->has_psr && crtc_state->has_sel_update) {
> - /*
> - * [PSR2 without colorimetry]
> - * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
> - * 3D stereo + PSR/PSR2 + Y-coordinate.
> - */
> - vsc->revision = 0x4;
> - vsc->length = 0xe;
> } else if (crtc_state->has_panel_replay) {
> /*
>* [Panel Replay without colorimetry info] @@ -2649,6
> +2641,14 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp
> *intel_dp,
>*/
> vsc->revision = 0x6;
> vsc->length = 0x10;
> + } else if (crtc_state->has_sel_update) {
> + /*
> + * [PSR2 without colorimetry]
> + * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
> + * 3D stereo + PSR/PSR2 + Y-coordinate.
> + */
The above code comments need to be modified for panel replay as well. How
psr2+selective_update and pr+selective_update will be managed with the same
intel_dp_compute_vsc_sdp() good to add some function description.
Regards,
Animesh
> + vsc->revision = 0x4;
> + vsc->length = 0xe;
> } else {
> /*
>* [PSR1]
> --
> 2.34.1
RE: [PATCH v3 10/21] drm/i915/psr: Rename has_psr2 as has_sel_update
> -Original Message-
> From: Hogander, Jouni
> Sent: Friday, January 19, 2024 3:40 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Hogander, Jouni
>
> Subject: [PATCH v3 10/21] drm/i915/psr: Rename has_psr2 as
> has_sel_update
>
> We are going to reuse has_psr2 for panel_replay as well. Rename it as
> has_sel_update to avoid confusion.
>
> v2: Rebase
>
> Signed-off-by: Jouni Högander
Reviewed-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 5 +++--
> drivers/gpu/drm/i915/display/intel_display.c | 2 +-
> drivers/gpu/drm/i915/display/intel_display_types.h | 2 +-
> drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
> drivers/gpu/drm/i915/display/intel_fbc.c | 2 +-
> drivers/gpu/drm/i915/display/intel_psr.c | 10 +-
> 6 files changed, 12 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> index 49fd100ec98a..5edbc9b3d766 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> @@ -266,9 +266,10 @@ void intel_crtc_state_dump(const struct
> intel_crtc_state *pipe_config,
> drm_dbg_kms(>drm, "sdp split: %s\n",
> str_enabled_disabled(pipe_config-
> >sdp_split_enable));
>
> - drm_dbg_kms(>drm, "psr: %s, psr2: %s, panel replay:
> %s, selective fetch: %s\n",
> + drm_dbg_kms(>drm,
> + "psr: %s, selective update: %s, panel replay: %s,
> selective
> +fetch: %s\n",
> str_enabled_disabled(pipe_config->has_psr),
> - str_enabled_disabled(pipe_config->has_psr2),
> + str_enabled_disabled(pipe_config-
> >has_sel_update),
> str_enabled_disabled(pipe_config-
> >has_panel_replay),
> str_enabled_disabled(pipe_config-
> >enable_psr2_sel_fetch));
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index b7e5b2774f2e..8bf1ba30b3fc 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5220,7 +5220,7 @@ intel_pipe_config_compare(const struct
> intel_crtc_state *current_config,
>*/
> if (current_config->has_panel_replay || pipe_config-
> >has_panel_replay) {
> PIPE_CONF_CHECK_BOOL(has_psr);
> - PIPE_CONF_CHECK_BOOL(has_psr2);
> + PIPE_CONF_CHECK_BOOL(has_sel_update);
> PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
> PIPE_CONF_CHECK_BOOL(enable_psr2_su_region_et);
> PIPE_CONF_CHECK_BOOL(has_panel_replay);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index ae2e8cff9d69..5890fef86547 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1211,7 +1211,7 @@ struct intel_crtc_state {
>
> /* PSR is supported but might not be enabled due the lack of enabled
> planes */
> bool has_psr;
> - bool has_psr2;
> + bool has_sel_update;
> bool enable_psr2_sel_fetch;
> bool enable_psr2_su_region_et;
> bool req_psr2_sdp_prior_scanline;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 11143fb9b0f0..4e01182662ff 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2633,7 +2633,7 @@ static void intel_dp_compute_vsc_sdp(struct
> intel_dp *intel_dp,
> if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
> intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
>vsc);
> - } else if (crtc_state->has_psr2) {
> + } else if (crtc_state->has_psr && crtc_state->has_sel_update) {
> /*
>* [PSR2 without colorimetry]
>* Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index f17a1afb4929..647dd1b56073 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -1235,7 +1235,7 @@ static int intel_fbc_check_plane(struct
> intel_atomic_state *state,
>* Recomme
RE: [PATCH v3 09/21] drm/i915/psr: Panel replay has to be enabled before link training
> -Original Message-
> From: Hogander, Jouni
> Sent: Friday, January 19, 2024 3:40 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Hogander, Jouni
>
> Subject: [PATCH v3 09/21] drm/i915/psr: Panel replay has to be enabled
> before link training
>
> Panel replay has to be enabled on sink side before link training. Take this
> into
> account in fastset check and in initial fastset check.
>
> Signed-off-by: Jouni Högander
LGTM.
Reviewed-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 12
> drivers/gpu/drm/i915/display/intel_dp.c | 8
> drivers/gpu/drm/i915/display/intel_psr.c | 3 ---
> drivers/gpu/drm/i915/display/intel_psr.h | 3 +++
> 4 files changed, 23 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index a92e959c8ac7..b7e5b2774f2e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5214,6 +5214,18 @@ intel_pipe_config_compare(const struct
> intel_crtc_state *current_config,
> PIPE_CONF_CHECK_CSC(output_csc);
> }
>
> + /*
> + * Panel replay has to be enabled before link training. PSR doesn't
> have
> + * this requirement -> check these only if using panel replay
> + */
> + if (current_config->has_panel_replay || pipe_config-
> >has_panel_replay) {
> + PIPE_CONF_CHECK_BOOL(has_psr);
> + PIPE_CONF_CHECK_BOOL(has_psr2);
> + PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
> + PIPE_CONF_CHECK_BOOL(enable_psr2_su_region_et);
> + PIPE_CONF_CHECK_BOOL(has_panel_replay);
> + }
> +
> PIPE_CONF_CHECK_BOOL(double_wide);
>
> if (dev_priv->display.dpll.mgr) {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index e7cda3162ea2..11143fb9b0f0 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3326,6 +3326,14 @@ bool intel_dp_initial_fastset_check(struct
> intel_encoder *encoder,
> fastset = false;
> }
>
> + if (CAN_PANEL_REPLAY(intel_dp)) {
> + drm_dbg_kms(>drm,
> + "[ENCODER:%d:%s] Forcing full modeset to
> compute panel replay state\n",
> + encoder->base.base.id, encoder->base.name);
> + crtc_state->uapi.mode_changed = true;
> + fastset = false;
> + }
> +
> return fastset;
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index b905aee0ec81..24a80f47b84f 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -192,9 +192,6 @@
> #define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \
> (intel_dp)->psr.source_support)
>
> -#define CAN_PANEL_REPLAY(intel_dp) ((intel_dp)-
> >psr.sink_panel_replay_support && \
> - (intel_dp)-
> >psr.source_panel_replay_support)
> -
> bool intel_encoder_can_psr(struct intel_encoder *encoder) {
> if (intel_encoder_is_dp(encoder) || encoder->type ==
> INTEL_OUTPUT_DP_MST) diff --git
> a/drivers/gpu/drm/i915/display/intel_psr.h
> b/drivers/gpu/drm/i915/display/intel_psr.h
> index b74382b38f4a..e687d7bdbb1f 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -21,6 +21,9 @@ struct intel_encoder;
> struct intel_plane;
> struct intel_plane_state;
>
> +#define CAN_PANEL_REPLAY(intel_dp) ((intel_dp)-
> >psr.sink_panel_replay_support && \
> + (intel_dp)-
> >psr.source_panel_replay_support)
> +
> bool intel_encoder_can_psr(struct intel_encoder *encoder); void
> intel_psr_init_dpcd(struct intel_dp *intel_dp); void
> intel_psr_enable_sink(struct intel_dp *intel_dp,
> --
> 2.34.1
RE: [PATCH v3 08/21] drm/i915/psr: Unify panel replay enable/disable sink
> -Original Message-
> From: Hogander, Jouni
> Sent: Friday, January 19, 2024 3:40 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Hogander, Jouni
>
> Subject: [PATCH v3 08/21] drm/i915/psr: Unify panel replay enable/disable
> sink
>
> Unify enabling and disabling of psr/panel replay for a sink. Modify
> intel_psr_enable_sink accordingly and use it for both cases.
>
> v2:
> - enable panel replay for sink before link training
> - write ALPM_CONFIG only for PSR
> - add DP_PSR_CRC_VERIFICATION only for PSR
> - take care of disable sink as well
>
> Signed-off-by: Jouni Högander
LGTM.
Reviewed-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 11 +++--
> drivers/gpu/drm/i915/display/intel_psr.c | 54 +---
> drivers/gpu/drm/i915/display/intel_psr.h | 2 +
> 3 files changed, 46 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 922194b957be..6721a478a633 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2800,15 +2800,14 @@ static void intel_ddi_pre_enable_dp(struct
> intel_atomic_state *state,
> const struct drm_connector_state
> *conn_state) {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>
> - if (HAS_DP20(dev_priv)) {
> + if (HAS_DP20(dev_priv))
> intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder),
> crtc_state);
> - if (crtc_state->has_panel_replay)
> - drm_dp_dpcd_writeb(_dp->aux,
> PANEL_REPLAY_CONFIG,
> -DP_PANEL_REPLAY_ENABLE);
> - }
> +
> + /* Panel replay has to be enabled in sink dpcd before link training. */
> + if (crtc_state->has_panel_replay)
> + intel_psr_enable_sink(enc_to_intel_dp(encoder), crtc_state);
>
> if (DISPLAY_VER(dev_priv) >= 14)
> mtl_ddi_pre_enable_dp(state, encoder, crtc_state,
> conn_state); diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 2d5d1c2ce246..b905aee0ec81 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -638,19 +638,29 @@ static bool psr2_su_region_et_valid(struct intel_dp
> *intel_dp)
> return false;
> }
>
> -static void intel_psr_enable_sink(struct intel_dp *intel_dp)
> +static unsigned int intel_psr_get_enable_sink_offset(struct intel_dp
> +*intel_dp) {
> + return intel_dp->psr.panel_replay_enabled ?
> + PANEL_REPLAY_CONFIG : DP_PSR_EN_CFG;
> +}
> +
> +/*
> + * Note: Most of the bits are same in PANEL_REPLAY_CONFIG and
> +DP_PSR_EN_CFG. We
> + * are relying on PSR definitions on these "common" bits.
> + */
> +void intel_psr_enable_sink(struct intel_dp *intel_dp,
> +const struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> u8 dpcd_val = DP_PSR_ENABLE;
>
> - if (intel_dp->psr.panel_replay_enabled)
> - return;
> -
> - if (intel_dp->psr.psr2_enabled) {
> + if (crtc_state->has_psr2) {
> /* Enable ALPM at sink for psr2 */
> - drm_dp_dpcd_writeb(_dp->aux,
> DP_RECEIVER_ALPM_CONFIG,
> -DP_ALPM_ENABLE |
> -
> DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
> + if (!crtc_state->has_panel_replay)
> + drm_dp_dpcd_writeb(_dp->aux,
> +DP_RECEIVER_ALPM_CONFIG,
> +DP_ALPM_ENABLE |
> +
> DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
>
> dpcd_val |= DP_PSR_ENABLE_PSR2 |
> DP_PSR_IRQ_HPD_WITH_CRC_ERRORS;
> if (psr2_su_region_et_valid(intel_dp))
> @@ -659,19 +669,26 @@ static void intel_psr_enable_sink(struct intel_dp
> *intel_dp)
> if (intel_dp->psr.link_standby)
> dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
>
> - if (DISPLAY_VER(dev_priv) >= 8)
> + if (!crtc_state->has_panel_replay && DISPLAY_VER(dev_priv)
> >= 8)
> dpcd_val |= DP_PSR_CRC_VERIFICATION;
> }
>
> - if (intel_dp->psr.req_psr2_sdp_prior_scanline)
> + if (crtc_state->has_panel_replay)
> + dpcd_val |=
> DP_P
RE: [PATCH v3 07/21] drm/i915/psr: Do not write registers/bits not applicable for panel replay
> -Original Message-
> From: Hogander, Jouni
> Sent: Friday, January 19, 2024 3:40 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Hogander, Jouni
>
> Subject: [PATCH v3 07/21] drm/i915/psr: Do not write registers/bits not
> applicable for panel replay
>
> From bspec:
>
> Additional programming considerations (repurposed eDP registers)
>
> mask register: Only PSR_MASK[Mask FBC modify] and PSR_MASK[Mask
> Hotplug] are used in panel replay mode.
>
> Status register: Only SRD_STATUS[SRD state] field is used in panel replay
> mode.
>
> Due to this stop writing and reading registers and bits not used by panel
> replay if panel replay is used.
>
> Bspec: 53370
>
> Signed-off-by: Jouni Högander
LGTM.
Reviewed-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 23 ++-
> 1 file changed, 18 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 6d7ef74201d2..2d5d1c2ce246 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -346,6 +346,9 @@ static void psr_irq_control(struct intel_dp *intel_dp)
> enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
> u32 mask;
>
> + if (intel_dp->psr.panel_replay_enabled)
> + return;
> +
> mask = psr_irq_psr_error_bit_get(intel_dp);
> if (intel_dp->psr.debug & I915_PSR_DEBUG_IRQ)
> mask |= psr_irq_post_exit_bit_get(intel_dp) | @@ -1559,13
> +1562,19 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
>* mask LPSP to avoid dependency on other drivers that might block
>* runtime_pm besides preventing other hw tracking issues now we
>* can rely on frontbuffer tracking.
> + *
> + * From bspec: Only PSR_MASK[Mask FBC modify] and
> PSR_MASK[Mask Hotplug]
> + * are used in panel replay mode.
>*/
> - mask = EDP_PSR_DEBUG_MASK_MEMUP |
> -EDP_PSR_DEBUG_MASK_HPD |
> -EDP_PSR_DEBUG_MASK_LPSP;
> + mask = EDP_PSR_DEBUG_MASK_HPD;
>
> - if (DISPLAY_VER(dev_priv) < 20)
> - mask |= EDP_PSR_DEBUG_MASK_MAX_SLEEP;
> + if (!intel_dp->psr.panel_replay_enabled) {
> + mask |= EDP_PSR_DEBUG_MASK_MEMUP |
> + EDP_PSR_DEBUG_MASK_LPSP;
> +
> + if (DISPLAY_VER(dev_priv) < 20)
> + mask |= EDP_PSR_DEBUG_MASK_MAX_SLEEP;
> + }
>
> /*
>* No separate pipe reg write mask on hsw/bdw, so have to unmask
> all @@ -1634,6 +1643,9 @@ static bool psr_interrupt_error_check(struct
> intel_dp *intel_dp)
> enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
> u32 val;
>
> + if (intel_dp->psr.panel_replay_enabled)
> + goto no_err;
> +
> /*
>* If a PSR error happened and the driver is reloaded, the
> EDP_PSR_IIR
>* will still keep the error set even after the reset done in the @@ -
> 1651,6 +1663,7 @@ static bool psr_interrupt_error_check(struct intel_dp
> *intel_dp)
> return false;
> }
>
> +no_err:
> return true;
> }
>
> --
> 2.34.1
RE: [PATCH v3 06/21] drm/i915/psr: Check possible errors for panel replay as well
> -Original Message-
> From: Hogander, Jouni
> Sent: Friday, January 19, 2024 3:40 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Hogander, Jouni
>
> Subject: [PATCH v3 06/21] drm/i915/psr: Check possible errors for panel
> replay as well
>
> On HPD interrupt we want to check if the reason for HPD was some panel
> replay error detected by monitor/panel. This is already done for PSR. We
> want to do this for panel replay as well. Modify intel_psr_short_pulse to
> support panel replay as well.
>
> Signed-off-by: Jouni Högander
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 21 -
> 1 file changed, 16 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 893c72ea8cf1..6d7ef74201d2 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -2959,6 +2959,13 @@ static void psr_capability_changed_check(struct
> intel_dp *intel_dp)
> }
> }
>
> +/*
> + * On common bits:
> + * DP_PSR_RFB_STORAGE_ERROR ==
> DP_PANEL_REPLAY_RFB_STORAGE_ERROR
> + * DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR ==
> +DP_PANEL_REPLAY_VSC_SDP_UNCORRECTABLE_ERROR
> + * DP_PSR_LINK_CRC_ERROR == DP_PANEL_REPLAY_LINK_CRC_ERROR
> + * this function is relying on PSR definitions */
> void intel_psr_short_pulse(struct intel_dp *intel_dp) {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); @@ -
> 2968,7 +2975,7 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp)
> DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR |
> DP_PSR_LINK_CRC_ERROR;
>
> - if (!CAN_PSR(intel_dp))
> + if (!CAN_PSR(intel_dp) && !CAN_PANEL_REPLAY(intel_dp))
I feel here the condition check would be:
if (!(CAN_PSR(intel_dp) || CAN_PANEL_REPLAY(intel_dp)))
> return;
>
> mutex_lock(>lock);
> @@ -2982,12 +2989,14 @@ void intel_psr_short_pulse(struct intel_dp
> *intel_dp)
> goto exit;
> }
>
> - if (status == DP_PSR_SINK_INTERNAL_ERROR || (error_status &
> errors)) {
> + if ((!psr->panel_replay_enabled && status ==
> DP_PSR_SINK_INTERNAL_ERROR) ||
> + (error_status & errors)) {
This will check only for psr, rt? .. The flag panel_replay_enabled will be true
and will not check for error status for panel-replay.
> intel_psr_disable_locked(intel_dp);
> psr->sink_not_reliable = true;
> }
>
> - if (status == DP_PSR_SINK_INTERNAL_ERROR && !error_status)
> + if (!psr->panel_replay_enabled && status ==
> DP_PSR_SINK_INTERNAL_ERROR &&
> + !error_status)
Same doubt as above.
Regards,
Animesh
> drm_dbg_kms(_priv->drm,
> "PSR sink internal error, disabling PSR\n");
> if (error_status & DP_PSR_RFB_STORAGE_ERROR) @@ -3007,8
> +3016,10 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp)
> /* clear status register */
> drm_dp_dpcd_writeb(_dp->aux, DP_PSR_ERROR_STATUS,
> error_status);
>
> - psr_alpm_check(intel_dp);
> - psr_capability_changed_check(intel_dp);
> + if (!psr->panel_replay_enabled) {
> + psr_alpm_check(intel_dp);
> + psr_capability_changed_check(intel_dp);
> + }
>
> exit:
> mutex_unlock(>lock);
> --
> 2.34.1
RE: [PATCH v3 05/21] drm/i915/psr: Do not update phy power state in case of panel replay
> -Original Message-
> From: Hogander, Jouni
> Sent: Friday, January 19, 2024 3:40 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Hogander, Jouni
>
> Subject: [PATCH v3 05/21] drm/i915/psr: Do not update phy power state in
> case of panel replay
>
> Currently panel replay is supporting only main link on mode -> Do not update
> phy power state for panel replay.
>
> Bspec: 53370
>
> Signed-off-by: Jouni Högander
LGTM.
Reviewed-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 11 +++
> 1 file changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 7b3290f4e0b4..893c72ea8cf1 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1681,13 +1681,15 @@ static void intel_psr_enable_locked(struct
> intel_dp *intel_dp,
> if (!psr_interrupt_error_check(intel_dp))
> return;
>
> - if (intel_dp->psr.panel_replay_enabled)
> + if (intel_dp->psr.panel_replay_enabled) {
> drm_dbg_kms(_priv->drm, "Enabling Panel Replay\n");
> - else
> + } else {
> drm_dbg_kms(_priv->drm, "Enabling PSR%s\n",
> intel_dp->psr.psr2_enabled ? "2" : "1");
>
> - intel_snps_phy_update_psr_power_state(dev_priv, phy, true);
> + intel_snps_phy_update_psr_power_state(dev_priv, phy,
> true);
> + }
> +
> intel_psr_enable_sink(intel_dp);
> intel_psr_enable_source(intel_dp, crtc_state);
> intel_dp->psr.enabled = true;
> @@ -1794,7 +1796,8 @@ static void intel_psr_disable_locked(struct intel_dp
> *intel_dp)
>CLKGATE_DIS_MISC_DMASC_GATING_DIS,
> 0);
> }
>
> - intel_snps_phy_update_psr_power_state(dev_priv, phy, false);
> + if (!intel_dp->psr.panel_replay_enabled)
> + intel_snps_phy_update_psr_power_state(dev_priv, phy,
> false);
>
> /* Disable PSR on Sink */
> drm_dp_dpcd_writeb(_dp->aux, DP_PSR_EN_CFG, 0);
> --
> 2.34.1
RE: [PATCH v3 04/21] drm/i915/psr: Rename intel_psr_enabled
> -Original Message-
> From: Hogander, Jouni
> Sent: Friday, January 19, 2024 3:40 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Hogander, Jouni
>
> Subject: [PATCH v3 04/21] drm/i915/psr: Rename intel_psr_enabled
>
> Intel_psr_enabled is now misleading name as we are using main link on with
> panel replay. I.e. link retraining is not controlled by hardware. Rename
> intel_psr_enabled as intel_psr_hw_controls_link_retrain.
>
> Signed-off-by: Jouni Högander
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
> drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
> drivers/gpu/drm/i915/display/intel_psr.h | 2 +-
> 3 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index ab415f41924d..e7cda3162ea2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4951,7 +4951,7 @@ intel_dp_needs_link_retrain(struct intel_dp
> *intel_dp)
>* Also when exiting PSR, HW will retrain the link anyways fixing
>* any link status error.
>*/
> - if (intel_psr_enabled(intel_dp))
> + if (intel_psr_hw_controls_link_retrain(intel_dp))
> return false;
>
> if (drm_dp_dpcd_read_phy_link_status(_dp->aux,
> DP_PHY_DPRX, diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index d11f8ea6e0a9..7b3290f4e0b4 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -3011,7 +3011,7 @@ void intel_psr_short_pulse(struct intel_dp
> *intel_dp)
> mutex_unlock(>lock);
> }
>
> -bool intel_psr_enabled(struct intel_dp *intel_dp)
> +bool intel_psr_hw_controls_link_retrain(struct intel_dp *intel_dp)
Based on CAN_PSR() check the function will return early and only get executed
for psr. No sure still do we need to rename it?
Regards,
Animesh
> {
> bool ret;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> b/drivers/gpu/drm/i915/display/intel_psr.h
> index cde781df84d5..f7c5cc07864f 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -45,7 +45,7 @@ void intel_psr_get_config(struct intel_encoder
> *encoder, void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir);
> void intel_psr_short_pulse(struct intel_dp *intel_dp); void
> intel_psr_wait_for_idle_locked(const struct intel_crtc_state
> *new_crtc_state); -bool intel_psr_enabled(struct intel_dp *intel_dp);
> +bool intel_psr_hw_controls_link_retrain(struct intel_dp *intel_dp);
> int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> struct intel_crtc *crtc);
> void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state
> *crtc_state);
> --
> 2.34.1
RE: [PATCH v3 01/21] drm/i915/psr: Add some documentation of variables used in psr code
> -Original Message- > From: Hogander, Jouni > Sent: Friday, January 19, 2024 3:40 PM > To: intel-gfx@lists.freedesktop.org > Cc: Manna, Animesh ; Hogander, Jouni > > Subject: [PATCH v3 01/21] drm/i915/psr: Add some documentation of > variables used in psr code > > We are adding more boolean variable into intel_psr and intel_crtc_state > structs. Add some documentation about these for sake of clarity. > > v2: Modify has_psr + has_panel_replay to mean panel replay > > Signed-off-by: Jouni Högander LGTM. Reviewed-by: Animesh Manna > --- > drivers/gpu/drm/i915/display/intel_psr.c | 16 > 1 file changed, 16 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > b/drivers/gpu/drm/i915/display/intel_psr.c > index 696d5d32ca9d..b9d2f6ceb568 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -171,6 +171,22 @@ > * > * The rest of the bits are more self-explanatory and/or > * irrelevant for normal operation. > + * > + * Description of intel_crtc_state variables. has_psr, has_panel_replay > + and > + * has_sel_update: > + * > + * has_psr (alone): PSR1 > + * has_psr + has_sel_update:PSR2 > + * has_psr + has_panel_replay: Panel Replay > + * has_psr + has_panel_replay + has_sel_update: Panel Replay Selective > Update > + * > + * Description of some intel_psr varibles. enabled, > + panel_replay_enabled, > + * sel_update_enabled > + * > + * enabled (alone): PSR1 > + * enabled + sel_update_enabled:PSR2 > + * enabled + panel_replay_enabled: Panel Replay > + * enabled + panel_replay_enabled + sel_update_enabled: Panel Replay > SU > */ > > #define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \ > -- > 2.34.1
RE: [PATCH v3 02/21] drm/i915/psr: Set intel_crtc_state->has_psr on panel replay as well
> -Original Message-
> From: Hogander, Jouni
> Sent: Friday, January 19, 2024 3:40 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh ; Hogander, Jouni
>
> Subject: [PATCH v3 02/21] drm/i915/psr: Set intel_crtc_state->has_psr on
> panel replay as well
>
> Current code is setting only intel_crtc_state->has_panel_replay in panel
> replay case. There are lots of stuff behind intel_crtc_state->has_psr that is
> needed for panel replay as well. Instead of converting each check to has_psr
> || has_panel_replay set has_psr in case of panel replay as well. Code can
> then differentiate between psr and panel replay by using intel_crtc_state-
> >has_panel_replay.
>
> Signed-off-by: Jouni Högander
LGTM.
Reviewed-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 11 ++-
> 1 file changed, 6 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index b9d2f6ceb568..d69fefc2a94d 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1409,10 +1409,11 @@ void intel_psr_compute_config(struct intel_dp
> *intel_dp,
>
> if (CAN_PANEL_REPLAY(intel_dp))
> crtc_state->has_panel_replay = true;
> - else
> - crtc_state->has_psr = _psr_compute_config(intel_dp,
> crtc_state);
>
> - if (!(crtc_state->has_panel_replay || crtc_state->has_psr))
> + crtc_state->has_psr = crtc_state->has_panel_replay ? true :
> + _psr_compute_config(intel_dp, crtc_state);
> +
> + if (!crtc_state->has_psr)
> return;
>
> crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state);
> @@ -1439,7 +1440,7 @@ void intel_psr_get_config(struct intel_encoder
> *encoder,
> goto unlock;
>
> if (intel_dp->psr.panel_replay_enabled) {
> - pipe_config->has_panel_replay = true;
> + pipe_config->has_psr = pipe_config->has_panel_replay =
> true;
> } else {
> /*
>* Not possible to read EDP_PSR/PSR2_CTL registers as it is
> @@ -2352,7 +2353,7 @@ void intel_psr_post_plane_update(struct
> intel_atomic_state *state,
> intel_atomic_get_new_crtc_state(state, crtc);
> struct intel_encoder *encoder;
>
> - if (!(crtc_state->has_psr || crtc_state->has_panel_replay))
> + if (!crtc_state->has_psr)
> return;
>
> for_each_intel_encoder_mask_with_psr(state->base.dev, encoder,
> --
> 2.34.1
RE: [PATCH v2 08/13] drm/i915/psr: Add sink_panel_replay_su_support to intel_psr
> -Original Message-
> From: Intel-gfx On Behalf Of Jouni
> Högander
> Sent: Wednesday, January 10, 2024 6:43 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [PATCH v2 08/13] drm/i915/psr: Add sink_panel_replay_su_support
> to intel_psr
>
> Add new boolean to store panel replay selective update support of sink.
>
> Signed-off-by: Jouni Högander
> ---
> drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 8315ec307d5f..3151741f49f5 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1721,6 +1721,7 @@ struct intel_psr {
> u16 su_y_granularity;
> bool source_panel_replay_support;
> bool sink_panel_replay_support;
> + bool sink_panel_replay_su_support;
This patch can be squashed with the patch which is using the variable.
Early patches psr2 get modified to sel_update .. can we have similar approach?
Then we do not need extra variable.
Regards,
Animesh
> bool panel_replay_enabled;
> u32 dc3co_exitline;
> u32 dc3co_exit_delay;
> --
> 2.34.1
RE: [PATCH v2 07/13] drm/i915/psr: Add some documentation of variables used in psr code
> -Original Message- > From: Intel-gfx On Behalf Of Jouni > Högander > Sent: Wednesday, January 10, 2024 6:43 PM > To: intel-gfx@lists.freedesktop.org > Subject: [PATCH v2 07/13] drm/i915/psr: Add some documentation of > variables used in psr code > > We are adding more boolean variable into intel_psr and intel_crtc_state > structs. Add some documentation about these for sake of clarity. > > Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna > --- > drivers/gpu/drm/i915/display/intel_psr.c | 16 > 1 file changed, 16 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > b/drivers/gpu/drm/i915/display/intel_psr.c > index cde95cc9925a..be8b1b7a8025 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -171,6 +171,22 @@ > * > * The rest of the bits are more self-explanatory and/or > * irrelevant for normal operation. > + * > + * Description of intel_crtc_state variables. has_psr, has_panel_replay > + and > + * has_sel_update: > + * > + * has_psr (alone): PSR1 > + * has_psr + has_sel_update:PSR2 > + * has_panel_replay:Panel Replay > + * has_panel_replay + has_sel_update: Panel Replay Selective Update > + * > + * Description of some intel_psr enabled, panel_replay_enabled, > + * sel_update_enabled > + * > + * enabled (alone): PSR1 > + * enabled + sel_update_enabled:PSR2 > + * enabled + panel_replay_enabled: Panel Replay > + * enabled + panel_replay_enabled + sel_update_enabled: Panel Replay > SU > */ > > bool intel_encoder_can_psr(struct intel_encoder *encoder) > -- > 2.34.1
RE: [PATCH v2 06/13] drm/i915/psr: Rename psr2_enabled as sel_update_enabled
> -Original Message-
> From: Intel-gfx On Behalf Of Jouni
> Högander
> Sent: Wednesday, January 10, 2024 6:43 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [PATCH v2 06/13] drm/i915/psr: Rename psr2_enabled as
> sel_update_enabled
>
> We are about to reuse psr2_enabled for panel replay as well. Rename it as
> sel_update_enabled to avoid confusion.
>
> Signed-off-by: Jouni Högander
Changes looks good to me.
Reviewed-by: Animesh Manna
> ---
> .../drm/i915/display/intel_display_types.h| 2 +-
> drivers/gpu/drm/i915/display/intel_psr.c | 52 +--
> 2 files changed, 27 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 8fdab2f0c546..8315ec307d5f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1706,7 +1706,7 @@ struct intel_psr {
> unsigned int busy_frontbuffer_bits;
> bool sink_psr2_support;
> bool link_standby;
> - bool psr2_enabled;
> + bool sel_update_enabled;
> bool psr2_sel_fetch_enabled;
> bool psr2_sel_fetch_cff_enabled;
> bool req_psr2_sdp_prior_scanline;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 3d00b4e396de..cde95cc9925a 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -339,12 +339,12 @@ static void psr_irq_control(struct intel_dp
> *intel_dp) }
>
> static void psr_event_print(struct drm_i915_private *i915,
> - u32 val, bool psr2_enabled)
> + u32 val, bool sel_update_enabled)
> {
> drm_dbg_kms(>drm, "PSR exit events: 0x%x\n", val);
> if (val & PSR_EVENT_PSR2_WD_TIMER_EXPIRE)
> drm_dbg_kms(>drm, "\tPSR2 watchdog timer
> expired\n");
> - if ((val & PSR_EVENT_PSR2_DISABLED) && psr2_enabled)
> + if ((val & PSR_EVENT_PSR2_DISABLED) && sel_update_enabled)
> drm_dbg_kms(>drm, "\tPSR2 disabled\n");
> if (val & PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN)
> drm_dbg_kms(>drm, "\tSU dirty FIFO underrun\n");
> @@ -372,7 +372,7 @@ static void psr_event_print(struct drm_i915_private
> *i915,
> drm_dbg_kms(>drm, "\tVBI enabled\n");
> if (val & PSR_EVENT_LPSP_MODE_EXIT)
> drm_dbg_kms(>drm, "\tLPSP mode exited\n");
> - if ((val & PSR_EVENT_PSR_DISABLE) && !psr2_enabled)
> + if ((val & PSR_EVENT_PSR_DISABLE) && !sel_update_enabled)
> drm_dbg_kms(>drm, "\tPSR disabled\n"); }
>
> @@ -400,7 +400,7 @@ void intel_psr_irq_handler(struct intel_dp *intel_dp,
> u32 psr_iir)
>
> val = intel_de_rmw(dev_priv,
> PSR_EVENT(cpu_transcoder), 0, 0);
>
> - psr_event_print(dev_priv, val, intel_dp-
> >psr.psr2_enabled);
> + psr_event_print(dev_priv, val, intel_dp-
> >psr.sel_update_enabled);
> }
> }
>
> @@ -636,7 +636,7 @@ static void intel_psr_enable_sink(struct intel_dp
> *intel_dp)
> if (intel_dp->psr.panel_replay_enabled)
> return;
>
> - if (intel_dp->psr.psr2_enabled) {
> + if (intel_dp->psr.sel_update_enabled) {
> /* Enable ALPM at sink for psr2 */
> drm_dp_dpcd_writeb(_dp->aux,
> DP_RECEIVER_ALPM_CONFIG,
> DP_ALPM_ENABLE |
> @@ -1446,10 +1446,10 @@ void intel_psr_get_config(struct intel_encoder
> *encoder,
> pipe_config->has_psr = true;
> }
>
> - pipe_config->has_sel_update = intel_dp->psr.psr2_enabled;
> + pipe_config->has_sel_update = intel_dp->psr.sel_update_enabled;
> pipe_config->infoframes.enable |=
> intel_hdmi_infoframe_enable(DP_SDP_VSC);
>
> - if (!intel_dp->psr.psr2_enabled)
> + if (!intel_dp->psr.sel_update_enabled)
> goto unlock;
>
> if (HAS_PSR2_SEL_FETCH(dev_priv)) {
> @@ -1485,7 +1485,7 @@ static void intel_psr_activate(struct intel_dp
> *intel_dp)
> /* psr1, psr2 and panel-replay are mutually exclusive.*/
> if (intel_dp->psr.panel_replay_enabled)
> dg2_activate_panel_replay(intel_dp);
> - else if (intel_dp->psr.psr2_enabled)
> + else if (intel_dp->psr.sel_update_enabled)
> hsw_activate_psr2(intel_dp);
> else
> hsw_activate_psr1(intel_dp);
> @@ -1598,7 +1598,7 @@ static void intel_psr_enable_source(struct intel_dp
> *intel_dp,
>*/
> wm_optimization_wa(intel_dp, crtc_state);
>
> - if (intel_dp->psr.psr2_enabled) {
> + if (intel_dp->psr.sel_update_enabled) {
> if (DISPLAY_VER(dev_priv) == 9)
> intel_de_rmw(dev_priv,
> CHICKEN_TRANS(cpu_transcoder), 0,
>PSR2_VSC_ENABLE_PROG_HEADER |
> @@ -1661,7 +1661,7 @@ static void intel_psr_enable_locked(struct
RE: [PATCH v2 05/13] drm/i915/psr: Rename has_psr2 as has_sel_update
> -Original Message-
> From: Intel-gfx On Behalf Of Jouni
> Högander
> Sent: Wednesday, January 10, 2024 6:43 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [PATCH v2 05/13] drm/i915/psr: Rename has_psr2 as
> has_sel_update
>
> We are going to reuse has_psr2 for panel_replay as well. Rename it as
> has_sel_update to avoid confusion.
Changes looks good to me..
Only nitpick: The documentation patch describing about
psr/panel-replay/selective-update flags maybe good to put before this patch.
Reviewed-by: Animesh Manna
>
> Signed-off-by: Jouni Högander
> ---
> drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 5 +++--
> drivers/gpu/drm/i915/display/intel_display.c | 2 +-
> drivers/gpu/drm/i915/display/intel_display_types.h | 2 +-
> drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
> drivers/gpu/drm/i915/display/intel_fbc.c | 2 +-
> drivers/gpu/drm/i915/display/intel_psr.c | 8
> 6 files changed, 11 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> index 49fd100ec98a..5edbc9b3d766 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> @@ -266,9 +266,10 @@ void intel_crtc_state_dump(const struct
> intel_crtc_state *pipe_config,
> drm_dbg_kms(>drm, "sdp split: %s\n",
> str_enabled_disabled(pipe_config-
> >sdp_split_enable));
>
> - drm_dbg_kms(>drm, "psr: %s, psr2: %s, panel replay:
> %s, selective fetch: %s\n",
> + drm_dbg_kms(>drm,
> + "psr: %s, selective update: %s, panel replay: %s,
> selective
> +fetch: %s\n",
> str_enabled_disabled(pipe_config->has_psr),
> - str_enabled_disabled(pipe_config->has_psr2),
> + str_enabled_disabled(pipe_config-
> >has_sel_update),
> str_enabled_disabled(pipe_config-
> >has_panel_replay),
> str_enabled_disabled(pipe_config-
> >enable_psr2_sel_fetch));
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index c5de4561f458..433276f24ae4 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5215,7 +5215,7 @@ intel_pipe_config_compare(const struct
> intel_crtc_state *current_config,
>
> if (current_config->active_planes) {
> PIPE_CONF_CHECK_BOOL(has_psr);
> - PIPE_CONF_CHECK_BOOL(has_psr2);
> + PIPE_CONF_CHECK_BOOL(has_sel_update);
> PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
> PIPE_CONF_CHECK_I(dc3co_exitline);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 6340fabd045c..8fdab2f0c546 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1211,7 +1211,7 @@ struct intel_crtc_state {
>
> /* PSR is supported but might not be enabled due the lack of enabled
> planes */
> bool has_psr;
> - bool has_psr2;
> + bool has_sel_update;
> bool enable_psr2_sel_fetch;
> bool enable_psr2_su_region_et;
> bool req_psr2_sdp_prior_scanline;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 7e4b7d5606d4..a26db4012172 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2633,7 +2633,7 @@ static void intel_dp_compute_vsc_sdp(struct
> intel_dp *intel_dp,
> if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
> intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
>vsc);
> - } else if (crtc_state->has_psr2) {
> + } else if (crtc_state->has_psr && crtc_state->has_sel_update) {
> /*
>* [PSR2 without colorimetry]
>* Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index f17a1afb4929..647dd1b56073 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -1235,7 +1235,7 @@ static int intel_fbc_check_plane(struct
> intel_atomic_state *state,
>* Recommendation is to keep this combination disabled
>* Bspec: 50422 HSD: 14010260002
>*/
> - if (IS_DISPLAY_VER(i915, 12, 14) && crtc_state->has_psr2) {
> + if (IS_DISPLAY_VER(i915, 12, 14) && crtc_state->has_sel_update) {
> plane_state->no_fbc_reason = "PSR2 enabled";
>
RE: [PATCH v2 04/13] drm/i915/psr: Unify panel replay enable sink
> -Original Message-
> From: Intel-gfx On Behalf Of Jouni
> Högander
> Sent: Wednesday, January 10, 2024 6:43 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [PATCH v2 04/13] drm/i915/psr: Unify panel replay enable sink
>
> Panel replay enable for a sink is currently done in
> intel_ddi.c:intel_ddi_pre_enable_dp. Move it to intel_psr_enable_sink to
> unify psr/panel replay paths. Also enable some additional hpd interrupts for
> panel replay.
There is a difference between psr and panel replay regarding sink enablement.
For panel replay sink need to be enabled before link training which is not same
for psr.
Regards,
Animesh
>
> Signed-off-by: Jouni Högander
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 7 +--
> drivers/gpu/drm/i915/display/intel_psr.c | 19 +--
> 2 files changed, 18 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 922194b957be..db2a027fc55e 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2800,15 +2800,10 @@ static void intel_ddi_pre_enable_dp(struct
> intel_atomic_state *state,
> const struct drm_connector_state
> *conn_state) {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>
> - if (HAS_DP20(dev_priv)) {
> + if (HAS_DP20(dev_priv))
> intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder),
> crtc_state);
> - if (crtc_state->has_panel_replay)
> - drm_dp_dpcd_writeb(_dp->aux,
> PANEL_REPLAY_CONFIG,
> -DP_PANEL_REPLAY_ENABLE);
> - }
>
> if (DISPLAY_VER(dev_priv) >= 14)
> mtl_ddi_pre_enable_dp(state, encoder, crtc_state,
> conn_state); diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index a9421dd092c5..8157a1eac8c2 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -618,6 +618,16 @@ static bool psr2_su_region_et_valid(struct intel_dp
> *intel_dp)
> return false;
> }
>
> +static unsigned int intel_psr_get_enable_sink_offset(struct intel_dp
> +*intel_dp) {
> + return intel_dp->psr.panel_replay_enabled ?
> + PANEL_REPLAY_CONFIG : DP_PSR_EN_CFG;
> +}
> +
> +/*
> + * Note: Most of the bits are same in PANEL_REPLAY_CONFIG and
> +DP_PSR_EN_CFG. We
> + * are relying on PSR definitions on these "common" bits.
> + */
> static void intel_psr_enable_sink(struct intel_dp *intel_dp) {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); @@ -
> 643,15 +653,20 @@ static void intel_psr_enable_sink(struct intel_dp
> *intel_dp)
> dpcd_val |= DP_PSR_CRC_VERIFICATION;
> }
>
> + if (intel_dp->psr.panel_replay_enabled)
> + dpcd_val |=
> DP_PANEL_REPLAY_UNRECOVERABLE_ERROR_EN |
> + DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN;
> +
> if (intel_dp->psr.req_psr2_sdp_prior_scanline)
> dpcd_val |= DP_PSR_SU_REGION_SCANLINE_CAPTURE;
>
> if (intel_dp->psr.entry_setup_frames > 0)
> dpcd_val |= DP_PSR_FRAME_CAPTURE;
>
> - drm_dp_dpcd_writeb(_dp->aux, DP_PSR_EN_CFG, dpcd_val);
> + drm_dp_dpcd_writeb(_dp->aux,
> +intel_psr_get_enable_sink_offset(intel_dp), dpcd_val);
>
> - drm_dp_dpcd_writeb(_dp->aux, DP_SET_POWER,
> DP_SET_POWER_D0);
> + if (intel_dp_is_edp(intel_dp))
> + drm_dp_dpcd_writeb(_dp->aux, DP_SET_POWER,
> DP_SET_POWER_D0);
> }
>
> static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp)
> --
> 2.34.1
RE: [PATCH v2 03/13] drm/i915/psr: Do not check alpm on DP or capability change for panel replay
> -Original Message- > From: Intel-gfx On Behalf Of Jouni > Högander > Sent: Wednesday, January 10, 2024 6:43 PM > To: intel-gfx@lists.freedesktop.org > Subject: [PATCH v2 03/13] drm/i915/psr: Do not check alpm on DP or > capability change for panel replay > > Alpm is eDP specific. Do not check if not eDP. Also panel replay doesn't know > about capability changes -> no need to check that. > > Signed-off-by: Jouni Högander > --- > drivers/gpu/drm/i915/display/intel_psr.c | 7 +-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > b/drivers/gpu/drm/i915/display/intel_psr.c > index 3e287a9f0e09..a9421dd092c5 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -2989,8 +2989,11 @@ void intel_psr_short_pulse(struct intel_dp > *intel_dp) > /* clear status register */ > drm_dp_dpcd_writeb(_dp->aux, DP_PSR_ERROR_STATUS, > error_status); > > - psr_alpm_check(intel_dp); > - psr_capability_changed_check(intel_dp); > + if (intel_dp_is_edp(intel_dp)) > + psr_alpm_check(intel_dp); > + > + if (!psr->panel_replay_enabled) > + psr_capability_changed_check(intel_dp); There is a CAN_PSR() check starting of the function intel_psr_short_pulse() which will take care non-edp and panel replay case, so do you see any gap there? Regards, Animesh > > exit: > mutex_unlock(>lock); > -- > 2.34.1
RE: [PATCH v2 02/13] drm/i915/psr: Intel_psr_pause/resume needs to support panel replay
> -Original Message-
> From: Intel-gfx On Behalf Of Jouni
> Högander
> Sent: Wednesday, January 10, 2024 6:43 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [PATCH v2 02/13] drm/i915/psr: Intel_psr_pause/resume needs to
> support panel replay
>
> Currently intel_psr_pause and intel_psr_resume do nothing in case of panel
> replay. Change them to perform pause and return also in case of panel
> replay.
>
> Signed-off-by: Jouni Högander
Changes looks good to me.
Reviewed-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 9705a75e063a..3e287a9f0e09 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1829,7 +1829,7 @@ void intel_psr_pause(struct intel_dp *intel_dp)
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> struct intel_psr *psr = _dp->psr;
>
> - if (!CAN_PSR(intel_dp))
> + if (!CAN_PSR(intel_dp) && !CAN_PANEL_REPLAY(intel_dp))
> return;
>
> mutex_lock(>lock);
> @@ -1862,7 +1862,7 @@ void intel_psr_resume(struct intel_dp *intel_dp) {
> struct intel_psr *psr = _dp->psr;
>
> - if (!CAN_PSR(intel_dp))
> + if (!CAN_PSR(intel_dp) && !CAN_PANEL_REPLAY(intel_dp))
> return;
>
> mutex_lock(>lock);
> --
> 2.34.1
RE: [PATCH v2 01/13] drm/i915/psr: Disable panel replay for now
> -Original Message-
> From: Intel-gfx On Behalf Of Jouni
> Högander
> Sent: Wednesday, January 10, 2024 6:43 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [PATCH v2 01/13] drm/i915/psr: Disable panel replay for now
>
> Panel replay is not completely validated yet. Let's disable it for now.
Hi,
As I understood currently the feature is not tested due to unavailability of
the panel and at the same time good to check negative testing like if this
feature is causing any regression for other feature like psr/psr2. Instead of
hardcoding Is it ok to have a kernel cmdline parameter to enable/disable this
feature? Can you please share your view.
Regards,
Animesh
>
> Signed-off-by: Jouni Högander
> ---
> drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
> drivers/gpu/drm/i915/display/intel_psr.c | 10 +-
> 2 files changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index ae2e8cff9d69..6340fabd045c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1692,6 +1692,7 @@ struct intel_psr {
> #define I915_PSR_DEBUG_ENABLE_SEL_FETCH 0x4
> #define I915_PSR_DEBUG_IRQ 0x10
> #define I915_PSR_DEBUG_SU_REGION_ET_DISABLE 0x20
> +#define I915_PSR_DEBUG_PANEL_REPLAY_DISABLE 0x40
>
> u32 debug;
> bool sink_support;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index dff21a5edeb7..9705a75e063a 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -214,6 +214,11 @@ static bool psr2_global_enabled(struct intel_dp
> *intel_dp)
> }
> }
>
> +static bool panel_replay_global_enabled(struct intel_dp *intel_dp) {
> + return !(intel_dp->psr.debug &
> I915_PSR_DEBUG_PANEL_REPLAY_DISABLE);
> +}
> +
> static u32 psr_irq_psr_error_bit_get(struct intel_dp *intel_dp) {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); @@ -
> 1386,7 +1391,7 @@ void intel_psr_compute_config(struct intel_dp
> *intel_dp,
> }
>
> if (CAN_PANEL_REPLAY(intel_dp))
> - crtc_state->has_panel_replay = true;
> + crtc_state->has_panel_replay =
> panel_replay_global_enabled(intel_dp);
> else
> crtc_state->has_psr = _psr_compute_config(intel_dp,
> crtc_state);
>
> @@ -2845,6 +2850,9 @@ void intel_psr_init(struct intel_dp *intel_dp)
> /* Disable early transport for now */
> intel_dp->psr.debug |= I915_PSR_DEBUG_SU_REGION_ET_DISABLE;
>
> + /* Disable panel replay for now */
> + intel_dp->psr.debug |= I915_PSR_DEBUG_PANEL_REPLAY_DISABLE;
> +
> /* Set link_standby x link_off defaults */
> if (DISPLAY_VER(dev_priv) < 12)
> /* For new platforms up to TGL let's respect VBT back again
> */
> --
> 2.34.1
Re: [Intel-gfx] [PATCH] drm/i915/edp: don't write to DP_LINK_BW_SET when using rate select
> -Original Message-
> From: Nikula, Jani
> Sent: Monday, December 4, 2023 3:28 PM
> To: Ville Syrjälä
> Cc: intel-gfx@lists.freedesktop.org; Manna, Animesh
>
> Subject: Re: [Intel-gfx] [PATCH] drm/i915/edp: don't write to
> DP_LINK_BW_SET when using rate select
>
> On Fri, 01 Dec 2023, Ville Syrjälä wrote:
> > On Fri, Dec 01, 2023 at 03:41:41PM +0200, Jani Nikula wrote:
> >> The eDP 1.5 spec adds a clarification for eDP 1.4x:
> >>
> >> > For eDP v1.4x, if the Source device chooses the Main-Link rate by
> >> > way of DPCD 00100h, the Sink device shall ignore DPCD 00115h[2:0].
> >>
> >> We write 0 to DP_LINK_BW_SET (DPCD 100h) even when using
> >> DP_LINK_RATE_SET (DPCD 114h). Stop doing that, as it can cause the
> >> panel to ignore the rate set method.
> >
> > What a terrible way to specify this :( This means the device must hav
> > some internal state to keep track of whethe BW_SET was ever written.
>
> Indeed.
>
> Additionally, eDP 1.5 specifies LINK_CONFIGURATION_STATUS (DPCD
> 0020Ch) which exposes the internal state as link rate set status, and whether
> that status is valid or not.
>
> Overall the spec looks like that's just for status, but the register is
> annotated
> Write/Read so who knows.
>
> >
> >>
> >> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9081
> >> Tested-by: Animesh Manna
> >> Signed-off-by: Jani Nikula
> >> ---
> >> .../drm/i915/display/intel_dp_link_training.c | 23
> >> +++
> >> 1 file changed, 13 insertions(+), 10 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> >> b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> >> index dbc1b66c8ee4..6336a39030a4 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> >> @@ -650,19 +650,22 @@ intel_dp_update_link_bw_set(struct intel_dp
> *intel_dp,
> >>const struct intel_crtc_state *crtc_state,
> >>u8 link_bw, u8 rate_select)
> >> {
> >> - u8 link_config[2];
> >> + u8 lane_count = crtc_state->lane_count;
> >>
> >> - /* Write the link configuration data */
> >> - link_config[0] = link_bw;
> >> - link_config[1] = crtc_state->lane_count;
> >>if (crtc_state->enhanced_framing)
> >> - link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
> >> - drm_dp_dpcd_write(_dp->aux, DP_LINK_BW_SET, link_config,
> 2);
> >> + lane_count |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
> >> +
> >> + if (link_bw) {
> >> + /* eDP 1.3 and earlier link bw set method. */
> >> + u8 link_config[] = { link_bw, lane_count };
> >>
> >> - /* eDP 1.4 rate select method. */
> >> - if (!link_bw)
> >> - drm_dp_dpcd_write(_dp->aux, DP_LINK_RATE_SET,
> >> -_select, 1);
> >> + drm_dp_dpcd_write(_dp->aux, DP_LINK_BW_SET,
> link_config,
> >> +ARRAY_SIZE(link_config));
> >> + } else {
> >> + /* eDP 1.4 rate select method. */
> >> + drm_dp_dpcd_writeb(_dp->aux,
> DP_LANE_COUNT_SET, lane_count);
> >> + drm_dp_dpcd_writeb(_dp->aux, DP_LINK_RATE_SET,
> rate_select);
> >
> > Doesn't look there's anything in the spec that specifies when the
> > device is supposed to reset its internal state to stop ignoring
> DP_LINK_RATE_SET.
> > Do we know when this panel does it? When VDD is removed?
>
> No idea. Animesh?
Hi Jani/Ville,
Tried below experiment and sharing my observation below:
Forcefully changed the value of dpcd 0x100 (LINK_BW_SET) to random value (0x99)
in edp_init_connector and later while VDD is on during modeset sequence I can
see it is not holding its value rather got reset to default value. This will
confirm when VDD is removed panel reset its internal state.
Regards,
Animesh
>
> I think it's just crazy writing 0 to explicitly disable DP_LINK_BW_SET renders
> DP_LINK_RATE_SET unusable. Pretty sure we've seen panels where this
> works as you'd expect.
>
> And the above depends on pre-os using the same logic as us for choosing
> DP_LINK_RATE_SET. GOP seems to do that. But if it or some other pre-os
> used DP_LINK_BW_SET, we'd fail. With some other panels, writing the 0
> might recover from that.
>
> No r-b, so do you have any better ideas?
>
>
> BR,
> Jani.
>
>
> >
> >> + }
> >> }
> >>
> >> /*
> >> --
> >> 2.39.2
>
> --
> Jani Nikula, Intel
Re: [Intel-gfx] [PATCH] drm/i915/display: Do not check psr2 if psr/panel replay is not supported
> -Original Message-
> From: Hogander, Jouni
> Sent: Monday, November 20, 2023 6:32 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Hogander, Jouni ; Manna, Animesh
>
> Subject: [PATCH] drm/i915/display: Do not check psr2 if psr/panel replay is
> not supported
>
> Do not continue to psr2 checks if psr or panel replay is not supported.
>
> Cc: Animesh Manna
>
> Fixes: b8cf5b5d266e ("drm/i915/panelreplay: Initializaton and compute
> config for panel replay")
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9670
> Signed-off-by: Jouni Högander
LGTM.
Reviewed-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 8d180132a74b..9aa1c269cfef 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1373,6 +1373,9 @@ void intel_psr_compute_config(struct intel_dp
> *intel_dp,
> else
> crtc_state->has_psr = _psr_compute_config(intel_dp,
> crtc_state);
>
> + if (!(crtc_state->has_panel_replay || crtc_state->has_psr))
> + return;
> +
> crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state);
>
> crtc_state->infoframes.enable |=
> intel_hdmi_infoframe_enable(DP_SDP_VSC);
> --
> 2.34.1
Re: [Intel-gfx] [PATCH v6] drm/i915/dsb: DSB code refactoring
> -Original Message- > From: Coelho, Luciano > Sent: Tuesday, November 14, 2023 4:47 PM > To: Manna, Animesh ; intel- > g...@lists.freedesktop.org > Cc: Nikula, Jani > Subject: Re: [Intel-gfx] [PATCH v6] drm/i915/dsb: DSB code refactoring > > On Fri, 2023-11-10 at 08:55 +0530, Animesh Manna wrote: > > Refactor DSB implementation to be compatible with Xe driver. > > > > v1: RFC version. > > v2: Make intel_dsb structure opaque from external usage. [Jani] > > v3: Rebased on latest. > > v4: > > - Add boundary check in dsb_buffer_memset(). [Luca] > > - Use size_t instead of u32. [Luca] > > v5: WARN_ON() added for out of boudary case with some optimization. > [Luca] > > ...and what is different in v6? Rebased on latest and fix a rebase-miss which CI did not caught well. Before merging want the green signal from CI. Regards, Animesh > > -- > Cheers, > Luca.
Re: [Intel-gfx] [PATCH v9 1/6] drm/panelreplay: dpcd register definition for panelreplay
> -Original Message- > From: Nikula, Jani > Sent: Thursday, November 9, 2023 6:37 PM > To: Manna, Animesh ; intel- > g...@lists.freedesktop.org; dri-de...@lists.freedesktop.org > Cc: Manna, Animesh ; Hogander, Jouni > ; Murthy, Arun R > Subject: Re: [PATCH v9 1/6] drm/panelreplay: dpcd register definition for > panelreplay > > On Wed, 08 Nov 2023, Animesh Manna wrote: > > Add DPCD register definition for discovering, enabling and checking > > status of panel replay of the sink. > > > > Cc: Jouni Högander > > Cc: Arun R Murthy > > Cc: Jani Nikula > > Reviewed-by: Arun R Murthy > > Signed-off-by: Animesh Manna > > You got the ack, please keep track of it. > > https://lore.kernel.org/r/elcebygxs432bcj7oez7ndlfvb3lru7m7yznyqp2ei4ocjk > vxp@23lf2rh45fmt Thanks Jani and everyone who helped in review. Pushed the initial 5 patches of this series. As 6th patch has dependency on igt changes, will push after igt changes get merged. Regards, Animesh > > > --- > > include/drm/display/drm_dp.h | 23 +++ > > 1 file changed, 23 insertions(+) > > > > diff --git a/include/drm/display/drm_dp.h > > b/include/drm/display/drm_dp.h index e69cece404b3..fc42b622ef32 > 100644 > > --- a/include/drm/display/drm_dp.h > > +++ b/include/drm/display/drm_dp.h > > @@ -543,6 +543,10 @@ > > /* DFP Capability Extension */ > > #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT0x0a3 /* 2.0 */ > > > > +#define DP_PANEL_REPLAY_CAP 0x0b0 /* DP 2.0 */ > > +# define DP_PANEL_REPLAY_SUPPORT(1 << 0) > > +# define DP_PANEL_REPLAY_SU_SUPPORT (1 << 1) > > + > > /* Link Configuration */ > > #defineDP_LINK_BW_SET 0x100 > > # define DP_LINK_RATE_TABLE0x00/* eDP 1.4 */ > > @@ -716,6 +720,13 @@ > > #define DP_BRANCH_DEVICE_CTRL 0x1a1 > > # define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0) > > > > +#define PANEL_REPLAY_CONFIG 0x1b0 /* DP 2.0 */ > > +# define DP_PANEL_REPLAY_ENABLE (1 << 0) > > +# define DP_PANEL_REPLAY_UNRECOVERABLE_ERROR_EN (1 << 3) > > +# define DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN (1 << 4) > > +# define DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN (1 << 5) > > +# define DP_PANEL_REPLAY_SU_ENABLE (1 << 6) > > + > > #define DP_PAYLOAD_ALLOCATE_SET0x1c0 > > #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1 #define > > DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2 @@ -1105,6 +1116,18 > @@ > > #define DP_LANE_ALIGN_STATUS_UPDATED_ESI 0x200e /* status same > as 0x204 */ > > #define DP_SINK_STATUS_ESI 0x200f /* status same as > > 0x205 */ > > > > +#define DP_PANEL_REPLAY_ERROR_STATUS 0x2020 /* DP 2.1*/ > > +# define DP_PANEL_REPLAY_LINK_CRC_ERROR(1 << 0) > > +# define DP_PANEL_REPLAY_RFB_STORAGE_ERROR (1 << 1) > > +# define DP_PANEL_REPLAY_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2) > > + > > +#define DP_SINK_DEVICE_PR_AND_FRAME_LOCK_STATUS0x2022 /* > DP 2.1 */ > > +# define DP_SINK_DEVICE_PANEL_REPLAY_STATUS_MASK (7 << 0) > > +# define DP_SINK_FRAME_LOCKED_SHIFT3 > > +# define DP_SINK_FRAME_LOCKED_MASK (3 << 3) > > +# define DP_SINK_FRAME_LOCKED_STATUS_VALID_SHIFT 5 > > +# define DP_SINK_FRAME_LOCKED_STATUS_VALID_MASK(1 << 5) > > + > > /* Extended Receiver Capability: See DP_DPCD_REV for definitions */ > > #define DP_DP13_DPCD_REV0x2200 > > -- > Jani Nikula, Intel
Re: [Intel-gfx] [PATCH v8 6/6] drm/i915/panelreplay: Debugfs support for panel replay
> -Original Message-
> From: Hogander, Jouni
> Sent: Monday, November 6, 2023 1:33 PM
> To: dri-de...@lists.freedesktop.org; Manna, Animesh
> ; intel-gfx@lists.freedesktop.org
> Cc: Murthy, Arun R ; Nikula, Jani
>
> Subject: Re: [PATCH v8 6/6] drm/i915/panelreplay: Debugfs support for
> panel replay
>
> Hello Animesh,
>
> Thank you for the changes. Now the patch is much shorter, cleaner and
> easier to review. See my inline comments below.
>
> On Sat, 2023-11-04 at 02:30 +0530, Animesh Manna wrote:
> > Add debugfs support which will print source and sink status per
> > connector basis. Existing i915_psr_status and i915_psr_sink_status
> > will be used to get the source and sink status of panel replay.
> >
> > v1: Initial version. [rb-ed by Arun]
> > v2: Added check for DP 2.0 and connector type in
> > connector_debugfs_add().
> > v3: Optimization and cosmetic changes. [Jouni]
> >
> > Cc: Jouni Högander
> > Cc: Arun R Murthy
> > Cc: Jani Nikula
> > Reviewed-by: Arun R Murthy
> > Signed-off-by: Animesh Manna
> > ---
> > drivers/gpu/drm/i915/display/intel_psr.c | 93 +-
> > --
> > 1 file changed, 66 insertions(+), 27 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 8ed4684b4528..8b7c03cd4989 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -2813,12 +2813,19 @@ static int
> > psr_get_status_and_error_status(struct intel_dp *intel_dp,
> > {
> > struct drm_dp_aux *aux = _dp->aux;
> > int ret;
> > + unsigned int offset;
> >
> > - ret = drm_dp_dpcd_readb(aux, DP_PSR_STATUS, status);
> > + offset = intel_dp->psr.panel_replay_enabled ?
> > + DP_SINK_DEVICE_PR_AND_FRAME_LOCK_STATUS :
> > DP_PSR_STATUS;
> > +
> > + ret = drm_dp_dpcd_readb(aux, offset, status);
> > if (ret != 1)
> > return ret;
> >
> > - ret = drm_dp_dpcd_readb(aux, DP_PSR_ERROR_STATUS,
> > error_status);
> > + offset = intel_dp->psr.panel_replay_enabled ?
> > + DP_PANEL_REPLAY_ERROR_STATUS : DP_PSR_ERROR_STATUS;
> > +
> > + ret = drm_dp_dpcd_readb(aux, offset, error_status);
> > if (ret != 1)
> > return ret;
> >
> > @@ -3039,7 +3046,7 @@ psr_source_status(struct intel_dp *intel_dp,
> > struct seq_file *m)
> > status = live_status[status_val];
> > }
> >
> > - seq_printf(m, "Source PSR status: %s [0x%08x]\n", status,
> > val);
> > + seq_printf(m, "Source PSR/PanelReplay status: %s [0x%08x]\n",
> > status, val);
> > }
> >
> > static int intel_psr_status(struct seq_file *m, struct intel_dp
> > *intel_dp)
> > @@ -3052,18 +3059,23 @@ static int intel_psr_status(struct seq_file
> > *m, struct intel_dp *intel_dp)
> > bool enabled;
> > u32 val;
> >
> > - seq_printf(m, "Sink support: %s", str_yes_no(psr-
> > >sink_support));
> > - if (psr->sink_support)
> > + seq_printf(m, "Sink support: PSR = %s, Panel Replay = %s",
> > + str_yes_no(psr->sink_support),
> > + str_yes_no(psr->sink_panel_replay_support));
> > +
> > + if (psr->sink_support || psr->sink_panel_replay_support)
> > seq_printf(m, " [0x%02x]", intel_dp->psr_dpcd[0]);
>
> The output will look like this:
>
> Sink support: PSR = yes, Panel Replay = yes, [0x01]
>
> I think more logical would be:
>
> Sink support: PSR = yes [0x01], Panel Replay = yes
>
>
> > seq_puts(m, "\n");
> >
> > - if (!psr->sink_support)
> > + if (!(psr->sink_support || psr->sink_panel_replay_support))
> > return 0;
> >
> > wakeref = intel_runtime_pm_get(_priv->runtime_pm);
> > mutex_lock(>lock);
> >
> > - if (psr->enabled)
> > + if (psr->panel_replay_enabled)
> > + status = "Panel Replay Enabled";
> > + else if (psr->enabled)
> > status = psr->psr2_enabled ? "PSR2 enabled" : "PSR1
> > enabled";
> > else
> > status = "disabled";
> > @@ -3076,14 +3088,17 @@ static int i
Re: [Intel-gfx] [PATCH v7 1/6] drm/panelreplay: dpcd register definition for panelreplay
> -Original Message- > From: Nikula, Jani > Sent: Friday, November 3, 2023 2:55 PM > To: Manna, Animesh ; intel- > g...@lists.freedesktop.org; Maxime Ripard ; Thomas > Zimmermann ; Maarten Lankhorst > > Cc: dri-de...@lists.freedesktop.org; Manna, Animesh > ; Hogander, Jouni > ; Murthy, Arun R > Subject: Re: [PATCH v7 1/6] drm/panelreplay: dpcd register definition for > panelreplay > > On Wed, 11 Oct 2023, Animesh Manna wrote: > > Add DPCD register definition for discovering, enabling and checking > > status of panel replay of the sink. > > > > Cc: Jouni Högander > > Cc: Arun R Murthy > > Cc: Jani Nikula > > Reviewed-by: Arun R Murthy > > Signed-off-by: Animesh Manna > > Maarten, Maxime, Thomas - > > Ack for merging this via drm-intel-next? Ping! Regards, Animesh > > Thanks, > Jani. > > > --- > > include/drm/display/drm_dp.h | 23 +++ > > 1 file changed, 23 insertions(+) > > > > diff --git a/include/drm/display/drm_dp.h > > b/include/drm/display/drm_dp.h index e69cece404b3..fc42b622ef32 > 100644 > > --- a/include/drm/display/drm_dp.h > > +++ b/include/drm/display/drm_dp.h > > @@ -543,6 +543,10 @@ > > /* DFP Capability Extension */ > > #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT0x0a3 /* 2.0 */ > > > > +#define DP_PANEL_REPLAY_CAP 0x0b0 /* DP 2.0 */ > > +# define DP_PANEL_REPLAY_SUPPORT(1 << 0) > > +# define DP_PANEL_REPLAY_SU_SUPPORT (1 << 1) > > + > > /* Link Configuration */ > > #defineDP_LINK_BW_SET 0x100 > > # define DP_LINK_RATE_TABLE0x00/* eDP 1.4 */ > > @@ -716,6 +720,13 @@ > > #define DP_BRANCH_DEVICE_CTRL 0x1a1 > > # define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0) > > > > +#define PANEL_REPLAY_CONFIG 0x1b0 /* DP 2.0 */ > > +# define DP_PANEL_REPLAY_ENABLE (1 << 0) > > +# define DP_PANEL_REPLAY_UNRECOVERABLE_ERROR_EN (1 << 3) > > +# define DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN (1 << 4) > > +# define DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN (1 << 5) > > +# define DP_PANEL_REPLAY_SU_ENABLE (1 << 6) > > + > > #define DP_PAYLOAD_ALLOCATE_SET0x1c0 > > #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1 #define > > DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2 @@ -1105,6 +1116,18 > @@ > > #define DP_LANE_ALIGN_STATUS_UPDATED_ESI 0x200e /* status same > as 0x204 */ > > #define DP_SINK_STATUS_ESI 0x200f /* status same as > > 0x205 */ > > > > +#define DP_PANEL_REPLAY_ERROR_STATUS 0x2020 /* DP 2.1*/ > > +# define DP_PANEL_REPLAY_LINK_CRC_ERROR(1 << 0) > > +# define DP_PANEL_REPLAY_RFB_STORAGE_ERROR (1 << 1) > > +# define DP_PANEL_REPLAY_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2) > > + > > +#define DP_SINK_DEVICE_PR_AND_FRAME_LOCK_STATUS0x2022 /* > DP 2.1 */ > > +# define DP_SINK_DEVICE_PANEL_REPLAY_STATUS_MASK (7 << 0) > > +# define DP_SINK_FRAME_LOCKED_SHIFT3 > > +# define DP_SINK_FRAME_LOCKED_MASK (3 << 3) > > +# define DP_SINK_FRAME_LOCKED_STATUS_VALID_SHIFT 5 > > +# define DP_SINK_FRAME_LOCKED_STATUS_VALID_MASK(1 << 5) > > + > > /* Extended Receiver Capability: See DP_DPCD_REV for definitions */ > > #define DP_DP13_DPCD_REV0x2200 > > -- > Jani Nikula, Intel
Re: [Intel-gfx] [PATCH v7 6/6] drm/i915/panelreplay: Debugfs support for panel replay
> -Original Message-
> From: Hogander, Jouni
> Sent: Friday, November 3, 2023 12:32 PM
> To: Manna, Animesh ; intel-
> g...@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org; Murthy, Arun R
> ; Nikula, Jani
> Subject: Re: [PATCH v7 6/6] drm/i915/panelreplay: Debugfs support for
> panel replay
>
> On Fri, 2023-11-03 at 06:10 +, Manna, Animesh wrote:
> >
> >
> > > -Original Message-
> > > From: Hogander, Jouni
> > > Sent: Thursday, November 2, 2023 1:08 PM
> > > To: Manna, Animesh ; intel-
> > > g...@lists.freedesktop.org
> > > Cc: dri-de...@lists.freedesktop.org; Murthy, Arun R
> > > ; Nikula, Jani
> > > Subject: Re: [PATCH v7 6/6] drm/i915/panelreplay: Debugfs support
> > > for panel replay
> > >
> > > On Wed, 2023-10-11 at 16:39 +0530, Animesh Manna wrote:
> > > > Add debugfs support which will print source and sink status per
> > > > connector basis.
> > >
> > > Sorry for late review. Noticed only by now that you have added this
> > > patch into you set.
> >
> > Added from v5.
> >
> > >
> > > Can you please describe in commit message how you see the output of
> > > debugfs interface will look like after your changes?
> >
> > Sure.
> >
> > >
> > > >
> > > > v1: Initial version. [rb-ed by Arun]
> > > > v2: Added check for DP 2.0 and connector type in
> > > > connector_debugfs_add().
> > > >
> > > > Cc: Jouni Högander
> > > > Cc: Arun R Murthy
> > > > Cc: Jani Nikula
> > > > Signed-off-by: Animesh Manna
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_psr.c | 136
> > > > +
> > > > --
> > > > 1 file changed, 102 insertions(+), 34 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > index 80de831c2f60..399fc0a8e636 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > @@ -2823,6 +2823,25 @@ static int
> > > > psr_get_status_and_error_status(struct intel_dp *intel_dp,
> > > > return 0;
> > > > }
> > > >
> > > > +static int panel_replay_get_status_and_error_status(struct
> > > > intel_dp
> > > > *intel_dp,
> > > > + u8 *status,
> > > > u8
> > > > *error_status)
> > > > +{
> > > > + struct drm_dp_aux *aux = _dp->aux;
> > > > + int ret;
> > > > +
> > > > + ret = drm_dp_dpcd_readb(aux,
> > > > DP_SINK_DEVICE_PR_AND_FRAME_LOCK_STATUS, status);
> > > > + if (ret != 1)
> > > > + return ret;
> > > > +
> > > > + ret = drm_dp_dpcd_readb(aux,
> > > > DP_PANEL_REPLAY_ERROR_STATUS,
> > > > error_status);
> > > > + if (ret != 1)
> > > > + return ret;
> > > > +
> > > > + *status = *status & DP_PSR_SINK_STATE_MASK;
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > >
> > > I think you should modify psr_get_status_and_error_status instead
> > > of duplicating most of it.
> >
> > DPCD addresses are different for panel replay, I did not get the need
> > of it.
>
> I would like to see:
>
> unsigned int offset = intel_dp->psr.panel_replay_enabled ?
> DP_SINK_DEVICE_PR_AND_FRAME_LOCK_STATUS : DP_PSR_STATUS;
>
> ret = drm_dp_dpcd_readb(aux, offset, status);
>
> rather than duplicating it.
Added in v8.
>
> >
> > >
> > > > static void psr_alpm_check(struct intel_dp *intel_dp)
> > > > {
> > > > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > > > @@
> > > > -3035,7 +3054,7 @@ psr_source_status(struct intel_dp *intel_dp,
> > > > struct seq_file *m)
> > > > status = live_status[status_val];
> > > > }
> > > >
> > > > - seq_printf(m, "Source PSR status: %s [0x%08x]\n", status,
> > > > val);
> > > > + seq_printf(m, "Source PSR/PanelReplay status: %s
> > >
Re: [Intel-gfx] [PATCH v7 6/6] drm/i915/panelreplay: Debugfs support for panel replay
> -Original Message-
> From: Hogander, Jouni
> Sent: Thursday, November 2, 2023 1:08 PM
> To: Manna, Animesh ; intel-
> g...@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org; Murthy, Arun R
> ; Nikula, Jani
> Subject: Re: [PATCH v7 6/6] drm/i915/panelreplay: Debugfs support for
> panel replay
>
> On Wed, 2023-10-11 at 16:39 +0530, Animesh Manna wrote:
> > Add debugfs support which will print source and sink status per
> > connector basis.
>
> Sorry for late review. Noticed only by now that you have added this patch
> into you set.
Added from v5.
>
> Can you please describe in commit message how you see the output of
> debugfs interface will look like after your changes?
Sure.
>
> >
> > v1: Initial version. [rb-ed by Arun]
> > v2: Added check for DP 2.0 and connector type in
> > connector_debugfs_add().
> >
> > Cc: Jouni Högander
> > Cc: Arun R Murthy
> > Cc: Jani Nikula
> > Signed-off-by: Animesh Manna
> > ---
> > drivers/gpu/drm/i915/display/intel_psr.c | 136 +
> > --
> > 1 file changed, 102 insertions(+), 34 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 80de831c2f60..399fc0a8e636 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -2823,6 +2823,25 @@ static int
> > psr_get_status_and_error_status(struct intel_dp *intel_dp,
> > return 0;
> > }
> >
> > +static int panel_replay_get_status_and_error_status(struct intel_dp
> > *intel_dp,
> > + u8 *status, u8
> > *error_status)
> > +{
> > + struct drm_dp_aux *aux = _dp->aux;
> > + int ret;
> > +
> > + ret = drm_dp_dpcd_readb(aux,
> > DP_SINK_DEVICE_PR_AND_FRAME_LOCK_STATUS, status);
> > + if (ret != 1)
> > + return ret;
> > +
> > + ret = drm_dp_dpcd_readb(aux, DP_PANEL_REPLAY_ERROR_STATUS,
> > error_status);
> > + if (ret != 1)
> > + return ret;
> > +
> > + *status = *status & DP_PSR_SINK_STATE_MASK;
> > +
> > + return 0;
> > +}
> > +
>
> I think you should modify psr_get_status_and_error_status instead of
> duplicating most of it.
DPCD addresses are different for panel replay, I did not get the need of it.
>
> > static void psr_alpm_check(struct intel_dp *intel_dp)
> > {
> > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); @@
> > -3035,7 +3054,7 @@ psr_source_status(struct intel_dp *intel_dp, struct
> > seq_file *m)
> > status = live_status[status_val];
> > }
> >
> > - seq_printf(m, "Source PSR status: %s [0x%08x]\n", status,
> > val);
> > + seq_printf(m, "Source PSR/PanelReplay status: %s [0x%08x]\n",
> > status, val);
> > }
> >
> > static int intel_psr_status(struct seq_file *m, struct intel_dp
> > *intel_dp)
> > @@ -3048,18 +3067,23 @@ static int intel_psr_status(struct seq_file
> > *m, struct intel_dp *intel_dp)
> > bool enabled;
> > u32 val;
> >
> > - seq_printf(m, "Sink support: %s", str_yes_no(psr-
> > >sink_support));
> > - if (psr->sink_support)
> > + seq_printf(m, "Sink support: PSR = %s, Panel Replay = %s",
> > + str_yes_no(psr->sink_support),
> > + str_yes_no(psr->sink_panel_replay_support));
> > +
> > + if (psr->sink_support || psr->sink_panel_replay_support)
> > seq_printf(m, " [0x%02x]", intel_dp->psr_dpcd[0]);
> > seq_puts(m, "\n");
> >
> > - if (!psr->sink_support)
> > + if (!(psr->sink_support || psr->sink_panel_replay_support))
> > return 0;
> >
> > wakeref = intel_runtime_pm_get(_priv->runtime_pm);
> > mutex_lock(>lock);
> >
> > - if (psr->enabled)
> > + if (psr->panel_replay_enabled)
> > + status = "Panel Replay Enabled";
> > + else if (psr->enabled)
> > status = psr->psr2_enabled ? "PSR2 enabled" : "PSR1
> > enabled";
> > else
> > status = "disabled";
> > @@ -3072,14 +3096,17 @@ static int intel_psr_status(struct seq_file
> >
Re: [Intel-gfx] [PATCH v4] drm/i915/dsb: DSB code refactoring
> -Original Message-
> From: Luca Coelho
> Sent: Tuesday, October 31, 2023 3:35 PM
> To: Manna, Animesh ; intel-
> g...@lists.freedesktop.org
> Cc: Nikula, Jani
> Subject: Re: [Intel-gfx] [PATCH v4] drm/i915/dsb: DSB code refactoring
>
> On Tue, 2023-10-31 at 09:15 +, Manna, Animesh wrote:
> >
> > > -Original Message-
> > > From: Luca Coelho
> > > Sent: Tuesday, October 31, 2023 1:14 PM
> > > To: Manna, Animesh ; intel-
> > > g...@lists.freedesktop.org
> > > Cc: Nikula, Jani
> > > Subject: Re: [Intel-gfx] [PATCH v4] drm/i915/dsb: DSB code
> > > refactoring
> > >
> > > On Fri, 2023-10-27 at 17:27 +0530, Animesh Manna wrote:
> > > > Refactor DSB implementation to be compatible with Xe driver.
> > > >
> > > > v1: RFC version.
> > > > v2: Make intel_dsb structure opaque from external usage. [Jani]
> > > > v3: Rebased on latest.
> > > > v4:
> > > > - Add boundary check in dsb_buffer_memset(). [Luca]
> > > > - Use size_t instead of u32. [Luca]
> > > >
> > > > Cc: Jani Nikula
> > > > Signed-off-by: Animesh Manna
> > > > ---
> > >
> > > [...]
> > > > +void intel_dsb_buffer_memset(struct intel_dsb_buffer *dsb_buf,
> > > > +u32 idx, u32 val, size_t size) {
> > > > + if ((idx > dsb_buf->buf_size / 4) || (size > dsb_buf->buf_size -
> > > > +idx
> > > > +* 4))
> > >
> > > You actually don't need the first expression. This expression
> > > should
> > > enough:
> > >
> > > dsb_buf->buf_size <= (idx + size) * sizeof(*dsb_buf->cmd_buf)
> >
> > Here size is in bytes, but idx is index of 32 bytes array. So, the
> > above expression would be,
> >
> > dsb_buf->buf_size <= (idx * sizeof(*dsb_buf->cmd_buf) + size)
>
> Oh, you're right, of course.
>
>
> > The same is done with 2nd expression but agree to use sizeof() instead of
> magic number 4.
> >
> > The first expression is added if idx is big number and due to overflow the
> above check can pass which is not correct. Please let me know your thoughts,
> if you are not ok will drop maybe.
>
> If you're worried about overflow when you're multiplying by 4, then you can
> just do it the opposite way, still with a single expression:
>
> dsb_buf->buf_size / sizeof(*dsb_buf->cmd_buf) <= idx + size /
> sizeof(*dsb_buf->cmd_buf)
>
> Or, taking advantage of the fact that both buf_size and size need to be
> divided by sizeof(), we could something like:
>
> idx > (dsb_buf->buf_size - size) / sizeof(*dsb_buf->cmd_buf)
>
> ...but we're bike-shedding. I don't think the number of expressions or the
> complexity of the expressions matter much here, unless you're really in a
> hotpath, in which case you should add an unlikely() or so.
>
> I'll leave it to you.
>
>
> > >
> > > > + return;
> > >
> > > Blindly returning here doesn't solve the problem, it just hides it.
> > > I think the best would be to use WARN_ON() instead of if.
> > >
> > > So:
> > > WARN_ON(dsb_buf->buf_size <= (idx + size) * sizeof(*dsb_buf-
> > > > cmd_buf));
> >
> > I will add the WARN_ON().
>
> This is the part that I actually think is important. ;)
Thanks for review, have floated v5 after adding the changes.
Regards,
Animesh
>
> --
> Cheers,
> Luca.
Re: [Intel-gfx] [PATCH v4] drm/i915/dsb: DSB code refactoring
> -Original Message-
> From: Luca Coelho
> Sent: Tuesday, October 31, 2023 1:14 PM
> To: Manna, Animesh ; intel-
> g...@lists.freedesktop.org
> Cc: Nikula, Jani
> Subject: Re: [Intel-gfx] [PATCH v4] drm/i915/dsb: DSB code refactoring
>
> On Fri, 2023-10-27 at 17:27 +0530, Animesh Manna wrote:
> > Refactor DSB implementation to be compatible with Xe driver.
> >
> > v1: RFC version.
> > v2: Make intel_dsb structure opaque from external usage. [Jani]
> > v3: Rebased on latest.
> > v4:
> > - Add boundary check in dsb_buffer_memset(). [Luca]
> > - Use size_t instead of u32. [Luca]
> >
> > Cc: Jani Nikula
> > Signed-off-by: Animesh Manna
> > ---
>
> [...]
> > +void intel_dsb_buffer_memset(struct intel_dsb_buffer *dsb_buf, u32
> > +idx, u32 val, size_t size) {
> > + if ((idx > dsb_buf->buf_size / 4) || (size > dsb_buf->buf_size - idx
> > +* 4))
>
> You actually don't need the first expression. This expression should
> enough:
>
> dsb_buf->buf_size <= (idx + size) * sizeof(*dsb_buf->cmd_buf)
Here size is in bytes, but idx is index of 32 bytes array. So, the above
expression would be,
dsb_buf->buf_size <= (idx * sizeof(*dsb_buf->cmd_buf) + size)
The same is done with 2nd expression but agree to use sizeof() instead of magic
number 4.
The first expression is added if idx is big number and due to overflow the
above check can pass which is not correct. Please let me know your thoughts, if
you are not ok will drop maybe.
>
> > + return;
>
> Blindly returning here doesn't solve the problem, it just hides it. I think
> the
> best would be to use WARN_ON() instead of if.
>
> So:
> WARN_ON(dsb_buf->buf_size <= (idx + size) * sizeof(*dsb_buf-
> >cmd_buf));
I will add the WARN_ON().
Regards,
Animesh
>
> > +
> > + memset(_buf->cmd_buf[idx], val, size); }
> [...]
>
> --
> Cheers,
> Luca.
Re: [Intel-gfx] [PATCH v3] drm/i915/dsb: DSB code refactoring
> -Original Message-
> From: Ville Syrjälä
> Sent: Friday, October 27, 2023 6:51 PM
> To: Manna, Animesh
> Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani
> Subject: Re: [Intel-gfx] [PATCH v3] drm/i915/dsb: DSB code refactoring
>
> On Fri, Oct 27, 2023 at 05:59:45AM +, Manna, Animesh wrote:
> >
> >
> > > -Original Message-
> > > From: Ville Syrjälä
> > > Sent: Thursday, October 26, 2023 8:03 PM
> > > To: Manna, Animesh
> > > Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani
> > >
> > > Subject: Re: [Intel-gfx] [PATCH v3] drm/i915/dsb: DSB code
> > > refactoring
> > >
> > > On Sun, Oct 08, 2023 at 03:42:06PM +0530, Animesh Manna wrote:
> > > > Refactor DSB implementation to be compatible with Xe driver.
> > > >
> > > > v1: RFC version.
> > > > v2: Make intel_dsb structure opaque from external usage. [Jani]
> > > > v3: Rebased on latest.
> > > >
> > > > Cc: Jani Nikula
> > > > Signed-off-by: Animesh Manna
> > > > ---
> > > > drivers/gpu/drm/i915/Makefile | 1 +
> > > > drivers/gpu/drm/i915/display/intel_dsb.c | 84 ---
> > > > .../gpu/drm/i915/display/intel_dsb_buffer.c | 64 ++
> > > > .../gpu/drm/i915/display/intel_dsb_buffer.h | 26 ++
> > > > 4 files changed, 126 insertions(+), 49 deletions(-) create mode
> > > > 100644 drivers/gpu/drm/i915/display/intel_dsb_buffer.c
> > > > create mode 100644
> > > > drivers/gpu/drm/i915/display/intel_dsb_buffer.h
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/Makefile
> > > > b/drivers/gpu/drm/i915/Makefile index dec78efa452a..7c3f91c2375a
> > > > 100644
> > > > --- a/drivers/gpu/drm/i915/Makefile
> > > > +++ b/drivers/gpu/drm/i915/Makefile
> > > > @@ -260,6 +260,7 @@ i915-y += \
> > > > display/intel_dpt.o \
> > > > display/intel_drrs.o \
> > > > display/intel_dsb.o \
> > > > + display/intel_dsb_buffer.o \
> > > > display/intel_fb.o \
> > > > display/intel_fb_pin.o \
> > > > display/intel_fbc.o \
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
> > > > b/drivers/gpu/drm/i915/display/intel_dsb.c
> > > > index 3e32aa49b8eb..ec89d968a873 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> > > > @@ -13,12 +13,13 @@
> > > > #include "intel_de.h"
> > > > #include "intel_display_types.h"
> > > > #include "intel_dsb.h"
> > > > +#include "intel_dsb_buffer.h"
> > > > #include "intel_dsb_regs.h"
> > > > #include "intel_vblank.h"
> > > > #include "intel_vrr.h"
> > > > #include "skl_watermark.h"
> > > >
> > > > -struct i915_vma;
> > > > +#define CACHELINE_BYTES 64
> > > >
> > > > enum dsb_id {
> > > > INVALID_DSB = -1,
> > > > @@ -31,8 +32,7 @@ enum dsb_id {
> > > > struct intel_dsb {
> > > > enum dsb_id id;
> > > >
> > > > - u32 *cmd_buf;
> > > > - struct i915_vma *vma;
> > > > + struct intel_dsb_buffer dsb_buf;
> > > > struct intel_crtc *crtc;
> > > >
> > > > /*
> > > > @@ -108,15 +108,17 @@ static void intel_dsb_dump(struct intel_dsb
> > > > *dsb) {
> > > > struct intel_crtc *crtc = dsb->crtc;
> > > > struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> > > > - const u32 *buf = dsb->cmd_buf;
> > > > int i;
> > > >
> > > > drm_dbg_kms(>drm, "[CRTC:%d:%s] DSB %d commands {\n",
> > > > crtc->base.base.id, crtc->base.name, dsb->id);
> > > > for (i = 0; i < ALIGN(dsb->free_pos, 64 / 4); i += 4)
> > > > drm_dbg_kms(>drm,
> > > > - " 0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
> > > > - i * 4, buf[i], buf[i+1], buf[i+2],
> > > > buf[i+3]);
> > > > + "
Re: [Intel-gfx] [PATCH v3] drm/i915/dsb: DSB code refactoring
> -Original Message-
> From: Luca Coelho
> Sent: Friday, October 27, 2023 12:19 PM
> To: Manna, Animesh ; intel-
> g...@lists.freedesktop.org
> Cc: Nikula, Jani
> Subject: Re: [Intel-gfx] [PATCH v3] drm/i915/dsb: DSB code refactoring
>
> On Thu, 2023-10-26 at 14:23 +, Manna, Animesh wrote:
> >
> > > -Original Message-
> > > From: Luca Coelho
> > > Sent: Thursday, October 26, 2023 1:08 PM
> > > To: Manna, Animesh ; intel-
> > > g...@lists.freedesktop.org
> > > Cc: Nikula, Jani
> > > Subject: Re: [Intel-gfx] [PATCH v3] drm/i915/dsb: DSB code
> > > refactoring
> > >
> > > On Sun, 2023-10-08 at 15:42 +0530, Animesh Manna wrote:
> > > > Refactor DSB implementation to be compatible with Xe driver.
> > > >
> > > > v1: RFC version.
> > > > v2: Make intel_dsb structure opaque from external usage. [Jani]
> > > > v3: Rebased on latest.
> > > >
> > > > Cc: Jani Nikula
> > > > Signed-off-by: Animesh Manna
> > > > ---
> > >
> > > Looks great overall! Just a couple of small comments below.
> >
> > Thanks for review.
> >
> > >
> > >
> > > [...]
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
> > > > b/drivers/gpu/drm/i915/display/intel_dsb.c
> > > > index 3e32aa49b8eb..ec89d968a873 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> > > > @@ -13,12 +13,13 @@
> > > > #include "intel_de.h"
> > > > #include "intel_display_types.h"
> > > > #include "intel_dsb.h"
> > > > +#include "intel_dsb_buffer.h"
> > > > #include "intel_dsb_regs.h"
> > > > #include "intel_vblank.h"
> > > > #include "intel_vrr.h"
> > > > #include "skl_watermark.h"
> > > >
> > > > -struct i915_vma;
> > > > +#define CACHELINE_BYTES 64
> > >
> > > I see that this macro is defined in GT and you want to avoid
> > > depending on the definition from GT, but you don't make any other
> > > changes related to the cacheline size here, so maybe this change
> > > should be a separate patch? Also, it looks a bit magic without an
> > > explanation on where the number is coming from.
> >
> > For Xe driver macro definition in GT may not accessible, so have redefined
> in Intel_dsb.c itself. It's related to dsb so kept in the same patch.
> > DSB command buffer is cacheline aligned. DSB support added from gen12
> and size of cacheline size will be 64 bytes. As per bspec each cacheline can
> have 8 dsb-instructions and 64 bits per instruction.
>
> Okay, even though this is clearly related to DSB only, I still don't think it
> should be in the same patch. In any case, I'm not going to block on this.
>
>
> > > [...]
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_dsb_buffer.c
> > > > b/drivers/gpu/drm/i915/display/intel_dsb_buffer.c
> > > > new file mode 100644
> > > > index ..723937591831
> > > > --- /dev/null
> > > > +++ b/drivers/gpu/drm/i915/display/intel_dsb_buffer.c
> > > > @@ -0,0 +1,64 @@
> > > > +// SPDX-License-Identifier: MIT
> > > > +/*
> > > > + * Copyright 2023, Intel Corporation.
> > > > + */
> > > > +
> > > > +#include "gem/i915_gem_internal.h"
> > > > +#include "i915_drv.h"
> > > > +#include "i915_vma.h"
> > > > +#include "intel_display_types.h"
> > > > +#include "intel_dsb_buffer.h"
> > > > +
> > > > +u32 intel_dsb_buffer_ggtt_offset(struct intel_dsb_buffer *dsb_buf) {
> > > > + return i915_ggtt_offset(dsb_buf->vma); }
> > > > +
> > > > +void intel_dsb_buffer_write(struct intel_dsb_buffer *dsb_buf, u32
> > > > +idx, u32 val) {
> > > > + dsb_buf->cmd_buf[idx] = val;
> > > > +}
> > > > +
> > > > +u32 intel_dsb_buffer_read(struct intel_dsb_buffer *dsb_buf, u32
> > > > +idx) {
> > > > + return dsb_buf->cmd_buf[idx];
> > > > +}
> > > > +
> > > > +void intel_dsb_buffer_memset(struct intel_dsb_buffer *dsb_buf,
> > > > +u32 idx, u32 val, u32 sz) {
> > > > + memset(_buf->cm
Re: [Intel-gfx] [PATCH v3] drm/i915/dsb: DSB code refactoring
> -Original Message-
> From: Ville Syrjälä
> Sent: Thursday, October 26, 2023 8:03 PM
> To: Manna, Animesh
> Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani
> Subject: Re: [Intel-gfx] [PATCH v3] drm/i915/dsb: DSB code refactoring
>
> On Sun, Oct 08, 2023 at 03:42:06PM +0530, Animesh Manna wrote:
> > Refactor DSB implementation to be compatible with Xe driver.
> >
> > v1: RFC version.
> > v2: Make intel_dsb structure opaque from external usage. [Jani]
> > v3: Rebased on latest.
> >
> > Cc: Jani Nikula
> > Signed-off-by: Animesh Manna
> > ---
> > drivers/gpu/drm/i915/Makefile | 1 +
> > drivers/gpu/drm/i915/display/intel_dsb.c | 84 ---
> > .../gpu/drm/i915/display/intel_dsb_buffer.c | 64 ++
> > .../gpu/drm/i915/display/intel_dsb_buffer.h | 26 ++
> > 4 files changed, 126 insertions(+), 49 deletions(-) create mode
> > 100644 drivers/gpu/drm/i915/display/intel_dsb_buffer.c
> > create mode 100644 drivers/gpu/drm/i915/display/intel_dsb_buffer.h
> >
> > diff --git a/drivers/gpu/drm/i915/Makefile
> > b/drivers/gpu/drm/i915/Makefile index dec78efa452a..7c3f91c2375a
> > 100644
> > --- a/drivers/gpu/drm/i915/Makefile
> > +++ b/drivers/gpu/drm/i915/Makefile
> > @@ -260,6 +260,7 @@ i915-y += \
> > display/intel_dpt.o \
> > display/intel_drrs.o \
> > display/intel_dsb.o \
> > + display/intel_dsb_buffer.o \
> > display/intel_fb.o \
> > display/intel_fb_pin.o \
> > display/intel_fbc.o \
> > diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
> > b/drivers/gpu/drm/i915/display/intel_dsb.c
> > index 3e32aa49b8eb..ec89d968a873 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> > @@ -13,12 +13,13 @@
> > #include "intel_de.h"
> > #include "intel_display_types.h"
> > #include "intel_dsb.h"
> > +#include "intel_dsb_buffer.h"
> > #include "intel_dsb_regs.h"
> > #include "intel_vblank.h"
> > #include "intel_vrr.h"
> > #include "skl_watermark.h"
> >
> > -struct i915_vma;
> > +#define CACHELINE_BYTES 64
> >
> > enum dsb_id {
> > INVALID_DSB = -1,
> > @@ -31,8 +32,7 @@ enum dsb_id {
> > struct intel_dsb {
> > enum dsb_id id;
> >
> > - u32 *cmd_buf;
> > - struct i915_vma *vma;
> > + struct intel_dsb_buffer dsb_buf;
> > struct intel_crtc *crtc;
> >
> > /*
> > @@ -108,15 +108,17 @@ static void intel_dsb_dump(struct intel_dsb
> > *dsb) {
> > struct intel_crtc *crtc = dsb->crtc;
> > struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> > - const u32 *buf = dsb->cmd_buf;
> > int i;
> >
> > drm_dbg_kms(>drm, "[CRTC:%d:%s] DSB %d commands {\n",
> > crtc->base.base.id, crtc->base.name, dsb->id);
> > for (i = 0; i < ALIGN(dsb->free_pos, 64 / 4); i += 4)
> > drm_dbg_kms(>drm,
> > - " 0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
> > - i * 4, buf[i], buf[i+1], buf[i+2], buf[i+3]);
> > + " 0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", i * 4,
> > + intel_dsb_buffer_read(>dsb_buf, i),
> > + intel_dsb_buffer_read(>dsb_buf, i + 1),
> > + intel_dsb_buffer_read(>dsb_buf, i + 2),
> > + intel_dsb_buffer_read(>dsb_buf, i + 3));
> > drm_dbg_kms(>drm, "}\n");
> > }
> >
> > @@ -128,8 +130,6 @@ static bool is_dsb_busy(struct drm_i915_private
> > *i915, enum pipe pipe,
> >
> > static void intel_dsb_emit(struct intel_dsb *dsb, u32 ldw, u32 udw)
> > {
> > - u32 *buf = dsb->cmd_buf;
> > -
> > if (!assert_dsb_has_room(dsb))
> > return;
> >
> > @@ -138,14 +138,13 @@ static void intel_dsb_emit(struct intel_dsb
> > *dsb, u32 ldw, u32 udw)
> >
> > dsb->ins_start_offset = dsb->free_pos;
> >
> > - buf[dsb->free_pos++] = ldw;
> > - buf[dsb->free_pos++] = udw;
> > + intel_dsb_buffer_write(>dsb_buf, dsb->free_pos++, ldw);
> > + intel_dsb_buffer_write(>dsb_buf, dsb->free_pos++, udw);
> > }
> >
> > static bool intel_dsb_prev_ins_is_write(struct intel_dsb *dsb,
> > u32
Re: [Intel-gfx] [PATCH v3] drm/i915/dsb: DSB code refactoring
> -Original Message-
> From: Luca Coelho
> Sent: Thursday, October 26, 2023 1:08 PM
> To: Manna, Animesh ; intel-
> g...@lists.freedesktop.org
> Cc: Nikula, Jani
> Subject: Re: [Intel-gfx] [PATCH v3] drm/i915/dsb: DSB code refactoring
>
> On Sun, 2023-10-08 at 15:42 +0530, Animesh Manna wrote:
> > Refactor DSB implementation to be compatible with Xe driver.
> >
> > v1: RFC version.
> > v2: Make intel_dsb structure opaque from external usage. [Jani]
> > v3: Rebased on latest.
> >
> > Cc: Jani Nikula
> > Signed-off-by: Animesh Manna
> > ---
>
> Looks great overall! Just a couple of small comments below.
Thanks for review.
>
>
> [...]
> > diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
> > b/drivers/gpu/drm/i915/display/intel_dsb.c
> > index 3e32aa49b8eb..ec89d968a873 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> > @@ -13,12 +13,13 @@
> > #include "intel_de.h"
> > #include "intel_display_types.h"
> > #include "intel_dsb.h"
> > +#include "intel_dsb_buffer.h"
> > #include "intel_dsb_regs.h"
> > #include "intel_vblank.h"
> > #include "intel_vrr.h"
> > #include "skl_watermark.h"
> >
> > -struct i915_vma;
> > +#define CACHELINE_BYTES 64
>
> I see that this macro is defined in GT and you want to avoid depending on
> the definition from GT, but you don't make any other changes related to the
> cacheline size here, so maybe this change should be a separate patch? Also,
> it looks a bit magic without an explanation on where the number is coming
> from.
For Xe driver macro definition in GT may not accessible, so have redefined in
Intel_dsb.c itself. It's related to dsb so kept in the same patch.
DSB command buffer is cacheline aligned. DSB support added from gen12 and size
of cacheline size will be 64 bytes. As per bspec each cacheline can have 8
dsb-instructions and 64 bits per instruction.
>
>
> [...]
> > diff --git a/drivers/gpu/drm/i915/display/intel_dsb_buffer.c
> > b/drivers/gpu/drm/i915/display/intel_dsb_buffer.c
> > new file mode 100644
> > index ..723937591831
> > --- /dev/null
> > +++ b/drivers/gpu/drm/i915/display/intel_dsb_buffer.c
> > @@ -0,0 +1,64 @@
> > +// SPDX-License-Identifier: MIT
> > +/*
> > + * Copyright 2023, Intel Corporation.
> > + */
> > +
> > +#include "gem/i915_gem_internal.h"
> > +#include "i915_drv.h"
> > +#include "i915_vma.h"
> > +#include "intel_display_types.h"
> > +#include "intel_dsb_buffer.h"
> > +
> > +u32 intel_dsb_buffer_ggtt_offset(struct intel_dsb_buffer *dsb_buf) {
> > + return i915_ggtt_offset(dsb_buf->vma); }
> > +
> > +void intel_dsb_buffer_write(struct intel_dsb_buffer *dsb_buf, u32
> > +idx, u32 val) {
> > + dsb_buf->cmd_buf[idx] = val;
> > +}
> > +
> > +u32 intel_dsb_buffer_read(struct intel_dsb_buffer *dsb_buf, u32 idx)
> > +{
> > + return dsb_buf->cmd_buf[idx];
> > +}
> > +
> > +void intel_dsb_buffer_memset(struct intel_dsb_buffer *dsb_buf, u32
> > +idx, u32 val, u32 sz) {
> > + memset(_buf->cmd_buf[idx], val, sz);
>
> I think you should check the array boundaries here, to be sure.
> Probably a good idea to do with the other functions as well, but I think this
> is
> the most critical and easiest to make mistakes with.
assert_dsb_has_room() function is taking care for not crossing the boundaries.
Here will check from the allocated buffer-size versus used/unused buffer.
Specifically intel_dsb_buffer_memset() is called from intel_dsb_align_tail()
where zero get set for unused cacheline space. No chance to cross the
boundaries in this case.
Please let me know for any further info.
Regards,
Animesh
>
> --
> Cheers,
> Luca.
Re: [Intel-gfx] [PATCH v7 4/6] drm/i915/panelreplay: Enable panel replay dpcd initialization for DP
> -Original Message- > From: Murthy, Arun R > Sent: Monday, October 16, 2023 9:56 AM > To: Manna, Animesh ; intel- > g...@lists.freedesktop.org > Cc: dri-de...@lists.freedesktop.org; Hogander, Jouni > ; Nikula, Jani > Subject: RE: [PATCH v7 4/6] drm/i915/panelreplay: Enable panel replay dpcd > initialization for DP > > > > -----Original Message- > > From: Manna, Animesh > > Sent: Wednesday, October 11, 2023 4:40 PM > > To: intel-gfx@lists.freedesktop.org > > Cc: dri-de...@lists.freedesktop.org; Manna, Animesh > > ; Hogander, Jouni > ; > > Murthy, Arun R ; Nikula, Jani > > > > Subject: [PATCH v7 4/6] drm/i915/panelreplay: Enable panel replay dpcd > > initialization for DP > > > > Due to similarity panel replay dpcd initialization got added in psr > > function which is specific for edp panel. This patch enables panel > > replay initialization for dp connector. > > > If panelreplay initialization then why is the function name psr_init_dpcd() ? > Also it its similar to PSR then these dpcd should already be available. Hi Arun, The first call for intel_psr_init_dpcd() get called from intel_edp_init_dpcd() which is not reachable for DP. So, in this patch need to add intel_psr_init_dpcd() for DP(non-edp) in intel_psr_init(). Panel replay initialization added in intel_psr_init() as per previous feedback just to align panel-replay with psr framework. Regards, Animesh > > Thanks and Regards, > Arun R Murthy > > > > Cc: Jouni Högander > > Cc: Arun R Murthy > > Cc: Jani Nikula > > Signed-off-by: Animesh Manna > > --- > > drivers/gpu/drm/i915/display/intel_psr.c | 3 +++ > > 1 file changed, 3 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > > b/drivers/gpu/drm/i915/display/intel_psr.c > > index f9837001aa5f..a2e0637c53fb 100644 > > --- a/drivers/gpu/drm/i915/display/intel_psr.c > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > > @@ -2738,6 +2738,9 @@ void intel_psr_init(struct intel_dp *intel_dp) > > if (!(HAS_PSR(dev_priv) || HAS_DP20(dev_priv))) > > return; > > > > + if (!intel_dp_is_edp(intel_dp)) > > + intel_psr_init_dpcd(intel_dp); > > + > > /* > > * HSW spec explicitly says PSR is tied to port A. > > * BDW+ platforms have a instance of PSR registers per transcoder > > but > > -- > > 2.29.0
