[Intel-gfx] [PATCH] drm/i915: do not set redundant DP dpms mode
Add a check to intel_dp_dpms() to skip setting the DP's DPMS mode if
the current mode is the same as the new one.
Signed-off-by: Simon Que
---
drivers/gpu/drm/i915/intel_dp.c |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index c71e0f0..ba86b4f 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1311,8 +1311,13 @@ intel_dp_dpms(struct drm_encoder *encoder, int mode)
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
struct drm_device *dev = encoder->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_connector *connector;
uint32_t dp_reg = I915_READ(intel_dp->output_reg);
+ list_for_each_entry(connector, &dev->mode_config.connector_list, head)
+ if (connector->encoder == encoder && connector->dpms == mode)
+ return;
+
if (mode != DRM_MODE_DPMS_ON) {
ironlake_edp_backlight_off(intel_dp);
ironlake_edp_panel_off(intel_dp);
--
1.7.8.6
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[Intel-gfx] [PATCH] xf86-video-intel: change order of DPMS operations
The operations when setting dpms on should be in the order opposite
of what's done when setting dpms off.
This is because of potentially conflicting effects:
~ drmModeConnectoSetProperty() enables/disables the backlight driver.
Some backlight drivers such as intel_backlight set the backlight to 0
when disabled and to max when enabled.
~ intel_output_dpms_backlight() saves the backlight value when turning
DPMS off and restores it when turning DPMS on.
Here's the current order of operations:
xset dpms force off (backlight is nonzero)
drmModeConnectoSetProperty(DPMSModeOff)
kernel: disable backlight, backlight=0
intel_output_dpms_backlight(DPMSModeOff)
save backlight value (0) <-- it has been set to 0 by kernel
set backlight to 0
xset dpms force on
drmModeConnectoSetProperty(DPMSModeOn)
kernel: enable backlight, backlight=max
intel_output_dpms_backlight(DPMSModeOn)
set backlight to saved value (0)
The correct way to do this would be to reverse the operations during
xset dpms force off:
intel_output_dpms_backlight(DPMSModeOff)
save backlight value (nonzero)
set backlight to 0
drmModeConnectoSetProperty(DPMSModeOff)
kernel: enable backlight, backlight=0
This restores the saved nonzero backlight value during the force on.
Signed-off-by: Simon Que
---
src/intel_display.c | 12 +---
1 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/src/intel_display.c b/src/intel_display.c
index 2183f4d..2a989d1 100644
--- a/src/intel_display.c
+++ b/src/intel_display.c
@@ -944,13 +944,19 @@ intel_output_dpms(xf86OutputPtr output, int dpms)
continue;
if (!strcmp(props->name, "DPMS")) {
+ /* Make sure to reverse the order between on and off. */
+ if (dpms == DPMSModeOff)
+ intel_output_dpms_backlight(output,
+
intel_output->dpms_mode,
+ dpms);
drmModeConnectorSetProperty(mode->fd,
intel_output->output_id,
props->prop_id,
dpms);
- intel_output_dpms_backlight(output,
- intel_output->dpms_mode,
- dpms);
+ if (dpms != DPMSModeOff)
+ intel_output_dpms_backlight(output,
+
intel_output->dpms_mode,
+ dpms);
intel_output->dpms_mode = dpms;
drmModeFreeProperty(props);
return;
--
1.7.3.1
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[Intel-gfx] [PATCH v4] drivers: i915: Default backlight PWM frequency
If the firmware did not initialize the backlight PWM registers, set up a
default PWM frequency of 200 Hz. This is determined using the following
formula:
freq = refclk / (128 * pwm_max)
The PWM register allows the max PWM value to be set. So we want to use
the formula, where freq = 200:
pwm_max = refclk / (128 * freq)
This patch will, in the case of missing PWM register initialization
values, look for the reference clock frequency. Based on that, it sets
an appropriate max PWM value for a frequency of 200 Hz.
If no refclk frequency is found, the max PWM will be zero, which results
in no change to the PWM registers.
Signed-off-by: Simon Que
---
drivers/gpu/drm/i915/intel_panel.c | 38 ++-
1 files changed, 32 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_panel.c
b/drivers/gpu/drm/i915/intel_panel.c
index f15388c..dda5de2 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -32,6 +32,12 @@
#define PCI_LBPC 0xf4 /* legacy/combination backlight modes */
+/* These are used to calculate a reasonable default when firmware has not
+ * configured a maximum PWM frequency, with 200Hz as the current default
target.
+ */
+#define DEFAULT_BACKLIGHT_PWM_FREQ 200
+#define BACKLIGHT_REFCLK_DIVISOR 128
+
void
intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
struct drm_display_mode *adjusted_mode)
@@ -129,12 +135,32 @@ static int is_backlight_combination_mode(struct
drm_device *dev)
return 0;
}
+static void i915_set_default_max_backlight(struct drm_i915_private *dev_priv)
+{
+ u32 refclk_freq_mhz = 0;
+ u32 max_pwm;
+
+ if (HAS_PCH_SPLIT(dev_priv->dev))
+ refclk_freq_mhz = I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
+ else if (dev_priv->lvds_use_ssc)
+ refclk_freq_mhz = dev_priv->lvds_ssc_freq;
+
+ max_pwm = refclk_freq_mhz * 100 /
+ (BACKLIGHT_REFCLK_DIVISOR * DEFAULT_BACKLIGHT_PWM_FREQ);
+
+ if (HAS_PCH_SPLIT(dev_priv->dev))
+ dev_priv->saveBLC_PWM_CTL2 = max_pwm << 16;
+ else if (IS_PINEVIEW(dev_priv->dev))
+ dev_priv->saveBLC_PWM_CTL = max_pwm << 17;
+ else
+ dev_priv->saveBLC_PWM_CTL = max_pwm << 16;
+}
+
static u32 i915_read_blc_pwm_ctl(struct drm_i915_private *dev_priv)
{
u32 val;
- /* Restore the CTL value if it lost, e.g. GPU reset */
-
+ /* Restore the CTL value if it was lost, e.g. GPU reset */
if (HAS_PCH_SPLIT(dev_priv->dev)) {
val = I915_READ(BLC_PWM_PCH_CTL2);
if (dev_priv->saveBLC_PWM_CTL2 == 0) {
@@ -168,11 +194,11 @@ u32 intel_panel_get_max_backlight(struct drm_device *dev)
max = i915_read_blc_pwm_ctl(dev_priv);
if (max == 0) {
- /* XXX add code here to query mode clock or hardware clock
-* and program max PWM appropriately.
+ /* If backlight PWM registers have not been set, set them to
+* default backlight PWM settings.
*/
- printk_once(KERN_WARNING "fixme: max PWM is zero.\n");
- return 1;
+ i915_set_default_max_backlight(dev_priv);
+ max = i915_read_blc_pwm_ctl(dev_priv);
}
if (HAS_PCH_SPLIT(dev)) {
--
1.7.2.3
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[Intel-gfx] [PATCH v3] drivers: i915: Default backlight PWM frequency
If the firmware did not initialize the backlight PWM registers, set up a
default PWM frequency of 200 Hz. This is determined using the following
formula:
freq = refclk / (128 * pwm_max)
The PWM register allows the max PWM value to be set. So we want to use
the formula, where freq = 200:
pwm_max = refclk / (128 * freq)
This patch will, in the case of missing PWM register initialization
values, look for the reference clock frequency. Based on that, it sets
an appropriate max PWM value for a frequency of 200 Hz.
If no refclk frequency is found, the max PWM will be zero, which results
in no change to the PWM registers.
Signed-off-by: Simon Que
To: intel-gfx@lists.freedesktop.org
To: Jesse Barnes
To: Chris Wilson
To: Eric Anholt
To: Matthew Garrett
Cc: Olof Johansson
Cc: Bryan Freed
Cc: Sameer Nanda
---
drivers/gpu/drm/i915/intel_panel.c | 36 ++--
1 files changed, 30 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_panel.c
b/drivers/gpu/drm/i915/intel_panel.c
index f15388c..98439b3 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -32,6 +32,10 @@
#define PCI_LBPC 0xf4 /* legacy/combination backlight modes */
+/* For computing default PWM settings */
+#define DEFAULT_BACKLIGHT_PWM_FREQ 200
+#define BACKLIGHT_REFCLK_DIVISOR 128
+
void
intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
struct drm_display_mode *adjusted_mode)
@@ -129,12 +133,32 @@ static int is_backlight_combination_mode(struct
drm_device *dev)
return 0;
}
+static void i915_set_default_max_backlight(struct drm_i915_private *dev_priv)
+{
+ u32 refclk_freq_mhz = 0;
+ u32 max_pwm;
+
+ if (HAS_PCH_SPLIT(dev_priv->dev))
+ refclk_freq_mhz = I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
+ else if (dev_priv->lvds_use_ssc)
+ refclk_freq_mhz = dev_priv->lvds_ssc_freq;
+
+ max_pwm = refclk_freq_mhz * 100 /
+ (BACKLIGHT_REFCLK_DIVISOR * DEFAULT_BACKLIGHT_PWM_FREQ);
+
+ if (HAS_PCH_SPLIT(dev_priv->dev))
+ dev_priv->saveBLC_PWM_CTL2 = max_pwm << 16;
+ else if (IS_PINEVIEW(dev_priv->dev))
+ dev_priv->saveBLC_PWM_CTL = max_pwm << 17;
+ else
+ dev_priv->saveBLC_PWM_CTL = max_pwm << 16;
+}
+
static u32 i915_read_blc_pwm_ctl(struct drm_i915_private *dev_priv)
{
u32 val;
- /* Restore the CTL value if it lost, e.g. GPU reset */
-
+ /* Restore the CTL value if it was lost, e.g. GPU reset */
if (HAS_PCH_SPLIT(dev_priv->dev)) {
val = I915_READ(BLC_PWM_PCH_CTL2);
if (dev_priv->saveBLC_PWM_CTL2 == 0) {
@@ -168,11 +192,11 @@ u32 intel_panel_get_max_backlight(struct drm_device *dev)
max = i915_read_blc_pwm_ctl(dev_priv);
if (max == 0) {
- /* XXX add code here to query mode clock or hardware clock
-* and program max PWM appropriately.
+ /* If backlight PWM registers have not been set, set them to
+* default backlight PWM settings.
*/
- printk_once(KERN_WARNING "fixme: max PWM is zero.\n");
- return 1;
+ i915_set_default_max_backlight(dev_priv);
+ max = i915_read_blc_pwm_ctl(dev_priv);
}
if (HAS_PCH_SPLIT(dev)) {
--
1.7.2.3
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[Intel-gfx] [PATCH v2] drivers: i915: Default backlight PWM frequency
If the firmware did not initialize the backlight PWM registers, set up a
default PWM frequency of 200 Hz. This is determined using the following
formula:
freq = refclk / (128 * pwm_max)
The PWM register allows the max PWM value to be set. So we want to use
the formula, where freq = 200:
pwm_max = refclk / (128 * freq)
This patch will, in the case of missing PWM register initialization
values, look for the reference clock frequency. Based on that, it sets
an appropriate max PWM value for a frequency of 200 Hz.
If no refclk frequency is found, the max PWM will be zero, which results
in no change to the PWM registers.
Signed-off-by: Simon Que
---
drivers/gpu/drm/i915/i915_reg.h|1 +
drivers/gpu/drm/i915/intel_panel.c | 37 +--
2 files changed, 31 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5d5def7..a832028 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3275,6 +3275,7 @@
#define PWM_POLARITY_ACTIVE_HIGH2 (0 << 28)
#define BLC_PWM_PCH_CTL2 0xc8254
+#define BLC_PWM_PCH_FREQ_SHIFT 16
#define PCH_PP_STATUS 0xc7200
#define PCH_PP_CONTROL 0xc7204
diff --git a/drivers/gpu/drm/i915/intel_panel.c
b/drivers/gpu/drm/i915/intel_panel.c
index f15388c..f865e52 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -32,6 +32,10 @@
#define PCI_LBPC 0xf4 /* legacy/combination backlight modes */
+/* For computing default PWM settings */
+#define DEFAULT_BACKLIGHT_PWM_FREQ 200
+#define BACKLIGHT_REFCLK_DIVISOR 128
+
void
intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
struct drm_display_mode *adjusted_mode)
@@ -129,12 +133,31 @@ static int is_backlight_combination_mode(struct
drm_device *dev)
return 0;
}
+static u32 i915_get_default_max_backlight(struct drm_i915_private *dev_priv)
+{
+ u32 refclk_freq_mhz = 0;
+ u32 max_pwm = 0;
+ if (HAS_PCH_SPLIT(dev_priv->dev))
+ refclk_freq_mhz = I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
+ else if (dev_priv->lvds_use_ssc)
+ refclk_freq_mhz = dev_priv->lvds_ssc_freq;
+
+ max_pwm = refclk_freq_mhz * 100 /
+ (BACKLIGHT_REFCLK_DIVISOR * DEFAULT_BACKLIGHT_PWM_FREQ);
+
+ if (HAS_PCH_SPLIT(dev_priv->dev))
+ dev_priv->saveBLC_PWM_CTL2 = max_pwm << BLC_PWM_PCH_FREQ_SHIFT;
+ else
+ dev_priv->saveBLC_PWM_CTL = max_pwm <<
+ BACKLIGHT_MODULATION_FREQ_SHIFT;
+ return max_pwm;
+}
+
static u32 i915_read_blc_pwm_ctl(struct drm_i915_private *dev_priv)
{
u32 val;
- /* Restore the CTL value if it lost, e.g. GPU reset */
-
+ /* Restore the CTL value if it was lost, e.g. GPU reset */
if (HAS_PCH_SPLIT(dev_priv->dev)) {
val = I915_READ(BLC_PWM_PCH_CTL2);
if (dev_priv->saveBLC_PWM_CTL2 == 0) {
@@ -168,11 +191,11 @@ u32 intel_panel_get_max_backlight(struct drm_device *dev)
max = i915_read_blc_pwm_ctl(dev_priv);
if (max == 0) {
- /* XXX add code here to query mode clock or hardware clock
-* and program max PWM appropriately.
-*/
- printk_once(KERN_WARNING "fixme: max PWM is zero.\n");
- return 1;
+ /* If backlight PWM registers have not been set, set them to */
+ /* default backlight PWM settings. */
+ max = i915_get_default_max_backlight(dev_priv);
+ i915_read_blc_pwm_ctl(dev_priv);
+ return max;
}
if (HAS_PCH_SPLIT(dev)) {
--
1.7.2.3
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[Intel-gfx] [PATCH 2/2] drivers: i915: Default backlight PWM frequency
If the firmware did not initialize the backlight PWM registers, set up a
default PWM frequency of 200 Hz. This is determined using the following
formula:
freq = refclk / (128 * pwm_max)
The PWM register allows the max PWM value to be set. So we want to use
the formula, where freq = 200:
pwm_max = refclk / (128 * freq)
This patch will, in the case of missing PWM register initialization
values, look for the reference clock frequency. Based on that, it sets
an appropriate max PWM value for a frequency of 200 Hz.
If no refclk frequency is found, the max PWM will be zero, which results
in no change to the PWM registers.
Signed-off-by: Simon Que
---
drivers/gpu/drm/i915/i915_reg.h|1 +
drivers/gpu/drm/i915/intel_panel.c | 32 +---
2 files changed, 30 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5d5def7..a832028 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3275,6 +3275,7 @@
#define PWM_POLARITY_ACTIVE_HIGH2 (0 << 28)
#define BLC_PWM_PCH_CTL2 0xc8254
+#define BLC_PWM_PCH_FREQ_SHIFT 16
#define PCH_PP_STATUS 0xc7200
#define PCH_PP_CONTROL 0xc7204
diff --git a/drivers/gpu/drm/i915/intel_panel.c
b/drivers/gpu/drm/i915/intel_panel.c
index f15388c..4bf2bde 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -32,6 +32,10 @@
#define PCI_LBPC 0xf4 /* legacy/combination backlight modes */
+/* For computing default PWM settings */
+#define DEFAULT_BACKLIGHT_PWM_FREQ 200
+#define BACKLIGHT_REFCLK_DIVISOR 128
+
void
intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
struct drm_display_mode *adjusted_mode)
@@ -129,14 +133,32 @@ static int is_backlight_combination_mode(struct
drm_device *dev)
return 0;
}
+static u32 i915_get_default_max_backlight(struct drm_i915_private *dev_priv)
+{
+ u32 refclk_freq_mhz = 0;
+ if (HAS_PCH_SPLIT(dev_priv->dev))
+ refclk_freq_mhz = I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
+ else if (dev_priv->lvds_use_ssc)
+ refclk_freq_mhz = dev_priv->lvds_ssc_freq;
+
+ return refclk_freq_mhz * 100 /
+ (BACKLIGHT_REFCLK_DIVISOR * DEFAULT_BACKLIGHT_PWM_FREQ);
+}
+
static u32 i915_read_blc_pwm_ctl(struct drm_i915_private *dev_priv)
{
u32 val;
-
- /* Restore the CTL value if it lost, e.g. GPU reset */
-
+ /* Restore the CTL value if it was lost, e.g. GPU reset */
+ /* Use the default PWM max value if none is available. */
+ /* Note that the default max value will only be used if there is no */
+ /* value already initialized in the PWM register by the BIOS and */
+ /* nothing saved in dev_priv. */
if (HAS_PCH_SPLIT(dev_priv->dev)) {
val = I915_READ(BLC_PWM_PCH_CTL2);
+ if (dev_priv->saveBLC_PWM_CTL2 == 0 && val == 0)
+ dev_priv->saveBLC_PWM_CTL2 =
+ i915_get_default_max_backlight(dev_priv) <<
+ BLC_PWM_PCH_FREQ_SHIFT;
if (dev_priv->saveBLC_PWM_CTL2 == 0) {
dev_priv->saveBLC_PWM_CTL2 = val;
} else if (val == 0) {
@@ -146,6 +168,10 @@ static u32 i915_read_blc_pwm_ctl(struct drm_i915_private
*dev_priv)
}
} else {
val = I915_READ(BLC_PWM_CTL);
+ if (dev_priv->saveBLC_PWM_CTL == 0 && val == 0)
+ dev_priv->saveBLC_PWM_CTL =
+ i915_get_default_max_backlight(dev_priv) <<
+ BACKLIGHT_MODULATION_FREQ_SHIFT;
if (dev_priv->saveBLC_PWM_CTL == 0) {
dev_priv->saveBLC_PWM_CTL = val;
dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
--
1.7.3.1
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[Intel-gfx] [PATCH 1/2] drivers: i915: Fix BLC PWM register setup
There is an error in i915_read_blc_pwm_ctl, where the register values
are not being copied correctly. BLC_PWM_CTL and BLC_PWM_CTL2 are
getting mixed up. This patch fixes that so that saveBLC_PWM_CTL2 and
not saveBLC_PWM_CTL is copied to the BLC_PWM_CTL2 register.
Signed-off-by: Simon Que
---
drivers/gpu/drm/i915/intel_panel.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_panel.c
b/drivers/gpu/drm/i915/intel_panel.c
index a9e0c7b..f15388c 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -141,8 +141,8 @@ static u32 i915_read_blc_pwm_ctl(struct drm_i915_private
*dev_priv)
dev_priv->saveBLC_PWM_CTL2 = val;
} else if (val == 0) {
I915_WRITE(BLC_PWM_PCH_CTL2,
- dev_priv->saveBLC_PWM_CTL);
- val = dev_priv->saveBLC_PWM_CTL;
+ dev_priv->saveBLC_PWM_CTL2);
+ val = dev_priv->saveBLC_PWM_CTL2;
}
} else {
val = I915_READ(BLC_PWM_CTL);
--
1.7.3.1
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Re: [Intel-gfx] [PATCH v3 2/2] drivers: i915: Default max backlight brightness value
On Tue, Nov 8, 2011 at 2:28 PM, Matthew Garrett wrote: > On Tue, Nov 08, 2011 at 02:27:04PM -0800, Simon Que wrote: > > > This is for an x86-based Chromebook. Its firmware doesn't have the VBIOS > > support. Previously, we had our own backlight driver that also did a > > similar initialization. Now, we are trying to move away from that and > use > > the upstream driver instead. However, we still don't have the firmware > > support, which is why we have this patch to provide the missing > information. > > I'm still not clear on this. There is no video support in the firmware > at all? What happens if the kernel fails to boot > ? > There is a backup kernel partition that can be used for boot. Failing that, the system can boot from a recovery image over USB. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 2/2] drivers: i915: Default max backlight brightness value
On Tue, Nov 8, 2011 at 2:10 PM, Matthew Garrett wrote: > On Tue, Nov 08, 2011 at 02:05:14PM -0800, Simon Que wrote: > > On Tue, Nov 8, 2011 at 1:42 PM, Matthew Garrett > wrote: > > > > > I feel like I'm missing something here. Where's the firmware getting > its > > > initial value from? > > > > > > My understanding is that normally, the firmware's VBIOS can program the > > value of the PWM register. But if the firmware doesn't have the VBIOS > > initialization code, it can still provide an initial value using this new > > param, as part of the kernel command line. Either way, it's up to the > > person writing or selecting the firmware to decide what initial value to > > provide. > > So the firmware doesn't set up graphics itself, it's entirely up to the > kernel? What hardware is this for? > This is for an x86-based Chromebook. Its firmware doesn't have the VBIOS support. Previously, we had our own backlight driver that also did a similar initialization. Now, we are trying to move away from that and use the upstream driver instead. However, we still don't have the firmware support, which is why we have this patch to provide the missing information. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v3 2/2] drivers: i915: Default max backlight brightness value
On Tue, Nov 8, 2011 at 1:42 PM, Matthew Garrett wrote: > I feel like I'm missing something here. Where's the firmware getting its > initial value from? My understanding is that normally, the firmware's VBIOS can program the value of the PWM register. But if the firmware doesn't have the VBIOS initialization code, it can still provide an initial value using this new param, as part of the kernel command line. Either way, it's up to the person writing or selecting the firmware to decide what initial value to provide. Simon ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 2/2] drivers: i915: Default max backlight brightness value
Use 0x1000 as the default backlight PWM max value and period. This is
passed in as a module parameter to i915_drv and is used to program the
PWM registers. It can be set to other values based on the needs of each
system.
Signed-off-by: Simon Que
---
Matthew, this patch has been reworked to better address your concerns. It is
more clearly shown that it will only affect the systems that don't have the
proper register values to begin with.
drivers/gpu/drm/i915/i915_drv.c|3 +++
drivers/gpu/drm/i915/i915_drv.h|1 +
drivers/gpu/drm/i915/i915_reg.h|1 +
drivers/gpu/drm/i915/intel_panel.c | 13 +++--
4 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index eb91e2d..fd06ce8 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -70,6 +70,9 @@ module_param_named(vbt_sdvo_panel_type,
i915_vbt_sdvo_panel_type, int, 0600);
static bool i915_try_reset = true;
module_param_named(reset, i915_try_reset, bool, 0600);
+unsigned int i915_max_backlight = 0x1000;
+module_param_named(max_backlight, i915_max_backlight, bool, 0600);
+
static struct drm_driver driver;
extern int intel_agp_enabled;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1c44613..2a2b558 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -999,6 +999,7 @@ extern unsigned int i915_panel_use_ssc;
extern int i915_vbt_sdvo_panel_type;
extern unsigned int i915_enable_rc6;
extern unsigned int i915_enable_fbc;
+extern unsigned int i915_max_backlight;
extern int i915_suspend(struct drm_device *dev, pm_message_t state);
extern int i915_resume(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5d5def7..a832028 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3275,6 +3275,7 @@
#define PWM_POLARITY_ACTIVE_HIGH2 (0 << 28)
#define BLC_PWM_PCH_CTL2 0xc8254
+#define BLC_PWM_PCH_FREQ_SHIFT 16
#define PCH_PP_STATUS 0xc7200
#define PCH_PP_CONTROL 0xc7204
diff --git a/drivers/gpu/drm/i915/intel_panel.c
b/drivers/gpu/drm/i915/intel_panel.c
index f15388c..a087f1c 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -133,10 +133,16 @@ static u32 i915_read_blc_pwm_ctl(struct drm_i915_private
*dev_priv)
{
u32 val;
- /* Restore the CTL value if it lost, e.g. GPU reset */
-
+ /* Restore the CTL value if it was lost, e.g. GPU reset */
+ /* Use the default PWM max value if none is available. */
+ /* Note that the default max value will only be used if there is no */
+ /* value already initialized in the PWM register by the BIOS and */
+ /* nothing saved in dev_priv. */
if (HAS_PCH_SPLIT(dev_priv->dev)) {
val = I915_READ(BLC_PWM_PCH_CTL2);
+ if (dev_priv->saveBLC_PWM_CTL2 == 0 && val == 0)
+ dev_priv->saveBLC_PWM_CTL2 =
+ i915_max_backlight << BLC_PWM_PCH_FREQ_SHIFT;
if (dev_priv->saveBLC_PWM_CTL2 == 0) {
dev_priv->saveBLC_PWM_CTL2 = val;
} else if (val == 0) {
@@ -146,6 +152,9 @@ static u32 i915_read_blc_pwm_ctl(struct drm_i915_private
*dev_priv)
}
} else {
val = I915_READ(BLC_PWM_CTL);
+ if (dev_priv->saveBLC_PWM_CTL == 0 && val == 0)
+ dev_priv->saveBLC_PWM_CTL = i915_max_backlight
+ << BACKLIGHT_MODULATION_FREQ_SHIFT;
if (dev_priv->saveBLC_PWM_CTL == 0) {
dev_priv->saveBLC_PWM_CTL = val;
dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
--
1.7.2.3
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[Intel-gfx] [PATCH 1/2] drivers: i915: Fix BLC PWM register setup
There is an error in i915_read_blc_pwm_ctl, where the register values
are not being copied correctly. BLC_PWM_CTL and BLC_PWM_CTL2 are
getting mixed up. This patch fixes that so that saveBLC_PWM_CTL2 and
not saveBLC_PWM_CTL is copied to the BLC_PWM_CTL2 register.
Signed-off-by: Simon Que
---
drivers/gpu/drm/i915/intel_panel.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_panel.c
b/drivers/gpu/drm/i915/intel_panel.c
index a9e0c7b..f15388c 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -141,8 +141,8 @@ static u32 i915_read_blc_pwm_ctl(struct drm_i915_private
*dev_priv)
dev_priv->saveBLC_PWM_CTL2 = val;
} else if (val == 0) {
I915_WRITE(BLC_PWM_PCH_CTL2,
- dev_priv->saveBLC_PWM_CTL);
- val = dev_priv->saveBLC_PWM_CTL;
+ dev_priv->saveBLC_PWM_CTL2);
+ val = dev_priv->saveBLC_PWM_CTL2;
}
} else {
val = I915_READ(BLC_PWM_CTL);
--
1.7.2.3
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Re: [Intel-gfx] [PATCH v2] drivers: i915: Default max backlight brightness value
On Tue, Nov 1, 2011 at 7:54 PM, Matthew Garrett wrote: > Again, adding arbitrary constants without any explanation for why you're > making this the default really isn't acceptable. We have no way to > determine whether fixing one machine is worth making things worse for > another. The default is applied only in the case where no valid register settings have been found to be initialized by the BIOS. Hence the only systems that will be affected by this patch are the ones whose backlight PWM is already improperly configured. Hence, I think affected systems will either benefit from this change or be made no worse, as they were already broken. That said, I do think the patch could use some more explanation in comments and the patch description. ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2] drivers: i915: Default max backlight brightness value
Use 0x1000 as the default backlight PWM max value and period. This is
passed in as a module parameter to i915_drv and is used to program the
PWM registers. It can be set to other values based on the needs of each
system.
Signed-off-by: Simon Que
---
drivers/gpu/drm/i915/i915_drv.c|3 +++
drivers/gpu/drm/i915/i915_drv.h|1 +
drivers/gpu/drm/i915/i915_reg.h|1 +
drivers/gpu/drm/i915/intel_panel.c | 29 +
4 files changed, 22 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index eb91e2d..fd06ce8 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -70,6 +70,9 @@ module_param_named(vbt_sdvo_panel_type,
i915_vbt_sdvo_panel_type, int, 0600);
static bool i915_try_reset = true;
module_param_named(reset, i915_try_reset, bool, 0600);
+unsigned int i915_max_backlight = 0x1000;
+module_param_named(max_backlight, i915_max_backlight, bool, 0600);
+
static struct drm_driver driver;
extern int intel_agp_enabled;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2d8fa6c..6096597 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -999,6 +999,7 @@ extern unsigned int i915_panel_use_ssc;
extern int i915_vbt_sdvo_panel_type;
extern unsigned int i915_enable_rc6;
extern unsigned int i915_enable_fbc;
+extern unsigned int i915_max_backlight;
extern int i915_suspend(struct drm_device *dev, pm_message_t state);
extern int i915_resume(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5d5def7..a832028 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3275,6 +3275,7 @@
#define PWM_POLARITY_ACTIVE_HIGH2 (0 << 28)
#define BLC_PWM_PCH_CTL2 0xc8254
+#define BLC_PWM_PCH_FREQ_SHIFT 16
#define PCH_PP_STATUS 0xc7200
#define PCH_PP_CONTROL 0xc7204
diff --git a/drivers/gpu/drm/i915/intel_panel.c
b/drivers/gpu/drm/i915/intel_panel.c
index 1af6888..82c6c05 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -133,27 +133,32 @@ static u32 i915_read_blc_pwm_ctl(struct drm_i915_private
*dev_priv)
{
u32 val;
- /* Restore the CTL value if it lost, e.g. GPU reset */
-
+ /* Restore the CTL value if it was lost, e.g. GPU reset */
+ /* Use the default PWM max if none is available. */
if (HAS_PCH_SPLIT(dev_priv->dev)) {
val = I915_READ(BLC_PWM_PCH_CTL2);
- if (dev_priv->saveBLC_PWM_CTL2 == 0) {
+ if (dev_priv->saveBLC_PWM_CTL2 == 0 && val == 0)
+ dev_priv->saveBLC_PWM_CTL2 =
+ i915_max_backlight << BLC_PWM_PCH_FREQ_SHIFT;
+ else if (dev_priv->saveBLC_PWM_CTL2 == 0)
dev_priv->saveBLC_PWM_CTL2 = val;
- } else if (val == 0) {
+ if (val == 0) {
I915_WRITE(BLC_PWM_PCH_CTL2,
- dev_priv->saveBLC_PWM_CTL);
- val = dev_priv->saveBLC_PWM_CTL;
+ dev_priv->saveBLC_PWM_CTL2);
+ val = dev_priv->saveBLC_PWM_CTL2;
}
} else {
val = I915_READ(BLC_PWM_CTL);
- if (dev_priv->saveBLC_PWM_CTL == 0) {
+ if (dev_priv->saveBLC_PWM_CTL == 0 && val == 0) {
+ dev_priv->saveBLC_PWM_CTL = i915_max_backlight
+ << BACKLIGHT_MODULATION_FREQ_SHIFT;
+ } else if (dev_priv->saveBLC_PWM_CTL == 0) {
dev_priv->saveBLC_PWM_CTL = val;
dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
- } else if (val == 0) {
- I915_WRITE(BLC_PWM_CTL,
- dev_priv->saveBLC_PWM_CTL);
- I915_WRITE(BLC_PWM_CTL2,
- dev_priv->saveBLC_PWM_CTL2);
+ }
+ if (val == 0) {
+ I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
+ I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2);
val = dev_priv->saveBLC_PWM_CTL;
}
}
--
1.7.2.3
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Re: [Intel-gfx] drivers: i915: Default max backlight brightness value
Sorry, this is the wrong patch, please disregard.
On Tue, Nov 1, 2011 at 6:58 PM, Simon Que wrote:
> Use 0x1000 as the default backlight PWM max value and period. This is
> passed in as a module parameter to i915_drv and is used to program the
> PWM registers. It can be set to other values based on the needs of each
> system.
>
> Signed-off-by: Simon Que
> ---
> drivers/gpu/drm/i915/i915_reg.h|1 +
> drivers/gpu/drm/i915/intel_panel.c | 29 +
> 2 files changed, 18 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 5d5def7..a832028 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3275,6 +3275,7 @@
> #define PWM_POLARITY_ACTIVE_HIGH2 (0 << 28)
>
> #define BLC_PWM_PCH_CTL2 0xc8254
> +#define BLC_PWM_PCH_FREQ_SHIFT 16
>
> #define PCH_PP_STATUS 0xc7200
> #define PCH_PP_CONTROL 0xc7204
> diff --git a/drivers/gpu/drm/i915/intel_panel.c
> b/drivers/gpu/drm/i915/intel_panel.c
> index 05f500c..b5d2244 100644
> --- a/drivers/gpu/drm/i915/intel_panel.c
> +++ b/drivers/gpu/drm/i915/intel_panel.c
> @@ -133,27 +133,32 @@ static u32 i915_read_blc_pwm_ctl(struct
> drm_i915_private *dev_priv)
> {
>u32 val;
>
> - /* Restore the CTL value if it lost, e.g. GPU reset */
> -
> + /* Restore the CTL value if it was lost, e.g. GPU reset */
> + /* Use the default PWM max if none is available. */
>if (HAS_PCH_SPLIT(dev_priv->dev)) {
>val = I915_READ(BLC_PWM_PCH_CTL2);
> - if (dev_priv->saveBLC_PWM_CTL2 == 0) {
> + if (dev_priv->saveBLC_PWM_CTL2 == 0 && val == 0)
> + dev_priv->saveBLC_PWM_CTL2 =
> + i915_max_backlight <<
> BLC_PWM_PCH_FREQ_SHIFT;
> + else if (dev_priv->saveBLC_PWM_CTL2 == 0)
>dev_priv->saveBLC_PWM_CTL2 = val;
> - } else if (val == 0) {
> + if (val == 0) {
>I915_WRITE(BLC_PWM_PCH_CTL2,
> - dev_priv->saveBLC_PWM_CTL);
> - val = dev_priv->saveBLC_PWM_CTL;
> + dev_priv->saveBLC_PWM_CTL2);
> + val = dev_priv->saveBLC_PWM_CTL2;
>}
>} else {
>val = I915_READ(BLC_PWM_CTL);
> - if (dev_priv->saveBLC_PWM_CTL == 0) {
> + if (dev_priv->saveBLC_PWM_CTL == 0 && val == 0) {
> + dev_priv->saveBLC_PWM_CTL = i915_max_backlight
> + << BACKLIGHT_MODULATION_FREQ_SHIFT;
> + } else if (dev_priv->saveBLC_PWM_CTL == 0) {
>dev_priv->saveBLC_PWM_CTL = val;
>dev_priv->saveBLC_PWM_CTL2 =
> I915_READ(BLC_PWM_CTL2);
> - } else if (val == 0) {
> - I915_WRITE(BLC_PWM_CTL,
> - dev_priv->saveBLC_PWM_CTL);
> - I915_WRITE(BLC_PWM_CTL2,
> - dev_priv->saveBLC_PWM_CTL2);
> + }
> + if (val == 0) {
> + I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
> + I915_WRITE(BLC_PWM_CTL2,
> dev_priv->saveBLC_PWM_CTL2);
>val = dev_priv->saveBLC_PWM_CTL;
>}
>}
> --
> 1.7.2.3
>
>
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[Intel-gfx] drivers: i915: Default max backlight brightness value
Use 0x1000 as the default backlight PWM max value and period. This is
passed in as a module parameter to i915_drv and is used to program the
PWM registers. It can be set to other values based on the needs of each
system.
Signed-off-by: Simon Que
---
drivers/gpu/drm/i915/i915_reg.h|1 +
drivers/gpu/drm/i915/intel_panel.c | 29 +
2 files changed, 18 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5d5def7..a832028 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3275,6 +3275,7 @@
#define PWM_POLARITY_ACTIVE_HIGH2 (0 << 28)
#define BLC_PWM_PCH_CTL2 0xc8254
+#define BLC_PWM_PCH_FREQ_SHIFT 16
#define PCH_PP_STATUS 0xc7200
#define PCH_PP_CONTROL 0xc7204
diff --git a/drivers/gpu/drm/i915/intel_panel.c
b/drivers/gpu/drm/i915/intel_panel.c
index 05f500c..b5d2244 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -133,27 +133,32 @@ static u32 i915_read_blc_pwm_ctl(struct drm_i915_private
*dev_priv)
{
u32 val;
- /* Restore the CTL value if it lost, e.g. GPU reset */
-
+ /* Restore the CTL value if it was lost, e.g. GPU reset */
+ /* Use the default PWM max if none is available. */
if (HAS_PCH_SPLIT(dev_priv->dev)) {
val = I915_READ(BLC_PWM_PCH_CTL2);
- if (dev_priv->saveBLC_PWM_CTL2 == 0) {
+ if (dev_priv->saveBLC_PWM_CTL2 == 0 && val == 0)
+ dev_priv->saveBLC_PWM_CTL2 =
+ i915_max_backlight << BLC_PWM_PCH_FREQ_SHIFT;
+ else if (dev_priv->saveBLC_PWM_CTL2 == 0)
dev_priv->saveBLC_PWM_CTL2 = val;
- } else if (val == 0) {
+ if (val == 0) {
I915_WRITE(BLC_PWM_PCH_CTL2,
- dev_priv->saveBLC_PWM_CTL);
- val = dev_priv->saveBLC_PWM_CTL;
+ dev_priv->saveBLC_PWM_CTL2);
+ val = dev_priv->saveBLC_PWM_CTL2;
}
} else {
val = I915_READ(BLC_PWM_CTL);
- if (dev_priv->saveBLC_PWM_CTL == 0) {
+ if (dev_priv->saveBLC_PWM_CTL == 0 && val == 0) {
+ dev_priv->saveBLC_PWM_CTL = i915_max_backlight
+ << BACKLIGHT_MODULATION_FREQ_SHIFT;
+ } else if (dev_priv->saveBLC_PWM_CTL == 0) {
dev_priv->saveBLC_PWM_CTL = val;
dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
- } else if (val == 0) {
- I915_WRITE(BLC_PWM_CTL,
- dev_priv->saveBLC_PWM_CTL);
- I915_WRITE(BLC_PWM_CTL2,
- dev_priv->saveBLC_PWM_CTL2);
+ }
+ if (val == 0) {
+ I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
+ I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2);
val = dev_priv->saveBLC_PWM_CTL;
}
}
--
1.7.2.3
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Re: [Intel-gfx] [PATCH] drivers: i915: Default max backlight brightness value
On Fri, Oct 14, 2011 at 4:46 PM, Simon Que wrote:
> In the native backlight driver, use 4096 (0x1000) as the default backlight
> period, and use the period as the default max brightness.
>
> The default brightness is defined in a separate function that can be
> expanded to allow for different defaults on different systems in the
> future.
>
> Change-Id: Ie783b53dd034dcd7bf42e24ffc911cf2f10a5676
> Signed-off-by: Simon Que
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_panel.c | 22 ++
> 2 files changed, 19 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5d5def7..a832028 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3275,6 +3275,7 @@
> #define PWM_POLARITY_ACTIVE_HIGH2 (0 << 28)
>
> #define BLC_PWM_PCH_CTL2 0xc8254
> +#define BLC_PWM_PCH_FREQ_SHIFT 16
>
> #define PCH_PP_STATUS 0xc7200
> #define PCH_PP_CONTROL 0xc7204
> diff --git a/drivers/gpu/drm/i915/intel_panel.c
> b/drivers/gpu/drm/i915/intel_panel.c
> index 05f500c..8205945 100644
> --- a/drivers/gpu/drm/i915/intel_panel.c
> +++ b/drivers/gpu/drm/i915/intel_panel.c
> @@ -161,6 +161,12 @@ static u32 i915_read_blc_pwm_ctl(struct drm_i915_private
> *dev_priv)
> return val;
> }
>
> +static u32 intel_panel_get_default_backlight_period(struct drm_device *dev)
> +{
> + /* The default number of clock cycles in one backlight PWM period. */
> + return 0x1000;
> +}
> +
> u32 intel_panel_get_max_backlight(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -168,11 +174,19 @@ u32 intel_panel_get_max_backlight(struct drm_device
> *dev)
>
> max = i915_read_blc_pwm_ctl(dev_priv);
> if (max == 0) {
> - /* XXX add code here to query mode clock or hardware clock
> - * and program max PWM appropriately.
> + /* If no max backlight was found, use the default PWM period
> as
> + * the max backlight value.
> */
> - printk_once(KERN_WARNING "fixme: max PWM is zero.\n");
> - return 1;
> + max = intel_panel_get_default_backlight_period(dev);
> + if (HAS_PCH_SPLIT(dev_priv->dev)) {
> + u32 val = max << BLC_PWM_PCH_FREQ_SHIFT;
> + I915_WRITE(BLC_PWM_PCH_CTL2, val);
> + } else {
> + u32 val = max << BACKLIGHT_MODULATION_FREQ_SHIFT;
> + I915_WRITE(BLC_PWM_CTL, val);
> + }
> +
> + return max;
> }
>
> if (HAS_PCH_SPLIT(dev)) {
> --
> 1.7.2.3
>
>
Please provide feedback on this patch. I am hoping that more people
are available now that the Linux Conference is over. :)
___
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Re: [Intel-gfx] [PATCH] drivers: i915: Default max backlight brightness value
Hi, could I get some feedback on this patch, please?
Simon
On Fri, Oct 14, 2011 at 4:46 PM, Simon Que wrote:
> In the native backlight driver, use 4096 (0x1000) as the default backlight
> period, and use the period as the default max brightness.
>
> The default brightness is defined in a separate function that can be
> expanded to allow for different defaults on different systems in the
> future.
>
> Change-Id: Ie783b53dd034dcd7bf42e24ffc911cf2f10a5676
> Signed-off-by: Simon Que
> ---
> drivers/gpu/drm/i915/i915_reg.h|1 +
> drivers/gpu/drm/i915/intel_panel.c | 22 ++
> 2 files changed, 19 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 5d5def7..a832028 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3275,6 +3275,7 @@
> #define PWM_POLARITY_ACTIVE_HIGH2 (0 << 28)
>
> #define BLC_PWM_PCH_CTL2 0xc8254
> +#define BLC_PWM_PCH_FREQ_SHIFT 16
>
> #define PCH_PP_STATUS 0xc7200
> #define PCH_PP_CONTROL 0xc7204
> diff --git a/drivers/gpu/drm/i915/intel_panel.c
> b/drivers/gpu/drm/i915/intel_panel.c
> index 05f500c..8205945 100644
> --- a/drivers/gpu/drm/i915/intel_panel.c
> +++ b/drivers/gpu/drm/i915/intel_panel.c
> @@ -161,6 +161,12 @@ static u32 i915_read_blc_pwm_ctl(struct
> drm_i915_private *dev_priv)
>return val;
> }
>
> +static u32 intel_panel_get_default_backlight_period(struct drm_device
> *dev)
> +{
> + /* The default number of clock cycles in one backlight PWM period.
> */
> + return 0x1000;
> +}
> +
> u32 intel_panel_get_max_backlight(struct drm_device *dev)
> {
>struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -168,11 +174,19 @@ u32 intel_panel_get_max_backlight(struct drm_device
> *dev)
>
>max = i915_read_blc_pwm_ctl(dev_priv);
>if (max == 0) {
> - /* XXX add code here to query mode clock or hardware clock
> -* and program max PWM appropriately.
> + /* If no max backlight was found, use the default PWM
> period as
> +* the max backlight value.
> */
> - printk_once(KERN_WARNING "fixme: max PWM is zero.\n");
> - return 1;
> + max = intel_panel_get_default_backlight_period(dev);
> + if (HAS_PCH_SPLIT(dev_priv->dev)) {
> + u32 val = max << BLC_PWM_PCH_FREQ_SHIFT;
> + I915_WRITE(BLC_PWM_PCH_CTL2, val);
> + } else {
> + u32 val = max << BACKLIGHT_MODULATION_FREQ_SHIFT;
> + I915_WRITE(BLC_PWM_CTL, val);
> + }
> +
> + return max;
>}
>
>if (HAS_PCH_SPLIT(dev)) {
> --
> 1.7.2.3
>
>
___
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[Intel-gfx] [PATCH] drivers: i915: Default max backlight brightness value
In the native backlight driver, use 4096 (0x1000) as the default backlight
period, and use the period as the default max brightness.
The default brightness is defined in a separate function that can be
expanded to allow for different defaults on different systems in the
future.
Change-Id: Ie783b53dd034dcd7bf42e24ffc911cf2f10a5676
Signed-off-by: Simon Que
---
drivers/gpu/drm/i915/i915_reg.h|1 +
drivers/gpu/drm/i915/intel_panel.c | 22 ++
2 files changed, 19 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5d5def7..a832028 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3275,6 +3275,7 @@
#define PWM_POLARITY_ACTIVE_HIGH2 (0 << 28)
#define BLC_PWM_PCH_CTL2 0xc8254
+#define BLC_PWM_PCH_FREQ_SHIFT 16
#define PCH_PP_STATUS 0xc7200
#define PCH_PP_CONTROL 0xc7204
diff --git a/drivers/gpu/drm/i915/intel_panel.c
b/drivers/gpu/drm/i915/intel_panel.c
index 05f500c..8205945 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -161,6 +161,12 @@ static u32 i915_read_blc_pwm_ctl(struct drm_i915_private
*dev_priv)
return val;
}
+static u32 intel_panel_get_default_backlight_period(struct drm_device *dev)
+{
+ /* The default number of clock cycles in one backlight PWM period. */
+ return 0x1000;
+}
+
u32 intel_panel_get_max_backlight(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -168,11 +174,19 @@ u32 intel_panel_get_max_backlight(struct drm_device *dev)
max = i915_read_blc_pwm_ctl(dev_priv);
if (max == 0) {
- /* XXX add code here to query mode clock or hardware clock
-* and program max PWM appropriately.
+ /* If no max backlight was found, use the default PWM period as
+* the max backlight value.
*/
- printk_once(KERN_WARNING "fixme: max PWM is zero.\n");
- return 1;
+ max = intel_panel_get_default_backlight_period(dev);
+ if (HAS_PCH_SPLIT(dev_priv->dev)) {
+ u32 val = max << BLC_PWM_PCH_FREQ_SHIFT;
+ I915_WRITE(BLC_PWM_PCH_CTL2, val);
+ } else {
+ u32 val = max << BACKLIGHT_MODULATION_FREQ_SHIFT;
+ I915_WRITE(BLC_PWM_CTL, val);
+ }
+
+ return max;
}
if (HAS_PCH_SPLIT(dev)) {
--
1.7.2.3
___
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Re: [Intel-gfx] [PATCH] CHROMIUM: i915: Select non-alternate SSC frequency for some systems
> Do you expect to have other settings that you won't get from a VBIOS VBT
> (e.g. video timings, dual refresh info)?
>
> If so, it might make more sense to have an alternate init path for the
> non-VBT values to replace all the VBT parsing. I.e. if your DMI match
> happens, call into something other than our init_bios routine to set up
> defaults for the platform.
>
> --
> Jesse Barnes, Intel Open Source Technology Center
Hi Jesse,
I am not expecting any other settings. Having an alternate init path
isn't quite what I have in mind. This patch is specifically for
intel_bios_ssc_frequency, which has 2 choices for frequency (primary &
alternate).
You do bring up a good point about other settings though. What if,
for example, there were another system that wanted lvds_dither=0 and
another wanted edp.bpp=8 and another wanted edp.bpp=16?. It would be
impractical to define separate functions for them -- we would have to
accommodate each of these system-specific settings independently.
Instead, I think we could introduce a function that would allow for
quick DMI checks, without having to define bulky DMI tables:
static bool is_product(const char *name) {
struct dmi_system_id id[] = {
{
.callback = NULL,
.matches = {
DMI_MATCH(DMI_PRODUCT_NAME, name),
}
},
{}
}
return dmi_check_system(id);
}
In this current patch, we can simply have:
if (is_product("Lumpy"))
dev_priv->lvds_ssc_freq = intel_bios_ssc_frequency(dev, 0);
else
dev_priv->lvds_ssc_freq = intel_bios_ssc_frequency(dev, 1);
In the future, if others want to add the example defaults I listed
earlier (lvds_dither and edp.bpp), they can do something like:
if (is_product("AAA") || is_product("BBB"))
dev_priv->lvds_dither = 1;
else
dev_priv->lvds_dither = 0;
...
if (is_product("CCC") || is_product("DDD"))
dev_priv->edp.bpp = 8;
else if (is_product("EEE"))
dev_priv->edp.bpp = 16;
else
dev_priv->edp.bpp = 18;
These selections are all independent of each other. All this will
still happen within init_vbt_defaults() but without the need to define
more DMI structures for each check.
Some ideas for developing this further:
- Create more quick DMI check functions for the other possible DMI
match criteria.
- Include all these functions in the DMI API, so all modules can use them.
Thanks,
Simon
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[Intel-gfx] [PATCH] CHROMIUM: i915: Select non-alternate SSC frequency for some systems
Hi,
Here's a patch to introduce a DMI-based SSC frequency selection in
intel_bios.c. Instead of always selecting the "alternate" SSC
frequency as default during initialization, this patch lets some
systems have the non-alternate frequency by default.
Thanks,
Simon
=
drivers: i915: Select non-alternate SSC frequency for some systems
When initializing VBT default values, the alternate BIOS SSC frequency
is selected. This patch allows the non-alternate frequency to be
selected as a default, for specified systems. There is a DMI match list
for systems that are to use the non-alternate frequency. Currently,
only Lumpy is on the list.
Signed-off-by: Simon Que
---
drivers/gpu/drm/i915/intel_bios.c | 17 -
1 files changed, 16 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_bios.c
b/drivers/gpu/drm/i915/intel_bios.c
index 927442a..ec75f15 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -25,6 +25,7 @@
*
*/
#include
+#include
#include "drmP.h"
#include "drm.h"
#include "i915_drm.h"
@@ -565,6 +566,17 @@ parse_device_mapping(struct drm_i915_private *dev_priv,
return;
}
+static const struct dmi_system_id lvds_do_not_use_alternate_frequency[] = {
+ {
+ .callback = NULL,
+ .ident = "Lumpy",
+ .matches = {
+ DMI_MATCH(DMI_PRODUCT_NAME, "Lumpy"),
+ }
+ },
+ { }
+};
+
static void
init_vbt_defaults(struct drm_i915_private *dev_priv)
{
@@ -585,7 +597,10 @@ init_vbt_defaults(struct drm_i915_private *dev_priv)
/* Default to using SSC */
dev_priv->lvds_use_ssc = 1;
- dev_priv->lvds_ssc_freq = intel_bios_ssc_frequency(dev, 1);
+ if (dmi_check_system(lvds_do_not_use_alternate_frequency))
+ dev_priv->lvds_ssc_freq = intel_bios_ssc_frequency(dev, 0);
+ else
+ dev_priv->lvds_ssc_freq = intel_bios_ssc_frequency(dev, 1);
DRM_DEBUG("Set default to SSC at %dMHz\n", dev_priv->lvds_ssc_freq);
/* eDP data */
--
1.7.2.3
___
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[Intel-gfx] Subject: [PATCH v4] i915: Added function to initialize VBT settings
Hi all,
I have updated the patch slightly. The title has been changed to
remove the reference to Chromium. I have also re-generated it against
drm-intel-next.
Thanks,
Simon
===
>From 070ccd99c1f2bb6c3df40c75aa4752ac01a67e45 Mon Sep 17 00:00:00 2001
From: Simon Que
Date: Wed, 22 Sep 2010 14:24:10 -0700
Subject: [PATCH] i915: Added function to initialize VBT settings
Added a function that sets the LVDS values to default settings. This will be
called by intel_init_bios before checking for the VBT (video BIOS table). The
default values are thus loaded regardless of whether a VBT is found.
The default settings in each parse function have been moved to the new
function. This consolidates all the default settings into one place.
The default dither bit value has been changed from 0 to 1. We can assume that
display devices will want dithering enabled.
Signed-off-by: Simon Que
Acked-by: Olof Johansson
BUG=none
TEST=Splash screen looks dithered upon boot.
Change-Id: If19c763824ee938ad107f655d8d94c65e39cfa56
---
drivers/gpu/drm/i915/intel_bios.c | 29 +++--
1 files changed, 19 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_bios.c
b/drivers/gpu/drm/i915/intel_bios.c
index 96f75d7..bb298f6 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -129,10 +129,6 @@ parse_lfp_panel_data(struct drm_i915_private *dev_priv,
int i, temp_downclock;
struct drm_display_mode *temp_mode;
- /* Defaults if we can't find VBT info */
- dev_priv->lvds_dither = 0;
- dev_priv->lvds_vbt = 0;
-
lvds_options = find_section(bdb, BDB_LVDS_OPTIONS);
if (!lvds_options)
return;
@@ -230,8 +226,6 @@ parse_sdvo_panel_data(struct drm_i915_private *dev_priv,
struct lvds_dvo_timing *dvo_timing;
struct drm_display_mode *panel_fixed_mode;
- dev_priv->sdvo_lvds_vbt_mode = NULL;
-
sdvo_lvds_options = find_section(bdb, BDB_SDVO_LVDS_OPTIONS);
if (!sdvo_lvds_options)
return;
@@ -260,10 +254,6 @@ parse_general_features(struct drm_i915_private *dev_priv,
struct drm_device *dev = dev_priv->dev;
struct bdb_general_features *general;
- /* Set sensible defaults in case we can't find the general block */
- dev_priv->int_tv_support = 1;
- dev_priv->int_crt_support = 1;
-
general = find_section(bdb, BDB_GENERAL_FEATURES);
if (general) {
dev_priv->int_tv_support = general->int_tv_support;
@@ -513,6 +503,22 @@ parse_device_mapping(struct drm_i915_private *dev_priv,
}
return;
}
+
+static void
+init_vbt_defaults(struct drm_i915_private *dev_priv)
+{
+ /* LFP panel data */
+ dev_priv->lvds_dither = 1;
+ dev_priv->lvds_vbt = 0;
+
+ /* SDVO panel data */
+ dev_priv->sdvo_lvds_vbt_mode = NULL;
+
+ /* general features */
+ dev_priv->int_tv_support = 1;
+ dev_priv->int_crt_support = 1;
+}
+
/**
* intel_init_bios - initialize VBIOS settings & find VBT
* @dev: DRM device
@@ -550,6 +556,9 @@ intel_init_bios(struct drm_device *dev)
}
}
+ /* Initialize to default VBT values */
+ init_vbt_defaults(dev_priv);
+
if (!vbt) {
DRM_ERROR("VBT signature missing\n");
pci_unmap_rom(pdev, bios);
--
1.7.1
From 070ccd99c1f2bb6c3df40c75aa4752ac01a67e45 Mon Sep 17 00:00:00 2001
From: Simon Que
Date: Wed, 22 Sep 2010 14:24:10 -0700
Subject: [PATCH] i915: Added function to initialize VBT settings
Added a function that sets the LVDS values to default settings. This will be
called by intel_init_bios before checking for the VBT (video BIOS table). The
default values are thus loaded regardless of whether a VBT is found.
The default settings in each parse function have been moved to the new
function. This consolidates all the default settings into one place.
The default dither bit value has been changed from 0 to 1. We can assume that
display devices will want dithering enabled.
Signed-off-by: Simon Que
Acked-by: Olof Johansson
BUG=none
TEST=Splash screen looks dithered upon boot.
Change-Id: If19c763824ee938ad107f655d8d94c65e39cfa56
---
drivers/gpu/drm/i915/intel_bios.c | 29 +++--
1 files changed, 19 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 96f75d7..bb298f6 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -129,10 +129,6 @@ parse_lfp_panel_data(struct drm_i915_private *dev_priv,
int i, temp_downclock;
struct drm_display_mode *temp_mode;
- /* Defaults if we can't find VBT info */
- dev_priv->lvds_dither = 0;
- dev_priv->lvds_vbt = 0;
-
lvds_options = find_section(bdb, BDB_LVDS_OPTION
[Intel-gfx] [PATCH v3] CHROMIUM: i915: Added function to initialize VBT settings
Hi all,
I have updated the patch containing the dither bit change and VBT
default settings. This time, all default values have been moved to a
single function, init_vbt_defaults. This function is called from
intel_init_bios before checking for VBT. Hence, it is used in both
the VBT found and VBT not found cases.
The parse functions previously contained VBT default values for the
case where VBT was found -- those have been moved to the new function
init_vbt_defaults. This new arrangement reduces code redundancy (no
need to set dither bit in two places) and consolidates all default
settings into one place.
Thanks,
Simon
==
CHROMIUM: i915: Added function to initialize VBT settings
Added a function that sets the LVDS values to default settings. This will be
called by intel_init_bios before checking for the VBT (video BIOS table). The
default values are thus loaded regardless of whether a VBT is found.
The default settings in each parse function have been moved to the new
function. This consolidates all the default settings into one place.
The default dither bit value has been changed from 0 to 1. We can assume that
display devices will want dithering enabled.
Signed-off-by: Simon Que
BUG=none
TEST=Splash screen looks dithered upon boot.
Change-Id: If19c763824ee938ad107f655d8d94c65e39cfa56
---
drivers/gpu/drm/i915/intel_bios.c | 29 +++--
1 files changed, 19 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_bios.c
b/drivers/gpu/drm/i915/intel_bios.c
index 70c9d4b..ad030ff 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -119,10 +119,6 @@ parse_lfp_panel_data(struct drm_i915_private *dev_priv,
int i, temp_downclock;
struct drm_display_mode *temp_mode;
- /* Defaults if we can't find VBT info */
- dev_priv->lvds_dither = 0;
- dev_priv->lvds_vbt = 0;
-
lvds_options = find_section(bdb, BDB_LVDS_OPTIONS);
if (!lvds_options)
return;
@@ -220,8 +216,6 @@ parse_sdvo_panel_data(struct drm_i915_private *dev_priv,
struct lvds_dvo_timing *dvo_timing;
struct drm_display_mode *panel_fixed_mode;
- dev_priv->sdvo_lvds_vbt_mode = NULL;
-
sdvo_lvds_options = find_section(bdb, BDB_SDVO_LVDS_OPTIONS);
if (!sdvo_lvds_options)
return;
@@ -250,10 +244,6 @@ parse_general_features(struct drm_i915_private *dev_priv,
struct drm_device *dev = dev_priv->dev;
struct bdb_general_features *general;
- /* Set sensible defaults in case we can't find the general block */
- dev_priv->int_tv_support = 1;
- dev_priv->int_crt_support = 1;
-
general = find_section(bdb, BDB_GENERAL_FEATURES);
if (general) {
dev_priv->int_tv_support = general->int_tv_support;
@@ -501,6 +491,22 @@ parse_device_mapping(struct drm_i915_private *dev_priv,
}
return;
}
+
+static void
+init_vbt_defaults(struct drm_i915_private *dev_priv)
+{
+ /* LFP panel data */
+ dev_priv->lvds_dither = 1;
+ dev_priv->lvds_vbt = 0;
+
+ /* SDVO panel data */
+ dev_priv->sdvo_lvds_vbt_mode = NULL;
+
+ /* general features */
+ dev_priv->int_tv_support = 1;
+ dev_priv->int_crt_support = 1;
+}
+
/**
* intel_init_bios - initialize VBIOS settings & find VBT
* @dev: DRM device
@@ -538,6 +544,9 @@ intel_init_bios(struct drm_device *dev)
}
}
+ /* Initialize to default VBT values */
+ init_vbt_defaults(dev_priv);
+
if (!vbt) {
DRM_ERROR("VBT signature missing\n");
pci_unmap_rom(pdev, bios);
--
1.7.1
From 8b1d178163e418aacb3677593e4e301c18603251 Mon Sep 17 00:00:00 2001
From: Simon Que
Date: Wed, 22 Sep 2010 14:24:10 -0700
Subject: [PATCH] CHROMIUM: i915: Added function to initialize VBT settings
Added a function that sets the LVDS values to default settings. This will be
called by intel_init_bios before checking for the VBT (video BIOS table). The
default values are thus loaded regardless of whether a VBT is found.
The default settings in each parse function have been moved to the new
function. This consolidates all the default settings into one place.
The default dither bit value has been changed from 0 to 1. We can assume that
display devices will want dithering enabled.
Signed-off-by: Simon Que
BUG=none
TEST=Splash screen looks dithered upon boot.
Change-Id: If19c763824ee938ad107f655d8d94c65e39cfa56
---
drivers/gpu/drm/i915/intel_bios.c | 29 +++--
1 files changed, 19 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 70c9d4b..ad030ff 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -119,10 +119,6 @@
[Intel-gfx] [PATCH v3] CHROMIUM: i915: Added function to initialize VBT settings
Hi all,
I have updated the patch containing the dither bit change and VBT
default settings. This time, all default values have been moved to a
single function, init_vbt_defaults. This function is called from
intel_init_bios before checking for VBT. Hence, it is used in both
the VBT found and VBT not found cases.
The parse functions previously contained VBT default values for the
case where VBT was found -- those have been moved to the new function
init_vbt_defaults. This new arrangement reduces code redundancy (no
need to set dither bit in two places) and consolidates all default
settings into one place.
Thanks,
Simon
==
CHROMIUM: i915: Added function to initialize VBT settings
Added a function that sets the LVDS values to default settings. This will be
called by intel_init_bios before checking for the VBT (video BIOS table). The
default values are thus loaded regardless of whether a VBT is found.
The default settings in each parse function have been moved to the new
function. This consolidates all the default settings into one place.
The default dither bit value has been changed from 0 to 1. We can assume that
display devices will want dithering enabled.
Signed-off-by: Simon Que
BUG=none
TEST=Splash screen looks dithered upon boot.
Change-Id: If19c763824ee938ad107f655d8d94c65e39cfa56
---
drivers/gpu/drm/i915/intel_bios.c | 29 +++--
1 files changed, 19 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_bios.c
b/drivers/gpu/drm/i915/intel_bios.c
index 70c9d4b..ad030ff 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -119,10 +119,6 @@ parse_lfp_panel_data(struct drm_i915_private *dev_priv,
int i, temp_downclock;
struct drm_display_mode *temp_mode;
- /* Defaults if we can't find VBT info */
- dev_priv->lvds_dither = 0;
- dev_priv->lvds_vbt = 0;
-
lvds_options = find_section(bdb, BDB_LVDS_OPTIONS);
if (!lvds_options)
return;
@@ -220,8 +216,6 @@ parse_sdvo_panel_data(struct drm_i915_private *dev_priv,
struct lvds_dvo_timing *dvo_timing;
struct drm_display_mode *panel_fixed_mode;
- dev_priv->sdvo_lvds_vbt_mode = NULL;
-
sdvo_lvds_options = find_section(bdb, BDB_SDVO_LVDS_OPTIONS);
if (!sdvo_lvds_options)
return;
@@ -250,10 +244,6 @@ parse_general_features(struct drm_i915_private *dev_priv,
struct drm_device *dev = dev_priv->dev;
struct bdb_general_features *general;
- /* Set sensible defaults in case we can't find the general block */
- dev_priv->int_tv_support = 1;
- dev_priv->int_crt_support = 1;
-
general = find_section(bdb, BDB_GENERAL_FEATURES);
if (general) {
dev_priv->int_tv_support = general->int_tv_support;
@@ -501,6 +491,22 @@ parse_device_mapping(struct drm_i915_private *dev_priv,
}
return;
}
+
+static void
+init_vbt_defaults(struct drm_i915_private *dev_priv)
+{
+ /* LFP panel data */
+ dev_priv->lvds_dither = 1;
+ dev_priv->lvds_vbt = 0;
+
+ /* SDVO panel data */
+ dev_priv->sdvo_lvds_vbt_mode = NULL;
+
+ /* general features */
+ dev_priv->int_tv_support = 1;
+ dev_priv->int_crt_support = 1;
+}
+
/**
* intel_init_bios - initialize VBIOS settings & find VBT
* @dev: DRM device
@@ -538,6 +544,9 @@ intel_init_bios(struct drm_device *dev)
}
}
+ /* Initialize to default VBT values */
+ init_vbt_defaults(dev_priv);
+
if (!vbt) {
DRM_ERROR("VBT signature missing\n");
pci_unmap_rom(pdev, bios);
--
1.7.1
From 8b1d178163e418aacb3677593e4e301c18603251 Mon Sep 17 00:00:00 2001
From: Simon Que
Date: Wed, 22 Sep 2010 14:24:10 -0700
Subject: [PATCH] CHROMIUM: i915: Added function to initialize VBT settings
Added a function that sets the LVDS values to default settings. This will be
called by intel_init_bios before checking for the VBT (video BIOS table). The
default values are thus loaded regardless of whether a VBT is found.
The default settings in each parse function have been moved to the new
function. This consolidates all the default settings into one place.
The default dither bit value has been changed from 0 to 1. We can assume that
display devices will want dithering enabled.
Signed-off-by: Simon Que
BUG=none
TEST=Splash screen looks dithered upon boot.
Change-Id: If19c763824ee938ad107f655d8d94c65e39cfa56
---
drivers/gpu/drm/i915/intel_bios.c | 29 +++--
1 files changed, 19 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 70c9d4b..ad030ff 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -119,10 +119,6 @@
[Intel-gfx] [PATCH v2] CHROMIUM: i915: Added default LVDS options for the no-VBT case
Hello,
I've updated my patch for default LVDS options, based on feedback from
Chris Wilson. Updates that I've made:
- Removed Kconfig option that enables dither bit being set -- because
we can assume that we want dither enabled for all architectures
anyway. No need to have an option to turn it off.
- In the parse function, the dither bit is now set to 1 by default.
That will be used by the case where VBT exists but the LVDS section
does not.
Thanks,
Simon
===
Subject: [PATCH] CHROMIUM: i915: Added default LVDS options for the no-VBT case
Added a function that sets the LVDS values to default settings (currently only
dither bit) when there is no VBT (video BIOS table) found. Also updated dither
bit in parse function to be set by default.
Signed-off-by: Simon Que
BUG=none
TEST=Splash screen looks dithered upon boot.
Change-Id: If19c763824ee938ad107f655d8d94c65e39cfa56
---
drivers/gpu/drm/i915/intel_bios.c | 10 +-
1 files changed, 9 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_bios.c
b/drivers/gpu/drm/i915/intel_bios.c
index 70c9d4b..6cb872c 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -120,7 +120,7 @@ parse_lfp_panel_data(struct drm_i915_private *dev_priv,
struct drm_display_mode *temp_mode;
/* Defaults if we can't find VBT info */
- dev_priv->lvds_dither = 0;
+ dev_priv->lvds_dither = 1;
dev_priv->lvds_vbt = 0;
lvds_options = find_section(bdb, BDB_LVDS_OPTIONS);
@@ -501,6 +501,13 @@ parse_device_mapping(struct drm_i915_private *dev_priv,
}
return;
}
+
+static void
+get_no_vbt_default_settings(struct drm_i915_private *dev_priv)
+{
+ dev_priv->lvds_dither = 1;
+}
+
/**
* intel_init_bios - initialize VBIOS settings & find VBT
* @dev: DRM device
@@ -541,6 +548,7 @@ intel_init_bios(struct drm_device *dev)
if (!vbt) {
DRM_ERROR("VBT signature missing\n");
pci_unmap_rom(pdev, bios);
+ get_no_vbt_default_settings(dev_priv);
return -1;
}
--
1.7.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] Fwd: [PATCH] CHROMIUM: i915: Added default LVDS options for the no-VBT case
I've subscribed to the intel-gfx list and am re-sending my email.
Please see below, thanks.
Simon
-- Forwarded message --
From:
Date: Thu, Sep 23, 2010 at 12:10 PM
Subject: [PATCH] CHROMIUM: i915: Added default LVDS options for the no-VBT case
To: s...@chromium.org
Your message has been automatically rejected because this mailing list
only accepts mails from members (to avoid spam). You could subscribe
the membership at
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
-- Forwarded message --
From: Simon Que
To: Chris Wilson , Jesse Barnes
, Eric Anholt ,
intel-gfx@lists.freedesktop.org
Date: Thu, 23 Sep 2010 12:10:49 -0700
Subject: [PATCH] CHROMIUM: i915: Added default LVDS options for the no-VBT case
Hello,
Here is a patch that sets default LVDS values for the i915 video
driver when there is no Video BIOS Table (VBT) found.
Currently, intel_bios.c in the i915 driver attempts to find the VBT.
- If the VBT is found, it will parse the VBT for each section. The
parse functions set default values for each section in case that
section is missing from the VBT.
- If the VBT is not found, it exits without setting anything.
There are no default settings for the second case, where the VBT is
not found. This patch will add a function that is called only in the
case of VBT not being found. The function will set some default
values for the video driver.
Currently the only thing that is being set by this function is the
dither bit. More could be added in the future. The motivation is
that our hardware does not have a VBT, but the dither bit needs to be
set for the display to work properly. We expect that the case of not
having a VBT will be rare on other systems.
Please provide your comments and feedback.
Thanks,
Simon
Subject: [PATCH] CHROMIUM: i915: Added default LVDS options for the no-VBT case
Added a function that sets the LVDS values to default settings (currently only
dither bit) when there is no VBT (video BIOS table) found.
Signed-off-by: Simon Que
BUG=none
TEST=Splash screen looks dithered upon boot.
Change-Id: If19c763824ee938ad107f655d8d94c65e39cfa56
---
drivers/gpu/drm/Kconfig | 9 +
drivers/gpu/drm/i915/intel_bios.c | 10 ++
1 files changed, 19 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_bios.c
b/drivers/gpu/drm/i915/intel_bios.c
index 70c9d4b..ad76f30 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -501,6 +501,15 @@ parse_device_mapping(struct drm_i915_private *dev_priv,
}
return;
}
+
+static void
+get_no_vbt_default_settings(struct drm_i915_private *dev_priv)
+{
+#if CONFIG_DRM_I915_ENABLE_NO_VBT_DEFAULTS
+ dev_priv->lvds_dither = 1;
+#endif
+}
+
/**
* intel_init_bios - initialize VBIOS settings & find VBT
* @dev: DRM device
@@ -541,6 +550,7 @@ intel_init_bios(struct drm_device *dev)
if (!vbt) {
DRM_ERROR("VBT signature missing\n");
pci_unmap_rom(pdev, bios);
+ get_no_vbt_default_settings(dev_priv);
return -1;
}
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 14e21c3..94979a5 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -136,6 +136,15 @@ config DRM_I915_DIRECT_BACKLIGHT
Direct backlight control gives finer granularity (0-256) than ACPI
and does not require BIOS support.
+config DRM_I915_ENABLE_NO_VBT_DEFAULTS
+ bool "Set default BIOS settings when VBT is not found"
+ depends on DRM_I915
+ help
+ Choose this option if you want the i915 driver to set the device
+ settings to a set of defaults in the event that VBT is not found.
+ This will happen on systems with firmware that does not initialize
+ video.
+
endchoice
config DRM_MGA
--
1.7.1
From a9a26c9892baeb4d39557d8520be12b33245d201 Mon Sep 17 00:00:00 2001
From: Simon Que
Date: Wed, 22 Sep 2010 14:24:10 -0700
Subject: [PATCH] CHROMIUM: i915: Added default LVDS options for the no-VBT case
Added a function that sets the LVDS values to default settings (currently only
dither bit) when there is no VBT (video BIOS table) found.
Signed-off-by: Simon Que
BUG=none
TEST=Splash screen looks dithered upon boot.
Change-Id: If19c763824ee938ad107f655d8d94c65e39cfa56
---
drivers/gpu/drm/Kconfig |9 +
drivers/gpu/drm/i915/intel_bios.c | 10 ++
1 files changed, 19 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 70c9d4b..ad76f30 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -501,6 +501,15 @@ parse_device_mapping(struct drm_i915_private *dev_priv,
}
return;
}
+
+static void
+get_no_vbt_default_settings(struct drm_i915_private *dev_priv)
+{
+#if CONFIG_DRM_I915_ENABLE_NO_VBT_DEFAULTS
+ dev_priv->lvds_dither = 1;
+#endif
+}
+
/**
* intel_init_bios - initialize VBIOS settings & find VB
