Re: [Intel-gfx] [PATCH 1/6] drm/i915: Transform WaInPlaceDecompressionHang into a simple reg write

2017-09-07 Thread Oscar Mateo 



On 09/07/2017 04:03 AM, Michał Winiarski wrote:

On Wed, Sep 06, 2017 at 05:15:49PM -0700, Oscar Mateo wrote:

Afaict, GEN9_GAMT_ECO_REG_RW_IA does not live in the context, so writing
it on every context creation is overkill (and wrong).

v2: Missing end parenthesis

Though there was a discussion whether this belongs in init_workarounds, or
init_clock_gating - I do believe that moving things around and/or renaming
things is something that should be done in a separate patch.

I compared modified registers with the spec. It all checks out.
With the missing end parenthesis added (you're still missing some in a different
patch ;) ), the whole series is:

Reviewed-by: Michał Winiarski 

-Michał


Yes, I reached the same conclusion myself after seeing how many 
wrongly-applied WAs we had. I would still like to reach an agreement on 
the refactoring of the WA code, though, because the whole thing is very 
confusing as it stands now.


Thanks for the review!

-- Oscar


Cc: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Rodrigo Vivi 
Signed-off-by: Oscar Mateo 
---
  drivers/gpu/drm/i915/intel_engine_cs.c | 25 +++--
  1 file changed, 15 insertions(+), 10 deletions(-)


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[Intel-gfx] [PATCH 1/6] drm/i915: Transform WaInPlaceDecompressionHang into a simple reg write

2017-09-07 Thread Oscar Mateo 
Afaict, GEN9_GAMT_ECO_REG_RW_IA does not live in the context, so writing
it on every context creation is overkill (and wrong).

v2: Missing end parenthesis

Cc: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Rodrigo Vivi 
Signed-off-by: Oscar Mateo 
Reviewed-by: Michał Winiarski 
---
 drivers/gpu/drm/i915/intel_engine_cs.c | 25 +++--
 1 file changed, 15 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 23812ec..4600325 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -985,8 +985,9 @@ static int skl_init_workarounds(struct intel_engine_cs 
*engine)
 
/* WaInPlaceDecompressionHang:skl */
if (IS_SKL_REVID(dev_priv, SKL_REVID_H0, REVID_FOREVER))
-   WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
-  GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
+   I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
+  (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
+   GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
 
/* WaDisableLSQCROPERFforOCL:skl */
ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
@@ -1059,8 +1060,9 @@ static int bxt_init_workarounds(struct intel_engine_cs 
*engine)
 
/* WaInPlaceDecompressionHang:bxt */
if (IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER))
-   WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
-  GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
+   I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
+  (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
+   GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
 
return 0;
 }
@@ -1089,8 +1091,9 @@ static int cnl_init_workarounds(struct intel_engine_cs 
*engine)
  GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE);
 
/* WaInPlaceDecompressionHang:cnl */
-   WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
-  GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
+   I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
+  (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
+   GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
 
/* WaPushConstantDereferenceHoldDisable:cnl */
WA_SET_BIT(GEN7_ROW_CHICKEN2, PUSH_CONSTANT_DEREF_DISABLE);
@@ -1143,8 +1146,9 @@ static int kbl_init_workarounds(struct intel_engine_cs 
*engine)
GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
 
/* WaInPlaceDecompressionHang:kbl */
-   WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
-  GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
+   I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
+  (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
+   GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
 
/* WaDisableLSQCROPERFforOCL:kbl */
ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
@@ -1196,8 +1200,9 @@ static int cfl_init_workarounds(struct intel_engine_cs 
*engine)
GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
 
/* WaInPlaceDecompressionHang:cfl */
-   WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
-  GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
+   I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
+  (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
+   GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
 
return 0;
 }
-- 
1.9.1

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Re: [Intel-gfx] [PATCH 1/6] drm/i915: Transform WaInPlaceDecompressionHang into a simple reg write

2017-09-07 Thread Michał Winiarski 
On Wed, Sep 06, 2017 at 05:15:49PM -0700, Oscar Mateo wrote:
> Afaict, GEN9_GAMT_ECO_REG_RW_IA does not live in the context, so writing
> it on every context creation is overkill (and wrong).
> 
> v2: Missing end parenthesis

Though there was a discussion whether this belongs in init_workarounds, or
init_clock_gating - I do believe that moving things around and/or renaming
things is something that should be done in a separate patch.

I compared modified registers with the spec. It all checks out.
With the missing end parenthesis added (you're still missing some in a different
patch ;) ), the whole series is:

Reviewed-by: Michał Winiarski 

-Michał

> 
> Cc: Chris Wilson 
> Cc: Mika Kuoppala 
> Cc: Rodrigo Vivi 
> Signed-off-by: Oscar Mateo 
> ---
>  drivers/gpu/drm/i915/intel_engine_cs.c | 25 +++--
>  1 file changed, 15 insertions(+), 10 deletions(-)
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[Intel-gfx] [PATCH 1/6] drm/i915: Transform WaInPlaceDecompressionHang into a simple reg write

2017-09-06 Thread Oscar Mateo 
Afaict, GEN9_GAMT_ECO_REG_RW_IA does not live in the context, so writing
it on every context creation is overkill (and wrong).

v2: Missing end parenthesis

Cc: Chris Wilson 
Cc: Mika Kuoppala 
Cc: Rodrigo Vivi 
Signed-off-by: Oscar Mateo 
---
 drivers/gpu/drm/i915/intel_engine_cs.c | 25 +++--
 1 file changed, 15 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 23812ec..4600325 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -985,8 +985,9 @@ static int skl_init_workarounds(struct intel_engine_cs 
*engine)
 
/* WaInPlaceDecompressionHang:skl */
if (IS_SKL_REVID(dev_priv, SKL_REVID_H0, REVID_FOREVER))
-   WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
-  GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
+   I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
+  (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
+   GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
 
/* WaDisableLSQCROPERFforOCL:skl */
ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
@@ -1059,8 +1060,9 @@ static int bxt_init_workarounds(struct intel_engine_cs 
*engine)
 
/* WaInPlaceDecompressionHang:bxt */
if (IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER))
-   WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
-  GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
+   I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
+  (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
+   GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
 
return 0;
 }
@@ -1089,8 +1091,9 @@ static int cnl_init_workarounds(struct intel_engine_cs 
*engine)
  GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE);
 
/* WaInPlaceDecompressionHang:cnl */
-   WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
-  GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
+   I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
+  (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
+   GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
 
/* WaPushConstantDereferenceHoldDisable:cnl */
WA_SET_BIT(GEN7_ROW_CHICKEN2, PUSH_CONSTANT_DEREF_DISABLE);
@@ -1143,8 +1146,9 @@ static int kbl_init_workarounds(struct intel_engine_cs 
*engine)
GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
 
/* WaInPlaceDecompressionHang:kbl */
-   WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
-  GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
+   I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
+  (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
+   GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
 
/* WaDisableLSQCROPERFforOCL:kbl */
ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
@@ -1196,8 +1200,9 @@ static int cfl_init_workarounds(struct intel_engine_cs 
*engine)
GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
 
/* WaInPlaceDecompressionHang:cfl */
-   WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
-  GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
+   I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
+  (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
+   GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
 
return 0;
 }
-- 
1.9.1

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