[Intel-gfx] [PATCH 2/9] drm/i915/pps: convert to drm device based logging

[Jani Nikula]

Prefer drm device based logging.

Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nik...@intel.com>
---
 drivers/gpu/drm/i915/display/intel_pps.c | 22 +++++++++++++---------
 1 file changed, 13 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_pps.c 
b/drivers/gpu/drm/i915/display/intel_pps.c
index e9c679bb1b2e..9c986e8932f8 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -1131,16 +1131,20 @@ intel_pps_readout_hw_state(struct intel_dp *intel_dp, 
struct edp_power_seq *seq)
 }
 
 static void
-intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
+intel_pps_dump_state(struct intel_dp *intel_dp, const char *state_name,
+                    const struct edp_power_seq *seq)
 {
-       DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
-                     state_name,
-                     seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
+       struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+
+       drm_dbg_kms(&i915->drm, "%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
+                   state_name,
+                   seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
 }
 
 static void
 intel_pps_verify_state(struct intel_dp *intel_dp)
 {
+       struct drm_i915_private *i915 = dp_to_i915(intel_dp);
        struct edp_power_seq hw;
        struct edp_power_seq *sw = &intel_dp->pps.pps_delays;
 
@@ -1148,9 +1152,9 @@ intel_pps_verify_state(struct intel_dp *intel_dp)
 
        if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
            hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
-               DRM_ERROR("PPS state mismatch\n");
-               intel_pps_dump_state("sw", sw);
-               intel_pps_dump_state("hw", &hw);
+               drm_err(&i915->drm, "PPS state mismatch\n");
+               intel_pps_dump_state(intel_dp, "sw", sw);
+               intel_pps_dump_state(intel_dp, "hw", &hw);
        }
 }
 
@@ -1168,7 +1172,7 @@ static void pps_init_delays(struct intel_dp *intel_dp)
 
        intel_pps_readout_hw_state(intel_dp, &cur);
 
-       intel_pps_dump_state("cur", &cur);
+       intel_pps_dump_state(intel_dp, "cur", &cur);
 
        vbt = dev_priv->vbt.edp.pps;
        /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
@@ -1200,7 +1204,7 @@ static void pps_init_delays(struct intel_dp *intel_dp)
         * too. */
        spec.t11_t12 = (510 + 100) * 10;
 
-       intel_pps_dump_state("vbt", &vbt);
+       intel_pps_dump_state(intel_dp, "vbt", &vbt);
 
        /* Use the max of the register settings and vbt. If both are
         * unset, fall back to the spec limits. */
-- 
2.30.2