Calculate port clock with C20 phy.
Signed-off-by: Mika Kahola <mika.kah...@intel.com>
Link:
https://patchwork.freedesktop.org/patch/msgid/20221014124740.774835-11-mika.kah...@intel.com
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 32 ++++++++++++++++++--
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 ++
drivers/gpu/drm/i915/display/intel_ddi.c | 4 +--
3 files changed, 33 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 285e4cdd23eb..14ea40cd0631 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -1571,9 +1571,10 @@ int intel_cx0mpllb_calc_state(struct intel_crtc_state
*crtc_state,
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
enum phy phy = intel_port_to_phy(i915, encoder->port);
- drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
-
- return intel_c10mpllb_calc_state(crtc_state, encoder);
+ if (intel_is_c10phy(i915, phy))
+ return intel_c10mpllb_calc_state(crtc_state, encoder);
+ else
+ return intel_c20pll_calc_state(crtc_state, encoder);
}
void intel_c10mpllb_readout_hw_state(struct intel_encoder *encoder,
@@ -2044,6 +2045,31 @@ int intel_c10mpllb_calc_port_clock(struct intel_encoder
*encoder,
return tmpclk;
}
+int intel_c20pll_calc_port_clock(struct intel_encoder *encoder,
+ const struct intel_c20pll_state *pll_state)
+{
+ unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1;
+ unsigned int multiplier, tx_clk_div, refclk = 38400;
+
+ if (pll_state->mpllb[6] & C20_MPLLB_FRACEN) {
+ frac_quot = pll_state->mpllb[8];
+ frac_rem = pll_state->mpllb[9];
+ frac_den = pll_state->mpllb[7];
+ multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK,
pll_state->mpllb[0]);
+ tx_clk_div = REG_FIELD_GET(C20_MPLLB_TX_CLK_DIV_MASK,
pll_state->mpllb[0]);
+ } else if (pll_state->mplla[6] & C20_MPLLA_FRACEN) {
+ frac_quot = pll_state->mplla[8];
+ frac_rem = pll_state->mplla[9];
+ frac_den = pll_state->mplla[7];
+ multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK,
pll_state->mplla[0]);
+ tx_clk_div = REG_FIELD_GET(C20_MPLLA_TX_CLK_DIV_MASK,
pll_state->mplla[1]);
+ }
+
+ return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier << 16) +
frac_quot) +
+ DIV_ROUND_CLOSEST(refclk * frac_rem, frac_den),
+ 10 << (tx_clk_div + 16));
+}
+
static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
const struct intel_crtc_state
*crtc_state,
bool lane_reversal)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index 86edbc4b1718..8ca77dfea24b 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -43,6 +43,8 @@ int intel_c10mpllb_calc_port_clock(struct intel_encoder
*encoder,
const struct intel_c10mpllb_state
*pll_state);
void intel_c10mpllb_state_verify(struct intel_atomic_state *state,
struct intel_crtc_state *new_crtc_state);
+int intel_c20pll_calc_port_clock(struct intel_encoder *encoder,
+ const struct intel_c20pll_state *pll_state);
int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock);
void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index c37f7f7d84cf..829c90b17b08 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3535,12 +3535,12 @@ static void mtl_ddi_get_config(struct intel_encoder
*encoder,
if (intel_is_c10phy(i915, phy)) {
intel_c10mpllb_readout_hw_state(encoder,
&crtc_state->cx0pll_state.c10mpllb_state);
intel_c10mpllb_dump_hw_state(i915,
&crtc_state->cx0pll_state.c10mpllb_state);
+ crtc_state->port_clock =
intel_c10mpllb_calc_port_clock(encoder,
&crtc_state->cx0pll_state.c10mpllb_state);
} else {
intel_c20pll_readout_hw_state(encoder,
&crtc_state->cx0pll_state.c20pll_state);
+ crtc_state->port_clock = intel_c20pll_calc_port_clock(encoder,
&crtc_state->cx0pll_state.c20pll_state);
}
- crtc_state->port_clock = intel_c10mpllb_calc_port_clock(encoder,
&crtc_state->cx0pll_state.c10mpllb_state);
-
intel_ddi_get_config(encoder, crtc_state);
}
--
2.34.1
