BDW/SKL/BXT support Color Space Conversion (CSC) using a 3x3 matrix
that needs to be programmed into respective CSC registers.
This patch does the following:
1. Adds the core function to program CSC correction values for
BDW/SKL/BXT platform
2. Adds CSC correction macros/defines
Signed-off-by: Shashank Sharma <shashank.sha...@intel.com>
Signed-off-by: Kausal Malladi <kausalmall...@gmail.com>
Signed-off-by: Kumar, Kiran S <kiran.s.ku...@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 7 ++
drivers/gpu/drm/i915/intel_color_manager.c | 113 +++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_color_manager.h | 8 ++
3 files changed, 128 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 39fbafc..9838afc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8195,4 +8195,11 @@ enum skl_disp_power_wells {
(_PIPE3(pipe, PAL_PREC_GCMAX_A, PAL_PREC_GCMAX_B, PAL_PREC_GCMAX_C))
+/* BDW CSC correction */
+#define CSC_COEFF_A 0x49010
+#define CSC_COEFF_B 0x49110
+#define CSC_COEFF_C 0x49210
+#define _PIPE_CSC_COEFF(pipe) \
+ (_PIPE3(pipe, CSC_COEFF_A, CSC_COEFF_B, CSC_COEFF_C))
+
#endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_color_manager.c
b/drivers/gpu/drm/i915/intel_color_manager.c
index 3d792b2..08a2e4e 100644
--- a/drivers/gpu/drm/i915/intel_color_manager.c
+++ b/drivers/gpu/drm/i915/intel_color_manager.c
@@ -363,6 +363,117 @@ static int bdw_set_degamma(struct drm_device *dev,
return 0;
}
+static uint32_t bdw_prepare_csc_coeff(int64_t coeff)
+{
+ uint32_t reg_val, ls_bit_pos, exponent_bits, sign_bit = 0;
+ int32_t mantissa;
+ uint64_t abs_coeff;
+
+ coeff = min_t(int64_t, coeff, BDW_CSC_COEFF_MAX_VAL);
+ coeff = max_t(int64_t, coeff, BDW_CSC_COEFF_MIN_VAL);
+
+ abs_coeff = abs(coeff);
+ if (abs_coeff < (BDW_CSC_COEFF_UNITY_VAL >> 3)) {
+ /* abs_coeff < 0.125 */
+ exponent_bits = 3;
+ ls_bit_pos = 19;
+ } else if (abs_coeff >= (BDW_CSC_COEFF_UNITY_VAL >> 3) &&
+ abs_coeff < (BDW_CSC_COEFF_UNITY_VAL >> 2)) {
+ /* abs_coeff >= 0.125 && val < 0.25 */
+ exponent_bits = 2;
+ ls_bit_pos = 20;
+ } else if (abs_coeff >= (BDW_CSC_COEFF_UNITY_VAL >> 2)
+ && abs_coeff < (BDW_CSC_COEFF_UNITY_VAL >> 1)) {
+ /* abs_coeff >= 0.25 && val < 0.5 */
+ exponent_bits = 1;
+ ls_bit_pos = 21;
+ } else if (abs_coeff >= (BDW_CSC_COEFF_UNITY_VAL >> 1)
+ && abs_coeff < BDW_CSC_COEFF_UNITY_VAL) {
+ /* abs_coeff >= 0.5 && val < 1.0 */
+ exponent_bits = 0;
+ ls_bit_pos = 22;
+ } else if (abs_coeff >= BDW_CSC_COEFF_UNITY_VAL &&
+ abs_coeff < (BDW_CSC_COEFF_UNITY_VAL << 1)) {
+ /* abs_coeff >= 1.0 && val < 2.0 */
+ exponent_bits = 7;
+ ls_bit_pos = 23;
+ } else {
+ /* abs_coeff >= 2.0 && val < 4.0 */
+ exponent_bits = 6;
+ ls_bit_pos = 24;
+ }
+
+ mantissa = GET_BITS_ROUNDOFF(abs_coeff, ls_bit_pos, CSC_MAX_VALS);
+ if (coeff < 0)
+ sign_bit = 1;
+
+ reg_val = 0;
+ SET_BITS(reg_val, exponent_bits, 12, 3);
+ SET_BITS(reg_val, mantissa, 3, 9);
+ SET_BITS(reg_val, sign_bit, 15, 1);
+ return reg_val;
+}
+
+static int bdw_set_csc(struct drm_device *dev, struct drm_property_blob *blob,
+ struct drm_crtc *crtc)
+{
+ enum pipe pipe;
+ enum plane plane;
+ int temp, word;
+ int count = 0;
+ u32 reg, plane_ctl, mode;
+ struct drm_ctm *csc_data;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ if (WARN_ON(!blob))
+ return -EINVAL;
+
+ if (blob->length != sizeof(struct drm_ctm)) {
+ DRM_ERROR("Invalid length of data received\n");
+ return -EINVAL;
+ }
+
+ csc_data = (struct drm_ctm *)blob->data;
+ pipe = to_intel_crtc(crtc)->pipe;
+ plane = to_intel_crtc(crtc)->plane;
+
+ plane_ctl = I915_READ(PLANE_CTL(pipe, plane));
+ plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
+ I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl);
+ reg = _PIPE_CSC_COEFF(pipe);
+
+ /*
+ * BDW CSC correction coefficients are written like this:
+ * first two values go in a pair, into first register(0:15 and 16:31)
+ * third one alone goes into second register (16:31). Same
+ * pattern repeats for 3 times = 3 * 3 = 9 values.
+ */
+ while (count < CSC_MAX_VALS) {
+ word = 0;
+ temp = bdw_prepare_csc_coeff(csc_data->ctm_coeff[count++]);
+ SET_BITS(word, temp, 16, 16);
+
+ temp = bdw_prepare_csc_coeff(csc_data->ctm_coeff[count++]);
+ SET_BITS(word, temp, 0, 16);
+
+ I915_WRITE(reg, word);
+ reg += 4;
+
+ word = 0;
+ temp = bdw_prepare_csc_coeff(csc_data->ctm_coeff[count++]);
+ SET_BITS(word, temp, 16, 16);
+ I915_WRITE(reg, word);
+ reg += 4;
+ }
+
+ /* Enable CSC functionality */
+ mode = I915_READ(PIPE_CSC_MODE(pipe));
+ mode |= CSC_POSITION_BEFORE_GAMMA;
+ I915_WRITE(PIPE_CSC_MODE(pipe), mode);
+ DRM_DEBUG_DRIVER("CSC enabled on Pipe %c\n", pipe_name(pipe));
+ return 0;
+}
+
static s32 chv_prepare_csc_coeff(s64 csc_value)
{
s32 csc_int_value;
@@ -667,6 +778,8 @@ void intel_color_manager_crtc_commit(struct drm_device *dev,
/* CSC correction */
if (IS_CHERRYVIEW(dev))
ret = chv_set_csc(dev, blob, crtc);
+ else if (IS_BROADWELL(dev) || IS_GEN9(dev))
+ ret = bdw_set_csc(dev, blob, crtc);
if (ret)
DRM_ERROR("set CSC correction failed\n");
diff --git a/drivers/gpu/drm/i915/intel_color_manager.h
b/drivers/gpu/drm/i915/intel_color_manager.h
index e0c486e..6c20cf0 100644
--- a/drivers/gpu/drm/i915/intel_color_manager.h
+++ b/drivers/gpu/drm/i915/intel_color_manager.h
@@ -90,6 +90,14 @@
#define CGM_CSC_EN (1 << 1)
#define CGM_DEGAMMA_EN (1 << 0)
+/* BDW CSC */
+/* 1.0000000 in S31.32 format */
+#define BDW_CSC_COEFF_UNITY_VAL 0x100000000
+/* 3.9921875 in S31.32 format */
+#define BDW_CSC_COEFF_MAX_VAL 0x3FE000000
+/*-4.000000 in S31.32 format */
+#define BDW_CSC_COEFF_MIN_VAL 0xFFFFFFFC00000000
+
/* Gamma on BDW */
#define BDW_SPLITGAMMA_MAX_VALS 512
#define BDW_8BIT_GAMMA_MAX_VALS 256
--
1.9.1
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