== Series Details ==

Series: series starting with [1/2] drm/i915/dp: abstract 
intel_dp_lane_max_vswing_reached()
URL   : https://patchwork.freedesktop.org/series/95689/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
89b690d2e4c1 drm/i915/dp: abstract intel_dp_lane_max_vswing_reached()
a5f36be2f5c0 drm/i915/dg2: update link training for 128b/132b
-:53: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or 
return
#53: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1349:
+               return train_set & DP_TX_FFE_PRESET_VALUE_MASK;
+       } else {

-:85: CHECK:LINE_SPACING: Please don't use multiple blank lines
#85: FILE: drivers/gpu/drm/i915/display/intel_dp_link_training.c:307:
 
+

-:142: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in 
parentheses
#142: FILE: drivers/gpu/drm/i915/display/intel_dp_link_training.c:396:
+#define TRAIN_REQ_TX_FFE_ARGS(link_status) \
+       _TRAIN_REQ_TX_FFE_ARGS(link_status, 0), \
+       _TRAIN_REQ_TX_FFE_ARGS(link_status, 1), \
+       _TRAIN_REQ_TX_FFE_ARGS(link_status, 2), \
+       _TRAIN_REQ_TX_FFE_ARGS(link_status, 3)

-:142: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'link_status' - possible 
side-effects?
#142: FILE: drivers/gpu/drm/i915/display/intel_dp_link_training.c:396:
+#define TRAIN_REQ_TX_FFE_ARGS(link_status) \
+       _TRAIN_REQ_TX_FFE_ARGS(link_status, 0), \
+       _TRAIN_REQ_TX_FFE_ARGS(link_status, 1), \
+       _TRAIN_REQ_TX_FFE_ARGS(link_status, 2), \
+       _TRAIN_REQ_TX_FFE_ARGS(link_status, 3)

-:188: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in 
parentheses
#188: FILE: drivers/gpu/drm/i915/display/intel_dp_link_training.c:521:
+#define TRAIN_SET_TX_FFE_ARGS(train_set) \
+       _TRAIN_SET_TX_FFE_ARGS((train_set)[0]), \
+       _TRAIN_SET_TX_FFE_ARGS((train_set)[1]), \
+       _TRAIN_SET_TX_FFE_ARGS((train_set)[2]), \
+       _TRAIN_SET_TX_FFE_ARGS((train_set)[3])

-:188: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'train_set' - possible 
side-effects?
#188: FILE: drivers/gpu/drm/i915/display/intel_dp_link_training.c:521:
+#define TRAIN_SET_TX_FFE_ARGS(train_set) \
+       _TRAIN_SET_TX_FFE_ARGS((train_set)[0]), \
+       _TRAIN_SET_TX_FFE_ARGS((train_set)[1]), \
+       _TRAIN_SET_TX_FFE_ARGS((train_set)[2]), \
+       _TRAIN_SET_TX_FFE_ARGS((train_set)[3])

total: 2 errors, 1 warnings, 3 checks, 251 lines checked


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