Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the DSPADDR register macro.
Signed-off-by: Jani Nikula <jani.nik...@intel.com>
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 8 ++++----
drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 2 +-
drivers/gpu/drm/i915/display/intel_fbc.c | 4 ++--
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 6 +++---
4 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
b/drivers/gpu/drm/i915/display/i9xx_plane.c
index ceb0a969357f..79280fe2662d 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -502,7 +502,7 @@ static void i9xx_plane_update_arm(struct intel_plane *plane,
intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
intel_plane_ggtt_offset(plane_state) +
dspaddr_offset);
else
- intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane),
+ intel_de_write_fw(dev_priv, DSPADDR(dev_priv, i9xx_plane),
intel_plane_ggtt_offset(plane_state) +
dspaddr_offset);
}
@@ -544,7 +544,7 @@ static void i9xx_plane_disable_arm(struct intel_plane
*plane,
if (DISPLAY_VER(dev_priv) >= 4)
intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 0);
else
- intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), 0);
+ intel_de_write_fw(dev_priv, DSPADDR(dev_priv, i9xx_plane), 0);
}
static void
@@ -1045,7 +1045,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) &
DISP_ADDR_MASK;
} else {
offset = 0;
- base = intel_de_read(dev_priv, DSPADDR(i9xx_plane));
+ base = intel_de_read(dev_priv, DSPADDR(dev_priv, i9xx_plane));
}
plane_config->base = base;
@@ -1096,7 +1096,7 @@ bool i9xx_fixup_initial_plane_config(struct intel_crtc
*crtc,
if (DISPLAY_VER(dev_priv) >= 4)
intel_de_write(dev_priv, DSPSURF(i9xx_plane), base);
else
- intel_de_write(dev_priv, DSPADDR(i9xx_plane), base);
+ intel_de_write(dev_priv, DSPADDR(dev_priv, i9xx_plane), base);
return true;
}
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
index d483569e4147..a68d7b228187 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
@@ -44,7 +44,7 @@
#define DISP_MIRROR REG_BIT(8) /* CHV pipe B */
#define _DSPAADDR 0x70184 /* pre-i965 */
-#define DSPADDR(plane) _MMIO_PIPE2(dev_priv, plane,
_DSPAADDR)
+#define DSPADDR(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane,
_DSPAADDR)
#define _DSPALINOFF 0x70184 /* i965+ */
#define DSPLINOFF(plane) _MMIO_PIPE2(dev_priv, plane,
_DSPALINOFF)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display/intel_fbc.c
index 680d7fc39503..f46e01cad053 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -327,8 +327,8 @@ static void i8xx_fbc_nuke(struct intel_fbc *fbc)
enum i9xx_plane_id i9xx_plane = fbc_state->plane->i9xx_plane;
struct drm_i915_private *dev_priv = fbc->i915;
- intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane),
- intel_de_read_fw(dev_priv, DSPADDR(i9xx_plane)));
+ intel_de_write_fw(dev_priv, DSPADDR(dev_priv, i9xx_plane),
+ intel_de_read_fw(dev_priv, DSPADDR(dev_priv,
i9xx_plane)));
}
static void i8xx_fbc_program_cfb(struct intel_fbc *fbc)
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 909823d7ed1b..944765fe22e7 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -166,7 +166,7 @@ static int iterate_generic_mmio(struct
intel_gvt_mmio_table_iter *iter)
MMIO_D(_MMIO(0x70098));
MMIO_D(_MMIO(0x7009c));
MMIO_D(DSPCNTR(dev_priv, PIPE_A));
- MMIO_D(DSPADDR(PIPE_A));
+ MMIO_D(DSPADDR(dev_priv, PIPE_A));
MMIO_D(DSPSTRIDE(PIPE_A));
MMIO_D(DSPPOS(PIPE_A));
MMIO_D(DSPSIZE(PIPE_A));
@@ -175,7 +175,7 @@ static int iterate_generic_mmio(struct
intel_gvt_mmio_table_iter *iter)
MMIO_D(DSPSURFLIVE(PIPE_A));
MMIO_D(REG_50080(PIPE_A, PLANE_PRIMARY));
MMIO_D(DSPCNTR(dev_priv, PIPE_B));
- MMIO_D(DSPADDR(PIPE_B));
+ MMIO_D(DSPADDR(dev_priv, PIPE_B));
MMIO_D(DSPSTRIDE(PIPE_B));
MMIO_D(DSPPOS(PIPE_B));
MMIO_D(DSPSIZE(PIPE_B));
@@ -184,7 +184,7 @@ static int iterate_generic_mmio(struct
intel_gvt_mmio_table_iter *iter)
MMIO_D(DSPSURFLIVE(PIPE_B));
MMIO_D(REG_50080(PIPE_B, PLANE_PRIMARY));
MMIO_D(DSPCNTR(dev_priv, PIPE_C));
- MMIO_D(DSPADDR(PIPE_C));
+ MMIO_D(DSPADDR(dev_priv, PIPE_C));
MMIO_D(DSPSTRIDE(PIPE_C));
MMIO_D(DSPPOS(PIPE_C));
MMIO_D(DSPSIZE(PIPE_C));
--
2.39.2
