Re: [Intel-gfx] [PATCH v10 4/9] drm/i915/guc: Update GuC load status as NONE on GPU reset

[Michal Wajdeczko]

On Wed, 27 Sep 2017 11:30:34 +0200, Sagar Arun Kamble  
 wrote:



Currently GPU is reset at the end of suspend via i915_gem_sanitize.
On resume, GuC will not be loaded until intel_uc_init_hw happens
during GEM resume flow but action to exit sleep can be sent to GuC
considering the FW load status. To make sure we don't invoke that
action update GuC FW load status at the end of GPU reset as NONE.

v2: Rebase.

v3: Removed intel_guc_sanitize. Marking load status as NONE at the
GPU reset point. (Chris/Michal)


Hmm, I'm not sure that touching guc private member from the outside
of guc/uc code is a good idea. Maybe we should keep call  
intel_uc_sanitize()

but call it from i915_gem_reset() as that place looks more appropriate?

Michal



Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Michał Winiarski 
Cc: Chris Wilson 
---
 drivers/gpu/drm/i915/intel_uncore.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c  
b/drivers/gpu/drm/i915/intel_uncore.c

index b3c3f94..83300f3 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1763,6 +1763,16 @@ int intel_gpu_reset(struct drm_i915_private  
*dev_priv, unsigned engine_mask)

}
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+   /*
+* FIXME: intel_uc_resume currently depends on load_status to resume
+* GuC. Since we are resetting Full GPU at the end of suspend, let us
+	 * mark the load status as NONE. Once intel_uc_resume is updated to  
take

+* into consideration GuC load state based on WOPCM, we can skip this
+* state change.
+*/
+   if (engine_mask == ALL_ENGINES)
+   dev_priv->guc.fw.load_status = INTEL_UC_FIRMWARE_NONE;
+
return ret;
 }

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Re: [Intel-gfx] [PATCH v10 9/9] drm/i915/guc: Fix GuC cleanup in unload path

[Michal Wajdeczko]

On Wed, 27 Sep 2017 11:30:39 +0200, Sagar Arun Kamble  
 wrote:



We ensure that GuC is completely suspended and client is destroyed
in i915_gem_suspend during i915_driver_unload. So now intel_uc_fini_hw
should just take care of cleanup,
hence s/intel_uc_fini_hw/intel_uc_cleanup. Correspondingly
we also updated as s/i915_guc_submission_fini/i915_guc_submission_cleanup
Other functionality to disable communication, disable interrupts and
update of ggtt.invalidate is taken care by intel_uc_suspend.

v2: Rebase w.r.t removal of GuC code restructuring.

v3: Removed intel_guc_cleanup. (Michal Wajdeczko)

v4: guc_free_load_err_log() needs to be called without checking
i915.enable_guc_loading as this param is cleared on GuC load failure.
(Michal Wajdeczko)

Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Michał Winiarski 
Reviewed-by: Michal Wajdeczko 
---
 drivers/gpu/drm/i915/i915_drv.c|  2 +-
 drivers/gpu/drm/i915/i915_guc_submission.c |  2 +-
 drivers/gpu/drm/i915/intel_uc.c| 14 --
 drivers/gpu/drm/i915/intel_uc.h|  4 ++--
 4 files changed, 8 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c  
b/drivers/gpu/drm/i915/i915_drv.c

index f79646b..4223cee 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -603,7 +603,7 @@ static void i915_gem_fini(struct drm_i915_private  
*dev_priv)

i915_gem_drain_workqueue(dev_priv);
mutex_lock(_priv->drm.struct_mutex);
-   intel_uc_fini_hw(dev_priv);
+   intel_uc_cleanup(dev_priv);
i915_gem_cleanup_engines(dev_priv);
i915_gem_contexts_fini(dev_priv);
i915_gem_cleanup_userptr(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c  
b/drivers/gpu/drm/i915/i915_guc_submission.c

index 45f2ee8..0ac9bd4 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -1053,7 +1053,7 @@ int i915_guc_submission_init(struct  
drm_i915_private *dev_priv)

return ret;
 }
-void i915_guc_submission_fini(struct drm_i915_private *dev_priv)
+void i915_guc_submission_cleanup(struct drm_i915_private *dev_priv)
 {
struct intel_guc *guc = _priv->guc;
diff --git a/drivers/gpu/drm/i915/intel_uc.c  
b/drivers/gpu/drm/i915/intel_uc.c

index 59e6995..0370265 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -439,7 +439,7 @@ int intel_uc_init_hw(struct drm_i915_private  
*dev_priv)

guc_capture_load_err_log(guc);
 err_submission:
if (i915_modparams.enable_guc_submission)
-   i915_guc_submission_fini(dev_priv);
+   i915_guc_submission_cleanup(dev_priv);
 err_guc:
i915_ggtt_disable_guc(dev_priv);
@@ -461,21 +461,15 @@ int intel_uc_init_hw(struct drm_i915_private  
*dev_priv)

return ret;
 }
-void intel_uc_fini_hw(struct drm_i915_private *dev_priv)
+void intel_uc_cleanup(struct drm_i915_private *dev_priv)
 {
guc_free_load_err_log(_priv->guc);
if (!i915_modparams.enable_guc_loading)
return;
-   guc_disable_communication(_priv->guc);
-
-   if (i915_modparams.enable_guc_submission) {
-   gen9_disable_guc_interrupts(dev_priv);
-   i915_guc_submission_fini(dev_priv);
-   }
-
-   i915_ggtt_disable_guc(dev_priv);
+   if (i915_modparams.enable_guc_submission)


In patch 6/9 you said we should avoid looking at user params
but here you're still using it ...


+   i915_guc_submission_cleanup(dev_priv);
 }
/**
diff --git a/drivers/gpu/drm/i915/intel_uc.h  
b/drivers/gpu/drm/i915/intel_uc.h

index 78ccbd9..838a364 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -207,7 +207,7 @@ struct intel_huc {
 void intel_uc_init_fw(struct drm_i915_private *dev_priv);
 void intel_uc_fini_fw(struct drm_i915_private *dev_priv);
 int intel_uc_init_hw(struct drm_i915_private *dev_priv);
-void intel_uc_fini_hw(struct drm_i915_private *dev_priv);
+void intel_uc_cleanup(struct drm_i915_private *dev_priv);
 int intel_uc_runtime_suspend(struct drm_i915_private *dev_priv);
 int intel_uc_runtime_resume(struct drm_i915_private *dev_priv);
 int intel_uc_suspend(struct drm_i915_private *dev_priv);
@@ -239,7 +239,7 @@ static inline void intel_guc_notify(struct intel_guc  
*guc)

 int i915_guc_submission_init(struct drm_i915_private *dev_priv);
 int i915_guc_submission_enable(struct drm_i915_private *dev_priv);
 void i915_guc_submission_disable(struct drm_i915_private *dev_priv);
-void i915_guc_submission_fini(struct drm_i915_private *dev_priv);
+void i915_guc_submission_cleanup(struct drm_i915_private *dev_priv);
 struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32  
size);

/* intel_guc_log.c */

___

Re: [Intel-gfx] [PATCH] drm/i915/cnl: WaForceContextSaveRestoreNonCoherent

[Chris Wilson]

Quoting Oscar Mateo (2017-09-27 18:37:07)
> 
> 
> On 09/27/2017 03:37 AM, Mika Kuoppala wrote:
> > Chris Wilson  writes:
> >
> >> Quoting Rodrigo Vivi (2017-08-23 00:27:15)
> >>> To avoid a potential hang condition with TLB invalidation
> >>> we need to enable masked bit 5 of MMIO 0xE5F0 at boot.
> >>>
> >>> Same workaround was in place for previous platforms,
> >>> but the change for CNL is more on the register offset.
> >>> But also BSpec doesn't mention the bit 15 as set on gen9
> >>> platforms and mark bit as reserved on CNL.
> >>>
> >>> Cc: Mika Kuoppala 
> >>> Cc: Oscar Mateo 
> >>> Signed-off-by: Rodrigo Vivi 
> >>> ---
> >>>   drivers/gpu/drm/i915/i915_reg.h| 1 +
> >>>   drivers/gpu/drm/i915/intel_engine_cs.c | 4 
> >>>   2 files changed, 5 insertions(+)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/i915_reg.h 
> >>> b/drivers/gpu/drm/i915/i915_reg.h
> >>> index d4ecb1905ad8..f31fab2651fb 100644
> >>> --- a/drivers/gpu/drm/i915/i915_reg.h
> >>> +++ b/drivers/gpu/drm/i915/i915_reg.h
> >>> @@ -7024,6 +7024,7 @@ enum {
> >>>   
> >>>   /* GEN8 chicken */
> >>>   #define HDC_CHICKEN0   _MMIO(0x7300)
> >>> +#define CNL_HDC_CHICKEN0   _MMIO(0xE5F0)
> >>>   #define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE(1<<15)
> >>>   #define  HDC_FENCE_DEST_SLM_DISABLE(1<<14)
> >>>   #define  HDC_DONOT_FETCH_MEM_WHEN_MASKED   (1<<11)
> >>> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
> >>> b/drivers/gpu/drm/i915/intel_engine_cs.c
> >>> index d23f18874309..26c35ce5f240 100644
> >>> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> >>> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> >>> @@ -1070,6 +1070,10 @@ static int cnl_init_workarounds(struct 
> >>> intel_engine_cs *engine)
> >>>  struct drm_i915_private *dev_priv = engine->i915;
> >>>  int ret;
> >>>   
> >>> +   /* WaForceContextSaveRestoreNonCoherent:cnl */
> >>> +   WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0,
> >>> + HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
> >> This register is not sticky (i.e. does not retain its value even with a
> >> powercontext loaded). Does it even exist?
> >> -Chris
> > That is a good question. The documentation indicates it does
> > and evidence indicates that it doesn't.
> >
> > I will check when I get cnl unless someone beats me to it.
> >
> > -Mika
> 
> H... there is a "programming note" in the BSpec for CNL+ that says:
> 
> "The register is write-only from LRI command. However, it is readable 
> for context save."

Ugh. So gem_workarounds can't read it directly or via SRM to check we
set it. But if we dumped the context image, we could find it. The test
will just have to learn to live without it.
-Chris
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/opregion: Remove null check before kfree

[Patchwork]

== Series Details ==

Series: drm/i915/opregion: Remove null check before kfree
URL   : https://patchwork.freedesktop.org/series/30964/
State : success

== Summary ==

Test perf:
Subgroup polling:
pass   -> FAIL   (shard-hsw) fdo#102252 +1
Test kms_setmode:
Subgroup basic:
fail   -> PASS   (shard-hsw) fdo#99912
Test kms_flip:
Subgroup flip-vs-modeset-interruptible:
pass   -> DMESG-WARN (shard-hsw) fdo#102557

fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102557 https://bugs.freedesktop.org/show_bug.cgi?id=102557

shard-hswtotal:2478 pass:1365 dwarn:2   dfail:0   fail:11  skip:1100 
time:10153s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5832/shards.html
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[Intel-gfx] [PATCH v2 10/11] drm/i915/execlists: Preemption!

[Chris Wilson]

When we write to ELSP, it triggers a context preemption at the earliest
arbitration point (3DPRIMITIVE, some PIPECONTROLs, a few other
operations and the explicit MI_ARB_CHECK). If this is to the same
context, it triggers a LITE_RESTORE where the RING_TAIL is merely
updated (used currently to chain requests from the same context
together, avoiding bubbles). However, if it is to a different context, a
full context-switch is performed and it will start to execute the new
context saving the image of the old for later execution.

Previously we avoided preemption by only submitting a new context when
the old was idle. But now we wish embrace it, and if the new request has
a higher priority than the currently executing request, we write to the
ELSP regardless, thus triggering preemption, but we tell the GPU to
switch to our special preemption context (not the target). In the
context-switch interrupt handler, we know that the previous contexts
have finished execution and so can unwind all the incomplete requests
and compute the new highest priority request to execute.

It would be feasible to avoid the switch-to-idle intermediate by
programming the ELSP with the target context. The difficulty is in
tracking which request that should be whilst maintaining the dependency
change, the error comes in with coalesced requests. As we only track the
most recent request and its priority, we may run into the issue of being
tricked in preempting a high priority request that was followed by a
low priority request from the same context (e.g. for PI); worse still
that earlier request may be our own dependency and the order then broken
by preemption. By injecting the switch-to-idle and then recomputing the
priority queue, we avoid the issue with tracking in-flight coalesced
requests. Having tried the preempt-to-busy approach, and failed to find
a way around the coalesced priority issue, Michal's original proposal to
inject an idle context (based on handling GuC preemption) succeeds.

The current heuristic for deciding when to preempt are only if the new
request is of higher priority, and has the privileged priority of
greater than 0. Note that the scheduler remains unfair!

v2: Disable for gen8 (bdw/bsw) as we need additional w/a for GPGPU.
Since, the feature is now conditional and not always available when we
have a scheduler, make it known via the HAS_SCHEDULER GETPARAM (now a
capability mask).

Suggested-by: Michal Winiarski 
Signed-off-by: Chris Wilson 
Cc: Michal Winiarski 
Cc: Tvrtko Ursulin 
Cc: Arkadiusz Hiler 
Cc: Mika Kuoppala 
Cc: Ben Widawsky 
Cc: Zhenyu Wang 
Cc: Zhi Wang 
---
 drivers/gpu/drm/i915/i915_drv.c |   9 ++-
 drivers/gpu/drm/i915/i915_irq.c |   6 +-
 drivers/gpu/drm/i915/i915_pci.c |   1 +
 drivers/gpu/drm/i915/intel_lrc.c| 129 +---
 drivers/gpu/drm/i915/intel_ringbuffer.h |   2 +
 5 files changed, 113 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index db3438ba92fd..d1949b40f419 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -368,9 +368,16 @@ static int i915_getparam(struct drm_device *dev, void 
*data,
break;
case I915_PARAM_HAS_SCHEDULER:
value = 0;
-   if (dev_priv->engine[RCS] && dev_priv->engine[RCS]->schedule)
+   if (dev_priv->engine[RCS] && dev_priv->engine[RCS]->schedule) {
value |= I915_SCHEDULER_CAP_ENABLED;
+
+   if (INTEL_INFO(dev_priv)->has_logical_ring_preemption &&
+   i915_modparams.enable_execlists &&
+   !i915_modparams.enable_guc_submission)
+   value |= I915_SCHEDULER_CAP_PREEMPTION;
+   }
break;
+
case I915_PARAM_MMAP_VERSION:
/* Remember to bump this if the version changes! */
case I915_PARAM_HAS_GEM:
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 0b7562135d1c..f4bc9ed560b1 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1382,10 +1382,8 @@ gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 
iir, int test_shift)
bool tasklet = false;
 
if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift)) {
-   if (port_count(>port[0])) {
-   __set_bit(ENGINE_IRQ_EXECLIST, >irq_posted);
-   tasklet = true;
-   }
+   __set_bit(ENGINE_IRQ_EXECLIST, >irq_posted);
+   tasklet = true;
}
 
if (iir & (GT_RENDER_USER_INTERRUPT << test_shift)) {
diff --git 

[Intel-gfx] [PATCH v2 02/11] drm/i915/execlists: Cache the last priolist lookup

[Chris Wilson]

From: Michał Winiarski 

Avoid the repeated rbtree lookup for each request as we unwind them by
tracking the last priolist.

v2: Fix up my unhelpful suggestion of using default_priolist.

Signed-off-by: Michał Winiarski 
Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/intel_lrc.c | 20 +---
 1 file changed, 13 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index d67907a7e8e6..3998f359d4f0 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -358,25 +358,31 @@ static void unwind_wa_tail(struct drm_i915_gem_request 
*rq)
 static void unwind_incomplete_requests(struct intel_engine_cs *engine)
 {
struct drm_i915_gem_request *rq, *rn;
+   struct i915_priolist *uninitialized_var(p);
+   int last_prio = INT_MAX;
 
lockdep_assert_held(>timeline->lock);
 
list_for_each_entry_safe_reverse(rq, rn,
 >timeline->requests,
 link) {
-   struct i915_priolist *p;
-
if (i915_gem_request_completed(rq))
return;
 
__i915_gem_request_unsubmit(rq);
unwind_wa_tail(rq);
 
-   p = lookup_priolist(engine,
-   >priotree,
-   rq->priotree.priority);
-   list_add(>priotree.link,
-_mask_bits(p, 1)->requests);
+   GEM_BUG_ON(rq->priotree.priority == INT_MAX);
+   if (rq->priotree.priority != last_prio) {
+   p = lookup_priolist(engine,
+   >priotree,
+   rq->priotree.priority);
+   p = ptr_mask_bits(p, 1);
+
+   last_prio = rq->priotree.priority;
+   }
+
+   list_add(>priotree.link, >requests);
}
 }
 
-- 
2.14.1

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[Intel-gfx] [PATCH v2 04/11] drm/i915/preempt: Default to disabled mid-command preemption levels

[Chris Wilson]

From: Michał Winiarski 

Supporting fine-granularity preemption levels may require changes in
userspace batch buffer programming. Therefore, we need to fallback to
safe default values, rather that use hardware defaults. Userspace is
still able to enable fine-granularity, since we're whitelisting the
register controlling it in WaEnablePreemptionGranularityControlByUMD.

Signed-off-by: Michał Winiarski 
Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_reg.h|  6 ++
 drivers/gpu/drm/i915/intel_engine_cs.c | 17 +
 2 files changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e4c424ba5905..242970a3c185 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6993,6 +6993,12 @@ enum {
 #define GEN9_CS_DEBUG_MODE1_MMIO(0x20ec)
 #define GEN9_CTX_PREEMPT_REG   _MMIO(0x2248)
 #define GEN8_CS_CHICKEN1   _MMIO(0x2580)
+#define GEN9_PREEMPT_3D_OBJECT_LEVEL   (1<<0)
+#define GEN9_PREEMPT_GPGPU_LEVEL(hi, lo)   (((hi) << 2) | ((lo) << 1))
+#define GEN9_PREEMPT_GPGPU_MID_THREAD_LEVELGEN9_PREEMPT_GPGPU_LEVEL(0, 0)
+#define GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL  GEN9_PREEMPT_GPGPU_LEVEL(0, 1)
+#define GEN9_PREEMPT_GPGPU_COMMAND_LEVEL   GEN9_PREEMPT_GPGPU_LEVEL(1, 0)
+#define GEN9_PREEMPT_GPGPU_LEVEL_MASK  GEN9_PREEMPT_GPGPU_LEVEL(1, 1)
 
 /* GEN7 chicken */
 #define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index af3fe494a429..21e037fc21b7 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1071,6 +1071,23 @@ static int gen9_init_workarounds(struct intel_engine_cs 
*engine)
I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
GEN8_LQSC_FLUSH_COHERENT_LINES));
 
+   /* Supporting preemption with fine-granularity requires changes in the
+* batch buffer programming. Since we can't break old userspace, we
+* need to set our default preemption level to safe value. Userspace is
+* still able to use more fine-grained preemption levels, since in
+* WaEnablePreemptionGranularityControlByUMD we're whitelisting the
+* per-ctx register. As such, WaDisableMidCmdPreemption is not a real
+* HW workaround, but merely a way to start using preemption while
+* maintaining old contract with userspace.
+*/
+
+   /* WaDisable3DMidCmdPreemption:skl,bxt,glk,cfl */
+   WA_CLR_BIT_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL);
+
+   /* WaDisableGPGPUMidCmdPreemption:skl,bxt,blk,cfl */
+   WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_GPGPU_LEVEL_MASK,
+   GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
+
/* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */
ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG);
if (ret)
-- 
2.14.1

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[Intel-gfx] [PATCH v2 06/11] drm/i915: Introduce a preempt context

[Chris Wilson]

Add another perma-pinned context for using for preemption at any time.
We cannot just reuse the existing kernel context, as first and foremost
we need to ensure that we can preempt the kernel context itself, so
require a distinct context id. Similar to the kernel context, we may
want to interrupt execution and switch to the preempt context at any
time, and so it needs to be permanently pinned and available.

To compensate for yet another permanent allocation, we shrink the
existing context and the new context by reducing their ringbuffer to the
minimum.

v2: Assert that we never allocate a request from the preemption context.
v3: Limit perma-pin to engines that may preempt.

Signed-off-by: Chris Wilson 
Reviewed-by: Michał Winiarski 
---
 drivers/gpu/drm/i915/i915_drv.h |  4 +++-
 drivers/gpu/drm/i915/i915_gem_context.c | 42 ++---
 drivers/gpu/drm/i915/i915_gem_request.c |  7 ++
 drivers/gpu/drm/i915/intel_engine_cs.c  | 22 +++--
 4 files changed, 64 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b7cba89080ed..b6794b103255 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -783,6 +783,7 @@ struct intel_csr {
func(has_l3_dpf); \
func(has_llc); \
func(has_logical_ring_contexts); \
+   func(has_logical_ring_preemption); \
func(has_overlay); \
func(has_pipe_cxsr); \
func(has_pooled_eu); \
@@ -2250,8 +2251,9 @@ struct drm_i915_private {
wait_queue_head_t gmbus_wait_queue;
 
struct pci_dev *bridge_dev;
-   struct i915_gem_context *kernel_context;
struct intel_engine_cs *engine[I915_NUM_ENGINES];
+   struct i915_gem_context *kernel_context;
+   struct i915_gem_context *preempt_context;
struct i915_vma *semaphore;
 
struct drm_dma_handle *status_page_dmah;
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index 921ee369c74d..1518e110fd04 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -416,14 +416,29 @@ i915_gem_context_create_gvt(struct drm_device *dev)
return ctx;
 }
 
+static struct i915_gem_context *
+create_kernel_context(struct drm_i915_private *i915, int prio)
+{
+   struct i915_gem_context *ctx;
+
+   ctx = i915_gem_create_context(i915, NULL);
+   if (IS_ERR(ctx))
+   return ctx;
+
+   i915_gem_context_clear_bannable(ctx);
+   ctx->priority = prio;
+   ctx->ring_size = PAGE_SIZE;
+
+   return ctx;
+}
+
 int i915_gem_contexts_init(struct drm_i915_private *dev_priv)
 {
struct i915_gem_context *ctx;
 
/* Init should only be called once per module load. Eventually the
 * restriction on the context_disabled check can be loosened. */
-   if (WARN_ON(dev_priv->kernel_context))
-   return 0;
+   GEM_BUG_ON(dev_priv->kernel_context);
 
INIT_LIST_HEAD(_priv->contexts.list);
INIT_WORK(_priv->contexts.free_work, contexts_free_worker);
@@ -441,23 +456,30 @@ int i915_gem_contexts_init(struct drm_i915_private 
*dev_priv)
BUILD_BUG_ON(MAX_CONTEXT_HW_ID > INT_MAX);
ida_init(_priv->contexts.hw_ida);
 
-   ctx = i915_gem_create_context(dev_priv, NULL);
+   /* lowest priority; idle task */
+   ctx = create_kernel_context(dev_priv, I915_PRIORITY_MIN);
if (IS_ERR(ctx)) {
DRM_ERROR("Failed to create default global context (error 
%ld)\n",
  PTR_ERR(ctx));
return PTR_ERR(ctx);
}
 
-   /* For easy recognisablity, we want the kernel context to be 0 and then
+   /*
+* For easy recognisablity, we want the kernel context to be 0 and then
 * all user contexts will have non-zero hw_id.
 */
GEM_BUG_ON(ctx->hw_id);
-
-   i915_gem_context_clear_bannable(ctx);
-   ctx->priority = I915_PRIORITY_MIN; /* lowest priority; idle task */
+   GEM_BUG_ON(!i915_gem_context_is_kernel(ctx));
dev_priv->kernel_context = ctx;
 
-   GEM_BUG_ON(!i915_gem_context_is_kernel(ctx));
+   /* highest priority; preempting task */
+   ctx = create_kernel_context(dev_priv, INT_MAX);
+   if (IS_ERR(ctx)) {
+   DRM_ERROR("Failed to create default preempt context (error 
%ld)\n",
+ PTR_ERR(ctx));
+   return PTR_ERR(ctx);
+   }
+   dev_priv->preempt_context = ctx;
 
DRM_DEBUG_DRIVER("%s context support initialized\n",
 dev_priv->engine[RCS]->context_size ? "logical" :
@@ -517,6 +539,10 @@ void i915_gem_contexts_fini(struct drm_i915_private *i915)
context_close(ctx);
i915_gem_context_free(ctx);
 
+   ctx = i915_gem_context_get(fetch_and_zero(>preempt_context));
+   

[Intel-gfx] [PATCH v2 05/11] drm/i915/execlists: Distinguish the incomplete context notifies

[Chris Wilson]

Let the listener know that the context we just scheduled out was not
complete, and will be scheduled back in at a later point.

v2: Handle CONTEXT_STATUS_PREEMPTED in gvt by aliasing it to
CONTEXT_STATUS_OUT for the moment, gvt can expand upon the difference
later.

Signed-off-by: Chris Wilson 
Cc: "Zhenyu Wang" 
Cc: "Wang, Zhi A" 
Cc: Michał Winiarski 
Cc: Mika Kuoppala 
Cc: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/gvt/scheduler.c | 1 +
 drivers/gpu/drm/i915/intel_lrc.c | 2 +-
 drivers/gpu/drm/i915/intel_lrc.h | 1 +
 3 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c 
b/drivers/gpu/drm/i915/gvt/scheduler.c
index d5892d24f0b6..f6ded475bb2c 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.c
+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
@@ -174,6 +174,7 @@ static int shadow_context_status_change(struct 
notifier_block *nb,
atomic_set(>shadow_ctx_active, 1);
break;
case INTEL_CONTEXT_SCHEDULE_OUT:
+   case INTEL_CONTEXT_SCHEDULE_PREEMPTED:
atomic_set(>shadow_ctx_active, 0);
break;
default:
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 3998f359d4f0..e3d65b49a40d 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -618,7 +618,7 @@ execlist_cancel_port_requests(struct intel_engine_execlists 
*execlists)
while (num_ports-- && port_isset(port)) {
struct drm_i915_gem_request *rq = port_request(port);
 
-   execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_OUT);
+   execlists_context_status_change(rq, 
INTEL_CONTEXT_SCHEDULE_PREEMPTED);
i915_gem_request_put(rq);
 
memset(port, 0, sizeof(*port));
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index 314adee7127a..689fde1a63a9 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -61,6 +61,7 @@
 enum {
INTEL_CONTEXT_SCHEDULE_IN = 0,
INTEL_CONTEXT_SCHEDULE_OUT,
+   INTEL_CONTEXT_SCHEDULE_PREEMPTED,
 };
 
 /* Logical Rings */
-- 
2.14.1

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[Intel-gfx] [PATCH v2 08/11] drm/i915/execlists: Keep request->priority for its lifetime

[Chris Wilson]

With preemption, we will want to "unsubmit" a request, taking it back
from the hw and returning it to the priority sorted execution list. In
order to know where to insert it into that list, we need to remember
its adjust priority (which may change even as it was being executed).

Signed-off-by: Chris Wilson 
Cc: Michal Winiarski 
---
 drivers/gpu/drm/i915/intel_lrc.c | 14 ++
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index e32109265eb9..7ac92a77aea8 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -585,8 +585,6 @@ static void execlists_dequeue(struct intel_engine_cs 
*engine)
}
 
INIT_LIST_HEAD(>priotree.link);
-   rq->priotree.priority = INT_MAX;
-
__i915_gem_request_submit(rq);
trace_i915_gem_request_in(rq, port_index(port, 
execlists));
last = rq;
@@ -794,6 +792,7 @@ static void intel_lrc_irq_handler(unsigned long data)
execlists_context_status_change(rq, 
INTEL_CONTEXT_SCHEDULE_OUT);
 
trace_i915_gem_request_out(rq);
+   rq->priotree.priority = INT_MAX;
i915_gem_request_put(rq);
 
execlists_port_complete(execlists, port);
@@ -846,11 +845,15 @@ static void execlists_submit_request(struct 
drm_i915_gem_request *request)
spin_unlock_irqrestore(>timeline->lock, flags);
 }
 
+static struct drm_i915_gem_request *pt_to_request(struct i915_priotree *pt)
+{
+   return container_of(pt, struct drm_i915_gem_request, priotree);
+}
+
 static struct intel_engine_cs *
 pt_lock_engine(struct i915_priotree *pt, struct intel_engine_cs *locked)
 {
-   struct intel_engine_cs *engine =
-   container_of(pt, struct drm_i915_gem_request, priotree)->engine;
+   struct intel_engine_cs *engine = pt_to_request(pt)->engine;
 
GEM_BUG_ON(!locked);
 
@@ -904,6 +907,9 @@ static void execlists_schedule(struct drm_i915_gem_request 
*request, int prio)
 * engines.
 */
list_for_each_entry(p, >signalers_list, signal_link) {
+   if 
(i915_gem_request_completed(pt_to_request(p->signaler)))
+   continue;
+
GEM_BUG_ON(p->signaler->priority < pt->priority);
if (prio > READ_ONCE(p->signaler->priority))
list_move_tail(>dfs_link, );
-- 
2.14.1

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[Intel-gfx] [PATCH v2 07/11] drm/i915/execlists: Move bdw GPGPU w/a to emit_bb

[Chris Wilson]

Move the re-enabling of MI arbitration from a per-bb w/a buffer to the
emission of the batch buffer itself.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/intel_lrc.c | 24 
 1 file changed, 4 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index e3d65b49a40d..e32109265eb9 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1157,24 +1157,6 @@ static u32 *gen8_init_indirectctx_bb(struct 
intel_engine_cs *engine, u32 *batch)
return batch;
 }
 
-/*
- *  This batch is started immediately after indirect_ctx batch. Since we ensure
- *  that indirect_ctx ends on a cacheline this batch is aligned automatically.
- *
- *  The number of DWORDS written are returned using this field.
- *
- *  This batch is terminated with MI_BATCH_BUFFER_END and so we need not add 
padding
- *  to align it with cacheline as padding after MI_BATCH_BUFFER_END is 
redundant.
- */
-static u32 *gen8_init_perctx_bb(struct intel_engine_cs *engine, u32 *batch)
-{
-   /* WaDisableCtxRestoreArbitration:bdw,chv */
-   *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
-   *batch++ = MI_BATCH_BUFFER_END;
-
-   return batch;
-}
-
 static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 
*batch)
 {
/* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */
@@ -1289,7 +1271,7 @@ static int intel_init_workaround_bb(struct 
intel_engine_cs *engine)
break;
case 8:
wa_bb_fn[0] = gen8_init_indirectctx_bb;
-   wa_bb_fn[1] = gen8_init_perctx_bb;
+   wa_bb_fn[1] = NULL;
break;
default:
MISSING_CASE(INTEL_GEN(engine->i915));
@@ -1533,13 +1515,15 @@ static int gen8_emit_bb_start(struct 
drm_i915_gem_request *req,
if (IS_ERR(cs))
return PTR_ERR(cs);
 
+   /* WaDisableCtxRestoreArbitration:bdw,chv */
+   *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
+
/* FIXME(BDW): Address space and security selectors. */
*cs++ = MI_BATCH_BUFFER_START_GEN8 |
(flags & I915_DISPATCH_SECURE ? 0 : BIT(8)) |
(flags & I915_DISPATCH_RS ? MI_BATCH_RESOURCE_STREAMER : 0);
*cs++ = lower_32_bits(offset);
*cs++ = upper_32_bits(offset);
-   *cs++ = MI_NOOP;
intel_ring_advance(req, cs);
 
return 0;
-- 
2.14.1

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[Intel-gfx] [PATCH v2 09/11] drm/i915: Expand I915_PARAM_HAS_SCHEDULER into a capability bitmask

[Chris Wilson]

In the next few patches, we wish to enable different features for the
scheduler, some which may subtlety change ABI (e.g. allow requests to be
reordered under different circumstances). So we need to make sure
userspace is cognizant of the changes (if they care), by which we employ
the usual method of a GETPARAM. We already have an
I915_PARAM_HAS_SCHEDULER (which notes the existing ability to reorder
requests to avoid bubbles), and now we wish to extend that to be a
bitmask to describe the different capabilities implemented.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_drv.c | 5 +++--
 include/uapi/drm/i915_drm.h | 9 -
 2 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 7056bb299dc6..db3438ba92fd 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -367,8 +367,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
value = i915_gem_mmap_gtt_version();
break;
case I915_PARAM_HAS_SCHEDULER:
-   value = dev_priv->engine[RCS] &&
-   dev_priv->engine[RCS]->schedule;
+   value = 0;
+   if (dev_priv->engine[RCS] && dev_priv->engine[RCS]->schedule)
+   value |= I915_SCHEDULER_CAP_ENABLED;
break;
case I915_PARAM_MMAP_VERSION:
/* Remember to bump this if the version changes! */
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index fe25a01c81f2..aa4a3b20ef6b 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -397,10 +397,17 @@ typedef struct drm_i915_irq_wait {
 #define I915_PARAM_MIN_EU_IN_POOL   39
 #define I915_PARAM_MMAP_GTT_VERSION 40
 
-/* Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution
+/*
+ * Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution
  * priorities and the driver will attempt to execute batches in priority order.
+ * The param returns a capability bitmask, nonzero implies that the scheduler
+ * is enabled, with different features present according to the mask.
  */
 #define I915_PARAM_HAS_SCHEDULER41
+#define   I915_SCHEDULER_CAP_ENABLED   (1ul << 0)
+#define   I915_SCHEDULER_CAP_PRIORITY  (1ul << 1)
+#define   I915_SCHEDULER_CAP_PREEMPTION(1ul << 2)
+
 #define I915_PARAM_HUC_STATUS   42
 
 /* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to opt-out of
-- 
2.14.1

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[Intel-gfx] [PATCH v2 11/11] drm/i915/scheduler: Support user-defined priorities

[Chris Wilson]

Use a priority stored in the context as the initial value when
submitting a request. This allows us to change the default priority on a
per-context basis, allowing different contexts to be favoured with GPU
time at the expense of lower importance work. The user can adjust the
context's priority via I915_CONTEXT_PARAM_PRIORITY, with more positive
values being higher priority (they will be serviced earlier, after their
dependencies have been resolved). Any prerequisite work for an execbuf
will have its priority raised to match the new request as required.

Normal users can specify any value in the range of -1023 to 0 [default],
i.e. they can reduce the priority of their workloads (and temporarily
boost it back to normal if so desired).

Privileged users can specify any value in the range of -1023 to 1023,
[default is 0], i.e. they can raise their priority above all overs and
so potentially starve the system.

Note that the existing schedulers are not fair, nor load balancing, the
execution is strictly by priority on a first-come, first-served basis,
and the driver may choose to boost some requests above the range
available to users.

This priority was originally based around nice(2), but evolved to allow
clients to adjust their priority within a small range, and allow for a
privileged high priority range.

For example, this can be used to implement EGL_IMG_context_priority
https://www.khronos.org/registry/egl/extensions/IMG/EGL_IMG_context_priority.txt

EGL_CONTEXT_PRIORITY_LEVEL_IMG determines the priority level of
the context to be created. This attribute is a hint, as an
implementation may not support multiple contexts at some
priority levels and system policy may limit access to high
priority contexts to appropriate system privilege level. The
default value for EGL_CONTEXT_PRIORITY_LEVEL_IMG is
EGL_CONTEXT_PRIORITY_MEDIUM_IMG."

so we can map

PRIORITY_HIGH -> 1023 [privileged, will failback to 0]
PRIORITY_MED -> 0 [default]
PRIORITY_LOW -> -1023

They also map onto the priorities used by VkQueue (and a VkQueue is
essentially a timeline, our i915_gem_context under full-ppgtt).

v2: s/CAP_SYS_ADMIN/CAP_SYS_NICE/
v3: Report min/max user priorities as defines in the uapi, and rebase
internal priorities on the exposed values.

Testcase: igt/gem_exec_schedule
Signed-off-by: Chris Wilson 
Reviewed-by: Tvrtko Ursulin 
---
 drivers/gpu/drm/i915/i915_drv.c |  1 +
 drivers/gpu/drm/i915/i915_gem_context.c | 23 +++
 drivers/gpu/drm/i915/i915_gem_request.h | 11 ---
 include/uapi/drm/i915_drm.h |  7 +++
 4 files changed, 39 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index d1949b40f419..3bdae56b1b8d 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -370,6 +370,7 @@ static int i915_getparam(struct drm_device *dev, void *data,
value = 0;
if (dev_priv->engine[RCS] && dev_priv->engine[RCS]->schedule) {
value |= I915_SCHEDULER_CAP_ENABLED;
+   value |= I915_SCHEDULER_CAP_PRIORITY;
 
if (INTEL_INFO(dev_priv)->has_logical_ring_preemption &&
i915_modparams.enable_execlists &&
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index 1518e110fd04..08cac18da622 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -1062,6 +1062,9 @@ int i915_gem_context_getparam_ioctl(struct drm_device 
*dev, void *data,
case I915_CONTEXT_PARAM_BANNABLE:
args->value = i915_gem_context_is_bannable(ctx);
break;
+   case I915_CONTEXT_PARAM_PRIORITY:
+   args->value = ctx->priority;
+   break;
default:
ret = -EINVAL;
break;
@@ -1117,6 +1120,26 @@ int i915_gem_context_setparam_ioctl(struct drm_device 
*dev, void *data,
else
i915_gem_context_clear_bannable(ctx);
break;
+
+   case I915_CONTEXT_PARAM_PRIORITY:
+   {
+   int priority = args->value;
+
+   if (args->size)
+   ret = -EINVAL;
+   else if (!to_i915(dev)->engine[RCS]->schedule)
+   ret = -ENODEV;
+   else if (priority > I915_CONTEXT_MAX_USER_PRIORITY ||
+priority < I915_CONTEXT_MIN_USER_PRIORITY)
+   ret = -EINVAL;
+   else if (priority > I915_CONTEXT_DEFAULT_PRIORITY &&
+!capable(CAP_SYS_NICE))
+   ret = -EPERM;
+   else
+  

Re: [Intel-gfx] [PATCH v10 9/9] drm/i915/guc: Fix GuC cleanup in unload path

[Sagar Arun Kamble]

On 9/27/2017 10:41 PM, Michal Wajdeczko wrote:
On Wed, 27 Sep 2017 11:30:39 +0200, Sagar Arun Kamble 
 wrote:



We ensure that GuC is completely suspended and client is destroyed
in i915_gem_suspend during i915_driver_unload. So now intel_uc_fini_hw
should just take care of cleanup,
hence s/intel_uc_fini_hw/intel_uc_cleanup. Correspondingly
we also updated as 
s/i915_guc_submission_fini/i915_guc_submission_cleanup

Other functionality to disable communication, disable interrupts and
update of ggtt.invalidate is taken care by intel_uc_suspend.

v2: Rebase w.r.t removal of GuC code restructuring.

v3: Removed intel_guc_cleanup. (Michal Wajdeczko)

v4: guc_free_load_err_log() needs to be called without checking
i915.enable_guc_loading as this param is cleared on GuC load failure.
(Michal Wajdeczko)

Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Michał Winiarski 
Reviewed-by: Michal Wajdeczko 
---
 drivers/gpu/drm/i915/i915_drv.c    |  2 +-
 drivers/gpu/drm/i915/i915_guc_submission.c |  2 +-
 drivers/gpu/drm/i915/intel_uc.c    | 14 --
 drivers/gpu/drm/i915/intel_uc.h    |  4 ++--
 4 files changed, 8 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c 
b/drivers/gpu/drm/i915/i915_drv.c

index f79646b..4223cee 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -603,7 +603,7 @@ static void i915_gem_fini(struct drm_i915_private 
*dev_priv)

 i915_gem_drain_workqueue(dev_priv);
mutex_lock(_priv->drm.struct_mutex);
-    intel_uc_fini_hw(dev_priv);
+    intel_uc_cleanup(dev_priv);
 i915_gem_cleanup_engines(dev_priv);
 i915_gem_contexts_fini(dev_priv);
 i915_gem_cleanup_userptr(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
b/drivers/gpu/drm/i915/i915_guc_submission.c

index 45f2ee8..0ac9bd4 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -1053,7 +1053,7 @@ int i915_guc_submission_init(struct 
drm_i915_private *dev_priv)

 return ret;
 }
-void i915_guc_submission_fini(struct drm_i915_private *dev_priv)
+void i915_guc_submission_cleanup(struct drm_i915_private *dev_priv)
 {
 struct intel_guc *guc = _priv->guc;
diff --git a/drivers/gpu/drm/i915/intel_uc.c 
b/drivers/gpu/drm/i915/intel_uc.c

index 59e6995..0370265 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -439,7 +439,7 @@ int intel_uc_init_hw(struct drm_i915_private 
*dev_priv)

 guc_capture_load_err_log(guc);
 err_submission:
 if (i915_modparams.enable_guc_submission)
-    i915_guc_submission_fini(dev_priv);
+    i915_guc_submission_cleanup(dev_priv);
 err_guc:
 i915_ggtt_disable_guc(dev_priv);
@@ -461,21 +461,15 @@ int intel_uc_init_hw(struct drm_i915_private 
*dev_priv)

 return ret;
 }
-void intel_uc_fini_hw(struct drm_i915_private *dev_priv)
+void intel_uc_cleanup(struct drm_i915_private *dev_priv)
 {
 guc_free_load_err_log(_priv->guc);
if (!i915_modparams.enable_guc_loading)
 return;
-    guc_disable_communication(_priv->guc);
-
-    if (i915_modparams.enable_guc_submission) {
-    gen9_disable_guc_interrupts(dev_priv);
-    i915_guc_submission_fini(dev_priv);
-    }
-
-    i915_ggtt_disable_guc(dev_priv);
+    if (i915_modparams.enable_guc_submission)


In patch 6/9 you said we should avoid looking at user params
but here you're still using it ...

Yes. I thought of taking that up in new series. Should I add another 
patch in this series itself to update such snippets?



+ i915_guc_submission_cleanup(dev_priv);
 }
/**
diff --git a/drivers/gpu/drm/i915/intel_uc.h 
b/drivers/gpu/drm/i915/intel_uc.h

index 78ccbd9..838a364 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -207,7 +207,7 @@ struct intel_huc {
 void intel_uc_init_fw(struct drm_i915_private *dev_priv);
 void intel_uc_fini_fw(struct drm_i915_private *dev_priv);
 int intel_uc_init_hw(struct drm_i915_private *dev_priv);
-void intel_uc_fini_hw(struct drm_i915_private *dev_priv);
+void intel_uc_cleanup(struct drm_i915_private *dev_priv);
 int intel_uc_runtime_suspend(struct drm_i915_private *dev_priv);
 int intel_uc_runtime_resume(struct drm_i915_private *dev_priv);
 int intel_uc_suspend(struct drm_i915_private *dev_priv);
@@ -239,7 +239,7 @@ static inline void intel_guc_notify(struct 
intel_guc *guc)

 int i915_guc_submission_init(struct drm_i915_private *dev_priv);
 int i915_guc_submission_enable(struct drm_i915_private *dev_priv);
 void i915_guc_submission_disable(struct drm_i915_private *dev_priv);
-void i915_guc_submission_fini(struct drm_i915_private *dev_priv);
+void i915_guc_submission_cleanup(struct drm_i915_private *dev_priv);
 struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 
size);

/* 

[Intel-gfx] [PATCH v2 01/11] drm/i915/execlists: Move request unwinding to a separate function

[Chris Wilson]

In the future, we will want to unwind requests following a preemption
point. This requires the same steps as for unwinding upon a reset, so
extract the existing code to a separate function for later use.

Signed-off-by: Chris Wilson 
Reviewed-by: Mika Kuoppala 
---
 drivers/gpu/drm/i915/intel_lrc.c | 54 +---
 1 file changed, 34 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 61cac26a8b05..d67907a7e8e6 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -348,6 +348,38 @@ lookup_priolist(struct intel_engine_cs *engine,
return ptr_pack_bits(p, first, 1);
 }
 
+static void unwind_wa_tail(struct drm_i915_gem_request *rq)
+{
+   rq->tail = intel_ring_wrap(rq->ring,
+  rq->wa_tail - WA_TAIL_DWORDS*sizeof(u32));
+   assert_ring_tail_valid(rq->ring, rq->tail);
+}
+
+static void unwind_incomplete_requests(struct intel_engine_cs *engine)
+{
+   struct drm_i915_gem_request *rq, *rn;
+
+   lockdep_assert_held(>timeline->lock);
+
+   list_for_each_entry_safe_reverse(rq, rn,
+>timeline->requests,
+link) {
+   struct i915_priolist *p;
+
+   if (i915_gem_request_completed(rq))
+   return;
+
+   __i915_gem_request_unsubmit(rq);
+   unwind_wa_tail(rq);
+
+   p = lookup_priolist(engine,
+   >priotree,
+   rq->priotree.priority);
+   list_add(>priotree.link,
+_mask_bits(p, 1)->requests);
+   }
+}
+
 static inline void
 execlists_context_status_change(struct drm_i915_gem_request *rq,
unsigned long status)
@@ -1382,7 +1414,6 @@ static void reset_common_ring(struct intel_engine_cs 
*engine,
  struct drm_i915_gem_request *request)
 {
struct intel_engine_execlists * const execlists = >execlists;
-   struct drm_i915_gem_request *rq, *rn;
struct intel_context *ce;
unsigned long flags;
 
@@ -1400,21 +1431,7 @@ static void reset_common_ring(struct intel_engine_cs 
*engine,
execlist_cancel_port_requests(execlists);
 
/* Push back any incomplete requests for replay after the reset. */
-   list_for_each_entry_safe_reverse(rq, rn,
->timeline->requests, link) {
-   struct i915_priolist *p;
-
-   if (i915_gem_request_completed(rq))
-   break;
-
-   __i915_gem_request_unsubmit(rq);
-
-   p = lookup_priolist(engine,
-   >priotree,
-   rq->priotree.priority);
-   list_add(>priotree.link,
-_mask_bits(p, 1)->requests);
-   }
+   unwind_incomplete_requests(engine);
 
spin_unlock_irqrestore(>timeline->lock, flags);
 
@@ -1451,10 +1468,7 @@ static void reset_common_ring(struct intel_engine_cs 
*engine,
intel_ring_update_space(request->ring);
 
/* Reset WaIdleLiteRestore:bdw,skl as well */
-   request->tail =
-   intel_ring_wrap(request->ring,
-   request->wa_tail - WA_TAIL_DWORDS*sizeof(u32));
-   assert_ring_tail_valid(request->ring, request->tail);
+   unwind_wa_tail(request);
 }
 
 static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
-- 
2.14.1

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[Intel-gfx] [PATCH v2 03/11] drm/i915/preempt: Fix WaEnablePreemptionGranularityControlByUMD

[Chris Wilson]

From: Jeff McGee 

The WA applies to all production Gen9 and requires both enabling and
whitelisting of the per-context preemption control register.

Signed-off-by: Jeff McGee 
Signed-off-by: Michał Winiarski 
Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/intel_engine_cs.c | 12 +++-
 1 file changed, 3 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index a28e2a864cf1..af3fe494a429 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1077,7 +1077,9 @@ static int gen9_init_workarounds(struct intel_engine_cs 
*engine)
return ret;
 
/* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl */
-   ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
+   I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
+  _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
+   ret = wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
if (ret)
return ret;
 
@@ -1139,14 +1141,6 @@ static int skl_init_workarounds(struct intel_engine_cs 
*engine)
if (ret)
return ret;
 
-   /*
-* Actual WA is to disable percontext preemption granularity control
-* until D0 which is the default case so this is equivalent to
-* !WaDisablePerCtxtPreemptionGranularityControl:skl
-*/
-   I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
-  _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
-
/* WaEnableGapsTsvCreditFix:skl */
I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
   GEN9_GAPS_TSV_CREDIT_DISABLE));
-- 
2.14.1

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[Intel-gfx] Execlists preemption & user priority

[Chris Wilson]

Some refinement from the earlier version, as Michal pointed some
workarounds we needed to prevent an obstructive break in ABI.
Preemption granularity affects how userspace should consider building
batches, so we need to match sure that as we switch preemption on, the
granulatity doesn't change. Sadly, this means we can't enable preemption
on BDW/BSW unconditionally. At least not at this time.

The usecase for this naked series is to enable preemption for pageflips.
It is also exposed to userspace via a context priority, but we reserve
for CAP_SYS_NICE processes for now as we have a very, very raw and
unfair scheduler. But it should enable display servers to squeeze that
last bit of vblank goodness out of the system.
-Chris

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Re: [Intel-gfx] [PATCH v10 3/9] drm/i915: Create uC runtime and system suspend/resume helpers

[Michal Wajdeczko]

On Wed, 27 Sep 2017 11:30:33 +0200, Sagar Arun Kamble  
 wrote:



Prepared generic helpers intel_uc_suspend, intel_uc_resume,
intel_uc_runtime_suspend, intel_uc_runtime_resume. These are
called from respective GEM functions.
Only exception is intel_uc_resume that needs to be called
w/ or w/o GuC loaded in i915_drm_resume path. Changes to
add WOPCM condition check to load GuC during resume will be added
in later patches.

v2: Rebase w.r.t removal of GuC code restructuring.

v3: Calling intel_uc_resume from i915_gem_resume post resuming
i915 gem setup. This is symmetrical with i915_gem_suspend.
Removed error messages from i915 suspend/resume routines as
uC suspend/resume routines will have those. (Michal Wajdeczko)
Declare wedged on uc_suspend failure and uc_resume failure.
(Michał Winiarski)
Keeping the uC suspend/resume function definitions close to other
uC functions.

v4: Added implementation to intel_uc_resume as GuC resume is
needed to be triggered post reloading the firmware as well. Added
comments about semantics of GuC resume with the firmware reload.

Signed-off-by: Sagar Arun Kamble 
Cc: Chris Wilson 
Cc: Michal Wajdeczko 
Cc: Michał Winiarski 
---
 drivers/gpu/drm/i915/i915_drv.c | 10 ++
 drivers/gpu/drm/i915/i915_gem.c | 36  


 drivers/gpu/drm/i915/intel_uc.c | 20 
 drivers/gpu/drm/i915/intel_uc.h |  4 
 4 files changed, 62 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c  
b/drivers/gpu/drm/i915/i915_drv.c

index 174a7c5..f79646b 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1698,6 +1698,16 @@ static int i915_drm_resume(struct drm_device *dev)
}
mutex_unlock(>struct_mutex);
+   /*
+* NB: Currently we know that at the end of suspend we have done Full
+* GPU reset, Hence GuC is loaded again during i915_gem_init_hw.
+* Now, send action to GuC to resume back again as earlier call to
+* intel_uc_resume from i915_gem_resume would have done nothing.
+*/
+   ret = intel_uc_resume(dev_priv);
+   if (ret)
+   i915_gem_set_wedged(dev_priv);
+
intel_modeset_init_hw(dev);
spin_lock_irq(_priv->irq_lock);
diff --git a/drivers/gpu/drm/i915/i915_gem.c  
b/drivers/gpu/drm/i915/i915_gem.c

index 11922af..c54c9b4 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2025,9 +2025,11 @@ int i915_gem_fault(struct vm_fault *vmf)
 int i915_gem_runtime_suspend(struct drm_i915_private *dev_priv)
 {
struct drm_i915_gem_object *obj, *on;
-   int i;
+   int i, ret;
-   intel_guc_suspend(dev_priv);
+   ret = intel_uc_runtime_suspend(dev_priv);
+   if (ret)
+   return ret;
/*
 * Only called during RPM suspend. All users of the userfault_list
@@ -2068,7 +2070,7 @@ int i915_gem_runtime_suspend(struct  
drm_i915_private *dev_priv)

reg->dirty = true;
}
-   return 0;
+   return ret;


Hmm, at this point we know that we didn't fail, so return 0 was fine.


 }
void i915_gem_runtime_resume(struct drm_i915_private *dev_priv)
@@ -2080,7 +2082,7 @@ void i915_gem_runtime_resume(struct  
drm_i915_private *dev_priv)

i915_gem_init_swizzling(dev_priv);
i915_gem_restore_fences(dev_priv);
-   intel_guc_resume(dev_priv);
+   intel_uc_runtime_resume(dev_priv);
 }
static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object  
*obj)
@@ -4571,7 +4573,9 @@ int i915_gem_suspend(struct drm_i915_private  
*dev_priv)

if (WARN_ON(!intel_engines_are_idle(dev_priv)))
i915_gem_set_wedged(dev_priv); /* no hope, discard everything */
-   intel_guc_suspend(dev_priv);
+   ret = intel_uc_suspend(dev_priv);
+   if (ret)
+   i915_gem_set_wedged(dev_priv); /* no hope, discard everything */
/*
 * Neither the BIOS, ourselves or any other kernel
@@ -4606,6 +4610,7 @@ int i915_gem_suspend(struct drm_i915_private  
*dev_priv)

 int i915_gem_resume(struct drm_i915_private *dev_priv)
 {
struct drm_device *dev = _priv->drm;
+   int ret;
WARN_ON(dev_priv->gt.awake);
@@ -4618,10 +4623,20 @@ int i915_gem_resume(struct drm_i915_private  
*dev_priv)

 * it and start again.
 */
dev_priv->gt.resume(dev_priv);
-   intel_guc_resume(dev_priv);
+
+   /*
+* NB: At the end of suspend, Full GPU reset is being done which
+* wipes/unloads the GuC firmware. If reset is avoided there, we can
+* check the WOPCM status here to see if GuC is still loaded and just
+* do GuC resume without reloading the firmware back.
+*/
+   ret = intel_uc_resume(dev_priv);
+   if (ret)
+   

[Intel-gfx] ✗ Fi.CI.IGT: failure for igt: Add a testsuite to validate VC4 MADV ioctl

[Patchwork]

== Series Details ==

Series: igt: Add a testsuite to validate VC4 MADV ioctl
URL   : https://patchwork.freedesktop.org/series/30959/
State : failure

== Summary ==

Test kms_draw_crc:
Subgroup draw-method-xrgb-render-xtiled:
skip   -> PASS   (shard-hsw)
Subgroup draw-method-xrgb-blt-xtiled:
skip   -> PASS   (shard-hsw)
Subgroup fill-fb:
skip   -> PASS   (shard-hsw)
Subgroup draw-method-xrgb2101010-pwrite-untiled:
fail   -> PASS   (shard-hsw)
Subgroup draw-method-rgb565-render-untiled:
pass   -> SKIP   (shard-hsw)
Subgroup draw-method-xrgb2101010-pwrite-ytiled:
pass   -> SKIP   (shard-hsw)
Subgroup draw-method-rgb565-pwrite-xtiled:
skip   -> PASS   (shard-hsw)
Subgroup draw-method-rgb565-blt-ytiled:
pass   -> SKIP   (shard-hsw)
Subgroup draw-method-xrgb2101010-mmap-cpu-ytiled:
pass   -> SKIP   (shard-hsw)
Subgroup draw-method-rgb565-mmap-gtt-ytiled:
pass   -> SKIP   (shard-hsw)
Subgroup draw-method-xrgb-mmap-wc-xtiled:
skip   -> PASS   (shard-hsw)
Subgroup draw-method-xrgb2101010-mmap-gtt-untiled:
skip   -> PASS   (shard-hsw)
Subgroup draw-method-xrgb-render-untiled:
skip   -> PASS   (shard-hsw)
Subgroup draw-method-xrgb2101010-mmap-wc-untiled:
skip   -> PASS   (shard-hsw)
Subgroup draw-method-rgb565-mmap-wc-ytiled:
pass   -> SKIP   (shard-hsw)
Subgroup draw-method-rgb565-mmap-cpu-xtiled:
skip   -> PASS   (shard-hsw)
Subgroup draw-method-xrgb-mmap-wc-untiled:
skip   -> PASS   (shard-hsw)
Subgroup draw-method-xrgb2101010-mmap-cpu-untiled:
skip   -> PASS   (shard-hsw)
Subgroup draw-method-xrgb-render-ytiled:
pass   -> SKIP   (shard-hsw)
Subgroup draw-method-xrgb2101010-mmap-wc-ytiled:
pass   -> SKIP   (shard-hsw)
Subgroup draw-method-rgb565-pwrite-ytiled:
pass   -> SKIP   (shard-hsw)
Subgroup draw-method-rgb565-mmap-cpu-untiled:
skip   -> PASS   (shard-hsw)
Subgroup draw-method-rgb565-mmap-wc-untiled:
skip   -> PASS   (shard-hsw)
Subgroup draw-method-xrgb2101010-blt-ytiled:
pass   -> SKIP   (shard-hsw)
Subgroup draw-method-rgb565-render-xtiled:
pass   -> SKIP   (shard-hsw)
Subgroup draw-method-xrgb-mmap-wc-ytiled:
pass   -> SKIP   (shard-hsw)
Subgroup draw-method-xrgb-blt-ytiled:
pass   -> SKIP   (shard-hsw)
Subgroup draw-method-xrgb2101010-blt-xtiled:
skip   -> PASS   (shard-hsw)
Subgroup draw-method-xrgb-pwrite-ytiled:
pass   -> SKIP   (shard-hsw)
Subgroup draw-method-xrgb2101010-mmap-cpu-xtiled:
skip   -> PASS   (shard-hsw)
Test kms_frontbuffer_tracking:
Subgroup psr-rgb101010-draw-mmap-gtt:
pass   -> SKIP   (shard-hsw)
Subgroup fbcpsr-2p-primscrn-spr-indfb-draw-blt:
pass   -> SKIP   (shard-hsw)
Subgroup fbcpsr-2p-scndscrn-shrfb-plflip-blt:
pass   -> SKIP   (shard-hsw)
Subgroup psr-2p-scndscrn-spr-indfb-draw-blt:
pass   -> SKIP   (shard-hsw)
Subgroup fbc-1p-primscrn-pri-shrfb-draw-render:
skip   -> PASS   (shard-hsw)
Subgroup psr-2p-scndscrn-indfb-msflip-blt:
pass   -> SKIP   (shard-hsw)
Subgroup fbc-1p-primscrn-pri-shrfb-draw-mmap-cpu:
skip   -> PASS   (shard-hsw)
Subgroup fbc-2p-scndscrn-spr-indfb-draw-render:
pass   -> SKIP   (shard-hsw)
Subgroup psr-2p-primscrn-shrfb-pgflip-blt:
pass   -> SKIP   (shard-hsw)
Subgroup fbc-2p-primscrn-spr-indfb-move:
pass   -> SKIP   (shard-hsw)
Subgroup fbcpsr-1p-primscrn-spr-indfb-fullscreen:
pass   -> SKIP   (shard-hsw)
Subgroup fbcpsr-rgb565-draw-mmap-cpu:
pass   -> SKIP   (shard-hsw)
Subgroup fbc-2p-scndscrn-cur-indfb-draw-mmap-gtt:
pass   -> SKIP   (shard-hsw)
Subgroup fbcpsr-1p-primscrn-spr-indfb-draw-mmap-cpu:
pass   -> SKIP   (shard-hsw)
Subgroup fbcpsr-2p-scndscrn-spr-indfb-onoff:
pass   -> SKIP   (shard-hsw)

Re: [Intel-gfx] [PATCH v10 2/9] drm/i915: Update GEM suspend/resume flows considering GuC and GEM fences

[Sagar Arun Kamble]

On 9/27/2017 9:17 PM, Michal Wajdeczko wrote:
On Wed, 27 Sep 2017 11:30:32 +0200, Sagar Arun Kamble 
 wrote:


This patch moves GuC suspend/resume handlers to corresponding GEM 
handlers

and orders them properly in the runtime and system suspend/resume flows.
i915_gem_restore_fences is GEM resumption task hence it is moved to
i915_gem_resume from i915_restore_state.

v2: Removed documentation of suspend/resume handlers as those are not
interfaces and are just hooks. (Chris)

Signed-off-by: Sagar Arun Kamble 
Cc: Chris Wilson 
Cc: Imre Deak 
Cc: Paulo Zanoni 
Cc: Rodrigo Vivi 
Cc: Michal Wajdeczko 
Cc: Michał Winiarski 
---
 drivers/gpu/drm/i915/i915_drv.c |  7 ---
 drivers/gpu/drm/i915/i915_gem.c | 11 ---
 drivers/gpu/drm/i915/i915_suspend.c |  2 --
 3 files changed, 8 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c 
b/drivers/gpu/drm/i915/i915_drv.c

index d0a710d..174a7c5 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1698,8 +1698,6 @@ static int i915_drm_resume(struct drm_device *dev)
 }
 mutex_unlock(>struct_mutex);
-    intel_guc_resume(dev_priv);
-
 intel_modeset_init_hw(dev);
spin_lock_irq(_priv->irq_lock);
@@ -2504,8 +2502,6 @@ static int intel_runtime_suspend(struct device 
*kdev)

 return ret;
 }
-    intel_guc_suspend(dev_priv);
-
 intel_runtime_pm_disable_interrupts(dev_priv);
ret = 0;
@@ -2522,7 +2518,6 @@ static int intel_runtime_suspend(struct device 
*kdev)

 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
 intel_runtime_pm_enable_interrupts(dev_priv);
-    intel_guc_resume(dev_priv);
 i915_gem_runtime_resume(dev_priv);
 enable_rpm_wakeref_asserts(dev_priv);
@@ -2591,8 +2586,6 @@ static int intel_runtime_resume(struct device 
*kdev)

 if (intel_uncore_unclaimed_mmio(dev_priv))
 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
-    intel_guc_resume(dev_priv);
-
 if (IS_GEN9_LP(dev_priv)) {
 bxt_disable_dc9(dev_priv);
 bxt_display_core_init(dev_priv, true);
diff --git a/drivers/gpu/drm/i915/i915_gem.c 
b/drivers/gpu/drm/i915/i915_gem.c

index 59a88f2..11922af 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2027,6 +2027,8 @@ int i915_gem_runtime_suspend(struct 
drm_i915_private *dev_priv)

 struct drm_i915_gem_object *obj, *on;
 int i;
+    intel_guc_suspend(dev_priv);
+
 /*
  * Only called during RPM suspend. All users of the userfault_list
  * must be holding an RPM wakeref to ensure that this can not
@@ -2077,6 +2079,8 @@ void i915_gem_runtime_resume(struct 
drm_i915_private *dev_priv)

  */
 i915_gem_init_swizzling(dev_priv);
 i915_gem_restore_fences(dev_priv);
+
+    intel_guc_resume(dev_priv);
 }
static int i915_gem_object_create_mmap_offset(struct 
drm_i915_gem_object *obj)
@@ -4551,8 +4555,6 @@ int i915_gem_suspend(struct drm_i915_private 
*dev_priv)

 i915_gem_contexts_lost(dev_priv);
 mutex_unlock(>struct_mutex);
-    intel_guc_suspend(dev_priv);
-
cancel_delayed_work_sync(_priv->gpu_error.hangcheck_work);
 cancel_delayed_work_sync(_priv->gt.retire_work);
@@ -4569,6 +4571,8 @@ int i915_gem_suspend(struct drm_i915_private 
*dev_priv)

 if (WARN_ON(!intel_engines_are_idle(dev_priv)))
 i915_gem_set_wedged(dev_priv); /* no hope, discard 
everything */

+    intel_guc_suspend(dev_priv);
+
 /*
  * Neither the BIOS, ourselves or any other kernel
  * expects the system to be in execlists mode on startup,
@@ -4607,13 +4611,14 @@ int i915_gem_resume(struct drm_i915_private 
*dev_priv)

mutex_lock(>struct_mutex);
 i915_gem_restore_gtt_mappings(dev_priv);
+    i915_gem_restore_fences(dev_priv);
/* As we didn't flush the kernel context before suspend, we cannot
  * guarantee that the context image is complete. So let's just 
reset

  * it and start again.
  */
 dev_priv->gt.resume(dev_priv);
-


I would leave that empty line

Sure. Will update.



+    intel_guc_resume(dev_priv);
 mutex_unlock(>struct_mutex);
return 0;
diff --git a/drivers/gpu/drm/i915/i915_suspend.c 
b/drivers/gpu/drm/i915/i915_suspend.c

index 5c86925a..8f3aa4d 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -108,8 +108,6 @@ int i915_restore_state(struct drm_i915_private 
*dev_priv)

mutex_lock(_priv->drm.struct_mutex);
-    i915_gem_restore_fences(dev_priv);
-


And this move of i915_gem_restore_fences() can likely be in separate 
patch


Michal

Ok. Will create separate patch.



 if (IS_GEN4(dev_priv))
 pci_write_config_word(pdev, GCDGMBUS,
   dev_priv->regfile.saveGCDGMBUS);

Re: [Intel-gfx] [PATCH v10 1/9] drm/i915: Create GEM runtime resume helper and handle GEM suspend/resume errors

[Sagar Arun Kamble]

On 9/27/2017 9:11 PM, Michal Wajdeczko wrote:
On Wed, 27 Sep 2017 11:30:31 +0200, Sagar Arun Kamble 
 wrote:



These changes are preparation to handle GuC suspend/resume. Prepared
helper i915_gem_runtime_resume to reinitialize suspended gem setup.
Returning status from i915_gem_runtime_suspend and i915_gem_resume.
This will be placeholder for handling any errors from uC suspend/resume
in upcoming patches. Restructured the suspend/resume routines w.r.t 
setup

creation and rollback order.
This also fixes issue of ordering of i915_gem_runtime_resume with
intel_runtime_pm_enable_interrupts.

v2: Fixed return from intel_runtime_resume. (Michał Winiarski)

v3: Not returning status from gem_runtime_resume. (Chris)

Signed-off-by: Sagar Arun Kamble 
Cc: Chris Wilson 
Cc: Imre Deak 
Cc: Paulo Zanoni 
Cc: Rodrigo Vivi 
Cc: Michal Wajdeczko 
Cc: Michał Winiarski 
---
 drivers/gpu/drm/i915/i915_drv.c | 22 +-
 drivers/gpu/drm/i915/i915_drv.h |  5 +++--
 drivers/gpu/drm/i915/i915_gem.c | 18 --
 3 files changed, 32 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c 
b/drivers/gpu/drm/i915/i915_drv.c

index 7056bb2..d0a710d 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1655,6 +1655,7 @@ static int i915_suspend_switcheroo(struct 
drm_device *dev, pm_message_t state)

 static int i915_drm_resume(struct drm_device *dev)
 {
 struct drm_i915_private *dev_priv = to_i915(dev);
+    struct pci_dev *pdev = dev_priv->drm.pdev;
 int ret;
disable_rpm_wakeref_asserts(dev_priv);
@@ -1666,7 +1667,9 @@ static int i915_drm_resume(struct drm_device *dev)
intel_csr_ucode_resume(dev_priv);
-    i915_gem_resume(dev_priv);
+    ret = i915_gem_resume(dev_priv);
+    if (ret)
+    dev_err(>dev, "GEM resume failed\n");


btw, code above/below uses DRM_ERROR()

This was in symmetry with i915_gem_suspend return handling.



i915_restore_state(dev_priv);
 intel_pps_unlock_regs_wa(dev_priv);
@@ -2495,7 +2498,11 @@ static int intel_runtime_suspend(struct device 
*kdev)
  * We are safe here against re-faults, since the fault handler 
takes

  * an RPM reference.
  */
-    i915_gem_runtime_suspend(dev_priv);
+    ret = i915_gem_runtime_suspend(dev_priv);
+    if (ret) {
+    enable_rpm_wakeref_asserts(dev_priv);
+    return ret;


as this is second place where we exit, maybe it's time for

if (ret)
    goto fail;
fail:
enable_rpm_wakeref_asserts(dev_priv);
return ret;
}


Yes. Will update.

+    }
intel_guc_suspend(dev_priv);
@@ -2515,6 +2522,8 @@ static int intel_runtime_suspend(struct device 
*kdev)

 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
 intel_runtime_pm_enable_interrupts(dev_priv);
+    intel_guc_resume(dev_priv);
+    i915_gem_runtime_resume(dev_priv);
 enable_rpm_wakeref_asserts(dev_priv);
    return ret;
@@ -2596,13 +2605,6 @@ static int intel_runtime_resume(struct device 
*kdev)

 ret = vlv_resume_prepare(dev_priv, true);
 }
-    /*
- * No point of rolling back things in case of an error, as the best
- * we can do is to hope that things will still work (and disable 
RPM).

- */
-    i915_gem_init_swizzling(dev_priv);
-    i915_gem_restore_fences(dev_priv);
-
 intel_runtime_pm_enable_interrupts(dev_priv);
/*
@@ -2615,6 +2617,8 @@ static int intel_runtime_resume(struct device 
*kdev)

intel_enable_ipc(dev_priv);
+    i915_gem_runtime_resume(dev_priv);
+
 enable_rpm_wakeref_asserts(dev_priv);
if (ret)
diff --git a/drivers/gpu/drm/i915/i915_drv.h 
b/drivers/gpu/drm/i915/i915_drv.h

index b7cba89..42f3d89 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3479,7 +3479,8 @@ struct i915_vma * __must_check
 int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
-void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
+int i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
+void i915_gem_runtime_resume(struct drm_i915_private *dev_priv);
static inline int __sg_page_count(const struct scatterlist *sg)
 {
@@ -3682,7 +3683,7 @@ void i915_gem_reset_engine(struct 
intel_engine_cs *engine,

 int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
    unsigned int flags);
 int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
-void i915_gem_resume(struct drm_i915_private *dev_priv);
+int i915_gem_resume(struct drm_i915_private *dev_priv);
 int i915_gem_fault(struct vm_fault *vmf);
 int i915_gem_object_wait(struct drm_i915_gem_object *obj,
  unsigned int flags,
diff --git a/drivers/gpu/drm/i915/i915_gem.c 

Re: [Intel-gfx] [PATCH] dim: Accept author x signed-off based on email.

[Rodrigo Vivi]

On Wed, Sep 27, 2017 at 12:14:55PM +, Daniel Vetter wrote:
> On Tue, Sep 26, 2017 at 09:55:44AM -0700, Rodrigo Vivi wrote:
> > On Tue, Sep 26, 2017 at 01:24:35PM +, Jani Nikula wrote:
> > > On Tue, 26 Sep 2017, Daniel Vetter  wrote:
> > > > On Thu, Sep 21, 2017 at 06:27:28AM -0700, Rodrigo Vivi wrote:
> > > >> On Thu, Sep 21, 2017 at 11:12:52AM +, Jani Nikula wrote:
> > > >> > On Wed, 20 Sep 2017, Rodrigo Vivi  wrote:
> > > >> > > It seems Patchwork or SMTP servers are messing some patches
> > > >> > > and changing the original git's author name on git per "Last, 
> > > >> > > First".
> > > >> > > So we end up with a mismatch were signed-off uses one name format
> > > >> > > and author is using another format.
> > > >> > >
> > > >> > > So, let's check for email addresses instead.
> > > >> > >
> > > >> > > v2: Avoid useles warning and only check for email.
> > > >> > >
> > > >> > > Cc: Jani Nikula 
> > > >> > > Cc: Joonas Lahtinen 
> > > >> > > Signed-off-by: Rodrigo Vivi 
> > > >> > 
> > > >> > Reviewed-by: Jani Nikula 
> > > >> 
> > > >> pushed, thanks.
> > > >
> > > > Yeah except this breaks funny people like me who use different mails for
> > > > stuff. My idea with fixing this was that we parse the mail name and 
> > > > check
> > > > for both "Last, First" and "First Last" to work around the outlook crap.
> > 
> > The name parsing with last and first can be really nasty and end up having 
> > other
> > corner cases soon.
> > 
> > Like, my legal name in us is still:
> > de Oliveira Vivi, Rodrigo
> > not
> > Vivi, Rodrigo de Oliveira
> > 
> > I can imagine many other possible combinations with this and other names.
> 
> Luckily you're only Rodrigo Vivi in intel's system, so we're passing.

my one was just the first example that came to my mind ;)

> 
> But yes, we probably need to check all possible combos for where we could
> place the comma.

yep, because my name wasn't the problem on the fixes branches flow.
Others names end up merged with last, name.

> 
> > 
> > > >
> > > > I really don't want to send mail from @intel.com to anywhere near public
> > > > stuff.
> > 
> > I'm not sure if it is outlook fault honestly. On my patches where this funny
> > mess happenend I checked my email on the mailing list and original and 
> > everything
> > seemed sane there. The only place where Last, First started was post 
> > pwclient.
> > 
> > > 
> > > Ok, I'm fine with reverting, and finding another way.
> > 
> > I'm fine with the revert as well, but before reverting let me propose one 
> > thing
> > that is name_match || email_match so we cover both cases.
> > 
> > What do you think?
> 
> I sent out a patch, pls test for your cases. I'll be happy to amend.

lets move with those patches and if I get impacted on fixes flow later again I 
raise it back ;)


> -Daniel
> 
> > 
> > > 
> > > BR,
> > > Jani.
> > > 
> > > > -Daniel
> > > >
> > > >> 
> > > >> > 
> > > >> > > ---
> > > >> > >  dim | 2 +-
> > > >> > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > > >> > >
> > > >> > > diff --git a/dim b/dim
> > > >> > > index dbaeb1ec944d..a63000fb67a8 100755
> > > >> > > --- a/dim
> > > >> > > +++ b/dim
> > > >> > > @@ -689,7 +689,7 @@ function checkpatch_commit_push
> > > >> > >sha1=$1
> > > >> > >  
> > > >> > ># use real names for people with many different email addresses
> > > >> > > -  author=$(git show -s $sha1 --format="format:%an")
> > > >> > > +  author=$(git show -s $sha1 --format="format:%ae")
> > > >> > >committer=$(git show -s $sha1 --format="format:%cn")
> > > >> > >  
> > > >> > ># check for author sign-off
> > > >> > 
> > > >> > -- 
> > > >> > Jani Nikula, Intel Open Source Technology Center
> > > >> ___
> > > >> Intel-gfx mailing list
> > > >> Intel-gfx@lists.freedesktop.org
> > > >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > > 
> > > -- 
> > > Jani Nikula, Intel Open Source Technology Center
> 
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
___
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH v10 1/9] drm/i915: Create GEM runtime resume helper and handle GEM suspend/resume errors

[Michal Wajdeczko]

On Wed, 27 Sep 2017 11:30:31 +0200, Sagar Arun Kamble  
 wrote:



These changes are preparation to handle GuC suspend/resume. Prepared
helper i915_gem_runtime_resume to reinitialize suspended gem setup.
Returning status from i915_gem_runtime_suspend and i915_gem_resume.
This will be placeholder for handling any errors from uC suspend/resume
in upcoming patches. Restructured the suspend/resume routines w.r.t setup
creation and rollback order.
This also fixes issue of ordering of i915_gem_runtime_resume with
intel_runtime_pm_enable_interrupts.

v2: Fixed return from intel_runtime_resume. (Michał Winiarski)

v3: Not returning status from gem_runtime_resume. (Chris)

Signed-off-by: Sagar Arun Kamble 
Cc: Chris Wilson 
Cc: Imre Deak 
Cc: Paulo Zanoni 
Cc: Rodrigo Vivi 
Cc: Michal Wajdeczko 
Cc: Michał Winiarski 
---
 drivers/gpu/drm/i915/i915_drv.c | 22 +-
 drivers/gpu/drm/i915/i915_drv.h |  5 +++--
 drivers/gpu/drm/i915/i915_gem.c | 18 --
 3 files changed, 32 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c  
b/drivers/gpu/drm/i915/i915_drv.c

index 7056bb2..d0a710d 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1655,6 +1655,7 @@ static int i915_suspend_switcheroo(struct  
drm_device *dev, pm_message_t state)

 static int i915_drm_resume(struct drm_device *dev)
 {
struct drm_i915_private *dev_priv = to_i915(dev);
+   struct pci_dev *pdev = dev_priv->drm.pdev;
int ret;
disable_rpm_wakeref_asserts(dev_priv);
@@ -1666,7 +1667,9 @@ static int i915_drm_resume(struct drm_device *dev)
intel_csr_ucode_resume(dev_priv);
-   i915_gem_resume(dev_priv);
+   ret = i915_gem_resume(dev_priv);
+   if (ret)
+   dev_err(>dev, "GEM resume failed\n");


btw, code above/below uses DRM_ERROR()


i915_restore_state(dev_priv);
intel_pps_unlock_regs_wa(dev_priv);
@@ -2495,7 +2498,11 @@ static int intel_runtime_suspend(struct device  
*kdev)

 * We are safe here against re-faults, since the fault handler takes
 * an RPM reference.
 */
-   i915_gem_runtime_suspend(dev_priv);
+   ret = i915_gem_runtime_suspend(dev_priv);
+   if (ret) {
+   enable_rpm_wakeref_asserts(dev_priv);
+   return ret;


as this is second place where we exit, maybe it's time for

if (ret)
goto fail;
fail:
enable_rpm_wakeref_asserts(dev_priv);
return ret;
}


+   }
intel_guc_suspend(dev_priv);
@@ -2515,6 +2522,8 @@ static int intel_runtime_suspend(struct device  
*kdev)

DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
intel_runtime_pm_enable_interrupts(dev_priv);
+   intel_guc_resume(dev_priv);
+   i915_gem_runtime_resume(dev_priv);
enable_rpm_wakeref_asserts(dev_priv);
return ret;
@@ -2596,13 +2605,6 @@ static int intel_runtime_resume(struct device  
*kdev)

ret = vlv_resume_prepare(dev_priv, true);
}
-   /*
-* No point of rolling back things in case of an error, as the best
-* we can do is to hope that things will still work (and disable RPM).
-*/
-   i915_gem_init_swizzling(dev_priv);
-   i915_gem_restore_fences(dev_priv);
-
intel_runtime_pm_enable_interrupts(dev_priv);
/*
@@ -2615,6 +2617,8 @@ static int intel_runtime_resume(struct device  
*kdev)

intel_enable_ipc(dev_priv);
+   i915_gem_runtime_resume(dev_priv);
+
enable_rpm_wakeref_asserts(dev_priv);
if (ret)
diff --git a/drivers/gpu/drm/i915/i915_drv.h  
b/drivers/gpu/drm/i915/i915_drv.h

index b7cba89..42f3d89 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3479,7 +3479,8 @@ struct i915_vma * __must_check
 int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
-void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
+int i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
+void i915_gem_runtime_resume(struct drm_i915_private *dev_priv);
static inline int __sg_page_count(const struct scatterlist *sg)
 {
@@ -3682,7 +3683,7 @@ void i915_gem_reset_engine(struct intel_engine_cs  
*engine,

 int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
   unsigned int flags);
 int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
-void i915_gem_resume(struct drm_i915_private *dev_priv);
+int i915_gem_resume(struct drm_i915_private *dev_priv);
 int i915_gem_fault(struct vm_fault *vmf);
 int i915_gem_object_wait(struct drm_i915_gem_object *obj,
   

Re: [Intel-gfx] [PATCH 1/3] dim: redo the author sob checks

[Rodrigo Vivi]

On Wed, Sep 27, 2017 at 09:48:48AM +, Daniel Vetter wrote:
> This reverts commit 41dddc0287bb9ef14be8de3c3185ed6aaa809d98 and then
> tries a different approach because from the commit that originally
> introduced this:
> 
> commit 3dd25f235c73f7855dc570585eb2551961a1911a
> Author: Benjamin Gaignard 
> Date:   Wed Jul 26 14:07:49 2017 +0200
> 
> dim: add checks for author and committer sign-off-by
> 
> we have
> 
> "Use real names for people with many different email addresses."
> 
> to work around outlook we need to convert the "Last, First" firm into
> what git expects instead, which also should solve the problem Rodrigo
> has.
> 
> Cc: Rodrigo Vivi 
> Cc: Jani Nikula 
> Signed-off-by: Daniel Vetter 

Acked-by: Rodrigo Vivi 

> ---
>  dim | 6 --
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/dim b/dim
> index 5e8c4d5b212d..4d75c7a7fb0e 100755
> --- a/dim
> +++ b/dim
> @@ -698,11 +698,13 @@ function checkpatch_commit_push
>   sha1=$1
>  
>   # use real names for people with many different email addresses
> - author=$(git show -s $sha1 --format="format:%ae")
> + author=$(git show -s $sha1 --format="format:%an")
>   committer=$(git show -s $sha1 --format="format:%cn")
> + # outlook mangles mails into "Last, First"
> + author_outlook=$(git show -s $sha1 --format="format:%an" | sed -e 
> 's/\([^ ]*\) \(.*\)/\2, \1/')
>  
>   # check for author sign-off
> - if ! git show -s $sha1 | grep -qi "S.*-by:.*$author"  ; then
> + if ! git show -s $sha1 | grep -qi 
> "S.*-by:.*\\($author\\|$author_outlook\\)" ; then
>   warn_or_fail "$sha1 is lacking author of sign-off"
>   fi
>  
> -- 
> 2.14.1
> 
___
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Re: [Intel-gfx] [PATCH v10 2/9] drm/i915: Update GEM suspend/resume flows considering GuC and GEM fences

[Michal Wajdeczko]

On Wed, 27 Sep 2017 11:30:32 +0200, Sagar Arun Kamble  
 wrote:


This patch moves GuC suspend/resume handlers to corresponding GEM  
handlers

and orders them properly in the runtime and system suspend/resume flows.
i915_gem_restore_fences is GEM resumption task hence it is moved to
i915_gem_resume from i915_restore_state.

v2: Removed documentation of suspend/resume handlers as those are not
interfaces and are just hooks. (Chris)

Signed-off-by: Sagar Arun Kamble 
Cc: Chris Wilson 
Cc: Imre Deak 
Cc: Paulo Zanoni 
Cc: Rodrigo Vivi 
Cc: Michal Wajdeczko 
Cc: Michał Winiarski 
---
 drivers/gpu/drm/i915/i915_drv.c |  7 ---
 drivers/gpu/drm/i915/i915_gem.c | 11 ---
 drivers/gpu/drm/i915/i915_suspend.c |  2 --
 3 files changed, 8 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c  
b/drivers/gpu/drm/i915/i915_drv.c

index d0a710d..174a7c5 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1698,8 +1698,6 @@ static int i915_drm_resume(struct drm_device *dev)
}
mutex_unlock(>struct_mutex);
-   intel_guc_resume(dev_priv);
-
intel_modeset_init_hw(dev);
spin_lock_irq(_priv->irq_lock);
@@ -2504,8 +2502,6 @@ static int intel_runtime_suspend(struct device  
*kdev)

return ret;
}
-   intel_guc_suspend(dev_priv);
-
intel_runtime_pm_disable_interrupts(dev_priv);
ret = 0;
@@ -2522,7 +2518,6 @@ static int intel_runtime_suspend(struct device  
*kdev)

DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
intel_runtime_pm_enable_interrupts(dev_priv);
-   intel_guc_resume(dev_priv);
i915_gem_runtime_resume(dev_priv);
enable_rpm_wakeref_asserts(dev_priv);
@@ -2591,8 +2586,6 @@ static int intel_runtime_resume(struct device  
*kdev)

if (intel_uncore_unclaimed_mmio(dev_priv))
DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
-   intel_guc_resume(dev_priv);
-
if (IS_GEN9_LP(dev_priv)) {
bxt_disable_dc9(dev_priv);
bxt_display_core_init(dev_priv, true);
diff --git a/drivers/gpu/drm/i915/i915_gem.c  
b/drivers/gpu/drm/i915/i915_gem.c

index 59a88f2..11922af 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2027,6 +2027,8 @@ int i915_gem_runtime_suspend(struct  
drm_i915_private *dev_priv)

struct drm_i915_gem_object *obj, *on;
int i;
+   intel_guc_suspend(dev_priv);
+
/*
 * Only called during RPM suspend. All users of the userfault_list
 * must be holding an RPM wakeref to ensure that this can not
@@ -2077,6 +2079,8 @@ void i915_gem_runtime_resume(struct  
drm_i915_private *dev_priv)

 */
i915_gem_init_swizzling(dev_priv);
i915_gem_restore_fences(dev_priv);
+
+   intel_guc_resume(dev_priv);
 }
static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object  
*obj)
@@ -4551,8 +4555,6 @@ int i915_gem_suspend(struct drm_i915_private  
*dev_priv)

i915_gem_contexts_lost(dev_priv);
mutex_unlock(>struct_mutex);
-   intel_guc_suspend(dev_priv);
-
cancel_delayed_work_sync(_priv->gpu_error.hangcheck_work);
cancel_delayed_work_sync(_priv->gt.retire_work);
@@ -4569,6 +4571,8 @@ int i915_gem_suspend(struct drm_i915_private  
*dev_priv)

if (WARN_ON(!intel_engines_are_idle(dev_priv)))
i915_gem_set_wedged(dev_priv); /* no hope, discard everything */
+   intel_guc_suspend(dev_priv);
+
/*
 * Neither the BIOS, ourselves or any other kernel
 * expects the system to be in execlists mode on startup,
@@ -4607,13 +4611,14 @@ int i915_gem_resume(struct drm_i915_private  
*dev_priv)

mutex_lock(>struct_mutex);
i915_gem_restore_gtt_mappings(dev_priv);
+   i915_gem_restore_fences(dev_priv);
/* As we didn't flush the kernel context before suspend, we cannot
 * guarantee that the context image is complete. So let's just reset
 * it and start again.
 */
dev_priv->gt.resume(dev_priv);
-


I would leave that empty line


+   intel_guc_resume(dev_priv);
mutex_unlock(>struct_mutex);
return 0;
diff --git a/drivers/gpu/drm/i915/i915_suspend.c  
b/drivers/gpu/drm/i915/i915_suspend.c

index 5c86925a..8f3aa4d 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -108,8 +108,6 @@ int i915_restore_state(struct drm_i915_private  
*dev_priv)

mutex_lock(_priv->drm.struct_mutex);
-   i915_gem_restore_fences(dev_priv);
-


And this move of i915_gem_restore_fences() can likely be in separate patch

Michal


if 

Re: [Intel-gfx] [PATCH 2/3] dim: auto-add remotes

[Rodrigo Vivi]

On Wed, Sep 27, 2017 at 09:48:49AM +, Daniel Vetter wrote:
> Well, bother to at least prompt. Prep work for adding drm-amd.git.
> 
> Signed-off-by: Daniel Vetter 
> ---
>  dim | 9 -
>  1 file changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/dim b/dim
> index 4d75c7a7fb0e..6ebbad2b6dfd 100755
> --- a/dim
> +++ b/dim
> @@ -274,7 +274,14 @@ function url_to_remote # url
>   echoerr "Please set it up using:"
>   echoerr "$ git remote add  $url"

I think these 2 messages above doesn't make sense anymore, right?

>   echoerr "with a name of your choice."
> - return 1

\o/
I like to see more automation on the setup...

> + remote=${url%.git}
> + remote=${remote##*/}
> + read -r -i "$remote" -e -p "Enter a name to auto-add 
> this remote, leave blank to abort: " || true

I'd be more in favor of forcing a standard and be flexible on .dimrc to any 
later change if people
really need that.

Anyways not blocking.
With messages above checked:

Acked-by: Rodrigo Vivi 

> + if [[ "$REPLY" == "" ]] ; then
> + exit 1
> + fi
> +
> + git remote add $remote $url
>   fi
>   fi
>  
> -- 
> 2.14.1
> 
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Re: [Intel-gfx] [PATCH 3/3] dim: add drm-amd.git

[Rodrigo Vivi]

On Wed, Sep 27, 2017 at 09:48:50AM +, Daniel Vetter wrote:
> Unfortunately there's a little bit of hardcoded stuff still.
> 
> Cc: Alex Deucher 
> Cc: Harry Wentland 
> Signed-off-by: Daniel Vetter 

Acked-by: Rodrigo Vivi 

> ---
>  dim | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/dim b/dim
> index 6ebbad2b6dfd..63ffebe14781 100755
> --- a/dim
> +++ b/dim
> @@ -761,6 +761,7 @@ function dim_push_branch
>  
>   update_linux_next $branch drm-intel-next-queued drm-intel-next-fixes 
> drm-intel-fixes
>   update_linux_next $branch drm-misc-next drm-misc-next-fixes 
> drm-misc-fixes
> + update_linux_next $branch drm-amd-next drm-amd-next-fixes drm-amd-fixes
>  
>   dim_rebuild_tip
>  }
> -- 
> 2.14.1
> 
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[Intel-gfx] [PATCH v2] drm/i915: Allow optimized platform checks

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

If we store the platform as a bitmask, and convert the
IS_PLATFORM macro to use it, we allow the compiler to
merge the IS_PLATFORM(a) || IS_PLATFORM(b) || ... checks
into a single conditional.

As a secondary benefit this saves almost 1k of text:

text   data bss dec hex filename
-1460254  600143656 1523924  1740d4 drivers/gpu/drm/i915/i915.ko
+1459260  600263656 1522942  173cfe drivers/gpu/drm/i915/i915.ko

v2: Removed the infamous -1.

Signed-off-by: Tvrtko Ursulin 
Cc: Jani Nikula 
---
 drivers/gpu/drm/i915/i915_drv.c | 4 
 drivers/gpu/drm/i915/i915_drv.h | 3 ++-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 03bbe23e4df8..187c0fad1b79 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -870,6 +870,10 @@ static int i915_driver_init_early(struct drm_i915_private 
*dev_priv,
memcpy(device_info, match_info, sizeof(*device_info));
device_info->device_id = dev_priv->drm.pdev->device;
 
+   BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
+sizeof(device_info->platform_mask) * BITS_PER_BYTE);
+   device_info->platform_mask = BIT(device_info->platform);
+
BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * 
BITS_PER_BYTE);
device_info->gen_mask = BIT(device_info->gen - 1);
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bda91db3fc46..3a6a34882427 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -861,6 +861,7 @@ struct intel_device_info {
u8 ring_mask; /* Rings supported by the HW */
 
enum intel_platform platform;
+   u32 platform_mask;
 
u32 display_mmio_offset;
 
@@ -2986,7 +2987,7 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define IS_REVID(p, since, until) \
(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
 
-#define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform == (p))
+#define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask & BIT(p))
 
 #define IS_I830(dev_priv)  IS_PLATFORM(dev_priv, INTEL_I830)
 #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
-- 
2.9.5

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Allow optimized platform checks

[Patchwork]

== Series Details ==

Series: drm/i915: Allow optimized platform checks
URL   : https://patchwork.freedesktop.org/series/30982/
State : success

== Summary ==

Series 30982v1 drm/i915: Allow optimized platform checks
https://patchwork.freedesktop.org/api/1.0/series/30982/revisions/1/mbox/

Test drv_module_reload:
Subgroup basic-reload:
dmesg-warn -> PASS   (fi-glk-1) fdo#102777

fdo#102777 https://bugs.freedesktop.org/show_bug.cgi?id=102777

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:440s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:479s
fi-blb-e6850 total:289  pass:224  dwarn:1   dfail:0   fail:0   skip:64  
time:419s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:519s
fi-bwr-2160  total:289  pass:184  dwarn:0   dfail:0   fail:0   skip:105 
time:282s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:499s
fi-byt-j1900 total:289  pass:254  dwarn:1   dfail:0   fail:0   skip:34  
time:492s
fi-cfl-s total:289  pass:223  dwarn:34  dfail:0   fail:0   skip:32  
time:544s
fi-cnl-y total:289  pass:258  dwarn:0   dfail:0   fail:4   skip:27  
time:637s
fi-elk-e7500 total:289  pass:230  dwarn:0   dfail:0   fail:0   skip:59  
time:420s
fi-glk-1 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:568s
fi-hsw-4770  total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:424s
fi-hsw-4770r total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:405s
fi-ilk-650   total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:437s
fi-ivb-3520m total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:493s
fi-ivb-3770  total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:468s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:471s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:584s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:593s
fi-pnv-d510  total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:546s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:446s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:745s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:485s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:473s
fi-snb-2520m total:289  pass:251  dwarn:0   dfail:0   fail:0   skip:38  
time:567s
fi-snb-2600  total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:410s

aa884e1abdf2ffb7db8c524fc6269280734e5145 drm-tip: 2017y-09m-27d-15h-39m-07s UTC 
integration manifest
6ef30a4343e1 drm/i915: Allow optimized platform checks

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5834/
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Re: [Intel-gfx] [PATCH] drm/i915/cnl: WaForceContextSaveRestoreNonCoherent

[Oscar Mateo]

On 09/27/2017 03:37 AM, Mika Kuoppala wrote:

Chris Wilson  writes:


Quoting Rodrigo Vivi (2017-08-23 00:27:15)

To avoid a potential hang condition with TLB invalidation
we need to enable masked bit 5 of MMIO 0xE5F0 at boot.

Same workaround was in place for previous platforms,
but the change for CNL is more on the register offset.
But also BSpec doesn't mention the bit 15 as set on gen9
platforms and mark bit as reserved on CNL.

Cc: Mika Kuoppala 
Cc: Oscar Mateo 
Signed-off-by: Rodrigo Vivi 
---
  drivers/gpu/drm/i915/i915_reg.h| 1 +
  drivers/gpu/drm/i915/intel_engine_cs.c | 4 
  2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d4ecb1905ad8..f31fab2651fb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7024,6 +7024,7 @@ enum {
  
  /* GEN8 chicken */

  #define HDC_CHICKEN0   _MMIO(0x7300)
+#define CNL_HDC_CHICKEN0   _MMIO(0xE5F0)
  #define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE(1<<15)
  #define  HDC_FENCE_DEST_SLM_DISABLE(1<<14)
  #define  HDC_DONOT_FETCH_MEM_WHEN_MASKED   (1<<11)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index d23f18874309..26c35ce5f240 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1070,6 +1070,10 @@ static int cnl_init_workarounds(struct intel_engine_cs 
*engine)
 struct drm_i915_private *dev_priv = engine->i915;
 int ret;
  
+   /* WaForceContextSaveRestoreNonCoherent:cnl */

+   WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0,
+ HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);

This register is not sticky (i.e. does not retain its value even with a
powercontext loaded). Does it even exist?
-Chris

That is a good question. The documentation indicates it does
and evidence indicates that it doesn't.

I will check when I get cnl unless someone beats me to it.

-Mika


H... there is a "programming note" in the BSpec for CNL+ that says:

"The register is write-only from LRI command. However, it is readable 
for context save."


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Re: [Intel-gfx] [PATCH v10 5/9] drm/i915/guc: Update GuC ggtt.invalidate/interrupts/communication across RPM suspend/resume

[Michal Wajdeczko]

On Wed, 27 Sep 2017 11:30:35 +0200, Sagar Arun Kamble  
 wrote:



Apart from configuring interrupts, we need to update the ggtt invalidate
interface and GuC communication on suspend/resume. This functionality
can be reused for other suspend and reset paths.

v2: Rebase w.r.t removal of GuC code restructuring.

v3: Removed GuC specific helpers as tasks other than send H2G for
sleep/resume are to be done from uc generic functions. (Michal Wajdeczko)

v4: Simplified/Unified the error messaging in uc_runtime_suspend/resume.
(Michal Wajdeczko). Rebase w.r.t i915_modparams change.
Added documentation to intel_uc_runtime_suspend/resume.

Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Michał Winiarski 
Reviewed-by: Michal Wajdeczko 
---
 drivers/gpu/drm/i915/i915_guc_submission.c |  5 ---
 drivers/gpu/drm/i915/intel_uc.c| 60  
+-

 2 files changed, 58 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c  
b/drivers/gpu/drm/i915/i915_guc_submission.c

index 04f1281..d1d6c0d 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -1226,8 +1226,6 @@ int intel_guc_suspend(struct drm_i915_private  
*dev_priv)

if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
return 0;


Btw, this check can be also moved to intel_uc_runtime_suspend()



-   gen9_disable_guc_interrupts(dev_priv);
-
ctx = dev_priv->kernel_context;
data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
@@ -1252,9 +1250,6 @@ int intel_guc_resume(struct drm_i915_private  
*dev_priv)

if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
return 0;


And above to intel_uc_runtime_resume()


-   if (i915_modparams.guc_log_level >= 0)
-   gen9_enable_guc_interrupts(dev_priv);
-
ctx = dev_priv->kernel_context;
data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
diff --git a/drivers/gpu/drm/i915/intel_uc.c  
b/drivers/gpu/drm/i915/intel_uc.c

index 7b30790..1446b5e 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -481,14 +481,70 @@ void intel_uc_fini_hw(struct drm_i915_private  
*dev_priv)

i915_ggtt_disable_guc(dev_priv);
 }
+/**
+ * intel_uc_runtime_suspend() - Suspend uC operation.
+ * @dev_priv: i915 device private
+ *
+ * This function invokes GuC OS suspension, makes ggtt_invalidate  
function to
+ * point to non-GuC variant, disables GuC interrupts and disable  
communication

+ * with GuC.
+ *
+ * Return: non-zero code on error
+ */
 int intel_uc_runtime_suspend(struct drm_i915_private *dev_priv)
 {
-   return intel_guc_suspend(dev_priv);
+   int ret;
+
+   if (!i915_modparams.enable_guc_loading)
+   return 0;
+
+   ret = intel_guc_suspend(dev_priv);
+   if (ret)
+   goto out;
+
+   i915_ggtt_disable_guc(dev_priv);
+   gen9_disable_guc_interrupts(dev_priv);
+   guc_disable_communication(_priv->guc);
+
+out:
+   if (ret)
+   DRM_ERROR("uC runtime suspend failed (%d)\n", ret);
+   return ret;
 }
+/**
+ * intel_uc_runtime_resume() - Resume uC operation.
+ * @dev_priv: i915 device private
+ *
+ * This function enables communication with GuC, enables GuC interrupts,
+ * makes ggtt_invalidate function to point to GuC variant and invokes
+ * GuC OS resumption.
+ *
+ * Return: non-zero code on error
+ */
 int intel_uc_runtime_resume(struct drm_i915_private *dev_priv)
 {
-   return intel_guc_resume(dev_priv);
+   int ret;
+
+   if (!i915_modparams.enable_guc_loading)
+   return 0;
+
+   ret = guc_enable_communication(_priv->guc);
+   if (ret)
+   goto out;
+
+   if (i915_modparams.guc_log_level >= 0)
+   gen9_enable_guc_interrupts(dev_priv);
+   i915_ggtt_enable_guc(dev_priv);
+
+   ret = intel_guc_resume(dev_priv);
+   if (ret)
+   goto out;
+
+out:
+   if (ret)
+   DRM_ERROR("uC runtime resume failed (%d)\n", ret);
+   return ret;
 }
int intel_uc_suspend(struct drm_i915_private *dev_priv)

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Re: [Intel-gfx] [PATCH v10 3/9] drm/i915: Create uC runtime and system suspend/resume helpers

[Sagar Arun Kamble]

On 9/27/2017 9:26 PM, Michal Wajdeczko wrote:
On Wed, 27 Sep 2017 11:30:33 +0200, Sagar Arun Kamble 
 wrote:



Prepared generic helpers intel_uc_suspend, intel_uc_resume,
intel_uc_runtime_suspend, intel_uc_runtime_resume. These are
called from respective GEM functions.
Only exception is intel_uc_resume that needs to be called
w/ or w/o GuC loaded in i915_drm_resume path. Changes to
add WOPCM condition check to load GuC during resume will be added
in later patches.

v2: Rebase w.r.t removal of GuC code restructuring.

v3: Calling intel_uc_resume from i915_gem_resume post resuming
i915 gem setup. This is symmetrical with i915_gem_suspend.
Removed error messages from i915 suspend/resume routines as
uC suspend/resume routines will have those. (Michal Wajdeczko)
Declare wedged on uc_suspend failure and uc_resume failure.
(Michał Winiarski)
Keeping the uC suspend/resume function definitions close to other
uC functions.

v4: Added implementation to intel_uc_resume as GuC resume is
needed to be triggered post reloading the firmware as well. Added
comments about semantics of GuC resume with the firmware reload.

Signed-off-by: Sagar Arun Kamble 
Cc: Chris Wilson 
Cc: Michal Wajdeczko 
Cc: Michał Winiarski 
---
 drivers/gpu/drm/i915/i915_drv.c | 10 ++
 drivers/gpu/drm/i915/i915_gem.c | 36 


 drivers/gpu/drm/i915/intel_uc.c | 20 
 drivers/gpu/drm/i915/intel_uc.h |  4 
 4 files changed, 62 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c 
b/drivers/gpu/drm/i915/i915_drv.c

index 174a7c5..f79646b 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1698,6 +1698,16 @@ static int i915_drm_resume(struct drm_device 
*dev)

 }
 mutex_unlock(>struct_mutex);
+    /*
+ * NB: Currently we know that at the end of suspend we have done 
Full

+ * GPU reset, Hence GuC is loaded again during i915_gem_init_hw.
+ * Now, send action to GuC to resume back again as earlier call to
+ * intel_uc_resume from i915_gem_resume would have done nothing.
+ */
+    ret = intel_uc_resume(dev_priv);
+    if (ret)
+    i915_gem_set_wedged(dev_priv);
+
 intel_modeset_init_hw(dev);
spin_lock_irq(_priv->irq_lock);
diff --git a/drivers/gpu/drm/i915/i915_gem.c 
b/drivers/gpu/drm/i915/i915_gem.c

index 11922af..c54c9b4 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2025,9 +2025,11 @@ int i915_gem_fault(struct vm_fault *vmf)
 int i915_gem_runtime_suspend(struct drm_i915_private *dev_priv)
 {
 struct drm_i915_gem_object *obj, *on;
-    int i;
+    int i, ret;
-    intel_guc_suspend(dev_priv);
+    ret = intel_uc_runtime_suspend(dev_priv);
+    if (ret)
+    return ret;
/*
  * Only called during RPM suspend. All users of the userfault_list
@@ -2068,7 +2070,7 @@ int i915_gem_runtime_suspend(struct 
drm_i915_private *dev_priv)

 reg->dirty = true;
 }
-    return 0;
+    return ret;


Hmm, at this point we know that we didn't fail, so return 0 was fine.
Ok. Will update. ret was also zero and I though returning ret will be 
good in future if we use goto to the end. But can be updated later if 
needed.



 }
void i915_gem_runtime_resume(struct drm_i915_private *dev_priv)
@@ -2080,7 +2082,7 @@ void i915_gem_runtime_resume(struct 
drm_i915_private *dev_priv)

 i915_gem_init_swizzling(dev_priv);
 i915_gem_restore_fences(dev_priv);
-    intel_guc_resume(dev_priv);
+    intel_uc_runtime_resume(dev_priv);
 }
static int i915_gem_object_create_mmap_offset(struct 
drm_i915_gem_object *obj)
@@ -4571,7 +4573,9 @@ int i915_gem_suspend(struct drm_i915_private 
*dev_priv)

 if (WARN_ON(!intel_engines_are_idle(dev_priv)))
 i915_gem_set_wedged(dev_priv); /* no hope, discard 
everything */

-    intel_guc_suspend(dev_priv);
+    ret = intel_uc_suspend(dev_priv);
+    if (ret)
+    i915_gem_set_wedged(dev_priv); /* no hope, discard 
everything */

/*
  * Neither the BIOS, ourselves or any other kernel
@@ -4606,6 +4610,7 @@ int i915_gem_suspend(struct drm_i915_private 
*dev_priv)

 int i915_gem_resume(struct drm_i915_private *dev_priv)
 {
 struct drm_device *dev = _priv->drm;
+    int ret;
WARN_ON(dev_priv->gt.awake);
@@ -4618,10 +4623,20 @@ int i915_gem_resume(struct drm_i915_private 
*dev_priv)

  * it and start again.
  */
 dev_priv->gt.resume(dev_priv);
-    intel_guc_resume(dev_priv);
+
+    /*
+ * NB: At the end of suspend, Full GPU reset is being done which
+ * wipes/unloads the GuC firmware. If reset is avoided there, we 
can
+ * check the WOPCM status here to see if GuC is still loaded and 
just

+ * do GuC resume without reloading the firmware back.
+ */
+    ret = intel_uc_resume(dev_priv);
+    if (ret)
+    

Re: [Intel-gfx] [PATCH v2] drm/i915: Allow optimized platform checks

[Chris Wilson]

Quoting Tvrtko Ursulin (2017-09-27 17:41:38)
> From: Tvrtko Ursulin 
> 
> If we store the platform as a bitmask, and convert the
> IS_PLATFORM macro to use it, we allow the compiler to
> merge the IS_PLATFORM(a) || IS_PLATFORM(b) || ... checks
> into a single conditional.
> 
> As a secondary benefit this saves almost 1k of text:
> 
> text   data bss dec hex filename
> -1460254  600143656 1523924  1740d4 drivers/gpu/drm/i915/i915.ko
> +1459260  600263656 1522942  173cfe drivers/gpu/drm/i915/i915.ko
> 
> v2: Removed the infamous -1.
> 
> Signed-off-by: Tvrtko Ursulin 
> Cc: Jani Nikula 

I checked a few of our IS_*() to make sure we were not storing any
inside a local int which may cause a few surprises (but unlikely if they
are ever used outside of boolean contxt).

Reviewed-by: Chris Wilson 
-Chris
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[Intel-gfx] [PATCH i-g-t v4 5/6] tests/kms_ccs: Test case where CCS is on a different BO

[Gabriel Krisman Bertazi]

Signed-off-by: Gabriel Krisman Bertazi 
---
 tests/kms_ccs.c | 17 ++---
 1 file changed, 14 insertions(+), 3 deletions(-)

diff --git a/tests/kms_ccs.c b/tests/kms_ccs.c
index 35dfcca6be14..2d7105eb1323 100644
--- a/tests/kms_ccs.c
+++ b/tests/kms_ccs.c
@@ -34,10 +34,11 @@ enum test_flags {
TEST_BAD_PIXEL_FORMAT   = 1 << 3,
TEST_BAD_ROTATION_90= 1 << 4,
TEST_NO_AUX_BUFFER  = 1 << 5,
+   TEST_BAD_CCS_HANDLE = 1 << 6,
 };
 
 #define TEST_FAIL_ON_ADDFB2 \
-   (TEST_BAD_PIXEL_FORMAT | TEST_NO_AUX_BUFFER)
+   (TEST_BAD_PIXEL_FORMAT | TEST_NO_AUX_BUFFER | TEST_BAD_CCS_HANDLE)
 
 enum test_fb_flags {
FB_COMPRESSED   = 1 << 0,
@@ -275,6 +276,7 @@ static void generate_fb(data_t *data, struct igt_fb *fb,
unsigned int size[2];
uint64_t modifier;
int ret;
+   uint32_t ccs_handle;
 
/* Use either compressed or Y-tiled to test. However, given the lack of
 * available bandwidth, we use linear for the primary plane when
@@ -325,10 +327,15 @@ static void generate_fb(data_t *data, struct igt_fb *fb,
size[1] = ccs_pitches * ALIGN(ccs_height, 32);
 
f.handles[0] = gem_create(data->drm_fd, size[0] + size[1]);
+   if (data->flags & TEST_BAD_CCS_HANDLE) {
+   /* Put the CCS buffer on a different BO. */
+   ccs_handle = gem_create(data->drm_fd, size[0] + 
size[1]);
+   } else
+   ccs_handle = f.handles[0];
 
if (!(data->flags & TEST_NO_AUX_BUFFER)) {
f.modifier[1] = modifier;
-   f.handles[1] = f.handles[0];
+   f.handles[1] = ccs_handle;
f.pitches[1] = ccs_pitches;
f.offsets[1] = ccs_offsets;
 
@@ -458,7 +465,8 @@ static void test_output(data_t *data)
 
if (data->flags & TEST_BAD_PIXEL_FORMAT ||
data->flags & TEST_BAD_ROTATION_90 ||
-   data->flags & TEST_NO_AUX_BUFFER) {
+   data->flags & TEST_NO_AUX_BUFFER ||
+   data->flags & TEST_BAD_CCS_HANDLE) {
try_config(data, fb_flags | FB_COMPRESSED);
}
 
@@ -532,6 +540,9 @@ igt_main
igt_subtest_f("pipe-%s-missing-ccs-buffer", pipe_name)
test_output();
 
+   data.flags = TEST_BAD_CCS_HANDLE;
+   igt_subtest_f("pipe-%s-ccs-on-another-bo", pipe_name)
+   test_output();
}
 
igt_fixture
-- 
2.11.0

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[Intel-gfx] [PATCH i-g-t v4 4/6] tests/kms_ccs: Test case where the CCS buffer was not provided

[Gabriel Krisman Bertazi]

Signed-off-by: Gabriel Krisman Bertazi 
---
 tests/kms_ccs.c | 37 +++--
 1 file changed, 27 insertions(+), 10 deletions(-)

diff --git a/tests/kms_ccs.c b/tests/kms_ccs.c
index 73025a1e019f..35dfcca6be14 100644
--- a/tests/kms_ccs.c
+++ b/tests/kms_ccs.c
@@ -33,8 +33,12 @@ enum test_flags {
TEST_ROTATE_180 = 1 << 2,
TEST_BAD_PIXEL_FORMAT   = 1 << 3,
TEST_BAD_ROTATION_90= 1 << 4,
+   TEST_NO_AUX_BUFFER  = 1 << 5,
 };
 
+#define TEST_FAIL_ON_ADDFB2 \
+   (TEST_BAD_PIXEL_FORMAT | TEST_NO_AUX_BUFFER)
+
 enum test_fb_flags {
FB_COMPRESSED   = 1 << 0,
FB_HAS_PLANE= 1 << 1,
@@ -315,22 +319,29 @@ static void generate_fb(data_t *data, struct igt_fb *fb,
 */
int ccs_width = ALIGN(width * 4, 32) / 32;
int ccs_height = ALIGN(height, 16) / 16;
-   f.pitches[1] = ALIGN(ccs_width * 1, 128);
-   f.modifier[1] = modifier;
-   f.offsets[1] = size[0];
-   size[1] = f.pitches[1] * ALIGN(ccs_height, 32);
+   int ccs_pitches = ALIGN(ccs_width * 1, 128);
+   int ccs_offsets = size[0];
+
+   size[1] = ccs_pitches * ALIGN(ccs_height, 32);
 
f.handles[0] = gem_create(data->drm_fd, size[0] + size[1]);
-   f.handles[1] = f.handles[0];
-   render_ccs(data, f.handles[1], f.offsets[1], size[1],
-  height, f.pitches[1]);
+
+   if (!(data->flags & TEST_NO_AUX_BUFFER)) {
+   f.modifier[1] = modifier;
+   f.handles[1] = f.handles[0];
+   f.pitches[1] = ccs_pitches;
+   f.offsets[1] = ccs_offsets;
+
+   render_ccs(data, f.handles[1], f.offsets[1], size[1],
+  height, f.pitches[1]);
+   }
} else
f.handles[0] = gem_create(data->drm_fd, size[0]);
 
render_fb(data, f.handles[0], size[0], fb_flags, height, f.pitches[0]);
 
ret = drmIoctl(data->drm_fd, LOCAL_DRM_IOCTL_MODE_ADDFB2, );
-   if (data->flags & TEST_BAD_PIXEL_FORMAT) {
+   if (data->flags & TEST_FAIL_ON_ADDFB2) {
igt_assert_eq(ret, -1);
igt_assert_eq(errno, EINVAL);
return;
@@ -379,7 +390,7 @@ static void try_config(data_t *data, enum test_fb_flags 
fb_flags)
drm_mode->vdisplay, fb_flags);
}
 
-   if (data->flags & TEST_BAD_PIXEL_FORMAT)
+   if (data->flags & TEST_FAIL_ON_ADDFB2)
return;
 
igt_plane_set_position(primary, 0, 0);
@@ -446,7 +457,8 @@ static void test_output(data_t *data)
}
 
if (data->flags & TEST_BAD_PIXEL_FORMAT ||
-   data->flags & TEST_BAD_ROTATION_90) {
+   data->flags & TEST_BAD_ROTATION_90 ||
+   data->flags & TEST_NO_AUX_BUFFER) {
try_config(data, fb_flags | FB_COMPRESSED);
}
 
@@ -515,6 +527,11 @@ igt_main
}
 
data.plane = NULL;
+
+   data.flags = TEST_NO_AUX_BUFFER;
+   igt_subtest_f("pipe-%s-missing-ccs-buffer", pipe_name)
+   test_output();
+
}
 
igt_fixture
-- 
2.11.0

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[Intel-gfx] [PATCH i-g-t 1/3] Fix rlim_cur compiler warnings when building on ARM.

[Eric Anholt]

Signed-off-by: Eric Anholt 
---
 benchmarks/prime_lookup.c | 2 +-
 tests/gem_exec_reuse.c| 3 ++-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/benchmarks/prime_lookup.c b/benchmarks/prime_lookup.c
index e995b766a173..d6c397299fcb 100644
--- a/benchmarks/prime_lookup.c
+++ b/benchmarks/prime_lookup.c
@@ -143,7 +143,7 @@ static bool allow_files(unsigned min)
return false;
 
igt_info("Current file limit is %ld, estimated we need %d\n",
-rlim.rlim_cur, min);
+(long)rlim.rlim_cur, min);
 
if (rlim.rlim_cur > min)
return true;
diff --git a/tests/gem_exec_reuse.c b/tests/gem_exec_reuse.c
index cdfa9783f5b7..4e3907cf7b52 100644
--- a/tests/gem_exec_reuse.c
+++ b/tests/gem_exec_reuse.c
@@ -122,7 +122,8 @@ static uint64_t max_open_files(void)
if (getrlimit(RLIMIT_NOFILE, ))
rlim.rlim_cur = 64 << 10;
 
-   igt_info("Process limit for file descriptors is %lu\n", rlim.rlim_cur);
+   igt_info("Process limit for file descriptors is %lu\n",
+(long)rlim.rlim_cur);
return rlim.rlim_cur;
 }
 
-- 
2.14.1

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[Intel-gfx] [PATCH i-g-t 2/3] meson: Fix build of igt_x86-using tests on non-x86 platforms.

[Eric Anholt]

Just stub out the features return value, and return an empty string.

Signed-off-by: Eric Anholt 
---
 lib/igt_x86.h   | 12 
 lib/meson.build |  5 -
 2 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/lib/igt_x86.h b/lib/igt_x86.h
index 589d224bec62..d6dcfa108331 100644
--- a/lib/igt_x86.h
+++ b/lib/igt_x86.h
@@ -40,7 +40,19 @@
 #define AVX0x80
 #define AVX2   0x100
 
+#if defined(__x86_64__)
 unsigned igt_x86_features(void);
 char *igt_x86_features_to_string(unsigned features, char *line);
+#else
+static inline unsigned igt_x86_features(void)
+{
+   return 0;
+}
+static inline char *igt_x86_features_to_string(unsigned features, char *line)
+{
+   line[0] = 0;
+   return line;
+}
+#endif
 
 #endif /* IGT_X86_H */
diff --git a/lib/meson.build b/lib/meson.build
index 203be520fd3f..df1dc465e310 100644
--- a/lib/meson.build
+++ b/lib/meson.build
@@ -54,7 +54,6 @@ lib_sources = [
'igt_rand.c',
'igt_stats.c',
'igt_sysfs.c',
-   'igt_x86.c',
'igt_vgem.c',
'instdone.c',
'intel_batchbuffer.c',
@@ -88,6 +87,10 @@ lib_sources = [
'igt_kmod.c',
 ]
 
+if ['x86', 'x86_64'].contains(host_machine.cpu_family())
+lib_sources += 'igt_x86.c'
+endif
+
 lib_deps = [
cairo,
glib,
-- 
2.14.1

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Re: [Intel-gfx] [PATCH i-g-t 2/2] igt: Add VC4 purgeable BO tests

[Eric Anholt]

Boris Brezillon  writes:

> On Wed, 27 Sep 2017 13:50:30 +0100
> Chris Wilson  wrote:
>
>> Quoting Boris Brezillon (2017-09-27 13:41:41)
>> > Hi Chris,
>> > 
>> > On Wed, 27 Sep 2017 13:07:28 +0100
>> > Chris Wilson  wrote:
>> >   
>> > > Quoting Boris Brezillon (2017-09-27 12:51:18)  
>> > > > +static void igt_vc4_trigger_purge(int fd)
>> > > > +{
>> > > 
>> > > May I suggest a /proc/sys/vm/drop_caches-esque interface?
>> > > For when you want to explicitly control reclaim.  
>> > 
>> > Eric suggested to add a debugfs entry to control the purge, I just
>> > thought I didn't really need it since I had a way to trigger this
>> > mechanism without adding yet another userspace -> kernel interface that
>> > will become part of the ABI and will have to be maintained forever.
>> > 
>> > If you think this is preferable, I'll go for the debugfs hook.  
>> 
>> I think you will find it useful in future. i915's drop-caches also has
>> options to make sure the GPU is idle, delayed frees are flushed, etc.
>> One thing we found useful is that through a debugfs interface, we can
>> pretend to be the shrinker/in-reclaim, setting
>> fs_reclaim_acquire(GFP_KERNEL) around the operation. That gives us
>> better lockdep coverage without having to trigger the shrinker.
>> 
>> Our experience says that you will make good use of a drop-caches
>> interface, it won't just be a one test wonder. :)
>
> Just had a look at i915_drop_caches_fops [1] and it seems
> over-complicated given what I can do in the VC4 driver: flush memory of
> BOs that are marked purgeable.
>
> Right now there's no shrinker object registered to the MM layer to help
> the system release memory. The only one who can trigger a purge is the
> VC4 BO allocator when it fails to allocate CMA memory.
> Also note that all VC4 BOs are backed by CMA mem, so I'm not sure
> plugging the BO purge system to the MM shrinker logic makes a lot of
> sense (is the MM core expecting shrinkers to release memory coming from
> the CMA pool?)

Given that general page cache stuff can live in CMA, freeing CMA memory
from your shrinker callback should be good for MM.  So, yeah, it would
be great if (in a later patchset) the mesa BO cache gets purged when the
system is busy doing non-graphics tasks and wants the memory back.

Also, I just landed the userspace side of BO labeling, so
/debug/dri/0/bo_stats will have a lot more useful information in it.  We
should probably have the mark-purgeable path in the kernel label the BO
as purgeable (erasing whatever previous label the BO had).  Then, maybe
after we can make it so that most allocations label their BOs, not just
debug Mesa builds.  Need to do some performance testing there.

> All this to say I'm not comfortable with designing a generic
> "drop_caches" debugfs hook that would take various options to delimit
> the scope of the cache-flush request. I'd prefer to have a simple
> "purge_purgeable_bos" file that does not care about the input value and
> flushes everything as soon as someone writes to it.
> But let's wait for Eric's feedback, maybe he has other plans and a
> better vision of what will be needed after this simple "purgeable-bo"
> implementation I'm about to post.

I thought your use of allocations to force purging was pretty elegant.
Also, it means that we'll be driving the purging code from the same
codepath as Mesa will be (BO allocation) rather than something slightly
different.

I think we'll want debugfs to test the shrinker path, since I don't know
of another good way for userspace to trigger it reliably without also
destabilizing the testing environment.


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Re: [Intel-gfx] [PATCH i-g-t 2/2] igt: Add VC4 purgeable BO tests

[Eric Anholt]

Boris Brezillon  writes:

> Signed-off-by: Boris Brezillon 

Another test we should have: Queue up a big rendering job (Copy a
2048x2048@32bpp BO?), mark the source purgeable, force the purge, wait
for rendering, make sure we correctly rendered, and maybe have some
sanity-checking of purgeable state of the BO.


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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] Fix rlim_cur compiler warnings when building on ARM.

[Patchwork]

== Series Details ==

Series: series starting with [1/3] Fix rlim_cur compiler warnings when building 
on ARM.
URL   : https://patchwork.freedesktop.org/series/30992/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
2885b10f99b4beeb046e75af8b8488c229f629d3 igt/gem_exec_schedule: Ignore 
set-priority failures on old kernels

with latest DRM-Tip kernel build CI_DRM_3146
aa884e1abdf2 drm-tip: 2017y-09m-27d-15h-39m-07s UTC integration manifest

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:444s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:473s
fi-blb-e6850 total:289  pass:224  dwarn:1   dfail:0   fail:0   skip:64  
time:418s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:528s
fi-bwr-2160  total:289  pass:184  dwarn:0   dfail:0   fail:0   skip:105 
time:279s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:504s
fi-byt-j1900 total:289  pass:254  dwarn:1   dfail:0   fail:0   skip:34  
time:495s
fi-cfl-s total:289  pass:222  dwarn:35  dfail:0   fail:0   skip:32  
time:540s
fi-cnl-y total:289  pass:258  dwarn:0   dfail:0   fail:4   skip:27  
time:659s
fi-elk-e7500 total:289  pass:230  dwarn:0   dfail:0   fail:0   skip:59  
time:421s
fi-glk-1 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:573s
fi-hsw-4770  total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:427s
fi-hsw-4770r total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:409s
fi-ilk-650   total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:433s
fi-ivb-3520m total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:496s
fi-ivb-3770  total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:470s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:477s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:583s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:591s
fi-pnv-d510  total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:548s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:460s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:745s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:491s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:473s
fi-snb-2520m total:289  pass:251  dwarn:0   dfail:0   fail:0   skip:38  
time:570s
fi-snb-2600  total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:420s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_261/
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Re: [Intel-gfx] [PATCH] drm/i915: Avoid using dev_priv->info.gen directly.

[Rodrigo Vivi]

On Wed, Sep 27, 2017 at 12:03 AM, Jani Nikula
 wrote:
> On Tue, 26 Sep 2017, Rodrigo Vivi  wrote:
>> On Tue, Sep 26, 2017 at 09:21:43PM +, Paulo Zanoni wrote:
>>> Em Ter, 2017-09-26 às 14:13 -0700, Rodrigo Vivi escreveu:
>>> > Let's stop this usage before it spreads so much.
>>> >
>>> > 1. This check is not part of usual searches happening when adding
>>> > new platform.
>>> > 2. There is already a duplication here with INTEL_INFO(dev_priv)->gen
>>> > and INTEL_GEN(dev_priv).
>>> >
>>> > So let's please avoid yet another way.
>>> >
>>> > Fixes: b22ca995ba1c ("drm/i915: prepare pipe for YCBCR420 output")
>>> > Fixes: 27082493e9c6 ("drm/i915/skl: Update DDB values atomically with
>>> > wms/plane attrs")
>>>
>>> Not sure if the Fixes tags are appropriate since this is not a bug fix.
>>
>> I wondered that... but since "dim fixes" provided me that tag along with the
>> list of people I should cc I decided to include here. I thought it
>> wouldn't hurt and also maybe good to propagate that to everywhere possible so
>> we don't recieve more code based on that usage.
>>
>> But I won't merge today to give time to get Jani's view on that.
>
> Please only use Fixes: for functional fixes that need to be
> backported. Like, nobody's going to be happier running a kernel they
> know uses INTEL_GEN() consistently.

Makes sense.
Merged to dinq without the "Fixes:" tags.
Thanks for all comments and reviews.

>
> BR,
> Jani.
>
>
>>
>>>
>>> Reviewed-by: Paulo Zanoni 
>>>
>>> > Cc: Lyude 
>>> > Cc: Ville Syrjälä 
>>> > Cc: Daniel Vetter 
>>> > Cc: Radhakrishna Sripada 
>>> > Cc: Hans de Goede 
>>> > Cc: Matt Roper 
>>> > Cc: Maarten Lankhorst 
>>> > Cc: Paulo Zanoni 
>>> > Cc: Ville Syrjala 
>>> > Cc: Imre Deak 
>>> > Cc: Shashank Sharma 
>>> > Cc: Jani Nikula 
>>> > Signed-off-by: Rodrigo Vivi 
>>> > ---
>>> >  drivers/gpu/drm/i915/intel_display.c | 6 +++---
>>> >  1 file changed, 3 insertions(+), 3 deletions(-)
>>> >
>>> > diff --git a/drivers/gpu/drm/i915/intel_display.c
>>> > b/drivers/gpu/drm/i915/intel_display.c
>>> > index 487b43ba3139..fba76f1bb6dd 100644
>>> > --- a/drivers/gpu/drm/i915/intel_display.c
>>> > +++ b/drivers/gpu/drm/i915/intel_display.c
>>> > @@ -9310,11 +9310,11 @@ static bool haswell_get_pipe_config(struct
>>> > intel_crtc *crtc,
>>> >pipe_config->gamma_mode =
>>> >I915_READ(GAMMA_MODE(crtc->pipe)) &
>>> > GAMMA_MODE_MODE_MASK;
>>> >
>>> > -  if (IS_BROADWELL(dev_priv) || dev_priv->info.gen >= 9) {
>>> > +  if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) {
>>> >u32 tmp = I915_READ(PIPEMISC(crtc->pipe));
>>> >bool clrspace_yuv = tmp &
>>> > PIPEMISC_OUTPUT_COLORSPACE_YUV;
>>> >
>>> > -  if (IS_GEMINILAKE(dev_priv) || dev_priv->info.gen >=
>>> > 10) {
>>> > +  if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv)
>>> > >= 10) {
>>> >bool blend_mode_420 = tmp &
>>> >  PIPEMISC_YUV420_MODE_F
>>> > ULL_BLEND;
>>> >
>>> > @@ -14217,7 +14217,7 @@ void intel_init_display_hooks(struct
>>> > drm_i915_private *dev_priv)
>>> >dev_priv->display.fdi_link_train =
>>> > hsw_fdi_link_train;
>>> >}
>>> >
>>> > -  if (dev_priv->info.gen >= 9)
>>> > +  if (INTEL_GEN(dev_priv) >= 9)
>>> >dev_priv->display.update_crtcs = skl_update_crtcs;
>>> >else
>>> >dev_priv->display.update_crtcs = intel_update_crtcs;
>
> --
> Jani Nikula, Intel Open Source Technology Center
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
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[Intel-gfx] ✗ Fi.CI.IGT: warning for RFC: drm: Allow driver-specific ioctls to be registered

[Patchwork]

== Series Details ==

Series: RFC: drm: Allow driver-specific ioctls to be registered
URL   : https://patchwork.freedesktop.org/series/30962/
State : warning

== Summary ==

Test gem_bad_reloc:
Subgroup negative-reloc-lut-bsd:
pass   -> DMESG-WARN (shard-hsw)
Subgroup negative-reloc-vebox:
pass   -> DMESG-WARN (shard-hsw)
Test gem_exec_schedule:
Subgroup fifo-blt:
pass   -> DMESG-WARN (shard-hsw)
Test prime_mmap:
Subgroup test_refcounting:
pass   -> DMESG-WARN (shard-hsw)
Subgroup test_userptr:
dmesg-warn -> PASS   (shard-hsw) fdo#102939
Test gem_wait:
Subgroup invalid-buf:
pass   -> DMESG-WARN (shard-hsw)
Subgroup basic-busy-all:
pass   -> DMESG-WARN (shard-hsw)
Test pm_rpm:
Subgroup system-suspend-execbuf:
pass   -> DMESG-WARN (shard-hsw)
Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-B-frame-sequence:
pass   -> DMESG-WARN (shard-hsw)
Test gem_mmap_gtt:
Subgroup forked-big-copy:
pass   -> DMESG-WARN (shard-hsw)
Test prime_vgem:
Subgroup fence-wait-bsd:
pass   -> DMESG-WARN (shard-hsw)
Test kms_cursor_crc:
Subgroup cursor-256x256-sliding:
pass   -> DMESG-WARN (shard-hsw)
Subgroup cursor-256x256-random:
pass   -> DMESG-WARN (shard-hsw)
Test kms_universal_plane:
Subgroup universal-plane-pipe-B-functional:
pass   -> DMESG-WARN (shard-hsw)
Test core_prop_blob:
Subgroup basic:
pass   -> DMESG-WARN (shard-hsw)
Test gem_render_copy_redux:
Subgroup interruptible:
pass   -> DMESG-WARN (shard-hsw)
Test prime_busy:
Subgroup basic-before-default:
pass   -> DMESG-WARN (shard-hsw)
Subgroup after-vebox:
pass   -> DMESG-WARN (shard-hsw)
Test gem_exec_params:
Subgroup invalid-fence-in:
pass   -> DMESG-WARN (shard-hsw)
Subgroup invalid-bsd2-flag-on-render:
pass   -> DMESG-WARN (shard-hsw)
Test gem_pipe_control_store_loop:
Subgroup reused-buffer:
pass   -> DMESG-WARN (shard-hsw)
Test kms_properties:
Subgroup plane-properties-legacy:
pass   -> DMESG-WARN (shard-hsw)
Test gem_eio:
Subgroup wait:
dmesg-warn -> PASS   (shard-hsw) fdo#102886 +1
Test kms_flip:
Subgroup flip-vs-dpms-off-vs-modeset:
pass   -> DMESG-WARN (shard-hsw)
Subgroup flip-vs-wf_vblank-interruptible:
dmesg-warn -> PASS   (shard-hsw)
Test gem_mmap_wc:
Subgroup write-cpu-read-wc:
pass   -> DMESG-WARN (shard-hsw)
Test kms_cursor_legacy:
Subgroup all-pipes-torture-bo:
pass   -> DMESG-WARN (shard-hsw)
Test prime_self_import:
Subgroup basic-llseek-bad:
pass   -> DMESG-WARN (shard-hsw)
Test perf:
Subgroup blocking:
fail   -> PASS   (shard-hsw) fdo#102252
Test gem_exec_parallel:
Subgroup render-contexts:
pass   -> DMESG-WARN (shard-hsw)
Test kms_atomic:
Subgroup atomic_invalid_params:
pass   -> DMESG-WARN (shard-hsw)

fdo#102939 https://bugs.freedesktop.org/show_bug.cgi?id=102939
fdo#102886 https://bugs.freedesktop.org/show_bug.cgi?id=102886
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-hswtotal:2429 pass:1309 dwarn:27  dfail:0   fail:10  skip:1083 
time:9461s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5833/shards.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for lib/igt_kms: Convert properties to be more atomic-like. (rev2)

[Patchwork]

== Series Details ==

Series: lib/igt_kms: Convert properties to be more atomic-like. (rev2)
URL   : https://patchwork.freedesktop.org/series/30903/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
2885b10f99b4beeb046e75af8b8488c229f629d3 igt/gem_exec_schedule: Ignore 
set-priority failures on old kernels

with latest DRM-Tip kernel build CI_DRM_3146
aa884e1abdf2 drm-tip: 2017y-09m-27d-15h-39m-07s UTC integration manifest

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:444s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:476s
fi-blb-e6850 total:289  pass:224  dwarn:1   dfail:0   fail:0   skip:64  
time:425s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:520s
fi-bwr-2160  total:289  pass:184  dwarn:0   dfail:0   fail:0   skip:105 
time:281s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:499s
fi-byt-j1900 total:289  pass:254  dwarn:1   dfail:0   fail:0   skip:34  
time:511s
fi-cfl-s total:289  pass:222  dwarn:27  dfail:0   fail:8   skip:32  
time:523s
fi-cnl-y total:289  pass:259  dwarn:0   dfail:0   fail:3   skip:27  
time:653s
fi-elk-e7500 total:289  pass:230  dwarn:0   dfail:0   fail:0   skip:59  
time:421s
fi-glk-1 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:563s
fi-hsw-4770  total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:428s
fi-hsw-4770r total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:407s
fi-ilk-650   total:289  pass:221  dwarn:0   dfail:0   fail:8   skip:60  
time:432s
fi-ivb-3520m total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:493s
fi-ivb-3770  total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:467s
fi-kbl-7500u total:289  pass:256  dwarn:1   dfail:0   fail:8   skip:24  
time:462s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:587s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:591s
fi-pnv-d510  total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:544s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:456s
fi-skl-6700k total:289  pass:257  dwarn:0   dfail:0   fail:8   skip:24  
time:740s
fi-skl-6770hqtotal:289  pass:261  dwarn:0   dfail:0   fail:8   skip:20  
time:487s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:479s
fi-snb-2520m total:289  pass:243  dwarn:0   dfail:0   fail:8   skip:38  
time:557s
fi-snb-2600  total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:417s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_259/
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[Intel-gfx] ✗ Fi.CI.IGT: warning for configure.ac: Install and distribute kabylake registers

[Patchwork]

== Series Details ==

Series: configure.ac: Install and distribute kabylake registers
URL   : https://patchwork.freedesktop.org/series/30973/
State : warning

== Summary ==

Test gem_double_irq_loop:
skip   -> PASS   (shard-hsw)
Test kms_frontbuffer_tracking:
Subgroup psr-2p-primscrn-pri-indfb-draw-mmap-cpu:
pass   -> SKIP   (shard-hsw)
Subgroup fbc-2p-pri-indfb-multidraw:
pass   -> SKIP   (shard-hsw)
Subgroup psr-1p-primscrn-shrfb-pgflip-blt:
pass   -> SKIP   (shard-hsw)
Subgroup fbc-1p-primscrn-cur-indfb-draw-pwrite:
skip   -> PASS   (shard-hsw)
Subgroup fbcpsr-2p-scndscrn-spr-indfb-fullscreen:
pass   -> SKIP   (shard-hsw)
Subgroup fbc-2p-primscrn-spr-indfb-draw-mmap-wc:
pass   -> SKIP   (shard-hsw)
Subgroup fbc-2p-scndscrn-spr-indfb-draw-mmap-wc:
pass   -> SKIP   (shard-hsw)
Subgroup fbc-2p-primscrn-spr-indfb-draw-mmap-gtt:
pass   -> SKIP   (shard-hsw)
Subgroup fbc-2p-scndscrn-cur-indfb-draw-pwrite:
pass   -> SKIP   (shard-hsw)
Subgroup fbcpsr-tilingchange:
pass   -> SKIP   (shard-hsw)
Subgroup fbcpsr-1p-offscren-pri-indfb-draw-mmap-gtt:
pass   -> SKIP   (shard-hsw)
Subgroup fbc-1p-primscrn-shrfb-pgflip-blt:
skip   -> PASS   (shard-hsw)
Subgroup fbc-2p-scndscrn-pri-shrfb-draw-mmap-wc:
pass   -> SKIP   (shard-hsw)
Subgroup psr-1p-primscrn-shrfb-msflip-blt:
pass   -> SKIP   (shard-hsw)
Subgroup fbcpsr-1p-primscrn-pri-indfb-draw-mmap-wc:
pass   -> SKIP   (shard-hsw)
Subgroup fbcpsr-rgb101010-draw-render:
pass   -> SKIP   (shard-hsw)
Subgroup psr-2p-scndscrn-pri-indfb-draw-blt:
pass   -> SKIP   (shard-hsw)
Subgroup psr-1p-primscrn-spr-indfb-draw-pwrite:
pass   -> SKIP   (shard-hsw)
Subgroup psr-rgb101010-draw-mmap-wc:
pass   -> SKIP   (shard-hsw)
Subgroup fbcpsr-2p-scndscrn-cur-indfb-move:
pass   -> SKIP   (shard-hsw)
Subgroup fbc-1p-primscrn-cur-indfb-draw-mmap-gtt:
skip   -> PASS   (shard-hsw)
Subgroup fbcpsr-1p-primscrn-indfb-plflip-blt:
pass   -> SKIP   (shard-hsw)
Subgroup psr-2p-primscrn-pri-shrfb-draw-mmap-wc:
pass   -> SKIP   (shard-hsw)
Subgroup fbc-2p-primscrn-pri-indfb-draw-mmap-wc:
pass   -> SKIP   (shard-hsw)
Subgroup psr-rgb101010-draw-render:
pass   -> SKIP   (shard-hsw)
Subgroup fbc-1p-primscrn-shrfb-msflip-blt:
skip   -> PASS   (shard-hsw)
Subgroup psr-1p-offscren-pri-indfb-draw-render:
pass   -> SKIP   (shard-hsw)
Subgroup fbc-1p-primscrn-indfb-pgflip-blt:
skip   -> PASS   (shard-hsw)
Subgroup psr-2p-scndscrn-pri-shrfb-draw-pwrite:
pass   -> SKIP   (shard-hsw)
Subgroup fbcpsr-rgb101010-draw-mmap-wc:
pass   -> SKIP   (shard-hsw)
Subgroup fbcpsr-1p-primscrn-cur-indfb-onoff:
pass   -> SKIP   (shard-hsw)
Subgroup psr-1p-primscrn-cur-indfb-onoff:
pass   -> SKIP   (shard-hsw)
Subgroup fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite:
pass   -> SKIP   (shard-hsw)
Subgroup psr-2p-primscrn-indfb-msflip-blt:
pass   -> SKIP   (shard-hsw)
Subgroup psr-2p-scndscrn-cur-indfb-draw-mmap-wc:
pass   -> SKIP   (shard-hsw)
Subgroup psr-1p-primscrn-shrfb-plflip-blt:
pass   -> SKIP   (shard-hsw)
Subgroup psr-2p-scndscrn-pri-indfb-draw-mmap-gtt:
pass   -> SKIP   (shard-hsw)
Subgroup fbc-2p-scndscrn-spr-indfb-draw-blt:
pass   -> SKIP   (shard-hsw)
Subgroup fbcpsr-2p-primscrn-indfb-msflip-blt:
pass   -> SKIP   (shard-hsw)
Subgroup psr-1p-offscren-pri-shrfb-draw-pwrite:
pass   -> SKIP   (shard-hsw)
Subgroup psr-1p-primscrn-spr-indfb-onoff:
pass   -> SKIP   (shard-hsw)
Subgroup fbc-1p-primscrn-indfb-msflip-blt:
skip   -> PASS   (shard-hsw)
Subgroup psr-2p-primscrn-spr-indfb-draw-mmap-cpu:
pass   -> SKIP   (shard-hsw)
Subgroup fbcpsr-1p-offscren-pri-indfb-draw-blt:
pass   -> SKIP   (shard-hsw)
Subgroup 

[Intel-gfx] [PATCH igt v3] igt/gem_exec_scheduler: HAS_SCHEDULER no longer means HAS_PREEMPTION

[Chris Wilson]

Michal wants to limit machines that can do preemption, which means that
we no longer can assume that if we have a scheduler for execbuf, that
implies we have preemption.

v2: Try a capability mask instead
v3: Pretty print the caps.

Signed-off-by: Chris Wilson 
---
 tests/gem_exec_schedule.c | 65 ++-
 1 file changed, 48 insertions(+), 17 deletions(-)

diff --git a/tests/gem_exec_schedule.c b/tests/gem_exec_schedule.c
index 79738ee1..ec0fd9ef 100644
--- a/tests/gem_exec_schedule.c
+++ b/tests/gem_exec_schedule.c
@@ -32,7 +32,12 @@
 #include "igt_rand.h"
 #include "igt_sysfs.h"
 
+#define BIT(x) (1ul << (x))
+
 #define LOCAL_PARAM_HAS_SCHEDULER 41
+#define   HAS_SCHEDULERBIT(0)
+#define   HAS_PRIORITY BIT(1)
+#define   HAS_PREEMPTION   BIT(2)
 #define LOCAL_CONTEXT_PARAM_PRIORITY 6
 
 #define LO 0
@@ -870,16 +875,33 @@ static void test_pi_ringfull(int fd, unsigned int engine)
munmap(result, 4096);
 }
 
-static bool has_scheduler(int fd)
+static unsigned int has_scheduler(int fd)
 {
drm_i915_getparam_t gp;
-   int has = -1;
+   unsigned int caps = 0;
+   char buf[200];
+   size_t len = 0;
 
gp.param = LOCAL_PARAM_HAS_SCHEDULER;
-   gp.value = 
+   gp.value = (int *)
drmIoctl(fd, DRM_IOCTL_I915_GETPARAM, );
 
-   return has > 0;
+   if (!caps)
+   return 0;
+
+   len = snprintf(buf, sizeof(buf), "Has kernel scheduler");
+   if (caps & HAS_PRIORITY)
+   len += snprintf(buf + len, sizeof(buf) - len,
+   "%s context priorities",
+   caps & (HAS_PRIORITY - 2) ? "," : " with");
+
+   if (caps & HAS_PREEMPTION)
+   len += snprintf(buf + len, sizeof(buf) - len,
+   "%s batchbuffer preemption",
+   caps & (HAS_PREEMPTION - 2) ? "," : " with");
+
+   igt_info("%s.\n", buf);
+   return caps;
 }
 
 #define HAVE_EXECLISTS 0x1
@@ -920,14 +942,16 @@ out:
 igt_main
 {
const struct intel_execution_engine *e;
-   unsigned int caps = 0;
+   unsigned int exec_caps = 0;
+   unsigned int sched_caps = 0;
int fd = -1;
 
igt_skip_on_simulation();
 
igt_fixture {
fd = drm_open_driver_master(DRIVER_INTEL);
-   caps = print_welcome(fd);
+   exec_caps = print_welcome(fd);
+   sched_caps = has_scheduler(fd);
igt_require_gem(fd);
gem_require_mmap_wc(fd);
igt_fork_hang_detector(fd);
@@ -949,7 +973,7 @@ igt_main
 
igt_subtest_group {
igt_fixture {
-   igt_require(has_scheduler(fd));
+   igt_require(sched_caps & HAS_SCHEDULER);
ctx_has_priority(fd);
}
 
@@ -973,17 +997,23 @@ igt_main
igt_subtest_f("promotion-%s", e->name)
promotion(fd, e->exec_id | e->flags);
 
-   igt_subtest_f("preempt-%s", e->name)
-   preempt(fd, e->exec_id | e->flags, 0);
+   igt_subtest_group {
+   igt_fixture {
+   igt_require(sched_caps & 
HAS_PREEMPTION);
+   }
 
-   igt_subtest_f("preempt-contexts-%s", e->name)
-   preempt(fd, e->exec_id | e->flags, 
NEW_CTX);
+   igt_subtest_f("preempt-%s", e->name)
+   preempt(fd, e->exec_id | 
e->flags, 0);
 
-   igt_subtest_f("preempt-other-%s", e->name)
-   preempt_other(fd, e->exec_id | 
e->flags);
+   igt_subtest_f("preempt-contexts-%s", 
e->name)
+   preempt(fd, e->exec_id | 
e->flags, NEW_CTX);
 
-   igt_subtest_f("preempt-self-%s", e->name)
-   preempt_self(fd, e->exec_id | e->flags);
+   igt_subtest_f("preempt-other-%s", 
e->name)
+   preempt_other(fd, e->exec_id | 
e->flags);
+
+   igt_subtest_f("preempt-self-%s", 
e->name)
+   preempt_self(fd, e->exec_id | 
e->flags);
+   }
 
igt_subtest_f("deep-%s", e->name)
deep(fd, e->exec_id | e->flags);
@@ -999,17 +1029,18 @@ igt_main
 
igt_subtest_group {
igt_fixture {
-   

[Intel-gfx] ✗ Fi.CI.IGT: failure for benchmarks: Actually build LIBDRM_INTEL_BENCHMARKS

[Patchwork]

== Series Details ==

Series: benchmarks: Actually build LIBDRM_INTEL_BENCHMARKS
URL   : https://patchwork.freedesktop.org/series/30970/
State : failure

== Summary ==

Test kms_flip_tiling:
Subgroup flip-changes-tiling-Y:
pass   -> SKIP   (shard-hsw)
Subgroup flip-to-Yf-tiled:
pass   -> SKIP   (shard-hsw)
Subgroup flip-Y-tiled:
pass   -> SKIP   (shard-hsw)
Subgroup flip-Yf-tiled:
pass   -> SKIP   (shard-hsw)
Test kms_flip:
Subgroup wf_vblank-vs-dpms:
skip   -> PASS   (shard-hsw) fdo#102614 +4
Subgroup 2x-flip-vs-absolute-wf_vblank-interruptible:
pass   -> SKIP   (shard-hsw)
Subgroup flip-vs-rmfb:
skip   -> PASS   (shard-hsw)
Subgroup wf_vblank-vs-dpms-interruptible:
skip   -> PASS   (shard-hsw)
Subgroup plain-flip-interruptible:
skip   -> PASS   (shard-hsw)
Subgroup vblank-vs-modeset-suspend-interruptible:
skip   -> PASS   (shard-hsw)
Subgroup dpms-vs-vblank-race:
pass   -> FAIL   (shard-hsw)
Subgroup flip-vs-absolute-wf_vblank:
skip   -> PASS   (shard-hsw) fdo#100368 +2
Subgroup vblank-vs-hang-interruptible:
skip   -> PASS   (shard-hsw)
Subgroup bo-too-big:
skip   -> PASS   (shard-hsw)
Subgroup flip-vs-panning-vs-hang-interruptible:
skip   -> PASS   (shard-hsw)
Subgroup 2x-dpms-vs-vblank-race:
pass   -> SKIP   (shard-hsw)
Subgroup 2x-wf_vblank:
pass   -> SKIP   (shard-hsw)
Subgroup absolute-wf_vblank:
skip   -> PASS   (shard-hsw)
Subgroup vblank-vs-modeset-rpm:
skip   -> PASS   (shard-hsw)
Subgroup flip-vs-modeset-vs-hang-interruptible:
skip   -> PASS   (shard-hsw)
Subgroup render-flip-vs-panning:
skip   -> PASS   (shard-hsw)
Subgroup single-buffer-flip-vs-dpms-off-vs-modeset-interruptible:
skip   -> PASS   (shard-hsw)
Subgroup rcs-wf_vblank-vs-modeset-interruptible:
skip   -> PASS   (shard-hsw)
Subgroup 2x-flip-vs-bad-tiling:
pass   -> SKIP   (shard-hsw)
Subgroup 2x-flip-vs-panning-vs-hang-interruptible:
pass   -> SKIP   (shard-hsw)
Subgroup 2x-vblank-vs-dpms-suspend:
pass   -> SKIP   (shard-hsw)
Subgroup blt-flip-vs-panning-interruptible:
skip   -> PASS   (shard-hsw)
Subgroup 2x-nonexisting-fb:
pass   -> SKIP   (shard-hsw)
Subgroup 2x-wf_vblank-interruptible:
pass   -> SKIP   (shard-hsw)
Subgroup 2x-rcs-wf_vblank-vs-dpms:
pass   -> SKIP   (shard-hsw)
Subgroup 2x-flip-vs-fences-interruptible:
pass   -> SKIP   (shard-hsw)
Subgroup vblank-vs-dpms-suspend:
skip   -> PASS   (shard-hsw)
Subgroup 2x-plain-flip-fb-recreate-interruptible:
pass   -> SKIP   (shard-hsw)
Subgroup 2x-blt-wf_vblank-vs-modeset:
pass   -> SKIP   (shard-hsw)
Subgroup 2x-blt-wf_vblank-vs-modeset-interruptible:
pass   -> SKIP   (shard-hsw)
Subgroup flip-vs-dpms-off-vs-modeset:
fail   -> PASS   (shard-hsw)
Subgroup 2x-plain-flip-ts-check:
pass   -> SKIP   (shard-hsw)
Subgroup 2x-vblank-vs-suspend:
pass   -> SKIP   (shard-hsw)
Subgroup absolute-wf_vblank-interruptible:
skip   -> PASS   (shard-hsw)
Subgroup 2x-flip-vs-modeset-interruptible:
pass   -> SKIP   (shard-hsw)
Subgroup busy-flip:
skip   -> PASS   (shard-hsw)
Subgroup flip-vs-wf_vblank-interruptible:
skip   -> PASS   (shard-hsw)
Subgroup 2x-blt-wf_vblank-vs-dpms-interruptible:
pass   -> SKIP   (shard-hsw)
Subgroup 2x-wf_vblank-ts-check-interruptible:
pass   -> SKIP   (shard-hsw)
Subgroup 2x-wf_vblank-vs-modeset-interruptible:
pass   -> SKIP   (shard-hsw)
Subgroup 2x-vblank-vs-modeset-suspend-interruptible:
pass   -> SKIP   (shard-hsw)
Subgroup bo-too-big-interruptible:
skip   -> PASS   (shard-hsw)
Subgroup 2x-rcs-wf_vblank-vs-dpms-interruptible:
pass   -> SKIP   (shard-hsw)
   

[Intel-gfx] [PATCH i-g-t v2 1/8] tests: Stop looking at plane private members

[Maarten Lankhorst]

Most of these tests have no reason to look at those members,
so try other ways of getting the information.

Signed-off-by: Maarten Lankhorst 
---
 lib/igt_kms.h |  21 
 tests/kms_atomic_transition.c | 117 +-
 tests/kms_busy.c  |   5 +-
 tests/kms_concurrent.c|   4 +-
 tests/kms_cursor_legacy.c |   6 +--
 tests/kms_fbc_crc.c   |   3 +-
 tests/kms_panel_fitting.c |  14 +
 tests/kms_plane_scaling.c |  14 +
 tests/kms_rmfb.c  |   2 +-
 tests/kms_rotation_crc.c  |  10 
 10 files changed, 93 insertions(+), 103 deletions(-)

diff --git a/lib/igt_kms.h b/lib/igt_kms.h
index 3d1061fa08c8..62197dcfea7b 100644
--- a/lib/igt_kms.h
+++ b/lib/igt_kms.h
@@ -556,6 +556,27 @@ static inline bool igt_output_is_connected(igt_output_t 
*output)
igt_assert_lt(0, drmModeAtomicAddProperty(req, 
output->config.connector->connector_id,\
  
output->config.atomic_props_connector[prop], value))
 
+/*
+ * igt_pipe_refresh:
+ * @display: a pointer to an #igt_display_t structure
+ * @pipe: Pipe to refresh
+ * @force: Should be set to true if mode_blob is no longer considered
+ * to be valid, for example after doing an atomic commit during fork or 
closing display fd.
+ *
+ * Requests the pipe to be part of the state on next update.
+ * This is useful when state may have been out of sync after
+ * a fork, or we just want to be sure the pipe is included
+ * in the next commit.
+ */
+static inline void
+igt_pipe_refresh(igt_display_t *display, enum pipe pipe, bool force)
+{
+   if (force)
+   display->pipes[pipe].mode_blob = 0;
+
+   display->pipes[pipe].mode_changed = true;
+}
+
 void igt_enable_connectors(void);
 void igt_reset_connectors(void);
 
diff --git a/tests/kms_atomic_transition.c b/tests/kms_atomic_transition.c
index e22763bdf94b..48823a09aed2 100644
--- a/tests/kms_atomic_transition.c
+++ b/tests/kms_atomic_transition.c
@@ -46,6 +46,11 @@ struct plane_parms {
 
 #define hweight32 __builtin_popcount
 
+/* globals for fence support */
+int *timeline;
+pthread_t *thread;
+int *seqno;
+
 static void
 run_primary_test(igt_display_t *display, enum pipe pipe, igt_output_t *output)
 {
@@ -89,9 +94,34 @@ run_primary_test(igt_display_t *display, enum pipe pipe, 
igt_output_t *output)
igt_remove_fb(display->drm_fd, );
 }
 
+static void *fence_inc_thread(void *arg)
+{
+   int t = *((int *) arg);
+
+   pthread_detach(pthread_self());
+
+   usleep(5000);
+   sw_sync_timeline_inc(t, 1);
+   return NULL;
+}
+
+static void configure_fencing(igt_plane_t *plane)
+{
+   int i, fd, ret;
+
+   i = plane->index;
+
+   seqno[i]++;
+   fd = sw_sync_timeline_create_fence(timeline[i], seqno[i]);
+   igt_plane_set_fence_fd(plane, fd);
+   close(fd);
+   ret = pthread_create([i], NULL, fence_inc_thread, [i]);
+   igt_assert_eq(ret, 0);
+}
+
 static void
 wm_setup_plane(igt_display_t *display, enum pipe pipe,
-  uint32_t mask, struct plane_parms *parms)
+  uint32_t mask, struct plane_parms *parms, bool fencing)
 {
igt_plane_t *plane;
 
@@ -108,6 +138,9 @@ wm_setup_plane(igt_display_t *display, enum pipe pipe,
continue;
}
 
+   if (fencing)
+   configure_fencing(plane);
+
igt_plane_set_fb(plane, parms[i].fb);
igt_fb_set_size(parms[i].fb, plane, parms[i].width, 
parms[i].height);
igt_plane_set_size(plane, parms[i].width, parms[i].height);
@@ -136,7 +169,7 @@ static bool 
skip_on_unsupported_nonblocking_modeset(igt_display_t *display)
 
/* Force the next state to update all crtc's, to synchronize with the 
nonblocking modeset. */
for_each_pipe(display, pipe)
-   display->pipes[pipe].mode_changed = true;
+   igt_pipe_refresh(display, pipe, false);
 
return false;
 }
@@ -183,6 +216,7 @@ static void set_sprite_wh(igt_display_t *display, enum pipe 
pipe,
 
 static void setup_parms(igt_display_t *display, enum pipe pipe,
const drmModeModeInfo *mode,
+   struct igt_fb *primary_fb,
struct igt_fb *argb_fb,
struct igt_fb *sprite_fb,
struct plane_parms *parms)
@@ -205,7 +239,7 @@ static void setup_parms(igt_display_t *display, enum pipe 
pipe,
int i = plane->index;
 
if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
-   parms[i].fb = plane->fb;
+   parms[i].fb = primary_fb;
parms[i].width = mode->hdisplay;
parms[i].height = mode->vdisplay;
} else if (plane->type == DRM_PLANE_TYPE_CURSOR) {
@@ -242,7 +276,7 @@ retry:

[Intel-gfx] [PATCH i-g-t v2 7/8] igt/kms_rotation_crc : Fix flip tests for sprite plane

[Maarten Lankhorst]

This test was flipping the primary plane instead of the sprite plane.
Flip the correct plane to make the test pass properly.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102691
Signed-off-by: Maarten Lankhorst 
---
 tests/kms_rotation_crc.c | 23 +--
 1 file changed, 17 insertions(+), 6 deletions(-)

diff --git a/tests/kms_rotation_crc.c b/tests/kms_rotation_crc.c
index 4932a0d44410..b8327dfa0d83 100644
--- a/tests/kms_rotation_crc.c
+++ b/tests/kms_rotation_crc.c
@@ -332,6 +332,9 @@ static void test_plane_rotation(data_t *data, int 
plane_type)
enum igt_commit_style commit = COMMIT_LEGACY;
int ret;
 
+   if (data->flips && plane_type != DRM_PLANE_TYPE_PRIMARY)
+   igt_require(data->display.is_atomic);
+
if (plane_type == DRM_PLANE_TYPE_PRIMARY || plane_type == 
DRM_PLANE_TYPE_CURSOR)
commit = COMMIT_UNIVERSAL;
 
@@ -390,12 +393,20 @@ static void test_plane_rotation(data_t *data, int 
plane_type)
 * check CRC against that one as well.
 */
if (data->flips) {
-   ret = drmModePageFlip(data->gfx_fd,
- 
output->config.crtc->crtc_id,
- data->fb_flip.fb_id,
- DRM_MODE_PAGE_FLIP_EVENT,
- NULL);
-   igt_assert_eq(ret, 0);
+   igt_plane_set_fb(plane, >fb_flip);
+   if (data->rotation == IGT_ROTATION_90 || 
data->rotation == IGT_ROTATION_270)
+   igt_plane_set_size(plane, 
data->fb.height, data->fb.width);
+
+   if (plane_type != DRM_PLANE_TYPE_PRIMARY) {
+   igt_display_commit_atomic(display, 
DRM_MODE_PAGE_FLIP_EVENT | DRM_MODE_ATOMIC_NONBLOCK, NULL);
+   } else {
+   ret = drmModePageFlip(data->gfx_fd,
+   
output->config.crtc->crtc_id,
+   data->fb_flip.fb_id,
+   
DRM_MODE_PAGE_FLIP_EVENT,
+   NULL);
+   igt_assert_eq(ret, 0);
+   }
wait_for_pageflip(data->gfx_fd);
igt_pipe_crc_collect_crc(data->pipe_crc,
 _output);
-- 
2.14.1

___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH i-g-t v2 5/8] lib/igt_kms: Rework plane properties to be more atomic, v2.

[Maarten Lankhorst]

In the future I want to allow tests to commit more properties,
but for this to work I have to fix all properties to work better
with atomic commit. Instead of special casing each
property make a bitmask for all property changed flags, and try to
commit all properties.

Changes since v1:
- Remove special dumping of src and crtc coordinates.
- Dump all modified coordinates.

Signed-off-by: Maarten Lankhorst 
---
 lib/igt_kms.c| 292 +--
 lib/igt_kms.h|  59 
 tests/kms_atomic_interruptible.c |  12 +-
 tests/kms_rotation_crc.c |   4 +-
 4 files changed, 159 insertions(+), 208 deletions(-)

diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index 07d2074c2b1a..3181ee605195 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -192,11 +192,11 @@ const char 
*igt_connector_prop_names[IGT_NUM_CONNECTOR_PROPS] = {
 
 /*
  * Retrieve all the properies specified in props_name and store them into
- * plane->atomic_props_plane.
+ * plane->props.
  */
 static void
-igt_atomic_fill_plane_props(igt_display_t *display, igt_plane_t *plane,
-   int num_props, const char **prop_names)
+igt_fill_plane_props(igt_display_t *display, igt_plane_t *plane,
+int num_props, const char **prop_names)
 {
drmModeObjectPropertiesPtr props;
int i, j, fd;
@@ -214,7 +214,7 @@ igt_atomic_fill_plane_props(igt_display_t *display, 
igt_plane_t *plane,
if (strcmp(prop->name, prop_names[j]) != 0)
continue;
 
-   plane->atomic_props_plane[j] = props->props[i];
+   plane->props[j] = props->props[i];
break;
}
 
@@ -1659,7 +1659,6 @@ void igt_display_init(igt_display_t *display, int drm_fd)
drmModeRes *resources;
drmModePlaneRes *plane_resources;
int i;
-   int is_atomic = 0;
 
memset(display, 0, sizeof(igt_display_t));
 
@@ -1679,7 +1678,9 @@ void igt_display_init(igt_display_t *display, int drm_fd)
igt_assert_f(display->pipes, "Failed to allocate memory for %d 
pipes\n", display->n_pipes);
 
drmSetClientCap(drm_fd, DRM_CLIENT_CAP_UNIVERSAL_PLANES, 1);
-   is_atomic = drmSetClientCap(drm_fd, DRM_CLIENT_CAP_ATOMIC, 1);
+   if (drmSetClientCap(drm_fd, DRM_CLIENT_CAP_ATOMIC, 1) == 0)
+   display->is_atomic = 1;
+
plane_resources = drmModeGetPlaneResources(display->drm_fd);
igt_assert(plane_resources);
 
@@ -1776,19 +1777,15 @@ void igt_display_init(igt_display_t *display, int 
drm_fd)
plane->type = type;
plane->pipe = pipe;
plane->drm_plane = drm_plane;
-   plane->fence_fd = -1;
+   plane->values[IGT_PLANE_IN_FENCE_FD] = ~0ULL;
 
-   if (is_atomic == 0) {
-   display->is_atomic = 1;
-   igt_atomic_fill_plane_props(display, plane, 
IGT_NUM_PLANE_PROPS, igt_plane_prop_names);
-   }
+   igt_fill_plane_props(display, plane, 
IGT_NUM_PLANE_PROPS, igt_plane_prop_names);
 
get_plane_property(display->drm_fd, drm_plane->plane_id,
   "rotation",
-  >rotation_property,
-  _value,
+  >props[IGT_PLANE_ROTATION],
+  >values[IGT_PLANE_ROTATION],
   NULL);
-   plane->rotation = (igt_rotation_t)prop_value;
}
 
/*
@@ -1805,8 +1802,10 @@ void igt_display_init(igt_display_t *display, int drm_fd)
 
pipe->n_planes = n_planes;
 
-   for_each_plane_on_pipe(display, i, plane)
-   plane->fb_changed = true;
+   for_each_plane_on_pipe(display, i, plane) {
+   igt_plane_set_prop_changed(plane, IGT_PLANE_FB_ID);
+   igt_plane_set_prop_changed(plane, IGT_PLANE_CRTC_ID);
+   }
 
pipe->mode_changed = true;
}
@@ -2070,18 +2069,7 @@ bool igt_pipe_get_property(igt_pipe_t *pipe, const char 
*name,
 
 static uint32_t igt_plane_get_fb_id(igt_plane_t *plane)
 {
-   if (plane->fb)
-   return plane->fb->fb_id;
-   else
-   return 0;
-}
-
-static uint32_t igt_plane_get_fb_gem_handle(igt_plane_t *plane)
-{
-   if (plane->fb)
-   return plane->fb->gem_handle;
-   else
-   return 0;
+   return plane->values[IGT_PLANE_FB_ID];
 }
 
 #define CHECK_RETURN(r, fail) {\
@@ -2090,9 +2078,6 @@ static uint32_t igt_plane_get_fb_gem_handle(igt_plane_t 
*plane)

[Intel-gfx] [PATCH i-g-t v2 6/8] lib/igt_kms: Rework pipe properties to be more atomic, v2.

[Maarten Lankhorst]

In the future I want to allow tests to commit more properties,
but for this to work I have to fix all properties to work better
with atomic commit. Instead of special casing each
property make a bitmask for all property changed flags, and try to
commit all properties.

This has been the most involved one, since legacy pipe commit still
handles a lot of the properties differently from the rest.

Changes since v1:
- Dump all changed properties on commit.
- Fix bug in igt_pipe_refresh().

Signed-off-by: Maarten Lankhorst 
---
 lib/igt_kms.c | 213 --
 lib/igt_kms.h |  77 ++
 tests/kms_atomic_interruptible.c  |   4 +-
 tests/kms_atomic_transition.c |   2 +-
 tests/kms_crtc_background_color.c |   2 +-
 5 files changed, 144 insertions(+), 154 deletions(-)

diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index 3181ee605195..23bb543efd61 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -259,8 +259,8 @@ igt_atomic_fill_connector_props(igt_display_t *display, 
igt_output_t *output,
 }
 
 static void
-igt_atomic_fill_pipe_props(igt_display_t *display, igt_pipe_t *pipe,
-   int num_crtc_props, const char **crtc_prop_names)
+igt_fill_pipe_props(igt_display_t *display, igt_pipe_t *pipe,
+   int num_crtc_props, const char **crtc_prop_names)
 {
drmModeObjectPropertiesPtr props;
int i, j, fd;
@@ -278,7 +278,7 @@ igt_atomic_fill_pipe_props(igt_display_t *display, 
igt_pipe_t *pipe,
if (strcmp(prop->name, crtc_prop_names[j]) != 0)
continue;
 
-   pipe->atomic_props_crtc[j] = props->props[i];
+   pipe->props[j] = props->props[i];
break;
}
 
@@ -1690,7 +1690,6 @@ void igt_display_init(igt_display_t *display, int drm_fd)
int p = 1;
int j, type;
uint8_t last_plane = 0, n_planes = 0;
-   uint64_t prop_value;
 
pipe->crtc_id = resources->crtcs[i];
pipe->display = display;
@@ -1700,29 +1699,12 @@ void igt_display_init(igt_display_t *display, int 
drm_fd)
pipe->planes = NULL;
pipe->out_fence_fd = -1;
 
+   igt_fill_pipe_props(display, pipe, IGT_NUM_CRTC_PROPS, 
igt_crtc_prop_names);
+
get_crtc_property(display->drm_fd, pipe->crtc_id,
-   "background_color",
-   >background_property,
-   _value,
+   "background_color", NULL,
+   >values[IGT_CRTC_BACKGROUND],
NULL);
-   pipe->background = (uint32_t)prop_value;
-   get_crtc_property(display->drm_fd, pipe->crtc_id,
- "DEGAMMA_LUT",
- >degamma_property,
- NULL,
- NULL);
-   get_crtc_property(display->drm_fd, pipe->crtc_id,
- "CTM",
- >ctm_property,
- NULL,
- NULL);
-   get_crtc_property(display->drm_fd, pipe->crtc_id,
- "GAMMA_LUT",
- >gamma_property,
- NULL,
- NULL);
-
-   igt_atomic_fill_pipe_props(display, pipe, IGT_NUM_CRTC_PROPS, 
igt_crtc_prop_names);
 
/* count number of valid planes */
for (j = 0; j < plane_resources->count_planes; j++) {
@@ -1807,7 +1789,7 @@ void igt_display_init(igt_display_t *display, int drm_fd)
igt_plane_set_prop_changed(plane, IGT_PLANE_CRTC_ID);
}
 
-   pipe->mode_changed = true;
+   igt_pipe_refresh(display, i, false);
}
 
/*
@@ -2284,7 +2266,7 @@ static int igt_primary_plane_commit_legacy(igt_plane_t 
*primary,
 
if (!igt_plane_is_prop_changed(primary, IGT_PLANE_FB_ID) &&
!(primary->changed & IGT_PLANE_COORD_CHANGED_MASK) &&
-   !primary->pipe->mode_changed)
+   !igt_pipe_obj_is_prop_changed(primary->pipe, IGT_CRTC_MODE_ID))
return 0;
 
crtc_id = pipe->crtc_id;
@@ -2353,6 +2335,16 @@ static int igt_plane_commit(igt_plane_t *plane,
}
 }
 
+static bool is_atomic_prop(enum igt_atomic_crtc_properties prop)
+{
+   if (prop == IGT_CRTC_MODE_ID ||
+  prop == IGT_CRTC_ACTIVE ||
+  prop == IGT_CRTC_OUT_FENCE_PTR)
+   return true;
+
+   return false;
+}
+
 /*
  * Commit all plane changes to an output.  Note that if @s is COMMIT_LEGACY,
  * enabling/disabling the primary 

[Intel-gfx] [PATCH i-g-t v2 4/8] lib/igt_kms: Rework connector properties to be more atomic, v2.

[Maarten Lankhorst]

In the future I want to allow tests to commit more properties,
but for this to work I have to fix all properties to work better
with atomic commit. Instead of special casing each
property make a bitmask for all property changed flags, and try to
commit all properties.

Changs since v1:
- Mention which properties we set to what.
- Assert the property to be set is valid.

Signed-off-by: Maarten Lankhorst 
---
 lib/igt_kms.c| 44 +++-
 lib/igt_kms.h| 35 +++-
 tests/kms_atomic_interruptible.c |  4 ++--
 tests/kms_panel_fitting.c|  2 +-
 4 files changed, 45 insertions(+), 40 deletions(-)

diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index d25090b05c70..07d2074c2b1a 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -248,7 +248,7 @@ igt_atomic_fill_connector_props(igt_display_t *display, 
igt_output_t *output,
if (strcmp(prop->name, conn_prop_names[j]) != 0)
continue;
 
-   output->config.atomic_props_connector[j] = 
props->props[i];
+   output->props[j] = props->props[i];
break;
}
 
@@ -1834,7 +1834,7 @@ void igt_display_init(igt_display_t *display, int drm_fd)
 
igt_output_refresh(output);
 
-   output->config.pipe_changed = true;
+   igt_output_set_prop_changed(output, IGT_CONNECTOR_CRTC_ID);
}
 
drmModeFreePlaneResources(plane_resources);
@@ -2514,23 +2514,24 @@ static void igt_atomic_prepare_crtc_commit(igt_pipe_t 
*pipe_obj, drmModeAtomicRe
 static void igt_atomic_prepare_connector_commit(igt_output_t *output, 
drmModeAtomicReq *req)
 {
 
-   struct kmstest_connector_config *config = >config;
+   int i;
 
-   if (config->connector_scaling_mode_changed)
-   igt_atomic_populate_connector_req(req, output, 
IGT_CONNECTOR_SCALING_MODE, config->connector_scaling_mode);
+   for (i = 0; i < IGT_NUM_CONNECTOR_PROPS; i++) {
+   if (!igt_output_is_prop_changed(output, i))
+   continue;
 
-   if (config->pipe_changed) {
-   uint32_t crtc_id = 0;
+   /* it's an error to try an unsupported feature */
+   igt_assert(output->props[i]);
 
-   if (output->config.pipe != PIPE_NONE)
-   crtc_id = output->config.crtc->crtc_id;
+   igt_debug("%s: Setting property \"%s\" to 
0x%"PRIx64"/%"PRIi64"\n",
+ igt_output_name(output), igt_connector_prop_names[i],
+ output->values[i], output->values[i]);
 
-   igt_atomic_populate_connector_req(req, output, 
IGT_CONNECTOR_CRTC_ID, crtc_id);
+   igt_assert_lt(0, drmModeAtomicAddProperty(req,
+ 
output->config.connector->connector_id,
+ output->props[i],
+ output->values[i]));
}
-   /*
-*  TODO: Add all other connector level properties here
-*/
-
 }
 
 /*
@@ -2625,11 +2626,10 @@ display_commit_changed(igt_display_t *display, enum 
igt_commit_style s)
for (i = 0; i < display->n_outputs; i++) {
igt_output_t *output = >outputs[i];
 
-   if (s != COMMIT_UNIVERSAL)
-   output->config.pipe_changed = false;
-
if (s == COMMIT_ATOMIC)
-   output->config.connector_scaling_mode_changed = false;
+   output->changed = 0;
+   else if (s != COMMIT_UNIVERSAL)
+   igt_output_clear_prop_changed(output, 
IGT_CONNECTOR_CRTC_ID);
}
 }
 
@@ -2873,18 +2873,16 @@ void igt_output_set_pipe(igt_output_t *output, enum 
pipe pipe)
if (pipe != PIPE_NONE)
display->pipes[pipe].mode_changed = true;
 
-   output->config.pipe_changed = true;
+   igt_output_set_prop_value(output, IGT_CONNECTOR_CRTC_ID, pipe == 
PIPE_NONE ? 0 : display->pipes[pipe].crtc_id);
 
igt_output_refresh(output);
 }
 
 void igt_output_set_scaling_mode(igt_output_t *output, uint64_t scaling_mode)
 {
-   output->config.connector_scaling_mode_changed = true;
-
-   output->config.connector_scaling_mode = scaling_mode;
+   igt_output_set_prop_value(output, IGT_CONNECTOR_SCALING_MODE, 
scaling_mode);
 
-   
igt_require(output->config.atomic_props_connector[IGT_CONNECTOR_SCALING_MODE]);
+   igt_require(output->props[IGT_CONNECTOR_SCALING_MODE]);
 }
 
 igt_plane_t *igt_output_get_plane(igt_output_t *output, int plane_idx)
diff --git a/lib/igt_kms.h b/lib/igt_kms.h
index 8dc118c961b7..1ef10e7d525c 100644
--- a/lib/igt_kms.h
+++ b/lib/igt_kms.h
@@ -131,10 +131,7 @@ struct kmstest_connector_config {
drmModeConnector *connector;
drmModeEncoder 

[Intel-gfx] [PATCH i-g-t v2 0/8] lib/igt_kms: Convert properties to be more atomic-like.

[Maarten Lankhorst]

Instead of having to special case each property when it's added,
I want to make sure that any test can add arbitrary properties without
having to add too much code. Some of the members I want to expose directly,
and I also add a way to set a blob as property for planes and pipes,
which will be useful for the upcoming plane color management stuff.

Now with bugfixes!

Maarten Lankhorst (8):
  tests: Stop looking at plane private members
  lib/igt_kms: Change output->pending_crtc_idx_mask to
output->pending_pipe
  lib/igt_kms: Commit primary plane when a modeset is forced on a pipe
  lib/igt_kms: Rework connector properties to be more atomic, v2.
  lib/igt_kms: Rework plane properties to be more atomic, v2.
  lib/igt_kms: Rework pipe properties to be more atomic, v2.
  igt/kms_rotation_crc : Fix flip tests for sprite plane
  tests: Rename kms_pipe_color to kms_color

 lib/igt_kms.c   | 587 +++-
 lib/igt_kms.h   | 154 -
 tests/Makefile.sources  |   2 +-
 tests/kms_atomic_interruptible.c|  20 +-
 tests/kms_atomic_transition.c   | 123 +++
 tests/kms_busy.c|   7 +-
 tests/{kms_pipe_color.c => kms_color.c} |   4 +-
 tests/kms_concurrent.c  |   4 +-
 tests/kms_crtc_background_color.c   |   2 +-
 tests/kms_cursor_legacy.c   |   8 +-
 tests/kms_fbc_crc.c |   3 +-
 tests/kms_panel_fitting.c   |  16 +-
 tests/kms_plane_scaling.c   |  14 +-
 tests/kms_rmfb.c|   2 +-
 tests/kms_rotation_crc.c|  37 +-
 15 files changed, 463 insertions(+), 520 deletions(-)
 rename tests/{kms_pipe_color.c => kms_color.c} (99%)

-- 
2.14.1

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[Intel-gfx] [PATCH i-g-t v2 3/8] lib/igt_kms: Commit primary plane when a modeset is forced on a pipe

[Maarten Lankhorst]

In between tests, some tests can do the following sequence:

(pipe C configured with FB)
igt_plane_set_fb(primary (pipe C), NULL);
/* Clear rotation property first */
igt_display_commit2(display, COMMIT_UNIVERSAL);

/* disable pipe */
igt_display_commit2(display, COMMIT_LEGACY);

This would result in PIPE_C not being properly disabled, which
will cause an error on the next mode. This can be seen when running
the full kms_rotation_crc testcase without --subtest, it will fail
on exhaust-fences because the bad-tiling subtest wasn't able to
disable pipe C correctly.

Testcase: kms_rotation_crc
Signed-off-by: Maarten Lankhorst 
---
 lib/igt_kms.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index a5db6bc493c2..d25090b05c70 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -2332,7 +2332,7 @@ static int igt_primary_plane_commit_legacy(igt_plane_t 
*primary,
igt_assert(!primary->rotation_changed);
 
if (!primary->fb_changed && !primary->position_changed &&
-   !primary->size_changed)
+   !primary->size_changed && !primary->pipe->mode_changed)
return 0;
 
crtc_id = pipe->crtc_id;
-- 
2.14.1

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[Intel-gfx] [PATCH i-g-t v2 8/8] tests: Rename kms_pipe_color to kms_color

[Maarten Lankhorst]

Rename kms_pipe_color to kms_color, and rename the invalid tests to 
pipe-invalid.
To prepare for adding support for plane color management.

Signed-off-by: Maarten Lankhorst 
---
 tests/Makefile.sources  | 2 +-
 tests/{kms_pipe_color.c => kms_color.c} | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)
 rename tests/{kms_pipe_color.c => kms_color.c} (99%)

diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 0adc28a014d2..c4d320ebc61b 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -177,6 +177,7 @@ TESTS_progs = \
kms_busy \
kms_ccs \
kms_chv_cursor_fail \
+   kms_color \
kms_concurrent \
kms_crtc_background_color \
kms_cursor_crc \
@@ -197,7 +198,6 @@ TESTS_progs = \
kms_mmio_vs_cs_flip \
kms_panel_fitting \
kms_pipe_b_c_ivb \
-   kms_pipe_color \
kms_pipe_crc_basic \
kms_plane \
kms_plane_lowres \
diff --git a/tests/kms_pipe_color.c b/tests/kms_color.c
similarity index 99%
rename from tests/kms_pipe_color.c
rename to tests/kms_color.c
index ccfc08e6be15..060a60152808 100644
--- a/tests/kms_pipe_color.c
+++ b/tests/kms_color.c
@@ -1205,10 +1205,10 @@ igt_main
igt_subtest_group
run_tests_for_pipe(, pipe);
 
-   igt_subtest_f("invalid-lut-sizes")
+   igt_subtest_f("pipe-invalid-lut-sizes")
invalid_lut_sizes();
 
-   igt_subtest_f("invalid-ctm-matrix-sizes")
+   igt_subtest_f("pipe-invalid-ctm-matrix-sizes")
invalid_ctm_matrix_sizes();
 
igt_fixture {
-- 
2.14.1

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[Intel-gfx] [PATCH i-g-t 3/3] meson: Disable the intel overlay on non-x86 builds.

[Eric Anholt]

It's got calls to rmb/wmb that end up not linking successfully.

Signed-off-by: Eric Anholt 
---
 meson.build | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/meson.build b/meson.build
index 1cc501f3062f..7a09228292fd 100644
--- a/meson.build
+++ b/meson.build
@@ -121,6 +121,8 @@ subdir('benchmarks')
 subdir('tools')
 if libdrm_intel.found()
subdir('assembler')
-   subdir('overlay')
+   if ['x86', 'x86_64'].contains(host_machine.cpu_family())
+   subdir('overlay')
+   endif
 endif
 subdir('man')
-- 
2.14.1

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[Intel-gfx] ✓ Fi.CI.BAT: success for igt/gem_exec_scheduler: HAS_SCHEDULER no longer means HAS_PREEMPTION (rev3)

[Patchwork]

== Series Details ==

Series: igt/gem_exec_scheduler: HAS_SCHEDULER no longer means HAS_PREEMPTION 
(rev3)
URL   : https://patchwork.freedesktop.org/series/30860/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
2885b10f99b4beeb046e75af8b8488c229f629d3 igt/gem_exec_schedule: Ignore 
set-priority failures on old kernels

with latest DRM-Tip kernel build CI_DRM_3146
aa884e1abdf2 drm-tip: 2017y-09m-27d-15h-39m-07s UTC integration manifest

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:445s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:471s
fi-blb-e6850 total:289  pass:224  dwarn:1   dfail:0   fail:0   skip:64  
time:422s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:525s
fi-bwr-2160  total:289  pass:184  dwarn:0   dfail:0   fail:0   skip:105 
time:281s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:504s
fi-byt-j1900 total:289  pass:254  dwarn:1   dfail:0   fail:0   skip:34  
time:503s
fi-cfl-s total:289  pass:223  dwarn:34  dfail:0   fail:0   skip:32  
time:541s
fi-cnl-y total:289  pass:258  dwarn:0   dfail:0   fail:4   skip:27  
time:678s
fi-elk-e7500 total:289  pass:230  dwarn:0   dfail:0   fail:0   skip:59  
time:419s
fi-glk-1 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:574s
fi-hsw-4770  total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:427s
fi-hsw-4770r total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:402s
fi-ilk-650   total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:441s
fi-ivb-3520m total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:493s
fi-ivb-3770  total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:474s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:472s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:577s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:593s
fi-pnv-d510  total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:543s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:460s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:750s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:504s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:481s
fi-snb-2520m total:289  pass:251  dwarn:0   dfail:0   fail:0   skip:38  
time:571s
fi-snb-2600  total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:418s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_262/
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[Intel-gfx] [PATCH i-g-t v2 2/8] lib/igt_kms: Change output->pending_crtc_idx_mask to output->pending_pipe

[Maarten Lankhorst]

igt_output_set_pipe with PIPE_ANY used to mean that we bind the output
to any pipe, but this is now a deprecated alias for PIPE_NONE, and
means the output will be unbound.

Because of this it's better to change output->pending_crtc_idx_mask to
an enum pipe, because only a single choice may be given for a pipe.

Signed-off-by: Maarten Lankhorst 
---
 lib/igt_kms.c | 46 ---
 lib/igt_kms.h |  2 +-
 tests/kms_atomic_transition.c |  4 ++--
 tests/kms_busy.c  |  2 +-
 tests/kms_cursor_legacy.c |  2 +-
 5 files changed, 26 insertions(+), 30 deletions(-)

diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index 7bcafc072f70..a5db6bc493c2 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -1561,9 +1561,10 @@ static void igt_display_log_shift(igt_display_t 
*display, int shift)
 static void igt_output_refresh(igt_output_t *output)
 {
igt_display_t *display = output->display;
-   unsigned long crtc_idx_mask;
+   unsigned long crtc_idx_mask = 0;
 
-   crtc_idx_mask = output->pending_crtc_idx_mask;
+   if (output->pending_pipe != PIPE_NONE)
+   crtc_idx_mask = 1 << output->pending_pipe;
 
kmstest_free_connector_config(>config);
 
@@ -1587,11 +1588,8 @@ static void igt_output_refresh(igt_output_t *output)
BROADCAST_RGB_FULL);
}
 
-   if (output->config.pipe == PIPE_NONE)
-   return;
-
LOG(display, "%s: Selecting pipe %s\n", output->name,
-   kmstest_pipe_name(output->config.pipe));
+   kmstest_pipe_name(output->pending_pipe));
 }
 
 static bool
@@ -1830,7 +1828,7 @@ void igt_display_init(igt_display_t *display, int drm_fd)
 * a pipe is set with igt_output_set_pipe().
 */
output->force_reprobe = true;
-   output->pending_crtc_idx_mask = 0;
+   output->pending_pipe = PIPE_NONE;
output->id = resources->connectors[i];
output->display = display;
 
@@ -1960,10 +1958,12 @@ static void igt_display_refresh(igt_display_t *display)
for (i = 0; i < display->n_outputs; i++) {
output = >outputs[i];
 
-   if (pipes_in_use & output->pending_crtc_idx_mask)
-   goto report_dup;
+   if (output->pending_pipe != PIPE_NONE) {
+   if (pipes_in_use & (1 << output->pending_pipe))
+   goto report_dup;
 
-   pipes_in_use |= output->pending_crtc_idx_mask;
+   pipes_in_use |= 1 << output->pending_pipe;
+   }
 
if (output->force_reprobe)
igt_output_refresh(output);
@@ -1975,11 +1975,11 @@ report_dup:
for (; i > 0; i--) {
igt_output_t *b = >outputs[i - 1];
 
-   igt_assert_f(output->pending_crtc_idx_mask !=
-b->pending_crtc_idx_mask,
+   igt_assert_f(output->pending_pipe !=
+b->pending_pipe,
 "%s and %s are both trying to use pipe %s\n",
 igt_output_name(output), igt_output_name(b),
-kmstest_pipe_name(ffs(b->pending_crtc_idx_mask) - 
1));
+kmstest_pipe_name(output->pending_pipe));
}
 }
 
@@ -1988,7 +1988,7 @@ static igt_pipe_t 
*igt_output_get_driving_pipe(igt_output_t *output)
igt_display_t *display = output->display;
enum pipe pipe;
 
-   if (!output->pending_crtc_idx_mask) {
+   if (output->pending_pipe == PIPE_NONE) {
/*
 * The user hasn't specified a pipe to use, return none.
 */
@@ -1998,7 +1998,7 @@ static igt_pipe_t 
*igt_output_get_driving_pipe(igt_output_t *output)
 * Otherwise, return the pending pipe (ie the pipe that should
 * drive this output after the commit()
 */
-   pipe = ffs(output->pending_crtc_idx_mask) - 1;
+   pipe = output->pending_pipe;
}
 
igt_assert(pipe >= 0 && pipe < display->n_pipes);
@@ -2051,7 +2051,7 @@ static igt_output_t *igt_pipe_get_output(igt_pipe_t *pipe)
for (i = 0; i < display->n_outputs; i++) {
igt_output_t *output = >outputs[i];
 
-   if (output->pending_crtc_idx_mask == (1 << pipe->pipe))
+   if (output->pending_pipe == pipe->pipe)
return output;
}
 
@@ -2860,22 +2860,18 @@ void igt_output_set_pipe(igt_output_t *output, enum 
pipe pipe)
 
igt_assert(output->name);
 
-   if (output->pending_crtc_idx_mask) {
+   if (output->pending_pipe != PIPE_NONE) {
old_pipe = igt_output_get_driving_pipe(output);
 
old_pipe->mode_changed = true;
}
 
-   if 

[Intel-gfx] [PATCH v4 1/2] drm/i915: Handle drm-layer errors in intel_dp_add_mst_connector

[James Ausmus]

Make intel_dp_add_mst_connector handle error returns from the drm_ calls.
Add intel_connector_free to support cleanup on the error path.

v2: Rename new function to avoid confusion, and simplify error
paths (Ville)

v3: Indentation fixup, style fixes (Ville)

v4: Clarify usage of intel_connector_free, and fix usage of
intel_connector_free

Cc: Ville Syrjälä 
Signed-off-by: James Ausmus 
---
 drivers/gpu/drm/i915/intel_display.c | 13 +
 drivers/gpu/drm/i915/intel_dp_mst.c  | 27 ++-
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 3 files changed, 36 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index c4b224a3a0ee..725014bf6f0f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6146,6 +6146,19 @@ struct intel_connector *intel_connector_alloc(void)
return connector;
 }
 
+/*
+ * Free the bits allocated by intel_connector_alloc.
+ * This should only be used after intel_connector_alloc has returned
+ * successfully, and before drm_connector_init returns successfully.
+ * Otherwise the destroy callbacks for the connector and the state should
+ * take care of proper cleanup/free
+ */
+void intel_connector_free(struct intel_connector *connector)
+{
+   kfree(to_intel_digital_connector_state(connector->base.state));
+   kfree(connector);
+}
+
 /* Simple connector->get_hw_state implementation for encoders that support only
  * one connector and no cloning and hence the encoder state determines the 
state
  * of the connector. */
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c 
b/drivers/gpu/drm/i915/intel_dp_mst.c
index 9a396f483f8b..8ceffad3e665 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -450,14 +450,20 @@ static struct drm_connector 
*intel_dp_add_mst_connector(struct drm_dp_mst_topolo
struct drm_device *dev = intel_dig_port->base.base.dev;
struct intel_connector *intel_connector;
struct drm_connector *connector;
-   int i;
+   int i, ret;
 
intel_connector = intel_connector_alloc();
if (!intel_connector)
return NULL;
 
connector = _connector->base;
-   drm_connector_init(dev, connector, _dp_mst_connector_funcs, 
DRM_MODE_CONNECTOR_DisplayPort);
+   ret = drm_connector_init(dev, connector, _dp_mst_connector_funcs,
+DRM_MODE_CONNECTOR_DisplayPort);
+   if (ret) {
+   intel_connector_free(intel_connector);
+   return NULL;
+   }
+
drm_connector_helper_add(connector, 
_dp_mst_connector_helper_funcs);
 
intel_connector->get_hw_state = intel_dp_mst_get_hw_state;
@@ -465,15 +471,26 @@ static struct drm_connector 
*intel_dp_add_mst_connector(struct drm_dp_mst_topolo
intel_connector->port = port;
 
for (i = PIPE_A; i <= PIPE_C; i++) {
-   drm_mode_connector_attach_encoder(_connector->base,
- 
_dp->mst_encoders[i]->base.base);
+   struct drm_encoder *enc = _dp->mst_encoders[i]->base.base;
+
+   ret = drm_mode_connector_attach_encoder(_connector->base,
+   enc);
+   if (ret)
+   goto err;
}
 
drm_object_attach_property(>base, 
dev->mode_config.path_property, 0);
drm_object_attach_property(>base, 
dev->mode_config.tile_property, 0);
 
-   drm_mode_connector_set_path_property(connector, pathprop);
+   ret = drm_mode_connector_set_path_property(connector, pathprop);
+   if (ret)
+   goto err;
+
return connector;
+
+err:
+   drm_connector_cleanup(connector);
+   return NULL;
 }
 
 static void intel_dp_register_mst_connector(struct drm_connector *connector)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 0cab667fff57..b549a0b45e57 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1360,6 +1360,7 @@ void intel_pps_unlock_regs_wa(struct drm_i915_private 
*dev_priv);
 void intel_encoder_destroy(struct drm_encoder *encoder);
 int intel_connector_init(struct intel_connector *);
 struct intel_connector *intel_connector_alloc(void);
+void intel_connector_free(struct intel_connector *connector);
 bool intel_connector_get_hw_state(struct intel_connector *connector);
 void intel_connector_attach_encoder(struct intel_connector *connector,
struct intel_encoder *encoder);
-- 
2.14.1

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[Intel-gfx] [PATCH 2/2] drm/i915: Use for_each_pipe in intel_dp_mst.c

[James Ausmus]

Use the helper instead of manually looping through pipes.

Suggested-by: Ville Syrjälä 
Signed-off-by: James Ausmus 
---
 drivers/gpu/drm/i915/intel_dp_mst.c | 17 +++--
 1 file changed, 11 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c 
b/drivers/gpu/drm/i915/intel_dp_mst.c
index 8ceffad3e665..adb105bf98e2 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -448,9 +448,11 @@ static struct drm_connector 
*intel_dp_add_mst_connector(struct drm_dp_mst_topolo
struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr);
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
struct drm_device *dev = intel_dig_port->base.base.dev;
+   struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_connector *intel_connector;
struct drm_connector *connector;
-   int i, ret;
+   enum pipe p;
+   int ret;
 
intel_connector = intel_connector_alloc();
if (!intel_connector)
@@ -470,8 +472,8 @@ static struct drm_connector 
*intel_dp_add_mst_connector(struct drm_dp_mst_topolo
intel_connector->mst_port = intel_dp;
intel_connector->port = port;
 
-   for (i = PIPE_A; i <= PIPE_C; i++) {
-   struct drm_encoder *enc = _dp->mst_encoders[i]->base.base;
+   for_each_pipe(dev_priv, p) {
+   struct drm_encoder *enc = _dp->mst_encoders[p]->base.base;
 
ret = drm_mode_connector_attach_encoder(_connector->base,
enc);
@@ -580,11 +582,14 @@ intel_dp_create_fake_mst_encoder(struct 
intel_digital_port *intel_dig_port, enum
 static bool
 intel_dp_create_fake_mst_encoders(struct intel_digital_port *intel_dig_port)
 {
-   int i;
+   struct drm_device *dev = intel_dig_port->base.base.dev;
+   struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_dp *intel_dp = _dig_port->dp;
+   enum pipe p;
 
-   for (i = PIPE_A; i <= PIPE_C; i++)
-   intel_dp->mst_encoders[i] = 
intel_dp_create_fake_mst_encoder(intel_dig_port, i);
+   for_each_pipe(dev_priv, p)
+   intel_dp->mst_encoders[p] =
+   intel_dp_create_fake_mst_encoder(intel_dig_port, p);
return true;
 }
 
-- 
2.14.1

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[Intel-gfx] [PATCH i-g-t v4 6/6] tests/kms_ccs: Test case for wrong aux buffer stride size

[Gabriel Krisman Bertazi]

Two scenarios tested:
  - unaligned stride
  - Stride too small

Signed-off-by: Gabriel Krisman Bertazi 
---
 tests/kms_ccs.c | 23 ++-
 1 file changed, 22 insertions(+), 1 deletion(-)

diff --git a/tests/kms_ccs.c b/tests/kms_ccs.c
index 2d7105eb1323..cb6e69c69ae5 100644
--- a/tests/kms_ccs.c
+++ b/tests/kms_ccs.c
@@ -35,14 +35,18 @@ enum test_flags {
TEST_BAD_ROTATION_90= 1 << 4,
TEST_NO_AUX_BUFFER  = 1 << 5,
TEST_BAD_CCS_HANDLE = 1 << 6,
+   TEST_BAD_AUX_STRIDE = 1 << 7,
 };
 
 #define TEST_FAIL_ON_ADDFB2 \
-   (TEST_BAD_PIXEL_FORMAT | TEST_NO_AUX_BUFFER | TEST_BAD_CCS_HANDLE)
+   (TEST_BAD_PIXEL_FORMAT | TEST_NO_AUX_BUFFER | TEST_BAD_CCS_HANDLE | \
+TEST_BAD_AUX_STRIDE)
 
 enum test_fb_flags {
FB_COMPRESSED   = 1 << 0,
FB_HAS_PLANE= 1 << 1,
+   FB_MISALIGN_AUX_STRIDE  = 1 << 2,
+   FB_SMALL_AUX_STRIDE = 1 << 3,
 };
 
 typedef struct {
@@ -324,6 +328,14 @@ static void generate_fb(data_t *data, struct igt_fb *fb,
int ccs_pitches = ALIGN(ccs_width * 1, 128);
int ccs_offsets = size[0];
 
+   if (fb_flags & FB_MISALIGN_AUX_STRIDE)
+   ccs_pitches -= 64;
+   else if (fb_flags & FB_SMALL_AUX_STRIDE) {
+   igt_skip_on_f(width <= 1024,
+ "FB already has the smallest possible 
stride\n");
+   ccs_pitches = ALIGN(ccs_width/2, 128);
+   }
+
size[1] = ccs_pitches * ALIGN(ccs_height, 32);
 
f.handles[0] = gem_create(data->drm_fd, size[0] + size[1]);
@@ -470,6 +482,11 @@ static void test_output(data_t *data)
try_config(data, fb_flags | FB_COMPRESSED);
}
 
+   if (data->flags & TEST_BAD_AUX_STRIDE) {
+   try_config(data, fb_flags | FB_COMPRESSED | 
FB_MISALIGN_AUX_STRIDE);
+   try_config(data, fb_flags | FB_COMPRESSED | 
FB_SMALL_AUX_STRIDE);
+   }
+
primary = igt_output_get_plane_type(data->output, 
DRM_PLANE_TYPE_PRIMARY);
igt_plane_set_fb(primary, NULL);
igt_plane_set_rotation(primary, IGT_ROTATION_0);
@@ -543,6 +560,10 @@ igt_main
data.flags = TEST_BAD_CCS_HANDLE;
igt_subtest_f("pipe-%s-ccs-on-another-bo", pipe_name)
test_output();
+
+   data.flags = TEST_BAD_AUX_STRIDE;
+   igt_subtest_f("pipe-%s-bad-aux-stride", pipe_name)
+   test_output();
}
 
igt_fixture
-- 
2.11.0

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[Intel-gfx] [PATCH i-g-t v4 2/6] lib/igt_kms: Fix off-by-one bug on skip of missing pipe

[Gabriel Krisman Bertazi]

display->n_pipes is zero-indexed, so N returned in
igt_display_get_n_pipes is already not a valid pipe.  This patch
prevents kms_ccs from going nuts when testing the first unxesting pipe.

Signed-off-by: Gabriel Krisman Bertazi 
Reviewed-by: Maarten Lankhorst 
---
 lib/igt_kms.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index 7bcafc072f70..c7b169afba54 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -1865,7 +1865,7 @@ void igt_display_require_output_on_pipe(igt_display_t 
*display, enum pipe pipe)
 {
igt_output_t *output;
 
-   igt_skip_on_f(igt_display_get_n_pipes(display) < pipe,
+   igt_skip_on_f(pipe >= igt_display_get_n_pipes(display),
  "Pipe %s does not exist.\n", kmstest_pipe_name(pipe));
 
for_each_valid_output_on_pipe(display, pipe, output)
-- 
2.11.0

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[Intel-gfx] [PATCH i-g-t v4 3/6] tests/kms_ccs: Prevent segfault if pipe is not supported

[Gabriel Krisman Bertazi]

for_each_plane_on_pipe() indexes bad memory when iterating over an invalid
pipe.  Make sure the pipe exists before trying to use it.  This prevents
the crash below:

root@ideacentre:~# igt-gpu-tools/tests/kms_ccs --r 
pipe-D-crc-sprite-planes-basic
IGT-Version: 1.19-g59f0e3d182a8 (x86_64) (Linux: 4.13.0-rc6.intel-boxes+x86_64)
Received signal SIGSEGV.
Stack trace:
 #0 [fatal_sig_handler+0x185]
 #1 [killpg+0x40]
 #2 [__real_main485+0x2de]
 #3 [main+0x3f]
 #4 [__libc_start_main+0xf1]
 #5 [_start+0x2a]
 #6 [+0x2a]
Subtest pipe-D-crc-sprite-planes-basic: CRASH (0.004s)

Signed-off-by: Gabriel Krisman Bertazi 
---
 tests/kms_ccs.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/tests/kms_ccs.c b/tests/kms_ccs.c
index 775c6999699f..73025a1e019f 100644
--- a/tests/kms_ccs.c
+++ b/tests/kms_ccs.c
@@ -503,6 +503,9 @@ igt_main
 
data.flags = TEST_CRC;
igt_subtest_f("pipe-%s-crc-sprite-planes-basic", pipe_name) {
+
+   igt_display_require_output_on_pipe(, 
data.pipe);
+
for_each_plane_on_pipe(, data.pipe, 
data.plane) {
if (data.plane->type == DRM_PLANE_TYPE_PRIMARY)
continue;
-- 
2.11.0

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[Intel-gfx] [PATCH i-g-t v4 1/6] tests/kms_ccs: Test pipes other than pipe A

[Gabriel Krisman Bertazi]

Commit d41c4ccbd2f9 ("tests/kms_ccs: Fix subtest enumeration")
accidently removed the update of data.pipe, causing kms_ccs to silently
only test PIPE_A.

This fixes the behavior reported by Daniel Vetter where tests would
succeed even on nonexistent pipes.

Signed-off-by: Gabriel Krisman Bertazi 
---
 tests/kms_ccs.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/tests/kms_ccs.c b/tests/kms_ccs.c
index ab9325d14991..775c6999699f 100644
--- a/tests/kms_ccs.c
+++ b/tests/kms_ccs.c
@@ -483,6 +483,8 @@ igt_main
const char *pipe_name = kmstest_pipe_name(pipe);
int sprite_idx = 0;
 
+   data.pipe = pipe;
+
data.flags = TEST_BAD_PIXEL_FORMAT;
igt_subtest_f("pipe-%s-bad-pixel-format", pipe_name)
test_output();
-- 
2.11.0

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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v4,1/6] tests/kms_ccs: Test pipes other than pipe A

[Patchwork]

== Series Details ==

Series: series starting with [v4,1/6] tests/kms_ccs: Test pipes other than pipe 
A
URL   : https://patchwork.freedesktop.org/series/30991/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
2885b10f99b4beeb046e75af8b8488c229f629d3 igt/gem_exec_schedule: Ignore 
set-priority failures on old kernels

with latest DRM-Tip kernel build CI_DRM_3146
aa884e1abdf2 drm-tip: 2017y-09m-27d-15h-39m-07s UTC integration manifest

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:440s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:471s
fi-blb-e6850 total:289  pass:224  dwarn:1   dfail:0   fail:0   skip:64  
time:421s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:527s
fi-bwr-2160  total:289  pass:184  dwarn:0   dfail:0   fail:0   skip:105 
time:280s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:504s
fi-byt-j1900 total:289  pass:254  dwarn:1   dfail:0   fail:0   skip:34  
time:500s
fi-cfl-s total:289  pass:223  dwarn:34  dfail:0   fail:0   skip:32  
time:541s
fi-cnl-y total:289  pass:259  dwarn:0   dfail:0   fail:3   skip:27  
time:668s
fi-elk-e7500 total:289  pass:230  dwarn:0   dfail:0   fail:0   skip:59  
time:422s
fi-glk-1 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:572s
fi-hsw-4770  total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:425s
fi-hsw-4770r total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:408s
fi-ilk-650   total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:441s
fi-ivb-3520m total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:485s
fi-ivb-3770  total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:465s
fi-kbl-7500u total:289  pass:263  dwarn:1   dfail:0   fail:1   skip:24  
time:472s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:581s
fi-kbl-r total:245  pass:220  dwarn:0   dfail:0   fail:0   skip:24 
fi-pnv-d510  total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:549s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:457s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:753s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:488s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:476s
fi-snb-2520m total:289  pass:251  dwarn:0   dfail:0   fail:0   skip:38  
time:583s
fi-snb-2600  total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:424s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_260/
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[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v2,01/11] drm/i915/execlists: Move request unwinding to a separate function

[Patchwork]

== Series Details ==

Series: series starting with [v2,01/11] drm/i915/execlists: Move request 
unwinding to a separate function
URL   : https://patchwork.freedesktop.org/series/30983/
State : failure

== Summary ==

Test gem_ctx_param:
Subgroup invalid-param-set:
pass   -> FAIL   (shard-hsw)
Subgroup invalid-param-get:
pass   -> FAIL   (shard-hsw)
Test kms_flip:
Subgroup flip-vs-wf_vblank-interruptible:
fail   -> PASS   (shard-hsw)

shard-hswtotal:2429 pass:1329 dwarn:4   dfail:0   fail:13  skip:1083 
time:9957s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5835/shards.html
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Re: [Intel-gfx] [PATCH] drm/i915/cnl: Avoid WA_SET_BIT_MASK on write-only CNL_HDC_CHICKEN0.

[Oscar Mateo]

On 09/27/2017 02:17 PM, Rodrigo Vivi wrote:

On Wed, Sep 27, 2017 at 09:08:10PM +, Oscar Mateo wrote:


On 09/27/2017 02:01 PM, Rodrigo Vivi wrote:

On CNL, HDC_CHICKEN0 "is write-only from LRI command.
However, it is readable for context save."

So we have no ways to check the coherency by reading it back on
our tests.

So let's just write that bit directly without saving it to
dev_priv->workarounds.

Wait, it's not that simple: CNL_HDC_CHICKEN0 lives in the context image, so
you are going to revert the value as soon as you restore the next context
(you want to save it in dev_priv->workarounds so that
intel_ring_workarounds_emit applies it to every newly created context).

hm... that makes sense...

I was only with the WA description in my head that states to set only once at 
boot:

" To avoid a potential hang condition with TLB invalidation
driver should enable masked bit 5 of MMIO 0xE5F0 at boot."

But apparently just a bad description in spec, right?!

If this is the case probably dev_priv->workarouds will need another component
"permission" to handle write-only registers and avoid reading that on debugfs?
Or any thing smarter?



Well, to begin with, the current debugfs interface does not make a lot 
of sense for things that live inside the context image. That's why Chris 
sent this patch earlier:


"igt/gem_workarounds: Read the workaround registers from the active context"

But this depends on LRI commands and thus makes it impossible to work 
with this particular register :/


Maybe create a context, force the HW to switch in & out of it and then a 
debugfs interface to read the WAs from inside the context image? Another 
possibility: in CNL+, the good old MI_SET_CONTEXT command is back, so 
maybe it can be used imaginatively to retrieve the context image :)


In any case, this looks like a lot of work only to debug that one WA is 
applied correctly...



Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102943
Fixes: acfb5554c769 ("drm/i915/cnl: WaForceContextSaveRestoreNonCoherent")
Cc: Mika Kuoppala 
Cc: Oscar Mateo 
Cc: Chris Wilson 
Signed-off-by: Rodrigo Vivi 
---
   drivers/gpu/drm/i915/intel_engine_cs.c | 4 ++--
   1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index a28e2a864cf1..047ba0a0308d 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1251,8 +1251,8 @@ static int cnl_init_workarounds(struct intel_engine_cs 
*engine)
GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT));
/* WaForceContextSaveRestoreNonCoherent:cnl */
-   WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0,
- HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
+   I915_WRITE(CNL_HDC_CHICKEN0,
+  
_MASKED_BIT_ENABLE(HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT));
/* WaThrottleEUPerfToAvoidTDBackPressure:cnl(pre-prod) */
if (IS_CNL_REVID(dev_priv, CNL_REVID_B0, CNL_REVID_B0))


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Re: [Intel-gfx] [PATCH] drm/i915/cnl: Avoid WA_SET_BIT_MASK on write-only CNL_HDC_CHICKEN0.

[Oscar Mateo]

On 09/27/2017 02:01 PM, Rodrigo Vivi wrote:

On CNL, HDC_CHICKEN0 "is write-only from LRI command.
However, it is readable for context save."

So we have no ways to check the coherency by reading it back on
our tests.

So let's just write that bit directly without saving it to
dev_priv->workarounds.


Wait, it's not that simple: CNL_HDC_CHICKEN0 lives in the context image, 
so you are going to revert the value as soon as you restore the next 
context (you want to save it in dev_priv->workarounds so that 
intel_ring_workarounds_emit applies it to every newly created context).



Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102943
Fixes: acfb5554c769 ("drm/i915/cnl: WaForceContextSaveRestoreNonCoherent")
Cc: Mika Kuoppala 
Cc: Oscar Mateo 
Cc: Chris Wilson 
Signed-off-by: Rodrigo Vivi 
---
  drivers/gpu/drm/i915/intel_engine_cs.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index a28e2a864cf1..047ba0a0308d 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1251,8 +1251,8 @@ static int cnl_init_workarounds(struct intel_engine_cs 
*engine)
GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT));
  
  	/* WaForceContextSaveRestoreNonCoherent:cnl */

-   WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0,
- HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
+   I915_WRITE(CNL_HDC_CHICKEN0,
+  
_MASKED_BIT_ENABLE(HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT));
  
  	/* WaThrottleEUPerfToAvoidTDBackPressure:cnl(pre-prod) */

if (IS_CNL_REVID(dev_priv, CNL_REVID_B0, CNL_REVID_B0))


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Re: [Intel-gfx] [PATCH] drm/i915/cnl: Avoid WA_SET_BIT_MASK on write-only CNL_HDC_CHICKEN0.

[Rodrigo Vivi]

On Wed, Sep 27, 2017 at 09:08:10PM +, Oscar Mateo wrote:
> 
> 
> On 09/27/2017 02:01 PM, Rodrigo Vivi wrote:
> > On CNL, HDC_CHICKEN0 "is write-only from LRI command.
> > However, it is readable for context save."
> > 
> > So we have no ways to check the coherency by reading it back on
> > our tests.
> > 
> > So let's just write that bit directly without saving it to
> > dev_priv->workarounds.
> 
> Wait, it's not that simple: CNL_HDC_CHICKEN0 lives in the context image, so
> you are going to revert the value as soon as you restore the next context
> (you want to save it in dev_priv->workarounds so that
> intel_ring_workarounds_emit applies it to every newly created context).

hm... that makes sense...

I was only with the WA description in my head that states to set only once at 
boot:

" To avoid a potential hang condition with TLB invalidation
driver should enable masked bit 5 of MMIO 0xE5F0 at boot."

But apparently just a bad description in spec, right?!

If this is the case probably dev_priv->workarouds will need another component
"permission" to handle write-only registers and avoid reading that on debugfs?
Or any thing smarter?

> 
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102943
> > Fixes: acfb5554c769 ("drm/i915/cnl: WaForceContextSaveRestoreNonCoherent")
> > Cc: Mika Kuoppala 
> > Cc: Oscar Mateo 
> > Cc: Chris Wilson 
> > Signed-off-by: Rodrigo Vivi 
> > ---
> >   drivers/gpu/drm/i915/intel_engine_cs.c | 4 ++--
> >   1 file changed, 2 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
> > b/drivers/gpu/drm/i915/intel_engine_cs.c
> > index a28e2a864cf1..047ba0a0308d 100644
> > --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> > @@ -1251,8 +1251,8 @@ static int cnl_init_workarounds(struct 
> > intel_engine_cs *engine)
> > GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT));
> > /* WaForceContextSaveRestoreNonCoherent:cnl */
> > -   WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0,
> > - HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
> > +   I915_WRITE(CNL_HDC_CHICKEN0,
> > +  
> > _MASKED_BIT_ENABLE(HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT));
> > /* WaThrottleEUPerfToAvoidTDBackPressure:cnl(pre-prod) */
> > if (IS_CNL_REVID(dev_priv, CNL_REVID_B0, CNL_REVID_B0))
> 
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[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Allow optimized platform checks

[Patchwork]

== Series Details ==

Series: drm/i915: Allow optimized platform checks
URL   : https://patchwork.freedesktop.org/series/30982/
State : success

== Summary ==

Test kms_flip:
Subgroup flip-vs-wf_vblank-interruptible:
fail   -> PASS   (shard-hsw)
Test perf:
Subgroup polling:
fail   -> PASS   (shard-hsw) fdo#102252

fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-hswtotal:2429 pass:1332 dwarn:4   dfail:0   fail:10  skip:1083 
time:9928s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5834/shards.html
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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/cnl: Avoid WA_SET_BIT_MASK on write-only CNL_HDC_CHICKEN0.

[Patchwork]

== Series Details ==

Series: drm/i915/cnl: Avoid WA_SET_BIT_MASK on write-only CNL_HDC_CHICKEN0.
URL   : https://patchwork.freedesktop.org/series/31001/
State : success

== Summary ==

Series 31001v1 drm/i915/cnl: Avoid WA_SET_BIT_MASK on write-only 
CNL_HDC_CHICKEN0.
https://patchwork.freedesktop.org/api/1.0/series/31001/revisions/1/mbox/

Test drv_module_reload:
Subgroup basic-reload:
dmesg-warn -> PASS   (fi-glk-1) fdo#102777 +1

fdo#102777 https://bugs.freedesktop.org/show_bug.cgi?id=102777

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:441s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:477s
fi-blb-e6850 total:289  pass:224  dwarn:1   dfail:0   fail:0   skip:64  
time:421s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:514s
fi-bwr-2160  total:289  pass:184  dwarn:0   dfail:0   fail:0   skip:105 
time:280s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:506s
fi-byt-j1900 total:289  pass:254  dwarn:1   dfail:0   fail:0   skip:34  
time:492s
fi-cfl-s total:289  pass:223  dwarn:34  dfail:0   fail:0   skip:32  
time:548s
fi-cnl-y total:289  pass:259  dwarn:0   dfail:0   fail:3   skip:27  
time:642s
fi-elk-e7500 total:289  pass:230  dwarn:0   dfail:0   fail:0   skip:59  
time:418s
fi-glk-1 total:289  pass:259  dwarn:1   dfail:0   fail:0   skip:29  
time:568s
fi-hsw-4770  total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:424s
fi-hsw-4770r total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:408s
fi-ilk-650   total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:430s
fi-ivb-3520m total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:487s
fi-ivb-3770  total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:464s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:469s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:579s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:594s
fi-pnv-d510  total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:541s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:452s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:748s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:487s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:472s
fi-snb-2520m total:289  pass:251  dwarn:0   dfail:0   fail:0   skip:38  
time:580s
fi-snb-2600  total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:420s

7f93222785e4887c083c85b76fcbb391bb1991d9 drm-tip: 2017y-09m-27d-20h-05m-25s UTC 
integration manifest
3e83dbea9928 drm/i915/cnl: Avoid WA_SET_BIT_MASK on write-only CNL_HDC_CHICKEN0.

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5836/
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[Intel-gfx] [PATCH v1] drm/i915: Enhanced for initialize partially filled pagetables

[Xiaolin Zhang]

if vgpu active, the page table entry should be initialized after
allocation and then the hypersivor can ping pages succesuffly,
otherwise hypervisor will ping pages failed and the host will print
a lot of annoying errors such as “ERROR gvt: guest page write error -22,
gfn 0x7ada8, pa 0x7ada89a8, var 0x6, len 1” when create linux guest.

Signed-off-by: Xiaolin Zhang 
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 731ce229a923..be52b139817d 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1175,7 +1175,7 @@ static int gen8_ppgtt_alloc_pd(struct i915_address_space 
*vm,
if (IS_ERR(pt))
goto unwind;
 
-   if (count < GEN8_PTES)
+   if (count < GEN8_PTES || intel_vgpu_active(vm->i915))
gen8_initialize_pt(vm, pt);
 
gen8_ppgtt_set_pde(vm, pd, pt, pde);
-- 
2.14.1

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Enhanced for initialize partially filled pagetables

[Patchwork]

== Series Details ==

Series: drm/i915: Enhanced for initialize partially filled pagetables
URL   : https://patchwork.freedesktop.org/series/31029/
State : success

== Summary ==

Series 31029v1 drm/i915: Enhanced for initialize partially filled pagetables
https://patchwork.freedesktop.org/api/1.0/series/31029/revisions/1/mbox/

Test drv_module_reload:
Subgroup basic-reload:
dmesg-warn -> PASS   (fi-glk-1) fdo#102777

fdo#102777 https://bugs.freedesktop.org/show_bug.cgi?id=102777

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:439s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:475s
fi-blb-e6850 total:289  pass:224  dwarn:1   dfail:0   fail:0   skip:64  
time:420s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:513s
fi-bwr-2160  total:289  pass:184  dwarn:0   dfail:0   fail:0   skip:105 
time:279s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:517s
fi-byt-j1900 total:289  pass:254  dwarn:1   dfail:0   fail:0   skip:34  
time:494s
fi-cfl-s total:289  pass:223  dwarn:34  dfail:0   fail:0   skip:32  
time:540s
fi-cnl-y total:289  pass:259  dwarn:0   dfail:0   fail:3   skip:27  
time:644s
fi-elk-e7500 total:289  pass:230  dwarn:0   dfail:0   fail:0   skip:59  
time:417s
fi-glk-1 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:567s
fi-hsw-4770  total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:426s
fi-hsw-4770r total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:403s
fi-ilk-650   total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:429s
fi-ivb-3520m total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:491s
fi-ivb-3770  total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:466s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:474s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:583s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:591s
fi-pnv-d510  total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:550s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:454s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:754s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:491s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:472s
fi-snb-2520m total:289  pass:251  dwarn:0   dfail:0   fail:0   skip:38  
time:560s
fi-snb-2600  total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:416s

7f93222785e4887c083c85b76fcbb391bb1991d9 drm-tip: 2017y-09m-27d-20h-05m-25s UTC 
integration manifest
ef12d5353059 drm/i915: Enhanced for initialize partially filled pagetables

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5840/
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Re: [Intel-gfx] [PATCH] drm/dp: Avoid needless delay while link training

[Lee, Shawn C]

>On Tue, 26 Sep 2017, "Lee, Shawn C"  wrote:
>> DP v1.3 spec reserved DPCD TRAINING_AUX_RD_INTERVAL (Eh)
>> bit7 to indicate Extended Receiver Capability. A DPRX with DPCD Rev. 
>> 1.4 (or higher) must have an Extended Receiver Capability field.
>> Driver have to clear bit7 when retrieve interval value and avoid to 
>> wait for needless delay.
>>
>> Cc: Jani Nikula 
>> Cc: Cooper Chiou 
>>
>> Signed-off-by: Shawn Lee 
>> ---
>>  drivers/gpu/drm/drm_dp_helper.c | 18 --
>>  include/drm/drm_dp_helper.h |  1 +
>>  2 files changed, 13 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/drm_dp_helper.c 
>> b/drivers/gpu/drm/drm_dp_helper.c index 08af8d6b844b..5a01c84b7f8f 
>> 100644
>> --- a/drivers/gpu/drm/drm_dp_helper.c
>> +++ b/drivers/gpu/drm/drm_dp_helper.c
>> @@ -118,19 +118,25 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const 
>> u8 link_status[DP_LINK_STATUS_SI  }  
>> EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis);
>>  
>> -void drm_dp_link_train_clock_recovery_delay(const u8 
>> dpcd[DP_RECEIVER_CAP_SIZE]) {
>> -if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
>> +void drm_dp_link_train_clock_recovery_delay(const u8 
>> +dpcd[DP_RECEIVER_CAP_SIZE]) {
>> +u8 interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] & 
>> +DP_TRAINING_AUX_RD_INTERVAL_MASK;
>> +
>> +if (interval == 0)
>>  udelay(100);
>>  else
>> -mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
>> +mdelay(interval * 4);
>
>DP 1.4 seems to change this to 100 us for main-link clock recovery, but let's 
>leave that to another patch, another day...
>

OK. Let's wait for DP 1.4 spec finalize it and commit the latest change later.

>>  }
>>  EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);
>>  
>> -void drm_dp_link_train_channel_eq_delay(const u8 
>> dpcd[DP_RECEIVER_CAP_SIZE]) {
>> -if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
>> +void drm_dp_link_train_channel_eq_delay(const u8 
>> +dpcd[DP_RECEIVER_CAP_SIZE]) {
>> +u8 interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] & 
>> +DP_TRAINING_AUX_RD_INTERVAL_MASK;
>> +
>> +if (interval == 0)
>>  udelay(400);
>>  else
>> -mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
>> +mdelay(interval * 4);
>>  }
>>  EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
>>  
>> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h 
>> index 2c412a15cfa1..12d4cf48096c 100644
>> --- a/include/drm/drm_dp_helper.h
>> +++ b/include/drm/drm_dp_helper.h
>> @@ -118,6 +118,7 @@
>>  # define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher 
>> */
>>  
>>  #define DP_TRAINING_AUX_RD_INTERVAL 0x00e   /* XXX 1.2? */
>> +#define DP_TRAINING_AUX_RD_INTERVAL_MASK(0x7f << 0)
>
>Please indent this like all other content definitions in this file, i.e. space 
>between "#" and "define".
>
>Please add
>
># define DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT (1 << 7) /* 1.4 */

I will do the change as you mention in next commit.

>while at it.
>
>Other than that, LGTM.
>
>BR,
>Jani.
>
>>  
>>  #define DP_ADAPTER_CAP  0x00f   /* 1.2 */
>>  # define DP_FORCE_LOAD_SENSE_CAP(1 << 0)
>
>--
>Jani Nikula, Intel Open Source Technology Center
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[Intel-gfx] [PATCH 2/2] drm/i915: enable to read CSB and CSB write pointer from HWSP in GVT-g VM

[Weinan Li]

Let GVT-g VM read the CSB and CSB write pointer from virtual HWSP, not all
the host support this feature, need to check the BIT(3) of caps in PVINFO.

Signed-off-by: Weinan Li 
Cc: Chris Wilson 
---
 drivers/gpu/drm/i915/i915_vgpu.c |  5 +
 drivers/gpu/drm/i915/i915_vgpu.h |  1 +
 drivers/gpu/drm/i915/intel_lrc.c | 18 +-
 3 files changed, 19 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 5fe9f3f..6f713c5 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -86,6 +86,11 @@ bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private 
*dev_priv)
return dev_priv->vgpu.caps & VGT_CAPS_FULL_48BIT_PPGTT;
 }
 
+bool intel_vgpu_has_hwsp_emulation(struct drm_i915_private *dev_priv)
+{
+   return dev_priv->vgpu.caps & VGT_CAPS_HWSP_EMULATION;
+}
+
 struct _balloon_info_ {
/*
 * There are up to 2 regions per mappable/unmappable graphic
diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
index b72bd29..cec0ec1 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.h
+++ b/drivers/gpu/drm/i915/i915_vgpu.h
@@ -29,6 +29,7 @@
 void i915_check_vgpu(struct drm_i915_private *dev_priv);
 
 bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv);
+bool intel_vgpu_has_hwsp_emulation(struct drm_i915_private *dev_priv);
 
 int intel_vgt_balloon(struct drm_i915_private *dev_priv);
 void intel_vgt_deballoon(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 955c879..cd2af7b 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -136,6 +136,7 @@
 #include 
 #include 
 #include "i915_drv.h"
+#include "i915_vgpu.h"
 #include "intel_mocs.h"
 
 #define RING_EXECLIST_QFULL(1 << 0x2)
@@ -664,7 +665,12 @@ static void intel_lrc_irq_handler(unsigned long data)
>status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
unsigned int head, tail;
 
-   /* However GVT emulation depends upon intercepting CSB mmio */
+   /* However GVT-g emulation depends upon host kernel
+* implementation, need to check support capbility by reading PV
+* INFO before access HWSP. Beside from this, another special
+* configuration may also need to force use mmio, like IOMMU
+* enabled.
+*/
if (unlikely(engine->csb_use_mmio)) {
buf = (u32 * __force)
(dev_priv->regs + 
i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0)));
@@ -1780,10 +1786,6 @@ static void execlists_set_default_submission(struct 
intel_engine_cs *engine)
 
 static bool irq_handler_force_mmio(struct drm_i915_private *i915)
 {
-   /* GVT emulation depends upon intercepting CSB mmio */
-   if (intel_vgpu_active(i915))
-   return true;
-
/*
 * IOMMU adds unpredictable latency causing the CSB write (from the
 * GPU into the HWSP) to only be visible some time after the interrupt
@@ -1792,6 +1794,12 @@ static bool irq_handler_force_mmio(struct 
drm_i915_private *i915)
if (intel_vtd_active())
return true;
 
+   /* GVT emulation depends upon host kernel implementation, check
+* support capbility by reading PV INFO before access HWSP.
+*/
+   if (intel_vgpu_active(i915) && !intel_vgpu_has_hwsp_emulation(i915))
+   return true;
+
return false;
 }
 
-- 
1.9.1

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[Intel-gfx] [PULL] drm-intel-fixes

[Rodrigo Vivi]

Hi Dave,

Here goes the drm/i915 fixes for 4.14-rc3

Couple fixes for stable:

- Fix ELD connector types and consequently audio on DP (Jani).
- Ignore HDMI on Port A and consequently fix an ops on i915 probe
  when VBT advertises HDMI on Port A (Jani).

And a small fix:

- That removes a reduntant hw_check on modeset. (Colin)

This last one is really minor, but dim scripts got it and
I decided to keep to keep consistency with our CI run.

Also, unfortunately I didn't rebase on Linus 4.14-rc2 tag as I should,
but it is based on a later merge he did. So pull request itself is
not ideal but at least it is sane this time.

But for next time I will make sure I rebase it on
fixed tags as Jani was doing and also I'm already taking a look to
improving our documents and maybe dim script to automate that rebase.

Thanks,
Rodrigo.

The following changes since commit e365806ac289457263a133bd32df8df49897f612:

  Merge branch 'for-linus' of 
git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs (2017-09-25 18:24:14 
-0700)

are available in the git repository at:

  git://anongit.freedesktop.org/git/drm-intel tags/drm-intel-fixes-2017-09-27

for you to fetch changes up to 2ba7d7e0437127314864238f8bfcb8369d81075c:

  drm/i915/bios: ignore HDMI on port A (2017-09-26 09:14:28 -0700)


drm/i915 fixes for 4.14-rc3

Couple fixes for stable:

- Fix ELD connector types and consequently audio on DP (Jani).
- Ignore HDMI on Port A and consequently fix an ops on i915 probe
  when VBT advertises HDMI on Port A (Jani).

And a small fix:

- That removes a reduntant hw_check on modeset. (Colin)


Colin Ian King (1):
  drm/i915: remove redundant variable hw_check

Jani Nikula (2):
  drm/i915: always update ELD connector type after get modes
  drm/i915/bios: ignore HDMI on port A

 drivers/gpu/drm/i915/intel_audio.c   |  5 -
 drivers/gpu/drm/i915/intel_bios.c|  7 +++
 drivers/gpu/drm/i915/intel_display.c |  2 --
 drivers/gpu/drm/i915/intel_modes.c   | 17 +
 4 files changed, 24 insertions(+), 7 deletions(-)
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[Intel-gfx] [PATCH v2] drm/dp: Do not prune the last mode on the connector

[Manasi Navare]

Currently the drm_mode_prune_invalid() function will
prune all the modes if it finds that the mode-status
is not MODE_OK. But if it ends up pruning all modes
then there are no modes left for that connector which will
eventually result into a black screen as userspace sees no
modes from the kernel. This can happen pretty quickly in case of
eDP panel that has only mode that might get pruned.
This patch fixes this problem by checking if the mode being pruned
is the last mode(only mode) on that connector and if so doesnt prune it.

v2:
* Use correct macro from list.h (Keith Packard)

Cc: dri-de...@lists.freedesktop.org
Cc: Keith Packard 
Cc: Jani Nikula 
Cc: Ville Syrjala 
Cc: Daniel Vetter 
Signed-off-by: Manasi Navare 
---
 drivers/gpu/drm/drm_modes.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c
index 4a3f68a..9dc38a4 100644
--- a/drivers/gpu/drm/drm_modes.c
+++ b/drivers/gpu/drm/drm_modes.c
@@ -1185,7 +1185,8 @@ void drm_mode_prune_invalid(struct drm_device *dev,
struct drm_display_mode *mode, *t;
 
list_for_each_entry_safe(mode, t, mode_list, head) {
-   if (mode->status != MODE_OK) {
+   if (mode->status != MODE_OK &&
+   !list_is_singular(mode_list)) {
list_del(>head);
if (verbose) {
drm_mode_debug_printmodeline(mode);
-- 
2.1.4

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[Intel-gfx] ✗ Fi.CI.IGT: warning for igt/gem_exec_scheduler: HAS_SCHEDULER no longer means HAS_PREEMPTION (rev3)

[Patchwork]

== Series Details ==

Series: igt/gem_exec_scheduler: HAS_SCHEDULER no longer means HAS_PREEMPTION 
(rev3)
URL   : https://patchwork.freedesktop.org/series/30860/
State : warning

== Summary ==

Test gem_exec_schedule:
Subgroup preempt-contexts-bsd:
pass   -> SKIP   (shard-hsw)
Subgroup deep-vebox:
pass   -> SKIP   (shard-hsw)
Subgroup deep-bsd2:
pass   -> SKIP   (shard-hsw)
Subgroup in-order-bsd2:
pass   -> SKIP   (shard-hsw)
Subgroup promotion-bsd2:
pass   -> SKIP   (shard-hsw)
Subgroup preempt-blt:
pass   -> SKIP   (shard-hsw)
Subgroup wide-bsd2:
pass   -> SKIP   (shard-hsw)
Subgroup out-order-render:
pass   -> SKIP   (shard-hsw)
Subgroup fifo-bsd2:
pass   -> SKIP   (shard-hsw)
Subgroup deep-bsd:
pass   -> SKIP   (shard-hsw)
Subgroup promotion-render:
pass   -> SKIP   (shard-hsw)
Subgroup preempt-other-vebox:
pass   -> SKIP   (shard-hsw)
Subgroup preempt-bsd2:
pass   -> SKIP   (shard-hsw)
Subgroup wide-blt:
pass   -> SKIP   (shard-hsw)
Subgroup promotion-bsd:
pass   -> SKIP   (shard-hsw)
Subgroup reorder-wide-bsd1:
pass   -> SKIP   (shard-hsw)
Subgroup out-order-blt:
pass   -> SKIP   (shard-hsw)
Subgroup pi-ringfull-render:
pass   -> SKIP   (shard-hsw)
Subgroup preempt-self-render:
fail   -> SKIP   (shard-hsw)
Subgroup preempt-other-blt:
pass   -> SKIP   (shard-hsw)
Subgroup pi-ringfull-default:
pass   -> SKIP   (shard-hsw)
Subgroup preempt-self-blt:
pass   -> SKIP   (shard-hsw)
Subgroup preempt-contexts-bsd1:
pass   -> SKIP   (shard-hsw)
Subgroup deep-bsd1:
pass   -> SKIP   (shard-hsw)
Subgroup preempt-contexts-blt:
pass   -> SKIP   (shard-hsw)
Subgroup fifo-blt:
skip   -> PASS   (shard-hsw)
Subgroup preempt-contexts-render:
pass   -> SKIP   (shard-hsw)
Subgroup reorder-wide-render:
pass   -> SKIP   (shard-hsw)
Subgroup reorder-wide-bsd:
pass   -> SKIP   (shard-hsw)
Subgroup preempt-render:
pass   -> SKIP   (shard-hsw)
Subgroup preempt-self-bsd2:
pass   -> SKIP   (shard-hsw)
Subgroup deep-render:
pass   -> SKIP   (shard-hsw)
Subgroup pi-ringfull-bsd2:
pass   -> SKIP   (shard-hsw)
Subgroup in-order-bsd1:
pass   -> SKIP   (shard-hsw)
Subgroup preempt-other-bsd1:
pass   -> SKIP   (shard-hsw)
Subgroup fifo-bsd:
skip   -> PASS   (shard-hsw)
Subgroup deep-blt:
pass   -> SKIP   (shard-hsw)
Subgroup pi-ringfull-bsd1:
pass   -> SKIP   (shard-hsw)
Subgroup preempt-vebox:
pass   -> SKIP   (shard-hsw)
Test drv_suspend:
Subgroup sysfs-reader-hibernate:
skip   -> FAIL   (shard-hsw) k.org#196691 +5
Subgroup sysfs-reader:
skip   -> PASS   (shard-hsw)
Subgroup fence-restore-untiled:
skip   -> PASS   (shard-hsw)
Subgroup debugfs-reader:
skip   -> PASS   (shard-hsw)
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-primscrn-indfb-pgflip-blt:
fail   -> PASS   (shard-hsw)
Subgroup psr-1p-offscren-pri-indfb-draw-mmap-wc:
pass   -> SKIP   (shard-hsw)
Subgroup fbc-2p-scndscrn-shrfb-pgflip-blt:
pass   -> SKIP   (shard-hsw)
Subgroup fbcpsr-2p-primscrn-cur-indfb-draw-mmap-cpu:
pass   -> SKIP   (shard-hsw)
Subgroup psr-rgb565-draw-blt:
pass   -> SKIP   (shard-hsw)
Subgroup psr-2p-scndscrn-cur-indfb-draw-render:
fail   -> SKIP   (shard-hsw)
Subgroup fbcpsr-tilingchange:
pass   -> SKIP   (shard-hsw)
Subgroup fbc-2p-indfb-fliptrack:
pass   -> SKIP   (shard-hsw)
Subgroup fbcpsr-2p-scndscrn-cur-indfb-move:
pass   -> SKIP   (shard-hsw)
Subgroup psr-rgb101010-draw-mmap-wc:
pass   

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/dp: Do not prune the last mode on the connector (rev2)

[Patchwork]

== Series Details ==

Series: drm/dp: Do not prune the last mode on the connector (rev2)
URL   : https://patchwork.freedesktop.org/series/31018/
State : failure

== Summary ==

Series 31018v2 drm/dp: Do not prune the last mode on the connector
https://patchwork.freedesktop.org/api/1.0/series/31018/revisions/2/mbox/

Test kms_force_connector_basic:
Subgroup force-connector-state:
pass   -> FAIL   (fi-bwr-2160)
pass   -> FAIL   (fi-elk-e7500)
pass   -> FAIL   (fi-snb-2520m)
pass   -> FAIL   (fi-snb-2600)
pass   -> FAIL   (fi-ivb-3520m)
pass   -> FAIL   (fi-ivb-3770)
pass   -> FAIL   (fi-byt-j1900)
Test prime_vgem:
Subgroup basic-fence-flip:
skip   -> PASS   (fi-ivb-3520m)
Test drv_module_reload:
Subgroup basic-reload:
dmesg-warn -> PASS   (fi-glk-1) fdo#102777 +1

fdo#102777 https://bugs.freedesktop.org/show_bug.cgi?id=102777

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:439s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:477s
fi-blb-e6850 total:289  pass:224  dwarn:1   dfail:0   fail:0   skip:64  
time:417s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:517s
fi-bwr-2160  total:289  pass:183  dwarn:0   dfail:0   fail:1   skip:105 
time:277s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:516s
fi-byt-j1900 total:289  pass:253  dwarn:1   dfail:0   fail:1   skip:34  
time:493s
fi-cfl-s total:289  pass:223  dwarn:34  dfail:0   fail:0   skip:32  
time:544s
fi-cnl-y total:289  pass:258  dwarn:0   dfail:0   fail:4   skip:27  
time:654s
fi-elk-e7500 total:289  pass:229  dwarn:0   dfail:0   fail:1   skip:59  
time:417s
fi-glk-1 total:289  pass:259  dwarn:1   dfail:0   fail:0   skip:29  
time:564s
fi-hsw-4770  total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:423s
fi-hsw-4770r total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:405s
fi-ilk-650   total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:431s
fi-ivb-3520m total:289  pass:261  dwarn:0   dfail:0   fail:1   skip:27  
time:492s
fi-ivb-3770  total:289  pass:260  dwarn:0   dfail:0   fail:1   skip:28  
time:464s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:478s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:577s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:589s
fi-pnv-d510  total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:545s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:455s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:754s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:485s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:476s
fi-snb-2520m total:289  pass:250  dwarn:0   dfail:0   fail:1   skip:38  
time:566s
fi-snb-2600  total:289  pass:249  dwarn:0   dfail:0   fail:1   skip:39  
time:415s

7f93222785e4887c083c85b76fcbb391bb1991d9 drm-tip: 2017y-09m-27d-20h-05m-25s UTC 
integration manifest
120bf9f3f5c0 drm/dp: Do not prune the last mode on the connector

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5839/
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[Intel-gfx] [PATCH 1/2] drm/i915/gvt: update CSB and CSB write pointer in virtual HWSP

[Weinan Li]

The engine provides a mirror of the CSB and CSB write pointer in the HWSP.
Read these status from virtual HWSP in VM can reduce CPU utilization while
applications have much more short GPU workloads. Here we update the
corresponding data in virtual HWSP as it in virtual MMIO.

Before read these status from HWSP in GVT-g VM, please ensure the host
support it by checking the BIT(3) of caps in PVINFO.

Virtual HWSP only support GEN8+ platform, since the HWSP MMIO may change
follow the platform update, please add the corresponding MMIO emulation
when enable new platforms in GVT-g.

Signed-off-by: Weinan Li 
Cc: Chris Wilson 
---
 drivers/gpu/drm/i915/gvt/execlist.c | 14 +
 drivers/gpu/drm/i915/gvt/gvt.h  |  1 +
 drivers/gpu/drm/i915/gvt/handlers.c | 41 +++--
 drivers/gpu/drm/i915/gvt/vgpu.c |  8 
 drivers/gpu/drm/i915/i915_pvinfo.h  |  1 +
 5 files changed, 63 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/execlist.c 
b/drivers/gpu/drm/i915/gvt/execlist.c
index 5c966ed..8227ea2 100644
--- a/drivers/gpu/drm/i915/gvt/execlist.c
+++ b/drivers/gpu/drm/i915/gvt/execlist.c
@@ -133,6 +133,8 @@ static void emulate_csb_update(struct intel_vgpu_execlist 
*execlist,
struct execlist_context_status_pointer_format ctx_status_ptr;
u32 write_pointer;
u32 ctx_status_ptr_reg, ctx_status_buf_reg, offset;
+   unsigned long hwsp_gpa;
+   struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
 
ctx_status_ptr_reg = execlist_ring_mmio(vgpu->gvt, ring_id,
_EL_OFFSET_STATUS_PTR);
@@ -158,6 +160,18 @@ static void emulate_csb_update(struct intel_vgpu_execlist 
*execlist,
ctx_status_ptr.write_ptr = write_pointer;
vgpu_vreg(vgpu, ctx_status_ptr_reg) = ctx_status_ptr.dw;
 
+   /*
+* Update the CSB and CSB write pointer in HWSP.
+*/
+   if (INTEL_INFO(dev_priv)->gen >= 8) {
+   hwsp_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, 
vgpu->hws_pga[ring_id]);
+   intel_gvt_hypervisor_write_gpa(vgpu,
+  hwsp_gpa + I915_HWS_CSB_BUF0_INDEX * 4 + write_pointer * 
8,
+  status, 8);
+   intel_gvt_hypervisor_write_gpa(vgpu,
+   hwsp_gpa + intel_hws_csb_write_index(dev_priv) * 4,
+   _pointer, 4);
+   }
gvt_dbg_el("vgpu%d: w pointer %u reg %x csb l %x csb h %x\n",
vgpu->id, write_pointer, offset, status->ldw, status->udw);
 
diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
index b7253d7..8b64f25 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.h
+++ b/drivers/gpu/drm/i915/gvt/gvt.h
@@ -189,6 +189,7 @@ struct intel_vgpu {
struct intel_vgpu_opregion opregion;
struct intel_vgpu_display display;
struct intel_vgpu_submission submission;
+   u32 hws_pga[I915_NUM_ENGINES];
 
 #if IS_ENABLED(CONFIG_DRM_I915_GVT_KVMGT)
struct {
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c 
b/drivers/gpu/drm/i915/gvt/handlers.c
index 87985c7..887bdf5 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1371,6 +1371,43 @@ static int mailbox_write(struct intel_vgpu *vgpu, 
unsigned int offset,
return intel_vgpu_default_mmio_write(vgpu, offset, , bytes);
 }
 
+static int hws_pga_write(struct intel_vgpu *vgpu, unsigned int offset,
+   void *p_data, unsigned int bytes)
+{
+   u32 value = *(u32 *)p_data;
+   /*
+* Need to emulate all the HWSP register write to ensure host can
+* update the VM CSB status correctly. Here listed registers can
+* support BDW, SKL or other platforms with same HWSP registers.
+*/
+   switch (offset) {
+   case 0x2080:
+   vgpu->hws_pga[RCS] = value;
+   break;
+   case 0x12080:
+   vgpu->hws_pga[VCS] = value;
+   break;
+   case 0x1c080:
+   vgpu->hws_pga[VCS2] = value;
+   break;
+   case 0x1a080:
+   vgpu->hws_pga[VECS] = value;
+   break;
+   case 0x22080:
+   vgpu->hws_pga[BCS] = value;
+   break;
+   default:
+   gvt_vgpu_err("VM(%d) access unkown hardware status page 
register:0x%x\n",
+vgpu->id, offset);
+   return -EINVAL;
+   }
+
+   gvt_dbg_mmio("VM(%d) write: 0x%x to HWSP: 0x%x\n",
+vgpu->id, value, offset);
+
+   return intel_vgpu_default_mmio_write(vgpu, offset, , bytes);
+}
+
 static int skl_power_well_ctl_write(struct intel_vgpu *vgpu,
unsigned int offset, void *p_data, unsigned int bytes)
 {
@@ -2574,8 +2611,8 @@ static int init_broadwell_mmio_info(struct intel_gvt *gvt)
MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 32, 0, 0, 0, D_BDW_PLUS, NULL, 
NULL);
 #undef 

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/cnl: Avoid WA_SET_BIT_MASK on write-only CNL_HDC_CHICKEN0.

[Patchwork]

== Series Details ==

Series: drm/i915/cnl: Avoid WA_SET_BIT_MASK on write-only CNL_HDC_CHICKEN0.
URL   : https://patchwork.freedesktop.org/series/31001/
State : failure

== Summary ==

Test perf:
Subgroup polling:
pass   -> FAIL   (shard-hsw) fdo#102252
Test prime_busy:
Subgroup before-render:
pass   -> FAIL   (shard-hsw)
Test kms_flip:
Subgroup flip-vs-modeset-interruptible:
pass   -> DMESG-WARN (shard-hsw) fdo#102557

fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#102557 https://bugs.freedesktop.org/show_bug.cgi?id=102557

shard-hswtotal:2429 pass:1329 dwarn:5   dfail:0   fail:12  skip:1083 
time:9949s

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5836/shards.html
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/gvt: update CSB and CSB write pointer in virtual HWSP

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915/gvt: update CSB and CSB write 
pointer in virtual HWSP
URL   : https://patchwork.freedesktop.org/series/31033/
State : failure

== Summary ==

Series 31033 revision 1 was fully merged or fully failed: no git log

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[Intel-gfx] [PATCH v11 06/11] drm/i915/guc: Make GuC related disable/destroy functions not depend on i915.enable_guc_submission

[Sagar Arun Kamble]

During GuC load/enable, state is setup by driver that can be looked at
while disabling. So remove the check for i915.enable_guc_submission
parameter in those functions.

Suggested-by: Chris Wilson 
Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Michał Winiarski 
---
 drivers/gpu/drm/i915/i915_guc_submission.c | 13 ++---
 drivers/gpu/drm/i915/i915_irq.c|  6 ++
 drivers/gpu/drm/i915/intel_guc_log.c   |  6 ++
 drivers/gpu/drm/i915/intel_uc.c| 12 
 4 files changed, 22 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 04f1281..a2f67ca 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -1002,7 +1002,8 @@ static int guc_ads_create(struct intel_guc *guc)
 
 static void guc_ads_destroy(struct intel_guc *guc)
 {
-   i915_vma_unpin_and_release(>ads_vma);
+   if (guc->ads_vma)
+   i915_vma_unpin_and_release(>ads_vma);
 }
 
 /*
@@ -1060,11 +1061,14 @@ void i915_guc_submission_fini(struct drm_i915_private 
*dev_priv)
 {
struct intel_guc *guc = _priv->guc;
 
+   WARN_ON_ONCE(!ida_is_empty(>stage_ids));
ida_destroy(>stage_ids);
guc_ads_destroy(guc);
intel_guc_log_destroy(guc);
-   i915_gem_object_unpin_map(guc->stage_desc_pool->obj);
-   i915_vma_unpin_and_release(>stage_desc_pool);
+   if (guc->stage_desc_pool) {
+   i915_gem_object_unpin_map(guc->stage_desc_pool->obj);
+   i915_vma_unpin_and_release(>stage_desc_pool);
+   }
 }
 
 static void guc_interrupts_capture(struct drm_i915_private *dev_priv)
@@ -1204,6 +1208,9 @@ void i915_guc_submission_disable(struct drm_i915_private 
*dev_priv)
 {
struct intel_guc *guc = _priv->guc;
 
+   if (!guc->execbuf_client)
+   return;
+
guc_interrupts_release(dev_priv);
 
/* Revert back to manual ELSP submission */
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 0b756213..75406ee 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -455,6 +455,9 @@ void gen9_reset_guc_interrupts(struct drm_i915_private 
*dev_priv)
 
 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv)
 {
+   if (READ_ONCE(dev_priv->guc.interrupts_enabled))
+   return;
+
spin_lock_irq(_priv->irq_lock);
if (!dev_priv->guc.interrupts_enabled) {
WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
@@ -467,6 +470,9 @@ void gen9_enable_guc_interrupts(struct drm_i915_private 
*dev_priv)
 
 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv)
 {
+   if (!READ_ONCE(dev_priv->guc.interrupts_enabled))
+   return;
+
spin_lock_irq(_priv->irq_lock);
dev_priv->guc.interrupts_enabled = false;
 
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c 
b/drivers/gpu/drm/i915/intel_guc_log.c
index 6571d96..7b6 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -584,7 +584,8 @@ int intel_guc_log_create(struct intel_guc *guc)
 void intel_guc_log_destroy(struct intel_guc *guc)
 {
guc_log_runtime_destroy(guc);
-   i915_vma_unpin_and_release(>log.vma);
+   if (guc->log.vma)
+   i915_vma_unpin_and_release(>log.vma);
 }
 
 int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val)
@@ -653,9 +654,6 @@ void i915_guc_log_register(struct drm_i915_private 
*dev_priv)
 
 void i915_guc_log_unregister(struct drm_i915_private *dev_priv)
 {
-   if (!i915_modparams.enable_guc_submission)
-   return;
-
mutex_lock(_priv->drm.struct_mutex);
/* GuC logging is currently the only user of Guc2Host interrupts */
gen9_disable_guc_interrupts(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index ab26232..ea7c39c 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -445,8 +445,7 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
 err_log_capture:
guc_capture_load_err_log(guc);
 err_submission:
-   if (i915_modparams.enable_guc_submission)
-   i915_guc_submission_fini(dev_priv);
+   i915_guc_submission_fini(dev_priv);
 err_guc:
i915_ggtt_disable_guc(dev_priv);
 
@@ -475,15 +474,12 @@ void intel_uc_fini_hw(struct drm_i915_private *dev_priv)
if (!i915_modparams.enable_guc_loading)
return;
 
-   if (i915_modparams.enable_guc_submission)
-   i915_guc_submission_disable(dev_priv);
+   i915_guc_submission_disable(dev_priv);
 
guc_disable_communication(_priv->guc);
 
-   if (i915_modparams.enable_guc_submission) {
-   

[Intel-gfx] [PATCH v11 08/11] drm/i915/guc: Update GuC ggtt.invalidate/interrupts/communication across RPM suspend/resume

[Sagar Arun Kamble]

Apart from configuring interrupts, we need to update the ggtt invalidate
interface and GuC communication on suspend/resume. This functionality
can be reused for other suspend and reset paths.

v2: Rebase w.r.t removal of GuC code restructuring.

v3: Removed GuC specific helpers as tasks other than send H2G for
sleep/resume are to be done from uc generic functions. (Michal Wajdeczko)

v4: Simplified/Unified the error messaging in uc_runtime_suspend/resume.
(Michal Wajdeczko). Rebase w.r.t i915_modparams change.
Added documentation to intel_uc_runtime_suspend/resume.

v5: Removed enable_guc_loading based check from intel_uc_runtime_suspend
and intel_uc_runtime_resume and pulled FW load_status based checks from
intel_guc_suspend/resume into these functions. (Michal Wajdeczko)

Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Michał Winiarski 
Reviewed-by: Michal Wajdeczko 
---
 drivers/gpu/drm/i915/i915_guc_submission.c | 11 --
 drivers/gpu/drm/i915/intel_uc.c| 60 +-
 2 files changed, 58 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
b/drivers/gpu/drm/i915/i915_guc_submission.c
index a2f67ca..ca6c4f9 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -1230,11 +1230,6 @@ int intel_guc_suspend(struct drm_i915_private *dev_priv)
struct i915_gem_context *ctx;
u32 data[3];
 
-   if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
-   return 0;
-
-   gen9_disable_guc_interrupts(dev_priv);
-
ctx = dev_priv->kernel_context;
 
data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
@@ -1256,12 +1251,6 @@ int intel_guc_resume(struct drm_i915_private *dev_priv)
struct i915_gem_context *ctx;
u32 data[3];
 
-   if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
-   return 0;
-
-   if (i915_modparams.guc_log_level >= 0)
-   gen9_enable_guc_interrupts(dev_priv);
-
ctx = dev_priv->kernel_context;
 
data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index b900e95..c54b302 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -482,14 +482,70 @@ void intel_uc_fini_hw(struct drm_i915_private *dev_priv)
i915_ggtt_disable_guc(dev_priv);
 }
 
+/**
+ * intel_uc_runtime_suspend() - Suspend uC operation.
+ * @dev_priv: i915 device private
+ *
+ * This function invokes GuC OS suspension, makes ggtt_invalidate function to
+ * point to non-GuC variant, disables GuC interrupts and disable communication
+ * with GuC.
+ *
+ * Return: non-zero code on error
+ */
 int intel_uc_runtime_suspend(struct drm_i915_private *dev_priv)
 {
-   return intel_guc_suspend(dev_priv);
+   int ret;
+
+   if (dev_priv->guc.fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
+   return 0;
+
+   ret = intel_guc_suspend(dev_priv);
+   if (ret)
+   goto out;
+
+   i915_ggtt_disable_guc(dev_priv);
+   gen9_disable_guc_interrupts(dev_priv);
+   guc_disable_communication(_priv->guc);
+
+out:
+   if (ret)
+   DRM_ERROR("uC runtime suspend failed (%d)\n", ret);
+   return ret;
 }
 
+/**
+ * intel_uc_runtime_resume() - Resume uC operation.
+ * @dev_priv: i915 device private
+ *
+ * This function enables communication with GuC, enables GuC interrupts,
+ * makes ggtt_invalidate function to point to GuC variant and invokes
+ * GuC OS resumption.
+ *
+ * Return: non-zero code on error
+ */
 int intel_uc_runtime_resume(struct drm_i915_private *dev_priv)
 {
-   return intel_guc_resume(dev_priv);
+   int ret;
+
+   if (dev_priv->guc.fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
+   return 0;
+
+   ret = guc_enable_communication(_priv->guc);
+   if (ret)
+   goto out;
+
+   if (i915_modparams.guc_log_level >= 0)
+   gen9_enable_guc_interrupts(dev_priv);
+   i915_ggtt_enable_guc(dev_priv);
+
+   ret = intel_guc_resume(dev_priv);
+   if (ret)
+   goto out;
+
+out:
+   if (ret)
+   DRM_ERROR("uC runtime resume failed (%d)\n", ret);
+   return ret;
 }
 
 int intel_uc_suspend(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[Intel-gfx] [PATCH v11 11/11] drm/i915/guc: Fix GuC cleanup in unload path

[Sagar Arun Kamble]

We ensure that GuC is completely suspended and client is destroyed
in i915_gem_suspend during i915_driver_unload. So now intel_uc_fini_hw
should just take care of cleanup,
hence s/intel_uc_fini_hw/intel_uc_cleanup. Correspondingly
we also updated as s/i915_guc_submission_fini/i915_guc_submission_cleanup
Other functionality to disable communication, disable interrupts and
update of ggtt.invalidate is taken care by intel_uc_suspend.

v2: Rebase w.r.t removal of GuC code restructuring.

v3: Removed intel_guc_cleanup. (Michal Wajdeczko)

v4: guc_free_load_err_log() needs to be called without checking
i915.enable_guc_loading as this param is cleared on GuC load failure.
(Michal Wajdeczko)

v5. Rebase.

Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Michał Winiarski 
Reviewed-by: Michal Wajdeczko 
---
 drivers/gpu/drm/i915/i915_drv.c|  2 +-
 drivers/gpu/drm/i915/i915_guc_submission.c |  2 +-
 drivers/gpu/drm/i915/intel_uc.c| 12 +++-
 drivers/gpu/drm/i915/intel_uc.h|  4 ++--
 4 files changed, 7 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 3e772c7..4874ff4 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -603,7 +603,7 @@ static void i915_gem_fini(struct drm_i915_private *dev_priv)
i915_gem_drain_workqueue(dev_priv);
 
mutex_lock(_priv->drm.struct_mutex);
-   intel_uc_fini_hw(dev_priv);
+   intel_uc_cleanup(dev_priv);
i915_gem_cleanup_engines(dev_priv);
i915_gem_contexts_fini(dev_priv);
i915_gem_cleanup_userptr(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
b/drivers/gpu/drm/i915/i915_guc_submission.c
index ab1c382..849f73e 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -1054,7 +1054,7 @@ int i915_guc_submission_init(struct drm_i915_private 
*dev_priv)
return ret;
 }
 
-void i915_guc_submission_fini(struct drm_i915_private *dev_priv)
+void i915_guc_submission_cleanup(struct drm_i915_private *dev_priv)
 {
struct intel_guc *guc = _priv->guc;
 
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index bfecbcc..e40d854 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -445,7 +445,7 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
 err_log_capture:
guc_capture_load_err_log(guc);
 err_submission:
-   i915_guc_submission_fini(dev_priv);
+   i915_guc_submission_cleanup(dev_priv);
 err_guc:
i915_ggtt_disable_guc(dev_priv);
 
@@ -467,17 +467,11 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
return ret;
 }
 
-void intel_uc_fini_hw(struct drm_i915_private *dev_priv)
+void intel_uc_cleanup(struct drm_i915_private *dev_priv)
 {
guc_free_load_err_log(_priv->guc);
 
-   guc_disable_communication(_priv->guc);
-
-   gen9_disable_guc_interrupts(dev_priv);
-   i915_guc_submission_fini(dev_priv);
-
-   if (i915_modparams.enable_guc_loading)
-   i915_ggtt_disable_guc(dev_priv);
+   i915_guc_submission_cleanup(dev_priv);
 }
 
 /**
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 330eb08..5db332d 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -207,7 +207,7 @@ struct intel_huc {
 void intel_uc_init_fw(struct drm_i915_private *dev_priv);
 void intel_uc_fini_fw(struct drm_i915_private *dev_priv);
 int intel_uc_init_hw(struct drm_i915_private *dev_priv);
-void intel_uc_fini_hw(struct drm_i915_private *dev_priv);
+void intel_uc_cleanup(struct drm_i915_private *dev_priv);
 int intel_uc_runtime_suspend(struct drm_i915_private *dev_priv);
 int intel_uc_runtime_resume(struct drm_i915_private *dev_priv);
 int intel_uc_suspend(struct drm_i915_private *dev_priv);
@@ -240,7 +240,7 @@ static inline void intel_guc_notify(struct intel_guc *guc)
 int i915_guc_submission_init(struct drm_i915_private *dev_priv);
 int i915_guc_submission_enable(struct drm_i915_private *dev_priv);
 void i915_guc_submission_disable(struct drm_i915_private *dev_priv);
-void i915_guc_submission_fini(struct drm_i915_private *dev_priv);
+void i915_guc_submission_cleanup(struct drm_i915_private *dev_priv);
 struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);
 
 /* intel_guc_log.c */
-- 
1.9.1

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[Intel-gfx] [PATCH v11 03/11] drm/i915: Move i915_gem_restore_fences to i915_gem_resume

[Sagar Arun Kamble]

i915_gem_restore_fences is GEM resumption task hence it is moved to
i915_gem_resume from i915_restore_state.

Signed-off-by: Sagar Arun Kamble 
Cc: Chris Wilson 
Cc: Michal Wajdeczko 
Cc: Michał Winiarski 
---
 drivers/gpu/drm/i915/i915_gem.c | 1 +
 drivers/gpu/drm/i915/i915_suspend.c | 2 --
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 932ac22..889b35f 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4611,6 +4611,7 @@ int i915_gem_resume(struct drm_i915_private *dev_priv)
 
mutex_lock(>struct_mutex);
i915_gem_restore_gtt_mappings(dev_priv);
+   i915_gem_restore_fences(dev_priv);
 
/* As we didn't flush the kernel context before suspend, we cannot
 * guarantee that the context image is complete. So let's just reset
diff --git a/drivers/gpu/drm/i915/i915_suspend.c 
b/drivers/gpu/drm/i915/i915_suspend.c
index 5c86925a..8f3aa4d 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -108,8 +108,6 @@ int i915_restore_state(struct drm_i915_private *dev_priv)
 
mutex_lock(_priv->drm.struct_mutex);
 
-   i915_gem_restore_fences(dev_priv);
-
if (IS_GEN4(dev_priv))
pci_write_config_word(pdev, GCDGMBUS,
  dev_priv->regfile.saveGCDGMBUS);
-- 
1.9.1

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[Intel-gfx] [PATCH v11 01/11] drm/i915: Create GEM runtime resume helper and handle GEM suspend/resume errors

[Sagar Arun Kamble]

These changes are preparation to handle GuC suspend/resume. Prepared
helper i915_gem_runtime_resume to reinitialize suspended gem setup.
Returning status from i915_gem_runtime_suspend and i915_gem_resume.
This will be placeholder for handling any errors from uC suspend/resume
in upcoming patches. Restructured the suspend/resume routines w.r.t setup
creation and rollback order.
This also fixes issue of ordering of i915_gem_runtime_resume with
intel_runtime_pm_enable_interrupts.

v2: Fixed return from intel_runtime_resume. (Michał Winiarski)

v3: Not returning status from gem_runtime_resume. (Chris)

v4: Refined return from i915_gem_runtime_suspend. (Michal Wajdeczko)

Signed-off-by: Sagar Arun Kamble 
Cc: Chris Wilson 
Cc: Imre Deak 
Cc: Paulo Zanoni 
Cc: Rodrigo Vivi 
Cc: Michal Wajdeczko 
Cc: Michał Winiarski 
---
 drivers/gpu/drm/i915/i915_drv.c | 33 +++--
 drivers/gpu/drm/i915/i915_drv.h |  5 +++--
 drivers/gpu/drm/i915/i915_gem.c | 18 --
 3 files changed, 38 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 7056bb2..502ae13 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1655,6 +1655,7 @@ static int i915_suspend_switcheroo(struct drm_device 
*dev, pm_message_t state)
 static int i915_drm_resume(struct drm_device *dev)
 {
struct drm_i915_private *dev_priv = to_i915(dev);
+   struct pci_dev *pdev = dev_priv->drm.pdev;
int ret;
 
disable_rpm_wakeref_asserts(dev_priv);
@@ -1666,7 +1667,9 @@ static int i915_drm_resume(struct drm_device *dev)
 
intel_csr_ucode_resume(dev_priv);
 
-   i915_gem_resume(dev_priv);
+   ret = i915_gem_resume(dev_priv);
+   if (ret)
+   dev_err(>dev, "GEM resume failed\n");
 
i915_restore_state(dev_priv);
intel_pps_unlock_regs_wa(dev_priv);
@@ -2495,7 +2498,9 @@ static int intel_runtime_suspend(struct device *kdev)
 * We are safe here against re-faults, since the fault handler takes
 * an RPM reference.
 */
-   i915_gem_runtime_suspend(dev_priv);
+   ret = i915_gem_runtime_suspend(dev_priv);
+   if (ret)
+   goto err_gem_suspend;
 
intel_guc_suspend(dev_priv);
 
@@ -2513,11 +2518,7 @@ static int intel_runtime_suspend(struct device *kdev)
 
if (ret) {
DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
-   intel_runtime_pm_enable_interrupts(dev_priv);
-
-   enable_rpm_wakeref_asserts(dev_priv);
-
-   return ret;
+   goto err_suspend_complete;
}
 
intel_uncore_suspend(dev_priv);
@@ -2560,6 +2561,15 @@ static int intel_runtime_suspend(struct device *kdev)
 
DRM_DEBUG_KMS("Device suspended\n");
return 0;
+
+err_suspend_complete:
+   intel_runtime_pm_enable_interrupts(dev_priv);
+   intel_guc_resume(dev_priv);
+   i915_gem_runtime_resume(dev_priv);
+
+err_gem_suspend:
+   enable_rpm_wakeref_asserts(dev_priv);
+   return ret;
 }
 
 static int intel_runtime_resume(struct device *kdev)
@@ -2596,13 +2606,6 @@ static int intel_runtime_resume(struct device *kdev)
ret = vlv_resume_prepare(dev_priv, true);
}
 
-   /*
-* No point of rolling back things in case of an error, as the best
-* we can do is to hope that things will still work (and disable RPM).
-*/
-   i915_gem_init_swizzling(dev_priv);
-   i915_gem_restore_fences(dev_priv);
-
intel_runtime_pm_enable_interrupts(dev_priv);
 
/*
@@ -2615,6 +2618,8 @@ static int intel_runtime_resume(struct device *kdev)
 
intel_enable_ipc(dev_priv);
 
+   i915_gem_runtime_resume(dev_priv);
+
enable_rpm_wakeref_asserts(dev_priv);
 
if (ret)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b7cba89..42f3d89 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3479,7 +3479,8 @@ struct i915_vma * __must_check
 int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
 
-void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
+int i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
+void i915_gem_runtime_resume(struct drm_i915_private *dev_priv);
 
 static inline int __sg_page_count(const struct scatterlist *sg)
 {
@@ -3682,7 +3683,7 @@ void i915_gem_reset_engine(struct intel_engine_cs *engine,
 int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
   unsigned int flags);
 int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
-void i915_gem_resume(struct drm_i915_private 

[Intel-gfx] [PATCH v11 05/11] drm/i915/guc: Introduce intel_uc_sanitize

[Sagar Arun Kamble]

Currently GPU is reset at the end of suspend via i915_gem_sanitize.
On resume, GuC will not be loaded until intel_uc_init_hw happens
during GEM resume flow but action to exit sleep can be sent to GuC
considering the FW load status. To make sure we don't invoke that
action update GuC FW load status at the end of GPU reset as NONE.
load_status indicates HW state and it is sanitized through this new
function intel_uc_sanitize.

v2: Rebase.

v3: Removed intel_guc_sanitize. Marking load status as NONE at the
GPU reset point. (Chris/Michal)

v4: Reinstated the uC function intel_uc_sanitize. (Michal Wajdeczko)

Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Michał Winiarski 
Cc: Chris Wilson 
---
 drivers/gpu/drm/i915/intel_uc.c | 12 
 drivers/gpu/drm/i915/intel_uc.h |  1 +
 drivers/gpu/drm/i915/intel_uncore.c |  3 +++
 3 files changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 80251ec..ab26232 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -508,6 +508,18 @@ int intel_uc_resume(struct drm_i915_private *dev_priv)
return intel_guc_resume(dev_priv);
 }
 
+void intel_uc_sanitize(struct drm_i915_private *dev_priv)
+{
+   /*
+* FIXME: intel_uc_resume currently depends on load_status to resume
+* GuC. Since we are resetting Full GPU at the end of suspend, let us
+* mark the load status as NONE. Once intel_uc_resume is updated to take
+* into consideration GuC load state based on WOPCM, we can skip this
+* state update.
+*/
+   dev_priv->guc.fw.load_status = INTEL_UC_FIRMWARE_NONE;
+}
+
 int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len)
 {
WARN(1, "Unexpected send: action=%#x\n", *action);
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 0a79e17..ce3cea5 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -212,6 +212,7 @@ struct intel_huc {
 int intel_uc_runtime_resume(struct drm_i915_private *dev_priv);
 int intel_uc_suspend(struct drm_i915_private *dev_priv);
 int intel_uc_resume(struct drm_i915_private *dev_priv);
+void intel_uc_sanitize(struct drm_i915_private *dev_priv);
 int intel_guc_sample_forcewake(struct intel_guc *guc);
 int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len);
 int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len);
diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
b/drivers/gpu/drm/i915/intel_uncore.c
index b3c3f94..acab013 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1763,6 +1763,9 @@ int intel_gpu_reset(struct drm_i915_private *dev_priv, 
unsigned engine_mask)
}
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 
+   if (engine_mask == ALL_ENGINES)
+   intel_uc_sanitize(dev_priv);
+
return ret;
 }
 
-- 
1.9.1

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[Intel-gfx] [PATCH v11 10/11] drm/i915/guc: Disable GuC submission and suspend it prior to i915 reset

[Sagar Arun Kamble]

Before i915 reset, we need to disable GuC submission and suspend GuC
operations as it is recreated during intel_uc_init_hw. We can't reuse the
intel_uc_suspend functionality as reset path already holds struct_mutex.

v2: Rebase w.r.t removal of GuC code restructuring. Updated reset_prepare
function as struct_mutex is not needed.

v3: Fixed typo in commit message. Made return from intel_uc_reset_prepare
simpler. (Michal)
Rebase w.r.t i915_modparams change.

v4: Rebase. Removed enable_guc_submission check for disabling GuC
submission. (Chris)

v5: Rebase.

Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Michał Winiarski 
Reviewed-by: Michal Wajdeczko 
---
 drivers/gpu/drm/i915/i915_gem.c | 2 ++
 drivers/gpu/drm/i915/intel_uc.c | 7 +++
 drivers/gpu/drm/i915/intel_uc.h | 1 +
 3 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 1f61d9c..87351d8 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2865,6 +2865,8 @@ int i915_gem_reset_prepare(struct drm_i915_private 
*dev_priv)
 
i915_gem_revoke_fences(dev_priv);
 
+   intel_uc_reset_prepare(dev_priv);
+
return err;
 }
 
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 9f137a9..bfecbcc 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -572,6 +572,13 @@ void intel_uc_sanitize(struct drm_i915_private *dev_priv)
dev_priv->guc.fw.load_status = INTEL_UC_FIRMWARE_NONE;
 }
 
+int intel_uc_reset_prepare(struct drm_i915_private *dev_priv)
+{
+   i915_guc_submission_disable(dev_priv);
+
+   return intel_uc_runtime_suspend(dev_priv);
+}
+
 int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len)
 {
WARN(1, "Unexpected send: action=%#x\n", *action);
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index ce3cea5..330eb08 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -212,6 +212,7 @@ struct intel_huc {
 int intel_uc_runtime_resume(struct drm_i915_private *dev_priv);
 int intel_uc_suspend(struct drm_i915_private *dev_priv);
 int intel_uc_resume(struct drm_i915_private *dev_priv);
+int intel_uc_reset_prepare(struct drm_i915_private *dev_priv);
 void intel_uc_sanitize(struct drm_i915_private *dev_priv);
 int intel_guc_sample_forcewake(struct intel_guc *guc);
 int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len);
-- 
1.9.1

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[Intel-gfx] [PATCH v11 04/11] drm/i915: Create uC runtime and system suspend/resume helpers

[Sagar Arun Kamble]

Prepared generic helpers intel_uc_suspend, intel_uc_resume,
intel_uc_runtime_suspend, intel_uc_runtime_resume. These are
called from respective GEM functions.
Only exception is intel_uc_resume that needs to be called
w/ or w/o GuC loaded in i915_drm_resume path. Changes to
add WOPCM condition check to load GuC during resume will be added
in later patches.

v2: Rebase w.r.t removal of GuC code restructuring.

v3: Calling intel_uc_resume from i915_gem_resume post resuming
i915 gem setup. This is symmetrical with i915_gem_suspend.
Removed error messages from i915 suspend/resume routines as
uC suspend/resume routines will have those. (Michal Wajdeczko)
Declare wedged on uc_suspend failure and uc_resume failure.
(Michał Winiarski)
Keeping the uC suspend/resume function definitions close to other
uC functions.

v4: Added implementation to intel_uc_resume as GuC resume is
needed to be triggered post reloading the firmware as well. Added
comments about semantics of GuC resume with the firmware reload.

v5: Updated return from i915_gem_runtime_suspend. Moved the comment
about GuC reload optimization to intel_uc_init_hw. (Michal Wajdeczko)
Updated FIXME correctly for these comments.

Signed-off-by: Sagar Arun Kamble 
Cc: Chris Wilson 
Cc: Michal Wajdeczko 
Cc: Michał Winiarski 
---
 drivers/gpu/drm/i915/i915_drv.c | 10 ++
 drivers/gpu/drm/i915/i915_gem.c | 24 +++-
 drivers/gpu/drm/i915/intel_uc.c | 27 +++
 drivers/gpu/drm/i915/intel_uc.h |  4 
 4 files changed, 60 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index a9821ae..3e772c7 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1698,6 +1698,16 @@ static int i915_drm_resume(struct drm_device *dev)
}
mutex_unlock(>struct_mutex);
 
+   /*
+* NB: Currently we know that at the end of suspend we have done Full
+* GPU reset and GuC is loaded again during i915_gem_init_hw.
+* Now, send action to GuC to resume back again as earlier call to
+* intel_uc_resume from i915_gem_resume would have done nothing.
+*/
+   ret = intel_uc_resume(dev_priv);
+   if (ret)
+   i915_gem_set_wedged(dev_priv);
+
intel_modeset_init_hw(dev);
 
spin_lock_irq(_priv->irq_lock);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 889b35f..1f61d9c 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2025,9 +2025,11 @@ int i915_gem_fault(struct vm_fault *vmf)
 int i915_gem_runtime_suspend(struct drm_i915_private *dev_priv)
 {
struct drm_i915_gem_object *obj, *on;
-   int i;
+   int i, ret;
 
-   intel_guc_suspend(dev_priv);
+   ret = intel_uc_runtime_suspend(dev_priv);
+   if (ret)
+   return ret;
 
/*
 * Only called during RPM suspend. All users of the userfault_list
@@ -2080,7 +2082,7 @@ void i915_gem_runtime_resume(struct drm_i915_private 
*dev_priv)
i915_gem_init_swizzling(dev_priv);
i915_gem_restore_fences(dev_priv);
 
-   intel_guc_resume(dev_priv);
+   intel_uc_runtime_resume(dev_priv);
 }
 
 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
@@ -4571,7 +4573,9 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv)
if (WARN_ON(!intel_engines_are_idle(dev_priv)))
i915_gem_set_wedged(dev_priv); /* no hope, discard everything */
 
-   intel_guc_suspend(dev_priv);
+   ret = intel_uc_suspend(dev_priv);
+   if (ret)
+   i915_gem_set_wedged(dev_priv); /* no hope, discard everything */
 
/*
 * Neither the BIOS, ourselves or any other kernel
@@ -4606,6 +4610,7 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv)
 int i915_gem_resume(struct drm_i915_private *dev_priv)
 {
struct drm_device *dev = _priv->drm;
+   int ret;
 
WARN_ON(dev_priv->gt.awake);
 
@@ -4619,7 +4624,16 @@ int i915_gem_resume(struct drm_i915_private *dev_priv)
 */
dev_priv->gt.resume(dev_priv);
 
-   intel_guc_resume(dev_priv);
+   /*
+* FIXME: At the end of suspend, Full GPU reset is done which unloads
+* the GuC firmware. If reset is avoided there, we can check the WOPCM
+* status here to see if GuC is still loaded and just do GuC resume
+* without reloading the firmware back.
+*/
+   ret = intel_uc_resume(dev_priv);
+   if (ret)
+   i915_gem_set_wedged(dev_priv);
+
mutex_unlock(>struct_mutex);
 
return 0;
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 2774778..80251ec 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -373,6 +373,13 @@ int 

[Intel-gfx] [PATCH v11 00/11] GEM/GuC Suspend/Resume/Reset fixes and restructuring

[Sagar Arun Kamble]

Older series can be found at
https://patchwork.freedesktop.org/series/30715/
https://patchwork.freedesktop.org/series/30502/
https://patchwork.freedesktop.org/series/30351/

v1-v8: Part of above three series.

v9:
Fixed patch 1 based on review inputs from Michal Winiarski.
Rebased all patches. Updated ordering of cc, s-o-b, r-b tags for all patches.

v10: Added new patch (6th). Addressed reviews on v9.

v11: Created separate patch for i915_gem_restore_fences change.
Added changes to disable/destroy GuC without dependency on
enable_guc_loading and enable_guc_submission. Rebased other patches.

Cc: Chris Wilson 
Cc: Imre Deak 
Cc: Paulo Zanoni 
Cc: Rodrigo Vivi 
Cc: Michal Wajdeczko 
Cc: Michał Winiarski 
Cc: Joonas Lahtinen 

Sagar Arun Kamble (11):
  drm/i915: Create GEM runtime resume helper and handle GEM
suspend/resume errors
  drm/i915: Update GEM suspend/resume flows with GuC suspend/resume
functions
  drm/i915: Move i915_gem_restore_fences to i915_gem_resume
  drm/i915: Create uC runtime and system suspend/resume helpers
  drm/i915/guc: Introduce intel_uc_sanitize
  drm/i915/guc: Make GuC related disable/destroy functions not depend on
i915.enable_guc_submission
  drm/i915/guc: Update i915.enable_guc_loading check in intel_uc_fini_hw
  drm/i915/guc: Update GuC ggtt.invalidate/interrupts/communication
across RPM suspend/resume
  drm/i915/guc: Update GuC suspend functionality in intel_uc_suspend
  drm/i915/guc: Disable GuC submission and suspend it prior to i915
reset
  drm/i915/guc: Fix GuC cleanup in unload path

 drivers/gpu/drm/i915/i915_drv.c|  48 +++-
 drivers/gpu/drm/i915/i915_drv.h|   5 +-
 drivers/gpu/drm/i915/i915_gem.c|  46 ++--
 drivers/gpu/drm/i915/i915_guc_submission.c |  29 +++-
 drivers/gpu/drm/i915/i915_irq.c|   6 ++
 drivers/gpu/drm/i915/i915_suspend.c|   2 -
 drivers/gpu/drm/i915/intel_guc_log.c   |   6 +-
 drivers/gpu/drm/i915/intel_uc.c| 116 ++---
 drivers/gpu/drm/i915/intel_uc.h|  10 ++-
 drivers/gpu/drm/i915/intel_uncore.c|   3 +
 10 files changed, 206 insertions(+), 65 deletions(-)

-- 
1.9.1

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[Intel-gfx] [PATCH v11 07/11] drm/i915/guc: Update i915.enable_guc_loading check in intel_uc_fini_hw

[Sagar Arun Kamble]

With most of the GuC disabling now separated from enable_guc_submission
parameter, only function that needs GuC parameter check is
i915_disable_guc_ggtt as that is enabled based on GuC kernel parameters.
Hence i915_disable_guc_ggtt is being called when enable_guc_loading is
set.

Signed-off-by: Sagar Arun Kamble 
Cc: Chris Wilson 
Cc: Michal Wajdeczko 
Cc: Michał Winiarski 
---
 drivers/gpu/drm/i915/intel_uc.c | 6 ++
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index ea7c39c..b900e95 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -471,9 +471,6 @@ void intel_uc_fini_hw(struct drm_i915_private *dev_priv)
 {
guc_free_load_err_log(_priv->guc);
 
-   if (!i915_modparams.enable_guc_loading)
-   return;
-
i915_guc_submission_disable(dev_priv);
 
guc_disable_communication(_priv->guc);
@@ -481,7 +478,8 @@ void intel_uc_fini_hw(struct drm_i915_private *dev_priv)
gen9_disable_guc_interrupts(dev_priv);
i915_guc_submission_fini(dev_priv);
 
-   i915_ggtt_disable_guc(dev_priv);
+   if (i915_modparams.enable_guc_loading)
+   i915_ggtt_disable_guc(dev_priv);
 }
 
 int intel_uc_runtime_suspend(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[Intel-gfx] [PATCH v11 09/11] drm/i915/guc: Update GuC suspend functionality in intel_uc_suspend

[Sagar Arun Kamble]

With this patch we disable GuC submission in i915_drm_suspend path.
This will destroy the client which will be setup back again. We also
reuse the complete sanitization done via intel_uc_runtime_suspend in
this path. Post i915_drm_resume, this state is recreated by
intel_uc_init_hw hence we need not have similar reuse for intel_uc_resume.
This also fixes issue where intel_uc_fini_hw was being called after GPU
reset happening in i915_gem_suspend during i915_driver_unload.

v2: Rebase w.r.t removal of GuC code restructuring. Added struct_mutex
protection for i915_guc_submission_disable.

v3: Rebase w.r.t updated GuC suspend function name.

v4: Added lockdep assert in i915_guc_submission_enable/disable.
Refined intel_uc_suspend to remove unnecessary locals and simplify
return. (Michal Winiarski)
Removed comment in guc_client_free about ignoring failure for
destroy_doorbell. (Oscar)
Rebase w.r.t i915_modparams change.

v5: Removed lockdep assert as mutex is needed by internal functions
which already have the asserts. (Chris)
Removed enable_guc_submission check for disabling GuC submission. (Chris)

v6: Rebase with enable_guc_submission related change done in earlier
newly introduced patches.

Signed-off-by: Sagar Arun Kamble 
Cc: Michal Wajdeczko 
Cc: Michał Winiarski 
Reviewed-by: Michał Winiarski 
---
 drivers/gpu/drm/i915/i915_guc_submission.c | 3 ---
 drivers/gpu/drm/i915/intel_uc.c| 8 +---
 2 files changed, 5 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
b/drivers/gpu/drm/i915/i915_guc_submission.c
index ca6c4f9..ab1c382 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -885,9 +885,6 @@ static void guc_client_free(struct i915_guc_client *client)
 * Be sure to drop any locks
 */
 
-   /* FIXME: in many cases, by the time we get here the GuC has been
-* reset, so we cannot destroy the doorbell properly. Ignore the
-* error message for now */
destroy_doorbell(client);
guc_stage_desc_fini(client->guc, client);
i915_gem_object_unpin_map(client->vma->obj);
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index c54b302..9f137a9 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -471,8 +471,6 @@ void intel_uc_fini_hw(struct drm_i915_private *dev_priv)
 {
guc_free_load_err_log(_priv->guc);
 
-   i915_guc_submission_disable(dev_priv);
-
guc_disable_communication(_priv->guc);
 
gen9_disable_guc_interrupts(dev_priv);
@@ -550,7 +548,11 @@ int intel_uc_runtime_resume(struct drm_i915_private 
*dev_priv)
 
 int intel_uc_suspend(struct drm_i915_private *dev_priv)
 {
-   return intel_guc_suspend(dev_priv);
+   mutex_lock(_priv->drm.struct_mutex);
+   i915_guc_submission_disable(dev_priv);
+   mutex_unlock(_priv->drm.struct_mutex);
+
+   return intel_uc_runtime_suspend(dev_priv);
 }
 
 int intel_uc_resume(struct drm_i915_private *dev_priv)
-- 
1.9.1

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[Intel-gfx] [PATCH v11 02/11] drm/i915: Update GEM suspend/resume flows with GuC suspend/resume functions

[Sagar Arun Kamble]

This patch moves GuC suspend/resume handlers to corresponding GEM handlers
and orders them properly in the runtime and system suspend/resume flows.

v2: Removed documentation of suspend/resume handlers as those are not
interfaces and are just hooks. (Chris)

v3: Rebase. Removed i915_gem_restore_fences change from this patch.
(Michal Wajdeczko)

Signed-off-by: Sagar Arun Kamble 
Cc: Chris Wilson 
Cc: Imre Deak 
Cc: Paulo Zanoni 
Cc: Rodrigo Vivi 
Cc: Michal Wajdeczko 
Cc: Michał Winiarski 
---
 drivers/gpu/drm/i915/i915_drv.c | 7 ---
 drivers/gpu/drm/i915/i915_gem.c | 9 +++--
 2 files changed, 7 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 502ae13..a9821ae 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1698,8 +1698,6 @@ static int i915_drm_resume(struct drm_device *dev)
}
mutex_unlock(>struct_mutex);
 
-   intel_guc_resume(dev_priv);
-
intel_modeset_init_hw(dev);
 
spin_lock_irq(_priv->irq_lock);
@@ -2502,8 +2500,6 @@ static int intel_runtime_suspend(struct device *kdev)
if (ret)
goto err_gem_suspend;
 
-   intel_guc_suspend(dev_priv);
-
intel_runtime_pm_disable_interrupts(dev_priv);
 
ret = 0;
@@ -2564,7 +2560,6 @@ static int intel_runtime_suspend(struct device *kdev)
 
 err_suspend_complete:
intel_runtime_pm_enable_interrupts(dev_priv);
-   intel_guc_resume(dev_priv);
i915_gem_runtime_resume(dev_priv);
 
 err_gem_suspend:
@@ -2592,8 +2587,6 @@ static int intel_runtime_resume(struct device *kdev)
if (intel_uncore_unclaimed_mmio(dev_priv))
DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
 
-   intel_guc_resume(dev_priv);
-
if (IS_GEN9_LP(dev_priv)) {
bxt_disable_dc9(dev_priv);
bxt_display_core_init(dev_priv, true);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 59a88f2..932ac22 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2027,6 +2027,8 @@ int i915_gem_runtime_suspend(struct drm_i915_private 
*dev_priv)
struct drm_i915_gem_object *obj, *on;
int i;
 
+   intel_guc_suspend(dev_priv);
+
/*
 * Only called during RPM suspend. All users of the userfault_list
 * must be holding an RPM wakeref to ensure that this can not
@@ -2077,6 +2079,8 @@ void i915_gem_runtime_resume(struct drm_i915_private 
*dev_priv)
 */
i915_gem_init_swizzling(dev_priv);
i915_gem_restore_fences(dev_priv);
+
+   intel_guc_resume(dev_priv);
 }
 
 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
@@ -4551,8 +4555,6 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv)
i915_gem_contexts_lost(dev_priv);
mutex_unlock(>struct_mutex);
 
-   intel_guc_suspend(dev_priv);
-
cancel_delayed_work_sync(_priv->gpu_error.hangcheck_work);
cancel_delayed_work_sync(_priv->gt.retire_work);
 
@@ -4569,6 +4571,8 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv)
if (WARN_ON(!intel_engines_are_idle(dev_priv)))
i915_gem_set_wedged(dev_priv); /* no hope, discard everything */
 
+   intel_guc_suspend(dev_priv);
+
/*
 * Neither the BIOS, ourselves or any other kernel
 * expects the system to be in execlists mode on startup,
@@ -4614,6 +4618,7 @@ int i915_gem_resume(struct drm_i915_private *dev_priv)
 */
dev_priv->gt.resume(dev_priv);
 
+   intel_guc_resume(dev_priv);
mutex_unlock(>struct_mutex);
 
return 0;
-- 
1.9.1

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[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,01/11] drm/i915/execlists: Move request unwinding to a separate function

[Patchwork]

== Series Details ==

Series: series starting with [v2,01/11] drm/i915/execlists: Move request 
unwinding to a separate function
URL   : https://patchwork.freedesktop.org/series/30983/
State : success

== Summary ==

Series 30983v1 series starting with [v2,01/11] drm/i915/execlists: Move request 
unwinding to a separate function
https://patchwork.freedesktop.org/api/1.0/series/30983/revisions/1/mbox/

Test kms_frontbuffer_tracking:
Subgroup basic:
pass   -> DMESG-WARN (fi-bdw-5557u) fdo#102473
Test pm_rpm:
Subgroup basic-rte:
pass   -> DMESG-WARN (fi-cfl-s) fdo#102294
Test drv_module_reload:
Subgroup basic-reload:
dmesg-warn -> PASS   (fi-glk-1) fdo#102777 +1

fdo#102473 https://bugs.freedesktop.org/show_bug.cgi?id=102473
fdo#102294 https://bugs.freedesktop.org/show_bug.cgi?id=102294
fdo#102777 https://bugs.freedesktop.org/show_bug.cgi?id=102777

fi-bdw-5557u total:289  pass:267  dwarn:1   dfail:0   fail:0   skip:21  
time:437s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:471s
fi-blb-e6850 total:289  pass:224  dwarn:1   dfail:0   fail:0   skip:64  
time:417s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:516s
fi-bwr-2160  total:289  pass:184  dwarn:0   dfail:0   fail:0   skip:105 
time:278s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:502s
fi-byt-j1900 total:289  pass:254  dwarn:1   dfail:0   fail:0   skip:34  
time:496s
fi-cfl-s total:289  pass:222  dwarn:35  dfail:0   fail:0   skip:32  
time:537s
fi-cnl-y total:289  pass:258  dwarn:0   dfail:0   fail:4   skip:27  
time:640s
fi-elk-e7500 total:289  pass:230  dwarn:0   dfail:0   fail:0   skip:59  
time:426s
fi-glk-1 total:289  pass:259  dwarn:1   dfail:0   fail:0   skip:29  
time:561s
fi-hsw-4770  total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:423s
fi-hsw-4770r total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:403s
fi-ilk-650   total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:429s
fi-ivb-3520m total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:489s
fi-ivb-3770  total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:463s
fi-kbl-7500u total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  
time:471s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:578s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:589s
fi-pnv-d510  total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:544s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:451s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:752s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:487s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:474s
fi-snb-2520m total:289  pass:251  dwarn:0   dfail:0   fail:0   skip:38  
time:566s
fi-snb-2600  total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:414s

aa884e1abdf2ffb7db8c524fc6269280734e5145 drm-tip: 2017y-09m-27d-15h-39m-07s UTC 
integration manifest
881ebce6c68a drm/i915/scheduler: Support user-defined priorities
7e29babc051f drm/i915/execlists: Preemption!
2ee2b66cbc55 drm/i915: Expand I915_PARAM_HAS_SCHEDULER into a capability bitmask
e440aa1cfb3b drm/i915/execlists: Keep request->priority for its lifetime
87a53d538b53 drm/i915/execlists: Move bdw GPGPU w/a to emit_bb
d45c37f2e91f drm/i915: Introduce a preempt context
fc6e993d1e56 drm/i915/execlists: Distinguish the incomplete context notifies
5f5faf86f76a drm/i915/preempt: Default to disabled mid-command preemption levels
8091c7afe694 drm/i915/preempt: Fix WaEnablePreemptionGranularityControlByUMD
cbd5945306cd drm/i915/execlists: Cache the last priolist lookup
2ab121643f85 drm/i915/execlists: Move request unwinding to a separate function

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5835/
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[Intel-gfx] ✗ Fi.CI.IGT: failure for lib/igt_kms: Convert properties to be more atomic-like. (rev2)

[Patchwork]

== Series Details ==

Series: lib/igt_kms: Convert properties to be more atomic-like. (rev2)
URL   : https://patchwork.freedesktop.org/series/30903/
State : failure

== Summary ==

Test pm_rpm:
Subgroup modeset-lpsp:
pass   -> SKIP   (shard-hsw)
Subgroup modeset-lpsp-stress-no-wait:
pass   -> SKIP   (shard-hsw)
Subgroup reg-read-ioctl:
skip   -> PASS   (shard-hsw)
Subgroup gem-idle:
skip   -> PASS   (shard-hsw)
Subgroup dpms-non-lpsp:
skip   -> PASS   (shard-hsw)
Subgroup modeset-pc8-residency-stress:
pass   -> SKIP   (shard-hsw)
Subgroup gem-execbuf-stress-pc8:
pass   -> SKIP   (shard-hsw)
Subgroup gem-mmap-gtt:
skip   -> PASS   (shard-hsw)
Subgroup pm-tiling:
skip   -> PASS   (shard-hsw)
Subgroup debugfs-read:
fail   -> PASS   (shard-hsw)
Subgroup system-suspend-modeset:
skip   -> PASS   (shard-hsw)
Subgroup modeset-lpsp-stress:
pass   -> SKIP   (shard-hsw)
Subgroup gem-evict-pwrite:
skip   -> PASS   (shard-hsw)
Subgroup dpms-lpsp:
pass   -> SKIP   (shard-hsw)
Subgroup system-suspend-execbuf:
skip   -> PASS   (shard-hsw)
Test prime_busy:
Subgroup after-vebox:
skip   -> PASS   (shard-hsw)
Subgroup before-vebox:
skip   -> PASS   (shard-hsw)
Subgroup after-bsd1:
pass   -> SKIP   (shard-hsw)
Subgroup before-bsd1:
pass   -> SKIP   (shard-hsw)
Subgroup before-render:
skip   -> PASS   (shard-hsw)
Subgroup basic-before-default:
skip   -> PASS   (shard-hsw)
Subgroup basic-after-default:
skip   -> PASS   (shard-hsw)
Subgroup hang-bsd:
skip   -> PASS   (shard-hsw)
Subgroup after-blt:
skip   -> PASS   (shard-hsw)
Subgroup hang-blt:
skip   -> PASS   (shard-hsw)
Subgroup wait-hang-bsd1:
pass   -> SKIP   (shard-hsw)
Subgroup wait-hang-render:
skip   -> PASS   (shard-hsw)
Subgroup wait-before-bsd2:
pass   -> SKIP   (shard-hsw)
Subgroup wait-after-bsd2:
pass   -> SKIP   (shard-hsw)
Subgroup hang-vebox:
skip   -> PASS   (shard-hsw)
Test kms_flip:
Subgroup 2x-flip-vs-wf_vblank:
pass   -> SKIP   (shard-hsw)
Subgroup vblank-vs-suspend:
skip   -> PASS   (shard-hsw)
Subgroup 2x-single-buffer-flip-vs-dpms-off-vs-modeset:
pass   -> SKIP   (shard-hsw)
Subgroup blt-wf_vblank-vs-modeset-interruptible:
skip   -> PASS   (shard-hsw)
Subgroup flip-vs-fences:
fail   -> PASS   (shard-hsw)
Subgroup plain-flip-fb-recreate-interruptible:
skip   -> PASS   (shard-hsw) fdo#100368 +1
Subgroup 2x-blt-flip-vs-panning:
pass   -> SKIP   (shard-hsw)
Subgroup flip-vs-panning:
skip   -> PASS   (shard-hsw)
Subgroup 2x-blt-wf_vblank-vs-modeset-interruptible:
pass   -> SKIP   (shard-hsw)
Subgroup 2x-render-flip-vs-panning:
pass   -> SKIP   (shard-hsw)
Subgroup 2x-vblank-vs-hang-interruptible:
pass   -> SKIP   (shard-hsw)
Subgroup wf_vblank-vs-modeset:
skip   -> PASS   (shard-hsw) fdo#102614 +2
Subgroup 2x-vblank-vs-suspend:
fail   -> SKIP   (shard-hsw)
Subgroup wf_vblank-vs-modeset-interruptible:
skip   -> PASS   (shard-hsw)
Subgroup 2x-busy-flip:
pass   -> SKIP   (shard-hsw)
Subgroup 2x-absolute-wf_vblank-interruptible:
pass   -> SKIP   (shard-hsw)
Subgroup basic-flip-vs-wf_vblank:
skip   -> PASS   (shard-hsw)
Subgroup 2x-wf_vblank-vs-modeset-interruptible:
pass   -> SKIP   (shard-hsw)
Subgroup blocking-wf_vblank:
skip   -> PASS   (shard-hsw)
Subgroup 2x-flip-vs-expired-vblank-interruptible:
pass   -> SKIP   (shard-hsw)
Subgroup 2x-vblank-vs-suspend-interruptible:
pass   -> SKIP   (shard-hsw)
Subgroup 2x-wf_vblank-vs-dpms-interruptible:

[Intel-gfx] [PATCH] drm/i915: Also discard second CRC on gen8+ platforms.

[Rodrigo Vivi]

One of the differences I spotted for GEN8+ platforms when
compared to older platforms is that spec for BDW+ includes
this sentence:

"The first CRC done indication after CRC is first enabled is
from only a partial frame, so it will not have the expected
CRC result."

This is an indication that on BDW+ platforms, by the time
we receive the interrupt the CRC is not accurate yet for
the full frame. That would be ok, because we are already
skipping the first CRC for all platforms. However the comment
on the code state that it is for some unknown reason. Also,
on CHV (gen8 lp) we were already discarding the second CRC
as well to make sure we have a reliable CRC on hand.

So based on all ou tests and bugs it seems that it is not
on CHV that needs to discard 2 first CRCs, but all BDW+
platforms.

Starting on SKL we have this CRC done bit (24), but the
experiments around the use of this bit wasn't that stable
as just discarding the second CRC. So, let's for now
just move with CHV solution for all gen8+ platforms and
make our CI a bit more stable.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102374
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101309
Cc: Mika Kahola 
Signed-off-by: Rodrigo Vivi 
---
 drivers/gpu/drm/i915/i915_irq.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 0b7562135d1c..efd7827ff181 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1647,11 +1647,11 @@ static void display_pipe_crc_irq_handler(struct 
drm_i915_private *dev_priv,
 * bonkers. So let's just wait for the next vblank and read
 * out the buggy result.
 *
-* On CHV sometimes the second CRC is bonkers as well, so
+* On GEN8+ sometimes the second CRC is bonkers as well, so
 * don't trust that one either.
 */
if (pipe_crc->skipped == 0 ||
-   (IS_CHERRYVIEW(dev_priv) && pipe_crc->skipped == 1)) {
+   (INTEL_GEN(dev_priv) >= 8 && pipe_crc->skipped == 1)) {
pipe_crc->skipped++;
spin_unlock(_crc->lock);
return;
-- 
2.13.5

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Also discard second CRC on gen8+ platforms.

[Patchwork]

== Series Details ==

Series: drm/i915: Also discard second CRC on gen8+ platforms.
URL   : https://patchwork.freedesktop.org/series/31023/
State : success

== Summary ==

Series 31023v1 drm/i915: Also discard second CRC on gen8+ platforms.
https://patchwork.freedesktop.org/api/1.0/series/31023/revisions/1/mbox/

Test chamelium:
Subgroup dp-crc-fast:
pass   -> FAIL   (fi-kbl-7500u) fdo#102514
Test drv_module_reload:
Subgroup basic-reload:
dmesg-warn -> PASS   (fi-glk-1) fdo#102777

fdo#102514 https://bugs.freedesktop.org/show_bug.cgi?id=102514
fdo#102777 https://bugs.freedesktop.org/show_bug.cgi?id=102777

fi-bdw-5557u total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  
time:437s
fi-bdw-gvtdvmtotal:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:475s
fi-blb-e6850 total:289  pass:224  dwarn:1   dfail:0   fail:0   skip:64  
time:419s
fi-bsw-n3050 total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  
time:517s
fi-bwr-2160  total:289  pass:184  dwarn:0   dfail:0   fail:0   skip:105 
time:277s
fi-bxt-j4205 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:500s
fi-byt-j1900 total:289  pass:254  dwarn:1   dfail:0   fail:0   skip:34  
time:494s
fi-cfl-s total:289  pass:223  dwarn:34  dfail:0   fail:0   skip:32  
time:541s
fi-cnl-y total:289  pass:259  dwarn:0   dfail:0   fail:3   skip:27  
time:638s
fi-elk-e7500 total:289  pass:230  dwarn:0   dfail:0   fail:0   skip:59  
time:419s
fi-glk-1 total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  
time:565s
fi-hsw-4770  total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:419s
fi-hsw-4770r total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  
time:403s
fi-ilk-650   total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  
time:433s
fi-ivb-3520m total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:498s
fi-ivb-3770  total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  
time:464s
fi-kbl-7500u total:289  pass:263  dwarn:1   dfail:0   fail:1   skip:24  
time:472s
fi-kbl-7560u total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  
time:572s
fi-kbl-r total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  
time:587s
fi-pnv-d510  total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  
time:543s
fi-skl-6260u total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:447s
fi-skl-6700k total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  
time:758s
fi-skl-6770hqtotal:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  
time:500s
fi-skl-gvtdvmtotal:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  
time:476s
fi-snb-2520m total:289  pass:251  dwarn:0   dfail:0   fail:0   skip:38  
time:568s
fi-snb-2600  total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  
time:413s

7f93222785e4887c083c85b76fcbb391bb1991d9 drm-tip: 2017y-09m-27d-20h-05m-25s UTC 
integration manifest
75da1d53cf05 drm/i915: Also discard second CRC on gen8+ platforms.

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5838/
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[Intel-gfx] [PATCH i-g-t] Fix compilation on some distros

[James Ausmus]

Some distros (such as Gentoo) are removing the include of
sys/sysmacros.h from sys/types.h. Explicitly include sysmacros.h in
files where we use the minor() and major() functions.

Signed-off-by: James Ausmus 
---
 lib/igt_debugfs.c | 1 +
 lib/igt_sysfs.c   | 1 +
 tools/aubdump.c   | 1 +
 3 files changed, 3 insertions(+)

diff --git a/lib/igt_debugfs.c b/lib/igt_debugfs.c
index 1e8c8cc3cd44..60b29e3a025a 100644
--- a/lib/igt_debugfs.c
+++ b/lib/igt_debugfs.c
@@ -25,6 +25,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
diff --git a/lib/igt_sysfs.c b/lib/igt_sysfs.c
index 817678bc28ed..f4e306003b01 100644
--- a/lib/igt_sysfs.c
+++ b/lib/igt_sysfs.c
@@ -24,6 +24,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
diff --git a/tools/aubdump.c b/tools/aubdump.c
index 78d183f49adc..ee4d99b06ed1 100644
--- a/tools/aubdump.c
+++ b/tools/aubdump.c
@@ -30,6 +30,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
-- 
2.14.1

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[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v4,1/6] tests/kms_ccs: Test pipes other than pipe A

[Patchwork]

== Series Details ==

Series: series starting with [v4,1/6] tests/kms_ccs: Test pipes other than pipe 
A
URL   : https://patchwork.freedesktop.org/series/30991/
State : failure

== Summary ==

Test kms_flip:
Subgroup blt-flip-vs-panning:
skip   -> PASS   (shard-hsw)
Subgroup bo-too-big:
skip   -> PASS   (shard-hsw)
Subgroup rcs-wf_vblank-vs-modeset-interruptible:
skip   -> PASS   (shard-hsw)
Subgroup 2x-flip-vs-absolute-wf_vblank:
pass   -> SKIP   (shard-hsw)
Subgroup blt-wf_vblank-vs-dpms-interruptible:
skip   -> PASS   (shard-hsw)
Subgroup flip-vs-dpms-interruptible:
skip   -> PASS   (shard-hsw)
Subgroup 2x-flip-vs-bad-tiling-interruptible:
pass   -> SKIP   (shard-hsw)
Subgroup vblank-vs-suspend:
skip   -> PASS   (shard-hsw)
Subgroup 2x-blt-flip-vs-panning:
pass   -> SKIP   (shard-hsw)
Subgroup 2x-wf_vblank-ts-check-interruptible:
pass   -> SKIP   (shard-hsw)
Subgroup flip-vs-expired-vblank:
skip   -> PASS   (shard-hsw) fdo#102367
Subgroup flip-vs-expired-vblank-interruptible:
skip   -> PASS   (shard-hsw) fdo#102887
Subgroup 2x-flip-vs-expired-vblank:
pass   -> SKIP   (shard-hsw)
Subgroup 2x-render-flip-vs-panning:
pass   -> SKIP   (shard-hsw)
Subgroup 2x-flip-vs-bad-tiling:
pass   -> SKIP   (shard-hsw)
Subgroup blocking-absolute-wf_vblank:
skip   -> PASS   (shard-hsw)
Subgroup vblank-vs-modeset-rpm-interruptible:
skip   -> PASS   (shard-hsw)
Subgroup 2x-absolute-wf_vblank-interruptible:
pass   -> SKIP   (shard-hsw)
Subgroup dpms-off-confusion-interruptible:
skip   -> PASS   (shard-hsw)
Subgroup vblank-vs-hang-interruptible:
skip   -> PASS   (shard-hsw)
Subgroup vblank-vs-suspend-interruptible:
skip   -> PASS   (shard-hsw)
Subgroup flip-vs-fences-interruptible:
skip   -> PASS   (shard-hsw) fdo#102946
Subgroup 2x-blocking-wf_vblank:
pass   -> SKIP   (shard-hsw)
Subgroup 2x-render-flip-vs-panning-interruptible:
pass   -> SKIP   (shard-hsw)
Subgroup 2x-flip-vs-modeset-vs-hang-interruptible:
pass   -> SKIP   (shard-hsw)
Subgroup 2x-blt-wf_vblank-vs-modeset:
pass   -> SKIP   (shard-hsw)
Subgroup 2x-vblank-vs-suspend-interruptible:
pass   -> SKIP   (shard-hsw)
Subgroup flip-vs-blocking-wf-vblank:
skip   -> PASS   (shard-hsw)
Subgroup 2x-plain-flip-fb-recreate:
pass   -> SKIP   (shard-hsw)
Subgroup flip-vs-absolute-wf_vblank:
skip   -> PASS   (shard-hsw) fdo#100368 +1
Subgroup 2x-plain-flip-ts-check:
pass   -> SKIP   (shard-hsw)
Subgroup 2x-absolute-wf_vblank:
pass   -> SKIP   (shard-hsw)
Subgroup 2x-wf_vblank-ts-check:
pass   -> SKIP   (shard-hsw)
Subgroup 2x-wf_vblank-vs-dpms-interruptible:
pass   -> SKIP   (shard-hsw)
Subgroup 2x-blt-flip-vs-panning-interruptible:
pass   -> SKIP   (shard-hsw)
Subgroup 2x-wf_vblank:
pass   -> SKIP   (shard-hsw)
Subgroup 2x-flip-vs-panning:
pass   -> SKIP   (shard-hsw)
Subgroup flip-vs-rmfb:
skip   -> PASS   (shard-hsw)
Subgroup vblank-vs-dpms-suspend:
skip   -> PASS   (shard-hsw)
Subgroup 2x-plain-flip:
pass   -> SKIP   (shard-hsw)
Subgroup 2x-blt-wf_vblank-vs-modeset-interruptible:
pass   -> SKIP   (shard-hsw)
Subgroup dpms-off-confusion:
skip   -> PASS   (shard-hsw) fdo#102614 +1
Subgroup 2x-blocking-absolute-wf_vblank:
pass   -> SKIP   (shard-hsw)
Subgroup 2x-flip-vs-fences:
pass   -> SKIP   (shard-hsw)
Subgroup 2x-rcs-wf_vblank-vs-dpms:
pass   -> SKIP   (shard-hsw)
Subgroup nonexisting-fb:
skip   -> PASS   (shard-hsw)
Subgroup 2x-flip-vs-rmfb-interruptible:
pass   -> SKIP   (shard-hsw)
Subgroup plain-flip-ts-check-interruptible:
skip   -> PASS   (shard-hsw) 

[Intel-gfx] [PATCH] drm/dp: Do not prune the last mode on the connector

[Manasi Navare]

Currently the drm_mode_prune_invalid() function will
prune all the modes if it finds that the mode-status
is not MODE_OK. But if it ends up pruning all modes
then there are no modes left for that connector which will
eventually result into a black screen as userspace sees no
modes from the kernel. This can happen pretty quickly in case of
eDP panel that has only mode that might get pruned.
This patch fixes this problem by checking if the mode being pruned
is the last mode on that connector and if so doesnt prune it.

Cc: dri-de...@lists.freedesktop.org
Cc: Keith Packard 
Cc: Jani Nikula 
Cc: Ville Syrjala 
Cc: Daniel Vetter 
Signed-off-by: Manasi Navare 
---
 drivers/gpu/drm/drm_modes.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c
index 4a3f68a..a9369eb 100644
--- a/drivers/gpu/drm/drm_modes.c
+++ b/drivers/gpu/drm/drm_modes.c
@@ -1185,7 +1185,8 @@ void drm_mode_prune_invalid(struct drm_device *dev,
struct drm_display_mode *mode, *t;
 
list_for_each_entry_safe(mode, t, mode_list, head) {
-   if (mode->status != MODE_OK) {
+   if (mode->status != MODE_OK &&
+   !(list_is_last(>head, mode_list))) {
list_del(>head);
if (verbose) {
drm_mode_debug_printmodeline(mode);
-- 
2.1.4

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