Re: [PATCH v3 1/3] dt-bindings: iommu: Add binding for MediaTek MT8167 IOMMU
On Sun, 2020-09-06 at 17:19 +0200, Fabien Parent wrote: > This commit adds IOMMU binding documentation and larb port definitions > for the MT8167 SoC. > > Signed-off-by: Fabien Parent > Acked-by: Rob Herring > --- > > V3: Added mt8167-larb-port.h file for iommu port definitions > V2: no change > > --- > .../bindings/iommu/mediatek,iommu.txt | 1 + > include/dt-bindings/memory/mt8167-larb-port.h | 49 +++ > 2 files changed, 50 insertions(+) > create mode 100644 include/dt-bindings/memory/mt8167-larb-port.h > > diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > index c1ccd8582eb2..f7a348f48e0d 100644 > --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > @@ -61,6 +61,7 @@ Required properties: > "mediatek,mt6779-m4u" for mt6779 which uses generation two m4u HW. > "mediatek,mt7623-m4u", "mediatek,mt2701-m4u" for mt7623 which uses >generation one m4u HW. > + "mediatek,mt8167-m4u" for mt8167 which uses generation two m4u HW. > "mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW. > "mediatek,mt8183-m4u" for mt8183 which uses generation two m4u HW. > - reg : m4u register base and size. Please also add this line in the iommu-cells property: dt-bindings/memory/mt8167-larb-port.h for mt8167. > diff --git a/include/dt-bindings/memory/mt8167-larb-port.h > b/include/dt-bindings/memory/mt8167-larb-port.h > new file mode 100644 > index ..4dd44d1037a7 > --- /dev/null > +++ b/include/dt-bindings/memory/mt8167-larb-port.h > @@ -0,0 +1,49 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Copyright (c) 2020 BayLibre, SAS > + * Author: Fabien Parent If I'm not wrong, the first version was created by: Honghui Zhang the original author should be kept. > + */ > +#ifndef __DTS_IOMMU_PORT_MT8167_H > +#define __DTS_IOMMU_PORT_MT8167_H > + > +#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port)) > + > +#define M4U_LARB0_ID 0 > +#define M4U_LARB1_ID 1 > +#define M4U_LARB2_ID 2 > + > +/* larb0 */ > +#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0) > +#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 1) > +#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 2) > +#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 3) > +#define M4U_PORT_MDP_RDMAMTK_M4U_ID(M4U_LARB0_ID, 4) > +#define M4U_PORT_MDP_WDMAMTK_M4U_ID(M4U_LARB0_ID, 5) > +#define M4U_PORT_MDP_WROTMTK_M4U_ID(M4U_LARB0_ID, 6) > +#define M4U_PORT_DISP_FAKE MTK_M4U_ID(M4U_LARB0_ID, 7) > + > +/* IMG larb1*/ > +#define M4U_PORT_CAM_IMGOMTK_M4U_ID(M4U_LARB1_ID, 0) > +#define M4U_PORT_CAM_IMG2O MTK_M4U_ID(M4U_LARB1_ID, 1) > +#define M4U_PORT_CAM_LSCIMTK_M4U_ID(M4U_LARB1_ID, 2) > +#define M4U_PORT_CAM_ESFKO MTK_M4U_ID(M4U_LARB1_ID, 3) > +#define M4U_PORT_CAM_AAO MTK_M4U_ID(M4U_LARB1_ID, 4) > +#define M4U_PORT_VENC_RECMTK_M4U_ID(M4U_LARB1_ID, 5) > +#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB1_ID, 6) > +#define M4U_PORT_VENC_RD_COMVMTK_M4U_ID(M4U_LARB1_ID, 7) > +#define M4U_PORT_CAM_IMGIMTK_M4U_ID(M4U_LARB1_ID, 8) > +#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB1_ID, 9) > +#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB1_ID, 10) > +#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB1_ID, 11) > +#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB1_ID, 12) > + > +/* VDEC larb2*/ > +#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB2_ID, 0) > +#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB2_ID, 1) > +#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB2_ID, 2) > +#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB2_ID, 3) > +#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB2_ID, 4) > +#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB2_ID, 5) > +#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB2_ID, 6) > + > +#endif ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
Re: [PATCH v3 3/3] iommu/mediatek: add support for MT8167
On Sun, 2020-09-06 at 17:19 +0200, Fabien Parent wrote:
> Add support for the IOMMU on MT8167
>
> Signed-off-by: Fabien Parent
> ---
>
> V3:
> * use LEGACY_IVRP_PADDR flag instead of using a platform data member
> V2:
> * removed if based on m4u_plat, and using instead the new
> has_legacy_ivrp_paddr member that was introduced in patch 2.
>
> ---
> drivers/iommu/mtk_iommu.c | 8
> drivers/iommu/mtk_iommu.h | 1 +
> 2 files changed, 9 insertions(+)
>
> diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> index b1f85a7e9346..6079f6a23c74 100644
> --- a/drivers/iommu/mtk_iommu.c
> +++ b/drivers/iommu/mtk_iommu.c
> @@ -817,6 +817,13 @@ static const struct mtk_iommu_plat_data mt6779_data = {
> .larbid_remap = {{0}, {1}, {2}, {3}, {5}, {7, 8}, {10}, {9}},
> };
>
> +static const struct mtk_iommu_plat_data mt8167_data = {
> + .m4u_plat = M4U_MT8167,
> + .flags= HAS_4GB_MODE | RESET_AXI | HAS_LEGACY_IVRP_PADDR,
The 4GB mode flow was improved at[1] which has just been applied.
If you add 4gb_mode flag but don't have "mt8167-infracfg", the probe may
be failed.
[1]
https://lore.kernel.org/linux-iommu/20200904112117.gc16...@8bytes.org/T/#m613e9926735d07ad004fddbbcedaa50b5afacca1
> + .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
> + .larbid_remap = {{0}, {1}, {2}}, /* Linear mapping. */
> +};
> +
> static const struct mtk_iommu_plat_data mt8173_data = {
> .m4u_plat = M4U_MT8173,
> .flags= HAS_4GB_MODE | HAS_BCLK | RESET_AXI |
> @@ -835,6 +842,7 @@ static const struct mtk_iommu_plat_data mt8183_data = {
> static const struct of_device_id mtk_iommu_of_ids[] = {
> { .compatible = "mediatek,mt2712-m4u", .data = _data},
> { .compatible = "mediatek,mt6779-m4u", .data = _data},
> + { .compatible = "mediatek,mt8167-m4u", .data = _data},
> { .compatible = "mediatek,mt8173-m4u", .data = _data},
> { .compatible = "mediatek,mt8183-m4u", .data = _data},
> {}
> diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
> index 122925dbe547..df32b3e3408b 100644
> --- a/drivers/iommu/mtk_iommu.h
> +++ b/drivers/iommu/mtk_iommu.h
> @@ -39,6 +39,7 @@ enum mtk_iommu_plat {
> M4U_MT2701,
> M4U_MT2712,
> M4U_MT6779,
> + M4U_MT8167,
> M4U_MT8173,
> M4U_MT8183,
> };
___
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
Re: [PATCH v3 2/3] iommu/mediatek: add flag for legacy ivrp paddr
On Sun, 2020-09-06 at 17:19 +0200, Fabien Parent wrote:
> Add a new flag in order to select which IVRP_PADDR format is used
> by an SoC.
>
> Signed-off-by: Fabien Parent
Reviewed-by: Yong Wu
> ---
>
> v3: set LEGACY_IVRP_PADDR as a flag instead of platform data
> v2: new patch
>
> ---
> drivers/iommu/mtk_iommu.c | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> index 785b228d39a6..b1f85a7e9346 100644
> --- a/drivers/iommu/mtk_iommu.c
> +++ b/drivers/iommu/mtk_iommu.c
> @@ -116,6 +116,7 @@
> #define OUT_ORDER_WR_EN BIT(4)
> #define HAS_SUB_COMM BIT(5)
> #define WR_THROT_EN BIT(6)
> +#define HAS_LEGACY_IVRP_PADDRBIT(7)
>
> #define MTK_IOMMU_HAS_FLAG(pdata, _x) \
> pdata)->flags) & (_x)) == (_x))
> @@ -582,7 +583,7 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data
> *data)
> F_INT_PRETETCH_TRANSATION_FIFO_FAULT;
> writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL);
>
> - if (data->plat_data->m4u_plat == M4U_MT8173)
> + if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_LEGACY_IVRP_PADDR))
> regval = (data->protect_base >> 1) | (data->enable_4GB << 31);
> else
> regval = lower_32_bits(data->protect_base) |
> @@ -818,7 +819,8 @@ static const struct mtk_iommu_plat_data mt6779_data = {
>
> static const struct mtk_iommu_plat_data mt8173_data = {
> .m4u_plat = M4U_MT8173,
> - .flags= HAS_4GB_MODE | HAS_BCLK | RESET_AXI,
> + .flags= HAS_4GB_MODE | HAS_BCLK | RESET_AXI |
> + HAS_LEGACY_IVRP_PADDR,
> .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
> .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */
> };
___
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
Re: [git pull] IOMMU Fixes for Linux v5.9-rc3
The pull request you sent on Sun, 6 Sep 2020 17:01:20 +0200: > git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git > tags/iommu-fixes-v5.9-rc3 has been merged into torvalds/linux.git: https://git.kernel.org/torvalds/c/2ccdd9f8b2ce7290aad6f0a34200ad394e61f940 Thank you! -- Deet-doot-dot, I am a bot. https://korg.docs.kernel.org/prtracker.html ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
Re: [PATCH v3 3/3] iommu/mediatek: add support for MT8167
On Sun, Sep 6, 2020 at 5:19 PM Fabien Parent wrote:
>
> Add support for the IOMMU on MT8167
>
> Signed-off-by: Fabien Parent
> ---
>
> V3:
> * use LEGACY_IVRP_PADDR flag instead of using a platform data member
Forgot to mention a change here: .larbid_remap has been fixed to only
contain the number of larb present on MT8167
> V2:
> * removed if based on m4u_plat, and using instead the new
> has_legacy_ivrp_paddr member that was introduced in patch 2.
>
> ---
> drivers/iommu/mtk_iommu.c | 8
> drivers/iommu/mtk_iommu.h | 1 +
> 2 files changed, 9 insertions(+)
>
> diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> index b1f85a7e9346..6079f6a23c74 100644
> --- a/drivers/iommu/mtk_iommu.c
> +++ b/drivers/iommu/mtk_iommu.c
> @@ -817,6 +817,13 @@ static const struct mtk_iommu_plat_data mt6779_data = {
> .larbid_remap = {{0}, {1}, {2}, {3}, {5}, {7, 8}, {10}, {9}},
> };
>
> +static const struct mtk_iommu_plat_data mt8167_data = {
> + .m4u_plat = M4U_MT8167,
> + .flags= HAS_4GB_MODE | RESET_AXI | HAS_LEGACY_IVRP_PADDR,
> + .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
> + .larbid_remap = {{0}, {1}, {2}}, /* Linear mapping. */
> +};
> +
> static const struct mtk_iommu_plat_data mt8173_data = {
> .m4u_plat = M4U_MT8173,
> .flags= HAS_4GB_MODE | HAS_BCLK | RESET_AXI |
> @@ -835,6 +842,7 @@ static const struct mtk_iommu_plat_data mt8183_data = {
> static const struct of_device_id mtk_iommu_of_ids[] = {
> { .compatible = "mediatek,mt2712-m4u", .data = _data},
> { .compatible = "mediatek,mt6779-m4u", .data = _data},
> + { .compatible = "mediatek,mt8167-m4u", .data = _data},
> { .compatible = "mediatek,mt8173-m4u", .data = _data},
> { .compatible = "mediatek,mt8183-m4u", .data = _data},
> {}
> diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
> index 122925dbe547..df32b3e3408b 100644
> --- a/drivers/iommu/mtk_iommu.h
> +++ b/drivers/iommu/mtk_iommu.h
> @@ -39,6 +39,7 @@ enum mtk_iommu_plat {
> M4U_MT2701,
> M4U_MT2712,
> M4U_MT6779,
> + M4U_MT8167,
> M4U_MT8173,
> M4U_MT8183,
> };
> --
> 2.28.0
>
___
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
RE: [PATCH 0/2] iommu/amd: Fix IOMMUv2 devices when SME is active
[AMD Official Use Only - Internal Distribution Only]
> -Original Message-
> From: Joerg Roedel
> Sent: Friday, September 4, 2020 6:06 AM
> To: Deucher, Alexander
> Cc: jroe...@suse.de; Kuehling, Felix ;
> iommu@lists.linux-foundation.org; Huang, Ray ;
> Koenig, Christian ; Lendacky, Thomas
> ; Suthikulpanit, Suravee
> ; linux-ker...@vger.kernel.org
> Subject: Re: [PATCH 0/2] iommu/amd: Fix IOMMUv2 devices when SME is
> active
>
> On Fri, Aug 28, 2020 at 03:47:07PM +, Deucher, Alexander wrote:
> > Ah, right, So CZ and ST are not an issue. Raven is paired with Zen based
> CPUs.
>
> Okay, so for the Raven case, can you add code to the amdgpu driver which
> makes it fail to initialize on Raven when SME is active? There is a global
> checking function for that, so that shouldn't be hard to do.
>
Sure. How about the attached patch?
Alex
From f479b9da353c2547c26ebac8930a5dcd9a134eb7 Mon Sep 17 00:00:00 2001
From: Alex Deucher
Date: Sun, 6 Sep 2020 12:05:12 -0400
Subject: [PATCH] drm/amdgpu: Fail to load on RAVEN if SME is active
Due to hardware bugs, scatter/gather display on raven requires
a 1:1 IOMMU mapping, however, SME (System Memory Encryption)
requires an indirect IOMMU mapping because the encryption bit
is beyond the DMA mask of the chip. As such, the two are
incompatible.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 12e16445df7c..d87d37c25329 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -1102,6 +1102,16 @@ static int amdgpu_pci_probe(struct pci_dev *pdev,
return -ENODEV;
}
+ /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping,
+ * however, SME requires an indirect IOMMU mapping because the encryption
+ * bit is beyond the DMA mask of the chip.
+ */
+ if (mem_encrypt_active() && ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) {
+ dev_info(>dev,
+ "SME is not compatible with RAVEN\n");
+ return -ENOTSUPP;
+ }
+
#ifdef CONFIG_DRM_AMDGPU_SI
if (!amdgpu_si_support) {
switch (flags & AMD_ASIC_MASK) {
--
2.25.4
___
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
[PATCH v3 1/3] dt-bindings: iommu: Add binding for MediaTek MT8167 IOMMU
This commit adds IOMMU binding documentation and larb port definitions for the MT8167 SoC. Signed-off-by: Fabien Parent Acked-by: Rob Herring --- V3: Added mt8167-larb-port.h file for iommu port definitions V2: no change --- .../bindings/iommu/mediatek,iommu.txt | 1 + include/dt-bindings/memory/mt8167-larb-port.h | 49 +++ 2 files changed, 50 insertions(+) create mode 100644 include/dt-bindings/memory/mt8167-larb-port.h diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt index c1ccd8582eb2..f7a348f48e0d 100644 --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt @@ -61,6 +61,7 @@ Required properties: "mediatek,mt6779-m4u" for mt6779 which uses generation two m4u HW. "mediatek,mt7623-m4u", "mediatek,mt2701-m4u" for mt7623 which uses generation one m4u HW. + "mediatek,mt8167-m4u" for mt8167 which uses generation two m4u HW. "mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW. "mediatek,mt8183-m4u" for mt8183 which uses generation two m4u HW. - reg : m4u register base and size. diff --git a/include/dt-bindings/memory/mt8167-larb-port.h b/include/dt-bindings/memory/mt8167-larb-port.h new file mode 100644 index ..4dd44d1037a7 --- /dev/null +++ b/include/dt-bindings/memory/mt8167-larb-port.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 BayLibre, SAS + * Author: Fabien Parent + */ +#ifndef __DTS_IOMMU_PORT_MT8167_H +#define __DTS_IOMMU_PORT_MT8167_H + +#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port)) + +#define M4U_LARB0_ID 0 +#define M4U_LARB1_ID 1 +#define M4U_LARB2_ID 2 + +/* larb0 */ +#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0) +#define M4U_PORT_DISP_RDMA0MTK_M4U_ID(M4U_LARB0_ID, 1) +#define M4U_PORT_DISP_WDMA0MTK_M4U_ID(M4U_LARB0_ID, 2) +#define M4U_PORT_DISP_RDMA1MTK_M4U_ID(M4U_LARB0_ID, 3) +#define M4U_PORT_MDP_RDMA MTK_M4U_ID(M4U_LARB0_ID, 4) +#define M4U_PORT_MDP_WDMA MTK_M4U_ID(M4U_LARB0_ID, 5) +#define M4U_PORT_MDP_WROT MTK_M4U_ID(M4U_LARB0_ID, 6) +#define M4U_PORT_DISP_FAKE MTK_M4U_ID(M4U_LARB0_ID, 7) + +/* IMG larb1*/ +#define M4U_PORT_CAM_IMGO MTK_M4U_ID(M4U_LARB1_ID, 0) +#define M4U_PORT_CAM_IMG2O MTK_M4U_ID(M4U_LARB1_ID, 1) +#define M4U_PORT_CAM_LSCI MTK_M4U_ID(M4U_LARB1_ID, 2) +#define M4U_PORT_CAM_ESFKO MTK_M4U_ID(M4U_LARB1_ID, 3) +#define M4U_PORT_CAM_AAO MTK_M4U_ID(M4U_LARB1_ID, 4) +#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB1_ID, 5) +#define M4U_PORT_VENC_BSDMAMTK_M4U_ID(M4U_LARB1_ID, 6) +#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB1_ID, 7) +#define M4U_PORT_CAM_IMGI MTK_M4U_ID(M4U_LARB1_ID, 8) +#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB1_ID, 9) +#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB1_ID, 10) +#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB1_ID, 11) +#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB1_ID, 12) + +/* VDEC larb2*/ +#define M4U_PORT_HW_VDEC_MC_EXTMTK_M4U_ID(M4U_LARB2_ID, 0) +#define M4U_PORT_HW_VDEC_PP_EXTMTK_M4U_ID(M4U_LARB2_ID, 1) +#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB2_ID, 2) +#define M4U_PORT_HW_VDEC_AVC_MV_EXTMTK_M4U_ID(M4U_LARB2_ID, 3) +#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB2_ID, 4) +#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB2_ID, 5) +#define M4U_PORT_HW_VDEC_PPWRAP_EXTMTK_M4U_ID(M4U_LARB2_ID, 6) + +#endif -- 2.28.0 ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
[PATCH v3 2/3] iommu/mediatek: add flag for legacy ivrp paddr
Add a new flag in order to select which IVRP_PADDR format is used
by an SoC.
Signed-off-by: Fabien Parent
---
v3: set LEGACY_IVRP_PADDR as a flag instead of platform data
v2: new patch
---
drivers/iommu/mtk_iommu.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 785b228d39a6..b1f85a7e9346 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -116,6 +116,7 @@
#define OUT_ORDER_WR_ENBIT(4)
#define HAS_SUB_COMM BIT(5)
#define WR_THROT_ENBIT(6)
+#define HAS_LEGACY_IVRP_PADDR BIT(7)
#define MTK_IOMMU_HAS_FLAG(pdata, _x) \
pdata)->flags) & (_x)) == (_x))
@@ -582,7 +583,7 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data
*data)
F_INT_PRETETCH_TRANSATION_FIFO_FAULT;
writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL);
- if (data->plat_data->m4u_plat == M4U_MT8173)
+ if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_LEGACY_IVRP_PADDR))
regval = (data->protect_base >> 1) | (data->enable_4GB << 31);
else
regval = lower_32_bits(data->protect_base) |
@@ -818,7 +819,8 @@ static const struct mtk_iommu_plat_data mt6779_data = {
static const struct mtk_iommu_plat_data mt8173_data = {
.m4u_plat = M4U_MT8173,
- .flags= HAS_4GB_MODE | HAS_BCLK | RESET_AXI,
+ .flags= HAS_4GB_MODE | HAS_BCLK | RESET_AXI |
+ HAS_LEGACY_IVRP_PADDR,
.inv_sel_reg = REG_MMU_INV_SEL_GEN1,
.larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */
};
--
2.28.0
___
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
[PATCH v3 3/3] iommu/mediatek: add support for MT8167
Add support for the IOMMU on MT8167
Signed-off-by: Fabien Parent
---
V3:
* use LEGACY_IVRP_PADDR flag instead of using a platform data member
V2:
* removed if based on m4u_plat, and using instead the new
has_legacy_ivrp_paddr member that was introduced in patch 2.
---
drivers/iommu/mtk_iommu.c | 8
drivers/iommu/mtk_iommu.h | 1 +
2 files changed, 9 insertions(+)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index b1f85a7e9346..6079f6a23c74 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -817,6 +817,13 @@ static const struct mtk_iommu_plat_data mt6779_data = {
.larbid_remap = {{0}, {1}, {2}, {3}, {5}, {7, 8}, {10}, {9}},
};
+static const struct mtk_iommu_plat_data mt8167_data = {
+ .m4u_plat = M4U_MT8167,
+ .flags= HAS_4GB_MODE | RESET_AXI | HAS_LEGACY_IVRP_PADDR,
+ .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
+ .larbid_remap = {{0}, {1}, {2}}, /* Linear mapping. */
+};
+
static const struct mtk_iommu_plat_data mt8173_data = {
.m4u_plat = M4U_MT8173,
.flags= HAS_4GB_MODE | HAS_BCLK | RESET_AXI |
@@ -835,6 +842,7 @@ static const struct mtk_iommu_plat_data mt8183_data = {
static const struct of_device_id mtk_iommu_of_ids[] = {
{ .compatible = "mediatek,mt2712-m4u", .data = _data},
{ .compatible = "mediatek,mt6779-m4u", .data = _data},
+ { .compatible = "mediatek,mt8167-m4u", .data = _data},
{ .compatible = "mediatek,mt8173-m4u", .data = _data},
{ .compatible = "mediatek,mt8183-m4u", .data = _data},
{}
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index 122925dbe547..df32b3e3408b 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -39,6 +39,7 @@ enum mtk_iommu_plat {
M4U_MT2701,
M4U_MT2712,
M4U_MT6779,
+ M4U_MT8167,
M4U_MT8173,
M4U_MT8183,
};
--
2.28.0
___
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
[git pull] IOMMU Fixes for Linux v5.9-rc3
Hi Linus, The following changes since commit f75aef392f869018f78cfedf3c320a6b3fcfda6b: Linux 5.9-rc3 (2020-08-30 16:01:54 -0700) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git tags/iommu-fixes-v5.9-rc3 for you to fetch changes up to 29aaebbca4abc4cceb38738483051abefafb6950: iommu/vt-d: Handle 36bit addressing for x86-32 (2020-09-04 12:14:28 +0200) IOMMU Fixes for Linux v5.9-rc3 Including: - Three Intel VT-d fixes to fix address handling on 32bit, fix a NULL pointer dereference bug and serialize a hardware register access as required by the VT-d spec. - Two patches for AMD IOMMU to force AMD GPUs into translation mode when memory encryption is active and disallow using IOMMUv2 functionality. This makes the AMDGPU driver working when memory encryption is active. - Two more fixes for AMD IOMMU to fix updating the Interrupt Remapping Table Entries. - MAINTAINERS file update for the Qualcom IOMMU driver. Chris Wilson (1): iommu/vt-d: Handle 36bit addressing for x86-32 Joerg Roedel (2): iommu/amd: Do not force direct mapping when SME is active iommu/amd: Do not use IOMMUv2 functionality when SME is active Lu Baolu (2): iommu/vt-d: Serialize IOMMU GCMD register modifications iommu/vt-d: Fix NULL pointer dereference in dev_iommu_priv_set() Lukas Bulwahn (1): MAINTAINERS: Update QUALCOMM IOMMU after Arm SMMU drivers move Suravee Suthikulpanit (2): iommu/amd: Restore IRTE.RemapEn bit after programming IRTE iommu/amd: Use cmpxchg_double() when updating 128-bit IRTE MAINTAINERS | 2 +- drivers/iommu/amd/Kconfig | 2 +- drivers/iommu/amd/init.c| 21 ++- drivers/iommu/amd/iommu.c | 26 ++-- drivers/iommu/amd/iommu_v2.c| 7 +++ drivers/iommu/intel/iommu.c | 114 drivers/iommu/intel/irq_remapping.c | 10 +++- 7 files changed, 119 insertions(+), 63 deletions(-) Please pull. Thanks, Joerg signature.asc Description: Digital signature ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
