subject:"\[kbuild\] drivers\/mtd\/nand\/raw\/renesas\-nand\-controller.c\:900 rnandc_setup_interface\(\) warn\: passing a valid pointer to 'PTR

[kbuild] drivers/mtd/nand/raw/renesas-nand-controller.c:900 rnandc_setup_interface() warn: passing a valid pointer to 'PTR_ERR'

2022-07-25 Thread kernel test robot

CC: kbuild-...@lists.01.org
BCC: l...@intel.com
CC: linux-ker...@vger.kernel.org
TO: Miquel Raynal 

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 
master
head:   e0dccc3b76fb35bb257b4118367a883073d7390e
commit: d8701fe890ecbab239086e7053d62d0f08587d7c mtd: rawnand: renesas: Add new 
NAND controller driver
date:   7 months ago
:: branch date: 14 hours ago
:: commit date: 7 months ago
config: parisc-randconfig-m031-20220724 
(https://download.01.org/0day-ci/archive/20220725/202207251805.7mlblni5-...@intel.com/config)
compiler: hppa-linux-gcc (GCC) 12.1.0

If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot 
Reported-by: Dan Carpenter 

smatch warnings:
drivers/mtd/nand/raw/renesas-nand-controller.c:900 rnandc_setup_interface() 
warn: passing a valid pointer to 'PTR_ERR'

vim +/PTR_ERR +900 drivers/mtd/nand/raw/renesas-nand-controller.c

d8701fe890ecba Miquel Raynal 2021-12-17  888  
d8701fe890ecba Miquel Raynal 2021-12-17  889  static int 
rnandc_setup_interface(struct nand_chip *chip, int chipnr,
d8701fe890ecba Miquel Raynal 2021-12-17  890  const 
struct nand_interface_config *conf)
d8701fe890ecba Miquel Raynal 2021-12-17  891  {
d8701fe890ecba Miquel Raynal 2021-12-17  892struct rnand_chip *rnand = 
to_rnand(chip);
d8701fe890ecba Miquel Raynal 2021-12-17  893struct rnandc *rnandc = 
to_rnandc(chip->controller);
d8701fe890ecba Miquel Raynal 2021-12-17  894unsigned int period_ns = 
10 / clk_get_rate(rnandc->eclk);
d8701fe890ecba Miquel Raynal 2021-12-17  895const struct nand_sdr_timings 
*sdr;
d8701fe890ecba Miquel Raynal 2021-12-17  896unsigned int cyc, cle, ale, 
bef_dly, ca_to_data;
d8701fe890ecba Miquel Raynal 2021-12-17  897  
d8701fe890ecba Miquel Raynal 2021-12-17  898sdr = 
nand_get_sdr_timings(conf);
d8701fe890ecba Miquel Raynal 2021-12-17  899if (IS_ERR(sdr))
d8701fe890ecba Miquel Raynal 2021-12-17 @900return PTR_ERR(sdr);
d8701fe890ecba Miquel Raynal 2021-12-17  901  
d8701fe890ecba Miquel Raynal 2021-12-17  902if (sdr->tRP_min != 
sdr->tWP_min || sdr->tREH_min != sdr->tWH_min) {
d8701fe890ecba Miquel Raynal 2021-12-17  903dev_err(rnandc->dev, 
"Read and write hold times must be identical\n");
d8701fe890ecba Miquel Raynal 2021-12-17  904return -EINVAL;
d8701fe890ecba Miquel Raynal 2021-12-17  905}
d8701fe890ecba Miquel Raynal 2021-12-17  906  
d8701fe890ecba Miquel Raynal 2021-12-17  907if (chipnr < 0)
d8701fe890ecba Miquel Raynal 2021-12-17  908return 0;
d8701fe890ecba Miquel Raynal 2021-12-17  909  
d8701fe890ecba Miquel Raynal 2021-12-17  910rnand->timings_asyn =
d8701fe890ecba Miquel Raynal 2021-12-17  911
TIMINGS_ASYN_TRWP(TO_CYCLES64(sdr->tRP_min, period_ns)) |
d8701fe890ecba Miquel Raynal 2021-12-17  912
TIMINGS_ASYN_TRWH(TO_CYCLES64(sdr->tREH_min, period_ns));
d8701fe890ecba Miquel Raynal 2021-12-17  913rnand->tim_seq0 =
d8701fe890ecba Miquel Raynal 2021-12-17  914
TIM_SEQ0_TCCS(TO_CYCLES64(sdr->tCCS_min, period_ns)) |
d8701fe890ecba Miquel Raynal 2021-12-17  915
TIM_SEQ0_TADL(TO_CYCLES64(sdr->tADL_min, period_ns)) |
d8701fe890ecba Miquel Raynal 2021-12-17  916
TIM_SEQ0_TRHW(TO_CYCLES64(sdr->tRHW_min, period_ns)) |
d8701fe890ecba Miquel Raynal 2021-12-17  917
TIM_SEQ0_TWHR(TO_CYCLES64(sdr->tWHR_min, period_ns));
d8701fe890ecba Miquel Raynal 2021-12-17  918rnand->tim_seq1 =
d8701fe890ecba Miquel Raynal 2021-12-17  919
TIM_SEQ1_TWB(TO_CYCLES64(sdr->tWB_max, period_ns)) |
d8701fe890ecba Miquel Raynal 2021-12-17  920
TIM_SEQ1_TRR(TO_CYCLES64(sdr->tRR_min, period_ns)) |
d8701fe890ecba Miquel Raynal 2021-12-17  921
TIM_SEQ1_TWW(TO_CYCLES64(sdr->tWW_min, period_ns));
d8701fe890ecba Miquel Raynal 2021-12-17  922  
d8701fe890ecba Miquel Raynal 2021-12-17  923cyc = sdr->tDS_min + 
sdr->tDH_min;
d8701fe890ecba Miquel Raynal 2021-12-17  924cle = sdr->tCLH_min + 
sdr->tCLS_min;
d8701fe890ecba Miquel Raynal 2021-12-17  925ale = sdr->tALH_min + 
sdr->tALS_min;
d8701fe890ecba Miquel Raynal 2021-12-17  926bef_dly = sdr->tWB_max - 
sdr->tDH_min;
d8701fe890ecba Miquel Raynal 2021-12-17  927ca_to_data = sdr->tWHR_min + 
sdr->tREA_max - sdr->tDH_min;
d8701fe890ecba Miquel Raynal 2021-12-17  928  
d8701fe890ecba Miquel Raynal 2021-12-17  929/*
d8701fe890ecba Miquel Raynal 2021-12-17  930 * D0 = CMD -> ADDR = tCLH + 
tCLS - 1 cycle
d8701fe890ecba Miquel Raynal 2021-12-17  931 * D1 = CMD -> CMD = tCLH + 
tCLS - 1 cycle
d8701fe890ecba Miquel Raynal 2021-12-17  932 * D2 = CMD -> DLY = tWB - tDH
d8701fe890ecba Miquel Raynal 2021-12-17  933 * D3 = CMD -> DATA = tWHR + 
tREA - tDH
d8701fe890ecba Miquel Raynal 2021-12-17  934 */
d8701fe890ecba Miquel Raynal 2021-12-17  935rnand->tim_gen_seq0 =
d8701fe890ecba Miquel Raynal 2021-12-17  936

[kbuild] drivers/mtd/nand/raw/renesas-nand-controller.c:900 rnandc_setup_interface() warn: passing a valid pointer to 'PTR_ERR'

2022-06-05 Thread kernel test robot

CC: kbuild-...@lists.01.org
BCC: l...@intel.com
CC: linux-ker...@vger.kernel.org
TO: Miquel Raynal 

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 
master
head:   d717180e7f9775d468f415c10a4a474640146001
commit: d8701fe890ecbab239086e7053d62d0f08587d7c mtd: rawnand: renesas: Add new 
NAND controller driver
date:   6 months ago
:: branch date: 7 hours ago
:: commit date: 6 months ago
config: microblaze-randconfig-m031-20220605 
(https://download.01.org/0day-ci/archive/20220606/202206060933.pohn51vu-...@intel.com/config)
compiler: microblaze-linux-gcc (GCC) 11.3.0

If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot 
Reported-by: Dan Carpenter 

smatch warnings:
drivers/mtd/nand/raw/renesas-nand-controller.c:900 rnandc_setup_interface() 
warn: passing a valid pointer to 'PTR_ERR'

vim +/PTR_ERR +900 drivers/mtd/nand/raw/renesas-nand-controller.c

d8701fe890ecba Miquel Raynal 2021-12-17  888  
d8701fe890ecba Miquel Raynal 2021-12-17  889  static int 
rnandc_setup_interface(struct nand_chip *chip, int chipnr,
d8701fe890ecba Miquel Raynal 2021-12-17  890  const 
struct nand_interface_config *conf)
d8701fe890ecba Miquel Raynal 2021-12-17  891  {
d8701fe890ecba Miquel Raynal 2021-12-17  892struct rnand_chip *rnand = 
to_rnand(chip);
d8701fe890ecba Miquel Raynal 2021-12-17  893struct rnandc *rnandc = 
to_rnandc(chip->controller);
d8701fe890ecba Miquel Raynal 2021-12-17  894unsigned int period_ns = 
10 / clk_get_rate(rnandc->eclk);
d8701fe890ecba Miquel Raynal 2021-12-17  895const struct nand_sdr_timings 
*sdr;
d8701fe890ecba Miquel Raynal 2021-12-17  896unsigned int cyc, cle, ale, 
bef_dly, ca_to_data;
d8701fe890ecba Miquel Raynal 2021-12-17  897  
d8701fe890ecba Miquel Raynal 2021-12-17  898sdr = 
nand_get_sdr_timings(conf);
d8701fe890ecba Miquel Raynal 2021-12-17  899if (IS_ERR(sdr))
d8701fe890ecba Miquel Raynal 2021-12-17 @900return PTR_ERR(sdr);
d8701fe890ecba Miquel Raynal 2021-12-17  901  
d8701fe890ecba Miquel Raynal 2021-12-17  902if (sdr->tRP_min != 
sdr->tWP_min || sdr->tREH_min != sdr->tWH_min) {
d8701fe890ecba Miquel Raynal 2021-12-17  903dev_err(rnandc->dev, 
"Read and write hold times must be identical\n");
d8701fe890ecba Miquel Raynal 2021-12-17  904return -EINVAL;
d8701fe890ecba Miquel Raynal 2021-12-17  905}
d8701fe890ecba Miquel Raynal 2021-12-17  906  
d8701fe890ecba Miquel Raynal 2021-12-17  907if (chipnr < 0)
d8701fe890ecba Miquel Raynal 2021-12-17  908return 0;
d8701fe890ecba Miquel Raynal 2021-12-17  909  
d8701fe890ecba Miquel Raynal 2021-12-17  910rnand->timings_asyn =
d8701fe890ecba Miquel Raynal 2021-12-17  911
TIMINGS_ASYN_TRWP(TO_CYCLES64(sdr->tRP_min, period_ns)) |
d8701fe890ecba Miquel Raynal 2021-12-17  912
TIMINGS_ASYN_TRWH(TO_CYCLES64(sdr->tREH_min, period_ns));
d8701fe890ecba Miquel Raynal 2021-12-17  913rnand->tim_seq0 =
d8701fe890ecba Miquel Raynal 2021-12-17  914
TIM_SEQ0_TCCS(TO_CYCLES64(sdr->tCCS_min, period_ns)) |
d8701fe890ecba Miquel Raynal 2021-12-17  915
TIM_SEQ0_TADL(TO_CYCLES64(sdr->tADL_min, period_ns)) |
d8701fe890ecba Miquel Raynal 2021-12-17  916
TIM_SEQ0_TRHW(TO_CYCLES64(sdr->tRHW_min, period_ns)) |
d8701fe890ecba Miquel Raynal 2021-12-17  917
TIM_SEQ0_TWHR(TO_CYCLES64(sdr->tWHR_min, period_ns));
d8701fe890ecba Miquel Raynal 2021-12-17  918rnand->tim_seq1 =
d8701fe890ecba Miquel Raynal 2021-12-17  919
TIM_SEQ1_TWB(TO_CYCLES64(sdr->tWB_max, period_ns)) |
d8701fe890ecba Miquel Raynal 2021-12-17  920
TIM_SEQ1_TRR(TO_CYCLES64(sdr->tRR_min, period_ns)) |
d8701fe890ecba Miquel Raynal 2021-12-17  921
TIM_SEQ1_TWW(TO_CYCLES64(sdr->tWW_min, period_ns));
d8701fe890ecba Miquel Raynal 2021-12-17  922  
d8701fe890ecba Miquel Raynal 2021-12-17  923cyc = sdr->tDS_min + 
sdr->tDH_min;
d8701fe890ecba Miquel Raynal 2021-12-17  924cle = sdr->tCLH_min + 
sdr->tCLS_min;
d8701fe890ecba Miquel Raynal 2021-12-17  925ale = sdr->tALH_min + 
sdr->tALS_min;
d8701fe890ecba Miquel Raynal 2021-12-17  926bef_dly = sdr->tWB_max - 
sdr->tDH_min;
d8701fe890ecba Miquel Raynal 2021-12-17  927ca_to_data = sdr->tWHR_min + 
sdr->tREA_max - sdr->tDH_min;
d8701fe890ecba Miquel Raynal 2021-12-17  928  
d8701fe890ecba Miquel Raynal 2021-12-17  929/*
d8701fe890ecba Miquel Raynal 2021-12-17  930 * D0 = CMD -> ADDR = tCLH + 
tCLS - 1 cycle
d8701fe890ecba Miquel Raynal 2021-12-17  931 * D1 = CMD -> CMD = tCLH + 
tCLS - 1 cycle
d8701fe890ecba Miquel Raynal 2021-12-17  932 * D2 = CMD -> DLY = tWB - tDH
d8701fe890ecba Miquel Raynal 2021-12-17  933 * D3 = CMD -> DATA = tWHR + 
tREA - tDH
d8701fe890ecba Miquel Raynal 2021-12-17  934 */
d8701fe890ecba Miquel Raynal 2021-12-17  935rnand->tim_gen_seq0 =
d8701fe890ecba Miquel Raynal 2021-12-17  936

[kbuild] drivers/mtd/nand/raw/renesas-nand-controller.c:900 rnandc_setup_interface() warn: passing a valid pointer to 'PTR_ERR'

2022-04-19 Thread kernel test robot

CC: kbuild-...@lists.01.org
BCC: l...@intel.com
CC: linux-ker...@vger.kernel.org
TO: Miquel Raynal 

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 
master
head:   b2d229d4ddb17db541098b83524d901257e93845
commit: d8701fe890ecbab239086e7053d62d0f08587d7c mtd: rawnand: renesas: Add new 
NAND controller driver
date:   4 months ago
:: branch date: 33 hours ago
:: commit date: 4 months ago
config: h8300-randconfig-m031-20220418 
(https://download.01.org/0day-ci/archive/20220419/202204191443.s4e9qa3p-...@intel.com/config)
compiler: h8300-linux-gcc (GCC) 11.2.0

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot 
Reported-by: Dan Carpenter 

smatch warnings:
drivers/mtd/nand/raw/renesas-nand-controller.c:900 rnandc_setup_interface() 
warn: passing a valid pointer to 'PTR_ERR'

vim +/PTR_ERR +900 drivers/mtd/nand/raw/renesas-nand-controller.c

d8701fe890ecba Miquel Raynal 2021-12-17  888  
d8701fe890ecba Miquel Raynal 2021-12-17  889  static int 
rnandc_setup_interface(struct nand_chip *chip, int chipnr,
d8701fe890ecba Miquel Raynal 2021-12-17  890  const 
struct nand_interface_config *conf)
d8701fe890ecba Miquel Raynal 2021-12-17  891  {
d8701fe890ecba Miquel Raynal 2021-12-17  892struct rnand_chip *rnand = 
to_rnand(chip);
d8701fe890ecba Miquel Raynal 2021-12-17  893struct rnandc *rnandc = 
to_rnandc(chip->controller);
d8701fe890ecba Miquel Raynal 2021-12-17  894unsigned int period_ns = 
10 / clk_get_rate(rnandc->eclk);
d8701fe890ecba Miquel Raynal 2021-12-17  895const struct nand_sdr_timings 
*sdr;
d8701fe890ecba Miquel Raynal 2021-12-17  896unsigned int cyc, cle, ale, 
bef_dly, ca_to_data;
d8701fe890ecba Miquel Raynal 2021-12-17  897  
d8701fe890ecba Miquel Raynal 2021-12-17  898sdr = 
nand_get_sdr_timings(conf);
d8701fe890ecba Miquel Raynal 2021-12-17  899if (IS_ERR(sdr))
d8701fe890ecba Miquel Raynal 2021-12-17 @900return PTR_ERR(sdr);
d8701fe890ecba Miquel Raynal 2021-12-17  901  
d8701fe890ecba Miquel Raynal 2021-12-17  902if (sdr->tRP_min != 
sdr->tWP_min || sdr->tREH_min != sdr->tWH_min) {
d8701fe890ecba Miquel Raynal 2021-12-17  903dev_err(rnandc->dev, 
"Read and write hold times must be identical\n");
d8701fe890ecba Miquel Raynal 2021-12-17  904return -EINVAL;
d8701fe890ecba Miquel Raynal 2021-12-17  905}
d8701fe890ecba Miquel Raynal 2021-12-17  906  
d8701fe890ecba Miquel Raynal 2021-12-17  907if (chipnr < 0)
d8701fe890ecba Miquel Raynal 2021-12-17  908return 0;
d8701fe890ecba Miquel Raynal 2021-12-17  909  
d8701fe890ecba Miquel Raynal 2021-12-17  910rnand->timings_asyn =
d8701fe890ecba Miquel Raynal 2021-12-17  911
TIMINGS_ASYN_TRWP(TO_CYCLES64(sdr->tRP_min, period_ns)) |
d8701fe890ecba Miquel Raynal 2021-12-17  912
TIMINGS_ASYN_TRWH(TO_CYCLES64(sdr->tREH_min, period_ns));
d8701fe890ecba Miquel Raynal 2021-12-17  913rnand->tim_seq0 =
d8701fe890ecba Miquel Raynal 2021-12-17  914
TIM_SEQ0_TCCS(TO_CYCLES64(sdr->tCCS_min, period_ns)) |
d8701fe890ecba Miquel Raynal 2021-12-17  915
TIM_SEQ0_TADL(TO_CYCLES64(sdr->tADL_min, period_ns)) |
d8701fe890ecba Miquel Raynal 2021-12-17  916
TIM_SEQ0_TRHW(TO_CYCLES64(sdr->tRHW_min, period_ns)) |
d8701fe890ecba Miquel Raynal 2021-12-17  917
TIM_SEQ0_TWHR(TO_CYCLES64(sdr->tWHR_min, period_ns));
d8701fe890ecba Miquel Raynal 2021-12-17  918rnand->tim_seq1 =
d8701fe890ecba Miquel Raynal 2021-12-17  919
TIM_SEQ1_TWB(TO_CYCLES64(sdr->tWB_max, period_ns)) |
d8701fe890ecba Miquel Raynal 2021-12-17  920
TIM_SEQ1_TRR(TO_CYCLES64(sdr->tRR_min, period_ns)) |
d8701fe890ecba Miquel Raynal 2021-12-17  921
TIM_SEQ1_TWW(TO_CYCLES64(sdr->tWW_min, period_ns));
d8701fe890ecba Miquel Raynal 2021-12-17  922  
d8701fe890ecba Miquel Raynal 2021-12-17  923cyc = sdr->tDS_min + 
sdr->tDH_min;
d8701fe890ecba Miquel Raynal 2021-12-17  924cle = sdr->tCLH_min + 
sdr->tCLS_min;
d8701fe890ecba Miquel Raynal 2021-12-17  925ale = sdr->tALH_min + 
sdr->tALS_min;
d8701fe890ecba Miquel Raynal 2021-12-17  926bef_dly = sdr->tWB_max - 
sdr->tDH_min;
d8701fe890ecba Miquel Raynal 2021-12-17  927ca_to_data = sdr->tWHR_min + 
sdr->tREA_max - sdr->tDH_min;
d8701fe890ecba Miquel Raynal 2021-12-17  928  
d8701fe890ecba Miquel Raynal 2021-12-17  929/*
d8701fe890ecba Miquel Raynal 2021-12-17  930 * D0 = CMD -> ADDR = tCLH + 
tCLS - 1 cycle
d8701fe890ecba Miquel Raynal 2021-12-17  931 * D1 = CMD -> CMD = tCLH + 
tCLS - 1 cycle
d8701fe890ecba Miquel Raynal 2021-12-17  932 * D2 = CMD -> DLY = tWB - tDH
d8701fe890ecba Miquel Raynal 2021-12-17  933 * D3 = CMD -> DATA = tWHR + 
tREA - tDH
d8701fe890ecba Miquel Raynal 2021-12-17  934 */
d8701fe890ecba Miquel Raynal 2021-12-17  935rnand->tim_gen_seq0 =
d8701fe890ecba Miquel Raynal 2021-12-17  936

[kbuild] drivers/mtd/nand/raw/renesas-nand-controller.c:900 rnandc_setup_interface() warn: passing a valid pointer to 'PTR_ERR'

2022-02-09 Thread kernel test robot

CC: kbuild-...@lists.01.org
CC: linux-ker...@vger.kernel.org
TO: Miquel Raynal 

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 
master
head:   e6251ab4551f51fa4cee03523e08051898c3ce82
commit: d8701fe890ecbab239086e7053d62d0f08587d7c mtd: rawnand: renesas: Add new 
NAND controller driver
date:   7 weeks ago
:: branch date: 18 hours ago
:: commit date: 7 weeks ago
config: arm-randconfig-m031-20220208 
(https://download.01.org/0day-ci/archive/20220209/202202092212.0gpyblck-...@intel.com/config)
compiler: arm-linux-gnueabi-gcc (GCC) 11.2.0

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot 
Reported-by: Dan Carpenter 

smatch warnings:
drivers/mtd/nand/raw/renesas-nand-controller.c:900 rnandc_setup_interface() 
warn: passing a valid pointer to 'PTR_ERR'

vim +/PTR_ERR +900 drivers/mtd/nand/raw/renesas-nand-controller.c

d8701fe890ecbab Miquel Raynal 2021-12-17  888  
d8701fe890ecbab Miquel Raynal 2021-12-17  889  static int 
rnandc_setup_interface(struct nand_chip *chip, int chipnr,
d8701fe890ecbab Miquel Raynal 2021-12-17  890 const 
struct nand_interface_config *conf)
d8701fe890ecbab Miquel Raynal 2021-12-17  891  {
d8701fe890ecbab Miquel Raynal 2021-12-17  892   struct rnand_chip *rnand = 
to_rnand(chip);
d8701fe890ecbab Miquel Raynal 2021-12-17  893   struct rnandc *rnandc = 
to_rnandc(chip->controller);
d8701fe890ecbab Miquel Raynal 2021-12-17  894   unsigned int period_ns = 
10 / clk_get_rate(rnandc->eclk);
d8701fe890ecbab Miquel Raynal 2021-12-17  895   const struct nand_sdr_timings 
*sdr;
d8701fe890ecbab Miquel Raynal 2021-12-17  896   unsigned int cyc, cle, ale, 
bef_dly, ca_to_data;
d8701fe890ecbab Miquel Raynal 2021-12-17  897  
d8701fe890ecbab Miquel Raynal 2021-12-17  898   sdr = 
nand_get_sdr_timings(conf);
d8701fe890ecbab Miquel Raynal 2021-12-17  899   if (IS_ERR(sdr))
d8701fe890ecbab Miquel Raynal 2021-12-17 @900   return PTR_ERR(sdr);
d8701fe890ecbab Miquel Raynal 2021-12-17  901  
d8701fe890ecbab Miquel Raynal 2021-12-17  902   if (sdr->tRP_min != 
sdr->tWP_min || sdr->tREH_min != sdr->tWH_min) {
d8701fe890ecbab Miquel Raynal 2021-12-17  903   dev_err(rnandc->dev, 
"Read and write hold times must be identical\n");
d8701fe890ecbab Miquel Raynal 2021-12-17  904   return -EINVAL;
d8701fe890ecbab Miquel Raynal 2021-12-17  905   }
d8701fe890ecbab Miquel Raynal 2021-12-17  906  
d8701fe890ecbab Miquel Raynal 2021-12-17  907   if (chipnr < 0)
d8701fe890ecbab Miquel Raynal 2021-12-17  908   return 0;
d8701fe890ecbab Miquel Raynal 2021-12-17  909  
d8701fe890ecbab Miquel Raynal 2021-12-17  910   rnand->timings_asyn =
d8701fe890ecbab Miquel Raynal 2021-12-17  911   
TIMINGS_ASYN_TRWP(TO_CYCLES64(sdr->tRP_min, period_ns)) |
d8701fe890ecbab Miquel Raynal 2021-12-17  912   
TIMINGS_ASYN_TRWH(TO_CYCLES64(sdr->tREH_min, period_ns));
d8701fe890ecbab Miquel Raynal 2021-12-17  913   rnand->tim_seq0 =
d8701fe890ecbab Miquel Raynal 2021-12-17  914   
TIM_SEQ0_TCCS(TO_CYCLES64(sdr->tCCS_min, period_ns)) |
d8701fe890ecbab Miquel Raynal 2021-12-17  915   
TIM_SEQ0_TADL(TO_CYCLES64(sdr->tADL_min, period_ns)) |
d8701fe890ecbab Miquel Raynal 2021-12-17  916   
TIM_SEQ0_TRHW(TO_CYCLES64(sdr->tRHW_min, period_ns)) |
d8701fe890ecbab Miquel Raynal 2021-12-17  917   
TIM_SEQ0_TWHR(TO_CYCLES64(sdr->tWHR_min, period_ns));
d8701fe890ecbab Miquel Raynal 2021-12-17  918   rnand->tim_seq1 =
d8701fe890ecbab Miquel Raynal 2021-12-17  919   
TIM_SEQ1_TWB(TO_CYCLES64(sdr->tWB_max, period_ns)) |
d8701fe890ecbab Miquel Raynal 2021-12-17  920   
TIM_SEQ1_TRR(TO_CYCLES64(sdr->tRR_min, period_ns)) |
d8701fe890ecbab Miquel Raynal 2021-12-17  921   
TIM_SEQ1_TWW(TO_CYCLES64(sdr->tWW_min, period_ns));
d8701fe890ecbab Miquel Raynal 2021-12-17  922  
d8701fe890ecbab Miquel Raynal 2021-12-17  923   cyc = sdr->tDS_min + 
sdr->tDH_min;
d8701fe890ecbab Miquel Raynal 2021-12-17  924   cle = sdr->tCLH_min + 
sdr->tCLS_min;
d8701fe890ecbab Miquel Raynal 2021-12-17  925   ale = sdr->tALH_min + 
sdr->tALS_min;
d8701fe890ecbab Miquel Raynal 2021-12-17  926   bef_dly = sdr->tWB_max - 
sdr->tDH_min;
d8701fe890ecbab Miquel Raynal 2021-12-17  927   ca_to_data = sdr->tWHR_min + 
sdr->tREA_max - sdr->tDH_min;
d8701fe890ecbab Miquel Raynal 2021-12-17  928  
d8701fe890ecbab Miquel Raynal 2021-12-17  929   /*
d8701fe890ecbab Miquel Raynal 2021-12-17  930* D0 = CMD -> ADDR = tCLH + 
tCLS - 1 cycle
d8701fe890ecbab Miquel Raynal 2021-12-17  931* D1 = CMD -> CMD = tCLH + 
tCLS - 1 cycle
d8701fe890ecbab Miquel Raynal 2021-12-17  932* D2 = CMD -> DLY = tWB - tDH
d8701fe890ecbab Miquel Raynal 2021-12-17  933* D3 = CMD -> DATA = tWHR + 
tREA - tDH
d8701fe890ecbab Miquel Raynal 2021-12-17  934*/
d8701fe890ecbab Miquel Raynal 2021-12-17  935   rnand->tim_gen_seq0 =
d8701fe890ecbab Miquel Raynal 2021-12-17  936

[kbuild] drivers/mtd/nand/raw/renesas-nand-controller.c:900 rnandc_setup_interface() warn: passing a valid pointer to 'PTR_ERR'

[kbuild] drivers/mtd/nand/raw/renesas-nand-controller.c:900 rnandc_setup_interface() warn: passing a valid pointer to 'PTR_ERR'

[kbuild] drivers/mtd/nand/raw/renesas-nand-controller.c:900 rnandc_setup_interface() warn: passing a valid pointer to 'PTR_ERR'

[kbuild] drivers/mtd/nand/raw/renesas-nand-controller.c:900 rnandc_setup_interface() warn: passing a valid pointer to 'PTR_ERR'

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