[kvm-devel] [PATCH][UPDATE] kvm-userspace: sync icache for more architectures

2007-12-18 Thread Christian Ehrhardt 
Subject: [PATCH][UPDATE] kvm-userspace: sync icache for more architectures
From: Christian Ehrhardt [EMAIL PROTECTED]

A ia64 patch introduced kvm_sync_icache within a ifdef __ia64__, but the 
concept of split caches is not bound to ia64. This patch replaces the the 
call to kvm_synch_icache by the flush_icache_range function
that is already available in qemu for ia64 and ppc (noop for x86). 
The call now depends on USE_KVM.

Signed-off-by: Christian Ehrhardt [EMAIL PROTECTED]

diff --git a/qemu/exec.c b/qemu/exec.c
index 8b6a2f6..7371cc7 100644
--- a/qemu/exec.c
+++ b/qemu/exec.c
@@ -35,6 +35,7 @@
 #include cpu.h
 #include exec-all.h
 #ifdef USE_KVM
+#include dyngen.h
 #include qemu-kvm.h
 #endif
 #if defined(CONFIG_USER_ONLY)
@@ -2600,8 +2601,10 @@ void cpu_physical_memory_rw(target_phys_addr_t addr, 
uint8_t *buf,
 phys_ram_dirty[addr1  TARGET_PAGE_BITS] |=
 (0xff  ~CODE_DIRTY_FLAG);
 }
-#ifdef __ia64__
-   kvm_sync_icache((unsigned long)ptr, l);
+#ifdef USE_KVM
+   /* qemu doesn't execute guest code directly, but kvm does
+  therefore fluch instruction caches */
+   flush_icache_range((unsigned long)ptr, ((unsigned long)ptr)+l);
 #endif
 }
 } else {
diff --git a/qemu/hw/ipf.c b/qemu/hw/ipf.c
index 03df73d..cf76f35 100644
--- a/qemu/hw/ipf.c
+++ b/qemu/hw/ipf.c
@@ -273,17 +273,6 @@ static void pc_init_ne2k_isa(NICInfo *nd, qemu_irq *pic)
 #ifdef USE_KVM
 extern kvm_context_t kvm_context;
 extern int kvm_allowed;
-
-void kvm_sync_icache(unsigned long address, int len)
-{
-   int l;
-
-   for(l = 0; l  (len + 32); l += 32)
-   __ia64_fc(address + l);
-
-   ia64_sync_i();
-   ia64_srlz_i();
-}
 #endif
 
 static void main_cpu_reset(void *opaque)
diff --git a/qemu/target-ia64/cpu.h b/qemu/target-ia64/cpu.h
index 7349e94..be409c7 100644
--- a/qemu/target-ia64/cpu.h
+++ b/qemu/target-ia64/cpu.h
@@ -73,9 +73,4 @@ CPUState *cpu_ia64_init(void);
 
 #include cpu-all.h
 
-/* IA64 has seperate I/D cache, with coherence maintained by DMA controller.
- * So to emulate right behavior that guest OS is assumed, we need to flush
- * I/D cache here.
- */
-void kvm_sync_icache(unsigned long address, int len);
 #endif

-
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Re: [kvm-devel] [PATCH][UPDATE] kvm-userspace: sync icache for more architectures

2007-12-18 Thread Avi Kivity 
Christian Ehrhardt wrote:
 Subject: [PATCH][UPDATE] kvm-userspace: sync icache for more architectures
 From: Christian Ehrhardt [EMAIL PROTECTED]

 A ia64 patch introduced kvm_sync_icache within a ifdef __ia64__, but the 
 concept of split caches is not bound to ia64. This patch replaces the the 
 call to kvm_synch_icache by the flush_icache_range function
 that is already available in qemu for ia64 and ppc (noop for x86). 
 The call now depends on USE_KVM.

   

Applied, thanks.

-- 
error compiling committee.c: too many arguments to function


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[kvm-devel] [PATCH][UPDATE] kvm-userspace: sync icache for more architectures

2007-12-13 Thread Christian Ehrhardt 
Subject: [PATCH][UPDATE] kvm-userspace: sync icache for more architectures
From: Christian Ehrhardt [EMAIL PROTECTED]

A ia64 patch introduced kvm_sync_icache within a ifdef __ia64__, but the 
concept of split caches is not bound to ia64 and we would like to implement
it for ppc too.
The call to kvm_synch_icache is replaced by the flush_icache_range function
that is already available in qemu for ia64 and ppc (noop for x86). The call
now depends on USE_KVM.
This patch supersedes my old [PATCH] kvm-userspace: kvm_sync_icache for more 
architectures from this morning. 
The current ppc code around is not yet ready (it compiles  works for x86),
could someone please testverify this patch for ia64?

Signed-off-by: Christian Ehrhardt [EMAIL PROTECTED]

diff --git a/qemu/exec.c b/qemu/exec.c
index cf14fdd..d2a8f5b 100644
--- a/qemu/exec.c
+++ b/qemu/exec.c
@@ -35,6 +35,7 @@
 #include cpu.h
 #include exec-all.h
 #ifdef USE_KVM
+#include dyngen.h
 #include qemu-kvm.h
 #endif
 #if defined(CONFIG_USER_ONLY)
@@ -2600,8 +2601,8 @@ void cpu_physical_memory_rw(target_phys_addr_t addr, 
uint8_t *buf,
 phys_ram_dirty[addr1  TARGET_PAGE_BITS] |=
 (0xff  ~CODE_DIRTY_FLAG);
 }
-#ifdef __ia64__
-   kvm_sync_icache((unsigned long)ptr, l);
+#ifdef USE_KVM
+   flush_icache_range((unsigned long)ptr, ((unsigned long)ptr)+l);
 #endif
 }
 } else {
diff --git a/qemu/hw/ipf.c b/qemu/hw/ipf.c
index 957e831..8686c1e 100644
--- a/qemu/hw/ipf.c
+++ b/qemu/hw/ipf.c
@@ -105,17 +105,6 @@ static void pc_init_ne2k_isa(NICInfo *nd, qemu_irq *pic)
 #ifdef USE_KVM
 extern kvm_context_t kvm_context;
 extern int kvm_allowed;
-
-void kvm_sync_icache(unsigned long address, int len)
-{
-   int l;
-
-   for(l = 0; l  (len + 32); l += 32)
-   __ia64_fc(address + l);
-
-   ia64_sync_i();
-   ia64_srlz_i();
-}
 #endif
 
 static void main_cpu_reset(void *opaque)
diff --git a/qemu/target-ia64/cpu.h b/qemu/target-ia64/cpu.h
index 7349e94..be409c7 100644
--- a/qemu/target-ia64/cpu.h
+++ b/qemu/target-ia64/cpu.h
@@ -73,9 +73,4 @@ CPUState *cpu_ia64_init(void);
 
 #include cpu-all.h
 
-/* IA64 has seperate I/D cache, with coherence maintained by DMA controller.
- * So to emulate right behavior that guest OS is assumed, we need to flush
- * I/D cache here.
- */
-void kvm_sync_icache(unsigned long address, int len);
 #endif

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Re: [kvm-devel] [PATCH][UPDATE] kvm-userspace: sync icache for more architectures

2007-12-13 Thread Hollis Blanchard 
On Thu, 2007-12-13 at 20:36 +0100, Christian Ehrhardt wrote:
 @@ -2600,8 +2601,8 @@ void cpu_physical_memory_rw(target_phys_addr_t
 addr, uint8_t *buf,
  phys_ram_dirty[addr1  TARGET_PAGE_BITS] |=
  (0xff  ~CODE_DIRTY_FLAG);
  }
 -#ifdef __ia64__
 - kvm_sync_icache((unsigned long)ptr, l);
 +#ifdef USE_KVM
 + flush_icache_range((unsigned long)ptr, ((unsigned long)ptr)+l);
  #endif
  }
  } else {

A comment to explain why the icache needs flushing only in the KVM case
would be useful. Other than that I'm fine with it.

Signed-off-by: Hollis Blanchard [EMAIL PROTECTED]

-- 
Hollis Blanchard
IBM Linux Technology Center


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