[PATCH v7 4/9] Documentation: perf: hisi: Documentation for HiP05/06/07 PMU event counting.
Documentation for perf usage and Hisilicon SoC PMU uncore events. The Hisilicon SOC has event counters for hardware modules like L3 cache, Miscellaneous node etc. These events are all uncore. Signed-off-by: Anurup M <anuru...@huawei.com> Signed-off-by: Shaokun Zhang <zhangshao...@hisilicon.com> --- Documentation/perf/hisi-pmu.txt | 75 + 1 file changed, 75 insertions(+) create mode 100644 Documentation/perf/hisi-pmu.txt diff --git a/Documentation/perf/hisi-pmu.txt b/Documentation/perf/hisi-pmu.txt new file mode 100644 index 000..a21571d --- /dev/null +++ b/Documentation/perf/hisi-pmu.txt @@ -0,0 +1,75 @@ +Hisilicon SoC PMU (Performance Monitoring Unit) + +The Hisilicon SoC HiP05/06/07 chips consist of various independent system +device PMU's such as L3 cache(L3C) and Miscellaneous Nodes(MN). +These PMU devices are independent and have hardware logic to gather +statistics and performance information. + +HiP0x chips are encapsulated by multiple CPU and IO dies. The CPU die is +called as Super CPU cluster (SCCL) which includes 16 cpu-cores. Every SCCL +is further grouped as CPU clusters (CCL) which includes 4 cpu-cores each. +Each SCCL has 1 L3 cache and 1 MN units. + +The L3 cache is shared by all CPU cores in a CPU die. The L3C has four banks +(or instances). Each bank or instance of L3C has Eight 32-bit counter +registers and also event control registers. The HiP05/06 chip L3 cache has +22 statistics events. The HiP07 chip has 66 statistics events. These events +are very useful for debugging. + +The MN module is also shared by all CPU cores in a CPU die. It receives +barriers and DVM(Distributed Virtual Memory) messages from cpu or smmu, and +perform the required actions and return response messages. These events are +very useful for debugging. The MN has total 9 statistics events and support +four 32-bit counter registers in HiP05/06/07 chips. + +There is no memory mapping for L3 cache and MN registers. It can be accessed +by using the Hisilicon djtag interface. The Djtag in a SCCL is an independent +module which connects with some modules in the SoC by Debug Bus. + +Hisilicon SoC (HiP05/06/07) PMU driver +-- +The HiP0x PMU driver shall register perf PMU drivers like L3 cache, MN etc. +The available events and configuration options shall be described in the sysfs. +The "perf list" shall list the available events from sysfs. + +The L3 cache in a SCCL is divided as 4 banks. Each L3 cache bank have separate +PMU registers for event counting and control. The L3 cache banks also do not +have any CPU affinity. So each L3 cache banks are registered with perf as a +separate PMU. +The PMU name will appear in event listing as hisi_l3c_. +where "bank-id" is the bank index (0 to 3) and "scl-id" is the SCCL identifier +e.g. hisi_l3c0_2/read_hit is READ_HIT event of L3 cache bank #0 SCCL ID #2. + +The MN in a SCCL is registered as a separate PMU with perf. +The PMU name will appear in event listing as hisi_mn_. +e.g. hisi_mn_2/read_req. READ_REQUEST event of MN of Super CPU cluster #2. + +The event code is represented by 8 bits. + i) event 0-7 + The event code will be represented using the LSB 8 bits. + +The driver also provides a "cpumask" sysfs attribute, which shows the CPU core +ID used to count the uncore PMU event. + +Example usage of perf: +$# perf list +hisi_l3c0_2/read_hit/ [kernel PMU event] +-- +hisi_l3c1_2/write_hit/ [kernel PMU event] +-- +hisi_l3c0_1/read_hit/ [kernel PMU event] +-- +hisi_l3c0_1/write_hit/ [kernel PMU event] +-- +hisi_mn_2/read_req/ [kernel PMU event] +hisi_mn_2/write_req/ [kernel PMU event] +-- + +$# perf stat -a -e "hisi_l3c0_2/read_allocate/" sleep 5 +$# perf stat -A -C 0 -e "hisi_l3c0_2/read_allocate/" sleep 5 + +The current driver does not support sampling. So "perf record" is unsupported. +Also attach to a task is unsupported as the events are all uncore. + +Note: Please contact the maintainer for a complete list of events supported for +the PMU devices in the SoC and its information if needed. -- 2.1.4 -- To unsubscribe from this list: send the line "unsubscribe linux-doc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v6 04/11] Documentation: perf: hisi: Documentation for HiP05/06/07 PMU event counting.
Thanks for the review. On Tuesday 21 March 2017 07:42 PM, Mark Rutland wrote: Hi, On Fri, Mar 10, 2017 at 01:27:39AM -0500, Anurup M wrote: +HiP0x chips are encapsulated by multiple CPU and IO die's. The CPU die is Nit: that apostrophe shouldn't be there. Ok. shall recheck and modify wherever applicable. [...] +The current driver doesnot support sampling. so "perf record" is unsupported. Nit: spacing Otherwise, this looked fine. Thanks. shall correct it. Thanks, Mark. -- To unsubscribe from this list: send the line "unsubscribe linux-doc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v6 04/11] Documentation: perf: hisi: Documentation for HiP05/06/07 PMU event counting.
Documentation for perf usage and Hisilicon SoC PMU uncore events. The Hisilicon SOC has event counters for hardware modules like L3 cache, Miscellaneous node etc. These events are all uncore. Signed-off-by: Anurup M <anuru...@huawei.com> Signed-off-by: Shaokun Zhang <zhangshao...@hisilicon.com> --- Documentation/perf/hisi-pmu.txt | 76 + 1 file changed, 76 insertions(+) create mode 100644 Documentation/perf/hisi-pmu.txt diff --git a/Documentation/perf/hisi-pmu.txt b/Documentation/perf/hisi-pmu.txt new file mode 100644 index 000..e3ac562 --- /dev/null +++ b/Documentation/perf/hisi-pmu.txt @@ -0,0 +1,76 @@ +Hisilicon SoC PMU (Performance Monitoring Unit) + +The Hisilicon SoC HiP05/06/07 chips consist of various independent system +device PMU's such as L3 cache(L3C) and Miscellaneous Nodes(MN). +These PMU devices are independent and have hardware logic to gather +statistics and performance information. + +HiP0x chips are encapsulated by multiple CPU and IO die's. The CPU die is +called as Super CPU cluster (SCCL) which includes 16 cpu-cores. Every SCCL +is further grouped as CPU clusters (CCL) which includes 4 cpu-cores each. +Each SCCL has 1 L3 cache and 1 MN units. + +The L3 cache is shared by all CPU cores in a CPU die. The L3C has four banks +(or instances). Each bank or instance of L3C has Eight 32-bit counter +registers and also event control registers. The HiP05/06 chip L3 cache has +22 statistics events. The HiP07 chip has 66 statistics events. These events +are very useful for debugging. + +The MN module is also shared by all CPU cores in a CPU die. It receives +barriers and DVM(Distributed Virtual Memory) messages from cpu or smmu, and +perform the required actions and return response messages. These events are +very useful for debugging. The MN has total 9 statistics events and support +four 32-bit counter registers in HiP05/06/07 chips. + +There is no memory mapping for L3 cache and MN registers. It can be accessed +by using the Hisilicon djtag interface. The Djtag in a SCCL is an independent +module which connects with some modules in the SoC by Debug Bus. + +Hisilicon SoC (HiP05/06/07) PMU driver +-- +The HiP0x PMU driver shall register perf PMU drivers like L3 cache, MN, etc. +The available events and configuration options shall be described in the sysfs. +The "perf list" shall list the available events from sysfs. + +The L3 cache in a SCCL is divided as 4 banks. Each L3 cache bank have separate +PMU registers for event counting and control. The L3 cache banks also do not +have any CPU affinity. So each L3 cache banks are registered with perf as a +separate PMU. +The PMU name will appear in event listing as hisi_l3c_. +where "bank-id" is the bank index (0 to 3) and "scl-id" is the SCCL identifier +e.g. hisi_l3c0_2/read_hit is READ_HIT event of L3 cache bank #0 SCCL ID #2. + +The MN in a SCCL is registered as a separate PMU with perf. +The PMU name will appear in event listing as hisi_mn_. +e.g. hisi_mn_2/read_req. READ_REQUEST event of MN of Super CPU cluster #2. + +The event code is represented by 12 bits. + i) event 0-11 + The event code will be represented using the LSB 12 bits. + +The driver also provides a "cpumask" sysfs attribute, which shows the CPU core +ID used to count the uncore PMU event. + +Example usage of perf: +$# perf list +hisi_l3c0_2/read_hit/ [kernel PMU event] +-- +hisi_l3c1_2/write_hit/ [kernel PMU event] +-- +hisi_l3c0_1/read_hit/ [kernel PMU event] +-- +hisi_l3c0_1/write_hit/ [kernel PMU event] +-- +hisi_mn_2/read_req/ [kernel PMU event] +hisi_mn_2/write_req/ [kernel PMU event] +-- + +$# perf stat -a -e "hisi_l3c0_2/read_allocate/" sleep 5 + +$# perf stat -A -C 0 -e "hisi_l3c0_2/read_allocate/" sleep 5 + +The current driver doesnot support sampling. so "perf record" is unsupported. +Also attach to a task is unsupported as the events are all uncore. + +Note: Please contact the maintainer for a complete list of events supported for +the PMU devices in the SoC and its information if needed. -- 2.1.4 -- To unsubscribe from this list: send the line "unsubscribe linux-doc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RESEND PATCH v5 04/11 (Missed 04/11 in PATCH v5 series)] Documentation: perf: hisi: Documentation for HiP05/06/07 PMU event counting.
Documentation for perf usage and Hisilicon SoC PMU uncore events. The Hisilicon SOC has event counters for hardware modules like L3 cache, Miscellaneous node etc. These events are all uncore. Signed-off-by: Anurup M <anuru...@huawei.com> Signed-off-by: Shaokun Zhang <zhangshao...@hisilicon.com> --- Documentation/perf/hisi-pmu.txt | 76 + 1 file changed, 76 insertions(+) create mode 100644 Documentation/perf/hisi-pmu.txt diff --git a/Documentation/perf/hisi-pmu.txt b/Documentation/perf/hisi-pmu.txt new file mode 100644 index 000..e3ac562 --- /dev/null +++ b/Documentation/perf/hisi-pmu.txt @@ -0,0 +1,76 @@ +Hisilicon SoC PMU (Performance Monitoring Unit) + +The Hisilicon SoC HiP05/06/07 chips consist of various independent system +device PMU's such as L3 cache(L3C) and Miscellaneous Nodes(MN). +These PMU devices are independent and have hardware logic to gather +statistics and performance information. + +HiP0x chips are encapsulated by multiple CPU and IO die's. The CPU die is +called as Super CPU cluster (SCCL) which includes 16 cpu-cores. Every SCCL +is further grouped as CPU clusters (CCL) which includes 4 cpu-cores each. +Each SCCL has 1 L3 cache and 1 MN units. + +The L3 cache is shared by all CPU cores in a CPU die. The L3C has four banks +(or instances). Each bank or instance of L3C has Eight 32-bit counter +registers and also event control registers. The HiP05/06 chip L3 cache has +22 statistics events. The HiP07 chip has 66 statistics events. These events +are very useful for debugging. + +The MN module is also shared by all CPU cores in a CPU die. It receives +barriers and DVM(Distributed Virtual Memory) messages from cpu or smmu, and +perform the required actions and return response messages. These events are +very useful for debugging. The MN has total 9 statistics events and support +four 32-bit counter registers in HiP05/06/07 chips. + +There is no memory mapping for L3 cache and MN registers. It can be accessed +by using the Hisilicon djtag interface. The Djtag in a SCCL is an independent +module which connects with some modules in the SoC by Debug Bus. + +Hisilicon SoC (HiP05/06/07) PMU driver +-- +The HiP0x PMU driver shall register perf PMU drivers like L3 cache, MN, etc. +The available events and configuration options shall be described in the sysfs. +The "perf list" shall list the available events from sysfs. + +The L3 cache in a SCCL is divided as 4 banks. Each L3 cache bank have separate +PMU registers for event counting and control. The L3 cache banks also do not +have any CPU affinity. So each L3 cache banks are registered with perf as a +separate PMU. +The PMU name will appear in event listing as hisi_l3c_. +where "bank-id" is the bank index (0 to 3) and "scl-id" is the SCCL identifier +e.g. hisi_l3c0_2/read_hit is READ_HIT event of L3 cache bank #0 SCCL ID #2. + +The MN in a SCCL is registered as a separate PMU with perf. +The PMU name will appear in event listing as hisi_mn_. +e.g. hisi_mn_2/read_req. READ_REQUEST event of MN of Super CPU cluster #2. + +The event code is represented by 12 bits. + i) event 0-11 + The event code will be represented using the LSB 12 bits. + +The driver also provides a "cpumask" sysfs attribute, which shows the CPU core +ID used to count the uncore PMU event. + +Example usage of perf: +$# perf list +hisi_l3c0_2/read_hit/ [kernel PMU event] +-- +hisi_l3c1_2/write_hit/ [kernel PMU event] +-- +hisi_l3c0_1/read_hit/ [kernel PMU event] +-- +hisi_l3c0_1/write_hit/ [kernel PMU event] +-- +hisi_mn_2/read_req/ [kernel PMU event] +hisi_mn_2/write_req/ [kernel PMU event] +-- + +$# perf stat -a -e "hisi_l3c0_2/read_allocate/" sleep 5 + +$# perf stat -A -C 0 -e "hisi_l3c0_2/read_allocate/" sleep 5 + +The current driver doesnot support sampling. so "perf record" is unsupported. +Also attach to a task is unsupported as the events are all uncore. + +Note: Please contact the maintainer for a complete list of events supported for +the PMU devices in the SoC and its information if needed. -- 2.1.4 -- To unsubscribe from this list: send the line "unsubscribe linux-doc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 04/10] Documentation: perf: hisi: Documentation for HiP05/06/07 PMU event counting.
On Tuesday 10 January 2017 11:25 PM, Mark Rutland wrote: On Mon, Jan 02, 2017 at 01:49:37AM -0500, Anurup M wrote: +The Hisilicon SoC HiP05/06/07 chips consist of various independent system +device PMU's such as L3 cache(L3C) and Miscellaneous Nodes(MN). +These PMU devices are independent and have hardware logic to gather +statistics and performance information. + +HiP0x chips are encapsulated by multiple CPU and IO die's. The CPU die is +called as Super CPU cluster (SCCL) which includes 16 cpu-cores. Every SCCL +is further grouped as CPU clusters (CCL) which includes 4 cpu-cores each. +Each SCCL has 1 L3 cache and 1 MN units. Are there systems with multiple SCCLs? Or is there only one SCCL per system? The HiP0x are encapsulated by multiple SCCL (CPU die) and SICL (IO die). The HiP06 and HiP07 have two SCCLs. +The L3 cache is shared by all CPU cores in a CPU die. The L3C has four banks +(or instances). Each bank or instance of L3C has Eight 32-bit counter +registers and also event control registers. The HiP05/06 chip L3 cache has +22 statistics events. The HiP07 chip has 66 statistics events. These events +are very useful for debugging. Is an L3C associated with a subset of physical memory (as with the ARM CCN's L3C), or is it associated with a set of CPUs (e.g. only those in a single SCCL) covering all physical memory (as with each CPU's L1 & L2)? Yes the L3C is associated with the set of CPUs in a single SCCL covering all physical memory. The L3 cache in all the SCCLs share the complete physical memory. Thanks, Anurup Thanks, Mark. -- To unsubscribe from this list: send the line "unsubscribe linux-doc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 04/10] Documentation: perf: hisi: Documentation for HIP05/06/07 PMU event counting.
Documentation for perf usage and Hisilicon SoC PMU uncore events. The Hisilicon SOC has event counters for hardware modules like L3 cache, Miscellaneous node etc. These events are all uncore. Signed-off-by: Anurup M <anuru...@huawei.com> Signed-off-by: Shaokun Zhang <zhangshao...@hisilicon.com> --- Documentation/perf/hisi-pmu.txt | 75 + 1 file changed, 75 insertions(+) create mode 100644 Documentation/perf/hisi-pmu.txt diff --git a/Documentation/perf/hisi-pmu.txt b/Documentation/perf/hisi-pmu.txt new file mode 100644 index 000..2539caf --- /dev/null +++ b/Documentation/perf/hisi-pmu.txt @@ -0,0 +1,75 @@ +Hisilicon SoC PMU (Performance Monitoring Unit) + +The Hisilicon SoC hip05/06/07 chips consist of varous independent system +device PMU's such as L3 cache(L3C) and Miscellaneous Nodes(MN). +These PMU devices are independent and have hardware logic to gather +statistics and performance information. + +Hip0x chips are encapsulated by multiple CPU and IO die's. The CPU die is +called as Super CPU cluster (SCCL) which includes 16 cpu-cores. Every SCCL +is further grouped as CPU clusters (CCL) which includes 4 cpu-cores each. +Each SCCL has 1 L3 cache and 1 MN units. + +The L3 cache is shared by all CPU cores in a CPU die. The L3C has four banks +(or instances). Each bank or instance of L3C has Eight 32-bit counter +registers and also event control registers. The hip05/06 chip L3 cache has +22 statistics events. The hip07 chip has 66 statistics events. These events +are very useful for debugging. + +The MN module is also shared by all CPU cores in a CPU die. It receives +barriers and DVM(Distributed Virtual Memory) messages from cpu or smmu, and +perform the required actions and return response messages. These events are +very useful for debugging. The MN has total 9 statistics events and support +four 32-bit counter registers in hip05/06/07 chips. + +There is no memory mapping for L3 cache and MN registers. It can be accessed +by using the Hisilicon djtag interface. The Djtag in a SCCL is an independent +module which connects with some modules in the SoC by Debug Bus. + +Hisilicon SoC (hip05/06/07) PMU driver +-- +The hip0x PMU driver shall register perf PMU drivers like L3 cache, MN, etc. +The available events and configuration options shall be described in the sysfs. +The "perf list" shall list the available events from sysfs. + +The L3 cache in a SCCL is divided as 4 banks. Each L3 cache bank have separate +PMU registers for event counting and control. So each L3 cache bank is +registered with perf as a separate PMU. +The PMU name will appear in event listing as hisi_l3c_. +where "bank-id" is the bank index (0 to 3) and "scl-id" is the SCCL identifier +e.g. hisi_l3c0_2/read_hit is READ_HIT event of L3 cache bank #0 SCCL ID #2. + +The MN in a SCCL is registered as a separate PMU with perf. +The PMU name will appear in event listing as hisi_mn_. +e.g. hisi_mn_2/read_req. READ_REQUEST event of MN of Super CPU cluster #2. + +The event code is represented by 12 bits. + i) event 0-11 + The event code will be represented using the LSB 12 bits. + +The driver also provides a "cpumask" sysfs attribute, which shows the CPU core +ID used to count the uncore PMU event. + +Example usage of perf: +$# perf list +hisi_l3c0_2/read_hit/ [kernel PMU event] +-- +hisi_l3c1_2/write_hit/ [kernel PMU event] +-- +hisi_l3c0_1/read_hit/ [kernel PMU event] +-- +hisi_l3c0_1/write_hit/ [kernel PMU event] +-- +hisi_mn_2/read_req/ [kernel PMU event] +hisi_mn_2/write_req/ [kernel PMU event] +-- + +$# perf stat -a -e "hisi_l3c0_2/read_allocate/" sleep 5 + +$# perf stat -A -C 0 -e "hisi_l3c0_2/read_allocate/" sleep 5 + +The current driver doesnot support sampling. so "perf record" is unsupported. +Also attach to a task is unsupported as the events are all uncore. + +Note: Please contact the maintainer for a complete list of events supported for +the PMU devices in the SoC and its information if needed. -- 2.1.4 -- To unsubscribe from this list: send the line "unsubscribe linux-doc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RESEND PATCH v1 05/11] dt-bindings: perf: hisi: Add Devicetree bindings for Hisilicon SoC PMU
On Tuesday 15 November 2016 03:21 PM, Mark Rutland wrote: On Mon, Nov 14, 2016 at 05:36:44AM +0530, Anurup M wrote: On Friday 11 November 2016 12:00 AM, Mark Rutland wrote: On Thu, Nov 03, 2016 at 01:42:01AM -0400, Anurup M wrote: + - scl-id : The Super Cluster ID. This can be the ID of the CPU die + or IO die in the chip. What's this needed for? This is used as suffix to the PMU name. hisi_l3c. (hisi_l3c2 - for scl-id = 2). This is to identify the pmu correspond to which CPU die in the socket. + - num-events : No of events supported by this PMU device. + + - num-counters : No of hardware counters available for counting. This isn't probeable or well-known? My idea is to have the common properties of SoC PMU added here. The num-events, num-counters etc. So that handling can be made common in the driver. Is it not recommended? Please share your comments. This feels like something that should be well-known for the programming model of the device. If the number of events and/or counters shange, I'd expect other things to also change such that the device is no longer compatible with previous versions. [...] Agreed, it is possible that the versions can be still incompatible. Shall move it to driver in v2. The below two properties (module-id, cfgen-map) differs between chips hip05/06 and hip07. The module-id property sounds like a HW description, but it's not entirely clear to me what cfgen-map is; more comments on that below. Please suggest. + - module-id : Module ID to input for djtag. This property is an array of + module_id for each L3 cache banks. + + - num-banks : Number of banks or instances of the device. What's a bank? Surely they have separate instances of the PMU? Yes each bank is a separate instance of PMU. If it is recommended to have each L3 cache bank registered as separate PMU with perf, then this property will be removed. Generally, I think that separate instances are preferable. What order are these in? The bank number will start from "1" till "4" for L3 cache as there are four banks in hip05/06/07 chips. + - cfgen-map : Config enable array to select the bank. Huh? As above, it's not clear to me what this property represents. Could you please clarify? This property is used to select the bank. The naming lead to confusion. I shall change it to bank_select. If it is recommended to register each L3 cache bank as separate PMU then this property will be moved to driver. Thanks Anurup Thanks, Mark. -- To unsubscribe from this list: send the line "unsubscribe linux-doc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RESEND PATCH v1 03/11] drivers: soc: hisi: Add support for Hisilicon Djtag driver
On Thursday 10 November 2016 11:25 PM, Mark Rutland wrote:
On Thu, Nov 03, 2016 at 01:41:59AM -0400, Anurup M wrote:
From: Tan Xiaojun <tanxiao...@huawei.com>
The Hisilicon Djtag is an independent component which connects
with some other components in the SoC by Debug Bus. This driver
can be configured to access the registers of connecting components
(like L3 cache) during real time debugging.
Just to check, is this likely to be used in multi-socket hardware, and
if so, are instances always-on?
Yes, It could be used in multi-socket hardware also.
The sockets are always enabled after bootup. Sorry I didn't get the
Signed-off-by: Tan Xiaojun <tanxiao...@huawei.com>
Signed-off-by: John Garry <john.ga...@huawei.com>
Signed-off-by: Anurup M <anuru...@huawei.com>
---
drivers/soc/Kconfig | 1 +
drivers/soc/Makefile| 1 +
drivers/soc/hisilicon/Kconfig | 12 +
drivers/soc/hisilicon/Makefile | 1 +
drivers/soc/hisilicon/djtag.c | 639
include/linux/soc/hisilicon/djtag.h | 38 +++
6 files changed, 692 insertions(+)
create mode 100644 drivers/soc/hisilicon/Kconfig
create mode 100644 drivers/soc/hisilicon/Makefile
create mode 100644 drivers/soc/hisilicon/djtag.c
create mode 100644 include/linux/soc/hisilicon/djtag.h
Other than the PMU driver(s), what is going to use this?
If you don't have something in particular, please also place this under
drivers/perf/hisilicon, along with the PMU driver(s).
We can always move it later if necessary.
[...]
Arnd also suggested the same. Currently as there are no other users I
shall move it to
drivers/perf/hisilicon.
+#define SC_DJTAG_TIMEOUT 10 /* 100ms */
This would be better as:
#define SC_DJTAG_TIMEOUT_US (100 * USEC_PER_MSEC)
(you'll need to include )
[...]
OK.
+static void djtag_read32_relaxed(void __iomem *regs_base, u32 off, u32 *value)
+{
+ void __iomem *reg_addr = regs_base + off;
+
+ *value = readl_relaxed(reg_addr);
+}
+
+static void djtag_write32(void __iomem *regs_base, u32 off, u32 val)
+{
+ void __iomem *reg_addr = regs_base + off;
+
+ writel(val, reg_addr);
+}
I think these make the driver harder to read, especially given the read
function is void and takes an output pointer.
In either case you can call readl/writel directly with base + off for
the __iomem ptr. Please do that.
Ok.
+
+/*
+ * djtag_readwrite_v1/v2: djtag read/write interface
+ * @reg_base: djtag register base address
+ * @offset:register's offset
+ * @mod_sel: module selection
+ * @mod_mask: mask to select specific modules for write
+ * @is_w: write -> true, read -> false
+ * @wval: value to register for write
+ * @chain_id: which sub module for read
+ * @rval: value in register for read
+ *
+ * Return non-zero if error, else return 0.
+ */
+static int djtag_readwrite_v1(void __iomem *regs_base, u32 offset, u32 mod_sel,
+ u32 mod_mask, bool is_w, u32 wval, int chain_id, u32 *rval)
+{
+ u32 rd;
+ int timeout = SC_DJTAG_TIMEOUT;
+
+ if (!(mod_mask & CHAIN_UNIT_CFG_EN)) {
+ pr_warn("djtag: do nothing.\n");
+ return 0;
+ }
+
+ /* djtag mster enable & accelerate R,W */
+ djtag_write32(regs_base, SC_DJTAG_MSTR_EN,
+ DJTAG_NOR_CFG | DJTAG_MSTR_EN);
+
+ /* select module */
+ djtag_write32(regs_base, SC_DJTAG_DEBUG_MODULE_SEL, mod_sel);
+ djtag_write32(regs_base, SC_DJTAG_CHAIN_UNIT_CFG_EN,
+ mod_mask & CHAIN_UNIT_CFG_EN);
+
+ if (is_w) {
+ djtag_write32(regs_base, SC_DJTAG_MSTR_WR, DJTAG_MSTR_W);
+ djtag_write32(regs_base, SC_DJTAG_MSTR_DATA, wval);
+ } else
+ djtag_write32(regs_base, SC_DJTAG_MSTR_WR, DJTAG_MSTR_R);
+
+ /* address offset */
+ djtag_write32(regs_base, SC_DJTAG_MSTR_ADDR, offset);
+
+ /* start to write to djtag register */
+ djtag_write32(regs_base, SC_DJTAG_MSTR_START_EN, DJTAG_MSTR_START_EN);
+
+ /* ensure the djtag operation is done */
+ do {
+ djtag_read32_relaxed(regs_base, SC_DJTAG_MSTR_START_EN, );
+ if (!(rd & DJTAG_MSTR_EN))
+ break;
+
+ udelay(1);
+ } while (timeout--);
+
+ if (timeout < 0) {
+ pr_err("djtag: %s timeout!\n", is_w ? "write" : "read");
+ return -EBUSY;
+ }
+
+ if (!is_w)
+ djtag_read32_relaxed(regs_base,
+ SC_DJTAG_RD_DATA_BASE + chain_id * 0x4, rval);
+
+ return 0;
+}
Please factor out the common bits into helpers and have separate
read/write functions. It's incredibly difficult to follow the code with
read/write hidden behind a b
Re: [RESEND PATCH v1 07/11] perf: hisi: Add support for Hisilicon SoC event counters
On Friday 11 November 2016 12:40 AM, Mark Rutland wrote:
On Thu, Nov 03, 2016 at 01:42:03AM -0400, Anurup M wrote:
+ do {
+ /* Get count from individual L3C banks and sum them up */
+ for (i = 0; i < num_banks; i++) {
+ total_raw_count += hisi_read_l3c_counter(l3c_hwmod_data,
+ idx, i);
+ }
+ prev_raw_count = local64_read(>prev_count);
+
+ /*
+* As prev_raw_count is updated with average value of
+* L3 cache banks, we multiply it by no of banks and
+* compute the delta
+*/
+ delta = (total_raw_count - (prev_raw_count * num_banks)) &
+ HISI_MAX_PERIOD;
+
+ local64_add(delta, >count);
+
+ /*
+* Divide by num of banks to get average count and
+* update prev_count with this value
+*/
+ avg_raw_count = total_raw_count / num_banks;
+ } while (local64_cmpxchg(
+>prev_count, prev_raw_count, avg_raw_count) !=
+prev_raw_count);
Please don't aggregate like this; expose separate PMUs instead.
This is racy, and by averaging and multiplying we're making up and/or
throwing away data.
[...]
I have some concerns or doubts regarding registering each L3 cache bank
as a separate PMU.
1) Each L3 cache PMU has total 22 statistics events. So if registered as
a separate PMU, will it not
create multiple entries (with same event names) in event listing for
multiple PMU's. Is there a way
I can avoid this? or this is acceptable?
Or is it acceptable to register as a single PMU and add a config
parameter in the event listing to
identify the L3 cache bank. ex: event name will appear as
"hisi_l3c2/read_allocate,bank=?/".
And user can choose count from bank 0x01 as -e
"hisi_l3c2/read_allocate,bank=0x01/"
2) The individual count from each L3 cache bank is not meaningful. Only
aggregate count is useful.
Which is the accepted way to handle such counters?
a) Register each PMU instance as in hardware and handle the aggregation
in user space.
b) Register as single PMU, handle aggregation in driver.
+ event_value = (val -
+ HISI_HWEVENT_L3C_READ_ALLOCATE);
+
+ /* Select the appropriate Event select register */
+ if (idx > 3)
+ reg_offset += 4;
+
+ /* Value to write to event type register */
+ val = event_value << (8 * idx);
+
Please add helpers for these, and explain *why* the transformations are
necessary.
Ok. shall add helpers.
+ /* Find the djtag Identifier of the Unit */
+ client = l3c_hwmod_data->client;
+
+ /*
+* Set the event in L3C_EVENT_TYPEx Register
+* for all L3C banks
+*/
As above, it seems like you should expose a separate PMU per bank
instead. That applies for all the other instances where you iterate over
banks.
[...]
+ for (i = 0; i < l3c_hwmod_data->l3c_hwcfg.num_banks; i++) {
+ module_id = l3c_hwmod_data->l3c_hwcfg.module_id[i];
+ cfg_en = l3c_hwmod_data->l3c_hwcfg.bank_cfgen[i];
+ ret = hisi_djtag_writereg(module_id,
+ cfg_en,
+ reg_offset,
+ value,
+ client);
+ if (!ret)
+ ret = value;
+ }
This is impossible to read. Please factor this into helpers such that
you don't need this amount of indentation.
Please do similarly elsewhere when you see this indentation pattern.
OK.
[...]
+static int hisi_l3c_get_event_idx(struct hisi_pmu *pl3c_pmu)
+{
+ struct hisi_l3c_data *l3c_hwmod_data = pl3c_pmu->hwmod_data;
+ int event_idx;
+
+ event_idx =
+ find_first_zero_bit(
+ l3c_hwmod_data->hisi_l3c_event_used_mask,
+pl3c_pmu->num_counters);
+
+ if (event_idx == HISI_MAX_CFG_L3C_CNTR)
+ return -EAGAIN;
+
+ __set_bit(event_idx,
+ l3c_hwmod_data->hisi_l3c_event_used_mask);
+
+ return event_idx;
+}
Please get rid of the weird hungarian notation (i.e. don't use 'p' as a
prefix for pointers), and use temporary variables consistently, e.g.
Ok.
static int hisi_l3c_get_event_idx(struct hisi_pmu *l3c_pmu)
{
struct hisi_l3c_data *l3c_hwmod_data = l3c_pmu->hwmod_data;
unsigned long *used_mask = l3c_hwmod_data->hisi_l3c_event_used_mask;
int num_counters = pl3c_pmu->num_counters
int idx;
idx = find_first_zero_bit(used_mas
Re: [RESEND PATCH v1 05/11] dt-bindings: perf: hisi: Add Devicetree bindings for Hisilicon SoC PMU
On Friday 11 November 2016 12:00 AM, Mark Rutland wrote: Hi, On Thu, Nov 03, 2016 at 01:42:01AM -0400, Anurup M wrote: 1) Device tree bindings for Hisilicon SoC PMU. 2) Add example for Hisilicon L3 cache, MN and DDRC PMU. Signed-off-by: Anurup M<anuru...@huawei.com> Signed-off-by: Shaokun Zhang<zhangshao...@hisilicon.com> --- .../devicetree/bindings/arm/hisilicon/pmu.txt | 127 + 1 file changed, 127 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/pmu.txt diff --git a/Documentation/devicetree/bindings/arm/hisilicon/pmu.txt b/Documentation/devicetree/bindings/arm/hisilicon/pmu.txt new file mode 100644 index 000..e7b35e0 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/pmu.txt @@ -0,0 +1,127 @@ +Hisilicon SoC hip05/06/07 ARMv8 PMU +=== + +The Hisilicon SoC chips like hip05/06/07 etc. consist of varous independent +system device PMU's such as L3 cache (L3C), Miscellaneous Nodes(MN) and DDR s/PMU's/PMUs/ OK. +comtroller. These PMU devices are independent and have hardware logic to s/comtroller/controller/ +gather statistics and performance information. + +HiSilicon SoC chip is encapsulated by multiple CPU and IO die's. The CPU die s/die's/dies/ OK. +is called as Super CPU cluster (SCCL) which includes 16 cpu-cores. Every SCCL +is further grouped as CPU clusters (CCL) which includes 4 cpu-cores each. +e.g. In the case of hip05/06/07, each SCCL has 1 L3 cache and 1 MN PMU device. + +The Hisilicon SoC PMU DT node bindigs for uncore PMU devices are as below. s/bindigs/bindings/ OK. Thanks. I shall make sure with spell checker before sending v2. +For PMU devices like L3 cache. MN etc. which are accessed using the djtag, +the parent node will be the djtag node of the corresponding CPU die(SCCL). + +For uncore PMU devices there are some common required properties as detailed +below. + +Required properties: + - compatible : This field contain two values. The first value is + always "hisilicon" and second value is the Module type as shown + in below examples: Just say: - Compatible: should contain one of: OK. + (a) "hisilicon,hisi-pmu-l3c-v1" for Hisilicon SoC L3C PMU + device (Version 1) + (b) "hisilicon,hisi-pmu-mn-v1" for Hisilicon SoC MN PMU + device (Version 1) + (c) "hisilicon,hisi-pmu-ddrc-v1" for Hisilicon SoC DDRC PMU + device (Version 1) + The hip05/06/07 chips have v1 hardware for L3C, MN and DDRC. + + - scl-id : The Super Cluster ID. This can be the ID of the CPU die + or IO die in the chip. What's this needed for? This is used as suffix to the PMU name. hisi_l3c. (hisi_l3c2 - for scl-id = 2). This is to identify the pmu correspond to which CPU die in the socket. + - num-events : No of events supported by this PMU device. + + - num-counters : No of hardware counters available for counting. This isn't probeable or well-known? My idea is to have the common properties of SoC PMU added here. The num-events, num-counters etc. So that handling can be made common in the driver. Is it not recommended? Please share your comments. + +L3 cache + +The L3 cache is dedicated for each SCCL and hence there are separate DT nodes +for L3 cache for each SCCL. For L3 cache PMU the additional required properties +are + - counter-reg : Counter register offset. + + - evtype-reg : Event select register offset. + + - evctrl-reg : Event counting control(LAUCTRL) register offset. Surely for a given revision of the chip these offsets are known? i.e. surely the compatible string implies specific offsets? + - event-en : Event enable value. Huh? As for the hip05/06 and 07 chips, the above four properties are same, I shall move them to the driver. The below two properties (module-id, cfgen-map) differs between chips hip05/06 and hip07. There were moved here so as to have minimal changes in driver across chips hip05/06/07. OR whether it is more recommended to have the of_device_id .data set accordingly for handling different chip versions? Please suggest. + - module-id : Module ID to input for djtag. This property is an array of + module_id for each L3 cache banks. + + - num-banks : Number of banks or instances of the device. What's a bank? Surely they have separate instances of the PMU? Yes each bank is a separate instance of PMU. If it is recommended to have each L3 cache bank registered as separate PMU with perf, then this property will be removed. What order are these in? The bank number will start from "1" till "4" for L3 cache as there are four banks in hip05/06/07 chips. + - cfgen-map : Config enable array to s
Re: [RESEND PATCH v1 02/11] dt-bindings: hisi: Add Hisilicon HiP05/06/07 Sysctrl and Djtag dts bindings
On Friday 11 November 2016 05:23 PM, Mark Rutland wrote:
On Fri, Nov 11, 2016 at 04:49:03PM +0530, Anurup M wrote:
On Thursday 10 November 2016 10:53 PM, Mark Rutland wrote:
On Thu, Nov 03, 2016 at 01:41:58AM -0400, Anurup M wrote:
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+Example:
+ /* for Hisilicon HiP05 djtag for CPU sysctrl */
+ djtag0: djtag@8001 {
+ compatible = "hisilicon,hip05-cpu-djtag-v1";
+ reg = <0x0 0x8001 0x0 0x1>;
+
+ /* For L3 cache PMU */
+ pmul3c0 {
+ compatible = "hisilicon,hisi-pmu-l3c-v1";
+ scl-id = <0x02>;
+ num-events = <0x16>;
+ num-counters = <0x08>;
+ module-id = <0x04>;
+ num-banks = <0x04>;
+ cfgen-map = <0x02 0x04 0x01 0x08>;
+ counter-reg = <0x170>;
+ evctrl-reg = <0x04>;
+ event-en = <0x100>;
+ evtype-reg = <0x140>;
+ };
This sub-node needs a binding document.
These properties are completely opaque
The L3 cache PMU bindings are defined @bindings/arm/hisilicon/pmu.txt.
Is it OK that I document here(hisilicon/djtag.txt), a reference to
the PMU bindings doc ?
At this point in the series, that file does not exist yet, and this is
an undocumented beinding.
Please introduce this sub-node long with the PMU bindings, later in the
series.
Thanks, I got your suggestion. Will add this later in series.
Thanks,
Mark.
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Re: [RESEND PATCH v1 05/11] dt-bindings: perf: hisi: Add Devicetree bindings for Hisilicon SoC PMU
On Thursday 03 November 2016 11:56 PM, Krzysztof Kozlowski wrote: On Thu, Nov 03, 2016 at 01:42:01AM -0400, Anurup M wrote: 1) Device tree bindings for Hisilicon SoC PMU. 2) Add example for Hisilicon L3 cache, MN and DDRC PMU. Get rid of this weird indentation in all patches. Thanks. I shall remove the TAB from the commit message in all patches. Signed-off-by: Anurup M <anuru...@huawei.com> Signed-off-by: Shaokun Zhang <zhangshao...@hisilicon.com> --- .../devicetree/bindings/arm/hisilicon/pmu.txt | 127 + 1 file changed, 127 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/pmu.txt diff --git a/Documentation/devicetree/bindings/arm/hisilicon/pmu.txt b/Documentation/devicetree/bindings/arm/hisilicon/pmu.txt new file mode 100644 index 000..e7b35e0 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/pmu.txt @@ -0,0 +1,127 @@ +Hisilicon SoC hip05/06/07 ARMv8 PMU +=== + +The Hisilicon SoC chips like hip05/06/07 etc. consist of varous independent +system device PMU's such as L3 cache (L3C), Miscellaneous Nodes(MN) and DDR +comtroller. These PMU devices are independent and have hardware logic to +gather statistics and performance information. + +HiSilicon SoC chip is encapsulated by multiple CPU and IO die's. The CPU die +is called as Super CPU cluster (SCCL) which includes 16 cpu-cores. Every SCCL +is further grouped as CPU clusters (CCL) which includes 4 cpu-cores each. +e.g. In the case of hip05/06/07, each SCCL has 1 L3 cache and 1 MN PMU device. + +The Hisilicon SoC PMU DT node bindigs for uncore PMU devices are as below. +For PMU devices like L3 cache. MN etc. which are accessed using the djtag, +the parent node will be the djtag node of the corresponding CPU die(SCCL). + +For uncore PMU devices there are some common required properties as detailed +below. + +Required properties: + - compatible : This field contain two values. The first value is + always "hisilicon" and second value is the Module type as shown + in below examples: Over-complicated sentence. Just: - compatible : One of: "hisilicon,hisi-pmu-l3c-v1" for Hisilicon SoC L3C PMU device (Version 1) ... ... Thanks. Shall refine it in next version. BTW, No need of CC-ing me. I am not a maintainer of relevant subsystems. Sure. Thanks, Anurup Best regards, Krzysztof -- To unsubscribe from this list: send the line "unsubscribe linux-doc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RESEND PATCH v1 10/11] perf: hisi: Support for Hisilicon DDRC PMU.
1. Add support for counting Hisilicon DDRC
statistics events in perf.
2. Support a total of 13 statistics events.
3. Events listed in /sys/devices//
Signed-off-by: Anurup M <anuru...@huawei.com>
Signed-off-by: Shaokun Zhang <zhangshao...@hisilicon.com>
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers/perf/hisilicon/hisi_uncore_ddrc.c | 444 ++
drivers/perf/hisilicon/hisi_uncore_ddrc.h | 73 +
3 files changed, 518 insertions(+), 1 deletion(-)
create mode 100644 drivers/perf/hisilicon/hisi_uncore_ddrc.c
create mode 100644 drivers/perf/hisilicon/hisi_uncore_ddrc.h
diff --git a/drivers/perf/hisilicon/Makefile b/drivers/perf/hisilicon/Makefile
index 8975104..8e9df2e 100644
--- a/drivers/perf/hisilicon/Makefile
+++ b/drivers/perf/hisilicon/Makefile
@@ -1 +1 @@
-obj-$(CONFIG_HISI_PMU) += hisi_uncore_pmu.o hisi_uncore_l3c.o hisi_uncore_mn.o
+obj-$(CONFIG_HISI_PMU) += hisi_uncore_pmu.o hisi_uncore_l3c.o hisi_uncore_mn.o
hisi_uncore_ddrc.o
diff --git a/drivers/perf/hisilicon/hisi_uncore_ddrc.c
b/drivers/perf/hisilicon/hisi_uncore_ddrc.c
new file mode 100644
index 000..b89a72e
--- /dev/null
+++ b/drivers/perf/hisilicon/hisi_uncore_ddrc.c
@@ -0,0 +1,444 @@
+/*
+ * HiSilicon SoC DDRC Hardware event counters support
+ *
+ * Copyright (C) 2016 Huawei Technologies Limited
+ * Author: Anurup M <anuru...@huawei.com>
+ *
+ * This code is based on the uncore PMU's like arm-cci and
+ * arm-ccn.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include "hisi_uncore_ddrc.h"
+
+static inline int hisi_ddrc_counter_valid(int idx, struct hisi_pmu *ddrc_pmu)
+{
+ return (idx >= 0 && idx < ddrc_pmu->num_counters);
+}
+
+static u32 hisi_ddrc_read32_relaxed(void __iomem *regs_base, u32 off)
+{
+ void __iomem *reg_addr = regs_base + off;
+
+ return readl_relaxed(reg_addr);
+}
+
+static void hisi_ddrc_write32(void __iomem *regs_base, u32 off, u32 val)
+{
+ void __iomem *reg_addr = regs_base + off;
+
+ writel(val, reg_addr);
+}
+
+static u32 hisi_read_ddrc_counter(struct hisi_ddrc_data *ddrc_hwmod_data,
+ unsigned long event_code, int idx)
+{
+ u32 value;
+ u32 reg_off;
+
+ reg_off = HISI_DDRC_FLUX_WR_REG_OFF + (event_code * 4);
+
+ value = hisi_ddrc_read32_relaxed(ddrc_hwmod_data->regs_base,
+ reg_off);
+ return value;
+}
+
+static u64 hisi_ddrc_event_update(struct perf_event *event,
+ struct hw_perf_event *hwc, int idx)
+{
+ struct hisi_pmu *ddrc_pmu = to_hisi_pmu(event->pmu);
+ struct hisi_ddrc_data *ddrc_hwmod_data;
+ u64 delta, prev_raw_count, new_raw_count = 0;
+
+ if (!hisi_ddrc_counter_valid(idx, ddrc_pmu)) {
+ dev_err(ddrc_pmu->dev,
+ "%s: Unsupported event index:%d!\n", __func__, idx);
+ return 0;
+ }
+
+ ddrc_hwmod_data = ddrc_pmu->hwmod_data;
+
+ /* Check if the DDRC data is initialized for this SCCL */
+ if (!ddrc_hwmod_data->regs_base) {
+ dev_err(ddrc_pmu->dev, "DDRC registers not mapped!\n");
+ return 0;
+ }
+
+ do {
+ prev_raw_count = local64_read(>prev_count);
+ new_raw_count =
+ hisi_read_ddrc_counter(ddrc_hwmod_data,
+ hwc->config_base, idx);
+ delta = (new_raw_count - prev_raw_count) &
+ HISI_MAX_PERIOD;
+
+ local64_add(delta, >count);
+ } while (local64_cmpxchg(
+ >prev_count, prev_raw_count, new_raw_count) !=
+ prev_raw_count);
+
+ return new_raw_count;
+}
+
+static u32 hisi_write_ddrc_counter(struct hisi_pmu *ddrc_pmu,
+ struct hw_perf_event *hwc, u32 value)
+{
+ struct hisi_ddrc_data *ddrc_hwmod_data = ddrc_pmu->hwmod_data;
+ u32 reg_off;
+ u32 event_code = hwc->config_base;
+
+ if (!(event_code >= HISI_HWEVENT_DDRC_FLUX_WR &&
+ event_code
[RESEND PATCH v1 08/11] perf: hisi: Add sysfs attributes for L3 cache(L3C) PMU
1. Add L3 caches events to /sys/devices/hisi_l3c2/events/
The events can be selected as shown in perf list
e.g.: For L3C_READ_ALLOCATE event for Super CPU cluster 2 the
event format is
-e "hisi_l3c2/read_allocate/"
2. Add cpu_mask attribute group for showing the available CPU
for counting.
Signed-off-by: Anurup M <anuru...@huawei.com>
Signed-off-by: Shaokun Zhang <zhangshao...@hisilicon.com>
---
drivers/perf/hisilicon/hisi_uncore_l3c.c | 57
drivers/perf/hisilicon/hisi_uncore_pmu.c | 40 ++
drivers/perf/hisilicon/hisi_uncore_pmu.h | 22
3 files changed, 119 insertions(+)
diff --git a/drivers/perf/hisilicon/hisi_uncore_l3c.c
b/drivers/perf/hisilicon/hisi_uncore_l3c.c
index f78f7b2..428fba0 100644
--- a/drivers/perf/hisilicon/hisi_uncore_l3c.c
+++ b/drivers/perf/hisilicon/hisi_uncore_l3c.c
@@ -436,6 +436,62 @@ static int init_hisi_l3c_data(struct device *dev,
return ret;
}
+static struct attribute *hisi_l3c_format_attr[] = {
+ HISI_PMU_FORMAT_ATTR(event, "config:0-11"),
+ NULL,
+};
+
+static struct attribute_group hisi_l3c_format_group = {
+ .name = "format",
+ .attrs = hisi_l3c_format_attr,
+};
+
+static struct attribute *hisi_l3c_events_attr[] = {
+ HISI_PMU_EVENT_ATTR_STR(read_allocate,
+ "event=0x0"),
+ HISI_PMU_EVENT_ATTR_STR(write_allocate,
+ "event=0x01"),
+ HISI_PMU_EVENT_ATTR_STR(read_noallocate,
+ "event=0x02"),
+ HISI_PMU_EVENT_ATTR_STR(write_noallocate,
+ "event=0x03"),
+ HISI_PMU_EVENT_ATTR_STR(read_hit, "event=0x04"),
+ HISI_PMU_EVENT_ATTR_STR(write_hit, "event=0x05"),
+ NULL,
+};
+
+static struct attribute_group hisi_l3c_events_group = {
+ .name = "events",
+ .attrs = hisi_l3c_events_attr,
+};
+
+static struct attribute *hisi_l3c_attrs[] = {
+ NULL,
+};
+
+struct attribute_group hisi_l3c_attr_group = {
+ .attrs = hisi_l3c_attrs,
+};
+
+static DEVICE_ATTR(cpumask, 0444, hisi_cpumask_sysfs_show, NULL);
+
+static struct attribute *hisi_l3c_cpumask_attrs[] = {
+ _attr_cpumask.attr,
+ NULL,
+};
+
+static const struct attribute_group hisi_l3c_cpumask_attr_group = {
+ .attrs = hisi_l3c_cpumask_attrs,
+};
+
+static const struct attribute_group *hisi_l3c_pmu_attr_groups[] = {
+ _l3c_attr_group,
+ _l3c_format_group,
+ _l3c_events_group,
+ _l3c_cpumask_attr_group,
+ NULL,
+};
+
static struct hisi_uncore_ops hisi_uncore_l3c_ops = {
.set_evtype = hisi_set_l3c_evtype,
.set_event_period = hisi_pmu_set_event_period,
@@ -496,6 +552,7 @@ static int hisi_pmu_l3c_dev_probe(struct hisi_djtag_client
*client)
.start = hisi_uncore_pmu_start,
.stop = hisi_uncore_pmu_stop,
.read = hisi_uncore_pmu_read,
+ .attr_groups = hisi_l3c_pmu_attr_groups,
};
ret = hisi_uncore_pmu_setup(pl3c_pmu, pl3c_pmu->name);
diff --git a/drivers/perf/hisilicon/hisi_uncore_pmu.c
b/drivers/perf/hisilicon/hisi_uncore_pmu.c
index 8d29fcc..d0a911a 100644
--- a/drivers/perf/hisilicon/hisi_uncore_pmu.c
+++ b/drivers/perf/hisilicon/hisi_uncore_pmu.c
@@ -26,6 +26,46 @@
#include
#include "hisi_uncore_pmu.h"
+/*
+ * PMU format attributes
+ */
+ssize_t hisi_format_sysfs_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct dev_ext_attribute *eattr;
+
+ eattr = container_of(attr, struct dev_ext_attribute,
+attr);
+ return sprintf(buf, "%s\n", (char *) eattr->var);
+}
+
+/*
+ * PMU event attributes
+ */
+ssize_t hisi_event_sysfs_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct perf_pmu_events_attr *pmu_attr =
+ container_of(attr, struct perf_pmu_events_attr, attr);
+
+ if (pmu_attr->event_str)
+ return sprintf(buf, "%s", pmu_attr->event_str);
+
+ return 0;
+}
+
+/*
+ * sysfs cpumask attributes
+ */
+ssize_t hisi_cpumask_sysfs_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct pmu *pmu = dev_get_drvdata(dev);
+ struct hisi_pmu *hisi_pmu = to_hisi_pmu(pmu);
+
+ return cpumap_print_to_pagebuf(true, buf, _pmu->cpu);
+}
+
/* djtag read interface - Call djtag driver to access SoC registers */
int hisi_djtag_readreg(int module_id, int bank, u32 offset,
struct hisi_djtag_client *client, u32 *pvalue)
diff --git a/drivers/perf/hisilicon/hisi_uncor
[RESEND PATCH v1 11/11] dts: arm64: hip06: Add Hisilicon SoC PMU support
1. Add nodes for hip06 L3 cache to support uncore events.
2. Add nodes for hip06 MN to support uncore events.
3. Add nodes for hip06 DDRC to support uncore events.
Signed-off-by: Anurup M <anuru...@huawei.com>
Signed-off-by: Shaokun Zhang <zhangshao...@hisilicon.com>
Signed-off-by: John Garry <john.ga...@huawei.com>
---
arch/arm64/boot/dts/hisilicon/hip06.dtsi | 116 +++
1 file changed, 116 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi
b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
index cb9e018..9ff3afe 100644
--- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
@@ -980,6 +980,122 @@
status = "disabled";
};
+ djtag0: djtag@6001 {
+ compatible = "hisilicon,hip06-cpu-djtag-v1";
+ reg = <0x0 0x6001 0x0 0x1>;
+
+ /* L3 cache for socket0 CPU die scl#2 */
+ pmul3c0 {
+ compatible = "hisilicon,hisi-pmu-l3c-v1";
+ scl-id = <0x02>;
+ num-events = <0x16>;
+ num-counters = <0x08>;
+ module-id = <0x04 0x04 0x04 0x04>;
+ num-banks = <0x04>;
+ cfgen-map = <0x02 0x04 0x01 0x08>;
+ counter-reg = <0x170>;
+ evctrl-reg = <0x04>;
+ event-en = <0x100>;
+ evtype-reg = <0x140>;
+ };
+
+ /* Miscellaneous node for socket0
+* CPU die scl#2
+*/
+ pmumn0 {
+ compatible = "hisilicon,hisi-pmu-mn-v1";
+ scl-id = <0x02>;
+ num-events = <0x09>;
+ num-counters = <0x04>;
+ module-id = <0x0b>;
+ cfgen-map = <0x01>;
+ counter-reg = <0x30>;
+ evctrl-reg = <0x40>;
+ event-en = <0x01>;
+ evtype-reg = <0x48>;
+ };
+ };
+
+ djtag1: djtag@4001 {
+ compatible = "hisilicon,hip06-cpu-djtag-v1";
+ reg = <0x0 0x4001 0x0 0x1>;
+
+ /* L3 cache for socket0 CPU die scl#1 */
+ pmul3c1 {
+ compatible = "hisilicon,hisi-pmu-l3c-v1";
+ scl-id = <0x01>;
+ num-events = <0x16>;
+ num-counters = <0x08>;
+ module-id = <0x04 0x04 0x04 0x04>;
+ num-banks = <0x04>;
+ cfgen-map = <0x02 0x04 0x01 0x08>;
+ counter-reg = <0x170>;
+ evctrl-reg = <0x04>;
+ event-en = <0x100>;
+ evtype-reg = <0x140>;
+ };
+
+ /* Miscellaneous node for socket0
+* CPU die scl#1
+*/
+ pmumn1 {
+ compatible = "hisilicon,hisi-pmu-mn-v1";
+ scl-id = <0x01>;
+ num-events = <0x09>;
+ num-counters = <0x04>;
+ module-id = <0x0b>;
+ cfgen-map = <0x01>;
+ counter-reg = <0x30>;
+ evctrl-reg = <0x40>;
+ event-en = <0x01>;
+ evtype-reg = <0x48>;
+ };
+ };
+
+ /* DDRC for CPU die scl #1 Channel #0 */
+ pmu_sccl0_ddrc0: pmu_ddrc0@40348000 {
+ compatible = "hisilicon,hisi-pmu-ddrc-v1";
+ scl-id = <0x01>;
+ ch-id = <0x0>;
+ num-events = <0x0d>;
+ num-counters = <0x04>;
+ reg = <0x0 0x40348000 0x0 0x1>; /* TOTEMA DDRC0 */
+ status = "oka
[RESEND PATCH v1 09/11] perf: hisi: Miscellanous node(MN) event counting in perf
From: Shaokun Zhang <zhangshao...@hisilicon.com>
1. Add support to count MN hardware events.
2. Mn events are listed in sysfs at /sys/devices/hisi_mn2/events/
The events can be selected as shown in perf list
e.g.: For MN_READ_REQUEST event for Super CPU cluster 2 the
event format is
-e "hisi_mn2/read_req/"
Signed-off-by: Shaokun Zhang <zhangshao...@hisilicon.com>
Signed-off-by: Anurup M <anuru...@huawei.com>
---
drivers/perf/hisilicon/Makefile | 2 +-
drivers/perf/hisilicon/hisi_uncore_mn.c | 571
drivers/perf/hisilicon/hisi_uncore_mn.h | 68
3 files changed, 640 insertions(+), 1 deletion(-)
create mode 100644 drivers/perf/hisilicon/hisi_uncore_mn.c
create mode 100644 drivers/perf/hisilicon/hisi_uncore_mn.h
diff --git a/drivers/perf/hisilicon/Makefile b/drivers/perf/hisilicon/Makefile
index e1766cf..8975104 100644
--- a/drivers/perf/hisilicon/Makefile
+++ b/drivers/perf/hisilicon/Makefile
@@ -1 +1 @@
-obj-$(CONFIG_HISI_PMU) += hisi_uncore_pmu.o hisi_uncore_l3c.o
+obj-$(CONFIG_HISI_PMU) += hisi_uncore_pmu.o hisi_uncore_l3c.o hisi_uncore_mn.o
diff --git a/drivers/perf/hisilicon/hisi_uncore_mn.c
b/drivers/perf/hisilicon/hisi_uncore_mn.c
new file mode 100644
index 000..920e346
--- /dev/null
+++ b/drivers/perf/hisilicon/hisi_uncore_mn.c
@@ -0,0 +1,571 @@
+/*
+ * HiSilicon SoC MN Hardware event counters support
+ *
+ * Copyright (C) 2016 Huawei Technologies Limited
+ * Author: Shaokun Zhang <zhangshao...@hisilicon.com>
+ *
+ * This code is based on the uncore PMU's like arm-cci and
+ * arm-ccn.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+#include
+#include
+#include
+#include
+#include "hisi_uncore_mn.h"
+
+static inline int hisi_mn_counter_valid(int idx)
+{
+ return (idx >= HISI_IDX_MN_COUNTER0 &&
+ idx <= HISI_IDX_MN_COUNTER_MAX);
+}
+
+static u32 hisi_read_mn_counter(struct hisi_mn_data *mn_hwmod_data,
+ int idx)
+{
+ u32 module_id = mn_hwmod_data->mn_hwcfg.module_id;
+ struct hisi_djtag_client *client = mn_hwmod_data->client;
+ u32 cfg_en, reg_offset, value;
+
+ cfg_en = mn_hwmod_data->mn_hwcfg.bank_cfgen;
+ reg_offset = mn_hwmod_data->mn_hwcfg.counter_reg0_off + (idx * 4);
+
+ hisi_djtag_readreg(module_id,
+ cfg_en,
+ reg_offset,
+ client, );
+
+ return value;
+}
+
+static u64 hisi_mn_event_update(struct perf_event *event,
+ struct hw_perf_event *hwc, int idx)
+{
+ struct hisi_pmu *pmn_pmu = to_hisi_pmu(event->pmu);
+ struct hisi_mn_data *mn_hwmod_data;
+ u64 delta, prev_raw_count, new_raw_count = 0;
+ u32 cfg_en;
+
+ if (!hisi_mn_counter_valid(idx)) {
+ dev_err(pmn_pmu->dev,
+ "Unsupported event index:%d!\n", idx);
+ return 0;
+ }
+
+ mn_hwmod_data = pmn_pmu->hwmod_data;
+
+ /* Check if the MN data is initialized for this SCCL */
+ if (!mn_hwmod_data->client) {
+ dev_err(pmn_pmu->dev,
+ "SCL=%d not initialized!\n", pmn_pmu->scl_id);
+ return 0;
+ }
+
+ cfg_en = mn_hwmod_data->mn_hwcfg.bank_cfgen;
+
+ do {
+ prev_raw_count = local64_read(>prev_count);
+ new_raw_count =
+ hisi_read_mn_counter(mn_hwmod_data, idx);
+ delta = (new_raw_count - prev_raw_count) &
+ HISI_MAX_PERIOD;
+
+ local64_add(delta, >count);
+ } while (local64_cmpxchg(
+ >prev_count, prev_raw_count, new_raw_count) !=
+ prev_raw_count);
+
+ return new_raw_count;
+}
+
+static void hisi_set_mn_evtype(struct hisi_pmu *pmn_pmu, int idx, u32 val)
+{
+ struct hisi_djtag_client *client;
+ struct hisi_mn_data *mn_hwmod_data = pmn_pmu->hwmod_data;
+ u32 reg_offset = mn_hwmod_data->mn_hwcfg.evtype_reg0_off;
+ u32 module_id = mn_hwmod_data->mn_hwcfg.module_id;
+ u32 cfg_e
[RESEND PATCH v1 03/11] drivers: soc: hisi: Add support for Hisilicon Djtag driver
From: Tan Xiaojun <tanxiao...@huawei.com> The Hisilicon Djtag is an independent component which connects with some other components in the SoC by Debug Bus. This driver can be configured to access the registers of connecting components (like L3 cache) during real time debugging. Signed-off-by: Tan Xiaojun <tanxiao...@huawei.com> Signed-off-by: John Garry <john.ga...@huawei.com> Signed-off-by: Anurup M <anuru...@huawei.com> --- drivers/soc/Kconfig | 1 + drivers/soc/Makefile| 1 + drivers/soc/hisilicon/Kconfig | 12 + drivers/soc/hisilicon/Makefile | 1 + drivers/soc/hisilicon/djtag.c | 639 include/linux/soc/hisilicon/djtag.h | 38 +++ 6 files changed, 692 insertions(+) create mode 100644 drivers/soc/hisilicon/Kconfig create mode 100644 drivers/soc/hisilicon/Makefile create mode 100644 drivers/soc/hisilicon/djtag.c create mode 100644 include/linux/soc/hisilicon/djtag.h diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index e6e90e8..89ecd42 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -3,6 +3,7 @@ menu "SOC (System On Chip) specific Drivers" source "drivers/soc/bcm/Kconfig" source "drivers/soc/fsl/qbman/Kconfig" source "drivers/soc/fsl/qe/Kconfig" +source "drivers/soc/hisilicon/Kconfig" source "drivers/soc/mediatek/Kconfig" source "drivers/soc/qcom/Kconfig" source "drivers/soc/rockchip/Kconfig" diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index 50c23d0..ce2beb5 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -6,6 +6,7 @@ obj-y += bcm/ obj-$(CONFIG_ARCH_DOVE)+= dove/ obj-$(CONFIG_MACH_DOVE)+= dove/ obj-y += fsl/ +obj-$(CONFIG_ARCH_HISI)+= hisilicon/ obj-$(CONFIG_ARCH_MEDIATEK)+= mediatek/ obj-$(CONFIG_ARCH_QCOM)+= qcom/ obj-$(CONFIG_ARCH_RENESAS) += renesas/ diff --git a/drivers/soc/hisilicon/Kconfig b/drivers/soc/hisilicon/Kconfig new file mode 100644 index 000..6dd4ba0 --- /dev/null +++ b/drivers/soc/hisilicon/Kconfig @@ -0,0 +1,12 @@ +# +# Hisilicon SoC drivers +# +config HISI_DJTAG + bool "Hisilicon Djtag Support" + depends on ARCH_HISI || COMPILE_TEST + help + Say y here to enable the Hisilicon Djtag support. It is + an independent component which connects with some other + components in the SoC by Debug Bus. This driver can be + configured to access the registers of connecting + components during real time debugging. diff --git a/drivers/soc/hisilicon/Makefile b/drivers/soc/hisilicon/Makefile new file mode 100644 index 000..35a7b4b --- /dev/null +++ b/drivers/soc/hisilicon/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_HISI_DJTAG) += djtag.o diff --git a/drivers/soc/hisilicon/djtag.c b/drivers/soc/hisilicon/djtag.c new file mode 100644 index 000..a87c8b6 --- /dev/null +++ b/drivers/soc/hisilicon/djtag.c @@ -0,0 +1,639 @@ +/* + * Driver for Hisilicon Djtag r/w via System Controller. + * + * Copyright (C) 2016 Hisilicon Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define SC_DJTAG_TIMEOUT 10 /* 100ms */ + +/* for djtag v1 */ +#define SC_DJTAG_MSTR_EN 0x6800 +#define DJTAG_NOR_CFG BIT(1) /* accelerate R,W */ +#define DJTAG_MSTR_EN BIT(0) +#define SC_DJTAG_MSTR_START_EN 0x6804 +#define DJTAG_MSTR_START_EN0x1 +#define SC_DJTAG_DEBUG_MODULE_SEL 0x680c +#define SC_DJTAG_MSTR_WR 0x6810 +#define DJTAG_MSTR_W 0x1 +#define DJTAG_MSTR_R 0x0 +#define SC_DJTAG_CHAIN_UNIT_CFG_EN 0x6814 +#define CHAIN_UNIT_CFG_EN 0x +#define SC_DJTAG_MSTR_ADDR 0x6818 +#define SC_DJTAG_MSTR_DATA 0x681c +#define SC_DJTAG_RD_DATA_BASE 0xe800 + +/* for djtag v2 */ +#define SC_DJTAG_SEC_ACC_EN_EX 0xd800 +#define DJTAG_SEC_ACC_EN_EX0x1 +#define SC_DJTAG_MSTR_CFG_EX 0xd818 +#define DJTAG_MSTR_RW_SHIFT_EX 29 +#define DJTAG_MSTR_RD_EX (0x0 << DJTAG_MSTR_RW_SHIFT_EX) +#define DJTAG_MSTR_WR_EX (0x1 << DJTAG_MSTR_RW_SHIFT_EX) +#define DEBUG_MODULE_SEL_SHIFT_EX 16 +#define CHAIN_UNIT_CFG_EN_EX 0x +#define SC_DJTAG_MSTR_ADDR_EX 0xd810 +#define SC_DJTAG_MSTR_DATA_EX 0xd814 +#define SC_DJTAG_MSTR_START_EN_EX 0xd81c +#define DJTAG_MSTR_START_EN_EX
[RESEND PATCH v1 04/11] Documentation: perf: hisi: Documentation for HIP05/06/07 PMU event counting.
Documentation for perf usage and Hisilicon SoC PMU uncore events. The Hisilicon SOC has event counters for hardware modules like L3 cache, Miscellaneous node, DDR cntroller etc. These events are all uncore. Signed-off-by: Anurup M <anuru...@huawei.com> Signed-off-by: Shaokun Zhang <zhangshao...@hisilicon.com> --- Documentation/perf/hisi-pmu.txt | 80 + 1 file changed, 80 insertions(+) create mode 100644 Documentation/perf/hisi-pmu.txt diff --git a/Documentation/perf/hisi-pmu.txt b/Documentation/perf/hisi-pmu.txt new file mode 100644 index 000..670a9df --- /dev/null +++ b/Documentation/perf/hisi-pmu.txt @@ -0,0 +1,80 @@ +Hisilicon SoC PMU (Performance Monitoring Unit) + +The Hisilicon SoC hip05/06/07 chips consist of varous independent system +device PMU's such as L3 cache(L3C), Miscellaneous Nodes(MN) and DDR +controllers. These PMU devices are independent and have hardware logic to +gather statistics and performance information. + +Hip0x chips are encapsulated by multiple CPU and IO die's. The CPU die is +called as Super CPU cluster (SCCL) which includes 16 cpu-cores. Every SCCL +is further grouped as CPU clusters (CCL) which includes 4 cpu-cores each. +Each SCCL has 1 L3 cache and 1 MN units. + +The L3 cache is shared by all CPU cores in a CPU die. The L3C has four banks +(or instances). Each bank or instance of L3C has Eight 32-bit counter +registers. The hip05/06 chip L3 cache has 22 statistics events. The hip07 +chip has 66 statistics events. These events are very useful for debugging. + +The MN module is also shared by all CPU cores in a CPU die. It receives +barriers and DVM(Distributed Virtual Memory) messages from cpu or smmu, and +perform the required actions and return response messages. These events are +very useful for debugging. The MN has total 9 statistics events and support +four 32-bit counter registers in hip05/06/07 chips. + +The DDR conroller supports various statistics events. Every SCCL has fot 2 +DDR channels and hence 2 DDR controllers. The Hip05/06/07 has support for a +total of 13 statistics events. + +There is no memory mapping for L3 cache and MN registers. It can be accessed +by using the Hisilicon djtag interface. The Djtag in a SCCL is an independent +module which connects with some modules in the SoC by Debug Bus. + +Hisilicon SoC (hip05/06/07) PMU driver +-- +The hip0x PMU driver shall register perf PMU drivers like L3 cache, MN, DDRC +etc. +Separate PMU shall be registered for L3 cache and MN for each Super CPU +cluster. +For DRR controller separate PMU shall be registered for each channel in a +Super CPU cluster. + +The available events and configuration options shall be described in the sysfs. +The "perf list" shall list the available events from sysfs. +eg. hisi_l3c2/read_allocate/ [kernel PMU event] + +The Super Cluster ID will be the number suffix to PMU name +e.g. hisi_l3c2. Here Super cluster ID is 2 and so hisi_l3c2/read_allocate +is the event for read_allocate of SCCL #2. + +For DDRC the channel number will be suffix at the end. +eg: hisi_ddrc2_0/flux_read/. Here Super cluster ID is 2 and the channel number +is 0 for the event flux_read. + +The event code is represented by 12 bits. + i) event 0-11 + The event code will be represented using the LSB 12 bits. + +The driver also provides a "cpumask" sysfs attribute, which shows the CPU core +ID used to count the uncore PMU event. + +Example usage of perf: +$# perf list +hisi_l3c2/read_hit/ [kernel PMU event] +hisi_l3c2/write_hit/ [kernel PMU event] +-- +hisi_l3c1/read_hit/ [kernel PMU event] +hisi_l3c1/write_hit/ [kernel PMU event] +-- +hisi_mn2/read_req/ [kernel PMU event] +hisi_mn2/write_req/ [kernel PMU event] +-- +hisi_ddrc2_0/flux_read/ [kernel PMU event] +-- + +$# perf stat -a -e hisi_l3c2/read_allocate/ sleep 5 + +The current driver doesnot support sampling. so "perf record" is unsupported. +Also attach to a task is unsupported as the events are all uncore. + +Note: Please contact the maintainer for a complete list of events supported for +the PMU devices in the SoC and its information if needed. -- 2.1.4 -- To unsubscribe from this list: send the line "unsubscribe linux-doc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RESEND PATCH v1 07/11] perf: hisi: Add support for Hisilicon SoC event counters
1. Hip05/06/07 uncore PMU to support different hardware
event counters.
2. Hisilicon PMU shall use the DJTAG hardware interface
to access hardware event counters and configuration
register.
3. Routines to initialize and setup PMU.
4. Routines to enable/disable/add/del/start/stop hardware
event counting.
5. Add support to count L3 cache hardware events.
Signed-off-by: Anurup M <anuru...@huawei.com>
Signed-off-by: Shaokun Zhang <zhangshao...@hisilicon.com>
Signed-off-by: John Garry <john.ga...@huawei.com>
---
drivers/perf/Makefile| 1 +
drivers/perf/hisilicon/Makefile | 1 +
drivers/perf/hisilicon/hisi_uncore_l3c.c | 571 +++
drivers/perf/hisilicon/hisi_uncore_l3c.h | 67
drivers/perf/hisilicon/hisi_uncore_pmu.c | 331 ++
drivers/perf/hisilicon/hisi_uncore_pmu.h | 108 ++
6 files changed, 1079 insertions(+)
create mode 100644 drivers/perf/hisilicon/Makefile
create mode 100644 drivers/perf/hisilicon/hisi_uncore_l3c.c
create mode 100644 drivers/perf/hisilicon/hisi_uncore_l3c.h
create mode 100644 drivers/perf/hisilicon/hisi_uncore_pmu.c
create mode 100644 drivers/perf/hisilicon/hisi_uncore_pmu.h
diff --git a/drivers/perf/Makefile b/drivers/perf/Makefile
index b116e98..061f229 100644
--- a/drivers/perf/Makefile
+++ b/drivers/perf/Makefile
@@ -1,2 +1,3 @@
obj-$(CONFIG_ARM_PMU) += arm_pmu.o
obj-$(CONFIG_XGENE_PMU) += xgene_pmu.o
+obj-$(CONFIG_HISI_PMU) += hisilicon/
diff --git a/drivers/perf/hisilicon/Makefile b/drivers/perf/hisilicon/Makefile
new file mode 100644
index 000..e1766cf
--- /dev/null
+++ b/drivers/perf/hisilicon/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_HISI_PMU) += hisi_uncore_pmu.o hisi_uncore_l3c.o
diff --git a/drivers/perf/hisilicon/hisi_uncore_l3c.c
b/drivers/perf/hisilicon/hisi_uncore_l3c.c
new file mode 100644
index 000..f78f7b2
--- /dev/null
+++ b/drivers/perf/hisilicon/hisi_uncore_l3c.c
@@ -0,0 +1,571 @@
+/*
+ * HiSilicon SoC L3C Hardware event counters support
+ *
+ * Copyright (C) 2016 Huawei Technologies Limited
+ * Author: Anurup M <anuru...@huawei.com>
+ *
+ * This code is based on the uncore PMU's like arm-cci and
+ * arm-ccn.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+#include
+#include
+#include
+#include
+#include "hisi_uncore_l3c.h"
+
+static inline int hisi_l3c_counter_valid(int idx)
+{
+ return (idx >= HISI_IDX_L3C_COUNTER0 &&
+ idx <= HISI_IDX_L3C_COUNTER_MAX);
+}
+
+static u32 hisi_read_l3c_counter(struct hisi_l3c_data *l3c_hwmod_data,
+ int cntr_idx, int bank_idx)
+{
+ struct hisi_djtag_client *client = l3c_hwmod_data->client;
+ u32 module_id = l3c_hwmod_data->l3c_hwcfg.module_id[bank_idx];
+ u32 cfg_en = l3c_hwmod_data->l3c_hwcfg.bank_cfgen[bank_idx];
+ u32 reg_offset, value;
+
+ reg_offset = l3c_hwmod_data->l3c_hwcfg.counter_reg0_off +
+ (cntr_idx * 4);
+
+ hisi_djtag_readreg(module_id, cfg_en, reg_offset, client, );
+
+ return value;
+}
+
+static u64 hisi_l3c_event_update(struct perf_event *event,
+ struct hw_perf_event *hwc, int idx)
+{
+ struct hisi_pmu *pl3c_pmu = to_hisi_pmu(event->pmu);
+ struct hisi_l3c_data *l3c_hwmod_data = pl3c_pmu->hwmod_data;
+ u64 delta, prev_raw_count, total_raw_count = 0, avg_raw_count = 0;
+ u32 num_banks = l3c_hwmod_data->l3c_hwcfg.num_banks;
+ int i;
+
+ if (!hisi_l3c_counter_valid(idx)) {
+ dev_err(pl3c_pmu->dev, "Unsupported event index:%d!\n", idx);
+ return 0;
+ }
+
+ /* Check if the L3C data is initialized for this SCCL */
+ if (!l3c_hwmod_data->client) {
+ dev_err(pl3c_pmu->dev, "SCL=%d not initialized!\n",
+ pl3c_pmu->scl_id);
+ return 0;
+ }
+
+ do {
+ /* Get count from individual L3C banks and sum them up */
+ for (i = 0; i < num_banks; i++) {
+ total_raw_count += hisi_read_l3c_counter(l3c_hwmod_data,
+
[RESEND PATCH v1 05/11] dt-bindings: perf: hisi: Add Devicetree bindings for Hisilicon SoC PMU
1) Device tree bindings for Hisilicon SoC PMU.
2) Add example for Hisilicon L3 cache, MN and DDRC PMU.
Signed-off-by: Anurup M <anuru...@huawei.com>
Signed-off-by: Shaokun Zhang <zhangshao...@hisilicon.com>
---
.../devicetree/bindings/arm/hisilicon/pmu.txt | 127 +
1 file changed, 127 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/pmu.txt
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/pmu.txt
b/Documentation/devicetree/bindings/arm/hisilicon/pmu.txt
new file mode 100644
index 000..e7b35e0
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/hisilicon/pmu.txt
@@ -0,0 +1,127 @@
+Hisilicon SoC hip05/06/07 ARMv8 PMU
+===
+
+The Hisilicon SoC chips like hip05/06/07 etc. consist of varous independent
+system device PMU's such as L3 cache (L3C), Miscellaneous Nodes(MN) and DDR
+comtroller. These PMU devices are independent and have hardware logic to
+gather statistics and performance information.
+
+HiSilicon SoC chip is encapsulated by multiple CPU and IO die's. The CPU die
+is called as Super CPU cluster (SCCL) which includes 16 cpu-cores. Every SCCL
+is further grouped as CPU clusters (CCL) which includes 4 cpu-cores each.
+e.g. In the case of hip05/06/07, each SCCL has 1 L3 cache and 1 MN PMU device.
+
+The Hisilicon SoC PMU DT node bindigs for uncore PMU devices are as below.
+For PMU devices like L3 cache. MN etc. which are accessed using the djtag,
+the parent node will be the djtag node of the corresponding CPU die(SCCL).
+
+For uncore PMU devices there are some common required properties as detailed
+below.
+
+Required properties:
+ - compatible : This field contain two values. The first value is
+ always "hisilicon" and second value is the Module type as shown
+ in below examples:
+ (a) "hisilicon,hisi-pmu-l3c-v1" for Hisilicon SoC L3C PMU
+ device (Version 1)
+ (b) "hisilicon,hisi-pmu-mn-v1" for Hisilicon SoC MN PMU
+ device (Version 1)
+ (c) "hisilicon,hisi-pmu-ddrc-v1" for Hisilicon SoC DDRC PMU
+ device (Version 1)
+ The hip05/06/07 chips have v1 hardware for L3C, MN and DDRC.
+
+ - scl-id : The Super Cluster ID. This can be the ID of the CPU die
+ or IO die in the chip.
+
+ - num-events : No of events supported by this PMU device.
+
+ - num-counters : No of hardware counters available for counting.
+
+L3 cache
+
+The L3 cache is dedicated for each SCCL and hence there are separate DT nodes
+for L3 cache for each SCCL. For L3 cache PMU the additional required properties
+are
+ - counter-reg : Counter register offset.
+
+ - evtype-reg : Event select register offset.
+
+ - evctrl-reg : Event counting control(LAUCTRL) register offset.
+
+ - event-en : Event enable value.
+
+ - module-id : Module ID to input for djtag. This property is an array of
+ module_id for each L3 cache banks.
+
+ - num-banks : Number of banks or instances of the device.
+
+ - cfgen-map : Config enable array to select the bank.
+
+Miscellaneous Node
+---
+The MN is dedicated for each SCCL and hence there are separate DT nodes for MN
+for each SCCL. For MN PMU the additional required properties are
+ - counter-reg : Counter register offset.
+
+ - evtype-reg : Event select register offset.
+
+ - evctrl-reg : Event counting control register offset.
+
+ - module-id : Module ID to input for djtag. As MN doesnot have multiple
banks
+ this property is a single value.
+
+ - cfgen-map : Config enable to select the bank. For MN it is a single
value
+
+ - event-en : Event enable value.
+
+Example:
+
+ djtag0: djtag@0 {
+ compatible = "hisilicon,hip05-cpu-djtag-v1";
+ pmul3c0 {
+ compatible = "hisilicon,hisi-pmu-l3c-v1";
+ scl-id = <0x02>;
+ num-events = <0x16>;
+ num-counters = <0x08>;
+ module-id = <0x04 0x04 0x04 0x04>;
+ num-banks = <0x04>;
+ cfgen-map = <0x02 0x04 0x01 0x08>;
+ counter-reg = <0x170>;
+ evctrl-reg = <0x04>;
+ event-en = <0x100>;
+ evtype-reg = <0x140>;
+ };
+
+ pmumn0 {
+ compatible = "hisilicon,hisi-pmu-mn-v1";
+ scl-id = <0x02>;
+ num-events = <0x09>;
+ num-counters = <0x04>;
+
[RESEND PATCH v1 02/11] dt-bindings: hisi: Add Hisilicon HiP05/06/07 Sysctrl and Djtag dts bindings
From: Tan Xiaojun <tanxiao...@huawei.com>
1) Add Hisilicon HiP05/06/07 CPU and ALGSUB system controller dts
bindings.
2) Add Hisilicon Djtag dts binding.
Signed-off-by: Tan Xiaojun <tanxiao...@huawei.com>
Signed-off-by: Anurup M <anuru...@huawei.com>
---
.../bindings/arm/hisilicon/hisilicon.txt | 82 ++
1 file changed, 82 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
index 7df79a7..341cbb9 100644
--- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
@@ -270,3 +270,85 @@ Required Properties:
[1]: bootwrapper size
[2]: relocation physical address
[3]: relocation size
+
+---
+The Hisilicon Djtag in CPU die is an independent component which connects with
+some other components in the SoC by Debug Bus. This driver can be configured
+to access the registers of connecting components (like L3 cache, l3 cache PMU
+ etc.) during real time debugging by sysctrl. These components appear as child
+nodes of djtag.
+
+The Hip05/06/07 CPU system controller(sysctrl) support to manage some important
+components (such as clock, reset, soft reset, secure debugger, etc.).
+The CPU sysctrl registers in hip05/06/07 doesnot use syscon but will be mapped
+by djtag driver for use by connecting components.
+
+Hisilicon HiP05 CPU system controller
+Required properties:
+ - compatible : "hisilicon,hip05-cpu-djtag-v1"
+ - reg : Register address and size
+
+Hisilicon HiP06 djtag for CPU sysctrl
+Required properties:
+- compatible : "hisilicon,hip06-sysctrl", "syscon", "simple-mfd";
+- reg : Register address and size
+- djtag :
+ - compatible : "hisilicon,hip06-cpu-djtag-v1"
+ - reg : Register address and size
+
+Hisilicon HiP07 djtag for CPU sysctrl
+Required properties:
+ - compatible : "hisilicon,hip07-cpu-djtag-v2"
+ - reg : Register address and size
+
+Example:
+ /* for Hisilicon HiP05 djtag for CPU sysctrl */
+ djtag0: djtag@8001 {
+ compatible = "hisilicon,hip05-cpu-djtag-v1";
+ reg = <0x0 0x8001 0x0 0x1>;
+
+ /* For L3 cache PMU */
+ pmul3c0 {
+ compatible = "hisilicon,hisi-pmu-l3c-v1";
+ scl-id = <0x02>;
+ num-events = <0x16>;
+ num-counters = <0x08>;
+ module-id = <0x04>;
+ num-banks = <0x04>;
+ cfgen-map = <0x02 0x04 0x01 0x08>;
+ counter-reg = <0x170>;
+ evctrl-reg = <0x04>;
+ event-en = <0x100>;
+ evtype-reg = <0x140>;
+ };
+ };
+
+---
+The Hisilicon HiP05/06/07 ALGSUB system controller(sysctrl) is in IO die
+of SoC. It has a similar function as the Hisilicon HiP05/06/07 CPU system
+controller in CPU die and it manage different components, like RSA, etc.
+The Hisilicon Djtag in IO die has a similar function as in CPU die and maps
+the sysctrl registers for use by connecting components.
+All connecting components shall appear as child nodes of djtag.
+
+Hisilicon HiP05 djtag for ALGSUB sysctrl
+Required properties:
+ - compatible : "hisilicon,hip05-io-djtag-v1"
+ - reg : Register address and size
+
+Hisilicon HiP06 djtag for ALGSUB sysctrl
+Required properties:
+ - compatible : "hisilicon,hip06-io-djtag-v2"
+ - reg : Register address and size
+
+Hisilicon HiP07 djtag for ALGSUB sysctrl
+Required properties:
+ - compatible : "hisilicon,hip07-io-djtag-v2"
+ - reg : Register address and size
+
+Example:
+ /* for Hisilicon HiP05 djtag for alg sysctrl */
+ djtag0: djtag@d000 {
+ compatible = "hisilicon,hip05-io-djtag-v1";
+ reg = <0x0 0xd000 0x0 0x1>;
+ };
--
2.1.4
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[RESEND PATCH v1 06/11] perf: hisi: Update Kconfig for Hisilicon PMU support
1. Update Kconfig for Hip05/06/07 PMU support. Signed-off-by: Anurup M <anuru...@huawei.com> Signed-off-by: Shaokun Zhang <zhangshao...@hisilicon.com> Signed-off-by: John Garry <john.ga...@huawei.com> --- drivers/perf/Kconfig | 9 + 1 file changed, 9 insertions(+) diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig index 4d5c5f9..da8dd97 100644 --- a/drivers/perf/Kconfig +++ b/drivers/perf/Kconfig @@ -19,4 +19,13 @@ config XGENE_PMU help Say y if you want to use APM X-Gene SoC performance monitors. +config HISI_PMU + bool "Enable hardware event counter support for HiSilicon SoC" + depends on HW_PERF_EVENTS && ARM64 + depends on HISI_DJTAG + help + Enable hardware event counter support for hardware event counters + in Hisilicon hip05/06/07 SoC. The hardware modules like L3C, MN and + DDRC have hardware events and counters. + endmenu -- 2.1.4 -- To unsubscribe from this list: send the line "unsubscribe linux-doc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RESEND PATCH v1 01/11] arm64: MAINTAINERS: hisi: Add hisilicon SoC PMU support
Add support for Hisilicon SoC hardware event counters for HIP05/06/07 chip versions. Signed-off-by: Anurup M <anuru...@huawei.com> --- MAINTAINERS | 10 ++ 1 file changed, 10 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index b224caa..839abc8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5725,6 +5725,16 @@ S: Maintained F: drivers/net/ethernet/hisilicon/ F: Documentation/devicetree/bindings/net/hisilicon*.txt +HISILICON SOC PMU +M: Anurup M <anuru...@huawei.com> +W: http://www.hisilicon.com +S: Supported +F: drivers/perf/hisilicon/* +F: drivers/soc/hisilicon/djtag.c +F: include/linux/soc/hisilicon/djtag.h +F: Documentation/perf/hisi-pmu.txt +F: Documentation/devicetree/bindings/arm/hisilicon/pmu.txt + HISILICON ROCE DRIVER M: Lijun Ou <ouli...@huawei.com> M: Wei Hu(Xavier) <xavier.hu...@huawei.com> -- 2.1.4 -- To unsubscribe from this list: send the line "unsubscribe linux-doc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RESEND PATCH v1 00/11] perf: arm64: Support for Hisilicon SoC Hardware event counters
[Resending after adding maintainers in --to] Provide Support for Hisilicon SoC(Hip05/06/07) Hardware event counters. The Hisilicon SoC Hip0x series has many uncore or non-CPU performance events and counters units. This initial patch series is implemented refering to arm-cci, Intel/AMD uncore and also the cavium thunderX and xgene uncore pmu patches. Support for Hisilicon L3 cache(L3C), MN and DDR hardware events and counters are added in this implementation. The Hisilicon uncore PMUs can be found under /sys/bus/event_source/devices. The counters are exported via sysfs in the corresponding events files under the PMU directory so the perf tool can list the event names. ToDo: 1) The counter overflow handling is currently unsupported in this patch series. 2) ACPI support. Anurup M (8): arm64: MAINTAINERS: hisi: Add hisilicon SoC PMU support Documentation: perf: hisi: Documentation for HIP05/06/07 PMU event counting. dt-bindings: perf: hisi: Add Devicetree bindings for Hisilicon SoC PMU perf: hisi: Update Kconfig for Hisilicon PMU support perf: hisi: Add support for Hisilicon SoC event counters perf: hisi: Add sysfs attributes for L3 cache(L3C) PMU perf: hisi: Support for Hisilicon DDRC PMU. dts: arm64: hip06: Add Hisilicon SoC PMU support Shaokun Zhang (1): perf: hisi: Miscellanous node(MN) event counting in perf Tan Xiaojun (2): dt-bindings: hisi: Add Hisilicon HiP05/06/07 Sysctrl and Djtag dts bindings drivers: soc: hisi: Add support for Hisilicon Djtag driver .../bindings/arm/hisilicon/hisilicon.txt | 82 +++ .../devicetree/bindings/arm/hisilicon/pmu.txt | 127 Documentation/perf/hisi-pmu.txt| 80 +++ MAINTAINERS| 10 + arch/arm64/boot/dts/hisilicon/hip06.dtsi | 116 drivers/perf/Kconfig | 9 + drivers/perf/Makefile | 1 + drivers/perf/hisilicon/Makefile| 1 + drivers/perf/hisilicon/hisi_uncore_ddrc.c | 444 ++ drivers/perf/hisilicon/hisi_uncore_ddrc.h | 73 +++ drivers/perf/hisilicon/hisi_uncore_l3c.c | 628 drivers/perf/hisilicon/hisi_uncore_l3c.h | 67 +++ drivers/perf/hisilicon/hisi_uncore_mn.c| 571 ++ drivers/perf/hisilicon/hisi_uncore_mn.h| 68 +++ drivers/perf/hisilicon/hisi_uncore_pmu.c | 371 drivers/perf/hisilicon/hisi_uncore_pmu.h | 130 + drivers/soc/Kconfig| 1 + drivers/soc/Makefile | 1 + drivers/soc/hisilicon/Kconfig | 12 + drivers/soc/hisilicon/Makefile | 1 + drivers/soc/hisilicon/djtag.c | 639 + include/linux/soc/hisilicon/djtag.h| 38 ++ 22 files changed, 3470 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/pmu.txt create mode 100644 Documentation/perf/hisi-pmu.txt create mode 100644 drivers/perf/hisilicon/Makefile create mode 100644 drivers/perf/hisilicon/hisi_uncore_ddrc.c create mode 100644 drivers/perf/hisilicon/hisi_uncore_ddrc.h create mode 100644 drivers/perf/hisilicon/hisi_uncore_l3c.c create mode 100644 drivers/perf/hisilicon/hisi_uncore_l3c.h create mode 100644 drivers/perf/hisilicon/hisi_uncore_mn.c create mode 100644 drivers/perf/hisilicon/hisi_uncore_mn.h create mode 100644 drivers/perf/hisilicon/hisi_uncore_pmu.c create mode 100644 drivers/perf/hisilicon/hisi_uncore_pmu.h create mode 100644 drivers/soc/hisilicon/Kconfig create mode 100644 drivers/soc/hisilicon/Makefile create mode 100644 drivers/soc/hisilicon/djtag.c create mode 100644 include/linux/soc/hisilicon/djtag.h -- 2.1.4 -- To unsubscribe from this list: send the line "unsubscribe linux-doc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
