Re: [RESEND PATCH v1 05/11] dt-bindings: perf: hisi: Add Devicetree bindings for Hisilicon SoC PMU

[Anurup M]

On Tuesday 15 November 2016 03:21 PM, Mark Rutland wrote:

On Mon, Nov 14, 2016 at 05:36:44AM +0530, Anurup M wrote:

On Friday 11 November 2016 12:00 AM, Mark Rutland wrote:

On Thu, Nov 03, 2016 at 01:42:01AM -0400, Anurup M wrote:

+   - scl-id : The Super Cluster ID. This can be the ID of the CPU die
+  or IO die in the chip.

What's this needed for?

This is used as suffix to the PMU name. hisi_l3c. (hisi_l3c2
- for scl-id = 2).
This is to identify the pmu correspond to which CPU die in the socket.

+   - num-events : No of events supported by this PMU device.
+
+   - num-counters : No of hardware counters available for counting.

This isn't probeable or well-known?

My idea is to have the common properties of SoC PMU added here.
The num-events, num-counters etc. So that handling can be made
common in the driver.
Is it not recommended? Please share your comments.

This feels like something that should be well-known for the programming
model of the device. If the number of events and/or counters shange, I'd
expect other things to also change such that the device is no longer
compatible with previous versions.

[...]

Agreed, it is possible that the versions can be still incompatible. 
Shall move it to

driver in v2.


The below two properties (module-id, cfgen-map) differs between
chips hip05/06 and hip07.

The module-id property sounds like a HW description, but it's not
entirely clear to me what cfgen-map is; more comments on that below.


Please suggest.

+   - module-id : Module ID to input for djtag. This property is an array of
+ module_id for each L3 cache banks.
+
+   - num-banks : Number of banks or instances of the device.

What's a bank? Surely they have separate instances of the PMU?

Yes each bank is a separate instance of PMU.
If it is recommended to have each L3 cache bank registered as
separate PMU with perf, then this property will be removed.

Generally, I think that separate instances are preferable.


What order are these in?

The bank number will start from "1" till "4" for L3 cache as there
are four banks in hip05/06/07 chips.

+   - cfgen-map : Config enable array to select the bank.

Huh?

As above, it's not clear to me what this property represents. Could you
please clarify?

This property is used to select the bank. The naming lead to confusion.
I shall change it to bank_select.
If it is recommended to register each L3 cache bank as separate PMU then
this property will be moved to driver.

Thanks
Anurup


Thanks,
Mark.


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Re: [RESEND PATCH v1 05/11] dt-bindings: perf: hisi: Add Devicetree bindings for Hisilicon SoC PMU

[Mark Rutland]

On Mon, Nov 14, 2016 at 05:36:44AM +0530, Anurup M wrote:
> On Friday 11 November 2016 12:00 AM, Mark Rutland wrote:
> >On Thu, Nov 03, 2016 at 01:42:01AM -0400, Anurup M wrote:

> >>+   - scl-id : The Super Cluster ID. This can be the ID of the CPU die
> >>+  or IO die in the chip.
> >What's this needed for?
> This is used as suffix to the PMU name. hisi_l3c. (hisi_l3c2
> - for scl-id = 2).
> This is to identify the pmu correspond to which CPU die in the socket.
> >>+   - num-events : No of events supported by this PMU device.
> >>+
> >>+   - num-counters : No of hardware counters available for counting.
> >This isn't probeable or well-known?
> My idea is to have the common properties of SoC PMU added here.
> The num-events, num-counters etc. So that handling can be made
> common in the driver.
> Is it not recommended? Please share your comments.

This feels like something that should be well-known for the programming
model of the device. If the number of events and/or counters shange, I'd
expect other things to also change such that the device is no longer
compatible with previous versions.

[...]

> The below two properties (module-id, cfgen-map) differs between
> chips hip05/06 and hip07.

The module-id property sounds like a HW description, but it's not
entirely clear to me what cfgen-map is; more comments on that below.

> Please suggest.
> >>+   - module-id : Module ID to input for djtag. This property is an array of
> >>+ module_id for each L3 cache banks.
> >>+
> >>+   - num-banks : Number of banks or instances of the device.
> >What's a bank? Surely they have separate instances of the PMU?
> Yes each bank is a separate instance of PMU.
> If it is recommended to have each L3 cache bank registered as
> separate PMU with perf, then this property will be removed.

Generally, I think that separate instances are preferable. 

> >What order are these in?
> The bank number will start from "1" till "4" for L3 cache as there
> are four banks in hip05/06/07 chips.
> >>+   - cfgen-map : Config enable array to select the bank.
> >Huh?

As above, it's not clear to me what this property represents. Could you
please clarify?

Thanks,
Mark.
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Re: [RESEND PATCH v1 05/11] dt-bindings: perf: hisi: Add Devicetree bindings for Hisilicon SoC PMU

[Anurup M]

On Friday 11 November 2016 12:00 AM, Mark Rutland wrote:

Hi,

On Thu, Nov 03, 2016 at 01:42:01AM -0400, Anurup M wrote:

1) Device tree bindings for Hisilicon SoC PMU.
2) Add example for Hisilicon L3 cache, MN and DDRC PMU.

Signed-off-by: Anurup M
Signed-off-by: Shaokun Zhang
---
  .../devicetree/bindings/arm/hisilicon/pmu.txt  | 127 +
  1 file changed, 127 insertions(+)
  create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/pmu.txt

diff --git a/Documentation/devicetree/bindings/arm/hisilicon/pmu.txt 
b/Documentation/devicetree/bindings/arm/hisilicon/pmu.txt
new file mode 100644
index 000..e7b35e0
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/hisilicon/pmu.txt
@@ -0,0 +1,127 @@
+Hisilicon SoC hip05/06/07 ARMv8 PMU
+===
+
+The Hisilicon SoC chips like hip05/06/07 etc. consist of varous independent
+system device PMU's such as L3 cache (L3C), Miscellaneous Nodes(MN) and DDR

s/PMU's/PMUs/

OK.

+comtroller. These PMU devices are independent and have hardware logic to

s/comtroller/controller/


+gather statistics and performance information.
+
+HiSilicon SoC chip is encapsulated by multiple CPU and IO die's. The CPU die

s/die's/dies/

OK.

+is called as Super CPU cluster (SCCL) which includes 16 cpu-cores. Every SCCL
+is further grouped as CPU clusters (CCL) which includes 4 cpu-cores each.
+e.g. In the case of hip05/06/07, each SCCL has 1 L3 cache and 1 MN PMU device.
+
+The Hisilicon SoC PMU DT node bindigs for uncore PMU devices are as below.

s/bindigs/bindings/

OK. Thanks. I shall make sure with spell checker before sending v2.

+For PMU devices like L3 cache. MN etc. which are accessed using the djtag,
+the parent node will be the djtag node of the corresponding CPU die(SCCL).
+
+For uncore PMU devices there are some common required properties as detailed
+below.
+
+Required properties:
+   - compatible : This field contain two values. The first value is
+   always "hisilicon" and second value is the Module type as shown
+   in below examples:

Just say:

  - Compatible: should contain one of:

OK.

+   (a) "hisilicon,hisi-pmu-l3c-v1" for Hisilicon SoC L3C PMU
+   device (Version 1)
+   (b) "hisilicon,hisi-pmu-mn-v1" for Hisilicon SoC MN PMU
+   device (Version 1)
+   (c) "hisilicon,hisi-pmu-ddrc-v1" for Hisilicon SoC DDRC PMU
+   device (Version 1)
+   The hip05/06/07 chips have v1 hardware for L3C, MN and DDRC.
+
+   - scl-id : The Super Cluster ID. This can be the ID of the CPU die
+  or IO die in the chip.

What's this needed for?
This is used as suffix to the PMU name. hisi_l3c. (hisi_l3c2 - 
for scl-id = 2).

This is to identify the pmu correspond to which CPU die in the socket.

+   - num-events : No of events supported by this PMU device.
+
+   - num-counters : No of hardware counters available for counting.

This isn't probeable or well-known?

My idea is to have the common properties of SoC PMU added here.
The num-events, num-counters etc. So that handling can be made common in 
the driver.

Is it not recommended? Please share your comments.

+
+L3 cache
+
+The L3 cache is dedicated for each SCCL and hence there are separate DT nodes
+for L3 cache for each SCCL. For L3 cache PMU the additional required properties
+are
+   - counter-reg : Counter register offset.
+
+   - evtype-reg : Event select register offset.
+
+   - evctrl-reg : Event counting control(LAUCTRL) register offset.

Surely for a given revision of the chip these offsets are known? i.e.
surely the compatible string implies specific offsets?


+   - event-en : Event enable value.

Huh?
As for the hip05/06 and 07 chips, the above four properties are same, I 
shall

move them to the driver.

The below two properties (module-id, cfgen-map) differs between chips 
hip05/06 and hip07.
There were moved here so as to have minimal changes in driver across 
chips hip05/06/07.


OR whether it is more recommended to have the of_device_id .data set 
accordingly for handling

different chip versions?

Please suggest.

+   - module-id : Module ID to input for djtag. This property is an array of
+ module_id for each L3 cache banks.
+
+   - num-banks : Number of banks or instances of the device.

What's a bank? Surely they have separate instances of the PMU?

Yes each bank is a separate instance of PMU.
If it is recommended to have each L3 cache bank registered as separate 
PMU with perf, then this property will be removed.

What order are these in?
The bank number will start from "1" till "4" for L3 cache as there are 
four banks in hip05/06/07 chips.

+   - cfgen-map : Config enable array to select the bank.

Huh?


+Miscellaneous Node
+---
+The MN is 

Re: [RESEND PATCH v1 05/11] dt-bindings: perf: hisi: Add Devicetree bindings for Hisilicon SoC PMU

[Mark Rutland]

Hi,

On Thu, Nov 03, 2016 at 01:42:01AM -0400, Anurup M wrote:
>   1) Device tree bindings for Hisilicon SoC PMU.
>   2) Add example for Hisilicon L3 cache, MN and DDRC PMU.
> 
> Signed-off-by: Anurup M 
> Signed-off-by: Shaokun Zhang 
> ---
>  .../devicetree/bindings/arm/hisilicon/pmu.txt  | 127 
> +
>  1 file changed, 127 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/pmu.txt
> 
> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/pmu.txt 
> b/Documentation/devicetree/bindings/arm/hisilicon/pmu.txt
> new file mode 100644
> index 000..e7b35e0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/hisilicon/pmu.txt
> @@ -0,0 +1,127 @@
> +Hisilicon SoC hip05/06/07 ARMv8 PMU
> +===
> +
> +The Hisilicon SoC chips like hip05/06/07 etc. consist of varous independent
> +system device PMU's such as L3 cache (L3C), Miscellaneous Nodes(MN) and DDR

s/PMU's/PMUs/

> +comtroller. These PMU devices are independent and have hardware logic to

s/comtroller/controller/

> +gather statistics and performance information.
> +
> +HiSilicon SoC chip is encapsulated by multiple CPU and IO die's. The CPU die

s/die's/dies/

> +is called as Super CPU cluster (SCCL) which includes 16 cpu-cores. Every SCCL
> +is further grouped as CPU clusters (CCL) which includes 4 cpu-cores each.
> +e.g. In the case of hip05/06/07, each SCCL has 1 L3 cache and 1 MN PMU 
> device.
> +
> +The Hisilicon SoC PMU DT node bindigs for uncore PMU devices are as below.

s/bindigs/bindings/

> +For PMU devices like L3 cache. MN etc. which are accessed using the djtag,
> +the parent node will be the djtag node of the corresponding CPU die(SCCL).
> +
> +For uncore PMU devices there are some common required properties as detailed
> +below.
> +
> +Required properties:
> + - compatible : This field contain two values. The first value is
> + always "hisilicon" and second value is the Module type as shown
> + in below examples:

Just say:

 - Compatible: should contain one of:

> + (a) "hisilicon,hisi-pmu-l3c-v1" for Hisilicon SoC L3C PMU
> + device (Version 1)
> + (b) "hisilicon,hisi-pmu-mn-v1" for Hisilicon SoC MN PMU
> + device (Version 1)
> + (c) "hisilicon,hisi-pmu-ddrc-v1" for Hisilicon SoC DDRC PMU
> + device (Version 1)
> + The hip05/06/07 chips have v1 hardware for L3C, MN and DDRC.
> +
> + - scl-id : The Super Cluster ID. This can be the ID of the CPU die
> +or IO die in the chip.

What's this needed for?

> + - num-events : No of events supported by this PMU device.
> +
> + - num-counters : No of hardware counters available for counting.

This isn't probeable or well-known?

> +
> +L3 cache
> +
> +The L3 cache is dedicated for each SCCL and hence there are separate DT nodes
> +for L3 cache for each SCCL. For L3 cache PMU the additional required 
> properties
> +are
> + - counter-reg : Counter register offset.
> +
> + - evtype-reg : Event select register offset.
> +
> + - evctrl-reg : Event counting control(LAUCTRL) register offset.

Surely for a given revision of the chip these offsets are known? i.e.
surely the compatible string implies specific offsets?

> + - event-en : Event enable value.

Huh?

> + - module-id : Module ID to input for djtag. This property is an array of
> +   module_id for each L3 cache banks.
> +
> + - num-banks : Number of banks or instances of the device.

What's a bank? Surely they have separate instances of the PMU?

What order are these in?

> + - cfgen-map : Config enable array to select the bank.

Huh?

> +Miscellaneous Node
> +---
> +The MN is dedicated for each SCCL and hence there are separate DT nodes for 
> MN
> +for each SCCL. For MN PMU the additional required properties are
> + - counter-reg : Counter register offset.
> +
> + - evtype-reg : Event select register offset.
> +
> + - evctrl-reg : Event counting control register offset.

Likewise, surely this is well-known for a given revision of the chip?

> +
> + - module-id : Module ID to input for djtag. As MN doesnot have multiple 
> banks
> +   this property is a single value.
> +
> + - cfgen-map : Config enable to select the bank. For MN it is a single 
> value
> +
> + - event-en : Event enable value.

Same comments as for the L3 cache nodes


[...]

> +DDR controller
> +--
> +Each SCCL in Hip05/06/07 chips have 2 DDR channels and hence 2 DDR 
> controllers.
> +There are separate DT nodes for each DDR channel.
> +For DDRC PMU the additional required properties are
> +
> + - ch-id : DDRC Channel ID.

Why is this necessary?

Thanks,
Mark.

> + - reg : Register base address and range for the DDRC channel.
> +

Re: [RESEND PATCH v1 05/11] dt-bindings: perf: hisi: Add Devicetree bindings for Hisilicon SoC PMU

[Anurup M]

On Thursday 03 November 2016 11:56 PM, Krzysztof Kozlowski wrote:

On Thu, Nov 03, 2016 at 01:42:01AM -0400, Anurup M wrote:

1) Device tree bindings for Hisilicon SoC PMU.
2) Add example for Hisilicon L3 cache, MN and DDRC PMU.

Get rid of this weird indentation in all patches.

Thanks. I shall remove the TAB from the commit message in all patches.



Signed-off-by: Anurup M 
Signed-off-by: Shaokun Zhang 
---
  .../devicetree/bindings/arm/hisilicon/pmu.txt  | 127 +
  1 file changed, 127 insertions(+)
  create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/pmu.txt

diff --git a/Documentation/devicetree/bindings/arm/hisilicon/pmu.txt 
b/Documentation/devicetree/bindings/arm/hisilicon/pmu.txt
new file mode 100644
index 000..e7b35e0
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/hisilicon/pmu.txt
@@ -0,0 +1,127 @@
+Hisilicon SoC hip05/06/07 ARMv8 PMU
+===
+
+The Hisilicon SoC chips like hip05/06/07 etc. consist of varous independent
+system device PMU's such as L3 cache (L3C), Miscellaneous Nodes(MN) and DDR
+comtroller. These PMU devices are independent and have hardware logic to
+gather statistics and performance information.
+
+HiSilicon SoC chip is encapsulated by multiple CPU and IO die's. The CPU die
+is called as Super CPU cluster (SCCL) which includes 16 cpu-cores. Every SCCL
+is further grouped as CPU clusters (CCL) which includes 4 cpu-cores each.
+e.g. In the case of hip05/06/07, each SCCL has 1 L3 cache and 1 MN PMU device.
+
+The Hisilicon SoC PMU DT node bindigs for uncore PMU devices are as below.
+For PMU devices like L3 cache. MN etc. which are accessed using the djtag,
+the parent node will be the djtag node of the corresponding CPU die(SCCL).
+
+For uncore PMU devices there are some common required properties as detailed
+below.
+
+Required properties:
+   - compatible : This field contain two values. The first value is
+   always "hisilicon" and second value is the Module type as shown
+   in below examples:

Over-complicated sentence. Just:

- compatible : One of:
"hisilicon,hisi-pmu-l3c-v1" for Hisilicon SoC L3C PMU
device (Version 1)
...
...

Thanks. Shall refine it in next version.

BTW, No need of CC-ing me. I am not a maintainer of relevant subsystems.

Sure.

Thanks,
Anurup

Best regards,
Krzysztof


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Re: [RESEND PATCH v1 05/11] dt-bindings: perf: hisi: Add Devicetree bindings for Hisilicon SoC PMU

[Krzysztof Kozlowski]

On Thu, Nov 03, 2016 at 01:42:01AM -0400, Anurup M wrote:
>   1) Device tree bindings for Hisilicon SoC PMU.
>   2) Add example for Hisilicon L3 cache, MN and DDRC PMU.

Get rid of this weird indentation in all patches.


> 
> Signed-off-by: Anurup M 
> Signed-off-by: Shaokun Zhang 
> ---
>  .../devicetree/bindings/arm/hisilicon/pmu.txt  | 127 
> +
>  1 file changed, 127 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/pmu.txt
> 
> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/pmu.txt 
> b/Documentation/devicetree/bindings/arm/hisilicon/pmu.txt
> new file mode 100644
> index 000..e7b35e0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/hisilicon/pmu.txt
> @@ -0,0 +1,127 @@
> +Hisilicon SoC hip05/06/07 ARMv8 PMU
> +===
> +
> +The Hisilicon SoC chips like hip05/06/07 etc. consist of varous independent
> +system device PMU's such as L3 cache (L3C), Miscellaneous Nodes(MN) and DDR
> +comtroller. These PMU devices are independent and have hardware logic to
> +gather statistics and performance information.
> +
> +HiSilicon SoC chip is encapsulated by multiple CPU and IO die's. The CPU die
> +is called as Super CPU cluster (SCCL) which includes 16 cpu-cores. Every SCCL
> +is further grouped as CPU clusters (CCL) which includes 4 cpu-cores each.
> +e.g. In the case of hip05/06/07, each SCCL has 1 L3 cache and 1 MN PMU 
> device.
> +
> +The Hisilicon SoC PMU DT node bindigs for uncore PMU devices are as below.
> +For PMU devices like L3 cache. MN etc. which are accessed using the djtag,
> +the parent node will be the djtag node of the corresponding CPU die(SCCL).
> +
> +For uncore PMU devices there are some common required properties as detailed
> +below.
> +
> +Required properties:
> + - compatible : This field contain two values. The first value is
> + always "hisilicon" and second value is the Module type as shown
> + in below examples:

Over-complicated sentence. Just:

- compatible : One of:
"hisilicon,hisi-pmu-l3c-v1" for Hisilicon SoC L3C PMU
device (Version 1)
...
...

BTW, No need of CC-ing me. I am not a maintainer of relevant subsystems.

Best regards,
Krzysztof
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[RESEND PATCH v1 05/11] dt-bindings: perf: hisi: Add Devicetree bindings for Hisilicon SoC PMU

[Anurup M]

1) Device tree bindings for Hisilicon SoC PMU.
2) Add example for Hisilicon L3 cache, MN and DDRC PMU.

Signed-off-by: Anurup M 
Signed-off-by: Shaokun Zhang 
---
 .../devicetree/bindings/arm/hisilicon/pmu.txt  | 127 +
 1 file changed, 127 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/pmu.txt

diff --git a/Documentation/devicetree/bindings/arm/hisilicon/pmu.txt 
b/Documentation/devicetree/bindings/arm/hisilicon/pmu.txt
new file mode 100644
index 000..e7b35e0
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/hisilicon/pmu.txt
@@ -0,0 +1,127 @@
+Hisilicon SoC hip05/06/07 ARMv8 PMU
+===
+
+The Hisilicon SoC chips like hip05/06/07 etc. consist of varous independent
+system device PMU's such as L3 cache (L3C), Miscellaneous Nodes(MN) and DDR
+comtroller. These PMU devices are independent and have hardware logic to
+gather statistics and performance information.
+
+HiSilicon SoC chip is encapsulated by multiple CPU and IO die's. The CPU die
+is called as Super CPU cluster (SCCL) which includes 16 cpu-cores. Every SCCL
+is further grouped as CPU clusters (CCL) which includes 4 cpu-cores each.
+e.g. In the case of hip05/06/07, each SCCL has 1 L3 cache and 1 MN PMU device.
+
+The Hisilicon SoC PMU DT node bindigs for uncore PMU devices are as below.
+For PMU devices like L3 cache. MN etc. which are accessed using the djtag,
+the parent node will be the djtag node of the corresponding CPU die(SCCL).
+
+For uncore PMU devices there are some common required properties as detailed
+below.
+
+Required properties:
+   - compatible : This field contain two values. The first value is
+   always "hisilicon" and second value is the Module type as shown
+   in below examples:
+   (a) "hisilicon,hisi-pmu-l3c-v1" for Hisilicon SoC L3C PMU
+   device (Version 1)
+   (b) "hisilicon,hisi-pmu-mn-v1" for Hisilicon SoC MN PMU
+   device (Version 1)
+   (c) "hisilicon,hisi-pmu-ddrc-v1" for Hisilicon SoC DDRC PMU
+   device (Version 1)
+   The hip05/06/07 chips have v1 hardware for L3C, MN and DDRC.
+
+   - scl-id : The Super Cluster ID. This can be the ID of the CPU die
+  or IO die in the chip.
+
+   - num-events : No of events supported by this PMU device.
+
+   - num-counters : No of hardware counters available for counting.
+
+L3 cache
+
+The L3 cache is dedicated for each SCCL and hence there are separate DT nodes
+for L3 cache for each SCCL. For L3 cache PMU the additional required properties
+are
+   - counter-reg : Counter register offset.
+
+   - evtype-reg : Event select register offset.
+
+   - evctrl-reg : Event counting control(LAUCTRL) register offset.
+
+   - event-en : Event enable value.
+
+   - module-id : Module ID to input for djtag. This property is an array of
+ module_id for each L3 cache banks.
+
+   - num-banks : Number of banks or instances of the device.
+
+   - cfgen-map : Config enable array to select the bank.
+
+Miscellaneous Node
+---
+The MN is dedicated for each SCCL and hence there are separate DT nodes for MN
+for each SCCL. For MN PMU the additional required properties are
+   - counter-reg : Counter register offset.
+
+   - evtype-reg : Event select register offset.
+
+   - evctrl-reg : Event counting control register offset.
+
+   - module-id : Module ID to input for djtag. As MN doesnot have multiple 
banks
+ this property is a single value.
+
+   - cfgen-map : Config enable to select the bank. For MN it is a single 
value
+
+   - event-en : Event enable value.
+
+Example:
+
+   djtag0: djtag@0 {
+   compatible = "hisilicon,hip05-cpu-djtag-v1";
+   pmul3c0 {
+   compatible = "hisilicon,hisi-pmu-l3c-v1";
+   scl-id = <0x02>;
+   num-events = <0x16>;
+   num-counters = <0x08>;
+   module-id = <0x04 0x04 0x04 0x04>;
+   num-banks = <0x04>;
+   cfgen-map = <0x02 0x04 0x01 0x08>;
+   counter-reg = <0x170>;
+   evctrl-reg = <0x04>;
+   event-en = <0x100>;
+   evtype-reg = <0x140>;
+   };
+
+   pmumn0 {
+   compatible = "hisilicon,hisi-pmu-mn-v1";
+   scl-id = <0x02>;
+   num-events = <0x09>;
+   num-counters = <0x04>;
+   module-id = <0x0b>;
+   cfgen-map = <0x01>;
+   counter-reg = <0x30>;
+   evctrl-reg = <0x40>;
+