Re: [PATCH -next] ALSA: es1688: Remove set but not used variable 'hw'
On Thu, 14 Feb 2019 03:10:33 +0100, YueHaibing wrote: > > Fixes gcc '-Wunused-but-set-variable' warning: > > sound/isa/es1688/es1688_lib.c: In function 'snd_es1688_probe': > sound/isa/es1688/es1688_lib.c:124:31: warning: > variable 'hw' set but not used [-Wunused-but-set-variable] > unsigned short major, minor, hw; >^ > > Signed-off-by: YueHaibing Applied, thanks. Takashi
Re: [PATCH 2/2] gpio: sprd: Change to use SoC compatible string
On Wed, Feb 13, 2019 at 5:10 PM Bartosz Golaszewski
wrote:
> śr., 13 lut 2019 o 14:15 Baolin Wang napisał(a):
> >
> > On Wed, 13 Feb 2019 at 20:59, Bartosz Golaszewski
> > wrote:
> > >
> > > śr., 13 lut 2019 o 13:49 Baolin Wang napisał(a):
> > > >
> > > > Change to use SoC compatible string instead of wildcard string.
> > > >
> > > > Signed-off-by: Baolin Wang
> > > > ---
> > > > drivers/gpio/gpio-pmic-eic-sprd.c |2 +-
> > > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > > >
> > > > diff --git a/drivers/gpio/gpio-pmic-eic-sprd.c
> > > > b/drivers/gpio/gpio-pmic-eic-sprd.c
> > > > index ac573da..24228cf 100644
> > > > --- a/drivers/gpio/gpio-pmic-eic-sprd.c
> > > > +++ b/drivers/gpio/gpio-pmic-eic-sprd.c
> > > > @@ -364,7 +364,7 @@ static int sprd_pmic_eic_probe(struct
> > > > platform_device *pdev)
> > > > }
> > > >
> > > > static const struct of_device_id sprd_pmic_eic_of_match[] = {
> > > > - { .compatible = "sprd,sc27xx-eic", },
> > > > + { .compatible = "sprd,sc2731-eic", },
> > > > { /* end of list */ }
> > > > };
> > > > MODULE_DEVICE_TABLE(of, sprd_pmic_eic_of_match);
> > > > --
> > > > 1.7.9.5
> > > >
> > >
> > > We guarantee to make older device-trees to work with new kernel so you
> > > can add the new compatible, but you can't remove the old one.
> >
> > But the old one is incorrect, and we still keep it?
> >
>
> Well in theory the device-tree is supposed to be a stable ABI so once
> it's released, it should work with any following kernel version.
>
> In practice changes are sometimes allowed and there are also bugs in DT files.
>
> Linus: what do you think?
In this specific case I'd keep both strings, it doesn't hurt does it?
You could add a comment to the wildcard string saying it is only there
for compatibility with elder device trees.
In general as long as there are not (a lot of) products shipped with
a certain device tree, I don't care much whether we change the bindings
or contents.
The hard rule to keep the device trees backward-compatible comes
from SPARC SunOS where the DTB was burned into a BIOS ROM
that was hard or impossible to update, Linux just had to handle
whatever was in there. If the situation with the device tree we change
is not similiar, we should not care either.
In practice there are companies and developers that always
recompile and ship their device trees at the same time as they
compile and ship their kernel, and in that case we need not care
about backward compatibility.
While the device tree enablement on ARM started out with the
former (strict) assumption, the practice of using DTs has shown
that it is an unrealistic and inappropriate stance to have for all
device trees. (IMO!) So I don't mind if you break compatibility here.
Yours,
Linus Walleij
Re: [PATCH v6 2/2] pwm: sifive: Add a driver for SiFive SoC PWM
On Wed, Feb 13, 2019 at 4:05 PM Uwe Kleine-König
wrote:
>
> Hello,
>
> On Wed, Feb 13, 2019 at 02:56:18PM +0530, Yash Shah wrote:
> > Adds a PWM driver for PWM chip present in SiFive's HiFive Unleashed SoC.
> >
> > Signed-off-by: Wesley W. Terpstra
> > [Atish: Various fixes and code cleanup]
> > Signed-off-by: Atish Patra
> > Signed-off-by: Yash Shah
> > ---
> > drivers/pwm/Kconfig | 11 ++
> > drivers/pwm/Makefile | 1 +
> > drivers/pwm/pwm-sifive.c | 311
> > +++
> > 3 files changed, 323 insertions(+)
> > create mode 100644 drivers/pwm/pwm-sifive.c
> >
> > diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
> > index a8f47df..4a61d1a 100644
> > --- a/drivers/pwm/Kconfig
> > +++ b/drivers/pwm/Kconfig
> > @@ -380,6 +380,17 @@ config PWM_SAMSUNG
> > To compile this driver as a module, choose M here: the module
> > will be called pwm-samsung.
> >
> > +config PWM_SIFIVE
> > + tristate "SiFive PWM support"
> > + depends on OF
> > + depends on COMMON_CLK
> > + depends on RISCV || COMPILE_TEST
> > + help
> > + Generic PWM framework driver for SiFive SoCs.
> > +
> > + To compile this driver as a module, choose M here: the module
> > + will be called pwm-sifive.
> > +
> > config PWM_SPEAR
> > tristate "STMicroelectronics SPEAr PWM support"
> > depends on PLAT_SPEAR
> > diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
> > index 9c676a0..30089ca 100644
> > --- a/drivers/pwm/Makefile
> > +++ b/drivers/pwm/Makefile
> > @@ -37,6 +37,7 @@ obj-$(CONFIG_PWM_RCAR) += pwm-rcar.o
> > obj-$(CONFIG_PWM_RENESAS_TPU)+= pwm-renesas-tpu.o
> > obj-$(CONFIG_PWM_ROCKCHIP) += pwm-rockchip.o
> > obj-$(CONFIG_PWM_SAMSUNG)+= pwm-samsung.o
> > +obj-$(CONFIG_PWM_SIFIVE) += pwm-sifive.o
> > obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o
> > obj-$(CONFIG_PWM_STI)+= pwm-sti.o
> > obj-$(CONFIG_PWM_STM32) += pwm-stm32.o
> > diff --git a/drivers/pwm/pwm-sifive.c b/drivers/pwm/pwm-sifive.c
> > new file mode 100644
> > index 000..c0eb90e
> > --- /dev/null
> > +++ b/drivers/pwm/pwm-sifive.c
> > @@ -0,0 +1,311 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2017-2018 SiFive
> > + * For SiFive's PWM IP block documentation please refer Chapter 14 of
> > + * Reference Manual : https://static.dev.sifive.com/FU540-C000-v1.0.pdf
> > + */
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +
> > +/* Register offsets */
> > +#define PWM_SIFIVE_PWMCFG0x0
> > +#define PWM_SIFIVE_PWMCOUNT 0x8
> > +#define PWM_SIFIVE_PWMS 0x10
> > +#define PWM_SIFIVE_PWMCMP0 0x20
> > +
> > +/* PWMCFG fields */
> > +#define PWM_SIFIVE_PWMCFG_SCALE 0
> > +#define PWM_SIFIVE_PWMCFG_STICKY 8
> > +#define PWM_SIFIVE_PWMCFG_ZERO_CMP 9
> > +#define PWM_SIFIVE_PWMCFG_DEGLITCH 10
> > +#define PWM_SIFIVE_PWMCFG_EN_ALWAYS 12
>
> PWM_SIFIVE_PWMCFG_EN_ALWAYS is always used as
>
> BIT(PWM_SIFIVE_PWMCFG_EN_ALWAYS)
>
> so defining this as BIT(12) directly makes some expressions below easier
> to read.
Sure, will do that.
>
> > +#define PWM_SIFIVE_PWMCFG_EN_ONCE13
> > +#define PWM_SIFIVE_PWMCFG_CENTER 16
> > +#define PWM_SIFIVE_PWMCFG_GANG 24
> > +#define PWM_SIFIVE_PWMCFG_IP 28
> > +
> > +/* PWM_SIFIVE_SIZE_PWMCMP is used to calculate offset for pwmcmpX
> > registers */
> > +#define PWM_SIFIVE_SIZE_PWMCMP 4
> > +#define PWM_SIFIVE_CMPWIDTH 16
> > +
> > +struct pwm_sifive_ddata {
> > + struct pwm_chip chip;
> > + struct notifier_block notifier;
> > + struct clk *clk;
> > + void __iomem *regs;
> > + unsigned int real_period;
> > + int user_count;
> > +};
> > +
> > +static inline
> > +struct pwm_sifive_ddata *pwm_sifive_chip_to_ddata(struct pwm_chip *c)
> > +{
> > + return container_of(c, struct pwm_sifive_ddata, chip);
> > +}
> > +
> > +static int pwm_sifive_request(struct pwm_chip *chip, struct pwm_device
> > *dev)
> > +{
> > + struct pwm_sifive_ddata *pwm = pwm_sifive_chip_to_ddata(chip);
> > +
> > + pwm->user_count++;
> > +
> > + return 0;
> > +}
> > +
> > +static void pwm_sifive_free(struct pwm_chip *chip, struct pwm_device *dev)
> > +{
> > + struct pwm_sifive_ddata *pwm = pwm_sifive_chip_to_ddata(chip);
> > +
> > + pwm->user_count--;
> > +}
> > +
> > +static void pwm_sifive_update_clock(struct pwm_sifive_ddata *pwm,
> > + unsigned long rate)
> > +{
> > + /* (1 << (16+scale)) * 10^9/rate = real_period */
>
> Maybe you want to mention here the relation between 16 and
> PWM_SIFIVE_CMPWIDTH.
Sure, will change it to
/* (1 << (PWM_SIFIVE_CMPWIDTH+scale)) * 10^9/rate = real_period */
>
> > + unsigned long scale_pow =
> > + div64_ul(pwm->real_period * (u64)rate,
Re: [PATCH v2] virtio_net: Introduce extended RSC feature
Can you please let me know whether this patch accepted?
Is yes, I'll post similar change to qemu to prevent future compilation
error when linux header will be updated.
Thanks,
Yuri
On Fri, Feb 1, 2019 at 10:50 AM Yuri Benditovich
wrote:
>
> VIRTIO_NET_F_RSC_EXT feature bit indicates that the device
> is able to provide extended RSC information. When the feature
> is active and 'gso_type' field in received packet is not GSO_NONE,
> the device reports number of coalesced packets in 'csum_start'
> field and number of duplicated acks in 'csum_offset' field
> and sets VIRTIO_NET_HDR_F_RSC_INFO in 'flags' field.
>
> Signed-off-by: Yuri Benditovich
> ---
> include/uapi/linux/virtio_net.h | 12 +++-
> 1 file changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/include/uapi/linux/virtio_net.h b/include/uapi/linux/virtio_net.h
> index a3715a3224c1..23e73d666fc2 100644
> --- a/include/uapi/linux/virtio_net.h
> +++ b/include/uapi/linux/virtio_net.h
> @@ -56,7 +56,7 @@
> #define VIRTIO_NET_F_MQ22 /* Device supports Receive Flow
> * Steering */
> #define VIRTIO_NET_F_CTRL_MAC_ADDR 23 /* Set MAC address */
> -
> +#define VIRTIO_NET_F_RSC_EXT 61/* Provides extended RSC info */
> #define VIRTIO_NET_F_STANDBY 62/* Act as standby for another device
> * with the same MAC.
> */
> @@ -104,6 +104,7 @@ struct virtio_net_config {
> struct virtio_net_hdr_v1 {
> #define VIRTIO_NET_HDR_F_NEEDS_CSUM1 /* Use csum_start,
> csum_offset */
> #define VIRTIO_NET_HDR_F_DATA_VALID2 /* Csum is valid */
> +#define VIRTIO_NET_HDR_F_RSC_INFO 4 /* rsc_ext data in csum_ fields */
> __u8 flags;
> #define VIRTIO_NET_HDR_GSO_NONE0 /* Not a GSO frame */
> #define VIRTIO_NET_HDR_GSO_TCPV4 1 /* GSO frame, IPv4 TCP (TSO)
> */
> @@ -118,6 +119,15 @@ struct virtio_net_hdr_v1 {
> __virtio16 num_buffers; /* Number of merged rx buffers */
> };
>
> +/* if VIRTIO_NET_HDR_F_RSC_INFO is set, the csum_start
> + * field contains number of coalesced segments
> + */
> +#define virtio_net_rsc_ext_num_packets csum_start
> +/* if VIRTIO_NET_HDR_F_RSC_INFO is set, the csum_offset
> + * field contains number of duplicated acks
> + */
> +#define virtio_net_rsc_ext_num_dupacks csum_offset
> +
> #ifndef VIRTIO_NET_NO_LEGACY
> /* This header comes first in the scatter-gather list.
> * For legacy virtio, if VIRTIO_F_ANY_LAYOUT is not negotiated, it must
> --
> 2.17.1
>
[PATCH v2] dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings
Add document the devicetree bindings for MediaTek Command-Queue DMA controller. Changes since v1: 1. fix wrong description and tags in the earlier patch
[PATCH v2 1/1] dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings
From: Shun-Chih Yu
Document the devicetree bindings for MediaTek Command-Queue DMA controller
which could be found on MT6765 SoC or other similar Mediatek SoCs.
Signed-off-by: Shun-Chih Yu
Reviewed-by: Rob Herring
Acked-by: Sean Wang
---
.../devicetree/bindings/dma/mtk-cqdma.txt | 31
1 file changed, 31 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/mtk-cqdma.txt
diff --git a/Documentation/devicetree/bindings/dma/mtk-cqdma.txt
b/Documentation/devicetree/bindings/dma/mtk-cqdma.txt
new file mode 100644
index 000..fb12927
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/mtk-cqdma.txt
@@ -0,0 +1,31 @@
+MediaTek Command-Queue DMA Controller
+==
+
+Required properties:
+
+- compatible: Must be "mediatek,mt6765-cqdma" for MT6765.
+- reg: Should contain the base address and length for each channel.
+- interrupts: Should contain references to the interrupts for each channel.
+- clocks: Should be the clock specifiers corresponding to the entry in
+ clock-names property.
+- clock-names: Should contain "cqdma" entries.
+- dma-channels: The number of DMA channels supported by the controller.
+- dma-requests: The number of DMA request supported by the controller.
+- #dma-cells: The length of the DMA specifier, must be <1>. This one cell
+ in dmas property of a client device represents the channel
+ number.
+Example:
+
+cqdma: dma-controller@10212000 {
+ compatible = "mediatek,mt6765-cqdma";
+ reg = <0 0x10212000 0 0x1000>;
+ interrupts = ,
+ ;
+ clocks = < CLK_IFR_CQ_DMA>;
+ clock-names = "cqdma";
+ dma-channels = <2>;
+ dma-requests = <32>;
+ #dma-cells = <1>;
+ };
+
+DMA clients must use the format described in dma/dma.txt file.
--
1.7.9.5
Re: [PATCH v2 3/3] regulator: bd718x7: Support SNVS low power state
Hello peeps,
A bug found from patch.
On Wed, Feb 13, 2019 at 11:50:49AM +0200, Matti Vaittinen wrote:
> read ROHM BD71837 / BD71847 specific device tree bindings for
> controlling the PMIC shutdown/reset states and voltages for
> different HW states. The PMIC was designed to be used with NXP
> i.MX8 SoC and it supports SNVS low power state which seems to
> be typical for NXP i.MX SoCs. However, when SNVS is used we must
> not allow SW to control enabling/disabling those regulators which
> are crucial for system to boot as there is a HW limitation which
> causes SW controlled regulators to be kept shut down after SNVS
> reset.
>
> Allow setting the SNVS to be used as reset target state and allow
> marking those regulators which are critical for boot.
>
> Signed-off-by: Matti Vaittinen
> --- a/drivers/regulator/bd718x7-regulator.c
> +++ b/drivers/regulator/bd718x7-regulator.c
> @@ -685,6 +817,7 @@ static const struct bd718xx_regulator_data
> bd71837_regulators[] = {
> .enable_reg = BD718XX_REG_BUCK2_CTRL,
> .enable_mask = BD718XX_BUCK_EN,
> .owner = THIS_MODULE,
> + .of_parse_cb = buck1_set_hw_dvs_levels,
This should be
+ .of_parse_cb = buck2_set_hw_dvs_levels,
Thanks to Angus for all the testing! I'll send v3 soonish.
--
Matti Vaittinen, Linux device drivers
ROHM Semiconductors, Finland SWDC
Kiviharjunlenkki 1E
90220 OULU
FINLAND
~~~ "I don't think so," said Rene Descartes. Just then, he vanished ~~~
Re: linux-next: build warning after merge of the leds tree
On Thu, Feb 14, 2019 at 4:46 AM Stephen Rothwell wrote:
>
> Hi Jacek,
>
> After merging the leds tree, today's linux-next build (x86_64
> allmodconfig) produced this warning:
>
> drivers/leds/leds-lp55xx-common.c: In function 'lp55xx_firmware_loaded':
> drivers/leds/leds-lp55xx-common.c:217:1: warning: label 'out' defined but not
> used [-Wunused-label]
> out:
> ^~~
>
> Introduced by commit
>
> 905c2157dd19 ("leds: lp55xx: fix null deref on firmware load failure")
I'm sorry guys, that's my fault. Let me fix that.
Michał
Re: [PATCH] fs/coda: get rid of CODA_ALLOC()
On Thu, Feb 14, 2019 at 08:04:43AM +0100, Julia Lawall wrote: > > > On Thu, 14 Feb 2019, Dan Carpenter wrote: > > > These days we have kvzalloc() so we can delete CODA_ALLOC(). > > Maybe it would be better to get rid fo CODA_FREE as well? > Actually, you're right. CODA_FREE() is especially weird without a CODA_ALLOC(). But let me send that as a second patch. regards, dan carpenter
Re: [RFC PATCH v8 04/14] swiotlb: Map the buffer if it was unmapped by XPFO
On Wed, Feb 13, 2019 at 05:01:27PM -0700, Khalid Aziz wrote:
> +++ b/kernel/dma/swiotlb.c
> @@ -396,8 +396,9 @@ static void swiotlb_bounce(phys_addr_t orig_addr,
> phys_addr_t tlb_addr,
> {
> unsigned long pfn = PFN_DOWN(orig_addr);
> unsigned char *vaddr = phys_to_virt(tlb_addr);
> + struct page *page = pfn_to_page(pfn);
>
> - if (PageHighMem(pfn_to_page(pfn))) {
> + if (PageHighMem(page) || xpfo_page_is_unmapped(page)) {
I think this just wants a page_unmapped or similar helper instead of
needing the xpfo_page_is_unmapped check. We actually have quite
a few similar construct in the arch dma mapping code for architectures
that require cache flushing.
> +bool xpfo_page_is_unmapped(struct page *page)
> +{
> + struct xpfo *xpfo;
> +
> + if (!static_branch_unlikely(_inited))
> + return false;
> +
> + xpfo = lookup_xpfo(page);
> + if (unlikely(!xpfo) && !xpfo->inited)
> + return false;
> +
> + return test_bit(XPFO_PAGE_UNMAPPED, >flags);
> +}
> +EXPORT_SYMBOL(xpfo_page_is_unmapped);
And at least for swiotlb there is no need to export this helper,
as it is always built in.
[PATCH v2 1/2] ACPI / CPPC: Add a helper to get desired performance
This patch add a helper to get the value of desired performance
register.
Signed-off-by: Xiongfeng Wang
---
drivers/acpi/cppc_acpi.c | 38 ++
include/acpi/cppc_acpi.h | 1 +
2 files changed, 39 insertions(+)
diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c
index 217a782..93588c5 100644
--- a/drivers/acpi/cppc_acpi.c
+++ b/drivers/acpi/cppc_acpi.c
@@ -1051,6 +1051,44 @@ static int cpc_write(int cpu, struct
cpc_register_resource *reg_res, u64 val)
}
/**
+ * cppc_get_desired_perf - Get the value of desired performance register.
+ * @cpunum: CPU from which to get desired performance.
+ * @desired_perf: address of a variable to store the returned desired
performance
+ *
+ * Return: 0 for success, -EIO otherwise.
+ */
+int cppc_get_desired_perf(int cpunum, u64 *desired_perf)
+{
+ struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
+ int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
+ struct cpc_register_resource *desired_reg;
+ struct cppc_pcc_data *pcc_ss_data = NULL;
+ int regs_in_pcc = 0;
+
+ desired_reg = _desc->cpc_regs[DESIRED_PERF];
+
+ if (CPC_IN_PCC(desired_reg)) {
+ if (pcc_ss_id < 0)
+ return -EIO;
+ pcc_ss_data = pcc_data[pcc_ss_id];
+ down_write(_ss_data->pcc_lock);
+ regs_in_pcc = 1;
+ if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) {
+ up_write(_ss_data->pcc_lock);
+ return -EIO;
+ }
+ }
+
+ cpc_read(cpunum, desired_reg, desired_perf);
+
+ if (regs_in_pcc)
+ up_write(_ss_data->pcc_lock);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(cppc_get_desired_perf);
+
+/**
* cppc_get_perf_caps - Get a CPUs performance capabilities.
* @cpunum: CPU from which to get capabilities info.
* @perf_caps: ptr to cppc_perf_caps. See cppc_acpi.h
diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h
index 4f34734..ba6fd72 100644
--- a/include/acpi/cppc_acpi.h
+++ b/include/acpi/cppc_acpi.h
@@ -137,6 +137,7 @@ struct cppc_cpudata {
cpumask_var_t shared_cpu_map;
};
+extern int cppc_get_desired_perf(int cpunum, u64 *desired_perf);
extern int cppc_get_perf_ctrs(int cpu, struct cppc_perf_fb_ctrs *perf_fb_ctrs);
extern int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls);
extern int cppc_get_perf_caps(int cpu, struct cppc_perf_caps *caps);
--
1.7.12.4
[PATCH v2 0/2] Work around for Hisilicon CPPC cpufreq
Hisilicon chips do not support delivered performance counter register and reference performance counter register. But the platform can calculate the real performance using its own method. This patch provide a workaround for this problem, and other platforms can also use this workaround framework. We reuse the desired performance register to store the real performance calculated by the platform. After the platform finished the frequency adjust, it gets the real performance and writes it into desired performance register. OS can use it to calculate the real frequency. Xiongfeng Wang (2): ACPI / CPPC: Add a helper to get desired performance cpufreq / cppc: Work around for Hisilicon CPPC cpufreq drivers/acpi/cppc_acpi.c | 38 +++ drivers/cpufreq/cppc_cpufreq.c | 70 ++ include/acpi/cppc_acpi.h | 1 + 3 files changed, 109 insertions(+) -- 1.7.12.4
[PATCH v2 2/2] cpufreq / cppc: Work around for Hisilicon CPPC cpufreq
Hisilicon chips do not support delivered performance counter register
and reference performance counter register. But the platform can
calculate the real performance using its own method. This patch provide
a workaround for this problem, and other platforms can also use this
workaround framework. We reuse the desired performance register to
store the real performance calculated by the platform. After the
platform finished the frequency adjust, it gets the real performance and
writes it into desired performance register. OS can use it to calculate
the real frequency.
Signed-off-by: Xiongfeng Wang
---
drivers/cpufreq/cppc_cpufreq.c | 70 ++
1 file changed, 70 insertions(+)
diff --git a/drivers/cpufreq/cppc_cpufreq.c b/drivers/cpufreq/cppc_cpufreq.c
index fd25c21c..da96fec 100644
--- a/drivers/cpufreq/cppc_cpufreq.c
+++ b/drivers/cpufreq/cppc_cpufreq.c
@@ -33,6 +33,16 @@
/* Offest in the DMI processor structure for the max frequency */
#define DMI_PROCESSOR_MAX_SPEED 0x14
+struct cppc_workaround_info {
+ char oem_id[ACPI_OEM_ID_SIZE +1];
+ char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
+ u32 oem_revision;
+ unsigned int (*get_rate)(unsigned int cpu);
+};
+
+/* CPPC workaround for get_rate callback */
+unsigned int (*cppc_wa_get_rate)(unsigned int cpu);
+
/*
* These structs contain information parsed from per CPU
* ACPI _CPC structures.
@@ -334,6 +344,9 @@ static unsigned int cppc_cpufreq_get_rate(unsigned int
cpunum)
struct cppc_cpudata *cpu = all_cpu_data[cpunum];
int ret;
+ if (cppc_wa_get_rate)
+ return cppc_wa_get_rate(cpunum);
+
ret = cppc_get_perf_ctrs(cpunum, _ctrs_t0);
if (ret)
return ret;
@@ -357,6 +370,61 @@ static unsigned int cppc_cpufreq_get_rate(unsigned int
cpunum)
.name = "cppc_cpufreq",
};
+/*
+ * HISI platform does not support delivered performance counter and
+ * reference performance counter. It can calculate the performance using the
+ * platform specific mechanism. We reuse the desired performance register to
+ * store the real performance calculated by the platform.
+ */
+static unsigned int hisi_cppc_cpufreq_get_rate(unsigned int cpunum)
+{
+ struct cppc_cpudata *cpudata = all_cpu_data[cpunum];
+ u64 desired_perf;
+ int ret;
+
+ ret = cppc_get_desired_perf(cpunum, _perf);
+ if (ret < 0)
+ return -EIO;
+
+ return cppc_cpufreq_perf_to_khz(cpudata, desired_perf);
+}
+
+static struct cppc_workaround_info wa_info[] = {
+ {
+ .oem_id = "HISI ",
+ .oem_table_id = "HIP07 ",
+ .oem_revision = 0,
+ .get_rate = hisi_cppc_cpufreq_get_rate,
+ }, {
+ .oem_id = "HISI ",
+ .oem_table_id = "HIP08 ",
+ .oem_revision = 0,
+ .get_rate = hisi_cppc_cpufreq_get_rate,
+ }
+};
+
+static int cppc_check_workaround(void)
+{
+ struct acpi_table_header *tbl;
+ acpi_status status = AE_OK;
+ int i;
+
+ status = acpi_get_table(ACPI_SIG_PCCT, 0, );
+ if (ACPI_FAILURE(status) || !tbl)
+ return -EINVAL;
+
+ for (i = 0; i < ARRAY_SIZE(wa_info); i++) {
+ if (!memcmp(wa_info[i].oem_id, tbl->oem_id, ACPI_OEM_ID_SIZE) &&
+ !memcmp(wa_info[i].oem_table_id, tbl->oem_table_id,
ACPI_OEM_TABLE_ID_SIZE) &&
+ wa_info[i].oem_revision == tbl->oem_revision) {
+ cppc_wa_get_rate = wa_info[i].get_rate;
+ return 0;
+ }
+ }
+
+ return -ENODEV;
+}
+
static int __init cppc_cpufreq_init(void)
{
int i, ret = 0;
@@ -386,6 +454,8 @@ static int __init cppc_cpufreq_init(void)
goto out;
}
+ cppc_check_workaround();
+
ret = cpufreq_register_driver(_cpufreq_driver);
if (ret)
goto out;
--
1.7.12.4
Re: [PATCH] f2fs: do not use mutex lock in atomic context
On Wed, Feb 13, 2019 at 11:25:31AM +0800, Chao Yu wrote:
> On 2019/2/4 16:06, Sahitya Tummala wrote:
> > Fix below warning coming because of using mutex lock in atomic context.
> >
> > BUG: sleeping function called from invalid context at
> > kernel/locking/mutex.c:98
> > in_atomic(): 1, irqs_disabled(): 0, pid: 585, name: sh
> > Preemption disabled at: __radix_tree_preload+0x28/0x130
> > Call trace:
> > dump_backtrace+0x0/0x2b4
> > show_stack+0x20/0x28
> > dump_stack+0xa8/0xe0
> > ___might_sleep+0x144/0x194
> > __might_sleep+0x58/0x8c
> > mutex_lock+0x2c/0x48
> > f2fs_trace_pid+0x88/0x14c
> > f2fs_set_node_page_dirty+0xd0/0x184
> >
> > Do not use f2fs_radix_tree_insert() to avoid doing cond_resched() with
> > spin_lock() acquired.
> >
> > Signed-off-by: Sahitya Tummala
> > ---
> > fs/f2fs/trace.c | 20 +---
> > 1 file changed, 13 insertions(+), 7 deletions(-)
> >
> > diff --git a/fs/f2fs/trace.c b/fs/f2fs/trace.c
> > index ce2a5eb..d0ab533 100644
> > --- a/fs/f2fs/trace.c
> > +++ b/fs/f2fs/trace.c
> > @@ -14,7 +14,7 @@
> > #include "trace.h"
> >
> > static RADIX_TREE(pids, GFP_ATOMIC);
> > -static struct mutex pids_lock;
> > +static spinlock_t pids_lock;
> > static struct last_io_info last_io;
> >
> > static inline void __print_last_io(void)
> > @@ -58,23 +58,29 @@ void f2fs_trace_pid(struct page *page)
> >
> > set_page_private(page, (unsigned long)pid);
> >
> > +retry:
> > if (radix_tree_preload(GFP_NOFS))
> > return;
> >
> > - mutex_lock(_lock);
> > + spin_lock(_lock);
> > p = radix_tree_lookup(, pid);
> > if (p == current)
> > goto out;
> > if (p)
> > radix_tree_delete(, pid);
> >
> > - f2fs_radix_tree_insert(, pid, current);
> > + if (radix_tree_insert(, pid, current)) {
> > + spin_unlock(_lock);
> > + radix_tree_preload_end();
> > + cond_resched();
> > + goto retry;
> > + }
> >
> > trace_printk("%3x:%3x %4x %-16s\n",
> > MAJOR(inode->i_sb->s_dev), MINOR(inode->i_sb->s_dev),
> > pid, current->comm);
>
> Hi Sahitya,
>
> Can trace_printk sleep? For safety, how about moving it out of spinlock?
>
Hi Chao,
Yes, trace_printk() is safe to use in atomic context (unlike printk).
Thanks,
Sahitya.
> Thanks,
>
> > out:
> > - mutex_unlock(_lock);
> > + spin_unlock(_lock);
> > radix_tree_preload_end();
> > }
> >
> > @@ -119,7 +125,7 @@ void f2fs_trace_ios(struct f2fs_io_info *fio, int flush)
> >
> > void f2fs_build_trace_ios(void)
> > {
> > - mutex_init(_lock);
> > + spin_lock_init(_lock);
> > }
> >
> > #define PIDVEC_SIZE128
> > @@ -147,7 +153,7 @@ void f2fs_destroy_trace_ios(void)
> > pid_t next_pid = 0;
> > unsigned int found;
> >
> > - mutex_lock(_lock);
> > + spin_lock(_lock);
> > while ((found = gang_lookup_pids(pid, next_pid, PIDVEC_SIZE))) {
> > unsigned idx;
> >
> > @@ -155,5 +161,5 @@ void f2fs_destroy_trace_ios(void)
> > for (idx = 0; idx < found; idx++)
> > radix_tree_delete(, pid[idx]);
> > }
> > - mutex_unlock(_lock);
> > + spin_unlock(_lock);
> > }
> >
>
--
--
Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
[PATCH 1/1] dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings
From: Shun-Chih Yu
Document the devicetree bindings for MediaTek Command-Queue DMA controller
which could be found on MT6765 SoC or other similar Mediatek SoCs.
Change-Id: I9736c8cac9be160358feeab935fabaffc5730519
Signed-off-by: Shun-Chih Yu
---
.../devicetree/bindings/dma/mtk-cqdma.txt | 31
1 file changed, 31 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/mtk-cqdma.txt
diff --git a/Documentation/devicetree/bindings/dma/mtk-cqdma.txt
b/Documentation/devicetree/bindings/dma/mtk-cqdma.txt
new file mode 100644
index 000..fb12927
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/mtk-cqdma.txt
@@ -0,0 +1,31 @@
+MediaTek Command-Queue DMA Controller
+==
+
+Required properties:
+
+- compatible: Must be "mediatek,mt6765-cqdma" for MT6765.
+- reg: Should contain the base address and length for each channel.
+- interrupts: Should contain references to the interrupts for each channel.
+- clocks: Should be the clock specifiers corresponding to the entry in
+ clock-names property.
+- clock-names: Should contain "cqdma" entries.
+- dma-channels: The number of DMA channels supported by the controller.
+- dma-requests: The number of DMA request supported by the controller.
+- #dma-cells: The length of the DMA specifier, must be <1>. This one cell
+ in dmas property of a client device represents the channel
+ number.
+Example:
+
+cqdma: dma-controller@10212000 {
+ compatible = "mediatek,mt6765-cqdma";
+ reg = <0 0x10212000 0 0x1000>;
+ interrupts = ,
+ ;
+ clocks = < CLK_IFR_CQ_DMA>;
+ clock-names = "cqdma";
+ dma-channels = <2>;
+ dma-requests = <32>;
+ #dma-cells = <1>;
+ };
+
+DMA clients must use the format described in dma/dma.txt file.
--
1.7.9.5
[PATCH] dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings
Add document the devicetree bindings for MediaTek Command-Queue DMA controller.
BUSINESS SOLUTION INVESTMENT FUNDING
Hello, Greetings, I represent business group in Middle East looking for projects to fund; we seek any business that will guaranty a safe and secure return on investments. Alternative powers, movies, start up companies etc. We are also looking for commercial building projects, hotels, casino, strip malls etc. If you have a project that differs from these and current budget is 2 over $ 40M, Write us and Provide Executive Summary and project details. I want to create a relationship with you. I represent the leading provider of alternative funding solutions for a busines investment project. Visit us at Site: http://saharapcc.com I'd like to provide capital to you. If you have a project that differs from these and current budget is over $40M, Write us and Provide Executive Summary and project details. (a)100% financing is available. (b)Possible JV partnerships or 100% loans. (c)Project must be over $20M total budget. May I send you more information? Best regards H.E. Eng. Abdulaziz Bin Abdullah Al-Zamil —— Chairman Board of Directors Sahara Petrochemical Ltd.
linux-next: Signed-off-by missing for commit in the cifs tree
Hi all,
Commit
375808983c63 ("smb3: request more credits on tree connect")
is missing a Signed-off-by from its author and committer.
--
Cheers,
Stephen Rothwell
pgpfgU8K4lhss.pgp
Description: OpenPGP digital signature
Re: [PATCH] fs/coda: get rid of CODA_ALLOC()
On Thu, Feb 14, 2019 at 08:04:43AM +0100, Julia Lawall wrote: > > > On Thu, 14 Feb 2019, Dan Carpenter wrote: > > > These days we have kvzalloc() so we can delete CODA_ALLOC(). > > Maybe it would be better to get rid fo CODA_FREE as well? I feel like that's a separate issue. The CODA_FREE() macro already uses kvfree() so it doesn't bother me as much as the CODA_ALLOC() macro. regards, dan carpenter
linux-next: Signed-off-by missing for commit in the leaks tree
Hi Tobin,
Commit
5d06b3fc8e61 ("leaking_addresses: Completely remove --version flag")
is missing a Signed-off-by from its author and committer.
--
Cheers,
Stephen Rothwell
pgpBYgpTieVp0.pgp
Description: OpenPGP digital signature
Re: [RESEND PATCH v4,1/3] media: dt-bindings: media: add 'assigned-clocks' to vcodec examples
Hi Yunfei Dong,
Why is this series resent? Patches 1 and 3 have been merged in our
media master tree already.
Regards,
Hans
On 2/14/19 3:24 AM, Yunfei Dong wrote:
> Fix MTK binding document for MT8173 dtsi changed in order
> to use standard CCF interface.
> MT8173 SoC from Mediatek.
>
> Signed-off-by: Yunfei Dong
> Signed-off-by: Qianqian Yan
> Reviewed-by: Rob Herring
> ---
> .../devicetree/bindings/media/mediatek-vcodec.txt | 13 +
> 1 file changed, 13 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/media/mediatek-vcodec.txt
> b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt
> index 2a615d8..b6b5dde 100644
> --- a/Documentation/devicetree/bindings/media/mediatek-vcodec.txt
> +++ b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt
> @@ -66,6 +66,15 @@ vcodec_dec: vcodec@1600 {
>"vencpll",
>"venc_lt_sel",
>"vdec_bus_clk_src";
> +assigned-clocks = < CLK_TOP_VENC_LT_SEL>,
> + < CLK_TOP_CCI400_SEL>,
> + < CLK_TOP_VDEC_SEL>,
> + < CLK_APMIXED_VCODECPLL>,
> + < CLK_APMIXED_VENCPLL>;
> +assigned-clock-parents = < CLK_TOP_VCODECPLL_370P5>,
> + < CLK_TOP_UNIVPLL_D2>,
> + < CLK_TOP_VCODECPLL>;
> +assigned-clock-rates = <0>, <0>, <0>, <148200>, <8>;
>};
>
>vcodec_enc: vcodec@18002000 {
> @@ -105,4 +114,8 @@ vcodec_dec: vcodec@1600 {
>"venc_sel",
>"venc_lt_sel_src",
>"venc_lt_sel";
> +assigned-clocks = < CLK_TOP_VENC_SEL>,
> + < CLK_TOP_VENC_LT_SEL>;
> +assigned-clock-parents = < CLK_TOP_VENCPLL_D2>,
> + < CLK_TOP_UNIVPLL1_D2>;
>};
>
Re: [PATCH v6 4/4] perf/smmuv3_pmu: Enable HiSilicon Erratum 162001800 quirk
On 2019/2/4 20:13, Shameer Kolothum wrote: > HiSilicon erratum 162001800 describes the limitation of > SMMUv3 PMCG implementation on HiSilicon Hip08 platforms. > > On these platforms, the PMCG event counter registers > (SMMU_PMCG_EVCNTRn) are read only and as a result it > is not possible to set the initial counter period value > on event monitor start. > > To work around this, the current value of the counter > is read and used for delta calculations. OEM information > from ACPI header is used to identify the affected hardware > platforms. > > Signed-off-by: Shameer Kolothum > --- > drivers/acpi/arm64/iort.c | 16 ++- > drivers/perf/arm_smmuv3_pmu.c | 48 > --- > include/linux/acpi_iort.h | 1 + > 3 files changed, 57 insertions(+), 8 deletions(-) For this patch, Reviewed-by: Hanjun Guo Thanks Hanjun
[PATCH v4] arm64: Add workaround for Fujitsu A64FX erratum 010001
Hi guys,
Thanks for your comments.
I am sending the revised patch, version 4, which includes a whole
description of the patch.
This patch adds a workaround for Fujitsu A64FX erratum 010001
There are some discussions on former versions, as follows:
[PATCH] arm64 memory accesses may cause undefined fault on Fujitsu-A64FX
https://lkml.org/lkml/2019/1/18/403
[PATCH v2 0/1] arm64: Add workaround for Fujitsu A64FX erratum 010001
https://lkml.org/lkml/2019/1/22/137
[PATCH v2 1/1] arm64: Add workaround for Fujitsu A64FX erratum 010001
https://lkml.org/lkml/2019/1/22/138
[PATCH v3 0/1] arm64: Add workaround for Fujitsu A64FX erratum 010001
https://www.spinics.net/lists/arm-kernel/msg703111.html
[v3,1/1] Arm64: Add workaround for Fujitsu A64FX erratum 010001
https://patchwork.kernel.org/patch/10786139/
Please merge this patch.
Note that this patch is for the linux-5.0-rc2 which set TCR_ELx.NFD1 to '1'
only once in the boot sequence and does not set TCR_ELx.NFD0.
If the newer kernel handles TCR_ELx.{NFD0,NFD1} in different way,
I will update the patch as soon as possible.
Changes since [v3]
* Add description of the patch.
* Add dependency to Kconfig.
- Set default value of FUJITSU_ERRATUM_010001 depends on RANDOMIZE_BASE.
Changes since [v2]
* Change TCR_ELx.NFD1.
- Set TCR_ELx.NFD1 to 0 when entry kernel.
- Set TCR_ELx.NFD1 to 1 when exit kernel.
Changes since [v1]
* Use the errata framework to work around for Fujitsu A64FX erratum 010001.
On the Fujitsu-A64FX cores ver(1.0, 1.1), memory access may
cause an undefined fault (Data abort, DFSC=0b11).
This fault occurs under a specific hardware condition when a
load/store instruction performs an address translation.
Any load/store instruction, except non-fault access
including Armv8 and SVE might cause this undefined fault.
Since this erratum occurs only when TCR_ELx.NFD1=1,
I keep TCR_ELx.NFD1=0 during EL1/EL2.
By doing above, the erratum occurs only in EL0.
I deal with this erratum in EL0 by a new fault handler
which ignores this undefined fault.
Signed-off-by: Zhang Lei
---
Documentation/arm64/silicon-errata.txt | 1 +
arch/arm64/Kconfig | 23 +++
arch/arm64/include/asm/cpucaps.h | 3 ++-
arch/arm64/include/asm/cputype.h | 4
arch/arm64/kernel/cpu_errata.c | 8
arch/arm64/kernel/entry.S | 16
arch/arm64/mm/fault.c | 16 +++-
arch/arm64/mm/proc.S | 20
8 files changed, 89 insertions(+), 2 deletions(-)
diff --git a/Documentation/arm64/silicon-errata.txt
b/Documentation/arm64/silicon-errata.txt
index 1f09d04..26d64e9 100644
--- a/Documentation/arm64/silicon-errata.txt
+++ b/Documentation/arm64/silicon-errata.txt
@@ -80,3 +80,4 @@ stable kernels.
| Qualcomm Tech. | Falkor v1 | E1009 |
QCOM_FALKOR_ERRATUM_1009|
| Qualcomm Tech. | QDF2400 ITS | E0065 |
QCOM_QDF2400_ERRATUM_0065 |
| Qualcomm Tech. | Falkor v{1,2} | E1041 |
QCOM_FALKOR_ERRATUM_1041|
+| Fujitsu| A64FX | E#010001| FUJITSU_ERRATUM_010001
|
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index a4168d3..7c76c66 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -643,6 +643,29 @@ config QCOM_FALKOR_ERRATUM_E1041
If unsure, say Y.
+config FUJITSU_ERRATUM_010001
+ bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
+depends on RANDOMIZE_BASE
+default RANDOMIZE_BASE
+ help
+ This option adds workaround for Fujitsu-A64FX erratum E#010001.
+ On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
accesses
+ may cause undefined fault (Data abort, DFSC=0b11).
+ This fault occurs under a specific hardware condition when a
load/store
+ instruction performs an address translation using:
+ case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
+ case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
+ case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
+ case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
+
+ The workaround is to set '0' to TCR_ELx.NFD1 at kernel-entry,
+ to set '1' at kernel-exit. And also replace the fault handler
+ for Data abort DFSC=0b11 with a new fault handler to ignore this
+ undefined fault.
+ The workaround only affect the Fujitsu-A64FX.
+
+ If unsure, say Y.
+
endmenu
diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h
index 82e9099..3a0b375 100644
--- a/arch/arm64/include/asm/cpucaps.h
+++ b/arch/arm64/include/asm/cpucaps.h
@@ -60,7 +60,8 @@
#define ARM64_HAS_ADDRESS_AUTH_IMP_DEF 39
#define ARM64_HAS_GENERIC_AUTH_ARCH40
#define ARM64_HAS_GENERIC_AUTH_IMP_DEF 41
+#define ARM64_WORKAROUND_FUJITSU_A64FX_011 42
-#define ARM64_NCAPS
Re: [PATCH -next] swiotlb: drop pointless static qualifier in swiotlb_dma_supported()
On Thu, Feb 14, 2019 at 01:41:47AM +, YueHaibing wrote: > There is no need to have the 'struct dentry *d_swiotlb_usage' variable > static since new value always be assigned before use it. FYI, this is in swiotlb_create_debugfs, not swiotlb_dma_supported.
Re: [PATCH net-next 2/2] net: hns3: add fixup handle for hns3 driver
在 2019/2/14 12:08, Florian Fainelli 写道:
>
>
> On 2/13/2019 8:31 PM, Jian Shen wrote:
>> The default led configuration of marvell 88E1510 is not fit
>> for hns3 driver, this patch fixes it.
>>
>> Signed-off-by: Jian Shen
>> ---
>> .../net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.c | 19
>> +++
>> 1 file changed, 19 insertions(+)
>>
>> diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.c
>> b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.c
>> index 84f2878..4c8346e 100644
>> --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.c
>> +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.c
>> @@ -2,6 +2,7 @@
>> // Copyright (c) 2016-2017 Hisilicon Limited.
>>
>> #include
>> +#include
>> #include
>>
>> #include "hclge_cmd.h"
>> @@ -125,6 +126,13 @@ static int hclge_mdio_read(struct mii_bus *bus, int
>> phyid, int regnum)
>> return le16_to_cpu(mdio_cmd->data_rd);
>> }
>>
>> +static int hclge_phy_marvell_fixup(struct phy_device *phydev)
>> +{
>> +phydev->dev_flags |= MARVELL_PHY_M1510_HNS3_LEDS;
>> +
>> +return 0;
>> +}
>> +
>> int hclge_mac_mdio_config(struct hclge_dev *hdev)
>> {
>> struct hclge_mac *mac = >hw.mac;
>> @@ -168,6 +176,15 @@ int hclge_mac_mdio_config(struct hclge_dev *hdev)
>> mac->phydev = phydev;
>> mac->mdio_bus = mdio_bus;
>>
>> +/* register the PHY board fixup (for Marvell 88E1510) */
>> +ret = phy_register_fixup_for_uid(MARVELL_PHY_ID_88E1510,
>> + MARVELL_PHY_ID_MASK,
>> + hclge_phy_marvell_fixup);
>> +/* we can live without it, so just issue a warning */
>> +if (ret)
>> +dev_warn(>pdev->dev,
>> + "Cannot register PHY board fixup\n");
>
> You don't need to register a fixup for passing your flags, you can do
> that at the time you attach to the PHY:
>
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/linux/phy.h#n945
>
>
Thanks, will fix it in next version.
>> +
>> return 0;
>> }
>>
>> @@ -240,6 +257,8 @@ void hclge_mac_disconnect_phy(struct hnae3_handle
>> *handle)
>> if (!phydev)
>> return;
>>
>> +phy_unregister_fixup_for_uid(MARVELL_PHY_ID_88E1510,
>> + MARVELL_PHY_ID_MASK);
>> phy_disconnect(phydev);
>> }
>>
>>
>
Re: [PATCH 1/3] mtd: spi-nor: add Global Block Unlock support
On 07/17/2018 07:28 PM, Tudor Ambarus wrote: > We can't determine this purely by manufacturer type and it's not > autodetectable by anything like SFDP, so make a new flag for it: > UNLOCK_GLOBAL_BLOCK. > > Note that the Global Block Unlock command has different names > depending on the manufacturer, but always the same command value: > 0x98. Macronix's MX25U12835F names it Gang Block Unlock, > Winbound's W25Q128FV names it Global Block Unlock and > Microchip's SST26VF064B names it Global Block Protection Unlock. > > Based on initial work done by Anurag Kumar Vulisha: > https://patchwork.kernel.org/patch/7611271/ Time passed and now I think that this should be part of the individual block lock support, as an optimization when one wants to unlock the entire flash memory. Will rework it. Cheers, ta
Re: [PATCH] mm: Fix the pgtable leak
On Wed, Feb 13, 2019 at 01:24:58PM +0100, Michal Hocko wrote:
> On Wed 13-02-19 21:12:00, Minchan Kim wrote:
> > On Wed, Feb 13, 2019 at 01:03:30PM +0100, Michal Hocko wrote:
> > > On Wed 13-02-19 20:29:00, Minchan Kim wrote:
> > > > [1] was backported to v4.9 stable tree but it introduces pgtable
> > > > memory leak because with fault retrial, preallocated pagetable
> > > > could be leaked in second iteration.
> > > > To fix the problem, this patch backport [2].
> > > >
> > > > [1] 5cf3e5ff95876, mm, memcg: fix reclaim deadlock with writeback
> > > > [2] b0b9b3df27d10, mm: stop leaking PageTables
> > > >
> > > > Fixes: 5cf3e5ff95876 ("mm, memcg: fix reclaim deadlock with writeback")
> > > > Cc: Johannes Weiner
> > > > Cc: Kirill A. Shutemov
> > > > Cc: Michal Hocko
> > > > Cc: Andrew Morton
> > > > Cc: Hugh Dickins
> > > > Cc: Liu Bo
> > > > Cc: [4.9]
> > > > Signed-off-by: Minchan Kim
> > >
> > > Thanks for catching this dependency. Do I assume it correctly that this
> > > is stable-4.9 only?
> >
> > I have no idea how I could find it automatically that a stable patch of
> > linus tree is spread out with several stable trees(Hope Greg has an
> > answer). I just checked 4.4 longterm kernel and couldn't find it in there.
>
> See http://lkml.kernel.org/r/20190115174036.ga24...@dhcp22.suse.cz
>
> But my question was more about "this is a stable only thing"? It was not
> obvious from the subject so I wanted to be sure that I am not missing
> anything.
Yub, I think only 4.9 stable tree need to be fixed because Hugh's patch was
in there since v4.10.
Thanks.
Re: [PATCH net-next 1/2] net: phy: marvell: add new m88e1510 LED configuration
在 2019/2/14 12:06, Florian Fainelli 写道:
>
>
> On 2/13/2019 8:31 PM, Jian Shen wrote:
>> The default m88e1510 LED configuration is 0x1177, used LED[0]
>> for 1000M link, LED[1] for 100M link, and LED[2] for active.
>> But for our boards, we want to use 0x1040, which use LED[0] for
>> link, and LED[1] for active.
>>
>> This patch adds a new m88e1510 LED configuration for it.
>
> There appears to be a precedent with the DNS323 flag that was defined
> for the same purpose, but this unfortunately does not scale we cannot
> have every new platform come up with its own LED configuration without
> having a more structured approach to representing the LED configuration.
>
> Maybe we can encode the desired LED behavior in a more generic way and
> utilize the 32 flag bits available to denote a selection, e.g.:
>
> MARVELL_PHY_FLAG_LED0_100MBIT(3)
> MARVELL_PHY_FLAG_LED0_1000M BIT(4)
>
> etc.
>
> or maybe even better would be to expose the LEDs using the standard LEDs
> class subsystem and allow configuring different triggers. We have some
> amount of support for PHY LEDs already in tree, but AFAIR what we do not
> have support for is a "hardware blinking" trigger which those LEDs are.
>
Thanks Florian.
I agree that we should use a generic way.
Maybe I understood incorrectly, for "utilize the 32 flag bits available to
denote a selection",
do you mean to define a serial flags for each usage of each led ?
For each led can be configured to several usages, include link/10M link/100M
link/1000M link/active/...,
it needs a lot bits for these combination, e.g:
#define MARVELL_PHY_FLAG_LED0_LINK BIT(2)
#define MARVELL_PHY_FLAG_LED0_LINK_100M BIT(3)
#define MARVELL_PHY_FLAG_LED0_LINK_1000MBIT(4)
#define MARVELL_PHY_FLAG_LED0_ACTIVEBIT(5)
#define MARVELL_PHY_FLAG_LED1_LINK BIT(6)
#define MARVELL_PHY_FLAG_LED1_LINK_100M BIT(7)
#define MARVELL_PHY_FLAG_LED1_LINK_1000MBIT(8)
#define MARVELL_PHY_FLAG_LED1_ACTIVEBIT(9)
...
Jian Shen
>>
>> Signed-off-by: Jian Shen
>> ---
>> drivers/net/phy/marvell.c | 22 +-
>> include/linux/marvell_phy.h | 1 +
>> 2 files changed, 22 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
>> index 3ccba37..c195286 100644
>> --- a/drivers/net/phy/marvell.c
>> +++ b/drivers/net/phy/marvell.c
>> @@ -128,6 +128,10 @@
>> #define MII_PHY_LED_CTRL16
>> #define MII_88E1121_PHY_LED_DEF 0x0030
>> #define MII_88E1510_PHY_LED_DEF 0x1177
>> +#define MII_88E1510_PHY_HNS3_LED_DEF0x1040
>> +
>> +#define MII_88E1510_PHY_LED_POLARITY_CTRL 0x11
>> +#define MII_88E1510_PHY_HNS3_LED_POLARITY 0x4415
>>
>> #define MII_M1011_PHY_STATUS0x11
>> #define MII_M1011_PHY_STATUS_1000 0x8000
>> @@ -619,12 +623,19 @@ static void marvell_config_led(struct phy_device
>> *phydev)
>> def_config = MII_88E1121_PHY_LED_DEF;
>> break;
>> /* Default PHY LED config:
>> + * For hns3:
>> + * LED[0] .. Link
>> + * LED[1] .. Activity
>> + * For others:
>> * LED[0] .. 1000Mbps Link
>> * LED[1] .. 100Mbps Link
>> * LED[2] .. Blink, Activity
>> */
>> case MARVELL_PHY_FAMILY_ID(MARVELL_PHY_ID_88E1510):
>> -def_config = MII_88E1510_PHY_LED_DEF;
>> +if (phydev->dev_flags & MARVELL_PHY_M1510_HNS3_LEDS)
>> +def_config = MII_88E1510_PHY_HNS3_LED_DEF;
>> +else
>> +def_config = MII_88E1510_PHY_LED_DEF;
>> break;
>> default:
>> return;
>> @@ -634,6 +645,15 @@ static void marvell_config_led(struct phy_device
>> *phydev)
>>def_config);
>> if (err < 0)
>> phydev_warn(phydev, "Fail to config marvell phy LED.\n");
>> +
>> +if (phydev->dev_flags & MARVELL_PHY_M1510_HNS3_LEDS) {
>> +err = phy_write_paged(phydev, MII_MARVELL_LED_PAGE,
>> + MII_88E1510_PHY_LED_POLARITY_CTRL,
>> + MII_88E1510_PHY_HNS3_LED_POLARITY);
>> +if (err < 0)
>> +phydev_warn(phydev,
>> +"Fail to config marvell phy LED
>> polarity.\n");
>> +}
>> }
>>
>> static int marvell_config_init(struct phy_device *phydev)
>> diff --git a/include/linux/marvell_phy.h b/include/linux/marvell_phy.h
>> index 1eb6f24..99e0bbb 100644
>> --- a/include/linux/marvell_phy.h
>> +++ b/include/linux/marvell_phy.h
>> @@ -32,5 +32,6 @@
>> /* struct phy_device dev_flags definitions */
>> #define MARVELL_PHY_M1145_FLAGS_RESISTANCE 0x0001
>> #define MARVELL_PHY_M1118_DNS323_LEDS 0x0002
>> +#define MARVELL_PHY_M1510_HNS3_LEDS 0x0004
>>
>> #endif /* _MARVELL_PHY_H */
>>
>
Re: [PATCH] mm: Fix the pgtable leak
On Wed, Feb 13, 2019 at 02:36:24PM +0100, Greg KH wrote:
> On Wed, Feb 13, 2019 at 08:29:00PM +0900, Minchan Kim wrote:
> > [1] was backported to v4.9 stable tree but it introduces pgtable
> > memory leak because with fault retrial, preallocated pagetable
> > could be leaked in second iteration.
> > To fix the problem, this patch backport [2].
> >
> > [1] 5cf3e5ff95876, mm, memcg: fix reclaim deadlock with writeback
>
> This is really commit 63f3655f9501 ("mm, memcg: fix reclaim deadlock
> with writeback") which was in 4.9.152, 4.14.94, 4.19.16, and 4.20.3 as
> well as 5.0-rc2.
Since 4.10, we has [2] so it should be okay other (tree > 4.10)
>
> > [2] b0b9b3df27d10, mm: stop leaking PageTables
>
> This commit was in 4.10, so I am guessing that this really is just a
> backport of that commit?
Yub.
>
> If so, it's not the full backport, why not take the whole thing? Why
> only cherry-pick one chunk of it? Why do we not need the other parts?
Because [2] actually aims for fixing [3] which was introduced at 4.10.
Since then, [1] relies on the chunk I sent. Thus we don't need other part
for 4.9.
[3] 953c66c2b22a ("mm: THP page cache support for ppc64")
Thanks.
[PATCH v4 2/3] PCI: altera: Enable driver on ARM64
Enable PCIE_ALTERA on ARM64 platform. Signed-off-by: Ley Foon Tan --- drivers/pci/controller/Kconfig |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig index 6671946..6012f30 100644 --- a/drivers/pci/controller/Kconfig +++ b/drivers/pci/controller/Kconfig @@ -175,7 +175,7 @@ config PCIE_IPROC_MSI config PCIE_ALTERA bool "Altera PCIe controller" - depends on ARM || NIOS2 || COMPILE_TEST + depends on ARM || NIOS2 || ARM64 || COMPILE_TEST help Say Y here if you want to enable PCIe controller support on Altera FPGA. -- 1.7.1
[PATCH v4 0/3] Add Stratix 10 PCIe Root Port support
Add PCIe Root Port support for Stratix 10 device and also update device tree binding documentation. v3 -> v4: - - Separate Kconfig change to a patch - Change cast to mask v2 -> v3: - - Rename Stratix10 to Stratix 10. - Change bool s10_flag to enum version. v1 -> v2: - - Add define S10_TLP_FMTTYPE_* macros. - Remove initialize structure members to NULL/zero. - Rename *_funcs to *_data. - Update comment and fix coding style warning from checkpatch.pl. - Rename StratixXX to stratix10. History: [v1]: https://lkml.org/lkml/2018/12/26/68 [v2]: https://lkml.org/lkml/2018/12/31/46 [v3]: https://lkml.org/lkml/2019/1/2/16 Ley Foon Tan (3): PCI: altera: Add Stratix 10 PCIe support PCI: altera: Enable driver on ARM64 dt-bindings: PCI: altera: Add altr,pcie-root-port-2.0 .../devicetree/bindings/pci/altera-pcie.txt|4 +- drivers/pci/controller/Kconfig |2 +- drivers/pci/controller/pcie-altera.c | 246 ++-- 3 files changed, 226 insertions(+), 26 deletions(-)
[PATCH v4 3/3] dt-bindings: PCI: altera: Add altr,pcie-root-port-2.0
Add support for altr,pcie-root-port-2.0. Signed-off-by: Ley Foon Tan Reviewed-by: Rob Herring --- .../devicetree/bindings/pci/altera-pcie.txt|4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/altera-pcie.txt b/Documentation/devicetree/bindings/pci/altera-pcie.txt index 6c396f1..816b244 100644 --- a/Documentation/devicetree/bindings/pci/altera-pcie.txt +++ b/Documentation/devicetree/bindings/pci/altera-pcie.txt @@ -1,11 +1,13 @@ * Altera PCIe controller Required properties: -- compatible : should contain "altr,pcie-root-port-1.0" +- compatible : should contain "altr,pcie-root-port-1.0" or "altr,pcie-root-port-2.0" - reg: a list of physical base address and length for TXS and CRA. + For "altr,pcie-root-port-2.0", additional HIP base address and length. - reg-names: must include the following entries: "Txs": TX slave port region "Cra": Control register access region + "Hip": Hard IP region (if "altr,pcie-root-port-2.0") - interrupts: specifies the interrupt source of the parent interrupt controller. The format of the interrupt specifier depends on the parent interrupt controller. -- 1.7.1
[PATCH v4 1/3] PCI: altera: Add Stratix 10 PCIe support
Add PCIe Root Port support for Stratix 10 device.
Main differences:
- HIP interface to access Root Port configuration register.
- TLP programming flow:
- One REG0 register
- Don't need to check alignment
Signed-off-by: Ley Foon Tan
---
drivers/pci/controller/pcie-altera.c | 246 ++
1 files changed, 222 insertions(+), 24 deletions(-)
diff --git a/drivers/pci/controller/pcie-altera.c
b/drivers/pci/controller/pcie-altera.c
index 7d05e51..76bb6a6 100644
--- a/drivers/pci/controller/pcie-altera.c
+++ b/drivers/pci/controller/pcie-altera.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -37,7 +38,12 @@
#define RP_LTSSM_MASK 0x1f
#define LTSSM_L0 0xf
-#define PCIE_CAP_OFFSET0x80
+#define S10_RP_TX_CNTRL0x2004
+#define S10_RP_RXCPL_REG 0x2008
+#define S10_RP_RXCPL_STATUS0x200C
+#define S10_RP_CFG_ADDR(pcie, reg) \
+ (((pcie)->hip_base) + (reg) + (1 << 20))
+
/* TLP configuration type 0 and 1 */
#define TLP_FMTTYPE_CFGRD0 0x04/* Configuration Read Type 0 */
#define TLP_FMTTYPE_CFGWR0 0x44/* Configuration Write Type 0 */
@@ -49,18 +55,19 @@
#define RP_DEVFN 0
#define TLP_REQ_ID(bus, devfn) (((bus) << 8) | (devfn))
#define TLP_CFGRD_DW0(pcie, bus) \
-bus == pcie->root_bus_nr) ? TLP_FMTTYPE_CFGRD0 \
- : TLP_FMTTYPE_CFGRD1) << 24) | \
- TLP_PAYLOAD_SIZE)
+ bus == pcie->root_bus_nr) ? pcie->pcie_data->cfgrd0 \
+ : pcie->pcie_data->cfgrd1) << 24) | \
+ TLP_PAYLOAD_SIZE)
#define TLP_CFGWR_DW0(pcie, bus) \
-bus == pcie->root_bus_nr) ? TLP_FMTTYPE_CFGWR0 \
- : TLP_FMTTYPE_CFGWR1) << 24) | \
- TLP_PAYLOAD_SIZE)
+ bus == pcie->root_bus_nr) ? pcie->pcie_data->cfgwr0 \
+ : pcie->pcie_data->cfgwr1) << 24) | \
+ TLP_PAYLOAD_SIZE)
#define TLP_CFG_DW1(pcie, tag, be) \
-(((TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be))
+ (((TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be))
#define TLP_CFG_DW2(bus, devfn, offset)\
(((bus) << 24) | ((devfn) << 16) | (offset))
#define TLP_COMP_STATUS(s) (((s) >> 13) & 7)
+#define TLP_BYTE_COUNT(s) (((s) >> 0) & 0xfff)
#define TLP_HDR_SIZE 3
#define TLP_LOOP 500
@@ -69,14 +76,43 @@
#define DWORD_MASK 3
+#define S10_TLP_FMTTYPE_CFGRD0 0x05
+#define S10_TLP_FMTTYPE_CFGRD1 0x04
+#define S10_TLP_FMTTYPE_CFGWR0 0x45
+#define S10_TLP_FMTTYPE_CFGWR1 0x44
+
+enum altera_pcie_version {
+ ALTERA_PCIE_V1 = 0,
+ ALTERA_PCIE_V2,
+};
+
struct altera_pcie {
struct platform_device *pdev;
- void __iomem*cra_base; /* DT Cra */
+ void __iomem*cra_base;
+ void __iomem*hip_base;
int irq;
u8 root_bus_nr;
struct irq_domain *irq_domain;
struct resource bus_range;
struct list_headresources;
+ const struct altera_pcie_data *pcie_data;
+};
+
+struct altera_pcie_data {
+ int (*tlp_read_pkt)(struct altera_pcie *pcie, u32 *value);
+ void (*tlp_write_pkt)(struct altera_pcie *pcie, u32 *headers,
+ u32 data, bool align);
+ bool (*get_link_status)(struct altera_pcie *pcie);
+ int (*rp_read_cfg)(struct altera_pcie *pcie, int where,
+ int size, u32 *value);
+ int (*rp_write_cfg)(struct altera_pcie *pcie, u8 bus, int where,
+ int size, u32 value);
+ enum altera_pcie_version version;
+ u32 cap_offset; /* PCIe capability structure register offset */
+ u32 cfgrd0;
+ u32 cfgrd1;
+ u32 cfgwr0;
+ u32 cfgwr1;
};
struct tlp_rp_regpair_t {
@@ -101,6 +137,15 @@ static bool altera_pcie_link_up(struct altera_pcie *pcie)
return !!((cra_readl(pcie, RP_LTSSM) & RP_LTSSM_MASK) == LTSSM_L0);
}
+static bool s10_altera_pcie_link_up(struct altera_pcie *pcie)
+{
+ void __iomem *addr = S10_RP_CFG_ADDR(pcie,
+ pcie->pcie_data->cap_offset +
+ PCI_EXP_LNKSTA);
+
+ return !!(readw(addr) & PCI_EXP_LNKSTA_DLLLA);
+}
+
/*
* Altera PCIe port uses BAR0 of RC's configuration space as the translation
* from PCI bus to native BUS. Entire DDR region is mapped into
RE: [PATCH V4 1/2] arm64: dts: freescale: imx8qxp: add cpu opp table
Hi, Viresh
Best Regards!
Anson Huang
> -Original Message-
> From: Viresh Kumar [mailto:viresh.ku...@linaro.org]
> Sent: 2019年2月14日 15:13
> To: Anson Huang
> Cc: robh...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org;
> s.ha...@pengutronix.de; ker...@pengutronix.de; feste...@gmail.com;
> mturque...@baylibre.com; sb...@kernel.org; Aisheng Dong
> ; Daniel Baluta ;
> devicet...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; linux-
> ker...@vger.kernel.org; linux-...@vger.kernel.org; dl-linux-imx i...@nxp.com>
> Subject: Re: [PATCH V4 1/2] arm64: dts: freescale: imx8qxp: add cpu opp
> table
>
> On 14-02-19, 01:54, Anson Huang wrote:
> > Add i.MX8QXP CPU opp table to support cpufreq.
> >
> > Signed-off-by: Anson Huang
> > ---
> > No change since V3.
> > ---
> > arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 25
> > +
> > 1 file changed, 25 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > index 4021f25..593e2db 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > @@ -34,6 +34,10 @@
> > reg = <0x0 0x0>;
> > enable-method = "psci";
> > next-level-cache = <_L2>;
> > + clocks = < IMX_A35_CLK>;
> > + clock-latency = <61036>;
>
> Who uses this value ? And why is it different from the one mentioned in the
> OPP table ?
Sorry, forgot to remove it. Will remove it in next version.
>
> > + #cooling-cells = <2>;
>
> clocks and cooling-cells must be defined for all the CPUs.
OK.
>
> > + operating-points-v2 = <_0_opp_table>;
> > };
> >
> > A35_1: cpu@1 {
> > @@ -42,6 +46,7 @@
> > reg = <0x0 0x1>;
> > enable-method = "psci";
> > next-level-cache = <_L2>;
> > + operating-points-v2 = <_0_opp_table>;
> > };
> >
> > A35_2: cpu@2 {
> > @@ -50,6 +55,7 @@
> > reg = <0x0 0x2>;
> > enable-method = "psci";
> > next-level-cache = <_L2>;
> > + operating-points-v2 = <_0_opp_table>;
> > };
> >
> > A35_3: cpu@3 {
> > @@ -58,6 +64,7 @@
> > reg = <0x0 0x3>;
> > enable-method = "psci";
> > next-level-cache = <_L2>;
> > + operating-points-v2 = <_0_opp_table>;
> > };
> >
> > A35_L2: l2-cache0 {
> > @@ -65,6 +72,24 @@
> > };
> > };
> >
> > + a35_0_opp_table: opp-table {
> > + compatible = "operating-points-v2";
> > + opp-shared;
> > +
> > + opp-9 {
> > + opp-hz = /bits/ 64 <9>;
> > + opp-microvolt = <100>;
> > + clock-latency-ns = <15>;
> > + };
> > +
> > + opp-12 {
> > + opp-hz = /bits/ 64 <12>;
> > + opp-microvolt = <110>;
> > + clock-latency-ns = <15>;
> > + opp-suspend;
>
> You want to go to a higher frequency on suspend ?
Yes, on most of i.MX SoCs, we always use highest frequency for suspend to reduce
the suspend/resume latency.
Thanks,
Anson.
>
> > + };
> > + };
> > +
> > gic: interrupt-controller@51a0 {
> > compatible = "arm,gic-v3";
> > reg = <0x0 0x51a0 0 0x1>, /* GIC Dist */
> > --
> > 2.7.4
>
> --
> viresh
Re: [PATCH v2 1/3] devicetree: bindings: bd718x7: document HW state related ROHM specific properties
Hello Angus, Glad to hear from you again =) On Wed, Feb 13, 2019 at 03:38:40PM -0800, Angus Ainslie wrote: > > > > Optional properties: > > - clock-output-names : Should contain name for output clock. > > +- rohm,reset-snvs-powered : Transfer BD718x7 to SNVS state at reset. > > + > > +The BD718x7 supports two different HW states as reset target states. > > States > > +are called as SNVS and READY. At READY state all the PMIC power outputs > > go > > +down and OTP is reload. At the SNVS state all other logic and external > > +devices apart from the SNVS power domain are shut off. Please refer to > > NXP > > +i.MX8 documentation for further information regarding SNVS state. When > > a > > +reset is done via SNVS state the PMIC OTP data is not reload. This > > cause > > + > > It looks like there is some text missing here. Actually, the "This cause" is a leftover from previous version. So nothings missing, just something extra :D But well spotted. I'll clean this up for next version! > > diff --git > > a/Documentation/devicetree/bindings/regulator/rohm,bd71837-regulator.txt > > b/Documentation/devicetree/bindings/regulator/rohm,bd71837-regulator.txt > > index 4b98ca26e61a..4a05cbf915ee 100644 > > --- > > a/Documentation/devicetree/bindings/regulator/rohm,bd71837-regulator.txt > > +++ > > b/Documentation/devicetree/bindings/regulator/rohm,bd71837-regulator.txt > > @@ -27,8 +27,38 @@ BUCK1, BUCK2, BUCK3, BUCK4, BUCK5, BUCK6 > > LDO1, LDO2, LDO3, LDO4, LDO5, LDO6 > > [...] > > + > > +rest | not supported | not supported | not supported > > + > > Example: > > Could you add an example of the optional properties ? Sure. I'll do that for next version as well :) Br, Matti Vaittinen -- Matti Vaittinen, Linux device drivers ROHM Semiconductors, Finland SWDC Kiviharjunlenkki 1E 90220 OULU FINLAND ~~~ "I don't think so," said Rene Descartes. Just then, he vanished ~~~
Re: [PATCH v4 00/15] Habana Labs kernel driver
On Thu, Feb 14, 2019 at 9:11 AM Greg KH wrote: > > On Mon, Feb 11, 2019 at 05:17:36PM +0200, Oded Gabbay wrote: > > Hello, > > This is v4 of the Habana Labs kernel driver patch-set. It contains fixes > > according to reviews done on v3, mainly for the command buffer, sysfs and > > MMU > > patches. In addition, patch 2/15 was reduced in size from 4.3MB to 1.4MB. > > > > The patch-set is rebased on v5.0-rc6. > > > > Link to v3 cover letter: https://lkml.org/lkml/2019/2/4/1033 > > > > Link to v2 cover letter: https://lkml.org/lkml/2019/1/30/1003 > > > > Link to v1 cover letter: https://lwn.net/Articles/777342/ > > > > I would appricate any feedback, question and/or review. > > There's been some 0-day bot feedback on some of these patches now that I > put them in my -testing branch. So I'm going to drop the patch series > from there now and wait for a v5 of the series that hopefully will have > those issues fixed :) > > thanks, > > greg k-h Sure, np. Thanks, Oded
Re: [PATCH V4 1/2] arm64: dts: freescale: imx8qxp: add cpu opp table
On 14-02-19, 01:54, Anson Huang wrote:
> Add i.MX8QXP CPU opp table to support cpufreq.
>
> Signed-off-by: Anson Huang
> ---
> No change since V3.
> ---
> arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 25 +
> 1 file changed, 25 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> index 4021f25..593e2db 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> @@ -34,6 +34,10 @@
> reg = <0x0 0x0>;
> enable-method = "psci";
> next-level-cache = <_L2>;
> + clocks = < IMX_A35_CLK>;
> + clock-latency = <61036>;
Who uses this value ? And why is it different from the one mentioned
in the OPP table ?
> + #cooling-cells = <2>;
clocks and cooling-cells must be defined for all the CPUs.
> + operating-points-v2 = <_0_opp_table>;
> };
>
> A35_1: cpu@1 {
> @@ -42,6 +46,7 @@
> reg = <0x0 0x1>;
> enable-method = "psci";
> next-level-cache = <_L2>;
> + operating-points-v2 = <_0_opp_table>;
> };
>
> A35_2: cpu@2 {
> @@ -50,6 +55,7 @@
> reg = <0x0 0x2>;
> enable-method = "psci";
> next-level-cache = <_L2>;
> + operating-points-v2 = <_0_opp_table>;
> };
>
> A35_3: cpu@3 {
> @@ -58,6 +64,7 @@
> reg = <0x0 0x3>;
> enable-method = "psci";
> next-level-cache = <_L2>;
> + operating-points-v2 = <_0_opp_table>;
> };
>
> A35_L2: l2-cache0 {
> @@ -65,6 +72,24 @@
> };
> };
>
> + a35_0_opp_table: opp-table {
> + compatible = "operating-points-v2";
> + opp-shared;
> +
> + opp-9 {
> + opp-hz = /bits/ 64 <9>;
> + opp-microvolt = <100>;
> + clock-latency-ns = <15>;
> + };
> +
> + opp-12 {
> + opp-hz = /bits/ 64 <12>;
> + opp-microvolt = <110>;
> + clock-latency-ns = <15>;
> + opp-suspend;
You want to go to a higher frequency on suspend ?
> + };
> + };
> +
> gic: interrupt-controller@51a0 {
> compatible = "arm,gic-v3";
> reg = <0x0 0x51a0 0 0x1>, /* GIC Dist */
> --
> 2.7.4
--
viresh
Re: [PATCH v4 00/15] Habana Labs kernel driver
On Mon, Feb 11, 2019 at 05:17:36PM +0200, Oded Gabbay wrote: > Hello, > This is v4 of the Habana Labs kernel driver patch-set. It contains fixes > according to reviews done on v3, mainly for the command buffer, sysfs and MMU > patches. In addition, patch 2/15 was reduced in size from 4.3MB to 1.4MB. > > The patch-set is rebased on v5.0-rc6. > > Link to v3 cover letter: https://lkml.org/lkml/2019/2/4/1033 > > Link to v2 cover letter: https://lkml.org/lkml/2019/1/30/1003 > > Link to v1 cover letter: https://lwn.net/Articles/777342/ > > I would appricate any feedback, question and/or review. There's been some 0-day bot feedback on some of these patches now that I put them in my -testing branch. So I'm going to drop the patch series from there now and wait for a v5 of the series that hopefully will have those issues fixed :) thanks, greg k-h
Re: [PATCH v2] staging: erofs: fix memleak of inode's shared xattr array
On 2019/2/14 14:46, Sheng Yong wrote:
> If it fails to read a shared xattr page, the inode's shared xattr array
> is not freed. The next time the inode's xattr is accessed, the previously
> allocated array is leaked.
>
> Signed-off-by: Sheng Yong
LGTM,
Fixes: b17500a0fdba ("staging: erofs: introduce xattr & acl support")
Cc: # 4.19+
Reviewed-by: Gao Xiang
[and there is also another race condition in it, but different root cause.
let me fix it later independently...]
Thanks,
Gao Xiang
Re: [PATCH 1/2] extcon-intel-cht-wc: Make charger detection co-existed with OTG host mode
On Thu, Feb 14, 2019 at 12:15:00AM +0100, Hans de Goede wrote: > Hi, > > On 10-02-19 21:36, Yauhen Kharuzhy wrote: > > Whiskey Cove Cherry Trail PMIC requires disabling OTG host mode before > > of charger detection procedure. Do this by manipulationg of CHGRCTRL1 > > register. > > > > Source: APCI DSDT code of Lenovo Yoga Book YB1-X91L and open-sourced > > Intel's drivers. > > Hmm, of the ACPI code is updating the otg-mode, then there should be > no reason for us to do this, can you provide an acpidump of your > device please? sure: https://github.com/jekhor/yogabook-linux/blob/master/yoga/acpi/yoga.acpidump.log Yes, there is ACPI routine for switching this but it is not called at IRQ handling because it is handled by extcon driver. See my notes here: https://github.com/jekhor/yogabook-linux/blob/master/yoga/acpi/investigate.txt#L364 -- Yauhen Kharuzhy
Re: [PATCH][RFC] ACPI: add "processor.broadcast_ppc" hook to broadcast _PPC to all online CPUs
On 14-02-19, 00:55, Yu Chen wrote:
> Hi Viresh,
> On Mon, Feb 11, 2019 at 04:03:07PM +0530, Viresh Kumar wrote:
> > On 09-02-19, 20:02, Chen Yu wrote:
> > > On Dell Inc. XPS13 9333, the BIOS changes the value of
> > > MSR_IA32_MISC_ENABLE_TURBO_DISABLE at runtime (e.g., when
> > > the power source changes), the maximum frequency of the
> > > CPU is not updated accordingly. This is due to the policy's
> > > cpuinfo.max is not updated when _PPC notifier fires.
> > >
> > > Fix this problem by updating the policy's cpuinfo.max
> > > and broadcast the _PPC notifier to all online CPUs.
> > >
> > > Link: https://bugzilla.kernel.org/show_bug.cgi?id=200759
> > > Reported-and-tested-by: Gabriele Mazzotta
> > > Originally-by: Srinivas Pandruvada
> > > Signed-off-by: Chen Yu
> > > ---
> > > drivers/acpi/processor_perflib.c | 16 ++--
> > > drivers/cpufreq/cpufreq.c| 2 ++
> > > drivers/cpufreq/intel_pstate.c | 15 ++-
> > > 3 files changed, 30 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/drivers/acpi/processor_perflib.c
> > > b/drivers/acpi/processor_perflib.c
> > > index a303fd0e108c..737dbf5aa7f7 100644
> > > --- a/drivers/acpi/processor_perflib.c
> > > +++ b/drivers/acpi/processor_perflib.c
> > > @@ -63,6 +63,10 @@ module_param(ignore_ppc, int, 0644);
> > > MODULE_PARM_DESC(ignore_ppc, "If the frequency of your machine gets
> > > wrongly" \
> > >"limited by BIOS, this should help");
> > >
> > > +static int broadcast_ppc;
> > > +module_param(broadcast_ppc, int, 0644);
> > > +MODULE_PARM_DESC(broadcast_ppc, "Broadcast the ppc to all online CPUs");
> > > +
> > > #define PPC_REGISTERED 1
> > > #define PPC_IN_USE 2
> > >
> > > @@ -180,8 +184,16 @@ void acpi_processor_ppc_has_changed(struct
> > > acpi_processor *pr, int event_flag)
> > > else
> > > acpi_processor_ppc_ost(pr->handle, 0);
> > > }
> > > - if (ret >= 0)
> > > - cpufreq_update_policy(pr->id);
> > > + if (ret >= 0) {
> > > + if (broadcast_ppc) {
> > > + int cpu;
> > > +
> > > + for_each_possible_cpu(cpu)
> > > + cpufreq_update_policy(cpu);
> > > + } else {
> > > + cpufreq_update_policy(pr->id);
> > > + }
> > > + }
> > > }
> > >
> > > int acpi_processor_get_bios_limit(int cpu, unsigned int *limit)
> > > diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c
> > > index e35a886e00bc..95e08816b512 100644
> > > --- a/drivers/cpufreq/cpufreq.c
> > > +++ b/drivers/cpufreq/cpufreq.c
> > > @@ -2237,6 +2237,8 @@ static int cpufreq_set_policy(struct cpufreq_policy
> > > *policy,
> > >
> > > policy->min = new_policy->min;
> > > policy->max = new_policy->max;
> > > + policy->cpuinfo.max_freq = new_policy->cpuinfo.max_freq;
> > > + policy->cpuinfo.min_freq = new_policy->cpuinfo.min_freq;
> > > trace_cpu_frequency_limits(policy);
> > >
> > > policy->cached_target_freq = UINT_MAX;
> > > diff --git a/drivers/cpufreq/intel_pstate.c
> > > b/drivers/cpufreq/intel_pstate.c
> > > index dd66decf2087..e1881313c396 100644
> > > --- a/drivers/cpufreq/intel_pstate.c
> > > +++ b/drivers/cpufreq/intel_pstate.c
> > > @@ -2081,11 +2081,24 @@ static void intel_pstate_adjust_policy_max(struct
> > > cpufreq_policy *policy,
> > >
> > > static int intel_pstate_verify_policy(struct cpufreq_policy *policy)
> > > {
> > > + int max_freq;
> > > struct cpudata *cpu = all_cpu_data[policy->cpu];
> > >
> > > update_turbo_state();
> > > + max_freq = intel_pstate_get_max_freq(cpu);
> > > +
> > > + if (acpi_ppc && policy->max == policy->cpuinfo.max_freq &&
> >
> > Why do have this check for policy->max here ?
> >
> Thanks for looking at this change, I've replied to another email in detail of
> the scenario that, this is due to corner case that if the system boots
> with battery and plug the AC after boot up, the cpufreq max limit will not
> increase even the turbo has been enabled after the AC plugged.
Yeah, but I asked a different question I believe, why is this
comparison necessary ?
policy->max == policy->cpuinfo.max_freq
--
viresh
Re: [PATCH] fs/coda: get rid of CODA_ALLOC()
On Thu, 14 Feb 2019, Dan Carpenter wrote:
> These days we have kvzalloc() so we can delete CODA_ALLOC().
Maybe it would be better to get rid fo CODA_FREE as well?
julia
>
> I made a couple related changes in coda_psdev_write(). First, I
> added some error handling to avoid a NULL dereference if the allocation
> failed. Second, I used kvmalloc() instead of kvzalloc() because we
> copy over the memory on the next line so there is no need to zero it
> first.
>
> Signed-off-by: Dan Carpenter
> ---
> fs/coda/coda_linux.h | 10 --
> fs/coda/psdev.c | 6 +-
> fs/coda/upcall.c | 4 ++--
> 3 files changed, 7 insertions(+), 13 deletions(-)
>
> diff --git a/fs/coda/coda_linux.h b/fs/coda/coda_linux.h
> index 126155cadfa9..1ea9521e79d7 100644
> --- a/fs/coda/coda_linux.h
> +++ b/fs/coda/coda_linux.h
> @@ -63,16 +63,6 @@ unsigned short coda_flags_to_cflags(unsigned short);
> void coda_sysctl_init(void);
> void coda_sysctl_clean(void);
>
> -#define CODA_ALLOC(ptr, cast, size) do { \
> -if (size < PAGE_SIZE) \
> -ptr = kzalloc((unsigned long) size, GFP_KERNEL); \
> -else \
> -ptr = (cast)vzalloc((unsigned long) size); \
> -if (!ptr) \
> - pr_warn("kernel malloc returns 0 at %s:%d\n", __FILE__, __LINE__); \
> -} while (0)
> -
> -
> #define CODA_FREE(ptr, size) kvfree((ptr))
>
> /* inode to cnode access functions */
> diff --git a/fs/coda/psdev.c b/fs/coda/psdev.c
> index c5234c21b539..49d44a485c9a 100644
> --- a/fs/coda/psdev.c
> +++ b/fs/coda/psdev.c
> @@ -124,7 +124,11 @@ static ssize_t coda_psdev_write(struct file *file, const
> char __user *buf,
> hdr.opcode, hdr.unique);
> nbytes = size;
> }
> - CODA_ALLOC(dcbuf, union outputArgs *, nbytes);
> + dcbuf = kvmalloc(nbytes, GFP_KERNEL);
> + if (!dcbuf) {
> + retval = -ENOMEM;
> + goto out;
> + }
> if (copy_from_user(dcbuf, buf, nbytes)) {
> CODA_FREE(dcbuf, nbytes);
> retval = -EFAULT;
> diff --git a/fs/coda/upcall.c b/fs/coda/upcall.c
> index 1175a1722411..203f029bcdc3 100644
> --- a/fs/coda/upcall.c
> +++ b/fs/coda/upcall.c
> @@ -46,7 +46,7 @@ static void *alloc_upcall(int opcode, int size)
> {
> union inputArgs *inp;
>
> - CODA_ALLOC(inp, union inputArgs *, size);
> + inp = kvzalloc(size, GFP_KERNEL);
> if (!inp)
> return ERR_PTR(-ENOMEM);
>
> @@ -743,7 +743,7 @@ static int coda_upcall(struct venus_comm *vcp,
> sig_req = kmalloc(sizeof(struct upc_req), GFP_KERNEL);
> if (!sig_req) goto exit;
>
> - CODA_ALLOC((sig_req->uc_data), char *, sizeof(struct coda_in_hdr));
> + sig_req->uc_data = kvzalloc(sizeof(struct coda_in_hdr), GFP_KERNEL);
> if (!sig_req->uc_data) {
> kfree(sig_req);
> goto exit;
> --
> 2.17.1
>
>
Re: [PATCH] PCI: pciehp: Do not turn off slot if presence comes up after link
On Wed, Feb 13, 2019 at 06:55:46PM +, alex_gagn...@dellteam.com wrote: > On 2/13/19 2:36 AM, Lukas Wunner wrote: > > > (*) A bit hypothetical: There is no hardware yet implementing the ECN. > > > > Hm, this contradicts Austin Bolen's e-mail of Jan 25 that "Yes, this > > platform disables in-band presence" (when asked whether your host > > controller already adheres to the ECN). > > Both statements are true. The hardware does indeed disable in-band > presence, in a rudimentary way that is not compliant with the ECN -- it > doesn't implement the bits required by the ECN. Ugh, can a BIOS update make those machines compliant to the ECN or do we need a quirk specifically for them? > > Polling PDS in > > pcie_wait_for_link() or disabling either PDC or DLLSC if in-band presence > > is disabled seems simpler to reason about. > > pcie_wait_for_link() is generic PCIe layer. I don't think mixing hotplug > concepts is a good layering violation. The function used to live in pciehp_hpc.c, but commits 9f5a70f18c58 and f0157160b359 moved it to generic code to allow code sharing with the DPC driver. That's the only reason it's in generic code AFAICS. > >> in-band PD disable (what's a good acronym for that, BTW?) > > > > I don't know, maybe inband_presence_disabled? > > PCI_EXP_SLTCAP2_IBPD ? Yes, something like that. It should match the spec, which I have no access to. Thanks, Lukas
[PATCH] fs/coda: get rid of CODA_ALLOC()
These days we have kvzalloc() so we can delete CODA_ALLOC().
I made a couple related changes in coda_psdev_write(). First, I
added some error handling to avoid a NULL dereference if the allocation
failed. Second, I used kvmalloc() instead of kvzalloc() because we
copy over the memory on the next line so there is no need to zero it
first.
Signed-off-by: Dan Carpenter
---
fs/coda/coda_linux.h | 10 --
fs/coda/psdev.c | 6 +-
fs/coda/upcall.c | 4 ++--
3 files changed, 7 insertions(+), 13 deletions(-)
diff --git a/fs/coda/coda_linux.h b/fs/coda/coda_linux.h
index 126155cadfa9..1ea9521e79d7 100644
--- a/fs/coda/coda_linux.h
+++ b/fs/coda/coda_linux.h
@@ -63,16 +63,6 @@ unsigned short coda_flags_to_cflags(unsigned short);
void coda_sysctl_init(void);
void coda_sysctl_clean(void);
-#define CODA_ALLOC(ptr, cast, size) do { \
-if (size < PAGE_SIZE) \
-ptr = kzalloc((unsigned long) size, GFP_KERNEL); \
-else \
-ptr = (cast)vzalloc((unsigned long) size); \
-if (!ptr) \
- pr_warn("kernel malloc returns 0 at %s:%d\n", __FILE__, __LINE__); \
-} while (0)
-
-
#define CODA_FREE(ptr, size) kvfree((ptr))
/* inode to cnode access functions */
diff --git a/fs/coda/psdev.c b/fs/coda/psdev.c
index c5234c21b539..49d44a485c9a 100644
--- a/fs/coda/psdev.c
+++ b/fs/coda/psdev.c
@@ -124,7 +124,11 @@ static ssize_t coda_psdev_write(struct file *file, const
char __user *buf,
hdr.opcode, hdr.unique);
nbytes = size;
}
- CODA_ALLOC(dcbuf, union outputArgs *, nbytes);
+ dcbuf = kvmalloc(nbytes, GFP_KERNEL);
+ if (!dcbuf) {
+ retval = -ENOMEM;
+ goto out;
+ }
if (copy_from_user(dcbuf, buf, nbytes)) {
CODA_FREE(dcbuf, nbytes);
retval = -EFAULT;
diff --git a/fs/coda/upcall.c b/fs/coda/upcall.c
index 1175a1722411..203f029bcdc3 100644
--- a/fs/coda/upcall.c
+++ b/fs/coda/upcall.c
@@ -46,7 +46,7 @@ static void *alloc_upcall(int opcode, int size)
{
union inputArgs *inp;
- CODA_ALLOC(inp, union inputArgs *, size);
+ inp = kvzalloc(size, GFP_KERNEL);
if (!inp)
return ERR_PTR(-ENOMEM);
@@ -743,7 +743,7 @@ static int coda_upcall(struct venus_comm *vcp,
sig_req = kmalloc(sizeof(struct upc_req), GFP_KERNEL);
if (!sig_req) goto exit;
- CODA_ALLOC((sig_req->uc_data), char *, sizeof(struct coda_in_hdr));
+ sig_req->uc_data = kvzalloc(sizeof(struct coda_in_hdr), GFP_KERNEL);
if (!sig_req->uc_data) {
kfree(sig_req);
goto exit;
--
2.17.1
Re: [PATCH v2 2/2] iwlwifi: Use struct_size() in kzalloc
On Tue, 2019-01-29 at 11:21 +0800, YueHaibing wrote: > Use struct_size() in kzalloc instead of the 'regd_to_copy' > > Signed-off-by: YueHaibing > --- Applied to our internal tree and it will reach the mainline following our normal upstreaming process. Thanks! -- Luca.
Re: [PATCH v2 1/2] iwlwifi: Use kmemdup instead of duplicating its function
On Tue, 2019-01-29 at 11:21 +0800, YueHaibing wrote:
> Use kmemdup rather than duplicating its implementation
>
> Signed-off-by: YueHaibing
> ---
> drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c | 8 ++--
> 1 file changed, 2 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c
> b/drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c
> index d9afedc..569cc50 100644
> --- a/drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c
> +++ b/drivers/net/wireless/intel/iwlwifi/iwl-nvm-parse.c
> @@ -1196,13 +1196,9 @@ iwl_parse_nvm_mcc_info(struct device *dev,
> const struct iwl_cfg *cfg,
> regd_to_copy = sizeof(struct ieee80211_regdomain) +
> valid_rules * sizeof(struct ieee80211_reg_rule);
>
> - copy_rd = kzalloc(regd_to_copy, GFP_KERNEL);
> - if (!copy_rd) {
> + copy_rd = kmemdup(regd, regd_to_copy, GFP_KERNEL);
> + if (!copy_rd)
> copy_rd = ERR_PTR(-ENOMEM);
> - goto out;
> - }
> -
> - memcpy(copy_rd, regd, regd_to_copy);
>
> out:
> kfree(regdb_ptrs);
This was already applied. Dropping.
--
Luca.
Re: [PATCH v2 1/2] leds: Add Intel Cherry Trail Whiskey Cove PMIC LEDs
On Wed, Feb 13, 2019 at 11:43:29PM +0100, Hans de Goede wrote: > Hi, > > On 12-02-19 21:59, Yauhen Kharuzhy wrote: > > Add support for LEDs connected to the Intel Cherry Trail Whiskey Cove > > PMIC. Charger and general-purpose leds are supported. Hardware blinking > > is implemented, breathing is not. > > > > This driver was tested with Lenovo Yoga Book notebook. > > Thank you for working on this. The CHT Whiskey Cove PMIC is > also used on the GPD win and GPD pocket devices and there LED1 > by default indicates the charging status. > > Since your driver forces the LED into SWCTL mode on probe() > this means that any kernel with it enabled will break the > charging LEDs OOTB function, this is undesirable. > > I believe it would be best to add a custom "mode" attribute > to the led classdev, with "manual" and "on-when-charging" > modes, this would then control bits 0-1 of reg 0x5e1f and > by default these bits should be left as is when the driver > loads. > > Note that in my experience the "charging" mode only works > when bits 0-1 have the value 10. I've some written notes from > when I played with this myself and they say: > >-CHT WC powerled control 0x5e1f: bits 0-1: > 0: > 1: Off > 2: On when charging > 3: On >-CHT WC powerled pattern control 0x5e20: bits 1-2: > 0: Off > 1: On > 2: Blinking > 3: Glowing Maybe you are right, I will check but at Linux Yoga Book this LED doesn't work as HW-controlled charging status indicator, so I didn't discovery this. I used this source as reference; https://github.com/jekhor/yogabook-linux-android-kernel/blob/cm-13.0/drivers/misc/charger_gp_led.c > Also note that the 0x5e20 notes do not match with your > defines, I believe this is a small bug in your code, see > comments in line below. > > As for the 0x5e20 settings, I believe another custom > sysfs attribute, called "breathing" would be a good idea to > export the breathing functionality. > > The way I see this working is that writing "1" to this will > turn on glowing mode, and writing 0 to it, or 0 to brightness > will turn it off. Reading it will return 1/0 depending on > whether the LED is in glowing mode or not. Jacek? Pavel? I thought about pattern_set() implementation for 'breathing' mode in future but this doesn't seem simple, maybe custom attribute will has sense? > > For an example of adding custom sysfs attributes to a > led-class device see kbd_led_groups and kbd_led_attrs in: > drivers/platform/x86/dell-laptop.c > > > + > > +#define CHT_WC_LED1_CTRL 0x5e1f > > +#define CHT_WC_LED1_FSM0x5e20 > > +#define CHT_WC_LED1_PWM0x5e21 > > + > > +#define CHT_WC_LED2_CTRL 0x4fdf > > +#define CHT_WC_LED2_FSM0x4fe0 > > +#define CHT_WC_LED2_PWM0x4fe1 > > + > > +/* HW or SW control of charging led */ > > +#define CHT_WC_LED1_SWCTL BIT(0) > > +#define CHT_WC_LED1_ON BIT(1) > > + > > +#define CHT_WC_LED2_ON BIT(0) > > +#define CHT_WC_LED_I_MA2_5 (2 << 2) > > +/* LED current limit */ > > +#define CHT_WC_LED_I_MASK GENMASK(3, 2) > > + > > +#define CHT_WC_LED_F_1_4_HZ(0 << 4) > > +#define CHT_WC_LED_F_1_2_HZ(1 << 4) > > +#define CHT_WC_LED_F_1_HZ (2 << 4) > > +#define CHT_WC_LED_F_2_HZ (3 << 4) > > +#define CHT_WC_LED_F_MASK 0x30 > > + > > +#define CHT_WC_LED_EFF_ON BIT(1) > > +#define CHT_WC_LED_EFF_BLINKINGBIT(2) > > +#define CHT_WC_LED_EFF_BREATHING BIT(3) > > +#define CHT_WC_LED_EFF_MASK0x06 > > So your MASK is correct here, but the values used should > be based on that, so you get: > > #define CHT_WC_LED_EFF_ON (1 << 1) > #define CHT_WC_LED_EFF_BLINKING (2 << 1) > #define CHT_WC_LED_EFF_BREATHING (3 << 1) > > Note that this effectively only changes the value of > CHT_WC_LED_EFF_BREATHING, so that it now to fits in your > mask. > > Regards, Hm, it seems lost in refactoring time, thanks. My original defines were: #define CHT_WC_LED_EFF_ON (1<<1) #define CHT_WC_LED_EFF_BLINKING (2<<1) #define CHT_WC_LED_EFF_BREATHING(3<<1) #define CHT_WC_LED_EFF_MASK 0x06 I will revert this in next version. -- Yauhen Kharuzhy
linux-next: Tree for Feb 14
Hi all, Changes since 20190213: The netfilter-next tree lost its build failure. The devicetree tree gained a conflict against Linus' tree. The kvm-arm tree gained a conflict against the kvm-fixes tree. Non-merge commits (relative to Linus' tree): 7716 8028 files changed, 324264 insertions(+), 193806 deletions(-) I have created today's linux-next tree at git://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git (patches at http://www.kernel.org/pub/linux/kernel/next/ ). If you are tracking the linux-next tree using git, you should not use "git pull" to do so as that will try to merge the new linux-next release with the old one. You should use "git fetch" and checkout or reset to the new master. You can see which trees have been included by looking in the Next/Trees file in the source. There are also quilt-import.log and merge.log files in the Next directory. Between each merge, the tree was built with a ppc64_defconfig for powerpc, an allmodconfig for x86_64, a multi_v7_defconfig for arm and a native build of tools/perf. After the final fixups (if any), I do an x86_64 modules_install followed by builds for x86_64 allnoconfig, powerpc allnoconfig (32 and 64 bit), ppc44x_defconfig, allyesconfig and pseries_le_defconfig and i386, sparc and sparc64 defconfig. And finally, a simple boot test of the powerpc pseries_le_defconfig kernel in qemu (with and without kvm enabled). Below is a summary of the state of the merge. I am currently merging 296 trees (counting Linus' and 69 trees of bug fix patches pending for the current merge release). Stats about the size of the tree over time can be seen at http://neuling.org/linux-next-size.html . Status of my local build tests will be at http://kisskb.ellerman.id.au/linux-next . If maintainers want to give advice about cross compilers/configs that work, we are always open to add more builds. Thanks to Randy Dunlap for doing many randconfig builds. And to Paul Gortmaker for triage and bug fixes. -- Cheers, Stephen Rothwell $ git checkout master $ git reset --hard stable Merging origin/master (1f947a7a011f Merge branch 'akpm' (patches from Andrew)) Merging fixes/master (0dd62c042779 x86/syscalls: Mark expected switch fall-throughs) Merging kbuild-current/fixes (207a369e3c08 sh: fix build error for invisible CONFIG_BUILTIN_DTB_SOURCE) Merging arc-current/for-curr (7e9246a982a6 ARCv2: support manual regfile save on interrupts) Merging arm-current/fixes (fc67e6f120a3 ARM: 8835/1: dma-mapping: Clear DMA ops on teardown) Merging arm64-fixes/for-next/fixes (ea5736805190 arm64: kexec_file: handle empty command-line) Merging m68k-current/for-linus (bed1369f5190 m68k: Fix memblock-related crashes) Merging powerpc-fixes/fixes (5a3840a470c4 powerpc/papr_scm: Use the correct bind address) Merging sparc/master (b71acb0e3721 Merge branch 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6) Merging fscrypt-current/for-stable (ae64f9bd1d36 Linux 4.15-rc2) Merging net/master (2fdeee254923 team: avoid complex list operations in team_nl_cmd_options_set()) Merging bpf/master (1e405c1a3f66 xsk: do not remove umem from netdevice on fall-back to copy-mode) Merging ipsec/master (fc2d5cfdcfe2 af_key: unconditionally clone on broadcast) Merging netfilter/master (753c111f655e netfilter: nft_compat: use-after-free when deleting targets) Merging ipvs/master (b2e3d68d1251 netfilter: nft_compat: destroy function must not have side effects) Merging wireless-drivers/master (d04ca383860b mt76x0u: fix suspend/resume) Merging mac80211/master (6157ca0d6bfe mac80211: Fix Tx aggregation session tear down with ITXQs) Merging rdma-fixes/for-rc (48396e80fb65 RDMA/srp: Rework SCSI device reset handling) Merging sound-current/for-linus (00a399cad1a0 ALSA: pcm: Revert capture stream behavior change in blocking mode) Merging sound-asoc-fixes/for-linus (d3dd6ab1b6fd Merge branch 'asoc-5.0' into asoc-linus) Merging regmap-fixes/for-linus (f17b5f06cb92 Linux 5.0-rc4) Merging regulator-fixes/for-linus (fc2454980161 Merge branch 'regulator-5.0' into regulator-linus) Merging spi-fixes/for-linus (e7f77d1a86f2 Merge branch 'spi-5.0' into spi-linus) Merging pci-current/for-linus (f57a98e1b713 PCI: Work around Synopsys duplicate Device ID (HAPS USB3, NXP i.MX)) Merging driver-core.current/driver-core-linus (d13937116f1e Linux 5.0-rc6) Merging tty.current/tty-linus (d13937116f1e Linux 5.0-rc6) Merging usb.current/usb-linus (d13937116f1e Linux 5.0-rc6) Merging usb-gadget-fixes/fixes (a53469a68eb8 usb: phy: am335x: fix race condition in _probe) Merging usb-serial-fixes/usb-linus (dd9d3d86b08d USB: serial: cp210x: add ID for Ingenico 3070) Merging usb-chipidea-fixes/ci-for-usb-stable (d6d768a0ec3c usb: chipidea: fix static checker warning for NULL pointer) Merging phy/fixes (827cb0323928 phy: ath79-usb: Fix the main reset name to match the DT binding) Merging sta
[PATCH v2] staging: erofs: fix memleak of inode's shared xattr array
If it fails to read a shared xattr page, the inode's shared xattr array
is not freed. The next time the inode's xattr is accessed, the previously
allocated array is leaked.
Signed-off-by: Sheng Yong
---
v2: * s/node/inode in commit message
* add prefix `staging:' to the subject
---
drivers/staging/erofs/xattr.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/staging/erofs/xattr.c b/drivers/staging/erofs/xattr.c
index 80dca6a4adbe..e3f8b904a680 100644
--- a/drivers/staging/erofs/xattr.c
+++ b/drivers/staging/erofs/xattr.c
@@ -92,8 +92,11 @@ static int init_inode_xattrs(struct inode *inode)
it.page = erofs_get_meta_page(sb,
++it.blkaddr, S_ISDIR(inode->i_mode));
- if (IS_ERR(it.page))
+ if (IS_ERR(it.page)) {
+ kfree(vi->xattr_shared_xattrs);
+ vi->xattr_shared_xattrs = NULL;
return PTR_ERR(it.page);
+ }
it.kaddr = kmap_atomic(it.page);
atomic_map = true;
--
2.17.1
[PATCH 0/8] stmmac: add some fixes for stm32
For common stmmac: - Add support to set CSR Clock range selection in DT For stm32mpu: - Glue codes to support magic packet - Glue codes to support all PHY config : PHY_MODE (MII,GMII, RMII, RGMII) and in normal, PHY wo crystal (25Mhz), PHY wo crystal (50Mhz), No 125Mhz from PHY config For stm32mcu: - Add Ethernet support for stm32h7 - Add syscfg clk support for stm32f4 Christophe Roullier (8): net: ethernet: stmmac: manage Ethernet WoL for stm32mp157c. net: ethernet: stmmac: update to support all PHY config for stm32mp157c. dt-bindings: net: stmmac: add phys config properties net: ethernet: stmmac: add management of clk_csr property net: ethernet: stmmac: update to be compatible with MCU family (stm32f4, stm32h7) dt-bindings: net: stmmac: add syscfg clock property ARM: dts: stm32: Add Ethernet support on stm32h7 SOC and activate it for eval and disco boards ARM: dts: stm32: add syscfg clock support for Ethernet on STM32F429 SoC .../devicetree/bindings/net/stm32-dwmac.txt| 10 +- arch/arm/boot/dts/stm32f429.dtsi | 6 +- arch/arm/boot/dts/stm32h743-pinctrl.dtsi | 15 ++ arch/arm/boot/dts/stm32h743.dtsi | 19 +++ arch/arm/boot/dts/stm32h743i-disco.dts | 17 ++ arch/arm/boot/dts/stm32h743i-eval.dts | 17 ++ drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c | 179 + .../net/ethernet/stmicro/stmmac/stmmac_platform.c | 3 + 8 files changed, 230 insertions(+), 36 deletions(-) -- 2.7.4
[PATCH 4/8] net: ethernet: stmmac: add management of clk_csr property
In Documentation stmmac.txt there is possibility to fixed CSR Clock range selection with property clk_csr. This patch add the management of this property For example to use it, add in your ethernet node DT: clk_csr = <3>; Signed-off-by: Christophe Roullier --- drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c index 2b800ce..3031f2b 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c @@ -408,6 +408,9 @@ stmmac_probe_config_dt(struct platform_device *pdev, const char **mac) /* Default to phy auto-detection */ plat->phy_addr = -1; + /* Get clk_csr from device tree */ + of_property_read_u32(np, "clk_csr", >clk_csr); + /* "snps,phy-addr" is not a standard property. Mark it as deprecated * and warn of its use. Remove this when phy node support is added. */ -- 2.7.4
[PATCH 6/8] dt-bindings: net: stmmac: add syscfg clock property
Need syscfg clock for MCU family in case bootloader does not activate it. Signed-off-by: Christophe Roullier --- Documentation/devicetree/bindings/net/stm32-dwmac.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.txt b/Documentation/devicetree/bindings/net/stm32-dwmac.txt index f42dc68..524f8a0 100644 --- a/Documentation/devicetree/bindings/net/stm32-dwmac.txt +++ b/Documentation/devicetree/bindings/net/stm32-dwmac.txt @@ -14,8 +14,8 @@ Required properties: - clock-names: Should be "stmmaceth" for the host clock. Should be "mac-clk-tx" for the MAC TX clock. Should be "mac-clk-rx" for the MAC RX clock. - For MPU family need to add also "ethstp" for power mode clock and, - "syscfg-clk" for SYSCFG clock. + Should be "syscfg-clk" for the SYSCFG clock. + For MPU family need to add also "ethstp" for power mode clock - interrupt-names: Should contain a list of interrupt names corresponding to the interrupts in the interrupts property, if available. Should be "macirq" for the main MAC IRQ -- 2.7.4
[PATCH 5/8] net: ethernet: stmmac: update to be compatible with MCU family (stm32f4, stm32h7)
Update glue codes to be compatible with MCU family.
Signed-off-by: Christophe Roullier
---
drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c | 51 ++-
1 file changed, 41 insertions(+), 10 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
index cee59e8..20a2daa 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
@@ -6,7 +6,6 @@
* License terms: GNU General Public License (GPL), version 2
*
*/
-
#include
#include
#include
@@ -119,12 +118,6 @@ static int stm32_dwmac_init(struct plat_stmmacenet_data
*plat_dat)
struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
int ret;
- if (dwmac->ops->set_mode) {
- ret = dwmac->ops->set_mode(plat_dat);
- if (ret)
- return ret;
- }
-
ret = clk_prepare_enable(dwmac->clk_tx);
if (ret)
return ret;
@@ -139,13 +132,26 @@ static int stm32_dwmac_init(struct plat_stmmacenet_data
*plat_dat)
if (dwmac->ops->clk_prepare) {
ret = dwmac->ops->clk_prepare(dwmac, true);
+ if (ret)
+ goto err_clk_disable;
+ }
+
+ if (dwmac->ops->set_mode) {
+ ret = dwmac->ops->set_mode(plat_dat);
if (ret) {
- clk_disable_unprepare(dwmac->clk_rx);
- clk_disable_unprepare(dwmac->clk_tx);
+ if (dwmac->ops->clk_prepare)
+ dwmac->ops->clk_prepare(dwmac, false);
+ goto err_clk_disable;
}
}
return ret;
+
+err_clk_disable:
+ clk_disable_unprepare(dwmac->clk_rx);
+ clk_disable_unprepare(dwmac->clk_tx);
+
+ return ret;
}
static int stm32mp1_clk_prepare(struct stm32_dwmac *dwmac, bool prepare)
@@ -240,7 +246,19 @@ static int stm32mcu_set_mode(struct plat_stmmacenet_data
*plat_dat)
}
return regmap_update_bits(dwmac->regmap, reg,
-dwmac->ops->syscfg_eth_mask, val);
+dwmac->ops->syscfg_eth_mask, val << 23);
+}
+
+static int stm32mcu_clk_prepare(struct stm32_dwmac *dwmac, bool prepare)
+{
+ int ret = 0;
+
+ if (prepare)
+ ret = clk_prepare_enable(dwmac->syscfg_clk);
+ else
+ clk_disable_unprepare(dwmac->syscfg_clk);
+
+ return ret;
}
static void stm32_dwmac_clk_disable(struct stm32_dwmac *dwmac)
@@ -347,6 +365,17 @@ static int stm32mp1_parse_data(struct stm32_dwmac *dwmac,
return err;
}
+static int stm32mcu_parse_data(struct stm32_dwmac *dwmac,
+ struct device *dev)
+{
+ /* Clock for sysconfig */
+ dwmac->syscfg_clk = devm_clk_get(dev, "syscfg-clk");
+ if (IS_ERR(dwmac->syscfg_clk))
+ dev_warn(dev, "No syscfg clock provided...\n");
+
+ return 0;
+}
+
static int stm32_dwmac_probe(struct platform_device *pdev)
{
struct plat_stmmacenet_data *plat_dat;
@@ -493,7 +522,9 @@ static SIMPLE_DEV_PM_OPS(stm32_dwmac_pm_ops,
static struct stm32_ops stm32mcu_dwmac_data = {
.set_mode = stm32mcu_set_mode,
+ .clk_prepare = stm32mcu_clk_prepare,
.suspend = stm32mcu_suspend,
+ .parse_data = stm32mcu_parse_data,
.syscfg_eth_mask = SYSCFG_MCU_ETH_MASK
};
--
2.7.4
[PATCH 2/8] net: ethernet: stmmac: update to support all PHY config for stm32mp157c.
Update glue codes to support all PHY config on stm32mp157c
PHY_MODE (MII,GMII, RMII, RGMII) and in normal, PHY wo crystal (25Mhz),
PHY wo crystal (50Mhz), No 125Mhz from PHY config.
Signed-off-by: Christophe Roullier
---
drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c | 102 +-
1 file changed, 82 insertions(+), 20 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
index d1cf145..cee59e8 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
@@ -25,9 +25,24 @@
#define SYSCFG_MCU_ETH_MASKBIT(23)
#define SYSCFG_MP1_ETH_MASKGENMASK(23, 16)
+#define SYSCFG_PMCCLRR_OFFSET 0x40
#define SYSCFG_PMCR_ETH_CLK_SELBIT(16)
#define SYSCFG_PMCR_ETH_REF_CLK_SELBIT(17)
+
+/* Ethernet PHY interface selection in register SYSCFG Configuration
+ *--
+ * src |BIT(23)| BIT(22)| BIT(21)|BIT(20)|
+ *--
+ * MII | 0 | 0| 0| 1 |
+ *--
+ * GMII | 0 | 0| 0| 0 |
+ *--
+ * RGMII | 0 | 0| 1| n/a |
+ *--
+ * RMII | 1 | 0| 0| n/a |
+ *--
+ */
#define SYSCFG_PMCR_ETH_SEL_MIIBIT(20)
#define SYSCFG_PMCR_ETH_SEL_RGMII BIT(21)
#define SYSCFG_PMCR_ETH_SEL_RMII BIT(23)
@@ -35,15 +50,54 @@
#define SYSCFG_MCU_ETH_SEL_MII 0
#define SYSCFG_MCU_ETH_SEL_RMII1
+/* STM32MP1 register definitions
+ *
+ * Below table summarizes the clock requirement and clock sources for
+ * supported phy interface modes.
+ * __
+ *|PHY_MODE | Normal | PHY wo crystal| PHY wo crystal |No 125Mhz from PHY|
+ *| || 25MHz|50MHz | |
+ * ---
+ *| MII| - | eth-ck|n/a | n/a|
+ *| || || |
+ * ---
+ *| GMII | - | eth-ck|n/a | n/a|
+ *| || || |
+ * ---
+ *| RGMII | - | eth-ck|n/a | eth-ck (no pin) |
+ *| || || st,eth_clk_sel |
+ * ---
+ *| RMII| - | eth-ck| eth-ck| n/a|
+ *| || | st,eth_ref_clk_sel | |
+ * ---
+ *
+ * BIT(17) : set this bit in RMII mode when you have PHY without crystal 50MHz
+ * BIT(16) : set this bit in GMII/RGMII PHY when you do not want use 125Mhz
+ * from PHY
+ *-
+ * src | BIT(17) | BIT(16) |
+ *-
+ * MII | n/a| n/a|
+ *-
+ * GMII | n/a | st,eth_clk_sel |
+ *-
+ * RGMII | n/a | st,eth_clk_sel |
+ *-
+ * RMII | st,eth_ref_clk_sel | n/a|
+ *-
+ *
+ */
+
struct stm32_dwmac {
struct clk *clk_tx;
struct clk *clk_rx;
struct clk *clk_eth_ck;
struct clk *clk_ethstp;
struct clk *syscfg_clk;
- bool int_phyclk;/* Clock from RCC to drive PHY */
+ int eth_clk_sel_reg;
+ int eth_ref_clk_sel_reg;
int irq_pwr_wakeup;
- u32 mode_reg; /* MAC glue-logic mode register */
+ u32 mode_reg;/* MAC glue-logic mode register */
struct regmap *regmap;
u32 speed;
const struct stm32_ops *ops;
@@ -103,7 +157,7 @@ static int stm32mp1_clk_prepare(struct stm32_dwmac *dwmac,
bool prepare)
if (ret)
return ret;
- if (dwmac->int_phyclk) {
+ if (dwmac->clk_eth_ck) {
ret = clk_prepare_enable(dwmac->clk_eth_ck);
if (ret) {
clk_disable_unprepare(dwmac->syscfg_clk);
@@ -112,7 +166,7 @@ static int
[PATCH 1/8] net: ethernet: stmmac: manage Ethernet WoL for stm32mp157c.
Add glue codes to support magic packet on stm32mp157c
Signed-off-by: Christophe Roullier
---
drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c | 30 ++-
1 file changed, 29 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
index 7e2e79d..d1cf145 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
@@ -42,6 +42,7 @@ struct stm32_dwmac {
struct clk *clk_ethstp;
struct clk *syscfg_clk;
bool int_phyclk;/* Clock from RCC to drive PHY */
+ int irq_pwr_wakeup;
u32 mode_reg; /* MAC glue-logic mode register */
struct regmap *regmap;
u32 speed;
@@ -232,7 +233,9 @@ static int stm32_dwmac_parse_data(struct stm32_dwmac *dwmac,
static int stm32mp1_parse_data(struct stm32_dwmac *dwmac,
struct device *dev)
{
+ struct platform_device *pdev = to_platform_device(dev);
struct device_node *np = dev->of_node;
+ int err = 0;
dwmac->int_phyclk = of_property_read_bool(np, "st,int-phyclk");
@@ -260,7 +263,26 @@ static int stm32mp1_parse_data(struct stm32_dwmac *dwmac,
return PTR_ERR(dwmac->syscfg_clk);
}
- return 0;
+ /* Get IRQ information early to have an ability to ask for deferred
+* probe if needed before we went too far with resource allocation.
+*/
+ dwmac->irq_pwr_wakeup = platform_get_irq_byname(pdev,
+ "stm32_pwr_wakeup");
+ if (!dwmac->int_phyclk && dwmac->irq_pwr_wakeup >= 0) {
+ err = device_init_wakeup(>dev, true);
+ if (err) {
+ dev_err(>dev, "Failed to init wake up irq\n");
+ return err;
+ }
+ err = dev_pm_set_dedicated_wake_irq(>dev,
+ dwmac->irq_pwr_wakeup);
+ if (err) {
+ dev_err(>dev, "Failed to set wake up irq\n");
+ device_init_wakeup(>dev, false);
+ }
+ device_set_wakeup_enable(>dev, false);
+ }
+ return err;
}
static int stm32_dwmac_probe(struct platform_device *pdev)
@@ -326,9 +348,15 @@ static int stm32_dwmac_remove(struct platform_device *pdev)
struct net_device *ndev = platform_get_drvdata(pdev);
struct stmmac_priv *priv = netdev_priv(ndev);
int ret = stmmac_dvr_remove(>dev);
+ struct stm32_dwmac *dwmac = priv->plat->bsp_priv;
stm32_dwmac_clk_disable(priv->plat->bsp_priv);
+ if (dwmac->irq_pwr_wakeup >= 0) {
+ dev_pm_clear_wake_irq(>dev);
+ device_init_wakeup(>dev, false);
+ }
+
return ret;
}
--
2.7.4
[PATCH 3/8] dt-bindings: net: stmmac: add phys config properties
Add properties to support all Phy config PHY_MODE (MII,GMII, RMII, RGMII) and in normal, PHY wo crystal (25Mhz), PHY wo crystal (50Mhz), No 125Mhz from PHY config. Signed-off-by: Christophe Roullier --- Documentation/devicetree/bindings/net/stm32-dwmac.txt | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.txt b/Documentation/devicetree/bindings/net/stm32-dwmac.txt index 1341012..f42dc68 100644 --- a/Documentation/devicetree/bindings/net/stm32-dwmac.txt +++ b/Documentation/devicetree/bindings/net/stm32-dwmac.txt @@ -24,9 +24,9 @@ Required properties: encompases the glue register, and the offset of the control register. Optional properties: -- clock-names: For MPU family "mac-clk-ck" for PHY without quartz -- st,int-phyclk (boolean) : valid only where PHY do not have quartz and need to be clock - by RCC +- clock-names: For MPU family "eth-ck" for PHY without quartz +- st,eth_clk_sel (boolean) : set this property in RGMII PHY when you do not want use 125Mhz +- st,eth_ref_clk_sel (boolean) : set this property in RMII mode when you have PHY without crystal 50MHz Example: -- 2.7.4
[PATCH 8/8] ARM: dts: stm32: add syscfg clock support for Ethernet on STM32F429 SoC
This patch add syscfg clock support for Ethernet of the STM32F429 SoC. Needed if bootloader do not manage it. Signed-off-by: Christophe Roullier --- arch/arm/boot/dts/stm32f429.dtsi | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index 8d6f028..6f78346 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -657,10 +657,12 @@ reg-names = "stmmaceth"; interrupts = <61>; interrupt-names = "macirq"; - clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx"; + clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx", + "syscfg-clk"; clocks = < 0 STM32F4_AHB1_CLOCK(ETHMAC)>, < 0 STM32F4_AHB1_CLOCK(ETHMACTX)>, - < 0 STM32F4_AHB1_CLOCK(ETHMACRX)>; + < 0 STM32F4_AHB1_CLOCK(ETHMACRX)>, + < 0 STM32F4_APB2_CLOCK(SYSCFG)>; st,syscon = < 0x4>; snps,pbl = <8>; snps,mixed-burst; -- 2.7.4
[PATCH 7/8] ARM: dts: stm32: Add Ethernet support on stm32h7 SOC and activate it for eval and disco boards
Synopsys GMAC 4.10 is used. And Phy mode for eval and disco is RMII
with PHY SMSC LAN8742
Signed-off-by: Christophe Roullier
---
arch/arm/boot/dts/stm32h743-pinctrl.dtsi | 15 +++
arch/arm/boot/dts/stm32h743.dtsi | 19 +++
arch/arm/boot/dts/stm32h743i-disco.dts | 17 +
arch/arm/boot/dts/stm32h743i-eval.dts| 17 +
4 files changed, 68 insertions(+)
diff --git a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
index 24be8e6..980b276 100644
--- a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
@@ -173,6 +173,21 @@
};
};
+ ethernet_rmii: rmii@0 {
+ pins {
+ pinmux = ,
+,
+,
+,
+,
+,
+,
+,
+;
+ slew-rate = <2>;
+ };
+ };
+
usart1_pins: usart1@0 {
pins1 {
pinmux = ;
/* USART1_TX */
diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi
index cbdd69c..f6384af 100644
--- a/arch/arm/boot/dts/stm32h743.dtsi
+++ b/arch/arm/boot/dts/stm32h743.dtsi
@@ -511,6 +511,25 @@
status = "disabled";
};
};
+
+ syscfg: system-config@58000400 {
+ compatible = "syscon";
+ reg = <0x58000400 0x400>;
+ };
+
+ mac: ethernet@40028000 {
+ compatible = "st,stm32-dwmac", "snps,dwmac-4.10a";
+ reg = <0x40028000 0x8000>;
+ reg-names = "stmmaceth";
+ interrupts = <61>;
+ interrupt-names = "macirq";
+ clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx",
+ "syscfg-clk";
+ clocks = < ETH1MAC_CK>, < ETH1TX_CK>, <
ETH1RX_CK>, < SYSCFG_CK>;
+ st,syscon = < 0x4>;
+ snps,pbl = <8>;
+ status = "disabled";
+ };
};
};
diff --git a/arch/arm/boot/dts/stm32h743i-disco.dts
b/arch/arm/boot/dts/stm32h743i-disco.dts
index 45e088c..0f738d0 100644
--- a/arch/arm/boot/dts/stm32h743i-disco.dts
+++ b/arch/arm/boot/dts/stm32h743i-disco.dts
@@ -66,6 +66,23 @@
clock-frequency = <2500>;
};
+ {
+ status = "okay";
+ pinctrl-0 = <_rmii>;
+ pinctrl-names = "default";
+ phy-mode= "rmii";
+ phy-handle = <>;
+
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ phy1: ethernet-phy@1 {
+ reg = <0>;
+ };
+ };
+};
+
{
pinctrl-0 = <_pins>;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/stm32h743i-eval.dts
b/arch/arm/boot/dts/stm32h743i-eval.dts
index 3f8e0c4..44997ba 100644
--- a/arch/arm/boot/dts/stm32h743i-eval.dts
+++ b/arch/arm/boot/dts/stm32h743i-eval.dts
@@ -104,6 +104,23 @@
status = "okay";
};
+ {
+ status = "okay";
+ pinctrl-0 = <_rmii>;
+ pinctrl-names = "default";
+ phy-mode= "rmii";
+ phy-handle = <>;
+
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ phy1: ethernet-phy@1 {
+ reg = <0>;
+ };
+ };
+};
+
{
pinctrl-0 = <_pins>;
pinctrl-names = "default";
--
2.7.4
[PATCH] powerpc/book3s: Remove a few page table update interfaces.
When updating page tables, we need to make sure we fill the page table
entry valid bit. We should be using page table populate interface for
updating the table entries. The page table 'set' interface allows
updating the raw value of page table entry. This can result in
updating the entry wrongly. Remove the 'set' interface so that we avoid
its future usage.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/pgalloc.h | 8
arch/powerpc/include/asm/book3s/64/pgtable.h | 14 --
2 files changed, 4 insertions(+), 18 deletions(-)
diff --git a/arch/powerpc/include/asm/book3s/64/pgalloc.h
b/arch/powerpc/include/asm/book3s/64/pgalloc.h
index 9c1173283b96..138bc2ecc0c4 100644
--- a/arch/powerpc/include/asm/book3s/64/pgalloc.h
+++ b/arch/powerpc/include/asm/book3s/64/pgalloc.h
@@ -111,7 +111,7 @@ static inline void pgd_free(struct mm_struct *mm, pgd_t
*pgd)
static inline void pgd_populate(struct mm_struct *mm, pgd_t *pgd, pud_t *pud)
{
- pgd_set(pgd, __pgtable_ptr_val(pud) | PGD_VAL_BITS);
+ *pgd = __pgd(__pgtable_ptr_val(pud) | PGD_VAL_BITS);
}
static inline pud_t *pud_alloc_one(struct mm_struct *mm, unsigned long addr)
@@ -138,7 +138,7 @@ static inline void pud_free(struct mm_struct *mm, pud_t
*pud)
static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd)
{
- pud_set(pud, __pgtable_ptr_val(pmd) | PUD_VAL_BITS);
+ *pud = __pud(__pgtable_ptr_val(pmd) | PUD_VAL_BITS);
}
static inline void __pud_free_tlb(struct mmu_gather *tlb, pud_t *pud,
@@ -176,13 +176,13 @@ static inline void __pmd_free_tlb(struct mmu_gather *tlb,
pmd_t *pmd,
static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd,
pte_t *pte)
{
- pmd_set(pmd, __pgtable_ptr_val(pte) | PMD_VAL_BITS);
+ *pmd = __pmd(__pgtable_ptr_val(pte) | PMD_VAL_BITS);
}
static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd,
pgtable_t pte_page)
{
- pmd_set(pmd, __pgtable_ptr_val(pte_page) | PMD_VAL_BITS);
+ *pmd = __pmd(__pgtable_ptr_val(pte_page) | PMD_VAL_BITS);
}
static inline pgtable_t pmd_pgtable(pmd_t pmd)
diff --git a/arch/powerpc/include/asm/book3s/64/pgtable.h
b/arch/powerpc/include/asm/book3s/64/pgtable.h
index dc71e2b92003..a24e00fb7fa7 100644
--- a/arch/powerpc/include/asm/book3s/64/pgtable.h
+++ b/arch/powerpc/include/asm/book3s/64/pgtable.h
@@ -853,11 +853,6 @@ static inline bool pte_ci(pte_t pte)
return false;
}
-static inline void pmd_set(pmd_t *pmdp, unsigned long val)
-{
- *pmdp = __pmd(val);
-}
-
static inline void pmd_clear(pmd_t *pmdp)
{
*pmdp = __pmd(0);
@@ -889,11 +884,6 @@ static inline int pmd_bad(pmd_t pmd)
return hash__pmd_bad(pmd);
}
-static inline void pud_set(pud_t *pudp, unsigned long val)
-{
- *pudp = __pud(val);
-}
-
static inline void pud_clear(pud_t *pudp)
{
*pudp = __pud(0);
@@ -936,10 +926,6 @@ static inline bool pud_access_permitted(pud_t pud, bool
write)
}
#define pgd_write(pgd) pte_write(pgd_pte(pgd))
-static inline void pgd_set(pgd_t *pgdp, unsigned long val)
-{
- *pgdp = __pgd(val);
-}
static inline void pgd_clear(pgd_t *pgdp)
{
--
2.20.1
[PATCH] sched/core: Remove BUG_ON()
pick_next_task is never return NULL because idle task will return when cpu is idle. Signed-off-by: Huang Zijiang --- kernel/sched/core.c | 1 - 1 file changed, 1 deletion(-) diff --git a/kernel/sched/core.c b/kernel/sched/core.c index dbe9a3f..1de1a85 100644 --- a/kernel/sched/core.c +++ b/kernel/sched/core.c @@ -5624,7 +5624,6 @@ static void migrate_tasks(struct rq *dead_rq, struct rq_flags *rf) * * pick_next_task() assumes pinned rq->lock: * */ next = pick_next_task(rq, _task, rf); - BUG_ON(!next); put_prev_task(rq, next); /* -- 1.8.3.1
[PATCH] net: hns: Fix object reference leaks in hns_dsaf_roce_reset()
The of_find_device_by_node() takes a reference to the underlying device
structure, we should release that reference.
Signed-off-by: Huang Zijiang
---
drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c
b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c
index 14d7ec7..697d929 100644
--- a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c
+++ b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c
@@ -3081,6 +3081,7 @@ int hns_dsaf_roce_reset(struct fwnode_handle
*dsaf_fwnode, bool dereset)
dsaf_dev = dev_get_drvdata(>dev);
if (!dsaf_dev) {
dev_err(>dev, "dsaf_dev is NULL\n");
+ put_device(>dev);
return -ENODEV;
}
@@ -3088,6 +3089,7 @@ int hns_dsaf_roce_reset(struct fwnode_handle
*dsaf_fwnode, bool dereset)
if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
dev_err(dsaf_dev->dev, "%s v1 chip doesn't support RoCE!\n",
dsaf_dev->ae_dev.name);
+ put_device(>dev);
return -ENODEV;
}
--
1.8.3.1
[PATCH 2/2] net: Replace dev_kfree_skb_any by dev_consume_skb_any
The skb should be freed by dev_consume_skb_any() efx_tx_tso_fallback()
when skb is still used. The skb is be replaced by segments, so the
original skb should be consumed(not drop).
Signed-off-by: Huang Zijiang
---
drivers/net/ethernet/sfc/tx.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/sfc/tx.c b/drivers/net/ethernet/sfc/tx.c
index c3ad564..ed551f0 100644
--- a/drivers/net/ethernet/sfc/tx.c
+++ b/drivers/net/ethernet/sfc/tx.c
@@ -471,7 +471,7 @@ static int efx_tx_tso_fallback(struct efx_tx_queue
*tx_queue,
if (IS_ERR(segments))
return PTR_ERR(segments);
- dev_kfree_skb_any(skb);
+ dev_consume_skb_any(skb);
skb = segments;
while (skb) {
--
1.8.3.1
[PATCH 1/2] net:ethernet:cadence: Replace dev_kfree_skb_any by dev_consume_skb_any
The skb should be freed by dev_consume_skb_any() in macb_pad_and_fcs() when *skb is still used. The *skb is be replaced by nskb, so the original *skb should be consumed(not drop). Signed-off-by: Huang Zijiang --- drivers/net/ethernet/cadence/macb_main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c index 1d86b4d..5a63ac5 100644 --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c @@ -1698,7 +1698,7 @@ static int macb_pad_and_fcs(struct sk_buff **skb, struct net_device *ndev) if (!nskb) return -ENOMEM; - dev_kfree_skb_any(*skb); + dev_consume_skb_any(*skb); *skb = nskb; } -- 1.8.3.1
[PATCH] net:dl2k: Replace dev_kfree_skb_irq by dev_consume_skb_irq
dev_consume_skb_irq() should be called when skb xmit done.It makes drop profiles more friendly. Signed-off-by: Huang Zijiang --- drivers/net/ethernet/dlink/dl2k.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/dlink/dl2k.c b/drivers/net/ethernet/dlink/dl2k.c index f0536b1..21810bf 100644 --- a/drivers/net/ethernet/dlink/dl2k.c +++ b/drivers/net/ethernet/dlink/dl2k.c @@ -843,7 +843,7 @@ rio_free_tx (struct net_device *dev, int irq) desc_to_dma(>tx_ring[entry]), skb->len, PCI_DMA_TODEVICE); if (irq) - dev_kfree_skb_irq(skb); + dev_consume_skb_irq(skb); else dev_kfree_skb(skb); -- 1.8.3.1
[PATCH] net:dl2k: Modify the code style escaping the warning
modify the code style in order to removing the following warning
when excute the script checkpatch.pl
WARNING: space prohibited between function name and open parenthesis '('
Signed-off-by: Huang Zijiang
---
drivers/net/ethernet/dlink/dl2k.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/dlink/dl2k.c
b/drivers/net/ethernet/dlink/dl2k.c
index f0536b1..228654a 100644
--- a/drivers/net/ethernet/dlink/dl2k.c
+++ b/drivers/net/ethernet/dlink/dl2k.c
@@ -843,9 +843,9 @@ rio_free_tx (struct net_device *dev, int irq)
desc_to_dma(>tx_ring[entry]),
skb->len, PCI_DMA_TODEVICE);
if (irq)
- dev_kfree_skb_irq (skb);
+ dev_kfree_skb_irq(skb);
else
- dev_kfree_skb (skb);
+ dev_kfree_skb(skb);
np->tx_skbuff[entry] = NULL;
entry = (entry + 1) % TX_RING_SIZE;
--
1.8.3.1
[PATCH] isdn:hisax: Replace dev_kfree_skb_any by dev_consume_skb_any
The skb should be freed by dev_consume_skb_any() in hfcpci_fill_fifo() when bcs->tx_skb is still used. The bcs->tx_skb is be replaced by skb_dequeue(>squeue), so the original bcs->tx_skb should be consumed(not drop). Signed-off-by: Huang Zijiang --- drivers/isdn/hisax/hfc_pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/isdn/hisax/hfc_pci.c b/drivers/isdn/hisax/hfc_pci.c index ea0e4c6..7f9e8cc 100644 --- a/drivers/isdn/hisax/hfc_pci.c +++ b/drivers/isdn/hisax/hfc_pci.c @@ -657,7 +657,7 @@ hfcpci_fill_fifo(struct BCState *bcs) schedule_event(bcs, B_ACKPENDING); } - dev_kfree_skb_any(bcs->tx_skb); + dev_consume_skb_any(bcs->tx_skb); bcs->tx_skb = skb_dequeue(>squeue);/* fetch next data */ } test_and_clear_bit(BC_FLG_BUSY, >Flag); -- 1.8.3.1
[PATCH] EDAC, altera: Add missing of_node_put()
The call to of_parse_phandle returns a node pointer with refcount
incremented thus it must be explicitly decremented here after the last
usage.
Signed-off-by: Huang Zijiang
---
drivers/edac/altera_edac.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
index c89d82a..1bcd778 100644
--- a/drivers/edac/altera_edac.c
+++ b/drivers/edac/altera_edac.c
@@ -1046,14 +1046,17 @@ altr_init_a10_ecc_block(struct device_node *np, u32
irq_mask,
return -ENODEV;
}
- if (of_address_to_resource(sysmgr_np, 0, ))
+ if (of_address_to_resource(sysmgr_np, 0, )) {
+ of_node_put(sysmgr_np);
return -ENOMEM;
+ }
/* Need physical address for SMCC call */
base = res.start;
ecc_mgr_map = regmap_init(NULL, NULL, (void *)base,
_sdram_regmap_cfg);
+ of_node_put(sysmgr_np);
}
of_node_put(np_eccmgr);
if (IS_ERR(ecc_mgr_map)) {
--
1.8.3.1
答复: [PATCH v2 3/3] scsi: ufs: Add HI3670 SoC UFS driver support
Fine to me. Thanks!
Acked-by: Wei Li
-邮件原件-
发件人: Manivannan Sadhasivam [mailto:manivannan.sadhasi...@linaro.org]
发送时间: 2019年1月5日 15:29
收件人: vinholika...@gmail.com; j...@linux.vnet.ibm.com;
martin.peter...@oracle.com; liwei (CM); robh...@kernel.org
抄送: linux-s...@vger.kernel.org; linux-kernel@vger.kernel.org;
linux-arm-ker...@lists.infradead.org; devicet...@vger.kernel.org;
john.stu...@linaro.org; amit.kuche...@linaro.org; guodong...@linaro.org;
Manivannan Sadhasivam
主题: [PATCH v2 3/3] scsi: ufs: Add HI3670 SoC UFS driver support
Add HI3670 SoC UFS driver support by extending the common ufs-hisi
driver. One major difference between HI3660 ad HI3670 SoCs interms of
UFS is the PHY. HI3670 has a 10nm variant PHY and hence this parameter is
used to distinguish the configuration.
Signed-off-by: Manivannan Sadhasivam
---
drivers/scsi/ufs/ufs-hisi.c | 127 +---
drivers/scsi/ufs/ufs-hisi.h | 4 ++
2 files changed, 109 insertions(+), 22 deletions(-)
diff --git a/drivers/scsi/ufs/ufs-hisi.c b/drivers/scsi/ufs/ufs-hisi.c
index 452e19f8fb47..f2d3df357a97 100644
--- a/drivers/scsi/ufs/ufs-hisi.c
+++ b/drivers/scsi/ufs/ufs-hisi.c
@@ -66,7 +66,7 @@ static int ufs_hisi_check_hibern8(struct ufs_hba *hba)
return err;
}
-static void ufs_hi3660_clk_init(struct ufs_hba *hba)
+static void ufs_hisi_clk_init(struct ufs_hba *hba)
{
struct ufs_hisi_host *host = ufshcd_get_variant(hba);
@@ -80,7 +80,7 @@ static void ufs_hi3660_clk_init(struct ufs_hba *hba)
ufs_sys_ctrl_set_bits(host, BIT_SYSCTRL_REF_CLOCK_EN, PHY_CLK_CTRL);
}
-static void ufs_hi3660_soc_init(struct ufs_hba *hba)
+static void ufs_hisi_soc_init(struct ufs_hba *hba)
{
struct ufs_hisi_host *host = ufshcd_get_variant(hba);
u32 reg;
@@ -139,6 +139,7 @@ static void ufs_hi3660_soc_init(struct ufs_hba *hba)
static int ufs_hisi_link_startup_pre_change(struct ufs_hba *hba)
{
+ struct ufs_hisi_host *host = ufshcd_get_variant(hba);
int err;
uint32_t value;
uint32_t reg;
@@ -153,6 +154,14 @@ static int ufs_hisi_link_startup_pre_change(struct ufs_hba
*hba)
ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8121, 0x0), 0x2D);
/* MPHY CBOVRCTRL3 */
ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8122, 0x0), 0x1);
+
+ if (host->caps & UFS_HISI_CAP_PHY10nm) {
+ /* MPHY CBOVRCTRL4 */
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8127, 0x0), 0x98);
+ /* MPHY CBOVRCTRL5 */
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8128, 0x0), 0x1);
+ }
+
/* Unipro VS_MphyCfgUpdt */
ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD085, 0x0), 0x1);
/* MPHY RXOVRCTRL4 rx0 */
@@ -173,10 +182,21 @@ static int ufs_hisi_link_startup_pre_change(struct
ufs_hba *hba)
ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8113, 0x0), 0x1);
ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xD085, 0x0), 0x1);
- /* Tactive RX */
- ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008F, 0x4), 0x7);
- /* Tactive RX */
- ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008F, 0x5), 0x7);
+ if (host->caps & UFS_HISI_CAP_PHY10nm) {
+ /* RX_Hibern8Time_Capability*/
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0092, 0x4), 0xA);
+ /* RX_Hibern8Time_Capability*/
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0092, 0x5), 0xA);
+ /* RX_Min_ActivateTime */
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008f, 0x4), 0xA);
+ /* RX_Min_ActivateTime*/
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008f, 0x5), 0xA);
+ } else {
+ /* Tactive RX */
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008F, 0x4), 0x7);
+ /* Tactive RX */
+ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008F, 0x5), 0x7);
+ }
/* Gear3 Synclength */
ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0095, 0x4), 0x4F);
@@ -208,7 +228,8 @@ static int ufs_hisi_link_startup_pre_change(struct ufs_hba
*hba)
if (err)
dev_err(hba->dev, "ufs_hisi_check_hibern8 error\n");
- ufshcd_writel(hba, UFS_HCLKDIV_NORMAL_VALUE, UFS_REG_HCLKDIV);
+ if (!(host->caps & UFS_HISI_CAP_PHY10nm))
+ ufshcd_writel(hba, UFS_HCLKDIV_NORMAL_VALUE, UFS_REG_HCLKDIV);
/* disable auto H8 */
reg = ufshcd_readl(hba, REG_AUTO_HIBERNATE_IDLE_TIMER);
@@ -253,7 +274,7 @@ static int ufs_hisi_link_startup_post_change(struct ufs_hba
*hba)
return 0;
}
-static int ufs_hi3660_link_startup_notify(struct ufs_hba *hba,
+static int ufs_hisi_link_startup_notify(struct ufs_hba *hba,
enum ufs_notify_change_status status)
{
int err = 0;
@@ -391,6 +412,28 @@ static void ufs_hisi_set_dev_cap(struct
ufs_hisi_dev_params *hisi_param)
static void ufs_hisi_pwr_change_pre_change(struct ufs_hba *hba)
{
+ struct ufs_hisi_host *host =
答复: [PATCH v2 2/3] arm64: dts: hisilicon: hi3670: Add UFS controller support
Fine to me. Thanks!
Acked-by: Wei Li
-邮件原件-
发件人: Manivannan Sadhasivam [mailto:manivannan.sadhasi...@linaro.org]
发送时间: 2019年1月5日 15:29
收件人: vinholika...@gmail.com; j...@linux.vnet.ibm.com;
martin.peter...@oracle.com; liwei (CM); robh...@kernel.org
抄送: linux-s...@vger.kernel.org; linux-kernel@vger.kernel.org;
linux-arm-ker...@lists.infradead.org; devicet...@vger.kernel.org;
john.stu...@linaro.org; amit.kuche...@linaro.org; guodong...@linaro.org;
Manivannan Sadhasivam
主题: [PATCH v2 2/3] arm64: dts: hisilicon: hi3670: Add UFS controller support
Add UFS controller support for HiSilicon HI3670 SoC.
Signed-off-by: Manivannan Sadhasivam
---
arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
index 6ccdf5040ffd..285219dd657f 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
@@ -654,6 +654,24 @@
clock-names = "apb_pclk";
};
+ /* UFS */
+ ufs: ufs@ff3c {
+ compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1";
+ /* 0: HCI standard */
+ /* 1: UFS SYS CTRL */
+ reg = <0x0 0xff3c 0x0 0x1000>,
+ <0x0 0xff3e 0x0 0x1000>;
+ interrupt-parent = <>;
+ interrupts = ;
+ clocks = <_ctrl HI3670_CLK_GATE_UFSIO_REF>,
+ <_ctrl HI3670_CLK_GATE_UFS_SUBSYS>;
+ clock-names = "ref_clk", "phy_clk";
+ freq-table-hz = <0 0>, <0 0>;
+ /* offset: 0x84; bit: 12 */
+ resets = <_rst 0x84 12>;
+ reset-names = "rst";
+ };
+
/* SD */
dwmmc1: dwmmc1@ff37f000 {
compatible = "hisilicon,hi3670-dw-mshc";
--
2.17.1
[PATCH v4] coccinelle: semantic patch for missing put_device()
The of_find_device_by_node() takes a reference to the underlying device
structure, we should release that reference.
The implementation of this semantic patch is:
In a function, for variables returned by calling of_find_device_by_node(),
a, if it is released by a function such as
put_device()/of_dev_put()/platform_device_put() after the last use,
it is considered that there is no reference leak;
b, if it is passed back to the caller via
dev_get_drvdata()/platform_get_drvdata()/get_device(), etc., the
reference will be released in other functions, and the current function
also considers that there is no reference leak;
c, for the rest of the situation, the current function should release the
reference by calling put_device, this patch will report the
corresponding error message.
By using this semantic patch, we have found some object reference leaks,
such as:
commit 11907e9d3533 ("ASoC: fsl-asoc-card: fix object reference leaks in
fsl_asoc_card_probe")
commit a12085d13997 ("mtd: rawnand: atmel: fix possible object reference leak")
commit 11493f26856a ("mtd: rawnand: jz4780: fix possible object reference leak")
There are still dozens of reference leaks in the current kernel code.
Further, for the case of b, the object returned to other functions may also
have a reference leak, we will continue to develop other cocci scripts to
further check the reference leak.
Signed-off-by: Wen Yang
Reviewed-by: Julia Lawall
Reviewed-by: Markus Elfring
Cc: Julia Lawall
Cc: Gilles Muller
Cc: Nicolas Palix
Cc: Michal Marek
Cc: Markus Elfring
Cc: Masahiro Yamada
Cc: Wen Yang
Cc: cheng.shen...@zte.com.cn
Cc: co...@systeme.lip6.fr
Cc: linux-kernel@vger.kernel.org
---
v4->v3:
- add Masahiro Yamada
- omit a blank line
- split the long message parameter
- reduce the number of metavariables
- Describe the implementation of the semantic patch,
explain the scenarios it can detect,
and further software development considerations.
v3->v2:
- reduction of a bit of redundant C code within SmPL search specifications.
- consider the message construction without using the extra Python variable
“msg”
v2->v1:
- put exists after search, and then drop the when exists below.
- should not use the same e as in the when's below.
- Make a new type metavariable and use it to put a cast on the result of
platform_get_drvdata.
scripts/coccinelle/free/put_device.cocci | 55
1 file changed, 55 insertions(+)
create mode 100644 scripts/coccinelle/free/put_device.cocci
diff --git a/scripts/coccinelle/free/put_device.cocci
b/scripts/coccinelle/free/put_device.cocci
new file mode 100644
index 000..6fd79cf
--- /dev/null
+++ b/scripts/coccinelle/free/put_device.cocci
@@ -0,0 +1,55 @@
+/// Find missing put_device for every of_find_device_by_node.
+///
+// Confidence: Moderate
+// Copyright: (C) 2018-2019 Wen Yang, ZTE. GPLv2.
+// Comments:
+// Options: --no-includes --include-headers
+
+virtual report
+virtual org
+
+@search exists@
+local idexpression id;
+expression x,e,e1;
+position p1,p2;
+type T,T1,T2,T3;
+@@
+
+id = of_find_device_by_node@p1(x)
+... when != e = id
+if (id == NULL || ...) { ... return ...; }
+... when != put_device(>dev)
+when != platform_device_put(id)
+when != of_dev_put(id)
+when != if (id) { ... put_device(>dev) ... }
+when != e1 = (T)id
+when != e1 = >dev
+when != e1 = get_device(>dev)
+when != e1 = (T1)platform_get_drvdata(id)
+(
+ return
+(id
+|(T2)dev_get_drvdata(>dev)
+|(T3)platform_get_drvdata(id)
+);
+| return@p2 ...;
+)
+
+@script:python depends on report@
+p1 << search.p1;
+p2 << search.p2;
+@@
+
+coccilib.report.print_report(p2[0],
+"ERROR: missing put_device;"
+ + " call of_find_device_by_node on line "
+ + p1[0].line
+ + " and return without releasing.")
+
+@script:python depends on org@
+p1 << search.p1;
+p2 << search.p2;
+@@
+
+cocci.print_main("of_find_device_by_node", p1)
+cocci.print_secs("needed put_device", p2)
--
2.9.5
答复: [PATCH v2 1/3] dt-bindings: ufs: Add HI3670 UFS controller binding
Fine to me. Thanks! Acked-by: Wei Li -邮件原件- 发件人: Manivannan Sadhasivam [mailto:manivannan.sadhasi...@linaro.org] 发送时间: 2019年1月5日 15:29 收件人: vinholika...@gmail.com; j...@linux.vnet.ibm.com; martin.peter...@oracle.com; liwei (CM); robh...@kernel.org 抄送: linux-s...@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org; devicet...@vger.kernel.org; john.stu...@linaro.org; amit.kuche...@linaro.org; guodong...@linaro.org; Manivannan Sadhasivam 主题: [PATCH v2 1/3] dt-bindings: ufs: Add HI3670 UFS controller binding Add devicetree binding for HI3670 UFS controller. HI3760 SoC is very similar to HI3660 SoC with almost same IPs. Only major difference in terms of UFS is the PHY. HI3670 has 10nm PHY. But since the original driver (HI3660 UFS) cannot make HI3670 UFS functional, a separate compatible is added for HI3670 without any fallback. Signed-off-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/ufs/ufs-hisi.txt | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/ufs/ufs-hisi.txt b/Documentation/devicetree/bindings/ufs/ufs-hisi.txt index a48c44817367..0b83df1a5418 100644 --- a/Documentation/devicetree/bindings/ufs/ufs-hisi.txt +++ b/Documentation/devicetree/bindings/ufs/ufs-hisi.txt @@ -6,9 +6,10 @@ Each UFS Host Controller should have its own node. Required properties: - compatible: compatible list, contains one of the following - "hisilicon,hi3660-ufs", "jedec,ufs-1.1" for hisi ufs - host controller present on Hi36xx chipset. + host controller present on Hi3660 chipset. + "hisilicon,hi3670-ufs", "jedec,ufs-2.1" for hisi ufs + host controller present on Hi3670 chipset. - reg : should contain UFS register address space & UFS SYS CTRL register address, -- interrupt-parent : interrupt device - interrupts: interrupt number - clocks : List of phandle and clock specifier pairs - clock-names : List of clock input name strings sorted in the same -- 2.17.1
[PATCH] powerpc/64s: Fix possible corruption on big endian due to pgd/pud_present()
In v4.20 we changed our pgd/pud_present() to check for _PAGE_PRESENT
rather than just checking that the value is non-zero, e.g.:
static inline int pgd_present(pgd_t pgd)
{
- return !pgd_none(pgd);
+ return (pgd_raw(pgd) & cpu_to_be64(_PAGE_PRESENT));
}
Unfortunately this is broken on big endian, as the result of the
bitwise && is truncated to int, which is always zero because
_PAGE_PRESENT is 0x8000ul. This means pgd_present() and
pud_present() are always false at compile time, and the compiler
elides the subsequent code.
Remarkably with that bug present we are still able to boot and run
with few noticeable effects. However under some work loads we are able
to trigger a warning in the ext4 code:
WARNING: CPU: 11 PID: 29593 at fs/ext4/inode.c:3927
.ext4_set_page_dirty+0x70/0xb0
CPU: 11 PID: 29593 Comm: debugedit Not tainted 4.20.0-rc1 #1
...
NIP .ext4_set_page_dirty+0x70/0xb0
LR .set_page_dirty+0xa0/0x150
Call Trace:
.set_page_dirty+0xa0/0x150
.unmap_page_range+0xbf0/0xe10
.unmap_vmas+0x84/0x130
.unmap_region+0xe8/0x190
.__do_munmap+0x2f0/0x510
.__vm_munmap+0x80/0x110
.__se_sys_munmap+0x14/0x30
system_call+0x5c/0x70
The fix is simple, we need to convert the result of the bitwise && to
an int before returning it.
Thanks to Jan Kara and Aneesh for help with debugging.
Fixes: da7ad366b497 ("powerpc/mm/book3s: Update pmd_present to look at
_PAGE_PRESENT bit")
Cc: sta...@vger.kernel.org # v4.20+
Reported-by: Erhard F.
Reviewed-by: Aneesh Kumar K.V
Signed-off-by: Michael Ellerman
---
arch/powerpc/include/asm/book3s/64/pgtable.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/book3s/64/pgtable.h
b/arch/powerpc/include/asm/book3s/64/pgtable.h
index c9bfe526ca9d..d8c8d7c9df15 100644
--- a/arch/powerpc/include/asm/book3s/64/pgtable.h
+++ b/arch/powerpc/include/asm/book3s/64/pgtable.h
@@ -904,7 +904,7 @@ static inline int pud_none(pud_t pud)
static inline int pud_present(pud_t pud)
{
- return (pud_raw(pud) & cpu_to_be64(_PAGE_PRESENT));
+ return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PRESENT));
}
extern struct page *pud_page(pud_t pud);
@@ -951,7 +951,7 @@ static inline int pgd_none(pgd_t pgd)
static inline int pgd_present(pgd_t pgd)
{
- return (pgd_raw(pgd) & cpu_to_be64(_PAGE_PRESENT));
+ return !!(pgd_raw(pgd) & cpu_to_be64(_PAGE_PRESENT));
}
static inline pte_t pgd_pte(pgd_t pgd)
--
2.20.1
RE: [PATCH v3 1/6] dt-bindings: add binding for USBSS-DRD controller.
Hi Rob,
>On Thu, Jan 31, 2019 at 11:52:28AM +, Pawel Laszczak wrote:
>> This patch aim at documenting USB related dt-bindings for the
>> Cadence USBSS-DRD controller.
>>
>> Signed-off-by: Pawel Laszczak
>> ---
>> .../devicetree/bindings/usb/cdns-usb3.txt | 33 +++
>> 1 file changed, 33 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/usb/cdns-usb3.txt
>>
>> diff --git a/Documentation/devicetree/bindings/usb/cdns-usb3.txt
>> b/Documentation/devicetree/bindings/usb/cdns-usb3.txt
>> new file mode 100644
>> index ..6dc38be77f5c
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/usb/cdns-usb3.txt
>> @@ -0,0 +1,33 @@
>> +Binding for the Cadence USBSS-DRD controller
>> +
>> +Required properties:
>> + - reg: Physical base address and size of the controller's register areas.
>> + Controller has 3 different regions:
>> + region 1 - HOST registers area
>> + region 2 - DEVICE registers area
>> + region 3 - OTG/DRD registers area
>> + - reg-names - register memory area names:
>> +"xhci" - for HOST registers space
>> +"dev" - for DEVICE registers space
>> +"otg" - for OTG/DRD registers space
>> + - compatible: Should contain: "cdns,usb3-1.0.0" or "cdns,usb3-1.0.1"
>> + - interrupts: Interrupt specifier. Refer to interrupt bindings.
>> +Driver supports only single interrupt line.
>
>Driver supports or h/w only has 1 interrupt?
h/w internally has 3 separate interrupt line, but in my testing board
they are ored. So physically driver sees only one h/w interrupt line and
assumes that h/w has single common interrupt line.
>
>> +This single interrupt is shared between Device,
>> +host and OTG/DRD part of driver.
>> +
>> +Optional properties:
>> + - maximum-speed : valid arguments are "super-speed", "high-speed" and
>> + "full-speed"; refer to usb/generic.txt
>> + - dr_mode: Should be one of "host", "peripheral" or "otg".
>> + - phys: reference to the USB PHY
>> +
>> +Example:
>> +usb@f300 {
>> +compatible = "cdns,usb3";
>
>Doesn't match above.
Right, should be:
Compatible = " cdns,usb3-1.0.0", "cdns,usb3-1.0.1";
>
>> +interrupts = ;
>> +reg = <0xf300 0x1 /* memory area for HOST
>> registers */
>> +0xf301 0x1 /* memory area for DEVICE
>> registers */
>> +0xf302 0x1>;/* memory area for OTG/DRD
>> registers */
>
>Are these really 64KB long? That wastes virtual address space on 32-bit
>systems if not.
Yes, on my testing platform it takes 64KB. It's only example, and it could be
limited.
>
>> +reg-names = "xhci", "dev", "otg";
>> +};
>> --
>> 2.17.1
>>
Thanks
Pawel
Re: [PATCH 2/2] Drivers: hv: vmbus: Display nothing in sysfs if monitor_allocated not set
On Mon, Feb 11, 2019 at 10:02:47AM -0800, Stephen Hemminger wrote:
> On Mon, 11 Feb 2019 02:01:18 -0500
> Kimberly Brown wrote:
>
> > On Fri, Feb 08, 2019 at 02:32:09PM -0800, Stephen Hemminger wrote:
> > > On Fri, 8 Feb 2019 05:01:12 -0500
> > > Kimberly Brown wrote:
> > >
> > > You are right, the current behavior is broken.
> > > It would be good to add a description of under what conditions
> > > monitor is not used. Is this some part of a project emulating
> > > Hyper-V?
> > >
> >
> > I'm not sure which conditions determine whether the monitor mechanism is
> > used. I've searched the Hypervisor TLFS, and I couldn't find any
> > information. If you have any suggestions for where I can find this
> > information, please let me know.
>
> The monitor page stuff pre-dates my involvement with Hyper-V. KY might know.
> But based on comments it looks like it was added to avoid hypercalls
> for each message. It probably showed up in Windows Server 2012 timeframe.
>
> To test you might want to dig up Windows Server 2008.
>
It looks like the monitor mechanism has always been used. It's present in the
earliest commit that I can find: 3e7ee4902fe6 ("add the Hyper-V virtual bus")
from 2009.
I propose that the following sentences be added to the sysfs documentation for
the affected attributes:
"The monitor page mechanism is used for performance critical channels (storage,
network, etc.). Channels that do not use the monitor page mechanism will return
EINVAL."
I think that this provides sufficient information for a user to understand why
opening an affected file can return EINVAL. What do you think?
[PATCH V2 1/2] lib/string: add memrchr function
Here is the detailed description for memrchr:
void *memrchr(const void *s, int c, size_t n);
The memrchr() function is like the memchr() function, except
that it searches backward from the end of the n bytes pointed
to by s instead of forward from the beginning.
The memrchr() functions return a pointer to the matching byte
or NULL if the character does not occur in the given memory
area.
Signed-off-by: Xiang Xiao
---
include/linux/string.h | 3 +++
lib/string.c | 23 +++
2 files changed, 26 insertions(+)
diff --git a/include/linux/string.h b/include/linux/string.h
index 7927b87..915c617 100644
--- a/include/linux/string.h
+++ b/include/linux/string.h
@@ -167,6 +167,9 @@ static inline void memcpy_flushcache(void *dst, const void
*src, size_t cnt)
memcpy(dst, src, cnt);
}
#endif
+#ifndef __HAVE_ARCH_MEMRCHR
+void *memrchr(const void *s, int c, size_t n);
+#endif
void *memchr_inv(const void *s, int c, size_t n);
char *strreplace(char *s, char old, char new);
diff --git a/lib/string.c b/lib/string.c
index 38e4ca0..595e0b3 100644
--- a/lib/string.c
+++ b/lib/string.c
@@ -964,6 +964,29 @@ void *memchr(const void *s, int c, size_t n)
EXPORT_SYMBOL(memchr);
#endif
+#ifndef __HAVE_ARCH_MEMRCHR
+/**
+ * memrchr - Find the last character in an area of memory.
+ * @s: The memory area
+ * @c: The byte to search for
+ * @n: The size of the area.
+ *
+ * Return: the address of the last occurrence of @c, or %NULL
+ * if @c is not found
+ */
+void *memrchr(const void *s, int c, size_t n)
+{
+ const unsigned char *p = s + n;
+
+ while (n-- != 0) {
+ if ((unsigned char)c == *--p)
+ return (void *)p;
+ }
+ return NULL;
+}
+EXPORT_SYMBOL(memrchr);
+#endif
+
static void *check_bytes8(const u8 *start, u8 value, unsigned int bytes)
{
while (bytes) {
--
2.7.4
[PATCH V2 2/2] rpmsg: add syslog redirection driver
From: Guiding Li
This driver allows the remote processor to redirect the output of
syslog or printf into the kernel log, which is very useful to see
what happen in the remote side.
Signed-off-by: Guiding Li
---
drivers/rpmsg/Kconfig| 12
drivers/rpmsg/Makefile | 1 +
drivers/rpmsg/rpmsg_syslog.c | 163 +++
3 files changed, 176 insertions(+)
create mode 100644 drivers/rpmsg/rpmsg_syslog.c
diff --git a/drivers/rpmsg/Kconfig b/drivers/rpmsg/Kconfig
index d0322b4..13ead55 100644
--- a/drivers/rpmsg/Kconfig
+++ b/drivers/rpmsg/Kconfig
@@ -15,6 +15,18 @@ config RPMSG_CHAR
in /dev. They make it possible for user-space programs to send and
receive rpmsg packets.
+config RPMSG_SYSLOG
+ tristate "RPMSG syslog redirection"
+ depends on RPMSG
+ help
+ Say Y here to redirect the syslog/printf from remote processor into
+ the kernel log which is very useful to see what happened in the remote
+ side.
+
+ If the remote processor hangs during bootup or panics during runtime,
+ we can even cat /sys/kernel/debug/remoteproc/remoteprocX/trace0 to
+ get the last log which hasn't been output yet.
+
config RPMSG_QCOM_GLINK_NATIVE
tristate
select RPMSG
diff --git a/drivers/rpmsg/Makefile b/drivers/rpmsg/Makefile
index 9aa8595..bfd22df 100644
--- a/drivers/rpmsg/Makefile
+++ b/drivers/rpmsg/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_RPMSG)+= rpmsg_core.o
obj-$(CONFIG_RPMSG_CHAR) += rpmsg_char.o
+obj-$(CONFIG_RPMSG_SYSLOG) += rpmsg_syslog.o
obj-$(CONFIG_RPMSG_QCOM_GLINK_RPM) += qcom_glink_rpm.o
obj-$(CONFIG_RPMSG_QCOM_GLINK_NATIVE) += qcom_glink_native.o
obj-$(CONFIG_RPMSG_QCOM_GLINK_SMEM) += qcom_glink_smem.o
diff --git a/drivers/rpmsg/rpmsg_syslog.c b/drivers/rpmsg/rpmsg_syslog.c
new file mode 100644
index 000..b7a0d27
--- /dev/null
+++ b/drivers/rpmsg/rpmsg_syslog.c
@@ -0,0 +1,163 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 Pinecone Inc.
+ *
+ * redirect syslog/printf from remote to the kernel.
+ */
+
+#include
+#include
+#include
+
+#define RPMSG_SYSLOG_TRANSFER 0
+#define RPMSG_SYSLOG_TRANSFER_DONE 1
+#define RPMSG_SYSLOG_SUSPEND 2
+#define RPMSG_SYSLOG_RESUME3
+
+struct rpmsg_syslog_header {
+ u32 command;
+ s32 result;
+} __packed;
+
+struct rpmsg_syslog_transfer {
+ struct rpmsg_syslog_header header;
+ u32 count;
+ chardata[0];
+} __packed;
+
+#define rpmsg_syslog_suspend rpmsg_syslog_header
+#define rpmsg_syslog_resumerpmsg_syslog_header
+#define rpmsg_syslog_transfer_done rpmsg_syslog_header
+
+struct rpmsg_syslog {
+ char*buf;
+ unsigned intnext;
+ unsigned intsize;
+};
+
+static int rpmsg_syslog_callback(struct rpmsg_device *rpdev,
+void *data, int len, void *priv_, u32 src)
+{
+ struct rpmsg_syslog *priv = dev_get_drvdata(>dev);
+ struct rpmsg_syslog_transfer *msg = data;
+ struct rpmsg_syslog_transfer_done done;
+ unsigned int copied = msg->count;
+ unsigned int printed = 0;
+ const char *nl;
+
+ if (msg->header.command != RPMSG_SYSLOG_TRANSFER)
+ return -EINVAL;
+
+ /* output the message before '\n' to the kernel log */
+ nl = memrchr(msg->data, '\n', msg->count);
+ if (nl) {
+ printed = nl + 1 - msg->data;
+ copied = msg->count - printed;
+
+ if (priv->next) {
+ pr_info("%.*s%.*s", priv->next,
+ priv->buf, printed, msg->data);
+ priv->next = 0;
+ } else {
+ pr_info("%.*s", printed, msg->data);
+ }
+ }
+
+ /* append the message after '\n' to the buffer */
+ if (copied != 0) {
+ unsigned int newsize = priv->next + copied;
+
+ if (newsize > priv->size) {
+ char *newbuf;
+
+ newbuf = krealloc(priv->buf, newsize, GFP_KERNEL);
+ if (newbuf) {
+ priv->buf = newbuf;
+ priv->size = newsize;
+ } else {
+ copied = priv->size - priv->next;
+ }
+ }
+
+ strncpy(priv->buf + priv->next, msg->data + printed, copied);
+ priv->next += copied;
+ }
+
+ done.command = RPMSG_SYSLOG_TRANSFER_DONE;
+ done.result = printed + copied;
+ return rpmsg_send(rpdev->ept, , sizeof(done));
+}
+
+static int
Re: [PATCH 1/3] drm/mediatek: move mipi_dsi_host_register to probe
Just some comments on the error path, I'm not sure about the change itself.
On Thu, Feb 14, 2019 at 12:42 PM Jitao Shi wrote:
>
> DSI panel driver need attach function which is inculde in
> mipi_dsi_host_ops.
>
> If mipi_dsi_host_register is not in probe, dsi panel will
> probe fail or more delay.
>
> So move the mipi_dsi_host_register to probe from bind.
>
> Signed-off-by: Jitao Shi
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 49 ++
> 1 file changed, 30 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
> b/drivers/gpu/drm/mediatek/mtk_dsi.c
> index 27b507eb4a99..93fa255b4aad 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> @@ -1045,12 +1045,6 @@ static int mtk_dsi_bind(struct device *dev, struct
> device *master, void *data)
> return ret;
> }
>
> - ret = mipi_dsi_host_register(>host);
> - if (ret < 0) {
> - dev_err(dev, "failed to register DSI host: %d\n", ret);
> - goto err_ddp_comp_unregister;
> - }
> -
> ret = mtk_dsi_create_conn_enc(drm, dsi);
> if (ret) {
> DRM_ERROR("Encoder create failed with %d\n", ret);
> @@ -1060,8 +1054,6 @@ static int mtk_dsi_bind(struct device *dev, struct
> device *master, void *data)
> return 0;
>
> err_unregister:
> - mipi_dsi_host_unregister(>host);
> -err_ddp_comp_unregister:
> mtk_ddp_comp_unregister(drm, >ddp_comp);
> return ret;
> }
> @@ -1097,31 +1089,37 @@ static int mtk_dsi_probe(struct platform_device *pdev)
>
> dsi->host.ops = _dsi_ops;
> dsi->host.dev = dev;
> + dsi->dev = dev;
> + ret = mipi_dsi_host_register(>host);
> + if (ret < 0) {
> + dev_err(dev, "failed to register DSI host: %d\n", ret);
> + return -EPROBE_DEFER;
return ret
> + }
>
> ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0,
> >panel, >bridge);
> if (ret)
> - return ret;
> + goto err_unregister_host;
>
> dsi->engine_clk = devm_clk_get(dev, "engine");
> if (IS_ERR(dsi->engine_clk)) {
> ret = PTR_ERR(dsi->engine_clk);
> dev_err(dev, "Failed to get engine clock: %d\n", ret);
> - return ret;
> + goto err_unregister_host;
> }
>
> dsi->digital_clk = devm_clk_get(dev, "digital");
> if (IS_ERR(dsi->digital_clk)) {
> ret = PTR_ERR(dsi->digital_clk);
> dev_err(dev, "Failed to get digital clock: %d\n", ret);
> - return ret;
> + goto err_unregister_host;
> }
>
> dsi->hs_clk = devm_clk_get(dev, "hs");
> if (IS_ERR(dsi->hs_clk)) {
> ret = PTR_ERR(dsi->hs_clk);
> dev_err(dev, "Failed to get hs clock: %d\n", ret);
> - return ret;
> + goto err_unregister_host;
> }
>
> regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> @@ -1129,33 +1127,35 @@ static int mtk_dsi_probe(struct platform_device *pdev)
> if (IS_ERR(dsi->regs)) {
> ret = PTR_ERR(dsi->regs);
> dev_err(dev, "Failed to ioremap memory: %d\n", ret);
> - return ret;
> + goto err_unregister_host;
> }
>
> dsi->phy = devm_phy_get(dev, "dphy");
> if (IS_ERR(dsi->phy)) {
> ret = PTR_ERR(dsi->phy);
> dev_err(dev, "Failed to get MIPI-DPHY: %d\n", ret);
> - return ret;
> + goto err_unregister_host;
> }
>
> comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DSI);
> if (comp_id < 0) {
> dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
> - return comp_id;
> + ret = comp_id;
> + goto err_unregister_host;
> }
>
> ret = mtk_ddp_comp_init(dev, dev->of_node, >ddp_comp, comp_id,
> _dsi_funcs);
> if (ret) {
> dev_err(dev, "Failed to initialize component: %d\n", ret);
> - return ret;
> + goto err_unregister_host;
> }
>
> irq_num = platform_get_irq(pdev, 0);
> if (irq_num < 0) {
> dev_err(>dev, "failed to request dsi irq resource\n");
> - return -EPROBE_DEFER;
> + ret = -EPROBE_DEFER;
I think you need to do ret = irq_num here, too (and yes, it was
probably wrong before?)
> + goto err_unregister_host;
> }
>
> irq_set_status_flags(irq_num, IRQ_TYPE_LEVEL_LOW);
> @@ -1163,14 +1163,25 @@ static int mtk_dsi_probe(struct platform_device *pdev)
>IRQF_TRIGGER_LOW, dev_name(>dev), dsi);
> if (ret) {
> dev_err(>dev, "failed to request
Re: [PATCH 0/5] use pinned_vm instead of locked_vm to account pinned pages
On Wed, Feb 13, 2019 at 05:53:14PM -0800, Ira Weiny wrote: > On Mon, Feb 11, 2019 at 03:54:47PM -0700, Jason Gunthorpe wrote: > > On Mon, Feb 11, 2019 at 05:44:32PM -0500, Daniel Jordan wrote: > > > > > All five of these places, and probably some of Davidlohr's conversions, > > > probably want to be collapsed into a common helper in the core mm for > > > accounting pinned pages. I tried, and there are several details that > > > likely need discussion, so this can be done as a follow-on. > > > > I've wondered the same.. > > I'm really thinking this would be a nice way to ensure it gets cleaned up and > does not happen again. > > Also, by moving it to the core we could better manage any user visible > changes. > > From a high level, pinned is a subset of locked so it seems like we need a 2 > sets of helpers. > > try_increment_locked_vm(...) > decrement_locked_vm(...) > > try_increment_pinned_vm(...) > decrement_pinned_vm(...) > > Where try_increment_pinned_vm() also increments locked_vm... Of course this > may end up reverting the improvement of Davidlohr Bueso's atomic work... :-( > > Furthermore it would seem better (although I don't know if at all possible) if > this were accounted for in core calls which tracked them based on how the > pages > are being used so that drivers can't call try_increment_locked_vm() and then > pin the pages... Thus getting the account wrong vs what actually happened. > > And then in the end we can go back to locked_vm being the value checked > against > RLIMIT_MEMLOCK. Someone would need to understand the bug that was fixed by splitting them. I think it had to do with double accounting pinned and mlocked pages and thus delivering a lower than expected limit to userspace. vfio has this bug, RDMA does not. RDMA has a bug where it can overallocate locked memory, vfio doesn't. Really unclear how to fix this. The pinned/locked split with two buckets may be the right way. Jason
Re: [PATCH] scsi: qla2xxx: remove redundant null check on pointer sess
On Wed, Feb 13, 2019 at 01:53:35PM +, Colin King wrote:
> From: Colin Ian King
>
> The null check on pointer sess and the subsequent call is redundant
> as sess is null on all the the paths that lead to the out_term2 label.
> Hence the null check and the call can be removed.
>
> Detected by CoverityScan, CID#1420663 ("Logically dead code")
>
> Signed-off-by: Colin Ian King
> ---
> drivers/scsi/qla2xxx/qla_target.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/drivers/scsi/qla2xxx/qla_target.c
> b/drivers/scsi/qla2xxx/qla_target.c
> index 6b8c655d9eb4..9af329a5ed90 100644
> --- a/drivers/scsi/qla2xxx/qla_target.c
> +++ b/drivers/scsi/qla2xxx/qla_target.c
> @@ -6396,8 +6396,6 @@ static void qlt_tmr_work(struct qla_tgt *tgt,
> return;
>
> out_term2:
> - if (sess)
> - ha->tgt.tgt_ops->put_sess(sess);
Several places do:
sess = NULL;
goto out_term2;
We could remove the "sess = NULL;" because it's not required now.
> spin_unlock_irqrestore(>tgt.sess_lock, flags);
> out_term:
> qlt_send_term_exchange(ha->base_qpair, NULL, >tm_iocb2, 1, 0);
regards,
dan carpenter
Re: [PATCH 3/3] drm/mediatek: add mt8183 dsi driver support
On Thu, Feb 14, 2019 at 12:43 PM Jitao Shi wrote:
>
> MT8183 dsi has two changes with mt8173.
> 1. Add the register double buffer control, but we no need it, So make
>it default off.
Can you describe a little bit more what this is about? That's shadow
registers, right?
> 2. Add picture size control.
>
> Signed-off-by: Jitao Shi
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 20 +++-
> 1 file changed, 19 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
> b/drivers/gpu/drm/mediatek/mtk_dsi.c
> index 80db02a25cb0..20cb53f05d42 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> @@ -78,6 +78,7 @@
> #define DSI_VBP_NL 0x24
> #define DSI_VFP_NL 0x28
> #define DSI_VACT_NL0x2C
> +#define DSI_SIZE_CON 0x38
> #define DSI_HSA_WC 0x50
> #define DSI_HBP_WC 0x54
> #define DSI_HFP_WC 0x58
> @@ -131,7 +132,10 @@
> #define VM_CMD_EN BIT(0)
> #define TS_VFP_EN BIT(5)
>
> -#define DSI_CMDQ0 0x180
As I said earlier, move this to 2/3.
> +#define DSI_SHADOW_DEBUG 0x190U
> +#define FORCE_COMMIT BIT(0)
> +#define BYPASS_SHADOW BIT(1)
> +
> #define CONFIG (0xff << 0)
> #define SHORT_PACKET 0
> #define LONG_PACKET2
> @@ -158,6 +162,7 @@ struct phy;
>
> struct mtk_dsi_driver_data {
> const u32 reg_cmdq_off;
> + bool has_size_ctl;
> };
>
> struct mtk_dsi {
> @@ -426,6 +431,9 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
> writel(vm->vfront_porch, dsi->regs + DSI_VFP_NL);
> writel(vm->vactive, dsi->regs + DSI_VACT_NL);
>
> + if (dsi->driver_data->has_size_ctl)
> + writel(vm->vactive << 16 | vm->hactive, dsi->regs +
> DSI_SIZE_CON);
> +
> horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10);
>
> if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
> @@ -595,6 +603,9 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
> }
>
> mtk_dsi_enable(dsi);
> +
> + /* DSI no need this double buffer, disable it when writing register */
"DSI does not need double buffering, disable it when writing register"
> + writel(FORCE_COMMIT | BYPASS_SHADOW, dsi->regs + DSI_SHADOW_DEBUG);
So you do this on all MT* variants, is that ok?
> mtk_dsi_reset_engine(dsi);
> mtk_dsi_phy_timconfig(dsi);
>
> @@ -1090,11 +1101,18 @@ static const struct mtk_dsi_driver_data
> mt2701_dsi_driver_data = {
> .reg_cmdq_off = 0x180,
> };
>
> +static const struct mtk_dsi_driver_data mt8183_dsi_driver_data = {
> + .reg_cmdq_off = 0x200,
> + .has_size_ctl = true,
> +};
> +
> static const struct of_device_id mtk_dsi_of_match[] = {
> { .compatible = "mediatek,mt2701-dsi",
> .data = _dsi_driver_data },
> { .compatible = "mediatek,mt8173-dsi",
> .data = _dsi_driver_data },
> + { .compatible = "mediatek,mt8183-dsi",
> + .data = _dsi_driver_data },
> { },
> };
>
> --
> 2.20.1
>
Re: [PATCH 2/3] drm/mediatek: CMDQ reg address of mt8173 is different with mt2701
On Thu, Feb 14, 2019 at 12:42 PM Jitao Shi wrote:
>
> Config the different CMDQ reg address in driver data.
>
> Signed-off-by: Jitao Shi
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 39 --
> 1 file changed, 31 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
> b/drivers/gpu/drm/mediatek/mtk_dsi.c
> index 93fa255b4aad..80db02a25cb0 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> @@ -156,6 +156,10 @@
>
> struct phy;
>
> +struct mtk_dsi_driver_data {
> + const u32 reg_cmdq_off;
> +};
> +
> struct mtk_dsi {
> struct mtk_ddp_comp ddp_comp;
> struct device *dev;
> @@ -182,6 +186,7 @@ struct mtk_dsi {
> bool enabled;
> u32 irq_data;
> wait_queue_head_t irq_wait_queue;
> + struct mtk_dsi_driver_data *driver_data;
> };
>
> static inline struct mtk_dsi *encoder_to_dsi(struct drm_encoder *e)
> @@ -934,6 +939,7 @@ static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const
> struct mipi_dsi_msg *msg)
> const char *tx_buf = msg->tx_buf;
> u8 config, cmdq_size, cmdq_off, type = msg->type;
> u32 reg_val, cmdq_mask, i;
> + u32 reg_cmdq_off = dsi->driver_data->reg_cmdq_off;
>
> if (MTK_DSI_HOST_IS_READ(type))
> config = BTA;
> @@ -953,9 +959,11 @@ static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const
> struct mipi_dsi_msg *msg)
> }
>
> for (i = 0; i < msg->tx_len; i++)
> - writeb(tx_buf[i], dsi->regs + DSI_CMDQ0 + cmdq_off + i);
> + mtk_dsi_mask(dsi, (reg_cmdq_off + cmdq_off + i) & (~0x3U),
> +(0xffUL << (((i + cmdq_off) & 3U) * 8U)),
> +tx_buf[i] << (((i + cmdq_off) & 3U) * 8U));
I found the writeb call _much_ clearer ... Either switch back to that,
or create a new mtk_disk_mask_byte function maybe?
>
> - mtk_dsi_mask(dsi, DSI_CMDQ0, cmdq_mask, reg_val);
> + mtk_dsi_mask(dsi, reg_cmdq_off, cmdq_mask, reg_val);
You're removing DSI_CMDQ0 usage in this patch, so remove the #define
in this patch too (instead of doing that in 3/3).
> mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE, cmdq_size);
> }
>
> @@ -1074,10 +1082,27 @@ static const struct component_ops
> mtk_dsi_component_ops = {
> .unbind = mtk_dsi_unbind,
> };
>
> +static const struct mtk_dsi_driver_data mt8173_dsi_driver_data = {
> + .reg_cmdq_off = 0x200,
> +};
> +
> +static const struct mtk_dsi_driver_data mt2701_dsi_driver_data = {
> + .reg_cmdq_off = 0x180,
> +};
> +
> +static const struct of_device_id mtk_dsi_of_match[] = {
> + { .compatible = "mediatek,mt2701-dsi",
> + .data = _dsi_driver_data },
> + { .compatible = "mediatek,mt8173-dsi",
> + .data = _dsi_driver_data },
> + { },
> +};
> +
> static int mtk_dsi_probe(struct platform_device *pdev)
> {
> struct mtk_dsi *dsi;
> struct device *dev = >dev;
> + const struct of_device_id *of_id;
> struct resource *regs;
> int irq_num;
> int comp_id;
> @@ -1101,6 +1126,10 @@ static int mtk_dsi_probe(struct platform_device *pdev)
> if (ret)
> goto err_unregister_host;
>
> + of_id = of_match_device(mtk_dsi_of_match, >dev);
> + dsi->driver_data = (struct mtk_dsi_driver_data *)
> + of_id->data;
This fits in 80 chars. Also, of_id->data is a void*, so no cast needed.
> +
> dsi->engine_clk = devm_clk_get(dev, "engine");
> if (IS_ERR(dsi->engine_clk)) {
> ret = PTR_ERR(dsi->engine_clk);
> @@ -1194,12 +1223,6 @@ static int mtk_dsi_remove(struct platform_device *pdev)
> return 0;
> }
>
> -static const struct of_device_id mtk_dsi_of_match[] = {
> - { .compatible = "mediatek,mt2701-dsi" },
> - { .compatible = "mediatek,mt8173-dsi" },
> - { },
> -};
Any reason you moved this up?
> -
> struct platform_driver mtk_dsi_driver = {
> .probe = mtk_dsi_probe,
> .remove = mtk_dsi_remove,
> --
> 2.20.1
>
Re: [PATCH v6 6/6] arm64: dts: Add Mediatek SoC MT8183 and evaluation board dts and Makefile
On Wed, 2019-02-13 at 15:54 +0100, Matthias Brugger wrote:
>
> On 13/02/2019 10:03, Erin Lo wrote:
> > On Thu, 2019-02-07 at 16:30 +0100, Matthias Brugger wrote:
> >>
> >> On 24/01/2019 09:07, Erin Lo wrote:
> >>> From: Ben Ho
> >>>
> >>> Add basic chip support for Mediatek 8183, include
> >>> pinctrl file, uart node with correct uart clocks, pwrap device
> >>>
> >>> Add clock controller nodes, include topckgen, infracfg,
> >>> apmixedsys and subsystem.
> >>>
> >>> Signed-off-by: Ben Ho
> >>> Signed-off-by: Erin Lo
> >>> Signed-off-by: Seiya Wang
> >>> Signed-off-by: Zhiyong Tao
> >>> Signed-off-by: Weiyi Lu
> >>> Signed-off-by: Mengqi Zhang
> >>> Signed-off-by: Hsin-Hsiung Wang
> >>> Signed-off-by: Eddie Huang
> >>> ---
> >>> arch/arm64/boot/dts/mediatek/Makefile |1 +
> >>> arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 136 +++
> >>> arch/arm64/boot/dts/mediatek/mt8183-pinfunc.h | 1120
> >>> +
> >>
> >> Would you mind to make the pinfunc.h a seperate patch and adding the
> >> pinctrl
> >> maintainers to the list.
> >>
> >> Regards,
> >> Matthias
> >>
> >
> > OK! I will take pinfunc.h out of this series.
>
> My take would be to somehow change this series in something like.
> One patch which adds basic support for the SoC without any dependencies on
> other
> series.
> Every node that has a dependency on a different series should go in a separate
> patch. In this case IMHO pinfunc.h can got with the dts node in one patch.
>
> Regards,
> Matthias
>
I will separate this patch into 3 patches : basic support for the SoC,
mt8183-pinfunc.h, and spi node.
Is that OK?
Is it ok, if pinctrl@1000b000 is included in basic node?
Best Regards.
Erin
> >
> > Best Regards,
> > Erin
> >
> >>> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 408 +
> >>> 4 files changed, 1665 insertions(+)
> >>> create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> >>> create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-pinfunc.h
> >>> create mode 100644 arch/arm64/boot/dts/mediatek/mt8183.dtsi
> >>>
> >>> diff --git a/arch/arm64/boot/dts/mediatek/Makefile
> >>> b/arch/arm64/boot/dts/mediatek/Makefile
> >>> index e8f952f..458bbc4 100644
> >>> --- a/arch/arm64/boot/dts/mediatek/Makefile
> >>> +++ b/arch/arm64/boot/dts/mediatek/Makefile
> >>> @@ -7,3 +7,4 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
> >>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb
> >>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb
> >>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb
> >>> +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb
> >>> diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> >>> b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> >>> new file mode 100644
> >>> index 000..b12c6ea
> >>> --- /dev/null
> >>> +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> >>> @@ -0,0 +1,136 @@
> >>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> >>> +/*
> >>> + * Copyright (c) 2018 MediaTek Inc.
> >>> + * Author: Ben Ho
> >>> + * Erin Lo
> >>> + */
> >>> +
> >>> +/dts-v1/;
> >>> +#include "mt8183.dtsi"
> >>> +
> >>> +/ {
> >>> + model = "MediaTek MT8183 evaluation board";
> >>> + compatible = "mediatek,mt8183-evb", "mediatek,mt8183";
> >>> +
> >>> + aliases {
> >>> + serial0 =
> >>> + };
> >>> +
> >>> + memory@4000 {
> >>> + device_type = "memory";
> >>> + reg = <0 0x4000 0 0x8000>;
> >>> + };
> >>> +
> >>> + chosen {
> >>> + stdout-path = "serial0:921600n8";
> >>> + };
> >>> +};
> >>> +
> >>> + {
> >>> + spi_pins_0: spi0{
> >>> + pins_spi{
> >>> + pinmux = ,
> >>> + ,
> >>> + ,
> >>> + ;
> >>> + bias-disable;
> >>> + };
> >>> + };
> >>> +
> >>> + spi_pins_1: spi1{
> >>> + pins_spi{
> >>> + pinmux = ,
> >>> + ,
> >>> + ,
> >>> + ;
> >>> + bias-disable;
> >>> + };
> >>> + };
> >>> +
> >>> + spi_pins_2: spi2{
> >>> + pins_spi{
> >>> + pinmux = ,
> >>> + ,
> >>> + ,
> >>> + ;
> >>> + bias-disable;
> >>> + };
> >>> + };
> >>> +
> >>> + spi_pins_3: spi3{
> >>> + pins_spi{
> >>> + pinmux = ,
> >>> + ,
> >>> + ,
> >>> + ;
> >>> + bias-disable;
> >>> + };
> >>> + };
> >>> +
> >>> + spi_pins_4: spi4{
> >>> + pins_spi{
> >>> + pinmux = ,
> >>> + ,
> >>> + ,
> >>> + ;
> >>> + bias-disable;
> >>> + };
> >>> + };
> >>> +
> >>> + spi_pins_5: spi5{
> >>> + pins_spi{
> >>> + pinmux = ,
[PATCH] perf trace: Fix potential USE_AFTER_FREE problem
From: Bo Yu
There is a freed pointer "evsel", so fix it.
Detected by CoverityScan, CID#1442595("Memory-illegalaccesses
(USE_AFTER_FREE)")
Fixes: 6ab3bc240ade4("perf trace: Support multiple "vfs_getname" probes")
Signed-off-by: Bo Yu
---
tools/perf/builtin-trace.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/perf/builtin-trace.c b/tools/perf/builtin-trace.c
index b36061cd1ab8..4036b20a1067 100644
--- a/tools/perf/builtin-trace.c
+++ b/tools/perf/builtin-trace.c
@@ -2515,7 +2515,7 @@ static size_t trace__fprintf_thread_summary(struct trace
*trace, FILE *fp);
static bool perf_evlist__add_vfs_getname(struct perf_evlist *evlist)
{
bool found = false;
- struct perf_evsel *evsel, *tmp;
+ struct perf_evsel *evsel = NULL, *tmp;
struct parse_events_error err = { .idx = 0, };
int ret = parse_events(evlist, "probe:vfs_getname*", );
--
2.11.0
[RFC PATCH v2] PCI/portdrv: Support for subtractive decode bridge
From: Honghui Zhang
The Class Code for subtractive decode PCI-to-PCI bridge is 060401h,
add one entry to make portdrv support this type bridge.
Signed-off-by: Honghui Zhang
---
drivers/pci/pcie/portdrv_pci.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/pci/pcie/portdrv_pci.c b/drivers/pci/pcie/portdrv_pci.c
index 0acca35..c129f2f 100644
--- a/drivers/pci/pcie/portdrv_pci.c
+++ b/drivers/pci/pcie/portdrv_pci.c
@@ -185,6 +185,8 @@ static void pcie_portdrv_err_resume(struct pci_dev *dev)
static const struct pci_device_id port_pci_ids[] = { {
/* handle any PCI-Express port */
PCI_DEVICE_CLASS(((PCI_CLASS_BRIDGE_PCI << 8) | 0x00), ~0),
+ /* subtractive decode PCI-to-PCI bridge, class type is 060401h */
+ PCI_DEVICE_CLASS(((PCI_CLASS_BRIDGE_PCI << 8) | 0x01), ~0),
}, { /* end: all zeroes */ }
};
--
2.6.4
RE: [PATCH] drm/amdgpu: Error handling issues about CHECKED_RETURN
> -Original Message-
> From: Bo YU
> Sent: Thursday, February 14, 2019 12:46 PM
> To: Deucher, Alexander ; Koenig, Christian
> ; Zhou, David(ChunMing)
> ; airl...@linux.ie; dan...@ffwll.ch; Zhu, Rex
> ; Grodzovsky, Andrey
> ; dri-de...@lists.freedesktop.org; linux-
> ker...@vger.kernel.org
> Cc: Bo Yu ; amd-...@lists.freedesktop.org
> Subject: [PATCH] drm/amdgpu: Error handling issues about
> CHECKED_RETURN
>
> From: Bo Yu
>
> Calling "amdgpu_ring_test_helper" without checking return value
We could need to continue to ring test even there is one ring test failed.
-David
>
> Signed-off-by: Bo Yu
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index 57cb3a51bda7..48465a61516b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -4728,7 +4728,9 @@ static int gfx_v8_0_cp_test_all_rings(struct
> amdgpu_device *adev)
>
> for (i = 0; i < adev->gfx.num_compute_rings; i++) {
> ring = >gfx.compute_ring[i];
> - amdgpu_ring_test_helper(ring);
> + r = amdgpu_ring_test_helper(ring);
> + if (r)
> + return r;
> }
>
> return 0;
> --
> 2.11.0
Re: [PATCH 11/15] PCI: pci-epf-test: Use pci_epc_get_features to get EPC features
Hi Lorenzo,
On 13/02/19 8:06 PM, Lorenzo Pieralisi wrote:
> On Wed, Feb 13, 2019 at 07:08:18PM +0530, Kishon Vijay Abraham I wrote:
>> Hi Lorenzo,
>>
>> On 12/02/19 8:37 PM, Lorenzo Pieralisi wrote:
>>> On Mon, Jan 07, 2019 at 12:11:44PM +0530, Kishon Vijay Abraham I wrote:
>>>
>>> [...]
>>>
static int pci_epf_test_bind(struct pci_epf *epf)
{
int ret;
struct pci_epf_test *epf_test = epf_get_drvdata(epf);
struct pci_epf_header *header = epf->header;
+ const struct pci_epc_features *epc_features;
+ enum pci_barno test_reg_bar = BAR_0;
struct pci_epc *epc = epf->epc;
struct device *dev = >dev;
+ bool linkup_notifier = false;
+ bool msix_capable = false;
+ bool msi_capable = true;
if (WARN_ON_ONCE(!epc))
return -EINVAL;
- if (epc->features & EPC_FEATURE_NO_LINKUP_NOTIFIER)
- epf_test->linkup_notifier = false;
- else
- epf_test->linkup_notifier = true;
-
- epf_test->msix_available = epc->features & EPC_FEATURE_MSIX_AVAILABLE;
+ epc_features = pci_epc_get_features(epc, epf->func_no);
>>>
>>> I think it would work out better if struct pci_epc_features was
>>> allocated in the caller (stack) and pci_epc_get_features() take a
>>> pointer parameter to it rather than the callee and the callee would just
>>> have to fill it out, this also removes data in the driver that is not
>>> really useful.
>>>
>>> Is there any other reason behind the current design choice ?
>>
>> Some drivers are used by multiple platforms each with different features. In
>> such cases it's cleaner to have separate epc_feature table for each platform.
>>
>> I think the driver should maintain some sort of data to even populate
>> pci_epc_features allocated by EP function driver.
>
> You mean that every EP controller driver should keep a table of
> pci_epc_features (instead of a single instance) to be matched using DT
> compatible strings to detect the platform variations ?
Yes.
Thanks
Kishon
Re: [PATCH] qlge: fix some indentation issues
From: Colin King Date: Tue, 12 Feb 2019 16:08:07 + > From: Colin Ian King > > There are some statements that are indented incorrectly. Fix these. > > Signed-off-by: Colin Ian King Applied to net-next.
Re: [PATCH] qed: fix indentation issue with statements in an if-block
From: Colin King Date: Tue, 12 Feb 2019 16:01:53 + > From: Colin Ian King > > There are some statements in an if-block that are not correctly > indented. Fix these. > > Signed-off-by: Colin Ian King Applied to net-next.
Re: [PATCH v3 6/7] trace: events: add devfreq trace event file
Hi Lukasz,
On 19. 2. 13. 오후 10:35, Lukasz Luba wrote:
> Hi Steven,
>
> On 2/13/19 12:14 AM, Steven Rostedt wrote:
>> On Tue, 12 Feb 2019 23:23:57 +0100
>> Lukasz Luba wrote:
>>
>>> The patch adds a new file for with trace events for devfreq
>>> framework. They are used for performance analysis of the framework.
>>> It also contains updates in MAINTAINERS file adding new entry for
>>> devfreq maintainers.
>>>
>>> Signed-off-by: Lukasz Luba
>>> ---
>>> MAINTAINERS| 1 +
>>> include/trace/events/devfreq.h | 39
>>> +++
>>> 2 files changed, 40 insertions(+)
>>> create mode 100644 include/trace/events/devfreq.h
>>>
>>> diff --git a/MAINTAINERS b/MAINTAINERS
>>> index 9919840..c042fda 100644
>>> --- a/MAINTAINERS
>>> +++ b/MAINTAINERS
>>> @@ -4447,6 +4447,7 @@ S:Maintained
>>> F:drivers/devfreq/
>>> F:include/linux/devfreq.h
>>> F:Documentation/devicetree/bindings/devfreq/
>>> +F: include/trace/events/devfreq.h
>>>
>>> DEVICE FREQUENCY EVENT (DEVFREQ-EVENT)
>>> M:Chanwoo Choi
>>> diff --git a/include/trace/events/devfreq.h b/include/trace/events/devfreq.h
>>> new file mode 100644
>>> index 000..fec9304
>>> --- /dev/null
>>> +++ b/include/trace/events/devfreq.h
>>> @@ -0,0 +1,39 @@
>>> +/* SPDX-License-Identifier: GPL-2.0 */
>>> +#undef TRACE_SYSTEM
>>> +#define TRACE_SYSTEM devfreq
>>> +
>>> +#if !defined(_TRACE_DEVFREQ_H) || defined(TRACE_HEADER_MULTI_READ)
>>> +#define _TRACE_DEVFREQ_H
>>> +
>>> +#include
>>> +#include
>>> +
>>> +TRACE_EVENT(devfreq_monitor,
>>> + TP_PROTO(const char *dev_name, unsigned long freq,
>>> +unsigned int polling_ms, unsigned long busy_time,
>>> +unsigned long total_time),
>>> +
>>> + TP_ARGS(dev_name, freq, polling_ms, busy_time, total_time),
>>> +
>>> + TP_STRUCT__entry(
>>> + __string(dev_name, dev_name)
>>> + __field(unsigned long, freq)
>>> + __field(unsigned int, polling_ms)
>>> + __field(unsigned int, load)
>>> + ),
>>> +
>>> + TP_fast_assign(
>>> + __assign_str(dev_name, dev_name);
>>> + __entry->freq = freq;
>>> + __entry->polling_ms = polling_ms;
>>> + __entry->load = (100 * busy_time) / total_time;
>>
>> How critical is the code that this trace event is called in. If it is
>> not that critical (it is a slow path), then this is fine, but if this
>> is not a slow path (something triggered 100 HZ or less), then I would
>> recommend moving the above calculation to TP_printk(). A divide is a
>> slow operation, and is best to do that in the post processing. The
>> current location does the divide at the time of the tracepoint is
>> called.
> I wasn't aware of these two stages, good to know.
> I will move it to TP_printk().
>>
>> I would also have a check to make sure that total_time is not zero
>> here, otherwise that could be bad.
>>
>> __entry->busy_time = busy_time;
>> __entry->total_time = total_time;
>>
>
>>> + ),
>>> +
>>> + TP_printk("dev_name=%s freq=%lu polling_ms=%u load=%u",
>>
>>
>>> + __get_str(dev_name), __entry->freq, __entry->polling_ms,
>>
>> __entry->total_time == 0 ? 100 :
>> __entry->busy_time / __entry->total_time)
> Thank you for the review.
> I will add this check.
>
> Regards,
> Lukasz
>>
>> -- Steve
>>
>>> + __entry->load)
>>> +);
>>> +#endif /* _TRACE_DEVFREQ_H */
>>> +
>>> +/* This part must be outside protection */
>>> +#include
>>
>>
>>
>
>
I agree that trace point is necessary for devfreq framework.
Reviewed-by: Chanwoo Choi
--
Best Regards,
Chanwoo Choi
Samsung Electronics
RE: Re: [PATCH v4 6/6] RISC-V: Free-up initrd in free_initrd_mem()
Hi, > On Wed, Feb 13, 2019 at 09:54:15AM -0800, Christoph Hellwig wrote: > > On Wed, Feb 13, 2019 at 09:38:36AM +0200, Mike Rapoport wrote: > > > memblock_free() is has no real effect at this point, no idea why arm64 > > > calls it. > > > > Looks like the call was added fairly recently by: > > > > commit 05c58752f9dce11e396676eb731a620541590ed0 > > Author: CHANDAN VN > > Date: Mon Apr 30 09:50:18 2018 +0530 > > > > arm64: To remove initrd reserved area entry from memblock > > > > which claims it is to work around the initrd being displayed in > > /sys/kernel/debug/memblock/reserved. > > > > I really think we need to have common behavior there - either do this > > for all architectures or none. I've just sent a series that > > consolidates all but a handful of the free_initrd_mem, so implementing > > any common behavior on top of that would be good. > > I've just started to look into it today :) > I'll reply on that thread. INITRD reserved area entry is not removed from memblock even though initrd reserved area is freed. The same can be checked from /sys/kernel/debug/memblock/reserved. We did not face this issue on arm32 architecture. Though the changes which i had submitted does not fix any memory leak, it does make sure that the entries freed from memblock are actually removed from the sys entry as well. Also the implementation of arm64 is quite different from arm32. I feel a generic implementation can be taken up only if its a real necessity.
Re: [PATCH v3 3/9] PCI: keystone: Use hwirq to get the legacy IRQ number offset
Hi Lorenzo,
On 13/02/19 10:27 PM, Lorenzo Pieralisi wrote:
> On Wed, Feb 13, 2019 at 06:56:23PM +0530, Kishon Vijay Abraham I wrote:
>> ks_pcie_legacy_irq_handler() uses 'virq' to get the IRQ number offset.
>> This offset is used to get the correct IRQ_STATUS register
>> corresponding to the IRQ line that raised the interrupt.
>> There is no guarantee that 'virq' assigned for consecutive hardware
>> IRQ will be contiguous. And this might get us an incorrect IRQ number
>> offset.
>>
>> Fix it here by using 'hwirq' to get the IRQ number offset.
>>
>> Link: https://lkml.kernel.org/r/bb081d21-7c03-0357-4294-7e92d95d8...@arm.com
>> Signed-off-by: Kishon Vijay Abraham I
>> ---
>> drivers/pci/controller/dwc/pci-keystone.c | 17 +
>> 1 file changed, 13 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/pci/controller/dwc/pci-keystone.c
>> b/drivers/pci/controller/dwc/pci-keystone.c
>> index e8b1d8eca78e..d35ac712a9f8 100644
>> --- a/drivers/pci/controller/dwc/pci-keystone.c
>> +++ b/drivers/pci/controller/dwc/pci-keystone.c
>> @@ -87,7 +87,7 @@ struct keystone_pcie {
>> struct dw_pcie *pci;
>> /* PCI Device ID */
>> u32 device_id;
>> -int legacy_host_irqs[PCI_NUM_INTX];
>> +int legacy_host_irq;
>> struct device_node *legacy_intc_np;
>>
>> int msi_host_irqs[MAX_MSI_HOST_IRQS];
>> @@ -582,11 +582,11 @@ static void ks_pcie_msi_irq_handler(struct irq_desc
>> *desc)
>> */
>> static void ks_pcie_legacy_irq_handler(struct irq_desc *desc)
>> {
>> -unsigned int irq = irq_desc_get_irq(desc);
>> +unsigned int irq = desc->irq_data.hwirq;
>> struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc);
>> struct dw_pcie *pci = ks_pcie->pci;
>> struct device *dev = pci->dev;
>> -u32 irq_offset = irq - ks_pcie->legacy_host_irqs[0];
>> +u32 irq_offset = irq - ks_pcie->legacy_host_irq;
>
> I think you should use the plain hwirq number (that if I understand
> correctly range in [0,3]) and drop legacy_host_irq.
The hwirq is [80, 83] for Keystone. We store legacy_host_irq (for Keystone it
is 80) to get the correct offset in the range [0, 3].
>
> See below.
>
>> struct irq_chip *chip = irq_desc_get_chip(desc);
>>
>> dev_dbg(dev, ": Handling legacy irq %d\n", irq);
>> @@ -657,6 +657,7 @@ static int ks_pcie_config_legacy_irq(struct
>> keystone_pcie *ks_pcie)
>> struct device_node *np = ks_pcie->np;
>> struct device_node *intc_np;
>> int irq_count, irq, ret, i;
>> +struct irq_data *irq_data;
>>
>> intc_np = of_get_child_by_name(np, "legacy-interrupt-controller");
>> if (!intc_np) {
>> @@ -677,7 +678,15 @@ static int ks_pcie_config_legacy_irq(struct
>> keystone_pcie *ks_pcie)
>> ret = -EINVAL;
>> goto err;
>> }
>> -ks_pcie->legacy_host_irqs[i] = irq;
>> +
>> +if (!ks_pcie->legacy_host_irq) {
>> +irq_data = irq_get_irq_data(irq);
>> +if (!irq_data) {
>> +ret = -EINVAL;
>> +goto err;
>> +}
>> +ks_pcie->legacy_host_irq = irq_data->hwirq;
>
> This depends on DT property ordering and may well be wrong. On top
> of that as I said above I do not think it is even needed.
right, it depends on the ordering of the entries in the "interrupts" property.
Right now we have something like below
interrupts = ,
,
,
;
And changing the order will make legacy_host_irq store the wrong hwirq. With
this patch we solve the problem of assuming virq to be contiguous for
contiguous hwirq however we do expect the hwirqs to be populated in the DT in
the correct order.
Ordering entries within a property is also followed in other properties like
"reg" where the drivers use platform_get_resource with index as argument. I'm
not sure if there's a way to get rid of the ordering requirement in DT for the
"interrupts" property.
Thanks
Kishon
Re: [PATCH v3 7/7] drivers: devfreq: add tracing for scheduling work
Hi Lukasz, On 19. 2. 13. 오전 7:23, Lukasz Luba wrote: > This patch add basic tracing of the devfreq workqueue and delayed work. > It aims to capture changes of the polling intervals and device state. > > Signed-off-by: Lukasz Luba > --- > drivers/devfreq/devfreq.c | 8 > 1 file changed, 8 insertions(+) > > diff --git a/drivers/devfreq/devfreq.c b/drivers/devfreq/devfreq.c > index 29e99ce..c1d0d8c 100644 > --- a/drivers/devfreq/devfreq.c > +++ b/drivers/devfreq/devfreq.c > @@ -29,6 +29,9 @@ > #include > #include "governor.h" > > +#define CREATE_TRACE_POINTS > +#include > + > /* The ~30% load threshold used for load calculation (due to fixed point > * arithmetic) */ > #define LOAD_THRESHOLD_IN_DEVICE_USAGE (300) > @@ -418,6 +421,7 @@ static void devfreq_monitor(struct work_struct *work) > struct devfreq *devfreq = container_of(work, > struct devfreq, work.work); > unsigned int polling_ms; > + const char *df_name = dev_name(>dev); nit: You can use 'dev_name(>dev)' directly without defining the separate df_name. > > mutex_lock(>lock); > polling_ms = devfreq_get_polling_delay(devfreq); > @@ -429,6 +433,10 @@ static void devfreq_monitor(struct work_struct *work) > schedule_delayed_work(>work, > msecs_to_jiffies(polling_ms)); > mutex_unlock(>lock); > + > + trace_devfreq_monitor(df_name, devfreq->previous_freq, polling_ms, > + devfreq->last_status.busy_time, > + devfreq->last_status.total_time); Regardless of type of work, I think that trace point is necessary for devfreq framework. Reviewed-by: Chanwoo Choi > } > > /** > -- Best Regards, Chanwoo Choi Samsung Electronics
Re: [PATCH 3/5] soc: qcom: socinfo: Expose custom attributes
On Thu, 2019-02-14 at 09:11 +0530, Vaishali Thakkar wrote:
> The Qualcomm socinfo provides a number of additional attributes,
> add these to the socinfo driver and expose them via debugfs
> functionality.
trivia:
> diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c
[]
> @@ -70,6 +93,10 @@ struct socinfo {
> struct qcom_socinfo {
> struct soc_device *soc_dev;
> struct soc_device_attribute attr;
> + #ifdef CONFIG_DEBUG_FS
> + struct dentry *dbg_root;
> + #endif /* CONFIG_DEBUG_FS */
It's generally better to move the #ifdef/#endif to column 1
Re: [PATCH v3 4/7] include: devfreq: add polling_idle_ms to 'profile'
Hi Lukasz,
If the user can select the type of work in accordance with
their choice, either deferrable work or delayed work
for periodic without stop on idle state,
I think that the existing polling_ms is enough.
Because, user determine to use the 'delayed work' for periodic timer,
user can change the polling_ms through already provided sysfs interface
according to multiple situation.
In fact,
If the user want to use the periodic timer without stop on idle state
instead of deferrable work, it means that the user always want to
monitor/check the current load/status of device at the correct interval
and then changing the frequency without any latency.
On 19. 2. 13. 오전 7:23, Lukasz Luba wrote:
> Add needed fields to support new state: idle, where different polling
> interval is in use. It provides better control of the devfreq device
> and lower the power consumption when the device is not busy.
>
> Signed-off-by: Lukasz Luba
> ---
> include/linux/devfreq.h | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/include/linux/devfreq.h b/include/linux/devfreq.h
> index fbffa74..5140970 100644
> --- a/include/linux/devfreq.h
> +++ b/include/linux/devfreq.h
> @@ -72,6 +72,11 @@ struct devfreq_dev_status {
> * @initial_freq:The operating frequency when devfreq_add_device() is
> * called.
> * @polling_ms: The polling interval in ms. 0 disables polling.
> + * @polling_idle_ms: The polling interval in 'idle state' in ms.
> + * When the device is running at lowest frequency and has
> + * low-load, it is considered as in 'idle state'.
> + * Thus, longer polling interval is used for the device
> + * to save some power.
> * @target: The device should set its operating frequency at
> * freq or lowest-upper-than-freq value. If freq is
> * higher than any operable frequency, set maximum.
> @@ -98,6 +103,7 @@ struct devfreq_dev_status {
> struct devfreq_dev_profile {
> unsigned long initial_freq;
> unsigned int polling_ms;
> + unsigned int polling_idle_ms;
>
> int (*target)(struct device *dev, unsigned long *freq, u32 flags);
> int (*get_dev_status)(struct device *dev,
>
--
Best Regards,
Chanwoo Choi
Samsung Electronics
Re: [RFC PATCH net-next 2/5] net: 8021q: vlan_dev: add vid tag for uc and mc address lists
On February 13, 2019 8:17:16 AM PST, Ivan Khoronzhuk wrote: >On Tue, Jan 22, 2019 at 03:12:41PM +0200, Ivan Khoronzhuk wrote: >>On Mon, Jan 21, 2019 at 03:37:41PM -0800, Florian Fainelli wrote: >>>On 12/4/18 3:42 PM, Ivan Khoronzhuk wrote: On Tue, Dec 04, 2018 at 11:49:27AM -0800, Florian Fainelli wrote: >> >>[...] >> >>> >>>Ivan, based on the recent submission I copied you on [1], it sounds >like >>>we want to move ahead with your proposal to extend netdev_hw_addr >with a >>>vid member. >>> >>>On second thought, your approach is good and if we enclose the vid >>>member within an #if IS_ENABLED(CONFIG_VLAN)8021Q) we should be good >for >>>most foreseeable use cases, if not, we can always introduce a >variable >>>size/defined context in the future. >>> >>>Can you resubmit this patch series as non-RFC in the next few days so >I >>>can also repost mine [1] and take advantage of these changes for >>>multicast over VLAN when VLAN filtering is globally enabled on the >device. >>> >>>[1]: https://www.spinics.net/lists/netdev/msg544722.html >>> >>>Thanks! >> >>Yes, sure. I can start to do that in several days. >>Just a little busy right now. >> >>Just before doing this, maybe some comments could be added as it has >more >>attention now. Meanwhile I can send alternative variant but based on >>real dev splitting addresses between vlans. In this approach it leaves >address >>space w/o vid extension but requires more changes to vlan core. >Drawback here >>that to change one address alg traverses all related vlan addresses, >it can be >>cpu/time wasteful, if it's done regularly, but saves memory >> >>Basically it's implemented locally in cpsw and requires more changes >to move >>it as some vlan core auxiliary functions to be reused. But it can work >only >>with vlans directly on top of real dev, which is fixable. >> >>Core function here: >>__hw_addr_ref_sync_dev >>it is called only for address the link of which was >increased/decreased, thus >>update made only on one address, comparing it for every vlan dev. >> >>It was added with this patch: >>[1] net: core: dev_addr_lists: add auxiliary func to handle reference >>address update e7946760de5852f32 >> >>And used by this patch: >>[2] net: ethernet: ti: cpsw: fix vlan mcast 15180eca569bfe1d4d >> >>So, idea is to move [2] to be vlan core auxiliary function to be >reused >>by NIC drivers. >> >>But potentially it can bring a little more changes I assume: >> >>1) add priv_flag |= IFF_IV_FLT (independent vlan filtering). It allows >to reuse >>this flag for farther changes, probably for per vlan allmulti or so. >> >>2) real dev has to have complete list for vlans, not only their vids, >but also >>all vlandevs in device chain above it. So changes in add_vid can be >required. >>Vlan core can assign vlan dev pointer to real device only after it's >completely >>initialized. And for propagation reasons it requires every device in >>infrastructure to be aware. That seems doable, but depends not only on >me. >> >>3) Move code from [2] to be auxiliary vlan core API for setting mc and >uc. >>From this patch only one function is cpsw specific: cpsw_set_mc(). The >rest can >>be applicable on every NIC supporting IFF_IV_FLT. >> >>4) Move code from link below to do the same but for uc addresses: >>https://git.linaro.org/people/ivan.khoronzhuk/tsn_kernel.git/commit/?h=ucast_vlan_fix=ebc88a7d8758759322d9ff88f25f8bac51ce7219 >>here only one func cpsw specific: cpsw_set_uc() >>the rest can be generic. >> >>As third alternative, we can think about how to reduce memory for >addresses by >>reusing them or else, but this is as continuation of addr+vid >approach, and API >>probably would be the same. >> >>Then all this can be compared for proper decision. > > >Hi Florian, > >After several more investigations and tries probably better left this >idea as is. Thank you for keeping the thread alive, does that mean you are going to resubmit this patch series as-is (rebased) or are you saying that you are abandoning the idea and leaving the situation the way it is in cpsw? > >Here actually several explanations for this: >1) If even assume that we can get access to vlan devices in the above >ndev >tree (we can) that doesn't guarantee that receive vlan filters are set >replicating this structure. For example bond device can have one active >slave >but both of them in the tree having vid set, in this case addresses are >syched only with active slave, no filters should be applied to not >active slave. >this can be achieved only each address has vid context. > >2) According to 1) rx filters device structure can be created while >mc_sync() >in each rx_mode(), and then used as orthogonal info. I've tried and it >looks >not cool and consumes anyway memory and even if it's less it's still >not very >scalable. (+ no normal signal "in complex structure case" when address >should >be undated to avoid redundant cpu cycles). Not sure it can have >practical >results and be universal enouph. > >3)
[PATCH] drm/amdgpu: Error handling issues about CHECKED_RETURN
From: Bo Yu
Calling "amdgpu_ring_test_helper" without checking return value
Signed-off-by: Bo Yu
---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 57cb3a51bda7..48465a61516b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4728,7 +4728,9 @@ static int gfx_v8_0_cp_test_all_rings(struct
amdgpu_device *adev)
for (i = 0; i < adev->gfx.num_compute_rings; i++) {
ring = >gfx.compute_ring[i];
- amdgpu_ring_test_helper(ring);
+ r = amdgpu_ring_test_helper(ring);
+ if (r)
+ return r;
}
return 0;
--
2.11.0
[PATCH 3/3] drm/mediatek: add mt8183 dsi driver support
MT8183 dsi has two changes with mt8173.
1. Add the register double buffer control, but we no need it, So make
it default off.
2. Add picture size control.
Signed-off-by: Jitao Shi
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 20 +++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 80db02a25cb0..20cb53f05d42 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -78,6 +78,7 @@
#define DSI_VBP_NL 0x24
#define DSI_VFP_NL 0x28
#define DSI_VACT_NL0x2C
+#define DSI_SIZE_CON 0x38
#define DSI_HSA_WC 0x50
#define DSI_HBP_WC 0x54
#define DSI_HFP_WC 0x58
@@ -131,7 +132,10 @@
#define VM_CMD_EN BIT(0)
#define TS_VFP_EN BIT(5)
-#define DSI_CMDQ0 0x180
+#define DSI_SHADOW_DEBUG 0x190U
+#define FORCE_COMMIT BIT(0)
+#define BYPASS_SHADOW BIT(1)
+
#define CONFIG (0xff << 0)
#define SHORT_PACKET 0
#define LONG_PACKET2
@@ -158,6 +162,7 @@ struct phy;
struct mtk_dsi_driver_data {
const u32 reg_cmdq_off;
+ bool has_size_ctl;
};
struct mtk_dsi {
@@ -426,6 +431,9 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
writel(vm->vfront_porch, dsi->regs + DSI_VFP_NL);
writel(vm->vactive, dsi->regs + DSI_VACT_NL);
+ if (dsi->driver_data->has_size_ctl)
+ writel(vm->vactive << 16 | vm->hactive, dsi->regs +
DSI_SIZE_CON);
+
horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10);
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
@@ -595,6 +603,9 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
}
mtk_dsi_enable(dsi);
+
+ /* DSI no need this double buffer, disable it when writing register */
+ writel(FORCE_COMMIT | BYPASS_SHADOW, dsi->regs + DSI_SHADOW_DEBUG);
mtk_dsi_reset_engine(dsi);
mtk_dsi_phy_timconfig(dsi);
@@ -1090,11 +1101,18 @@ static const struct mtk_dsi_driver_data
mt2701_dsi_driver_data = {
.reg_cmdq_off = 0x180,
};
+static const struct mtk_dsi_driver_data mt8183_dsi_driver_data = {
+ .reg_cmdq_off = 0x200,
+ .has_size_ctl = true,
+};
+
static const struct of_device_id mtk_dsi_of_match[] = {
{ .compatible = "mediatek,mt2701-dsi",
.data = _dsi_driver_data },
{ .compatible = "mediatek,mt8173-dsi",
.data = _dsi_driver_data },
+ { .compatible = "mediatek,mt8183-dsi",
+ .data = _dsi_driver_data },
{ },
};
--
2.20.1
[PATCH 1/3] drm/mediatek: move mipi_dsi_host_register to probe
DSI panel driver need attach function which is inculde in
mipi_dsi_host_ops.
If mipi_dsi_host_register is not in probe, dsi panel will
probe fail or more delay.
So move the mipi_dsi_host_register to probe from bind.
Signed-off-by: Jitao Shi
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 49 ++
1 file changed, 30 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 27b507eb4a99..93fa255b4aad 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -1045,12 +1045,6 @@ static int mtk_dsi_bind(struct device *dev, struct
device *master, void *data)
return ret;
}
- ret = mipi_dsi_host_register(>host);
- if (ret < 0) {
- dev_err(dev, "failed to register DSI host: %d\n", ret);
- goto err_ddp_comp_unregister;
- }
-
ret = mtk_dsi_create_conn_enc(drm, dsi);
if (ret) {
DRM_ERROR("Encoder create failed with %d\n", ret);
@@ -1060,8 +1054,6 @@ static int mtk_dsi_bind(struct device *dev, struct device
*master, void *data)
return 0;
err_unregister:
- mipi_dsi_host_unregister(>host);
-err_ddp_comp_unregister:
mtk_ddp_comp_unregister(drm, >ddp_comp);
return ret;
}
@@ -1097,31 +1089,37 @@ static int mtk_dsi_probe(struct platform_device *pdev)
dsi->host.ops = _dsi_ops;
dsi->host.dev = dev;
+ dsi->dev = dev;
+ ret = mipi_dsi_host_register(>host);
+ if (ret < 0) {
+ dev_err(dev, "failed to register DSI host: %d\n", ret);
+ return -EPROBE_DEFER;
+ }
ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0,
>panel, >bridge);
if (ret)
- return ret;
+ goto err_unregister_host;
dsi->engine_clk = devm_clk_get(dev, "engine");
if (IS_ERR(dsi->engine_clk)) {
ret = PTR_ERR(dsi->engine_clk);
dev_err(dev, "Failed to get engine clock: %d\n", ret);
- return ret;
+ goto err_unregister_host;
}
dsi->digital_clk = devm_clk_get(dev, "digital");
if (IS_ERR(dsi->digital_clk)) {
ret = PTR_ERR(dsi->digital_clk);
dev_err(dev, "Failed to get digital clock: %d\n", ret);
- return ret;
+ goto err_unregister_host;
}
dsi->hs_clk = devm_clk_get(dev, "hs");
if (IS_ERR(dsi->hs_clk)) {
ret = PTR_ERR(dsi->hs_clk);
dev_err(dev, "Failed to get hs clock: %d\n", ret);
- return ret;
+ goto err_unregister_host;
}
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -1129,33 +1127,35 @@ static int mtk_dsi_probe(struct platform_device *pdev)
if (IS_ERR(dsi->regs)) {
ret = PTR_ERR(dsi->regs);
dev_err(dev, "Failed to ioremap memory: %d\n", ret);
- return ret;
+ goto err_unregister_host;
}
dsi->phy = devm_phy_get(dev, "dphy");
if (IS_ERR(dsi->phy)) {
ret = PTR_ERR(dsi->phy);
dev_err(dev, "Failed to get MIPI-DPHY: %d\n", ret);
- return ret;
+ goto err_unregister_host;
}
comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DSI);
if (comp_id < 0) {
dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
- return comp_id;
+ ret = comp_id;
+ goto err_unregister_host;
}
ret = mtk_ddp_comp_init(dev, dev->of_node, >ddp_comp, comp_id,
_dsi_funcs);
if (ret) {
dev_err(dev, "Failed to initialize component: %d\n", ret);
- return ret;
+ goto err_unregister_host;
}
irq_num = platform_get_irq(pdev, 0);
if (irq_num < 0) {
dev_err(>dev, "failed to request dsi irq resource\n");
- return -EPROBE_DEFER;
+ ret = -EPROBE_DEFER;
+ goto err_unregister_host;
}
irq_set_status_flags(irq_num, IRQ_TYPE_LEVEL_LOW);
@@ -1163,14 +1163,25 @@ static int mtk_dsi_probe(struct platform_device *pdev)
IRQF_TRIGGER_LOW, dev_name(>dev), dsi);
if (ret) {
dev_err(>dev, "failed to request mediatek dsi irq\n");
- return -EPROBE_DEFER;
+ ret = -EPROBE_DEFER;
+ goto err_unregister_host;
}
init_waitqueue_head(>irq_wait_queue);
platform_set_drvdata(pdev, dsi);
- return component_add(>dev, _dsi_component_ops);
+ ret = component_add(>dev, _dsi_component_ops);
+ if (ret) {
+ ret = -EPROBE_DEFER;
+ goto err_unregister_host;
+ }
+
+
[PATCH 2/3] drm/mediatek: CMDQ reg address of mt8173 is different with mt2701
Config the different CMDQ reg address in driver data.
Signed-off-by: Jitao Shi
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 39 --
1 file changed, 31 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 93fa255b4aad..80db02a25cb0 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -156,6 +156,10 @@
struct phy;
+struct mtk_dsi_driver_data {
+ const u32 reg_cmdq_off;
+};
+
struct mtk_dsi {
struct mtk_ddp_comp ddp_comp;
struct device *dev;
@@ -182,6 +186,7 @@ struct mtk_dsi {
bool enabled;
u32 irq_data;
wait_queue_head_t irq_wait_queue;
+ struct mtk_dsi_driver_data *driver_data;
};
static inline struct mtk_dsi *encoder_to_dsi(struct drm_encoder *e)
@@ -934,6 +939,7 @@ static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct
mipi_dsi_msg *msg)
const char *tx_buf = msg->tx_buf;
u8 config, cmdq_size, cmdq_off, type = msg->type;
u32 reg_val, cmdq_mask, i;
+ u32 reg_cmdq_off = dsi->driver_data->reg_cmdq_off;
if (MTK_DSI_HOST_IS_READ(type))
config = BTA;
@@ -953,9 +959,11 @@ static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct
mipi_dsi_msg *msg)
}
for (i = 0; i < msg->tx_len; i++)
- writeb(tx_buf[i], dsi->regs + DSI_CMDQ0 + cmdq_off + i);
+ mtk_dsi_mask(dsi, (reg_cmdq_off + cmdq_off + i) & (~0x3U),
+(0xffUL << (((i + cmdq_off) & 3U) * 8U)),
+tx_buf[i] << (((i + cmdq_off) & 3U) * 8U));
- mtk_dsi_mask(dsi, DSI_CMDQ0, cmdq_mask, reg_val);
+ mtk_dsi_mask(dsi, reg_cmdq_off, cmdq_mask, reg_val);
mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE, cmdq_size);
}
@@ -1074,10 +1082,27 @@ static const struct component_ops mtk_dsi_component_ops
= {
.unbind = mtk_dsi_unbind,
};
+static const struct mtk_dsi_driver_data mt8173_dsi_driver_data = {
+ .reg_cmdq_off = 0x200,
+};
+
+static const struct mtk_dsi_driver_data mt2701_dsi_driver_data = {
+ .reg_cmdq_off = 0x180,
+};
+
+static const struct of_device_id mtk_dsi_of_match[] = {
+ { .compatible = "mediatek,mt2701-dsi",
+ .data = _dsi_driver_data },
+ { .compatible = "mediatek,mt8173-dsi",
+ .data = _dsi_driver_data },
+ { },
+};
+
static int mtk_dsi_probe(struct platform_device *pdev)
{
struct mtk_dsi *dsi;
struct device *dev = >dev;
+ const struct of_device_id *of_id;
struct resource *regs;
int irq_num;
int comp_id;
@@ -1101,6 +1126,10 @@ static int mtk_dsi_probe(struct platform_device *pdev)
if (ret)
goto err_unregister_host;
+ of_id = of_match_device(mtk_dsi_of_match, >dev);
+ dsi->driver_data = (struct mtk_dsi_driver_data *)
+ of_id->data;
+
dsi->engine_clk = devm_clk_get(dev, "engine");
if (IS_ERR(dsi->engine_clk)) {
ret = PTR_ERR(dsi->engine_clk);
@@ -1194,12 +1223,6 @@ static int mtk_dsi_remove(struct platform_device *pdev)
return 0;
}
-static const struct of_device_id mtk_dsi_of_match[] = {
- { .compatible = "mediatek,mt2701-dsi" },
- { .compatible = "mediatek,mt8173-dsi" },
- { },
-};
-
struct platform_driver mtk_dsi_driver = {
.probe = mtk_dsi_probe,
.remove = mtk_dsi_remove,
--
2.20.1
Re: [PATCH 3/3] leaking_addresses: Expand tilde in output file name
On Thu, Feb 07, 2019 at 04:35:55PM -0700, Tycho Andersen wrote:
> On Fri, Feb 08, 2019 at 09:50:26AM +1100, Tobin C. Harding wrote:
> > Currently if user passes an output file to the script via
> > --output-raw we do not handle expansion of tilde.
> >
> > Use perl function glob() to expand tilde in output file name.
> >
> > Signed-off-by: Tobin C. Harding
> > ---
> > scripts/leaking_addresses.pl | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/scripts/leaking_addresses.pl b/scripts/leaking_addresses.pl
> > index ef9e5b2a1614..ce545ca3fb70 100755
> > --- a/scripts/leaking_addresses.pl
> > +++ b/scripts/leaking_addresses.pl
> > @@ -150,7 +150,7 @@ if (!(is_supported_architecture() or $opt_32bit or
> > $page_offset_32bit)) {
> > }
> >
> > if ($output_raw) {
> > - open my $fh, '>', $output_raw or die "$0: $output_raw: $!\n";
> > + open my $fh, '>', glob($output_raw) or die "$0: $output_raw: $!\n";
>
> Seems like you might also have the same problem with $input_raw? I
> wonder if you can just do this in GetOptions somehow, so that all
> users of these further down in the script don't have to remember to do
> this.
I don't know what changed between now and when I first wrote this patch
(a fair while ago) but I just tested with bash and zsh _without_ this
patch and tilde was handled fine.
Dropping this patch, moving the other two onto leaks-next.
thanks,
Tobin.
