Re: [PATCH v2 4/7] dt-bindings: soc: mediatek: apusys: Add new document for APU power domain
On Thu, 2021-04-15 at 10:25 -0500, Rob Herring wrote: > On Thu, Apr 15, 2021 at 01:52:37PM +0800, Flora Fu wrote: > > Document the bindings for APU power domain on MediaTek SoC. > > > > Signed-off-by: Flora Fu > > --- > > Note: > > This patch depends on MT8192 clock[1] patches which haven't yet been > > accepted. > > [1] > > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20210324104110.13383-7-chun-jie.c...@mediatek.com/__;!!CTRNKA9wMg0ARbw!zINTC3jweo4_C2yxqf9kHaxAXhO-k-I_JplIY4OQ390IeSfk5QCR4ojmFz2gPbBV$ > > > > --- > > .../soc/mediatek/mediatek,apu-pm.yaml | 145 ++ > > 1 file changed, 145 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml > > > > diff --git > > a/Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml > > b/Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml > > new file mode 100644 > > index ..6ff966920917 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml > > @@ -0,0 +1,145 @@ > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: > > https://urldefense.com/v3/__http://devicetree.org/schemas/soc/mediatek/mediatek,apu-pm.yaml*__;Iw!!CTRNKA9wMg0ARbw!zINTC3jweo4_C2yxqf9kHaxAXhO-k-I_JplIY4OQ390IeSfk5QCR4ojmF_yHpQUx$ > > > > +$schema: > > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!zINTC3jweo4_C2yxqf9kHaxAXhO-k-I_JplIY4OQ390IeSfk5QCR4ojmFy1L2FzU$ > > > > + > > +title: Mediatek APU Power Domains > > + > > +maintainers: > > + - Flora Fu > > + > > +description: | > > + Mediatek AI Process Unit (APU) include support for power domains which > > can be > > + powered up/down by software. > > + APU subsys belonging to a power domain should contain a 'power-domains' > > + property that is a phandle for apuspm node representing the domain. > > + > > +properties: > > + compatible: > > +items: > > + - enum: > > + - mediatek,mt8192-apu-pm > > + - const: syscon > > + > > + reg: > > +description: Address range of the APU power domain controller. > > +maxItems: 1 > > + > > + '#address-cells': > > +const: 1 > > + > > + '#size-cells': > > +const: 0 > > + > > + '#power-domain-cells': > > +const: 1 > > + > > + vsram-supply: > > +description: apu sram regulator supply. > > + > > + mediatek,scpsys: > > +$ref: /schemas/types.yaml#/definitions/phandle > > +description: | > > + phandle to the device containing the scpsys register range. > > + > > + mediatek,apu-conn: > > +$ref: /schemas/types.yaml#/definitions/phandle > > +description: | > > + phandle to the device containing the scpsys apu conn register range. > > + > > + mediatek,apu-conn1: > > +$ref: /schemas/types.yaml#/definitions/phandle > > +description: | > > + phandle to the device containing the scpsys apu conn1 register range. > > + > > + mediatek,apu-vcore: > > +$ref: /schemas/types.yaml#/definitions/phandle > > +description: | > > + phandle to the device containing the scpsys apu vcore register range. > > + > > +patternProperties: > > + "^power-domain@[0-9a-f]+$": > > +type: object > > +description: | > > + Represents the power domains within the power controller node as > > + documented in > > Documentation/devicetree/bindings/power/power-domain.yaml. > > + > > +properties: > > + reg: > > +description: | > > + Power domain index. Valid values are defined in: > > + "include/dt-bindings/power/mt8182-apu-power.h" > > +maxItems: 1 > > + > > + '#power-domain-cells': > > +description: | > > + Must be 0 for nodes representing a single PM domain and 1 for > > nodes > > + providing multiple PM. > > + > > + clocks: > > +description: | > > + List of phandles of clocks list. Specify by order according to > > + power-up sequence. > > + > > + clock-names: > > +description: | > > + List of names of clocks. Specify by order according to power-up > > +
Re: [PATCH 4/8] dt-bindings: arm: mediatek: Add new document bindings for APU
On Thu, 2021-04-15 at 16:24 -0500, Rob Herring wrote:
> On Mon, Apr 12, 2021 at 1:45 AM Flora Fu wrote:
> >
> > On Fri, 2021-04-09 at 13:25 -0500, Rob Herring wrote:
> > > On Wed, Apr 07, 2021 at 11:28:02AM +0800, Flora Fu wrote:
> > > > Document the apusys bindings.
> > > >
> > > > Signed-off-by: Flora Fu
> > > > ---
> > > > .../arm/mediatek/mediatek,apusys.yaml | 56 +++
> > > > 1 file changed, 56 insertions(+)
> > > > create mode 100644
> > > > Documentation/devicetree/bindings/arm/mediatek/mediatek,apusys.yaml
> > > >
> > > > diff --git
> > > > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apusys.yaml
> > > > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apusys.yaml
> > > > new file mode 100644
> > > > index ..dc04a46f1bad
> > > > --- /dev/null
> > > > +++
> > > > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apusys.yaml
> > > > @@ -0,0 +1,56 @@
> > > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > > > +%YAML 1.2
> > > > +---
> > > > +$id:
> > > > https://urldefense.com/v3/__http://devicetree.org/schemas/arm/mediatek/mediatek,apusys.yaml*__;Iw!!CTRNKA9wMg0ARbw!3ryKFTA2CvsVss4Pt2ZOG7wv4jgR-2LPxuGn30IxFmpxoxSRdzNdf8FrAYYvZWcw$
> > > > +$schema:
> > > > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!3ryKFTA2CvsVss4Pt2ZOG7wv4jgR-2LPxuGn30IxFmpxoxSRdzNdf8FrARlhCQ0w$
> > > > +
> > > > +title: MediaTek APUSYS Controller
> > > > +
> > > > +maintainers:
> > > > + - Flora Fu
> > > > +
> > > > +description:
> > > > + The Mediatek apusys controller provides functional configurations
> > > > and clocks
> > > > + to the system.
> > > > +
> > > > +properties:
> > > > + compatible:
> > > > +items:
> > > > + - enum:
> > > > + - mediatek,mt8192-apu_mbox
> > > > + - mediatek,mt8192-apu_conn
> > > > + - mediatek,mt8192-apu_vcore
> > >
> > > s/_/-/
> > >
> >
> > OK. I will update expression strings in the next version.
> >
> > > > + - const: syscon
> > > > +
> > > > + reg:
> > > > +maxItems: 1
> > > > +
> > > > + '#clock-cells':
> > > > +const: 1
> > > > +
> > > > +required:
> > > > + - compatible
> > > > + - reg
> > > > +
> > > > +additionalProperties: false
> > > > +
> > > > +examples:
> > > > + - |
> > > > +apu_mbox: apu_mbox@1900 {
> > >
> > > mailbox@...? Is this a mailbox provider?
> > >
> >
> > Yes, the apu_mbox is the for setup mailbox in the APU hardware.
>
> Then you need #mbox-cells here.
>
> And in that case, what makes it a syscon?
>
The apu_mbox are registers for setup mail box communications between apu
processor and the AP side kernel drivers. It also has spare registers
that reserved for keep specific information between apu and AP side.
That's why I set it as syscon to avoid ioremap from users. Do you think
it is reasonable or it is better to be kept inside the user nodes when
using it?
> >
> > > > +compatible = "mediatek,mt8192-apu_mbox", "syscon";
> > > > +reg = <0x1900 0x1000>;
> > > > +};
[PATCH v2 7/7] arm64: dts: mt8192: Add APU power domain node
Add APU power domain node to MT8192.
Signed-off-by: Flora Fu
---
Note:
This patch depends on MT8192 clock[1] and PMIC[2] patches which haven't yet
been accepted.
[1]
https://patchwork.kernel.org/project/linux-mediatek/patch/20210324104110.13383-7-chun-jie.c...@mediatek.com/
[2]
https://patchwork.kernel.org/project/linux-mediatek/patch/1617188527-3392-9-git-send-email-hsin-hsiung.w...@mediatek.com/
---
arch/arm64/boot/dts/mediatek/mt8192-evb.dts | 7 ++
arch/arm64/boot/dts/mediatek/mt8192.dtsi| 28 +
2 files changed, 35 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
index 1769f3a9b510..688c97c46d44 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
@@ -65,3 +65,10 @@
_vrf12_ldo_reg {
regulator-always-on;
};
+
+ {
+ vsram-supply = <_vsram_md_ldo_reg>;
+ apu_top: power-domain@0 {
+ domain-supply = <_vproc1_buck_reg>;
+ };
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 561025d2ebab..90436757386e 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1033,6 +1033,34 @@
#clock-cells = <1>;
};
+ apuspm: power-domain@190f {
+ compatible = "mediatek,mt8192-apu-pm", "syscon";
+ reg = <0 0x190f 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+ mediatek,scpsys = <>;
+ mediatek,apu-conn = <_conn>;
+ mediatek,apu-vcore = <_vcore>;
+
+ apu_top: power-domain@0 {
+ reg = <0>;
+ #power-domain-cells = <0>;
+ clocks = < CLK_TOP_DSP_SEL>,
+< CLK_TOP_IPU_IF_SEL>,
+<>,
+< CLK_TOP_UNIVPLL_D6_D2>;
+ clock-names = "clk_top_conn",
+ "clk_top_ipu_if",
+ "clk_off",
+ "clk_on_default";
+ assigned-clocks = < CLK_TOP_DSP_SEL>,
+ <
CLK_TOP_IPU_IF_SEL>;
+ assigned-clock-parents = <
CLK_TOP_UNIVPLL_D6_D2>,
+<
CLK_TOP_UNIVPLL_D6_D2>;
+ };
+ };
+
larb13: larb@1a001000 {
compatible = "mediatek,mt8192-smi-larb";
reg = <0 0x1a001000 0 0x1000>;
--
2.18.0
[PATCH v2 5/7] soc: mediatek: apu: Add apusys and add apu power domain driver
Add the apusys in soc.
Add driver for apu power domains.
Signed-off-by: Flora Fu
---
drivers/soc/mediatek/Kconfig | 10 +
drivers/soc/mediatek/Makefile| 1 +
drivers/soc/mediatek/apusys/Makefile | 2 +
drivers/soc/mediatek/apusys/mtk-apu-pm.c | 612 +++
4 files changed, 625 insertions(+)
create mode 100644 drivers/soc/mediatek/apusys/Makefile
create mode 100644 drivers/soc/mediatek/apusys/mtk-apu-pm.c
diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
index fdd8bc08569e..76ee7e354b27 100644
--- a/drivers/soc/mediatek/Kconfig
+++ b/drivers/soc/mediatek/Kconfig
@@ -5,6 +5,16 @@
menu "MediaTek SoC drivers"
depends on ARCH_MEDIATEK || COMPILE_TEST
+config MTK_APUSYS
+ bool "MediaTek APUSYS Support"
+ select REGMAP
+ select PM_GENERIC_DOMAINS if PM
+ help
+ Say yes here to add support for the MediaTek AI Processing Unit
+ Subsystem(APUSYS).
+ The APUSYS is a proprietary hardware in SoC to support AI
+ operations.
+
config MTK_CMDQ
tristate "MediaTek CMDQ Support"
depends on ARCH_MEDIATEK || COMPILE_TEST
diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
index c916b6799baa..4ca2d59b75cb 100644
--- a/drivers/soc/mediatek/Makefile
+++ b/drivers/soc/mediatek/Makefile
@@ -1,4 +1,5 @@
# SPDX-License-Identifier: GPL-2.0-only
+obj-$(CONFIG_MTK_APUSYS) += apusys/
obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o
obj-$(CONFIG_MTK_DEVAPC) += mtk-devapc.o
obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
diff --git a/drivers/soc/mediatek/apusys/Makefile
b/drivers/soc/mediatek/apusys/Makefile
new file mode 100644
index ..01c339e35b80
--- /dev/null
+++ b/drivers/soc/mediatek/apusys/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_MTK_APUSYS) += mtk-apu-pm.o
diff --git a/drivers/soc/mediatek/apusys/mtk-apu-pm.c
b/drivers/soc/mediatek/apusys/mtk-apu-pm.c
new file mode 100644
index ..c21f8b4085fd
--- /dev/null
+++ b/drivers/soc/mediatek/apusys/mtk-apu-pm.c
@@ -0,0 +1,612 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define APU_PD_IPUIF_HW_CG BIT(0)
+#define APU_PD_RPC_AUTO_BUCK BIT(1)
+#define APU_PD_CAPS(_pd, _x) ((_pd)->data->caps & (_x))
+
+#define MTK_POLL_DELAY_US 10
+#define MTK_POLL_TIMEOUTUSEC_PER_SEC
+
+/*spm_cross_wake_m01*/
+#define WAKEUP_APU (0x1 << 0)
+
+/* spm_other_pwr_status*/
+#define PWR_STATUS (0x1 << 5)
+
+/* rpc_intf_pwr_rdy */
+#define PWR0_RDY (0x1 << 0)
+
+/* rpc_top_con*/
+#define SLEEP_REQ BIT(0)
+#define APU_BUCK_ELS_ENBIT(3)
+
+/*conn_clr, conn1_clr, vcore_clr */
+#define CG_CLR (0x)
+
+/* mt8192 rpc_sw_type */
+#define MT8192_RPC_SW_TYPE0(0x200)
+#define MT8192_RPC_SW_TYPE1(0x210)
+#define MT8192_RPC_SW_TYPE2(0x220)
+#define MT8192_RPC_SW_TYPE3(0x230)
+#define MT8192_RPC_SW_TYPE4(0x240)
+#define MT8192_RPC_SW_TYPE6(0x260)
+#define MT8192_RPC_SW_TYPE7(0x270)
+
+/* rpc_sw_type*/
+static const struct reg_sequence mt8192_rpc_sw_type[] = {
+ { MT8192_RPC_SW_TYPE0, 0xFF },
+ { MT8192_RPC_SW_TYPE2, 0x7 },
+ { MT8192_RPC_SW_TYPE3, 0x7 },
+ { MT8192_RPC_SW_TYPE6, 0x3 },
+};
+
+struct apu_top_domain {
+ u32 spm_ext_buck_iso;
+ u32 spm_ext_buck_iso_mask;
+ u32 spm_cross_wake_m01;
+ u32 spm_other_pwr;
+ u32 conn_clr;
+ u32 conn1_clr;
+ u32 vcore_clr;
+ u32 rpc_top_con;
+ u32 rpc_top_con_init_mask;
+ u32 rpc_top_sel;
+ u32 rpc_top_intf_pwr_rdy;
+ const struct reg_sequence *rpc_sw_type;
+ int rpc_sw_ntype;
+};
+
+static struct apu_top_domain mt8192_top_reg = {
+ .spm_ext_buck_iso = 0x39C,
+ .spm_ext_buck_iso_mask = 0x21,
+ .spm_cross_wake_m01 = 0x670,
+ .spm_other_pwr = 0x178,
+ .conn_clr = 0x008,
+ .vcore_clr = 0x008,
+ .rpc_top_con = 0x000,
+ .rpc_top_con_init_mask = 0x49E,
+ .rpc_top_sel = 0x004,
+ .rpc_top_intf_pwr_rdy = 0x044,
+ .rpc_sw_type = mt8192_rpc_sw_type,
+ .rpc_sw_ntype = ARRAY_SIZE(mt8192_rpc_sw_type),
+};
+
+struct apusys {
+ struct device *dev;
+ struct regmap *scpsys;
+ struct regmap *conn;
+ struct regmap *conn1;
+ struct regmap *vcore;
+ struct regmap *rpc;
+ struct regulator *vsram_supply;
+ const struct apu_pm_data *data;
+ struct genpd_onecell_data pd_data;
+ struct generic_pm_domain *domains[];
+};
+
+struct apu_domain {
+ struct generic_pm_domain genpd;
+ const struct apu_domain_data *dat
[PATCH v2 6/7] arm64: dts: mt8192: Add APU node
Add APU node to MT8192.
Signed-off-by: Flora Fu
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index eb17274c3719..561025d2ebab 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1016,6 +1016,23 @@
#clock-cells = <1>;
};
+ apu_mbox: apu_mbox@1900 {
+ compatible = "mediatek,mt8192-apu-mbox", "syscon";
+ reg = <0 0x1900 0 0x1000>;
+ };
+
+ apu_conn: apu_conn@1902 {
+ compatible = "mediatek,mt8192-apu-conn", "syscon";
+ reg = <0 0x1902 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ apu_vcore: apu_vcore@19029000 {
+ compatible = "mediatek,mt8192-apu-vcore", "syscon";
+ reg = <0 0x19029000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
larb13: larb@1a001000 {
compatible = "mediatek,mt8192-smi-larb";
reg = <0 0x1a001000 0 0x1000>;
--
2.18.0
[PATCH v2 4/7] dt-bindings: soc: mediatek: apusys: Add new document for APU power domain
Document the bindings for APU power domain on MediaTek SoC.
Signed-off-by: Flora Fu
---
Note:
This patch depends on MT8192 clock[1] patches which haven't yet been accepted.
[1]
https://patchwork.kernel.org/project/linux-mediatek/patch/20210324104110.13383-7-chun-jie.c...@mediatek.com/
---
.../soc/mediatek/mediatek,apu-pm.yaml | 145 ++
1 file changed, 145 insertions(+)
create mode 100644
Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml
diff --git
a/Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml
b/Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml
new file mode 100644
index ..6ff966920917
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml
@@ -0,0 +1,145 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/mediatek/mediatek,apu-pm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek APU Power Domains
+
+maintainers:
+ - Flora Fu
+
+description: |
+ Mediatek AI Process Unit (APU) include support for power domains which can be
+ powered up/down by software.
+ APU subsys belonging to a power domain should contain a 'power-domains'
+ property that is a phandle for apuspm node representing the domain.
+
+properties:
+ compatible:
+items:
+ - enum:
+ - mediatek,mt8192-apu-pm
+ - const: syscon
+
+ reg:
+description: Address range of the APU power domain controller.
+maxItems: 1
+
+ '#address-cells':
+const: 1
+
+ '#size-cells':
+const: 0
+
+ '#power-domain-cells':
+const: 1
+
+ vsram-supply:
+description: apu sram regulator supply.
+
+ mediatek,scpsys:
+$ref: /schemas/types.yaml#/definitions/phandle
+description: |
+ phandle to the device containing the scpsys register range.
+
+ mediatek,apu-conn:
+$ref: /schemas/types.yaml#/definitions/phandle
+description: |
+ phandle to the device containing the scpsys apu conn register range.
+
+ mediatek,apu-conn1:
+$ref: /schemas/types.yaml#/definitions/phandle
+description: |
+ phandle to the device containing the scpsys apu conn1 register range.
+
+ mediatek,apu-vcore:
+$ref: /schemas/types.yaml#/definitions/phandle
+description: |
+ phandle to the device containing the scpsys apu vcore register range.
+
+patternProperties:
+ "^power-domain@[0-9a-f]+$":
+type: object
+description: |
+ Represents the power domains within the power controller node as
+ documented in Documentation/devicetree/bindings/power/power-domain.yaml.
+
+properties:
+ reg:
+description: |
+ Power domain index. Valid values are defined in:
+ "include/dt-bindings/power/mt8182-apu-power.h"
+maxItems: 1
+
+ '#power-domain-cells':
+description: |
+ Must be 0 for nodes representing a single PM domain and 1 for nodes
+ providing multiple PM.
+
+ clocks:
+description: |
+ List of phandles of clocks list. Specify by order according to
+ power-up sequence.
+
+ clock-names:
+description: |
+ List of names of clocks. Specify by order according to power-up
+ sequence.
+
+ assigned-clocks:
+maxItems: 2
+
+ assigned-clock-parents:
+maxItems: 2
+
+ domain-supply:
+description: domain regulator supply.
+
+required:
+ - reg
+ - '#power-domain-cells'
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - '#power-domain-cells'
+ - vsram-supply
+ - mediatek,scpsys
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+apuspm: power-domain@190f {
+compatible = "mediatek,mt8192-apu-pm", "syscon";
+reg = <0x190f 0x1000>;
+#address-cells = <1>;
+#size-cells = <0>;
+#power-domain-cells = <1>;
+vsram-supply = <_vsram_md_ldo_reg>;
+mediatek,scpsys = <>;
+mediatek,apu-conn = <_conn>;
+mediatek,apu-vcore = <_vcore>;
+
+apu_top: power-domain@0 {
+reg = <0>;
+#power-domain-cells = <0>;
+clocks = < CLK_TOP_DSP_SEL>,
+ < CLK_TOP_IPU_IF_SEL>,
+ <>,
+ < CLK_TOP_UNIVPLL_D6_D2>;
+clock-names = "clk_top_conn",
+ "clk_top_ipu_if",
+ "clk_off",
+ "clk_on_default";
+assigned-clocks = < CLK_TOP_DSP_SEL>,
+ < CLK_TOP_IPU_IF_SEL>;
+assigned-clock-parents = < CLK_TOP_UNIVPLL_D6_D2>,
+ < CLK_TOP_UNIVPLL_D6_D2>;
+domain-supply = <_vproc1_buck_reg>;
+};
+};
--
2.18.0
[PATCH v2 3/7] dt-bindings: arm: mediatek: Add new document bindings for APU
Document the apusys bindings.
Signed-off-by: Flora Fu
---
.../arm/mediatek/mediatek,apusys.yaml | 56 +++
1 file changed, 56 insertions(+)
create mode 100644
Documentation/devicetree/bindings/arm/mediatek/mediatek,apusys.yaml
diff --git
a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apusys.yaml
b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apusys.yaml
new file mode 100644
index ..d46290548b34
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apusys.yaml
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,apusys.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek APUSYS Controller
+
+maintainers:
+ - Flora Fu
+
+description:
+ The Mediatek apusys controller provides functional configurations and clocks
+ to the system.
+
+properties:
+ compatible:
+items:
+ - enum:
+ - mediatek,mt8192-apu-mbox
+ - mediatek,mt8192-apu-conn
+ - mediatek,mt8192-apu-vcore
+ - const: syscon
+
+ reg:
+maxItems: 1
+
+ '#clock-cells':
+const: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+apu_mbox: apu_mbox@1900 {
+compatible = "mediatek,mt8192-apu-mbox", "syscon";
+reg = <0x1900 0x1000>;
+};
+
+ - |
+apu_conn: apu_conn@1902 {
+compatible = "mediatek,mt8192-apu-conn", "syscon";
+reg = <0x1902 0x1000>;
+#clock-cells = <1>;
+};
+
+ - |
+apu_vcore: apu_vcore@19029000 {
+compatible = "mediatek,mt8192-apu-vcore", "syscon";
+reg = <0x19029000 0x1000>;
+#clock-cells = <1>;
+};
--
2.18.0
[PATCH v2 2/7] clk: mediatek: mt8192: Add APU clocks support
Add APU clocks support on MT8192.
Signed-off-by: Flora Fu
---
drivers/clk/mediatek/clk-mt8192.c | 91 +++
1 file changed, 91 insertions(+)
diff --git a/drivers/clk/mediatek/clk-mt8192.c
b/drivers/clk/mediatek/clk-mt8192.c
index bf6a2084a348..4eb61f006306 100644
--- a/drivers/clk/mediatek/clk-mt8192.c
+++ b/drivers/clk/mediatek/clk-mt8192.c
@@ -244,6 +244,65 @@ static const char * const ccu_parents[] = {
"univpll_d6_d2"
};
+static const char * const dsp_parents[] = {
+ "clk26m",
+ "univpll_d6_d2",
+ "univpll_d4_d2",
+ "univpll_d5",
+ "univpll_d4",
+ "mmpll_d4",
+ "mainpll_d3",
+ "univpll_d3"
+};
+
+static const char * const dsp1_parents[] = {
+ "clk26m",
+ "npupll_ck",
+ "mainpll_d4_d2",
+ "univpll_d5",
+ "univpll_d4",
+ "mainpll_d3",
+ "univpll_d3",
+ "apupll_ck"
+};
+
+static const char * const dsp1_npupll_parents[] = {
+ "dsp1_sel",
+ "npupll_ck"
+};
+
+static const char * const dsp2_parents[] = {
+ "clk26m",
+ "npupll_ck",
+ "mainpll_d4_d2",
+ "univpll_d5",
+ "univpll_d4",
+ "mainpll_d3",
+ "univpll_d3",
+ "apupll_ck"
+};
+
+static const char * const dsp2_npupll_parents[] = {
+ "dsp2_sel",
+ "npupll_ck"
+};
+
+static const char * const dsp5_parents[] = {
+ "clk26m",
+ "apupll_ck",
+ "univpll_d4_d2",
+ "mainpll_d4",
+ "univpll_d4",
+ "mmpll_d4",
+ "mainpll_d3",
+ "univpll_d3"
+};
+
+static const char * const dsp5_apupll_parents[] = {
+ "dsp5_sel",
+ "apupll_ck"
+};
+
static const char * const dsp7_parents[] = {
"clk26m",
"mainpll_d4_d2",
@@ -255,6 +314,17 @@ static const char * const dsp7_parents[] = {
"mmpll_d4"
};
+static const char * const ipu_if_parents[] = {
+ "clk26m",
+ "univpll_d6_d2",
+ "mainpll_d4_d2",
+ "univpll_d4_d2",
+ "univpll_d5",
+ "mainpll_d4",
+ "tvdpll_ck",
+ "univpll_d4"
+};
+
static const char * const mfg_ref_parents[] = {
"clk26m",
"clk26m",
@@ -734,9 +804,26 @@ static const struct mtk_mux top_mtk_muxes[] = {
cam_parents, 0x030, 0x034, 0x038, 16, 4, 23, 0x004, 10),
MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU_SEL, "ccu_sel",
ccu_parents, 0x030, 0x034, 0x038, 24, 4, 31, 0x004, 11),
+ /* CLK_CFG_3 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP_SEL, "dsp_sel",
+ dsp_parents, 0x040, 0x044, 0x048, 0, 3, 7, 0x004, 12),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP1_SEL, "dsp1_sel",
+ dsp1_parents, 0x040, 0x044, 0x048, 8, 3, 15, 0x004, 13),
+ MUX_CLR_SET_UPD(CLK_TOP_DSP1_NPUPLL_SEL, "dsp1_npupll_sel",
+ dsp1_npupll_parents, 0x040, 0x044, 0x048, 11, 1, -1, -1),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP2_SEL, "dsp2_sel",
+ dsp2_parents, 0x040, 0x044, 0x048, 16, 3, 23, 0x004, 14),
+ MUX_CLR_SET_UPD(CLK_TOP_DSP2_NPUPLL_SEL, "dsp2_npupll_sel",
+ dsp2_npupll_parents, 0x040, 0x044, 0x048, 19, 1, -1, -1),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP5_SEL, "dsp5_sel",
+ dsp5_parents, 0x040, 0x044, 0x048, 24, 3, 31, 0x004, 15),
+ MUX_CLR_SET_UPD(CLK_TOP_DSP5_APUPLL_SEL, "dsp5_apupll_sel",
+ dsp5_apupll_parents, 0x040, 0x044, 0x048, 27, 1, -1, -1),
/* CLK_CFG_4 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP7_SEL, "dsp7_sel",
dsp7_parents, 0x050, 0x054, 0x058, 0, 3, 7, 0x004, 16),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_IPU_IF_SEL, "ipu_if_sel",
+ ipu_if_parents, 0x050, 0x054, 0x058, 8, 3, 15, 0x004, 17),
MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_REF_SEL, "mfg_ref_sel",
mfg_ref_parents, 0x050, 0x054, 0x058, 16, 2, 23, 0x004, 18),
MUX_CLR_SET_UPD(CLK_TOP_MFG_PLL_SEL, "mfg_pll_sel",
@@ -1175,6 +1262,10 @@ static const struct mtk_pll_data plls[] = {
0, 0, 32, 0x031c, 24, 0x0040, 0x000c, 0, 0x0320, 0),
PLL_B(CLK_APMIXED_APLL2, "apll2", 0x032c, 0x033c, 0x,
0, 0, 32, 0x0330, 24, 0, 0, 0, 0x0334, 0),
+ PLL_B(CLK_APMIXED_APUPLL, "apupll", 0x03a0, 0x03ac, 0xff01,
+ HAVE_RST_BAR, BIT(23), 22, 0x03a4, 24, 0, 0, 0, 0x03a4, 0),
+ PLL_B(CLK_APMIXED_NPUPLL, "npupll", 0x03b4, 0x03c0, 0x0001,
+ 0, 0, 22, 0x03b8, 24, 0, 0, 0, 0x03b8, 0),
};
static struct clk_onecell_data *top_clk_data;
--
2.18.0
[PATCH v2 1/7] dt-bindings: clock: Add MT8192 APU clock bindings
Add clock bindings for APU on MT8192. Signed-off-by: Flora Fu Acked-by: Rob Herring --- include/dt-bindings/clock/mt8192-clk.h | 14 -- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/include/dt-bindings/clock/mt8192-clk.h b/include/dt-bindings/clock/mt8192-clk.h index ece5b4c0356c..71e07858f5dc 100644 --- a/include/dt-bindings/clock/mt8192-clk.h +++ b/include/dt-bindings/clock/mt8192-clk.h @@ -164,7 +164,15 @@ #define CLK_TOP_APLL12_DIV9152 #define CLK_TOP_SSUSB_TOP_REF 153 #define CLK_TOP_SSUSB_PHY_REF 154 -#define CLK_TOP_NR_CLK 155 +#define CLK_TOP_DSP_SEL155 +#define CLK_TOP_DSP1_SEL 156 +#define CLK_TOP_DSP1_NPUPLL_SEL157 +#define CLK_TOP_DSP2_SEL 158 +#define CLK_TOP_DSP2_NPUPLL_SEL159 +#define CLK_TOP_DSP5_SEL 160 +#define CLK_TOP_DSP5_APUPLL_SEL161 +#define CLK_TOP_IPU_IF_SEL 162 +#define CLK_TOP_NR_CLK 163 /* INFRACFG */ @@ -309,7 +317,9 @@ #define CLK_APMIXED_APLL1 8 #define CLK_APMIXED_APLL2 9 #define CLK_APMIXED_MIPID26M 10 -#define CLK_APMIXED_NR_CLK 11 +#define CLK_APMIXED_APUPLL 11 +#define CLK_APMIXED_NPUPLL 12 +#define CLK_APMIXED_NR_CLK 13 /* SCP_ADSP */ -- 2.18.0
[PATCH v2 0/7] Add Support for MediaTek MT8192 APU Power
The MediaTek AI Processing Unit (APU) is a proprietary hardware in the SoC to support AI operations. The series is to create apusys in the SoC folder for developing the related drivers. Add the apu clocks, basic apu nodes and the power domain to provide the power controller of APU subsystem. This series is based on MT8192 clock[1] and PMIC[2] patches. [1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=454523 [2] https://patchwork.kernel.org/project/linux-mediatek/list/?series=458733 Change notes: v1->v2: 1) update expression "s/_/-/" in dt-bindings documents. 2) drop apu power domain header file for mt8192. v1: https://patchwork.kernel.org/project/linux-mediatek/list/?series=461999 Flora Fu (7): dt-bindings: clock: Add MT8192 APU clock bindings clk: mediatek: mt8192: Add APU clocks support dt-bindings: arm: mediatek: Add new document bindings for APU dt-bindings: soc: mediatek: apusys: Add new document for APU power domain soc: mediatek: apu: Add apusys and add apu power domain driver arm64: dts: mt8192: Add APU node arm64: dts: mt8192: Add APU power domain node .../arm/mediatek/mediatek,apusys.yaml | 56 ++ .../soc/mediatek/mediatek,apu-pm.yaml | 145 + arch/arm64/boot/dts/mediatek/mt8192-evb.dts | 7 + arch/arm64/boot/dts/mediatek/mt8192.dtsi | 45 ++ drivers/clk/mediatek/clk-mt8192.c | 91 +++ drivers/soc/mediatek/Kconfig | 10 + drivers/soc/mediatek/Makefile | 1 + drivers/soc/mediatek/apusys/Makefile | 2 + drivers/soc/mediatek/apusys/mtk-apu-pm.c | 612 ++ include/dt-bindings/clock/mt8192-clk.h| 14 +- 10 files changed, 981 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,apusys.yaml create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml create mode 100644 drivers/soc/mediatek/apusys/Makefile create mode 100644 drivers/soc/mediatek/apusys/mtk-apu-pm.c -- 2.18.0
[PATCH v2 0/7] Add Support for MediaTek MT8192 APU Power
The MediaTek AI Processing Unit (APU) is a proprietary hardware in the SoC to support AI operations. The series is to create apusys in the SoC folder for developing the related drivers. Add the apu clocks, basic apu nodes and the power domain to provide the power controller of APU subsystem. This series is based on MT8192 clock[1] and PMIC[2] patches. [1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=454523 [2] https://patchwork.kernel.org/project/linux-mediatek/list/?series=458733 Change notes: v1->v2: 1) update expression "s/_/-/" in dt-bindings documents. 2) drop apu power domain header file for mt8192. v1: https://patchwork.kernel.org/project/linux-mediatek/list/?series=461999 Flora Fu (7): dt-bindings: clock: Add MT8192 APU clock bindings clk: mediatek: mt8192: Add APU clocks support dt-bindings: arm: mediatek: Add new document bindings for APU dt-bindings: soc: mediatek: apusys: Add new document for APU power domain soc: mediatek: apu: Add apusys and add apu power domain driver arm64: dts: mt8192: Add APU node arm64: dts: mt8192: Add APU power domain node .../arm/mediatek/mediatek,apusys.yaml | 56 ++ .../soc/mediatek/mediatek,apu-pm.yaml | 145 + arch/arm64/boot/dts/mediatek/mt8192-evb.dts | 7 + arch/arm64/boot/dts/mediatek/mt8192.dtsi | 45 ++ drivers/clk/mediatek/clk-mt8192.c | 91 +++ drivers/soc/mediatek/Kconfig | 10 + drivers/soc/mediatek/Makefile | 1 + drivers/soc/mediatek/apusys/Makefile | 2 + drivers/soc/mediatek/apusys/mtk-apu-pm.c | 612 ++ include/dt-bindings/clock/mt8192-clk.h| 14 +- 10 files changed, 981 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,apusys.yaml create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml create mode 100644 drivers/soc/mediatek/apusys/Makefile create mode 100644 drivers/soc/mediatek/apusys/mtk-apu-pm.c -- 2.18.0
Re: [PATCH 3/8] dt-bindings: apu: Add MT8192 APU power domain
Hi, Rob, In mt8192 hardware, we only control top power domain in kernel. It is unnecessary to create a specific header just for such purpose. I will update the patch in the next version. Thanks for your review. Thanks, Flora On Fri, 2021-04-09 at 13:23 -0500, Rob Herring wrote: > On Wed, Apr 07, 2021 at 11:28:01AM +0800, Flora Fu wrote: > > Create MT8192 APU power domain bindings. > > Add top power domain id. > > > > Signed-off-by: Flora Fu > > --- > > include/dt-bindings/power/mt8192-apu-power.h | 11 +++ > > 1 file changed, 11 insertions(+) > > create mode 100644 include/dt-bindings/power/mt8192-apu-power.h > > > > diff --git a/include/dt-bindings/power/mt8192-apu-power.h > > b/include/dt-bindings/power/mt8192-apu-power.h > > new file mode 100644 > > index ..b821bd4811a6 > > --- /dev/null > > +++ b/include/dt-bindings/power/mt8192-apu-power.h > > @@ -0,0 +1,11 @@ > > +/* SPDX-License-Identifier: GPL-2.0 > > + * > > + * Copyright (c) 2021 MediaTek Inc. > > + */ > > + > > +#ifndef _DT_BINDINGS_POWER_MT8192_APU_POWER_H > > +#define _DT_BINDINGS_POWER_MT8192_APU_POWER_H > > + > > +#define MT8192_POWER_DOMAIN_APUSYS_TOP 0 > > Really, you don't know what the other power domains are? Please make > this as complete as possible. These headers create a merge mess. > > Rob
Re: [PATCH 4/8] dt-bindings: arm: mediatek: Add new document bindings for APU
On Fri, 2021-04-09 at 13:25 -0500, Rob Herring wrote:
> On Wed, Apr 07, 2021 at 11:28:02AM +0800, Flora Fu wrote:
> > Document the apusys bindings.
> >
> > Signed-off-by: Flora Fu
> > ---
> > .../arm/mediatek/mediatek,apusys.yaml | 56 +++
> > 1 file changed, 56 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/arm/mediatek/mediatek,apusys.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apusys.yaml
> > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apusys.yaml
> > new file mode 100644
> > index ..dc04a46f1bad
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apusys.yaml
> > @@ -0,0 +1,56 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id:
> > https://urldefense.com/v3/__http://devicetree.org/schemas/arm/mediatek/mediatek,apusys.yaml*__;Iw!!CTRNKA9wMg0ARbw!3ryKFTA2CvsVss4Pt2ZOG7wv4jgR-2LPxuGn30IxFmpxoxSRdzNdf8FrAYYvZWcw$
> >
> > +$schema:
> > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!3ryKFTA2CvsVss4Pt2ZOG7wv4jgR-2LPxuGn30IxFmpxoxSRdzNdf8FrARlhCQ0w$
> >
> > +
> > +title: MediaTek APUSYS Controller
> > +
> > +maintainers:
> > + - Flora Fu
> > +
> > +description:
> > + The Mediatek apusys controller provides functional configurations and
> > clocks
> > + to the system.
> > +
> > +properties:
> > + compatible:
> > +items:
> > + - enum:
> > + - mediatek,mt8192-apu_mbox
> > + - mediatek,mt8192-apu_conn
> > + - mediatek,mt8192-apu_vcore
>
> s/_/-/
>
OK. I will update expression strings in the next version.
> > + - const: syscon
> > +
> > + reg:
> > +maxItems: 1
> > +
> > + '#clock-cells':
> > +const: 1
> > +
> > +required:
> > + - compatible
> > + - reg
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > +apu_mbox: apu_mbox@1900 {
>
> mailbox@...? Is this a mailbox provider?
>
Yes, the apu_mbox is the for setup mailbox in the APU hardware.
> > +compatible = "mediatek,mt8192-apu_mbox", "syscon";
> > +reg = <0x1900 0x1000>;
> > +};
> > +
> > + - |
> > +apu_conn: apu_conn@1902 {
> > +compatible = "mediatek,mt8192-apu_conn", "syscon";
> > +reg = <0x1902 0x1000>;
> > +#clock-cells = <1>;
> > +};
> > +
> > + - |
> > +apu_vcore: apu_vcore@19029000 {
> > +compatible = "mediatek,mt8192-apu_vcore", "syscon";
> > +reg = <0x19029000 0x1000>;
> > +#clock-cells = <1>;
> > +};
> > --
> > 2.18.0
> >
Re: [PATCH 5/8] dt-bindings: soc: mediatek: apusys: Add new document for APU power domain
Hi, Rob, The error is resulted from some un-merged patch. Please note that the patch depends MT8192 clock patches which haven't yet been accepted. https://patchwork.kernel.org/project/linux-mediatek/patch/20210324104110.13383-7-chun-jie.c...@mediatek.com/ Thanks for your review. On Wed, 2021-04-07 at 09:28 -0500, Rob Herring wrote: > On Wed, 07 Apr 2021 11:28:03 +0800, Flora Fu wrote: > > Document the bindings for APU power domain on MediaTek SoC. > > > > Signed-off-by: Flora Fu > > --- > > .../soc/mediatek/mediatek,apu-pm.yaml | 146 ++ > > 1 file changed, 146 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml > > > > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' > on your patch (DT_CHECKER_FLAGS is new in v5.13): > > yamllint warnings/errors: > > dtschema/dtc warnings/errors: > Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.example.dts:19:18: > fatal error: dt-bindings/clock/mt8192-clk.h: No such file or directory >19 | #include > | ^~~~ > compilation terminated. > make[1]: *** [scripts/Makefile.lib:377: > Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.example.dt.yaml] > Error 1 > make[1]: *** Waiting for unfinished jobs > make: *** [Makefile:1414: dt_binding_check] Error 2 > > See > https://urldefense.com/v3/__https://patchwork.ozlabs.org/patch/1463115__;!!CTRNKA9wMg0ARbw!0XUn1LcNHfvUShNClpM_yH73TAR9qdm29SZMckasoCQ8UzeKS-vZW0QUu3Ssn-s6$ > > > This check can fail if there are any dependencies. The base for a patch > series is generally the most recent rc1. > > If you already ran 'make dt_binding_check' and didn't see the above > error(s), then make sure 'yamllint' is installed and dt-schema is up to > date: > > pip3 install dtschema --upgrade > > Please check and re-submit. >
[PATCH 8/8] arm64: dts: mt8192: Add APU power domain node
Add APU power domain node to MT8192.
Signed-off-by: Flora Fu
---
arch/arm64/boot/dts/mediatek/mt8192-evb.dts | 7 +
arch/arm64/boot/dts/mediatek/mt8192.dtsi| 29 +
2 files changed, 36 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
index 1769f3a9b510..9e89efb3dc8a 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
@@ -65,3 +65,10 @@
_vrf12_ldo_reg {
regulator-always-on;
};
+
+ {
+ vsram-supply = <_vsram_md_ldo_reg>;
+ power-domain@MT8192_POWER_DOMAIN_APUSYS_TOP {
+ domain-supply = <_vproc1_buck_reg>;
+ };
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index b1467ccbe5aa..546c058ef560 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
/ {
compatible = "mediatek,mt8192";
@@ -1033,6 +1034,34 @@
#clock-cells = <1>;
};
+ apuspm: power-domain@190f {
+ compatible = "mediatek,mt8192-apu-pm", "syscon";
+ reg = <0 0x190f 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+ mediatek,scpsys = <>;
+ mediatek,apu_conn = <_conn>;
+ mediatek,apu_vcore = <_vcore>;
+
+ power-domain@MT8192_POWER_DOMAIN_APUSYS_TOP {
+ reg = ;
+ #power-domain-cells = <0>;
+ clocks = < CLK_TOP_DSP_SEL>,
+< CLK_TOP_IPU_IF_SEL>,
+<>,
+< CLK_TOP_UNIVPLL_D6_D2>;
+ clock-names = "clk_top_conn",
+ "clk_top_ipu_if",
+ "clk_off",
+ "clk_on_default";
+ assigned-clocks = < CLK_TOP_DSP_SEL>,
+ <
CLK_TOP_IPU_IF_SEL>;
+ assigned-clock-parents = <
CLK_TOP_UNIVPLL_D6_D2>,
+<
CLK_TOP_UNIVPLL_D6_D2>;
+ };
+ };
+
larb13: larb@1a001000 {
compatible = "mediatek,mt8192-smi-larb";
reg = <0 0x1a001000 0 0x1000>;
--
2.18.0
[PATCH 4/8] dt-bindings: arm: mediatek: Add new document bindings for APU
Document the apusys bindings.
Signed-off-by: Flora Fu
---
.../arm/mediatek/mediatek,apusys.yaml | 56 +++
1 file changed, 56 insertions(+)
create mode 100644
Documentation/devicetree/bindings/arm/mediatek/mediatek,apusys.yaml
diff --git
a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apusys.yaml
b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apusys.yaml
new file mode 100644
index ..dc04a46f1bad
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apusys.yaml
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,apusys.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek APUSYS Controller
+
+maintainers:
+ - Flora Fu
+
+description:
+ The Mediatek apusys controller provides functional configurations and clocks
+ to the system.
+
+properties:
+ compatible:
+items:
+ - enum:
+ - mediatek,mt8192-apu_mbox
+ - mediatek,mt8192-apu_conn
+ - mediatek,mt8192-apu_vcore
+ - const: syscon
+
+ reg:
+maxItems: 1
+
+ '#clock-cells':
+const: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+apu_mbox: apu_mbox@1900 {
+compatible = "mediatek,mt8192-apu_mbox", "syscon";
+reg = <0x1900 0x1000>;
+};
+
+ - |
+apu_conn: apu_conn@1902 {
+compatible = "mediatek,mt8192-apu_conn", "syscon";
+reg = <0x1902 0x1000>;
+#clock-cells = <1>;
+};
+
+ - |
+apu_vcore: apu_vcore@19029000 {
+compatible = "mediatek,mt8192-apu_vcore", "syscon";
+reg = <0x19029000 0x1000>;
+#clock-cells = <1>;
+};
--
2.18.0
[PATCH 6/8] soc: mediatek: apu: Add apusys and add apu power domain driver
Add the apusys in soc.
Add driver for apu power domains.
Signed-off-by: Flora Fu
---
drivers/soc/mediatek/Kconfig | 10 +
drivers/soc/mediatek/Makefile| 1 +
drivers/soc/mediatek/apusys/Makefile | 2 +
drivers/soc/mediatek/apusys/mtk-apu-pm.c | 613 +++
4 files changed, 626 insertions(+)
create mode 100644 drivers/soc/mediatek/apusys/Makefile
create mode 100644 drivers/soc/mediatek/apusys/mtk-apu-pm.c
diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
index fdd8bc08569e..76ee7e354b27 100644
--- a/drivers/soc/mediatek/Kconfig
+++ b/drivers/soc/mediatek/Kconfig
@@ -5,6 +5,16 @@
menu "MediaTek SoC drivers"
depends on ARCH_MEDIATEK || COMPILE_TEST
+config MTK_APUSYS
+ bool "MediaTek APUSYS Support"
+ select REGMAP
+ select PM_GENERIC_DOMAINS if PM
+ help
+ Say yes here to add support for the MediaTek AI Processing Unit
+ Subsystem(APUSYS).
+ The APUSYS is a proprietary hardware in SoC to support AI
+ operations.
+
config MTK_CMDQ
tristate "MediaTek CMDQ Support"
depends on ARCH_MEDIATEK || COMPILE_TEST
diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
index c916b6799baa..4ca2d59b75cb 100644
--- a/drivers/soc/mediatek/Makefile
+++ b/drivers/soc/mediatek/Makefile
@@ -1,4 +1,5 @@
# SPDX-License-Identifier: GPL-2.0-only
+obj-$(CONFIG_MTK_APUSYS) += apusys/
obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o
obj-$(CONFIG_MTK_DEVAPC) += mtk-devapc.o
obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
diff --git a/drivers/soc/mediatek/apusys/Makefile
b/drivers/soc/mediatek/apusys/Makefile
new file mode 100644
index ..01c339e35b80
--- /dev/null
+++ b/drivers/soc/mediatek/apusys/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_MTK_APUSYS) += mtk-apu-pm.o
diff --git a/drivers/soc/mediatek/apusys/mtk-apu-pm.c
b/drivers/soc/mediatek/apusys/mtk-apu-pm.c
new file mode 100644
index ..37f481692cbb
--- /dev/null
+++ b/drivers/soc/mediatek/apusys/mtk-apu-pm.c
@@ -0,0 +1,613 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define APU_PD_IPUIF_HW_CG BIT(0)
+#define APU_PD_RPC_AUTO_BUCK BIT(1)
+#define APU_PD_CAPS(_pd, _x) ((_pd)->data->caps & (_x))
+
+#define MTK_POLL_DELAY_US 10
+#define MTK_POLL_TIMEOUTUSEC_PER_SEC
+
+/*spm_cross_wake_m01*/
+#define WAKEUP_APU (0x1 << 0)
+
+/* spm_other_pwr_status*/
+#define PWR_STATUS (0x1 << 5)
+
+/* rpc_intf_pwr_rdy */
+#define PWR0_RDY (0x1 << 0)
+
+/* rpc_top_con*/
+#define SLEEP_REQ BIT(0)
+#define APU_BUCK_ELS_ENBIT(3)
+
+/*conn_clr, conn1_clr, vcore_clr */
+#define CG_CLR (0x)
+
+/* mt8192 rpc_sw_type */
+#define MT8192_RPC_SW_TYPE0(0x200)
+#define MT8192_RPC_SW_TYPE1(0x210)
+#define MT8192_RPC_SW_TYPE2(0x220)
+#define MT8192_RPC_SW_TYPE3(0x230)
+#define MT8192_RPC_SW_TYPE4(0x240)
+#define MT8192_RPC_SW_TYPE6(0x260)
+#define MT8192_RPC_SW_TYPE7(0x270)
+
+/* rpc_sw_type*/
+static const struct reg_sequence mt8192_rpc_sw_type[] = {
+ { MT8192_RPC_SW_TYPE0, 0xFF },
+ { MT8192_RPC_SW_TYPE2, 0x7 },
+ { MT8192_RPC_SW_TYPE3, 0x7 },
+ { MT8192_RPC_SW_TYPE6, 0x3 },
+};
+
+struct apu_top_domain {
+ u32 spm_ext_buck_iso;
+ u32 spm_ext_buck_iso_mask;
+ u32 spm_cross_wake_m01;
+ u32 spm_other_pwr;
+ u32 conn_clr;
+ u32 conn1_clr;
+ u32 vcore_clr;
+ u32 rpc_top_con;
+ u32 rpc_top_con_init_mask;
+ u32 rpc_top_sel;
+ u32 rpc_top_intf_pwr_rdy;
+ const struct reg_sequence *rpc_sw_type;
+ int rpc_sw_ntype;
+};
+
+static struct apu_top_domain mt8192_top_reg = {
+ .spm_ext_buck_iso = 0x39C,
+ .spm_ext_buck_iso_mask = 0x21,
+ .spm_cross_wake_m01 = 0x670,
+ .spm_other_pwr = 0x178,
+ .conn_clr = 0x008,
+ .vcore_clr = 0x008,
+ .rpc_top_con = 0x000,
+ .rpc_top_con_init_mask = 0x49E,
+ .rpc_top_sel = 0x004,
+ .rpc_top_intf_pwr_rdy = 0x044,
+ .rpc_sw_type = mt8192_rpc_sw_type,
+ .rpc_sw_ntype = ARRAY_SIZE(mt8192_rpc_sw_type),
+};
+
+struct apusys {
+ struct device *dev;
+ struct regmap *scpsys;
+ struct regmap *conn;
+ struct regmap *conn1;
+ struct regmap *vcore;
+ struct regmap *rpc;
+ struct regulator *vsram_supply;
+ const struct apu_pm_data *data;
+ struct genpd_onecell_data pd_data;
+ struct generic_pm_domain *domains[];
+};
+
+struct apu_domain {
+ struct generic_pm_domain genpd;
+ const struct apu_domain
[PATCH 7/8] arm64: dts: mt8192: Add APU node
Add APU node to MT8192.
Signed-off-by: Flora Fu
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index eb17274c3719..b1467ccbe5aa 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1016,6 +1016,23 @@
#clock-cells = <1>;
};
+ apu_mbox: apu_mbox@1900 {
+ compatible = "mediatek,mt8192-apu_mbox", "syscon";
+ reg = <0 0x1900 0 0x1000>;
+ };
+
+ apu_conn: apu_conn@1902 {
+ compatible = "mediatek,mt8192-apu_conn", "syscon";
+ reg = <0 0x1902 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ apu_vcore: apu_vcore@19029000 {
+ compatible = "mediatek,mt8192-apu_vcore", "syscon";
+ reg = <0 0x19029000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
larb13: larb@1a001000 {
compatible = "mediatek,mt8192-smi-larb";
reg = <0 0x1a001000 0 0x1000>;
--
2.18.0
[PATCH 5/8] dt-bindings: soc: mediatek: apusys: Add new document for APU power domain
Document the bindings for APU power domain on MediaTek SoC.
Signed-off-by: Flora Fu
---
.../soc/mediatek/mediatek,apu-pm.yaml | 146 ++
1 file changed, 146 insertions(+)
create mode 100644
Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml
diff --git
a/Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml
b/Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml
new file mode 100644
index ..c99e812977f9
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml
@@ -0,0 +1,146 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/mediatek/mediatek,apu-pm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek APU Power Domains
+
+maintainers:
+ - Flora Fu
+
+description: |
+ Mediatek AI Process Unit (APU) include support for power domains which can be
+ powered up/down by software.
+ APU subsys belonging to a power domain should contain a 'power-domains'
+ property that is a phandle for apuspm node representing the domain.
+
+properties:
+ compatible:
+items:
+ - enum:
+ - mediatek,mt8192-apu-pm
+ - const: syscon
+
+ reg:
+description: Address range of the APU power domain controller.
+maxItems: 1
+
+ '#address-cells':
+const: 1
+
+ '#size-cells':
+const: 0
+
+ '#power-domain-cells':
+const: 1
+
+ vsram-supply:
+description: apu sram regulator supply.
+
+ mediatek,scpsys:
+$ref: /schemas/types.yaml#/definitions/phandle
+description: |
+ phandle to the device containing the scpsys register range.
+
+ mediatek,apu_conn:
+$ref: /schemas/types.yaml#/definitions/phandle
+description: |
+ phandle to the device containing the scpsys apu conn register range.
+
+ mediatek,apu_conn1:
+$ref: /schemas/types.yaml#/definitions/phandle
+description: |
+ phandle to the device containing the scpsys apu conn1 register range.
+
+ mediatek,apu_vcore:
+$ref: /schemas/types.yaml#/definitions/phandle
+description: |
+ phandle to the device containing the scpsys apu vcore register range.
+
+patternProperties:
+ "^power-domain@[0-9a-f]+$":
+type: object
+description: |
+ Represents the power domains within the power controller node as
+ documented in Documentation/devicetree/bindings/power/power-domain.yaml.
+
+properties:
+ reg:
+description: |
+ Power domain index. Valid values are defined in:
+ "include/dt-bindings/power/mt8182-apu-power.h"
+maxItems: 1
+
+ '#power-domain-cells':
+description: |
+ Must be 0 for nodes representing a single PM domain and 1 for nodes
+ providing multiple PM.
+
+ clocks:
+description: |
+ List of phandles of clocks list. Specify by order according to
+ power-up sequence.
+
+ clock-names:
+description: |
+ List of names of clocks. Specify by order according to power-up
+ sequence.
+
+ assigned-clocks:
+maxItems: 2
+
+ assigned-clock-parents:
+maxItems: 2
+
+ domain-supply:
+description: domain regulator supply.
+
+required:
+ - reg
+ - '#power-domain-cells'
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - '#power-domain-cells'
+ - vsram-supply
+ - mediatek,scpsys
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+apuspm: power-domain@190f {
+compatible = "mediatek,mt8192-apu-pm", "syscon";
+reg = <0x190f 0x1000>;
+#address-cells = <1>;
+#size-cells = <0>;
+#power-domain-cells = <1>;
+vsram-supply = <_vsram_md_ldo_reg>;
+mediatek,scpsys = <>;
+mediatek,apu_conn = <_conn>;
+mediatek,apu_vcore = <_vcore>;
+
+power-domain@MT8192_POWER_DOMAIN_APUSYS_TOP {
+reg = ;
+#power-domain-cells = <0>;
+clocks = < CLK_TOP_DSP_SEL>,
+ < CLK_TOP_IPU_IF_SEL>,
+ <>,
+ < CLK_TOP_UNIVPLL_D6_D2>;
+clock-names = "clk_top_conn",
+ "clk_top_ipu_if",
+ "clk_off",
+ "clk_on_default";
+assigned-clocks = < CLK_TOP_DSP_SEL>,
+ < CLK_TOP_IPU_IF_SEL>;
+assigned-clock-parents = < CLK_TOP_UNIVPLL_D6_D2>,
+ < CLK_TOP_UNIVPLL_D6_D2>;
+domain-supply = <_vproc1_buck_reg>;
+};
+};
--
2.18.0
[PATCH 3/8] dt-bindings: apu: Add MT8192 APU power domain
Create MT8192 APU power domain bindings. Add top power domain id. Signed-off-by: Flora Fu --- include/dt-bindings/power/mt8192-apu-power.h | 11 +++ 1 file changed, 11 insertions(+) create mode 100644 include/dt-bindings/power/mt8192-apu-power.h diff --git a/include/dt-bindings/power/mt8192-apu-power.h b/include/dt-bindings/power/mt8192-apu-power.h new file mode 100644 index ..b821bd4811a6 --- /dev/null +++ b/include/dt-bindings/power/mt8192-apu-power.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (c) 2021 MediaTek Inc. + */ + +#ifndef _DT_BINDINGS_POWER_MT8192_APU_POWER_H +#define _DT_BINDINGS_POWER_MT8192_APU_POWER_H + +#define MT8192_POWER_DOMAIN_APUSYS_TOP 0 + +#endif -- 2.18.0
[PATCH 2/8] clk: mediatek: mt8192: Add APU clocks support
Add APU clocks support on MT8192.
Signed-off-by: Flora Fu
---
drivers/clk/mediatek/clk-mt8192.c | 91 +++
1 file changed, 91 insertions(+)
diff --git a/drivers/clk/mediatek/clk-mt8192.c
b/drivers/clk/mediatek/clk-mt8192.c
index bf6a2084a348..4eb61f006306 100644
--- a/drivers/clk/mediatek/clk-mt8192.c
+++ b/drivers/clk/mediatek/clk-mt8192.c
@@ -244,6 +244,65 @@ static const char * const ccu_parents[] = {
"univpll_d6_d2"
};
+static const char * const dsp_parents[] = {
+ "clk26m",
+ "univpll_d6_d2",
+ "univpll_d4_d2",
+ "univpll_d5",
+ "univpll_d4",
+ "mmpll_d4",
+ "mainpll_d3",
+ "univpll_d3"
+};
+
+static const char * const dsp1_parents[] = {
+ "clk26m",
+ "npupll_ck",
+ "mainpll_d4_d2",
+ "univpll_d5",
+ "univpll_d4",
+ "mainpll_d3",
+ "univpll_d3",
+ "apupll_ck"
+};
+
+static const char * const dsp1_npupll_parents[] = {
+ "dsp1_sel",
+ "npupll_ck"
+};
+
+static const char * const dsp2_parents[] = {
+ "clk26m",
+ "npupll_ck",
+ "mainpll_d4_d2",
+ "univpll_d5",
+ "univpll_d4",
+ "mainpll_d3",
+ "univpll_d3",
+ "apupll_ck"
+};
+
+static const char * const dsp2_npupll_parents[] = {
+ "dsp2_sel",
+ "npupll_ck"
+};
+
+static const char * const dsp5_parents[] = {
+ "clk26m",
+ "apupll_ck",
+ "univpll_d4_d2",
+ "mainpll_d4",
+ "univpll_d4",
+ "mmpll_d4",
+ "mainpll_d3",
+ "univpll_d3"
+};
+
+static const char * const dsp5_apupll_parents[] = {
+ "dsp5_sel",
+ "apupll_ck"
+};
+
static const char * const dsp7_parents[] = {
"clk26m",
"mainpll_d4_d2",
@@ -255,6 +314,17 @@ static const char * const dsp7_parents[] = {
"mmpll_d4"
};
+static const char * const ipu_if_parents[] = {
+ "clk26m",
+ "univpll_d6_d2",
+ "mainpll_d4_d2",
+ "univpll_d4_d2",
+ "univpll_d5",
+ "mainpll_d4",
+ "tvdpll_ck",
+ "univpll_d4"
+};
+
static const char * const mfg_ref_parents[] = {
"clk26m",
"clk26m",
@@ -734,9 +804,26 @@ static const struct mtk_mux top_mtk_muxes[] = {
cam_parents, 0x030, 0x034, 0x038, 16, 4, 23, 0x004, 10),
MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU_SEL, "ccu_sel",
ccu_parents, 0x030, 0x034, 0x038, 24, 4, 31, 0x004, 11),
+ /* CLK_CFG_3 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP_SEL, "dsp_sel",
+ dsp_parents, 0x040, 0x044, 0x048, 0, 3, 7, 0x004, 12),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP1_SEL, "dsp1_sel",
+ dsp1_parents, 0x040, 0x044, 0x048, 8, 3, 15, 0x004, 13),
+ MUX_CLR_SET_UPD(CLK_TOP_DSP1_NPUPLL_SEL, "dsp1_npupll_sel",
+ dsp1_npupll_parents, 0x040, 0x044, 0x048, 11, 1, -1, -1),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP2_SEL, "dsp2_sel",
+ dsp2_parents, 0x040, 0x044, 0x048, 16, 3, 23, 0x004, 14),
+ MUX_CLR_SET_UPD(CLK_TOP_DSP2_NPUPLL_SEL, "dsp2_npupll_sel",
+ dsp2_npupll_parents, 0x040, 0x044, 0x048, 19, 1, -1, -1),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP5_SEL, "dsp5_sel",
+ dsp5_parents, 0x040, 0x044, 0x048, 24, 3, 31, 0x004, 15),
+ MUX_CLR_SET_UPD(CLK_TOP_DSP5_APUPLL_SEL, "dsp5_apupll_sel",
+ dsp5_apupll_parents, 0x040, 0x044, 0x048, 27, 1, -1, -1),
/* CLK_CFG_4 */
MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP7_SEL, "dsp7_sel",
dsp7_parents, 0x050, 0x054, 0x058, 0, 3, 7, 0x004, 16),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_IPU_IF_SEL, "ipu_if_sel",
+ ipu_if_parents, 0x050, 0x054, 0x058, 8, 3, 15, 0x004, 17),
MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_REF_SEL, "mfg_ref_sel",
mfg_ref_parents, 0x050, 0x054, 0x058, 16, 2, 23, 0x004, 18),
MUX_CLR_SET_UPD(CLK_TOP_MFG_PLL_SEL, "mfg_pll_sel",
@@ -1175,6 +1262,10 @@ static const struct mtk_pll_data plls[] = {
0, 0, 32, 0x031c, 24, 0x0040, 0x000c, 0, 0x0320, 0),
PLL_B(CLK_APMIXED_APLL2, "apll2", 0x032c, 0x033c, 0x,
0, 0, 32, 0x0330, 24, 0, 0, 0, 0x0334, 0),
+ PLL_B(CLK_APMIXED_APUPLL, "apupll", 0x03a0, 0x03ac, 0xff01,
+ HAVE_RST_BAR, BIT(23), 22, 0x03a4, 24, 0, 0, 0, 0x03a4, 0),
+ PLL_B(CLK_APMIXED_NPUPLL, "npupll", 0x03b4, 0x03c0, 0x0001,
+ 0, 0, 22, 0x03b8, 24, 0, 0, 0, 0x03b8, 0),
};
static struct clk_onecell_data *top_clk_data;
--
2.18.0
[PATCH 1/8] dt-bindings: clock: Add MT8192 APU clock bindings
Add clock bindings for APU on MT8192. Signed-off-by: Flora Fu --- include/dt-bindings/clock/mt8192-clk.h | 14 -- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/include/dt-bindings/clock/mt8192-clk.h b/include/dt-bindings/clock/mt8192-clk.h index ece5b4c0356c..71e07858f5dc 100644 --- a/include/dt-bindings/clock/mt8192-clk.h +++ b/include/dt-bindings/clock/mt8192-clk.h @@ -164,7 +164,15 @@ #define CLK_TOP_APLL12_DIV9152 #define CLK_TOP_SSUSB_TOP_REF 153 #define CLK_TOP_SSUSB_PHY_REF 154 -#define CLK_TOP_NR_CLK 155 +#define CLK_TOP_DSP_SEL155 +#define CLK_TOP_DSP1_SEL 156 +#define CLK_TOP_DSP1_NPUPLL_SEL157 +#define CLK_TOP_DSP2_SEL 158 +#define CLK_TOP_DSP2_NPUPLL_SEL159 +#define CLK_TOP_DSP5_SEL 160 +#define CLK_TOP_DSP5_APUPLL_SEL161 +#define CLK_TOP_IPU_IF_SEL 162 +#define CLK_TOP_NR_CLK 163 /* INFRACFG */ @@ -309,7 +317,9 @@ #define CLK_APMIXED_APLL1 8 #define CLK_APMIXED_APLL2 9 #define CLK_APMIXED_MIPID26M 10 -#define CLK_APMIXED_NR_CLK 11 +#define CLK_APMIXED_APUPLL 11 +#define CLK_APMIXED_NPUPLL 12 +#define CLK_APMIXED_NR_CLK 13 /* SCP_ADSP */ -- 2.18.0
[PATCH 0/8] Add Support for MediaTek MT8192 APU Power
The MediaTek AI Processing Unit (APU) is a proprietary hardware in the SoC to support AI operations. The series is to create apusys in the SoC folder for developing the related drivers. Add the apu clocks, basic apu nodes and the power domain to provide the power controller of APU subsystem. This series is based on MT8192 clock[1] and PMIC[2] patches. [1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=454523 [2] https://patchwork.kernel.org/project/linux-mediatek/list/?series=458733 Flora Fu (8): dt-bindings: clock: Add MT8192 APU clock bindings clk: mediatek: mt8192: Add APU clocks support dt-bindings: apu: Add MT8192 APU power domain dt-bindings: arm: mediatek: Add new document bindings for APU dt-bindings: soc: mediatek: apusys: Add new document for APU power domain soc: mediatek: apu: Add apusys and add apu power domain driver arm64: dts: mt8192: Add APU node arm64: dts: mt8192: Add APU power domain node .../arm/mediatek/mediatek,apusys.yaml | 56 ++ .../soc/mediatek/mediatek,apu-pm.yaml | 146 + arch/arm64/boot/dts/mediatek/mt8192-evb.dts | 7 + arch/arm64/boot/dts/mediatek/mt8192.dtsi | 46 ++ drivers/clk/mediatek/clk-mt8192.c | 91 +++ drivers/soc/mediatek/Kconfig | 10 + drivers/soc/mediatek/Makefile | 1 + drivers/soc/mediatek/apusys/Makefile | 2 + drivers/soc/mediatek/apusys/mtk-apu-pm.c | 613 ++ include/dt-bindings/clock/mt8192-clk.h| 14 +- include/dt-bindings/power/mt8192-apu-power.h | 11 + 11 files changed, 995 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,apusys.yaml create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,apu-pm.yaml create mode 100644 drivers/soc/mediatek/apusys/Makefile create mode 100644 drivers/soc/mediatek/apusys/mtk-apu-pm.c create mode 100644 include/dt-bindings/power/mt8192-apu-power.h -- 2.18.0
[PATCH v4 2/3] dt-bindings: Add Reset Controller for MediaTek SoC
Add device tree bindings.
Acked-by: Philipp Zabel
Signed-off-by: Flora Fu
---
.../devicetree/bindings/reset/mediatek,reset.txt | 52 ++
1 file changed, 52 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/mediatek,reset.txt
diff --git a/Documentation/devicetree/bindings/reset/mediatek,reset.txt
b/Documentation/devicetree/bindings/reset/mediatek,reset.txt
new file mode 100644
index 000..647b401
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/mediatek,reset.txt
@@ -0,0 +1,52 @@
+MediaTek SoC Reset Controller
+==
+The reset controller driver accesses registers through the syscon regmap. It
+is a child node of syscon.
+
+Required properties:
+- compatible : "mediatek,reset"
+- #reset-cells: 1
+- reg: The register region can be accessed from syscon. The first parameter is
+ reset base address offset. The second parameter is byte width of reset
registers.
+
+example:
+infracfg: syscon@10001000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mediatek,mt8135-infracfg", "syscon";
+ reg = <0 0x10001000 0 0x1000>;
+
+ infrarst: reset-controller@30 {
+ #reset-cells = <1>;
+ compatible = "mediatek,mt8135-infracfg-reset", "mediatek,reset";
+ reg = <0x30 0x8>;
+ };
+};
+
+Specifying reset lines connected to IP modules
+==
+
+The reset controller(mtk-reset) manages various reset sources. Those device
nodes should
+specify the reset line on the rstc in their resets property, containing a
phandle to the
+rstc device node and a RESET_INDEX specifying which module to reset, as
described in
+reset.txt.
+
+For MediaTek SoC, RESET_INDEX is reset bit defined in INFRACFG or PERICFG
registers.
+
+example:
+pwrap: pwrap@1000f000 {
+ compatible = "mediatek,mt8135-pwrap";
+ reg = <0 0x1000f000 0 0x1000>,
+ <0 0x11017000 0 0x1000>;
+ reg-names = "pwrap-base",
+ "pwrap-bridge-base";
+ resets = < MT8135_INFRA_PMIC_WRAP_RST>,
+ < MT8135_PERI_PWRAP_BRIDGE_SW_RST>;
+ reset-names = "infrarst", "perirst";
+};
+
+Definitions for the supported resets by IC:
+MT8135:
+include/dt-bindings/reset-controller/mt8135-resets.h
+MT8173:
+include/dt-bindings/reset-controller/mt8173-resets.h
--
1.8.1.1.dirty
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[PATCH v4 3/3] arm: dts: mt8135: Add Reset Controller for MediaTek SoC
Add reset controller to MT8135.dtsi.
Acked-by: Philipp Zabel
Signed-off-by: Flora Fu
---
arch/arm/boot/dts/mt8135.dtsi | 29 +
1 file changed, 29 insertions(+)
diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi
index ec83e69..989e488 100644
--- a/arch/arm/boot/dts/mt8135.dtsi
+++ b/arch/arm/boot/dts/mt8135.dtsi
@@ -14,6 +14,7 @@
#include
#include
+#include
#include "skeleton64.dtsi"
/ {
@@ -100,6 +101,34 @@
compatible = "simple-bus";
ranges;
+ infracfg: syscon@10001000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mediatek,mt8135-infracfg", "syscon";
+ reg = <0 0x10001000 0 0x1000>;
+ #clock-cells = <1>;
+
+ infrarst: reset-controller@30 {
+ #reset-cells = <1>;
+ compatible = "mediatek,mt8135-infracfg-reset",
"mediatek,reset";
+ reg = <0x30 0x8>;
+ };
+ };
+
+ pericfg: syscon@10003000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mediatek,mt8135-pericfg", "syscon";
+ reg = <0 0x10003000 0 0x1000>;
+ #clock-cells = <1>;
+
+ perirst: reset-controller@00 {
+ #reset-cells = <1>;
+ compatible = "mediatek,mt8135-pericfg-reset",
"mediatek,reset";
+ reg = <0x00 0x8>;
+ };
+ };
+
timer: timer@10008000 {
compatible = "mediatek,mt8135-timer",
"mediatek,mt6577-timer";
--
1.8.1.1.dirty
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[PATCH v4 1/3] reset: mediatek: Add Reset Controller for MediaTek SoC
Add a driver in reset controller.
Signed-off-by: Flora Fu
---
drivers/reset/Makefile | 1 +
drivers/reset/reset-mtk.c | 130 +
.../dt-bindings/reset-controller/mt8135-resets.h | 64 ++
.../dt-bindings/reset-controller/mt8173-resets.h | 63 ++
4 files changed, 258 insertions(+)
create mode 100644 drivers/reset/reset-mtk.c
create mode 100644 include/dt-bindings/reset-controller/mt8135-resets.h
create mode 100644 include/dt-bindings/reset-controller/mt8173-resets.h
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 157d421..d81a60a 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -3,3 +3,4 @@ obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o
obj-$(CONFIG_ARCH_BERLIN) += reset-berlin.o
obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o
obj-$(CONFIG_ARCH_STI) += sti/
+obj-$(CONFIG_ARCH_MEDIATEK) += reset-mtk.o
diff --git a/drivers/reset/reset-mtk.c b/drivers/reset/reset-mtk.c
new file mode 100644
index 000..ccdd4bb
--- /dev/null
+++ b/drivers/reset/reset-mtk.c
@@ -0,0 +1,130 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Flora Fu
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct mtk_reset_data {
+ struct regmap *regmap;
+ u32 resetbase;
+ u32 num_regs;
+ struct reset_controller_dev rcdev;
+};
+
+static int mtk_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct regmap *regmap;
+ u32 addr;
+ u32 mask;
+ struct mtk_reset_data *data = container_of(rcdev,
+struct mtk_reset_data,
+rcdev);
+ regmap = data->regmap;
+ addr = data->resetbase + ((id / 32) << 2);
+ mask = BIT(id % 32);
+
+ return regmap_update_bits(regmap, addr, mask, mask);
+}
+
+static int mtk_reset_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct regmap *regmap;
+ u32 addr;
+ u32 mask;
+ struct mtk_reset_data *data = container_of(rcdev,
+struct mtk_reset_data,
+rcdev);
+
+ regmap = data->regmap;
+ addr = data->resetbase + ((id / 32) << 2);
+ mask = BIT(id % 32);
+
+ return regmap_update_bits(regmap, addr, mask, ~mask);
+}
+
+static struct reset_control_ops mtk_reset_ops = {
+ .assert = mtk_reset_assert,
+ .deassert = mtk_reset_deassert,
+};
+
+static int mtk_reset_probe(struct platform_device *pdev)
+{
+ struct mtk_reset_data *data;
+ struct device_node *np = pdev->dev.of_node;
+ struct device_node *syscon_np;
+ u32 reg[2];
+ int ret;
+
+ data = devm_kzalloc(>dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ syscon_np = of_get_parent(np);
+ data->regmap = syscon_node_to_regmap(syscon_np);
+ of_node_put(syscon_np);
+ if (IS_ERR(data->regmap)) {
+ dev_err(>dev, "couldn't get syscon-reset regmap\n");
+ return PTR_ERR(data->regmap);
+ }
+ ret = of_property_read_u32_array(np, "reg", reg, 2);
+ if (ret) {
+ dev_err(>dev, "couldn't read reset base from syscon!\n");
+ return -EINVAL;
+ }
+
+ data->resetbase = reg[0];
+ data->num_regs = reg[1] >> 2;
+ data->rcdev.owner = THIS_MODULE;
+ data->rcdev.nr_resets = data->num_regs * 32;
+ data->rcdev.ops = _reset_ops;
+ data->rcdev.of_node = pdev->dev.of_node;
+
+ return reset_controller_register(>rcdev);
+}
+
+static int mtk_reset_remove(struct platform_device *pdev)
+{
+ struct mtk_reset_data *data = platform_get_drvdata(pdev);
+
+ reset_controller_unregister(>rcdev);
+
+ return 0;
+}
+
+static const struct of_device_id mtk_reset_dt_ids[] = {
+ { .compatible = "mediatek,reset", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, mtk_reset_dt_ids);
+
+static struct platform_driver mtk_reset_driver = {
+ .probe = mtk_reset_probe,
+ .remove = mtk_reset_remove,
+ .driver = {
+ .name = "mtk-reset",
+ .of_match_table = mtk_reset_dt_ids,
+ },
+};
+
+
[PATCH v4 0/3] Add Reset Controller for MediaTek SoC
Hi, This driver implements the reset controller for MediaTek SoC. It adds support for MT8135 and MT8173 SoC in the patch set. The reset controller uses syscon as its regmap and adopts syscon RFC in https://lkml.org/lkml/2014/11/3/134. This driver is based on 3.19-rc1. Changes since v3 1. Merge patch set by 3.19-rc1. 2. Add header file "mt8173-resets.h" for supported resets in MT8173. Changes since v2 - Correct #size-cell to be 1. - Add header file "mt8135-resets.h" for supported resets in MT8135. Changes since v1 (1) Patch 1/3: Update reset controller driver's implementation. - rename mt_ prefixes to the prefix mtk_ - use module_platform_driver() macro for driver init. - clean up includes of header files. - reset controll is a child of syscon. Get regamp through its parent node. - rename data->size to data->num_regs. It is number of registers in syscon for reset usage. (2) Patch 2/3: update bindings document according to new dts layout of reset-controller. (3) Patch 3/3: change reset-controller device node as child of syscon. Flora Fu (3): reset: mediatek: Add Reset Controller for MediaTek SoC dt-bindings: Add Reset Controller for MediaTek SoC arm: dts: mt8135: Add Reset Controller for MediaTek SoC .../devicetree/bindings/reset/mediatek,reset.txt | 52 + arch/arm/boot/dts/mt8135.dtsi | 29 + drivers/reset/Makefile | 1 + drivers/reset/reset-mtk.c | 130 + .../dt-bindings/reset-controller/mt8135-resets.h | 64 ++ .../dt-bindings/reset-controller/mt8173-resets.h | 63 ++ 6 files changed, 339 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/mediatek,reset.txt create mode 100644 drivers/reset/reset-mtk.c create mode 100644 include/dt-bindings/reset-controller/mt8135-resets.h create mode 100644 include/dt-bindings/reset-controller/mt8173-resets.h -- 1.8.1.1.dirty -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v4 0/3] Add Reset Controller for MediaTek SoC
Hi, This driver implements the reset controller for MediaTek SoC. It adds support for MT8135 and MT8173 SoC in the patch set. The reset controller uses syscon as its regmap and adopts syscon RFC in https://lkml.org/lkml/2014/11/3/134. This driver is based on 3.19-rc1. Changes since v3 1. Merge patch set by 3.19-rc1. 2. Add header file mt8173-resets.h for supported resets in MT8173. Changes since v2 - Correct #size-cell to be 1. - Add header file mt8135-resets.h for supported resets in MT8135. Changes since v1 (1) Patch 1/3: Update reset controller driver's implementation. - rename mt_ prefixes to the prefix mtk_ - use module_platform_driver() macro for driver init. - clean up includes of header files. - reset controll is a child of syscon. Get regamp through its parent node. - rename data-size to data-num_regs. It is number of registers in syscon for reset usage. (2) Patch 2/3: update bindings document according to new dts layout of reset-controller. (3) Patch 3/3: change reset-controller device node as child of syscon. Flora Fu (3): reset: mediatek: Add Reset Controller for MediaTek SoC dt-bindings: Add Reset Controller for MediaTek SoC arm: dts: mt8135: Add Reset Controller for MediaTek SoC .../devicetree/bindings/reset/mediatek,reset.txt | 52 + arch/arm/boot/dts/mt8135.dtsi | 29 + drivers/reset/Makefile | 1 + drivers/reset/reset-mtk.c | 130 + .../dt-bindings/reset-controller/mt8135-resets.h | 64 ++ .../dt-bindings/reset-controller/mt8173-resets.h | 63 ++ 6 files changed, 339 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/mediatek,reset.txt create mode 100644 drivers/reset/reset-mtk.c create mode 100644 include/dt-bindings/reset-controller/mt8135-resets.h create mode 100644 include/dt-bindings/reset-controller/mt8173-resets.h -- 1.8.1.1.dirty -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v4 1/3] reset: mediatek: Add Reset Controller for MediaTek SoC
Add a driver in reset controller.
Signed-off-by: Flora Fu flora...@mediatek.com
---
drivers/reset/Makefile | 1 +
drivers/reset/reset-mtk.c | 130 +
.../dt-bindings/reset-controller/mt8135-resets.h | 64 ++
.../dt-bindings/reset-controller/mt8173-resets.h | 63 ++
4 files changed, 258 insertions(+)
create mode 100644 drivers/reset/reset-mtk.c
create mode 100644 include/dt-bindings/reset-controller/mt8135-resets.h
create mode 100644 include/dt-bindings/reset-controller/mt8173-resets.h
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 157d421..d81a60a 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -3,3 +3,4 @@ obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o
obj-$(CONFIG_ARCH_BERLIN) += reset-berlin.o
obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o
obj-$(CONFIG_ARCH_STI) += sti/
+obj-$(CONFIG_ARCH_MEDIATEK) += reset-mtk.o
diff --git a/drivers/reset/reset-mtk.c b/drivers/reset/reset-mtk.c
new file mode 100644
index 000..ccdd4bb
--- /dev/null
+++ b/drivers/reset/reset-mtk.c
@@ -0,0 +1,130 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Flora Fu flora...@mediatek.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/mfd/syscon.h
+#include linux/module.h
+#include linux/of.h
+#include linux/platform_device.h
+#include linux/regmap.h
+#include linux/reset-controller.h
+
+struct mtk_reset_data {
+ struct regmap *regmap;
+ u32 resetbase;
+ u32 num_regs;
+ struct reset_controller_dev rcdev;
+};
+
+static int mtk_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct regmap *regmap;
+ u32 addr;
+ u32 mask;
+ struct mtk_reset_data *data = container_of(rcdev,
+struct mtk_reset_data,
+rcdev);
+ regmap = data-regmap;
+ addr = data-resetbase + ((id / 32) 2);
+ mask = BIT(id % 32);
+
+ return regmap_update_bits(regmap, addr, mask, mask);
+}
+
+static int mtk_reset_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct regmap *regmap;
+ u32 addr;
+ u32 mask;
+ struct mtk_reset_data *data = container_of(rcdev,
+struct mtk_reset_data,
+rcdev);
+
+ regmap = data-regmap;
+ addr = data-resetbase + ((id / 32) 2);
+ mask = BIT(id % 32);
+
+ return regmap_update_bits(regmap, addr, mask, ~mask);
+}
+
+static struct reset_control_ops mtk_reset_ops = {
+ .assert = mtk_reset_assert,
+ .deassert = mtk_reset_deassert,
+};
+
+static int mtk_reset_probe(struct platform_device *pdev)
+{
+ struct mtk_reset_data *data;
+ struct device_node *np = pdev-dev.of_node;
+ struct device_node *syscon_np;
+ u32 reg[2];
+ int ret;
+
+ data = devm_kzalloc(pdev-dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ syscon_np = of_get_parent(np);
+ data-regmap = syscon_node_to_regmap(syscon_np);
+ of_node_put(syscon_np);
+ if (IS_ERR(data-regmap)) {
+ dev_err(pdev-dev, couldn't get syscon-reset regmap\n);
+ return PTR_ERR(data-regmap);
+ }
+ ret = of_property_read_u32_array(np, reg, reg, 2);
+ if (ret) {
+ dev_err(pdev-dev, couldn't read reset base from syscon!\n);
+ return -EINVAL;
+ }
+
+ data-resetbase = reg[0];
+ data-num_regs = reg[1] 2;
+ data-rcdev.owner = THIS_MODULE;
+ data-rcdev.nr_resets = data-num_regs * 32;
+ data-rcdev.ops = mtk_reset_ops;
+ data-rcdev.of_node = pdev-dev.of_node;
+
+ return reset_controller_register(data-rcdev);
+}
+
+static int mtk_reset_remove(struct platform_device *pdev)
+{
+ struct mtk_reset_data *data = platform_get_drvdata(pdev);
+
+ reset_controller_unregister(data-rcdev);
+
+ return 0;
+}
+
+static const struct of_device_id mtk_reset_dt_ids[] = {
+ { .compatible = mediatek,reset, },
+ {},
+};
+MODULE_DEVICE_TABLE(of, mtk_reset_dt_ids);
+
+static struct platform_driver mtk_reset_driver = {
+ .probe = mtk_reset_probe,
+ .remove = mtk_reset_remove,
+ .driver = {
+ .name = mtk-reset,
+ .of_match_table = mtk_reset_dt_ids
[PATCH v4 2/3] dt-bindings: Add Reset Controller for MediaTek SoC
Add device tree bindings.
Acked-by: Philipp Zabel p.za...@pengutronix.de
Signed-off-by: Flora Fu flora...@mediatek.com
---
.../devicetree/bindings/reset/mediatek,reset.txt | 52 ++
1 file changed, 52 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/mediatek,reset.txt
diff --git a/Documentation/devicetree/bindings/reset/mediatek,reset.txt
b/Documentation/devicetree/bindings/reset/mediatek,reset.txt
new file mode 100644
index 000..647b401
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/mediatek,reset.txt
@@ -0,0 +1,52 @@
+MediaTek SoC Reset Controller
+==
+The reset controller driver accesses registers through the syscon regmap. It
+is a child node of syscon.
+
+Required properties:
+- compatible : mediatek,reset
+- #reset-cells: 1
+- reg: The register region can be accessed from syscon. The first parameter is
+ reset base address offset. The second parameter is byte width of reset
registers.
+
+example:
+infracfg: syscon@10001000 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = mediatek,mt8135-infracfg, syscon;
+ reg = 0 0x10001000 0 0x1000;
+
+ infrarst: reset-controller@30 {
+ #reset-cells = 1;
+ compatible = mediatek,mt8135-infracfg-reset, mediatek,reset;
+ reg = 0x30 0x8;
+ };
+};
+
+Specifying reset lines connected to IP modules
+==
+
+The reset controller(mtk-reset) manages various reset sources. Those device
nodes should
+specify the reset line on the rstc in their resets property, containing a
phandle to the
+rstc device node and a RESET_INDEX specifying which module to reset, as
described in
+reset.txt.
+
+For MediaTek SoC, RESET_INDEX is reset bit defined in INFRACFG or PERICFG
registers.
+
+example:
+pwrap: pwrap@1000f000 {
+ compatible = mediatek,mt8135-pwrap;
+ reg = 0 0x1000f000 0 0x1000,
+ 0 0x11017000 0 0x1000;
+ reg-names = pwrap-base,
+ pwrap-bridge-base;
+ resets = infrarst MT8135_INFRA_PMIC_WRAP_RST,
+ perirst MT8135_PERI_PWRAP_BRIDGE_SW_RST;
+ reset-names = infrarst, perirst;
+};
+
+Definitions for the supported resets by IC:
+MT8135:
+include/dt-bindings/reset-controller/mt8135-resets.h
+MT8173:
+include/dt-bindings/reset-controller/mt8173-resets.h
--
1.8.1.1.dirty
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[PATCH v4 3/3] arm: dts: mt8135: Add Reset Controller for MediaTek SoC
Add reset controller to MT8135.dtsi.
Acked-by: Philipp Zabel p.za...@pengutronix.de
Signed-off-by: Flora Fu flora...@mediatek.com
---
arch/arm/boot/dts/mt8135.dtsi | 29 +
1 file changed, 29 insertions(+)
diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi
index ec83e69..989e488 100644
--- a/arch/arm/boot/dts/mt8135.dtsi
+++ b/arch/arm/boot/dts/mt8135.dtsi
@@ -14,6 +14,7 @@
#include dt-bindings/interrupt-controller/irq.h
#include dt-bindings/interrupt-controller/arm-gic.h
+#include dt-bindings/reset-controller/mt8135-resets.h
#include skeleton64.dtsi
/ {
@@ -100,6 +101,34 @@
compatible = simple-bus;
ranges;
+ infracfg: syscon@10001000 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = mediatek,mt8135-infracfg, syscon;
+ reg = 0 0x10001000 0 0x1000;
+ #clock-cells = 1;
+
+ infrarst: reset-controller@30 {
+ #reset-cells = 1;
+ compatible = mediatek,mt8135-infracfg-reset,
mediatek,reset;
+ reg = 0x30 0x8;
+ };
+ };
+
+ pericfg: syscon@10003000 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = mediatek,mt8135-pericfg, syscon;
+ reg = 0 0x10003000 0 0x1000;
+ #clock-cells = 1;
+
+ perirst: reset-controller@00 {
+ #reset-cells = 1;
+ compatible = mediatek,mt8135-pericfg-reset,
mediatek,reset;
+ reg = 0x00 0x8;
+ };
+ };
+
timer: timer@10008000 {
compatible = mediatek,mt8135-timer,
mediatek,mt6577-timer;
--
1.8.1.1.dirty
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[PATCH v4 2/6] mfd: MT6397: Add support for PMIC MT6397 MFD
Add core files for MT6397 MFD driver.
Signed-off-by: Flora Fu
---
drivers/mfd/Kconfig | 10 +
drivers/mfd/Makefile | 1 +
drivers/mfd/mt6397-core.c| 94 +
include/linux/mfd/mt6397/core.h | 23 +++
include/linux/mfd/mt6397/registers.h | 362 +++
5 files changed, 490 insertions(+)
create mode 100644 drivers/mfd/mt6397-core.c
create mode 100644 include/linux/mfd/mt6397/core.h
create mode 100644 include/linux/mfd/mt6397/registers.h
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 2e6b731..7782e95 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -489,6 +489,16 @@ config MFD_MAX8998
additional drivers must be enabled in order to use the functionality
of the device.
+config MFD_MT6397
+ tristate "MediaTek MT6397 PMIC Support"
+ select MFD_CORE
+ select IRQ_DOMAIN
+ help
+ Say yes here to add support for MediaTek MT6397 PMIC. This is
+ a Power Management IC. This driver provides common support for
+ accessing the device; additional drivers must be enabled in order
+ to use the functionality of the device.
+
config MFD_MENF21BMC
tristate "MEN 14F021P00 Board Management Controller Support"
depends on I2C
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 53467e2..329d4ed 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -179,3 +179,4 @@ obj-$(CONFIG_MFD_DLN2) += dln2.o
intel-soc-pmic-objs:= intel_soc_pmic_core.o intel_soc_pmic_crc.o
obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o
+obj-$(CONFIG_MFD_MT6397) += mt6397-core.o
diff --git a/drivers/mfd/mt6397-core.c b/drivers/mfd/mt6397-core.c
new file mode 100644
index 000..45ce01a
--- /dev/null
+++ b/drivers/mfd/mt6397-core.c
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Flora Fu
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+
+static const struct mfd_cell mt6397_devs[] = {
+ {
+ .name = "mt6397-rtc",
+ .of_compatible = "mediatek,mt6397-rtc",
+ },
+ {
+ .name = "mt6397-regulator",
+ .of_compatible = "mediatek,mt6397-regulator",
+ },
+ {
+ .name = "mt6397-codec",
+ .of_compatible = "mediatek,mt6397-codec",
+ },
+ {
+ .name = "mt6397-clk",
+ .of_compatible = "mediatek,mt6397-clk",
+ },
+};
+
+static int mt6397_probe(struct platform_device *pdev)
+{
+ int ret;
+ struct mt6397_chip *mt6397;
+
+ mt6397 = devm_kzalloc(>dev, sizeof(*mt6397), GFP_KERNEL);
+ if (!mt6397)
+ return -ENOMEM;
+
+ mt6397->dev = >dev;
+ /*
+* mt6397 MFD is child device of soc pmic wrapper.
+* Regmap is set from its parent.
+*/
+ mt6397->regmap = dev_get_platdata(>dev);
+ if (!mt6397->regmap)
+ return -ENODEV;
+
+ platform_set_drvdata(pdev, mt6397);
+
+ ret = mfd_add_devices(>dev, -1, mt6397_devs,
+ ARRAY_SIZE(mt6397_devs), NULL, 0, NULL);
+ if (ret)
+ dev_err(>dev, "failed to add child devices: %d\n", ret);
+
+ return ret;
+}
+
+static int mt6397_remove(struct platform_device *pdev)
+{
+ mfd_remove_devices(>dev);
+
+ return 0;
+}
+
+static const struct of_device_id mt6397_of_match[] = {
+ { .compatible = "mediatek,mt6397" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, mt6397_of_match);
+
+static struct platform_driver mt6397_driver = {
+ .probe = mt6397_probe,
+ .remove = mt6397_remove,
+ .driver = {
+ .name = "mt6397",
+ .of_match_table = of_match_ptr(mt6397_of_match),
+ },
+};
+
+module_platform_driver(mt6397_driver);
+
+MODULE_AUTHOR("Flora Fu ");
+MODULE_DESCRIPTION("Driver for MediaTek MT6397 PMIC");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:mt6397");
diff --git a/include/linux/mfd/mt6397/core.h b/include/linux/mfd/mt6397/core.h
new file mode 100644
index 000..567164e
--- /dev/null
+++ b/include/linux/mfd/mt6397/core.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Flora Fu
+ *
+ * This program is free software; you c
[PATCH v4 1/6] soc: mediatek: Add PMIC wrapper for MT8135 and MT6397 SoC
Add PMIC wrapper of MT8135 to access MT6397 MFD.
Signed-off-by: Flora Fu
---
drivers/soc/Kconfig | 1 +
drivers/soc/Makefile| 1 +
drivers/soc/mediatek/Kconfig| 12 +
drivers/soc/mediatek/Makefile | 1 +
drivers/soc/mediatek/mt8135-pmic-wrap.c | 855
drivers/soc/mediatek/mt8135-pmic-wrap.h | 138 ++
6 files changed, 1008 insertions(+)
create mode 100644 drivers/soc/mediatek/Kconfig
create mode 100644 drivers/soc/mediatek/Makefile
create mode 100644 drivers/soc/mediatek/mt8135-pmic-wrap.c
create mode 100644 drivers/soc/mediatek/mt8135-pmic-wrap.h
diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
index 76d6bd4..d8bde82 100644
--- a/drivers/soc/Kconfig
+++ b/drivers/soc/Kconfig
@@ -1,5 +1,6 @@
menu "SOC (System On Chip) specific Drivers"
+source "drivers/soc/mediatek/Kconfig"
source "drivers/soc/qcom/Kconfig"
source "drivers/soc/ti/Kconfig"
source "drivers/soc/versatile/Kconfig"
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index 063113d..70042b2 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -2,6 +2,7 @@
# Makefile for the Linux Kernel SOC specific device drivers.
#
+obj-$(CONFIG_ARCH_MEDIATEK)+= mediatek/
obj-$(CONFIG_ARCH_QCOM)+= qcom/
obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-$(CONFIG_SOC_TI) += ti/
diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
new file mode 100644
index 000..746e030
--- /dev/null
+++ b/drivers/soc/mediatek/Kconfig
@@ -0,0 +1,12 @@
+#
+# MediaTek SoC drivers
+#
+config MT8135_PMIC_WRAP
+ tristate "MediaTek MT8135 PMIC Wrapper Support"
+ depends on ARCH_MEDIATEK
+ select REGMAP
+ help
+ Say yes here to add support for MediaTek MT8135 PMIC Wrapper.
+ PMIC wrapper is a proprietary hardware in MT8135 to make
+ communication protocols to access PMIC device.
+ This driver implement access protocols for MT8135.
diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
new file mode 100644
index 000..49b9588
--- /dev/null
+++ b/drivers/soc/mediatek/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_MT8135_PMIC_WRAP) += mt8135-pmic-wrap.o
diff --git a/drivers/soc/mediatek/mt8135-pmic-wrap.c
b/drivers/soc/mediatek/mt8135-pmic-wrap.c
new file mode 100644
index 000..3c35afc
--- /dev/null
+++ b/drivers/soc/mediatek/mt8135-pmic-wrap.c
@@ -0,0 +1,855 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Flora Fu
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "mt8135-pmic-wrap.h"
+
+/* macro for wrapper status */
+#define PWRAP_GET_WACS0_WDATA(x) (((x) >> 0) & 0x)
+#define PWRAP_GET_WACS0_ADR(x) (((x) >> 16) & 0x7fff)
+#define PWRAP_GET_WACS0_WRITE(x) (((x) >> 31) & 0x0001)
+#define PWRAP_GET_WACS0_RDATA(x) (((x) >> 0) & 0x)
+#define PWRAP_GET_WACS0_FSM(x) (((x) >> 16) & 0x0007)
+#define PWRAP_STATE_SYNC_IDLE0 (1 << 20)
+#define PWRAP_STATE_INIT_DONE0 (1 << 21)
+
+/* macro for WACS FSM */
+#define PWRAP_WACS_FSM_IDLE0x00
+#define PWRAP_WACS_FSM_REQ 0x02
+#define PWRAP_WACS_FSM_WFDLE 0x04
+#define PWRAP_WACS_FSM_WFVLDCLR0x06
+#define PWRAP_WACS_INIT_DONE 0x01
+#define PWRAP_WACS_WACS_SYNC_IDLE 0x01
+
+/* macro for device wrapper default value */
+#define PWRAP_DEW_READ_TEST_VAL0x5aa5
+#define PWRAP_DEW_WRITE_TEST_VAL 0xa55a
+
+/* macro for manual command */
+#define PWRAP_OP_WR0x1
+#define PWRAP_OP_RD0x0
+#define PWRAP_OP_CSH 0x0
+#define PWRAP_OP_CSL 0x1
+#define PWRAP_OP_OUTS 0x8
+#define PWRAP_OP_OUTD 0x9
+#define PWRAP_OP_OUTQ 0xA
+
+struct pmic_wrapper {
+ struct platform_device *pdev;
+ void __iomem *pwrap_base;
+ void __iomem *pwrap_bridge_base;
+ struct regmap *regmap;
+};
+
+static bool is_fsm_idle(u32 x)
+{
+ return PWRAP_GET_WACS0_FSM(x) == PWRAP_WACS_FSM_IDLE;
+}
+
+static bool is_fsm_vldclr(u32 x)
+{
+ return PWRAP_GET_WACS0_FSM(x) == PWRAP_WACS_FSM_WFVLDCLR;
+}
+
+static bool is_sync_idle(u32 x)
+{
+ return x & PWR
[PATCH v4 4/6] dt-bindings: Add document for MT6397 MFD
Signed-off-by: Flora Fu
---
Documentation/devicetree/bindings/mfd/mt6397.txt | 75
1 file changed, 75 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mfd/mt6397.txt
diff --git a/Documentation/devicetree/bindings/mfd/mt6397.txt
b/Documentation/devicetree/bindings/mfd/mt6397.txt
new file mode 100644
index 000..64ef408
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/mt6397.txt
@@ -0,0 +1,75 @@
+MediaTek MT6397 Multifunction Device Driver
+
+MT6397 is a multifunction device with the following sub modules:
+- Regulator
+- RTC
+- Audio codec
+- GPIO
+- Clock
+
+It is interfaced to host controller using SPI interface by a proprietary
hardware
+called PMIC wrapper or pwrap. MT6397 MFD is a child device of pwrap.
+See the following for pwarp node definitions:
+Documentation/devicetree/bindings/soc/mediatek,mt8135-pwrap.txt
+
+This document describes the binding for mfd device and its sub module.
+
+Required properties:
+compatible: "mediatek,mt6397"
+
+Optional properties:
+- codec: Audio codec
+- pinctrl: GPIO in mt6397
+- rtc: RTC
+- clock: clocks in mt6397
+- regulators: regulators in mt6397
+
+Example:
+ pwrap: pwrap@1000f000 {
+ compatible = "mediatek,mt8135-pwrap";
+ reg = <0 0x1000f000 0 0x1000>,
+ <0 0x11017000 0 0x1000>;
+ reg-names = "pwrap-base", "pwrap-bridge-base";
+ interrupts = ;
+ resets = < MT8135_INFRA_PMIC_WRAP_RST>,
+ < MT8135_PERI_PWRAP_BRIDGE_SW_RST>;
+ reset-names = "infra-pwrap-rst",
+ "peri-pwrap-bridge-rst";
+ clocks = <_sel>, <>;
+ clock-names = "pmicspi-sel", "pmicspi-parent";
+
+ pmic {
+ compatible = "mediatek,mt6397";
+
+ codec: mt6397codec {
+ compatible = "mediatek,mt6397-codec";
+ };
+
+ pinctrl@0xC000 {
+ compatible = "mediatek,mt6397-pinctrl";
+ reg = <0 0xC000 0 0x0108>;
+ gpio-controller;
+ };
+
+ mt6397regulator: mt6397regulator {
+ compatible = "mediatek,mt6397-regulator";
+
+ mt6397_vpca15_reg: buck_vpca15 {
+ regulator-compatible = "buck_vpca15";
+ regulator-name = "vpca15";
+ regulator-min-microvolt = < 85>;
+ regulator-max-microvolt = <140>;
+ regulator-ramp-delay = <12500>;
+ regulator-always-on;
+ };
+
+ mt6397_vgp4_reg: ldo_vgp4 {
+ regulator-compatible = "ldo_vgp4";
+ regulator-name = "vgp4";
+ regulator-min-microvolt = <120>;
+ regulator-max-microvolt = <330>;
+ regulator-enable-ramp-delay = <218>;
+ };
+ };
+ };
+ };
--
1.8.1.1.dirty
--
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Please read the FAQ at http://www.tux.org/lkml/
[PATCH v4 3/6] dt-bindings:: Add document for MT8135 PMIC Wrapper
Signed-off-by: Flora Fu
---
.../soc/mediatek/mediatek,mt8135-pwrap.txt | 51 ++
1 file changed, 51 insertions(+)
create mode 100644
Documentation/devicetree/bindings/soc/mediatek/mediatek,mt8135-pwrap.txt
diff --git
a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mt8135-pwrap.txt
b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mt8135-pwrap.txt
new file mode 100644
index 000..d630fa0
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mt8135-pwrap.txt
@@ -0,0 +1,51 @@
+MediaTek MT8135 PMIC Wrapper Driver
+
+MediaTek PMIC MFD is interfaced to host controller using SPI interface
+by a proprietary hardware called PMIC wrapper or pwrap.
+
++-+ +---+
+| | | |
+| Mediatek AP SoC | | |
+| (ex. MT8135)| |MT6397 |
+| | | |
+| ++ | (SPI bus) | ++|
+| || |---| |||
+| | PMIC | |---| | PMIC ||
+| | Wrapper| |---| | Wrapper||
+| || |---| |||
+| ++ | | ++|
+| | | |
++-+ +---+
+
+This document describes the binding for MT8135 PMIC wrapper.
+
+Required properties in pwrap device node.
+- compatible:"mediatek,mt8135-pwrap"
+- interrupts: IRQ for pwrap in SOC
+- reg: address range for pwrap registers
+- resets: reset bit for pwrap
+- clock: clock frequency selection in SPI bus
+
+Optional properities:
+- pmic: Mediatek PMIC MFD is the child device of pwrap
+ See the following for child node definitions:
+ Documentation/devicetree/bindings/mfd/mt6397.txt
+
+Example:
+ pwrap: pwrap@1000f000 {
+ compatible = "mediatek,mt8135-pwrap";
+ reg = <0 0x1000f000 0 0x1000>,
+ <0 0x11017000 0 0x1000>;
+ reg-names = "pwrap-base", "pwrap-bridge-base";
+ interrupts = ;
+ resets = < MT8135_INFRA_PMIC_WRAP_RST>,
+ < MT8135_PERI_PWRAP_BRIDGE_SW_RST>;
+ reset-names = "infra-pwrap-rst",
+ "peri-pwrap-bridge-rst";
+ clocks = <_sel>, <>;
+ clock-names = "pmicspi-sel", "pmicspi-parent";
+
+ pmic {
+ compatible = "mediatek,mt6397";
+ };
+ };
--
1.8.1.1.dirty
--
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Please read the FAQ at http://www.tux.org/lkml/
[PATCH v4 6/6] arm: dts: mt8135: Add support for MT6397 MFD and regulator
Add device tree for MT6397 MFD and regulator in mt8135 evb board file.
Signed-off-by: Flora Fu
---
arch/arm/boot/dts/mt8135-evbp1.dts | 193 +
1 file changed, 193 insertions(+)
diff --git a/arch/arm/boot/dts/mt8135-evbp1.dts
b/arch/arm/boot/dts/mt8135-evbp1.dts
index a5adf97..3be2c8b 100644
--- a/arch/arm/boot/dts/mt8135-evbp1.dts
+++ b/arch/arm/boot/dts/mt8135-evbp1.dts
@@ -23,3 +23,196 @@
reg = <0 0x8000 0 0x4000>;
};
};
+
+ {
+ pmic: mt6397 {
+ compatible = "mediatek,mt6397";
+
+ mt6397regulator: mt6397regulator {
+ compatible = "mediatek,mt6397-regulator";
+
+ mt6397_vpca15_reg: buck_vpca15 {
+ regulator-compatible = "buck_vpca15";
+ regulator-name = "vpca15";
+ regulator-min-microvolt = < 85>;
+ regulator-max-microvolt = <135>;
+ regulator-ramp-delay = <12500>;
+ regulator-always-on;
+ };
+
+ mt6397_vpca7_reg: buck_vpca7 {
+ regulator-compatible = "buck_vpca7";
+ regulator-name = "vpca7";
+ regulator-min-microvolt = < 85>;
+ regulator-max-microvolt = <135>;
+ regulator-ramp-delay = <12500>;
+ regulator-always-on;
+ };
+
+ mt6397_vsramca15_reg: buck_vsramca15 {
+ regulator-compatible = "buck_vsramca15";
+ regulator-name = "vsramca15";
+ regulator-min-microvolt = < 85>;
+ regulator-max-microvolt = <135>;
+ regulator-ramp-delay = <12500>;
+ regulator-always-on;
+ };
+
+ mt6397_vsramca7_reg: buck_vsramca7 {
+ regulator-compatible = "buck_vsramca7";
+ regulator-name = "vsramca7";
+ regulator-min-microvolt = < 85>;
+ regulator-max-microvolt = <135>;
+ regulator-ramp-delay = <12500>;
+ regulator-always-on;
+ };
+
+ mt6397_vcore_reg: buck_vcore {
+ regulator-compatible = "buck_vcore";
+ regulator-name = "vcore";
+ regulator-min-microvolt = < 85>;
+ regulator-max-microvolt = <135>;
+ regulator-ramp-delay = <12500>;
+ regulator-always-on;
+ };
+
+ mt6397_vgpu_reg: buck_vgpu {
+ regulator-compatible = "buck_vgpu";
+ regulator-name = "vgpu";
+ regulator-min-microvolt = < 70>;
+ regulator-max-microvolt = <135>;
+ regulator-ramp-delay = <12500>;
+ regulator-enable-ramp-delay = <115>;
+ };
+
+ mt6397_vdrm_reg: buck_vdrm {
+ regulator-compatible = "buck_vdrm";
+ regulator-name = "vdrm";
+ regulator-min-microvolt = <120>;
+ regulator-max-microvolt = <140>;
+ regulator-ramp-delay = <12500>;
+ regulator-always-on;
+ };
+
+ mt6397_vio18_reg: buck_vio18 {
+ regulator-compatible = "buck_vio18";
+ regulator-name = "vio18";
+ regulator-min-microvolt = <162>;
+ regulator-max-microvolt = <198>;
+ regulator-ramp-delay = <12500>;
+ regulator-always-on;
+ };
+
+ mt6397_vtcxo_reg: ldo_vtcxo {
+ regulator-compatible = "ldo_vtcxo";
+
[PATCH v4 5/6] arm: dts: mt8135: Add support for MT8135 PMIC wrapper
Add device tree for MT8135 PMIC wrapper in mt8135.dtsi.
Signed-off-by: Flora Fu
---
arch/arm/boot/dts/mt8135.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi
index ec83e69..ab08063 100644
--- a/arch/arm/boot/dts/mt8135.dtsi
+++ b/arch/arm/boot/dts/mt8135.dtsi
@@ -117,6 +117,20 @@
reg = <0 0x10200030 0 0x1c>;
};
+ pwrap: pwrap@1000f000 {
+ compatible = "mediatek,mt8135-pwrap";
+ reg = <0 0x1000f000 0 0x1000>,
+ <0 0x11017000 0 0x1000>;
+ reg-names = "pwrap-base", "pwrap-bridge-base";
+ interrupts = ;
+ resets = < MT8135_INFRA_PMIC_WRAP_RST>,
+ <
MT8135_PERI_PWRAP_BRIDGE_SW_RST>;
+ reset-names = "infra-pwrap-rst",
+ "peri-pwrap-bridge-rst";
+ clocks = < TOP_PMICSPI_SEL>, <> ;
+ clock-names = "pmicspi-sel", "pmicspi-parent";
+ };
+
gic: interrupt-controller@10211000 {
compatible = "arm,cortex-a15-gic";
interrupt-controller;
--
1.8.1.1.dirty
--
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[PATCH v4 0/6] Add Support for MediaTek PMIC MT6397 MFD Core and Regulator
Hi, The patch sets add support for MediaTek PMIC MT6397 MFD core and its regulator driver. This is hardware layout for access PMIC MT6397 from AP SoC MT8135. Between PMIC MT6397 and MT8135, the physical signal channel is SPI bus. A specific hardware called PMIC Wrapper or PWRAP to handle access protocols in both PMIC and AP side. +-+ +---+ | | | | | Mediatek AP SoC | | | | (ex. MT8135)| |MT6397 | | | | | | ++ | (SPI bus) | ++| | || |---| ||| | | PMIC | |---| | PMIC || | | Wrapper| |---| | Wrapper|| | || |---| ||| | ++ | | ++| | | | | +-+ +---+ This driver is based on kernel release 3.19. Changes since v3 (1) Patch 1/6: PMIC Wrapper is the parent of MT6397 MFD. Use auxdata to pass regmap pointer as MFD's platform data. (2) Patch 2/6: Update MT6397 MFD implmentation according to patch 1/6. Update MFD cells table: rtc, codec, clock for sub modules. (3) Patch 4/6: Document for MT8135 PMIC wrapper. (4) Patch 5/6: Document for MT6397 MFD. (5) Patch 7/6: Device tree for MT8135 PMIC wrapper in mt8135.dtsi. - nodes of clocks depend on mt8135 clocks - nodes of resets depend on mt8135 reset controllers: https://lkml.org/lkml/2014/11/3/134 https://lkml.org/lkml/2014/11/5/283 (6) Patch 6/6: Add device tree for MT6397 MFD and regulators in mt8135 board file. v3: https://lkml.org/lkml/2014/12/4/924 Changes since v2 (1) Patch 1/8: Update kernel config of MT8135 PMIC Wrapper. It needs to select REGMAP. (2) Patch 2/8: Update patch of MT6397 MFD driver to fix defeat of coding styles. (3) Patch 3/8: Update MT6397 regulator driver - use standard helpers for ops ".set_voltage_sel", ".get_voltage_sel" and ".is_enabled" - remove regulator's DT matching codes in the driver. - fix defeat of coding styles. (4) Patch 4/8: Update document for MT8135 PMIC wrapper. (5) Patch 5/8: Update document for MT6397 MFD. (6) Patch 6/8: Update document for MT6397 regulators. (7) Patch 7/8: Update device tree for MT8135 PMIC wrapper in mt8135.dtsi. (8) Patch 8/8: Add device tree for MT6397 MFD and regulators in mt8135-evbp1.dts board file. v2: http://lists.infradead.org/pipermail/linux-arm-kernel/2014-November/307069.html Changes since v1 (1) Patch 1/8: Add MT8135 PMIC wrapper driver for SoC's proprietary hardware. (2) Patch 2/8: Update patch of MT6397 MFD driver to contain only MFD related codes and fix defeat of coding styles. (3) Patch 3/8: Update MT6397 regulator driver - use helpers and standard ways for specifying data in regulator description. - add more comments to explaining why the driver implement its own regulator_ops for ".is_enabled", ".set_voltage_sel" and ".get_voltage_sel". - update driver implement for coding styles. (4) Patch 4/8: Add document for MT8135 PMIC wrapper. (5) Patch 5/8: Update document for MT6397 MFD. (6) Patch 6/8: Update document for MT6397 regulators. (7) Patch 7/8: Add device tree for MT6397 MFD in mt8135.dtsi. (8) Patch 8/8: Update device tree for MT6397 regulators in mt8135.dtsi. Initial version (v1): http://lists.infradead.org/pipermail/linux-arm-kernel/2014-November/302984.html Flora Fu (6): soc: mediatek: Add PMIC wrapper for MT8135 and MT6397 SoC mfd: MT6397: Add support for PMIC MT6397 MFD dt-bindings:: Add document for MT8135 PMIC Wrapper dt-bindings: Add document for MT6397 MFD arm: dts: mt8135: Add support for MT8135 PMIC wrapper arm: dts: mt8135: Add support for MT6397 MFD and regulator Documentation/devicetree/bindings/mfd/mt6397.txt | 75 ++ .../soc/mediatek/mediatek,mt8135-pwrap.txt | 51 ++ arch/arm/boot/dts/mt8135-evbp1.dts | 193 + arch/arm/boot/dts/mt8135.dtsi | 14 + drivers/mfd/Kconfig| 10 + drivers/mfd/Makefile | 1 + drivers/mfd/mt6397-core.c | 94 +++ drivers/soc/Kconfig| 1 + drivers/soc/Makefile | 1 + drivers/soc/mediatek/Kconfig | 12 + drivers/soc/mediatek/Makefile | 1 + drivers/soc/mediatek/mt8135-pmic-wrap.c| 855 + drivers/soc/mediatek/mt8135-pmic-wrap.h| 138 include/linux/mfd/mt6397/core.h| 23 + include/linux/mfd/mt6397/registers.h | 362 + 15 files c
[PATCH v4 0/6] Add Support for MediaTek PMIC MT6397 MFD Core and Regulator
Hi, The patch sets add support for MediaTek PMIC MT6397 MFD core and its regulator driver. This is hardware layout for access PMIC MT6397 from AP SoC MT8135. Between PMIC MT6397 and MT8135, the physical signal channel is SPI bus. A specific hardware called PMIC Wrapper or PWRAP to handle access protocols in both PMIC and AP side. +-+ +---+ | | | | | Mediatek AP SoC | | | | (ex. MT8135)| |MT6397 | | | | | | ++ | (SPI bus) | ++| | || |---| ||| | | PMIC | |---| | PMIC || | | Wrapper| |---| | Wrapper|| | || |---| ||| | ++ | | ++| | | | | +-+ +---+ This driver is based on kernel release 3.19. Changes since v3 (1) Patch 1/6: PMIC Wrapper is the parent of MT6397 MFD. Use auxdata to pass regmap pointer as MFD's platform data. (2) Patch 2/6: Update MT6397 MFD implmentation according to patch 1/6. Update MFD cells table: rtc, codec, clock for sub modules. (3) Patch 4/6: Document for MT8135 PMIC wrapper. (4) Patch 5/6: Document for MT6397 MFD. (5) Patch 7/6: Device tree for MT8135 PMIC wrapper in mt8135.dtsi. - nodes of clocks depend on mt8135 clocks - nodes of resets depend on mt8135 reset controllers: https://lkml.org/lkml/2014/11/3/134 https://lkml.org/lkml/2014/11/5/283 (6) Patch 6/6: Add device tree for MT6397 MFD and regulators in mt8135 board file. v3: https://lkml.org/lkml/2014/12/4/924 Changes since v2 (1) Patch 1/8: Update kernel config of MT8135 PMIC Wrapper. It needs to select REGMAP. (2) Patch 2/8: Update patch of MT6397 MFD driver to fix defeat of coding styles. (3) Patch 3/8: Update MT6397 regulator driver - use standard helpers for ops .set_voltage_sel, .get_voltage_sel and .is_enabled - remove regulator's DT matching codes in the driver. - fix defeat of coding styles. (4) Patch 4/8: Update document for MT8135 PMIC wrapper. (5) Patch 5/8: Update document for MT6397 MFD. (6) Patch 6/8: Update document for MT6397 regulators. (7) Patch 7/8: Update device tree for MT8135 PMIC wrapper in mt8135.dtsi. (8) Patch 8/8: Add device tree for MT6397 MFD and regulators in mt8135-evbp1.dts board file. v2: http://lists.infradead.org/pipermail/linux-arm-kernel/2014-November/307069.html Changes since v1 (1) Patch 1/8: Add MT8135 PMIC wrapper driver for SoC's proprietary hardware. (2) Patch 2/8: Update patch of MT6397 MFD driver to contain only MFD related codes and fix defeat of coding styles. (3) Patch 3/8: Update MT6397 regulator driver - use helpers and standard ways for specifying data in regulator description. - add more comments to explaining why the driver implement its own regulator_ops for .is_enabled, .set_voltage_sel and .get_voltage_sel. - update driver implement for coding styles. (4) Patch 4/8: Add document for MT8135 PMIC wrapper. (5) Patch 5/8: Update document for MT6397 MFD. (6) Patch 6/8: Update document for MT6397 regulators. (7) Patch 7/8: Add device tree for MT6397 MFD in mt8135.dtsi. (8) Patch 8/8: Update device tree for MT6397 regulators in mt8135.dtsi. Initial version (v1): http://lists.infradead.org/pipermail/linux-arm-kernel/2014-November/302984.html Flora Fu (6): soc: mediatek: Add PMIC wrapper for MT8135 and MT6397 SoC mfd: MT6397: Add support for PMIC MT6397 MFD dt-bindings:: Add document for MT8135 PMIC Wrapper dt-bindings: Add document for MT6397 MFD arm: dts: mt8135: Add support for MT8135 PMIC wrapper arm: dts: mt8135: Add support for MT6397 MFD and regulator Documentation/devicetree/bindings/mfd/mt6397.txt | 75 ++ .../soc/mediatek/mediatek,mt8135-pwrap.txt | 51 ++ arch/arm/boot/dts/mt8135-evbp1.dts | 193 + arch/arm/boot/dts/mt8135.dtsi | 14 + drivers/mfd/Kconfig| 10 + drivers/mfd/Makefile | 1 + drivers/mfd/mt6397-core.c | 94 +++ drivers/soc/Kconfig| 1 + drivers/soc/Makefile | 1 + drivers/soc/mediatek/Kconfig | 12 + drivers/soc/mediatek/Makefile | 1 + drivers/soc/mediatek/mt8135-pmic-wrap.c| 855 + drivers/soc/mediatek/mt8135-pmic-wrap.h| 138 include/linux/mfd/mt6397/core.h| 23 + include/linux/mfd/mt6397/registers.h | 362 + 15 files changed, 1831 insertions(+) create mode 100644 Documentation/devicetree/bindings
[PATCH v4 6/6] arm: dts: mt8135: Add support for MT6397 MFD and regulator
Add device tree for MT6397 MFD and regulator in mt8135 evb board file.
Signed-off-by: Flora Fu flora...@mediatek.com
---
arch/arm/boot/dts/mt8135-evbp1.dts | 193 +
1 file changed, 193 insertions(+)
diff --git a/arch/arm/boot/dts/mt8135-evbp1.dts
b/arch/arm/boot/dts/mt8135-evbp1.dts
index a5adf97..3be2c8b 100644
--- a/arch/arm/boot/dts/mt8135-evbp1.dts
+++ b/arch/arm/boot/dts/mt8135-evbp1.dts
@@ -23,3 +23,196 @@
reg = 0 0x8000 0 0x4000;
};
};
+
+pwrap {
+ pmic: mt6397 {
+ compatible = mediatek,mt6397;
+
+ mt6397regulator: mt6397regulator {
+ compatible = mediatek,mt6397-regulator;
+
+ mt6397_vpca15_reg: buck_vpca15 {
+ regulator-compatible = buck_vpca15;
+ regulator-name = vpca15;
+ regulator-min-microvolt = 85;
+ regulator-max-microvolt = 135;
+ regulator-ramp-delay = 12500;
+ regulator-always-on;
+ };
+
+ mt6397_vpca7_reg: buck_vpca7 {
+ regulator-compatible = buck_vpca7;
+ regulator-name = vpca7;
+ regulator-min-microvolt = 85;
+ regulator-max-microvolt = 135;
+ regulator-ramp-delay = 12500;
+ regulator-always-on;
+ };
+
+ mt6397_vsramca15_reg: buck_vsramca15 {
+ regulator-compatible = buck_vsramca15;
+ regulator-name = vsramca15;
+ regulator-min-microvolt = 85;
+ regulator-max-microvolt = 135;
+ regulator-ramp-delay = 12500;
+ regulator-always-on;
+ };
+
+ mt6397_vsramca7_reg: buck_vsramca7 {
+ regulator-compatible = buck_vsramca7;
+ regulator-name = vsramca7;
+ regulator-min-microvolt = 85;
+ regulator-max-microvolt = 135;
+ regulator-ramp-delay = 12500;
+ regulator-always-on;
+ };
+
+ mt6397_vcore_reg: buck_vcore {
+ regulator-compatible = buck_vcore;
+ regulator-name = vcore;
+ regulator-min-microvolt = 85;
+ regulator-max-microvolt = 135;
+ regulator-ramp-delay = 12500;
+ regulator-always-on;
+ };
+
+ mt6397_vgpu_reg: buck_vgpu {
+ regulator-compatible = buck_vgpu;
+ regulator-name = vgpu;
+ regulator-min-microvolt = 70;
+ regulator-max-microvolt = 135;
+ regulator-ramp-delay = 12500;
+ regulator-enable-ramp-delay = 115;
+ };
+
+ mt6397_vdrm_reg: buck_vdrm {
+ regulator-compatible = buck_vdrm;
+ regulator-name = vdrm;
+ regulator-min-microvolt = 120;
+ regulator-max-microvolt = 140;
+ regulator-ramp-delay = 12500;
+ regulator-always-on;
+ };
+
+ mt6397_vio18_reg: buck_vio18 {
+ regulator-compatible = buck_vio18;
+ regulator-name = vio18;
+ regulator-min-microvolt = 162;
+ regulator-max-microvolt = 198;
+ regulator-ramp-delay = 12500;
+ regulator-always-on;
+ };
+
+ mt6397_vtcxo_reg: ldo_vtcxo {
+ regulator-compatible = ldo_vtcxo;
+ regulator-name = vtcxo;
+ regulator-always-on;
+ };
+
+ mt6397_va28_reg: ldo_va28 {
+ regulator-compatible = ldo_va28;
+ regulator-name = va28;
+ regulator-always-on;
+ };
+
+ mt6397_vcama_reg: ldo_vcama
[PATCH v4 5/6] arm: dts: mt8135: Add support for MT8135 PMIC wrapper
Add device tree for MT8135 PMIC wrapper in mt8135.dtsi.
Signed-off-by: Flora Fu flora...@mediatek.com
---
arch/arm/boot/dts/mt8135.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi
index ec83e69..ab08063 100644
--- a/arch/arm/boot/dts/mt8135.dtsi
+++ b/arch/arm/boot/dts/mt8135.dtsi
@@ -117,6 +117,20 @@
reg = 0 0x10200030 0 0x1c;
};
+ pwrap: pwrap@1000f000 {
+ compatible = mediatek,mt8135-pwrap;
+ reg = 0 0x1000f000 0 0x1000,
+ 0 0x11017000 0 0x1000;
+ reg-names = pwrap-base, pwrap-bridge-base;
+ interrupts = GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH;
+ resets = infrarst MT8135_INFRA_PMIC_WRAP_RST,
+ perirst
MT8135_PERI_PWRAP_BRIDGE_SW_RST;
+ reset-names = infra-pwrap-rst,
+ peri-pwrap-bridge-rst;
+ clocks = topckgen TOP_PMICSPI_SEL, clk26m ;
+ clock-names = pmicspi-sel, pmicspi-parent;
+ };
+
gic: interrupt-controller@10211000 {
compatible = arm,cortex-a15-gic;
interrupt-controller;
--
1.8.1.1.dirty
--
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[PATCH v4 3/6] dt-bindings:: Add document for MT8135 PMIC Wrapper
Signed-off-by: Flora Fu flora...@mediatek.com
---
.../soc/mediatek/mediatek,mt8135-pwrap.txt | 51 ++
1 file changed, 51 insertions(+)
create mode 100644
Documentation/devicetree/bindings/soc/mediatek/mediatek,mt8135-pwrap.txt
diff --git
a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mt8135-pwrap.txt
b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mt8135-pwrap.txt
new file mode 100644
index 000..d630fa0
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mt8135-pwrap.txt
@@ -0,0 +1,51 @@
+MediaTek MT8135 PMIC Wrapper Driver
+
+MediaTek PMIC MFD is interfaced to host controller using SPI interface
+by a proprietary hardware called PMIC wrapper or pwrap.
+
++-+ +---+
+| | | |
+| Mediatek AP SoC | | |
+| (ex. MT8135)| |MT6397 |
+| | | |
+| ++ | (SPI bus) | ++|
+| || |---| |||
+| | PMIC | |---| | PMIC ||
+| | Wrapper| |---| | Wrapper||
+| || |---| |||
+| ++ | | ++|
+| | | |
++-+ +---+
+
+This document describes the binding for MT8135 PMIC wrapper.
+
+Required properties in pwrap device node.
+- compatible:mediatek,mt8135-pwrap
+- interrupts: IRQ for pwrap in SOC
+- reg: address range for pwrap registers
+- resets: reset bit for pwrap
+- clock: clock frequency selection in SPI bus
+
+Optional properities:
+- pmic: Mediatek PMIC MFD is the child device of pwrap
+ See the following for child node definitions:
+ Documentation/devicetree/bindings/mfd/mt6397.txt
+
+Example:
+ pwrap: pwrap@1000f000 {
+ compatible = mediatek,mt8135-pwrap;
+ reg = 0 0x1000f000 0 0x1000,
+ 0 0x11017000 0 0x1000;
+ reg-names = pwrap-base, pwrap-bridge-base;
+ interrupts = GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH;
+ resets = infrarst MT8135_INFRA_PMIC_WRAP_RST,
+ perirst MT8135_PERI_PWRAP_BRIDGE_SW_RST;
+ reset-names = infra-pwrap-rst,
+ peri-pwrap-bridge-rst;
+ clocks = pmicspi_sel, clk26m;
+ clock-names = pmicspi-sel, pmicspi-parent;
+
+ pmic {
+ compatible = mediatek,mt6397;
+ };
+ };
--
1.8.1.1.dirty
--
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[PATCH v4 4/6] dt-bindings: Add document for MT6397 MFD
Signed-off-by: Flora Fu flora...@mediatek.com
---
Documentation/devicetree/bindings/mfd/mt6397.txt | 75
1 file changed, 75 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mfd/mt6397.txt
diff --git a/Documentation/devicetree/bindings/mfd/mt6397.txt
b/Documentation/devicetree/bindings/mfd/mt6397.txt
new file mode 100644
index 000..64ef408
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/mt6397.txt
@@ -0,0 +1,75 @@
+MediaTek MT6397 Multifunction Device Driver
+
+MT6397 is a multifunction device with the following sub modules:
+- Regulator
+- RTC
+- Audio codec
+- GPIO
+- Clock
+
+It is interfaced to host controller using SPI interface by a proprietary
hardware
+called PMIC wrapper or pwrap. MT6397 MFD is a child device of pwrap.
+See the following for pwarp node definitions:
+Documentation/devicetree/bindings/soc/mediatek,mt8135-pwrap.txt
+
+This document describes the binding for mfd device and its sub module.
+
+Required properties:
+compatible: mediatek,mt6397
+
+Optional properties:
+- codec: Audio codec
+- pinctrl: GPIO in mt6397
+- rtc: RTC
+- clock: clocks in mt6397
+- regulators: regulators in mt6397
+
+Example:
+ pwrap: pwrap@1000f000 {
+ compatible = mediatek,mt8135-pwrap;
+ reg = 0 0x1000f000 0 0x1000,
+ 0 0x11017000 0 0x1000;
+ reg-names = pwrap-base, pwrap-bridge-base;
+ interrupts = GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH;
+ resets = infrarst MT8135_INFRA_PMIC_WRAP_RST,
+ perirst MT8135_PERI_PWRAP_BRIDGE_SW_RST;
+ reset-names = infra-pwrap-rst,
+ peri-pwrap-bridge-rst;
+ clocks = pmicspi_sel, clk26m;
+ clock-names = pmicspi-sel, pmicspi-parent;
+
+ pmic {
+ compatible = mediatek,mt6397;
+
+ codec: mt6397codec {
+ compatible = mediatek,mt6397-codec;
+ };
+
+ pinctrl@0xC000 {
+ compatible = mediatek,mt6397-pinctrl;
+ reg = 0 0xC000 0 0x0108;
+ gpio-controller;
+ };
+
+ mt6397regulator: mt6397regulator {
+ compatible = mediatek,mt6397-regulator;
+
+ mt6397_vpca15_reg: buck_vpca15 {
+ regulator-compatible = buck_vpca15;
+ regulator-name = vpca15;
+ regulator-min-microvolt = 85;
+ regulator-max-microvolt = 140;
+ regulator-ramp-delay = 12500;
+ regulator-always-on;
+ };
+
+ mt6397_vgp4_reg: ldo_vgp4 {
+ regulator-compatible = ldo_vgp4;
+ regulator-name = vgp4;
+ regulator-min-microvolt = 120;
+ regulator-max-microvolt = 330;
+ regulator-enable-ramp-delay = 218;
+ };
+ };
+ };
+ };
--
1.8.1.1.dirty
--
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[PATCH v4 2/6] mfd: MT6397: Add support for PMIC MT6397 MFD
Add core files for MT6397 MFD driver.
Signed-off-by: Flora Fu flora...@mediatek.com
---
drivers/mfd/Kconfig | 10 +
drivers/mfd/Makefile | 1 +
drivers/mfd/mt6397-core.c| 94 +
include/linux/mfd/mt6397/core.h | 23 +++
include/linux/mfd/mt6397/registers.h | 362 +++
5 files changed, 490 insertions(+)
create mode 100644 drivers/mfd/mt6397-core.c
create mode 100644 include/linux/mfd/mt6397/core.h
create mode 100644 include/linux/mfd/mt6397/registers.h
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 2e6b731..7782e95 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -489,6 +489,16 @@ config MFD_MAX8998
additional drivers must be enabled in order to use the functionality
of the device.
+config MFD_MT6397
+ tristate MediaTek MT6397 PMIC Support
+ select MFD_CORE
+ select IRQ_DOMAIN
+ help
+ Say yes here to add support for MediaTek MT6397 PMIC. This is
+ a Power Management IC. This driver provides common support for
+ accessing the device; additional drivers must be enabled in order
+ to use the functionality of the device.
+
config MFD_MENF21BMC
tristate MEN 14F021P00 Board Management Controller Support
depends on I2C
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 53467e2..329d4ed 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -179,3 +179,4 @@ obj-$(CONFIG_MFD_DLN2) += dln2.o
intel-soc-pmic-objs:= intel_soc_pmic_core.o intel_soc_pmic_crc.o
obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o
+obj-$(CONFIG_MFD_MT6397) += mt6397-core.o
diff --git a/drivers/mfd/mt6397-core.c b/drivers/mfd/mt6397-core.c
new file mode 100644
index 000..45ce01a
--- /dev/null
+++ b/drivers/mfd/mt6397-core.c
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Flora Fu flora...@mediatek.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/module.h
+#include linux/of_device.h
+#include linux/mfd/core.h
+#include linux/mfd/mt6397/core.h
+
+static const struct mfd_cell mt6397_devs[] = {
+ {
+ .name = mt6397-rtc,
+ .of_compatible = mediatek,mt6397-rtc,
+ },
+ {
+ .name = mt6397-regulator,
+ .of_compatible = mediatek,mt6397-regulator,
+ },
+ {
+ .name = mt6397-codec,
+ .of_compatible = mediatek,mt6397-codec,
+ },
+ {
+ .name = mt6397-clk,
+ .of_compatible = mediatek,mt6397-clk,
+ },
+};
+
+static int mt6397_probe(struct platform_device *pdev)
+{
+ int ret;
+ struct mt6397_chip *mt6397;
+
+ mt6397 = devm_kzalloc(pdev-dev, sizeof(*mt6397), GFP_KERNEL);
+ if (!mt6397)
+ return -ENOMEM;
+
+ mt6397-dev = pdev-dev;
+ /*
+* mt6397 MFD is child device of soc pmic wrapper.
+* Regmap is set from its parent.
+*/
+ mt6397-regmap = dev_get_platdata(pdev-dev);
+ if (!mt6397-regmap)
+ return -ENODEV;
+
+ platform_set_drvdata(pdev, mt6397);
+
+ ret = mfd_add_devices(pdev-dev, -1, mt6397_devs,
+ ARRAY_SIZE(mt6397_devs), NULL, 0, NULL);
+ if (ret)
+ dev_err(pdev-dev, failed to add child devices: %d\n, ret);
+
+ return ret;
+}
+
+static int mt6397_remove(struct platform_device *pdev)
+{
+ mfd_remove_devices(pdev-dev);
+
+ return 0;
+}
+
+static const struct of_device_id mt6397_of_match[] = {
+ { .compatible = mediatek,mt6397 },
+ { }
+};
+MODULE_DEVICE_TABLE(of, mt6397_of_match);
+
+static struct platform_driver mt6397_driver = {
+ .probe = mt6397_probe,
+ .remove = mt6397_remove,
+ .driver = {
+ .name = mt6397,
+ .of_match_table = of_match_ptr(mt6397_of_match),
+ },
+};
+
+module_platform_driver(mt6397_driver);
+
+MODULE_AUTHOR(Flora Fu flora...@mediatek.com);
+MODULE_DESCRIPTION(Driver for MediaTek MT6397 PMIC);
+MODULE_LICENSE(GPL);
+MODULE_ALIAS(platform:mt6397);
diff --git a/include/linux/mfd/mt6397/core.h b/include/linux/mfd/mt6397/core.h
new file mode 100644
index 000..567164e
--- /dev/null
+++ b/include/linux/mfd/mt6397/core.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Flora Fu flora...@mediatek.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General
[PATCH v4 1/6] soc: mediatek: Add PMIC wrapper for MT8135 and MT6397 SoC
Add PMIC wrapper of MT8135 to access MT6397 MFD.
Signed-off-by: Flora Fu flora...@mediatek.com
---
drivers/soc/Kconfig | 1 +
drivers/soc/Makefile| 1 +
drivers/soc/mediatek/Kconfig| 12 +
drivers/soc/mediatek/Makefile | 1 +
drivers/soc/mediatek/mt8135-pmic-wrap.c | 855
drivers/soc/mediatek/mt8135-pmic-wrap.h | 138 ++
6 files changed, 1008 insertions(+)
create mode 100644 drivers/soc/mediatek/Kconfig
create mode 100644 drivers/soc/mediatek/Makefile
create mode 100644 drivers/soc/mediatek/mt8135-pmic-wrap.c
create mode 100644 drivers/soc/mediatek/mt8135-pmic-wrap.h
diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
index 76d6bd4..d8bde82 100644
--- a/drivers/soc/Kconfig
+++ b/drivers/soc/Kconfig
@@ -1,5 +1,6 @@
menu SOC (System On Chip) specific Drivers
+source drivers/soc/mediatek/Kconfig
source drivers/soc/qcom/Kconfig
source drivers/soc/ti/Kconfig
source drivers/soc/versatile/Kconfig
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index 063113d..70042b2 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -2,6 +2,7 @@
# Makefile for the Linux Kernel SOC specific device drivers.
#
+obj-$(CONFIG_ARCH_MEDIATEK)+= mediatek/
obj-$(CONFIG_ARCH_QCOM)+= qcom/
obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-$(CONFIG_SOC_TI) += ti/
diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
new file mode 100644
index 000..746e030
--- /dev/null
+++ b/drivers/soc/mediatek/Kconfig
@@ -0,0 +1,12 @@
+#
+# MediaTek SoC drivers
+#
+config MT8135_PMIC_WRAP
+ tristate MediaTek MT8135 PMIC Wrapper Support
+ depends on ARCH_MEDIATEK
+ select REGMAP
+ help
+ Say yes here to add support for MediaTek MT8135 PMIC Wrapper.
+ PMIC wrapper is a proprietary hardware in MT8135 to make
+ communication protocols to access PMIC device.
+ This driver implement access protocols for MT8135.
diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
new file mode 100644
index 000..49b9588
--- /dev/null
+++ b/drivers/soc/mediatek/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_MT8135_PMIC_WRAP) += mt8135-pmic-wrap.o
diff --git a/drivers/soc/mediatek/mt8135-pmic-wrap.c
b/drivers/soc/mediatek/mt8135-pmic-wrap.c
new file mode 100644
index 000..3c35afc
--- /dev/null
+++ b/drivers/soc/mediatek/mt8135-pmic-wrap.c
@@ -0,0 +1,855 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Flora Fu flora...@mediatek.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/clk.h
+#include linux/interrupt.h
+#include linux/io.h
+#include linux/kernel.h
+#include linux/module.h
+#include linux/of_device.h
+#include linux/platform_device.h
+#include linux/regmap.h
+#include linux/reset.h
+#include linux/mfd/mt6397/registers.h
+#include mt8135-pmic-wrap.h
+
+/* macro for wrapper status */
+#define PWRAP_GET_WACS0_WDATA(x) (((x) 0) 0x)
+#define PWRAP_GET_WACS0_ADR(x) (((x) 16) 0x7fff)
+#define PWRAP_GET_WACS0_WRITE(x) (((x) 31) 0x0001)
+#define PWRAP_GET_WACS0_RDATA(x) (((x) 0) 0x)
+#define PWRAP_GET_WACS0_FSM(x) (((x) 16) 0x0007)
+#define PWRAP_STATE_SYNC_IDLE0 (1 20)
+#define PWRAP_STATE_INIT_DONE0 (1 21)
+
+/* macro for WACS FSM */
+#define PWRAP_WACS_FSM_IDLE0x00
+#define PWRAP_WACS_FSM_REQ 0x02
+#define PWRAP_WACS_FSM_WFDLE 0x04
+#define PWRAP_WACS_FSM_WFVLDCLR0x06
+#define PWRAP_WACS_INIT_DONE 0x01
+#define PWRAP_WACS_WACS_SYNC_IDLE 0x01
+
+/* macro for device wrapper default value */
+#define PWRAP_DEW_READ_TEST_VAL0x5aa5
+#define PWRAP_DEW_WRITE_TEST_VAL 0xa55a
+
+/* macro for manual command */
+#define PWRAP_OP_WR0x1
+#define PWRAP_OP_RD0x0
+#define PWRAP_OP_CSH 0x0
+#define PWRAP_OP_CSL 0x1
+#define PWRAP_OP_OUTS 0x8
+#define PWRAP_OP_OUTD 0x9
+#define PWRAP_OP_OUTQ 0xA
+
+struct pmic_wrapper {
+ struct platform_device *pdev;
+ void __iomem *pwrap_base;
+ void __iomem *pwrap_bridge_base;
+ struct regmap *regmap;
+};
+
+static bool is_fsm_idle(u32 x)
+{
+ return PWRAP_GET_WACS0_FSM(x) == PWRAP_WACS_FSM_IDLE;
+}
+
+static bool is_fsm_vldclr(u32 x)
+{
+ return PWRAP_GET_WACS0_FSM(x) == PWRAP_WACS_FSM_WFVLDCLR;
+}
+
+static bool
Re: [PATCH RESEND v2] mfd: syscon: add child device support
Hi,
The patch set is used to implement reset controller in
http://lists.infradead.org/pipermail/linux-arm-kernel/2014-November/299141.html
Tested-by: Flora Fu
Thanks,
Flora
On Mon, 2014-12-15 at 09:58 +, Lee Jones wrote:
> On Mon, 15 Dec 2014, Philipp Zabel wrote:
> > Am Montag, den 01.12.2014, 17:25 +0100 schrieb Philipp Zabel:
> > > For devices which have a complete register for themselves, it is possible
> > > to
> > > place them next to the syscon device with overlapping reg ranges. The
> > > same is
> > > not possible for devices which only occupy bitfields in registers shared
> > > with
> > > other users.
> > > For devices that are completely controlled by bitfields in the syscon
> > > address
> > > range, such as multiplexers or voltage regulators, allow to put child
> > > devices
> > > into the syscon device node.
> >
> > What is the status of this patch?
> > Is this ok to be applied after the merge window closes?
> >
> > For reference, these are the previous threads:
> > https://lkml.org/lkml/2014/5/27/422
> > https://lkml.org/lkml/2014/11/3/134
>
> As this is such an important driver I need more Acks for users/testers
> and senior reviewers before applying.
>
> > > Signed-off-by: Philipp Zabel
> > > ---
> > > Changes since v1:
> > > - Reworded binding documentation to allow #size-cells = <1>, which is
> > > useful
> > >for syscon children that are controlled through a (possibly shared)
> > > register
> > >range.
> > > ---
> > > Documentation/devicetree/bindings/mfd/syscon.txt | 13 +
> > > drivers/mfd/syscon.c | 3 +++
> > > 2 files changed, 16 insertions(+)
> > >
> > > diff --git a/Documentation/devicetree/bindings/mfd/syscon.txt
> > > b/Documentation/devicetree/bindings/mfd/syscon.txt
> > > index fe8150b..0c6b497 100644
> > > --- a/Documentation/devicetree/bindings/mfd/syscon.txt
> > > +++ b/Documentation/devicetree/bindings/mfd/syscon.txt
> > > @@ -9,12 +9,25 @@ using a specific compatible value), interrogate the
> > > node (or associated
> > > OS driver) to determine the location of the registers, and access the
> > > registers directly.
> > >
> > > +Optionally, devices that are controlled exclusively through syscon
> > > registers,
> > > +or even bitfields in shared syscon registers, can also be added as child
> > > nodes
> > > +to the syscon device node. These devices can implicitly assume their
> > > parent
> > > +node is a syscon provider without referencing it explicitly via phandle.
> > > +In this case, the syscon node should have #address-cells = <1> and
> > > +#size-cells = <0> or <1> and no ranges property.
> > > +
> > > Required properties:
> > > - compatible: Should contain "syscon".
> > > - reg: the register region can be accessed from syscon
> > >
> > > +Optional properties:
> > > +- #address-cells: Should be 1.
> > > +- #size-cells: Should be 0 or 1.
> > > +
> > > Examples:
> > > gpr: iomuxc-gpr@020e {
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
> > > reg = <0x020e 0x38>;
> > > };
> > > diff --git a/drivers/mfd/syscon.c b/drivers/mfd/syscon.c
> > > index ca15878..38da178 100644
> > > --- a/drivers/mfd/syscon.c
> > > +++ b/drivers/mfd/syscon.c
> > > @@ -155,6 +155,9 @@ static int syscon_probe(struct platform_device *pdev)
> > >
> > > dev_dbg(dev, "regmap %pR registered\n", res);
> > >
> > > + if (!of_device_is_compatible(pdev->dev.of_node, "simple-bus"))
> > > + of_platform_populate(pdev->dev.of_node, NULL, NULL, >dev);
> > > +
> > > return 0;
> > > }
> > >
> >
> >
>
--
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Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH RESEND v2] mfd: syscon: add child device support
Hi,
The patch set is used to implement reset controller in
http://lists.infradead.org/pipermail/linux-arm-kernel/2014-November/299141.html
Tested-by: Flora Fu flora...@mediatek.com
Thanks,
Flora
On Mon, 2014-12-15 at 09:58 +, Lee Jones wrote:
On Mon, 15 Dec 2014, Philipp Zabel wrote:
Am Montag, den 01.12.2014, 17:25 +0100 schrieb Philipp Zabel:
For devices which have a complete register for themselves, it is possible
to
place them next to the syscon device with overlapping reg ranges. The
same is
not possible for devices which only occupy bitfields in registers shared
with
other users.
For devices that are completely controlled by bitfields in the syscon
address
range, such as multiplexers or voltage regulators, allow to put child
devices
into the syscon device node.
What is the status of this patch?
Is this ok to be applied after the merge window closes?
For reference, these are the previous threads:
https://lkml.org/lkml/2014/5/27/422
https://lkml.org/lkml/2014/11/3/134
As this is such an important driver I need more Acks for users/testers
and senior reviewers before applying.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
Changes since v1:
- Reworded binding documentation to allow #size-cells = 1, which is
useful
for syscon children that are controlled through a (possibly shared)
register
range.
---
Documentation/devicetree/bindings/mfd/syscon.txt | 13 +
drivers/mfd/syscon.c | 3 +++
2 files changed, 16 insertions(+)
diff --git a/Documentation/devicetree/bindings/mfd/syscon.txt
b/Documentation/devicetree/bindings/mfd/syscon.txt
index fe8150b..0c6b497 100644
--- a/Documentation/devicetree/bindings/mfd/syscon.txt
+++ b/Documentation/devicetree/bindings/mfd/syscon.txt
@@ -9,12 +9,25 @@ using a specific compatible value), interrogate the
node (or associated
OS driver) to determine the location of the registers, and access the
registers directly.
+Optionally, devices that are controlled exclusively through syscon
registers,
+or even bitfields in shared syscon registers, can also be added as child
nodes
+to the syscon device node. These devices can implicitly assume their
parent
+node is a syscon provider without referencing it explicitly via phandle.
+In this case, the syscon node should have #address-cells = 1 and
+#size-cells = 0 or 1 and no ranges property.
+
Required properties:
- compatible: Should contain syscon.
- reg: the register region can be accessed from syscon
+Optional properties:
+- #address-cells: Should be 1.
+- #size-cells: Should be 0 or 1.
+
Examples:
gpr: iomuxc-gpr@020e {
+ #address-cells = 1;
+ #size-cells = 0;
compatible = fsl,imx6q-iomuxc-gpr, syscon;
reg = 0x020e 0x38;
};
diff --git a/drivers/mfd/syscon.c b/drivers/mfd/syscon.c
index ca15878..38da178 100644
--- a/drivers/mfd/syscon.c
+++ b/drivers/mfd/syscon.c
@@ -155,6 +155,9 @@ static int syscon_probe(struct platform_device *pdev)
dev_dbg(dev, regmap %pR registered\n, res);
+ if (!of_device_is_compatible(pdev-dev.of_node, simple-bus))
+ of_platform_populate(pdev-dev.of_node, NULL, NULL, pdev-dev);
+
return 0;
}
--
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Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v3 1/8] soc: mediatek: Add PMIC wrapper for MT8135 and MT6397 SoC
Hi, On Tue, 2014-12-09 at 12:20 +0100, Arnd Bergmann wrote: > On Tuesday 09 December 2014 11:30:15 Matthias Brugger wrote: > > 2014-12-09 11:13 GMT+01:00 Sascha Hauer : > > > On Tue, Dec 09, 2014 at 09:23:18AM +0100, Arnd Bergmann wrote: > > >> > > >> I think we have had a similar case recently where a controller wasn't > > >> actually using I2C, but the sofware protocol was close enough so we > > >> decided > > >> to make it appear as i2c in Linux. > > >> > > >> Would that work for you, i.e. register the pmic wrapper as a fake spi > > >> master driver in drivers/spi/ and register the rtc/regulator/codec > > >> as SPI clients from DT? > > > > > > I don't think that's appropriate. I mean technically that could even > > > work, but in software you really don't see anything from the underlying > > > SPI bus. The SoC and the PMIC are really tightly coupled via the PMIC > > > wrapper. This goes to the point where pins of the SoCs internal I2C and > > > keypad controllers are routed over the SPI bus out of the PMIC. In > > > software you do this by setting a bit in the I2C controller. If it's > > > set, the signals are routed out of the PMIC instead of the main die. > > > As said, technically we probably could create a fake SPI master, but > > > that wouldn't really fit to this situation. > > Ok, I see. > > > I agree with Sascha. Although from the hardware point of view, the > > communication between the PMIC and the SOC is done through SPI from > > the point of view of the software everything looks like I2C commands > > which will be "transalted" into SPI messages by the PMIC wrapper. > > If it looks like i2c messages, would it be more appropriate to make > it appear as an i2c controller then? Although the message looks like I2C command, it is not I2C. Form source code, the software does not touch any I2C i/o or protocols. It depends SoC and has specific initial flow, read and write transfer state. It is not able to an i2c controller. That's why we consider its a proprietary hardware with specific protocols. How about let it appear in driver/soc? Thanks, Flora -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v3 1/8] soc: mediatek: Add PMIC wrapper for MT8135 and MT6397 SoC
Hi, On Tue, 2014-12-09 at 12:20 +0100, Arnd Bergmann wrote: On Tuesday 09 December 2014 11:30:15 Matthias Brugger wrote: 2014-12-09 11:13 GMT+01:00 Sascha Hauer s.ha...@pengutronix.de: On Tue, Dec 09, 2014 at 09:23:18AM +0100, Arnd Bergmann wrote: I think we have had a similar case recently where a controller wasn't actually using I2C, but the sofware protocol was close enough so we decided to make it appear as i2c in Linux. Would that work for you, i.e. register the pmic wrapper as a fake spi master driver in drivers/spi/ and register the rtc/regulator/codec as SPI clients from DT? I don't think that's appropriate. I mean technically that could even work, but in software you really don't see anything from the underlying SPI bus. The SoC and the PMIC are really tightly coupled via the PMIC wrapper. This goes to the point where pins of the SoCs internal I2C and keypad controllers are routed over the SPI bus out of the PMIC. In software you do this by setting a bit in the I2C controller. If it's set, the signals are routed out of the PMIC instead of the main die. As said, technically we probably could create a fake SPI master, but that wouldn't really fit to this situation. Ok, I see. I agree with Sascha. Although from the hardware point of view, the communication between the PMIC and the SOC is done through SPI from the point of view of the software everything looks like I2C commands which will be transalted into SPI messages by the PMIC wrapper. If it looks like i2c messages, would it be more appropriate to make it appear as an i2c controller then? Although the message looks like I2C command, it is not I2C. Form source code, the software does not touch any I2C i/o or protocols. It depends SoC and has specific initial flow, read and write transfer state. It is not able to an i2c controller. That's why we consider its a proprietary hardware with specific protocols. How about let it appear in driver/soc? Thanks, Flora -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v3 1/8] soc: mediatek: Add PMIC wrapper for MT8135 and MT6397 SoC
Hi, Arnd, On Fri, 2014-12-05 at 11:13 +0100, Arnd Bergmann wrote: > On Friday 05 December 2014 12:07:52 Flora Fu wrote: > > Add PMIC wrapper of MT8135 to access MT6397 MFD. > > > > Signed-off-by: Flora Fu > > > > Please explain what a PMIC wrapper is and why you need one for MT8135. > I don't understand the purpose of this code at all. Is this just another > way of accessing the MT6397 when not using i2c or spi like other > PMIC drivers do? > Yes, MT8135 uses a proprietary hardware to communicate with MT6397. The hardware is called PMIC Wrapper or PWRAP. Since it is not standard i2c or spi protocols, a soc related software driver is implemented to handle access protocols in AP side. +-+ +---+ | | | | | Mediatek AP SoC | | | | (ex. MT8135)| |MT6397 | | | | | | ++ | (SPI bus) | ++| | || |---| ||| | | PMIC | |---| | PMIC || | | Wrapper| |---| | Wrapper|| | || |---| ||| | ++ | | ++| | | | | +-+ +---+ Thanks, Flora -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v3 1/8] soc: mediatek: Add PMIC wrapper for MT8135 and MT6397 SoC
Hi, Arnd, On Fri, 2014-12-05 at 11:13 +0100, Arnd Bergmann wrote: On Friday 05 December 2014 12:07:52 Flora Fu wrote: Add PMIC wrapper of MT8135 to access MT6397 MFD. Signed-off-by: Flora Fu flora...@mediatek.com Please explain what a PMIC wrapper is and why you need one for MT8135. I don't understand the purpose of this code at all. Is this just another way of accessing the MT6397 when not using i2c or spi like other PMIC drivers do? Yes, MT8135 uses a proprietary hardware to communicate with MT6397. The hardware is called PMIC Wrapper or PWRAP. Since it is not standard i2c or spi protocols, a soc related software driver is implemented to handle access protocols in AP side. +-+ +---+ | | | | | Mediatek AP SoC | | | | (ex. MT8135)| |MT6397 | | | | | | ++ | (SPI bus) | ++| | || |---| ||| | | PMIC | |---| | PMIC || | | Wrapper| |---| | Wrapper|| | || |---| ||| | ++ | | ++| | | | | +-+ +---+ Thanks, Flora -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v3 3/8] regulator: MT6397: Add support for MT6397 regulator
Add MT6397 regulator driver.
Signed-off-by: Flora Fu
---
drivers/regulator/Kconfig | 9 +
drivers/regulator/Makefile | 1 +
drivers/regulator/mt6397-regulator.c | 332 +
include/linux/regulator/mt6397-regulator.h | 49 +
4 files changed, 391 insertions(+)
create mode 100644 drivers/regulator/mt6397-regulator.c
create mode 100644 include/linux/regulator/mt6397-regulator.h
diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index 55d7b7b..38a8d84 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -433,6 +433,15 @@ config REGULATOR_MC13892
Say y here to support the regulators found on the Freescale MC13892
PMIC.
+config REGULATOR_MT6397
+ tristate "MediaTek MT6397 PMIC"
+ depends on MFD_MT6397
+ help
+ Say y here to select this option to enable the power regulator of
+ MediaTek MT6397 PMIC.
+ This driver supports the control of different power rails of device
+ through regulator interface.
+
config REGULATOR_PALMAS
tristate "TI Palmas PMIC Regulators"
depends on MFD_PALMAS
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index 1029ed3..bad280e 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -58,6 +58,7 @@ obj-$(CONFIG_REGULATOR_MAX77802) += max77802.o
obj-$(CONFIG_REGULATOR_MC13783) += mc13783-regulator.o
obj-$(CONFIG_REGULATOR_MC13892) += mc13892-regulator.o
obj-$(CONFIG_REGULATOR_MC13XXX_CORE) += mc13xxx-regulator-core.o
+obj-$(CONFIG_REGULATOR_MT6397) += mt6397-regulator.o
obj-$(CONFIG_REGULATOR_QCOM_RPM) += qcom_rpm-regulator.o
obj-$(CONFIG_REGULATOR_PALMAS) += palmas-regulator.o
obj-$(CONFIG_REGULATOR_PFUZE100) += pfuze100-regulator.o
diff --git a/drivers/regulator/mt6397-regulator.c
b/drivers/regulator/mt6397-regulator.c
new file mode 100644
index 000..a5b2f47
--- /dev/null
+++ b/drivers/regulator/mt6397-regulator.c
@@ -0,0 +1,332 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Flora Fu
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/*
+ * MT6397 regulators' information
+ *
+ * @desc: standard fields of regulator description.
+ * @qi: Mask for query enable signal status of regulators
+ * @vselon_reg: Register sections for hardware control mode of bucks
+ * @vselctrl_reg: Register for controlling the buck control mode.
+ * @vselctrl_mask: Mask for query buck's voltage control mode.
+ */
+struct mt6397_regulator_info {
+ struct regulator_desc desc;
+ u32 qi;
+ u32 vselon_reg;
+ u32 vselctrl_reg;
+ u32 vselctrl_mask;
+};
+
+#define MT6397_BUCK(match, vreg, min, max, step, volt_ranges, enreg, \
+ vosel, vosel_mask, voselon, vosel_ctrl) \
+[MT6397_ID_##vreg] = { \
+ .desc = { \
+ .name = #vreg, \
+ .of_match = of_match_ptr(match),\
+ .ops = _volt_range_ops, \
+ .type = REGULATOR_VOLTAGE, \
+ .id = MT6397_ID_##vreg, \
+ .owner = THIS_MODULE, \
+ .n_voltages = (max - min)/step + 1, \
+ .linear_ranges = volt_ranges, \
+ .n_linear_ranges = ARRAY_SIZE(volt_ranges), \
+ .vsel_reg = vosel, \
+ .vsel_mask = vosel_mask,\
+ .enable_reg = enreg,\
+ .enable_mask = BIT(0), \
+ }, \
+ .qi = BIT(13), \
+ .vselon_reg = voselon, \
+ .vselctrl_reg = vosel_ctrl, \
+ .vselctrl_mask = BIT(1),\
+}
+
+#define MT6397_LDO(match, vreg, ldo_volt_table, enreg, enbit, vosel, \
+ vosel_mask)
[PATCH v3 1/8] soc: mediatek: Add PMIC wrapper for MT8135 and MT6397 SoC
Add PMIC wrapper of MT8135 to access MT6397 MFD.
Signed-off-by: Flora Fu
---
drivers/soc/Kconfig| 1 +
drivers/soc/Makefile | 1 +
drivers/soc/mediatek/Kconfig | 12 +
drivers/soc/mediatek/Makefile | 1 +
drivers/soc/mediatek/mt8135-pmic-wrap.c| 844 +
drivers/soc/mediatek/mt8135-pmic-wrap.h| 138 +
include/linux/soc/mediatek/mtk-pmic-wrap.h | 25 +
7 files changed, 1022 insertions(+)
create mode 100644 drivers/soc/mediatek/Kconfig
create mode 100644 drivers/soc/mediatek/Makefile
create mode 100644 drivers/soc/mediatek/mt8135-pmic-wrap.c
create mode 100644 drivers/soc/mediatek/mt8135-pmic-wrap.h
create mode 100644 include/linux/soc/mediatek/mtk-pmic-wrap.h
diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
index 76d6bd4..d8bde82 100644
--- a/drivers/soc/Kconfig
+++ b/drivers/soc/Kconfig
@@ -1,5 +1,6 @@
menu "SOC (System On Chip) specific Drivers"
+source "drivers/soc/mediatek/Kconfig"
source "drivers/soc/qcom/Kconfig"
source "drivers/soc/ti/Kconfig"
source "drivers/soc/versatile/Kconfig"
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index 063113d..70042b2 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -2,6 +2,7 @@
# Makefile for the Linux Kernel SOC specific device drivers.
#
+obj-$(CONFIG_ARCH_MEDIATEK)+= mediatek/
obj-$(CONFIG_ARCH_QCOM)+= qcom/
obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-$(CONFIG_SOC_TI) += ti/
diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
new file mode 100644
index 000..746e030
--- /dev/null
+++ b/drivers/soc/mediatek/Kconfig
@@ -0,0 +1,12 @@
+#
+# MediaTek SoC drivers
+#
+config MT8135_PMIC_WRAP
+ tristate "MediaTek MT8135 PMIC Wrapper Support"
+ depends on ARCH_MEDIATEK
+ select REGMAP
+ help
+ Say yes here to add support for MediaTek MT8135 PMIC Wrapper.
+ PMIC wrapper is a proprietary hardware in MT8135 to make
+ communication protocols to access PMIC device.
+ This driver implement access protocols for MT8135.
diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
new file mode 100644
index 000..49b9588
--- /dev/null
+++ b/drivers/soc/mediatek/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_MT8135_PMIC_WRAP) += mt8135-pmic-wrap.o
diff --git a/drivers/soc/mediatek/mt8135-pmic-wrap.c
b/drivers/soc/mediatek/mt8135-pmic-wrap.c
new file mode 100644
index 000..75aa28e
--- /dev/null
+++ b/drivers/soc/mediatek/mt8135-pmic-wrap.c
@@ -0,0 +1,844 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Flora Fu
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "mt8135-pmic-wrap.h"
+
+/* macro for wrapper status */
+#define PWRAP_GET_WACS0_WDATA(x) (((x) >> 0) & 0x)
+#define PWRAP_GET_WACS0_ADR(x) (((x) >> 16) & 0x7fff)
+#define PWRAP_GET_WACS0_WRITE(x) (((x) >> 31) & 0x0001)
+#define PWRAP_GET_WACS0_RDATA(x) (((x) >> 0) & 0x)
+#define PWRAP_GET_WACS0_FSM(x) (((x) >> 16) & 0x0007)
+#define PWRAP_STATE_SYNC_IDLE0 (1 << 20)
+#define PWRAP_STATE_INIT_DONE0 (1 << 21)
+
+/* macro for WACS FSM */
+#define PWRAP_WACS_FSM_IDLE0x00
+#define PWRAP_WACS_FSM_REQ 0x02
+#define PWRAP_WACS_FSM_WFDLE 0x04
+#define PWRAP_WACS_FSM_WFVLDCLR0x06
+#define PWRAP_WACS_INIT_DONE 0x01
+#define PWRAP_WACS_WACS_SYNC_IDLE 0x01
+
+/* macro for device wrapper default value */
+#define PWRAP_DEW_READ_TEST_VAL0x5aa5
+#define PWRAP_DEW_WRITE_TEST_VAL 0xa55a
+
+/* macro for manual command */
+#define PWRAP_OP_WR0x1
+#define PWRAP_OP_RD0x0
+#define PWRAP_OP_CSH 0x0
+#define PWRAP_OP_CSL 0x1
+#define PWRAP_OP_OUTS 0x8
+#define PWRAP_OP_OUTD 0x9
+#define PWRAP_OP_OUTQ 0xA
+
+static bool is_fsm_idle(u32 x)
+{
+ return PWRAP_GET_WACS0_FSM(x) == PWRAP_WACS_FSM_IDLE;
+}
+
+static bool is_fsm_vldclr(u32 x)
+{
+ return PWRAP_GET_WACS0_FSM(x) == PWRAP_WACS_FSM_WFVLDCLR;
+}
+
+static bool is_sync_idle(u32 x)
+{
+ return x & PWRAP_STATE_SYNC_ID
[PATCH v3 4/8] dt-bindings:: Add document for MT8135 PMIC Wrapper
Signed-off-by: Flora Fu
---
.../soc/mediatek/mediatek,mt8135-pwrap.txt | 51 ++
1 file changed, 51 insertions(+)
create mode 100644
Documentation/devicetree/bindings/soc/mediatek/mediatek,mt8135-pwrap.txt
diff --git
a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mt8135-pwrap.txt
b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mt8135-pwrap.txt
new file mode 100644
index 000..d630fa0
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mt8135-pwrap.txt
@@ -0,0 +1,51 @@
+MediaTek MT8135 PMIC Wrapper Driver
+
+MediaTek PMIC MFD is interfaced to host controller using SPI interface
+by a proprietary hardware called PMIC wrapper or pwrap.
+
++-+ +---+
+| | | |
+| Mediatek AP SoC | | |
+| (ex. MT8135)| |MT6397 |
+| | | |
+| ++ | (SPI bus) | ++|
+| || |---| |||
+| | PMIC | |---| | PMIC ||
+| | Wrapper| |---| | Wrapper||
+| || |---| |||
+| ++ | | ++|
+| | | |
++-+ +---+
+
+This document describes the binding for MT8135 PMIC wrapper.
+
+Required properties in pwrap device node.
+- compatible:"mediatek,mt8135-pwrap"
+- interrupts: IRQ for pwrap in SOC
+- reg: address range for pwrap registers
+- resets: reset bit for pwrap
+- clock: clock frequency selection in SPI bus
+
+Optional properities:
+- pmic: Mediatek PMIC MFD is the child device of pwrap
+ See the following for child node definitions:
+ Documentation/devicetree/bindings/mfd/mt6397.txt
+
+Example:
+ pwrap: pwrap@1000f000 {
+ compatible = "mediatek,mt8135-pwrap";
+ reg = <0 0x1000f000 0 0x1000>,
+ <0 0x11017000 0 0x1000>;
+ reg-names = "pwrap-base", "pwrap-bridge-base";
+ interrupts = ;
+ resets = < MT8135_INFRA_PMIC_WRAP_RST>,
+ < MT8135_PERI_PWRAP_BRIDGE_SW_RST>;
+ reset-names = "infra-pwrap-rst",
+ "peri-pwrap-bridge-rst";
+ clocks = <_sel>, <>;
+ clock-names = "pmicspi-sel", "pmicspi-parent";
+
+ pmic {
+ compatible = "mediatek,mt6397";
+ };
+ };
--
1.8.1.1.dirty
--
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Please read the FAQ at http://www.tux.org/lkml/
[PATCH v3 7/8] ARM: dts: mt8135: Add support for MT8135 PMIC wrapper
Add device tree for MT8135 PMIC wrapper in mt8135.dtsi.
Signed-off-by: Flora Fu
---
arch/arm/boot/dts/mt8135.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi
index 90a56ad..86b1326 100644
--- a/arch/arm/boot/dts/mt8135.dtsi
+++ b/arch/arm/boot/dts/mt8135.dtsi
@@ -102,6 +102,20 @@
clock-names = "system-clk", "rtc-clk";
};
+ pwrap: pwrap@1000f000 {
+ compatible = "mediatek,mt8135-pwrap";
+ reg = <0 0x1000f000 0 0x1000>,
+ <0 0x11017000 0 0x1000>;
+ reg-names = "pwrap-base", "pwrap-bridge-base";
+ interrupts = ;
+ resets = < MT8135_INFRA_PMIC_WRAP_RST>,
+ <
MT8135_PERI_PWRAP_BRIDGE_SW_RST>;
+ reset-names = "infra-pwrap-rst",
+ "peri-pwrap-bridge-rst";
+ clocks = <_sel>, <> ;
+ clock-names = "pmicspi-sel", "pmicspi-parent";
+ };
+
gic: interrupt-controller@10211000 {
compatible = "arm,cortex-a15-gic";
interrupt-controller;
--
1.8.1.1.dirty
--
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[PATCH v3 2/8] mfd: MT6397: Add support for PMIC MT6397 MFD
Add core files for MT6397 MFD driver.
Signed-off-by: Flora Fu
---
drivers/mfd/Kconfig | 10 +
drivers/mfd/Makefile | 1 +
drivers/mfd/mt6397-core.c| 87 +
include/linux/mfd/mt6397/core.h | 23 +++
include/linux/mfd/mt6397/registers.h | 362 +++
5 files changed, 483 insertions(+)
create mode 100644 drivers/mfd/mt6397-core.c
create mode 100644 include/linux/mfd/mt6397/core.h
create mode 100644 include/linux/mfd/mt6397/registers.h
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 1456ea7..f0b3efc 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -1318,6 +1318,16 @@ config MFD_STW481X
in various ST Microelectronics and ST-Ericsson embedded
Nomadik series.
+config MFD_MT6397
+ tristate "MediaTek MT6397 PMIC Support"
+ select MFD_CORE
+ select IRQ_DOMAIN
+ help
+ Say yes here to add support for MediaTek MT6397 PMIC. This is
+ a Power Management IC. This driver provides common support for
+ accessing the device; additional drivers must be enabled in order
+ to use the functionality of the device.
+
menu "Multimedia Capabilities Port drivers"
depends on ARCH_SA1100
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 8bd54b1..7168193 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -177,3 +177,4 @@ obj-$(CONFIG_MFD_HI6421_PMIC) += hi6421-pmic-core.o
intel-soc-pmic-objs:= intel_soc_pmic_core.o intel_soc_pmic_crc.o
obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o
+obj-$(CONFIG_MFD_MT6397) += mt6397-core.o
diff --git a/drivers/mfd/mt6397-core.c b/drivers/mfd/mt6397-core.c
new file mode 100644
index 000..85631e0
--- /dev/null
+++ b/drivers/mfd/mt6397-core.c
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Flora Fu
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+static const struct mfd_cell mt6397_devs[] = {
+ { .name = "mt6397-rtc" },
+ {
+ .name = "mt6397-regulator",
+ .of_compatible = "mediatek,mt6397-regulator",
+ },
+ {
+ .name = "mt6397-codec",
+ .of_compatible = "mediatek,mt6397-codec",
+ },
+};
+
+static int mt6397_probe(struct platform_device *pdev)
+{
+ u32 ret;
+ struct mt6397_chip *mt6397;
+ struct pmic_wrapper *wrp;
+
+ /* mt6397 MFD is child device of soc pmic wrapper. */
+ if (!pdev->dev.parent)
+ return -ENODEV;
+
+ wrp = dev_get_drvdata(pdev->dev.parent);
+ mt6397 = devm_kzalloc(>dev, sizeof(*mt6397), GFP_KERNEL);
+ if (!mt6397)
+ return -ENOMEM;
+
+ mt6397->dev = >dev;
+ mt6397->regmap = wrp->regmap;
+ platform_set_drvdata(pdev, mt6397);
+
+ ret = mfd_add_devices(>dev, -1, _devs[0],
+ ARRAY_SIZE(mt6397_devs), NULL, 0, NULL);
+ if (ret)
+ dev_err(>dev, "failed to add child devices: %d\n", ret);
+
+ return ret;
+}
+
+static int mt6397_remove(struct platform_device *pdev)
+{
+ mfd_remove_devices(>dev);
+
+ return 0;
+}
+
+static const struct of_device_id mt6397_of_match[] = {
+ { .compatible = "mediatek,mt6397" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, mt6397_of_match);
+
+static struct platform_driver mt6397_driver = {
+ .probe = mt6397_probe,
+ .remove = mt6397_remove,
+ .driver = {
+ .name = "mt6397",
+ .of_match_table = of_match_ptr(mt6397_of_match),
+ },
+};
+
+module_platform_driver(mt6397_driver);
+
+MODULE_AUTHOR("Flora Fu ");
+MODULE_DESCRIPTION("Driver for MediaTek MT6397 PMIC");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:mt6397");
diff --git a/include/linux/mfd/mt6397/core.h b/include/linux/mfd/mt6397/core.h
new file mode 100644
index 000..567164e
--- /dev/null
+++ b/include/linux/mfd/mt6397/core.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Flora Fu
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANT
[PATCH v3 5/8] dt-bindings: Add document for MT6397 MFD
Signed-off-by: Flora Fu
---
Documentation/devicetree/bindings/mfd/mt6397.txt | 75
1 file changed, 75 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mfd/mt6397.txt
diff --git a/Documentation/devicetree/bindings/mfd/mt6397.txt
b/Documentation/devicetree/bindings/mfd/mt6397.txt
new file mode 100644
index 000..64ef408
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/mt6397.txt
@@ -0,0 +1,75 @@
+MediaTek MT6397 Multifunction Device Driver
+
+MT6397 is a multifunction device with the following sub modules:
+- Regulator
+- RTC
+- Audio codec
+- GPIO
+- Clock
+
+It is interfaced to host controller using SPI interface by a proprietary
hardware
+called PMIC wrapper or pwrap. MT6397 MFD is a child device of pwrap.
+See the following for pwarp node definitions:
+Documentation/devicetree/bindings/soc/mediatek,mt8135-pwrap.txt
+
+This document describes the binding for mfd device and its sub module.
+
+Required properties:
+compatible: "mediatek,mt6397"
+
+Optional properties:
+- codec: Audio codec
+- pinctrl: GPIO in mt6397
+- rtc: RTC
+- clock: clocks in mt6397
+- regulators: regulators in mt6397
+
+Example:
+ pwrap: pwrap@1000f000 {
+ compatible = "mediatek,mt8135-pwrap";
+ reg = <0 0x1000f000 0 0x1000>,
+ <0 0x11017000 0 0x1000>;
+ reg-names = "pwrap-base", "pwrap-bridge-base";
+ interrupts = ;
+ resets = < MT8135_INFRA_PMIC_WRAP_RST>,
+ < MT8135_PERI_PWRAP_BRIDGE_SW_RST>;
+ reset-names = "infra-pwrap-rst",
+ "peri-pwrap-bridge-rst";
+ clocks = <_sel>, <>;
+ clock-names = "pmicspi-sel", "pmicspi-parent";
+
+ pmic {
+ compatible = "mediatek,mt6397";
+
+ codec: mt6397codec {
+ compatible = "mediatek,mt6397-codec";
+ };
+
+ pinctrl@0xC000 {
+ compatible = "mediatek,mt6397-pinctrl";
+ reg = <0 0xC000 0 0x0108>;
+ gpio-controller;
+ };
+
+ mt6397regulator: mt6397regulator {
+ compatible = "mediatek,mt6397-regulator";
+
+ mt6397_vpca15_reg: buck_vpca15 {
+ regulator-compatible = "buck_vpca15";
+ regulator-name = "vpca15";
+ regulator-min-microvolt = < 85>;
+ regulator-max-microvolt = <140>;
+ regulator-ramp-delay = <12500>;
+ regulator-always-on;
+ };
+
+ mt6397_vgp4_reg: ldo_vgp4 {
+ regulator-compatible = "ldo_vgp4";
+ regulator-name = "vgp4";
+ regulator-min-microvolt = <120>;
+ regulator-max-microvolt = <330>;
+ regulator-enable-ramp-delay = <218>;
+ };
+ };
+ };
+ };
--
1.8.1.1.dirty
--
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[PATCH v3 8/8] ARM: dts: mt8135: Add support for MT6397 MFD and regulator
Add device tree for MT6397 MFD and regulator in mt8135-evbp1.dts board file
Signed-off-by: Flora Fu
---
arch/arm/boot/dts/mt8135-evbp1.dts | 193 +
1 file changed, 193 insertions(+)
diff --git a/arch/arm/boot/dts/mt8135-evbp1.dts
b/arch/arm/boot/dts/mt8135-evbp1.dts
index cba80b8..627cc47 100644
--- a/arch/arm/boot/dts/mt8135-evbp1.dts
+++ b/arch/arm/boot/dts/mt8135-evbp1.dts
@@ -22,3 +22,196 @@
reg = <0 0x8000 0 0x4000>;
};
};
+
+ {
+ pmic {
+ compatible = "mediatek,mt6397";
+
+ mt6397regulator: mt6397regulator {
+ compatible = "mediatek,mt6397-regulator";
+
+ mt6397_vpca15_reg: buck_vpca15 {
+ regulator-compatible = "buck_vpca15";
+ regulator-name = "vpca15";
+ regulator-min-microvolt = < 85>;
+ regulator-max-microvolt = <135>;
+ regulator-ramp-delay = <12500>;
+ regulator-always-on;
+ };
+
+ mt6397_vpca7_reg: buck_vpca7 {
+ regulator-compatible = "buck_vpca7";
+ regulator-name = "vpca7";
+ regulator-min-microvolt = < 85>;
+ regulator-max-microvolt = <135>;
+ regulator-ramp-delay = <12500>;
+ regulator-always-on;
+ };
+
+ mt6397_vsramca15_reg: buck_vsramca15 {
+ regulator-compatible = "buck_vsramca15";
+ regulator-name = "vsramca15";
+ regulator-min-microvolt = < 85>;
+ regulator-max-microvolt = <135>;
+ regulator-ramp-delay = <12500>;
+ regulator-always-on;
+ };
+
+ mt6397_vsramca7_reg: buck_vsramca7 {
+ regulator-compatible = "buck_vsramca7";
+ regulator-name = "vsramca7";
+ regulator-min-microvolt = < 85>;
+ regulator-max-microvolt = <135>;
+ regulator-ramp-delay = <12500>;
+ regulator-always-on;
+ };
+
+ mt6397_vcore_reg: buck_vcore {
+ regulator-compatible = "buck_vcore";
+ regulator-name = "vcore";
+ regulator-min-microvolt = < 85>;
+ regulator-max-microvolt = <135>;
+ regulator-ramp-delay = <12500>;
+ regulator-always-on;
+ };
+
+ mt6397_vgpu_reg: buck_vgpu {
+ regulator-compatible = "buck_vgpu";
+ regulator-name = "vgpu";
+ regulator-min-microvolt = < 70>;
+ regulator-max-microvolt = <135>;
+ regulator-ramp-delay = <12500>;
+ regulator-enable-ramp-delay = <115>;
+ };
+
+ mt6397_vdrm_reg: buck_vdrm {
+ regulator-compatible = "buck_vdrm";
+ regulator-name = "vdrm";
+ regulator-min-microvolt = <120>;
+ regulator-max-microvolt = <140>;
+ regulator-ramp-delay = <12500>;
+ regulator-always-on;
+ };
+
+ mt6397_vio18_reg: buck_vio18 {
+ regulator-compatible = "buck_vio18";
+ regulator-name = "vio18";
+ regulator-min-microvolt = <162>;
+ regulator-max-microvolt = <198>;
+ regulator-ramp-delay = <12500>;
+ regulator-always-on;
+ };
+
+ mt6397_vtcxo_reg: ldo_vtcxo {
+ regulator-compatible = "ldo_vtcxo";
+
[PATCH v3 6/8] dt-bindings: Add document for MT6397 regulator
Signed-off-by: Flora Fu
---
.../bindings/regulator/mt6397-regulator.txt| 217 +
1 file changed, 217 insertions(+)
create mode 100644
Documentation/devicetree/bindings/regulator/mt6397-regulator.txt
diff --git a/Documentation/devicetree/bindings/regulator/mt6397-regulator.txt
b/Documentation/devicetree/bindings/regulator/mt6397-regulator.txt
new file mode 100644
index 000..a42b1d6
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/mt6397-regulator.txt
@@ -0,0 +1,217 @@
+Mediatek MT6397 Regulator Driver
+
+Required properties:
+- compatible: "mediatek,mt6397-regulator"
+- mt6397regulator: List of regulators provided by this controller. It is named
+ according to its regulator type, buck_ and ldo_.
+ The definition for each of these nodes is defined using the standard binding
+ for regulators at Documentation/devicetree/bindings/regulator/regulator.txt.
+
+The valid names for regulators are::
+BUCK:
+ buck_vpca15, buck_vpca7, buck_vsramca15, buck_vsramca7, buck_vcore,
buck_vgpu,
+ buck_vdrm, buck_vio18
+LDO:
+ ldo_vtcxo, ldo_va28, ldo_vcama, ldo_vio28, ldo_vusb, ldo_vmc, ldo_vmch,
+ ldo_vemc3v3, ldo_vgp1, ldo_vgp2, ldo_vgp3, ldo_vgp4, ldo_vgp5, ldo_vgp6,
+ ldo_vibr
+
+Example:
+ pmic {
+ compatible = "mediatek,mt6397";
+
+ mt6397regulator: mt6397regulator {
+ compatible = "mediatek,mt6397-regulator";
+
+ mt6397_vpca15_reg: buck_vpca15 {
+ regulator-compatible = "buck_vpca15";
+ regulator-name = "vpca15";
+ regulator-min-microvolt = < 85>;
+ regulator-max-microvolt = <135>;
+ regulator-ramp-delay = <12500>;
+ regulator-enable-ramp-delay = <200>;
+ };
+
+ mt6397_vpca7_reg: buck_vpca7 {
+ regulator-compatible = "buck_vpca7";
+ regulator-name = "vpca7";
+ regulator-min-microvolt = < 85>;
+ regulator-max-microvolt = <135>;
+ regulator-ramp-delay = <12500>;
+ regulator-enable-ramp-delay = <115>;
+ };
+
+ mt6397_vsramca15_reg: buck_vsramca15 {
+ regulator-compatible = "buck_vsramca15";
+ regulator-name = "vsramca15";
+ regulator-min-microvolt = < 85>;
+ regulator-max-microvolt = <135>;
+ regulator-ramp-delay = <12500>;
+ regulator-enable-ramp-delay = <115>;
+
+ };
+
+ mt6397_vsramca7_reg: buck_vsramca7 {
+ regulator-compatible = "buck_vsramca7";
+ regulator-name = "vsramca7";
+ regulator-min-microvolt = < 85>;
+ regulator-max-microvolt = <135>;
+ regulator-ramp-delay = <12500>;
+ regulator-enable-ramp-delay = <115>;
+
+ };
+
+ mt6397_vcore_reg: buck_vcore {
+ regulator-compatible = "buck_vcore";
+ regulator-name = "vcore";
+ regulator-min-microvolt = < 85>;
+ regulator-max-microvolt = <135>;
+ regulator-ramp-delay = <12500>;
+ regulator-enable-ramp-delay = <115>;
+ };
+
+ mt6397_vgpu_reg: buck_vgpu {
+ regulator-compatible = "buck_vgpu";
+ regulator-name = "vgpu";
+ regulator-min-microvolt = < 70>;
+ regulator-max-microvolt = <135>;
+ regulator-ramp-delay = <12500>;
+ regulator-enable-ramp-delay = <115>;
+ };
+
+ mt6397_vdrm_reg: buck_vdrm {
+ regulator-compatible = "buck_vdrm";
+ regulator-name = "vdrm";
+ regulator-min-microvolt = < 80>;
+
[PATCH v3 0/8] Add Support for MediaTek PMIC MT6397 MFD Core and Regulator
Hi, The patch sets add support for MediaTek PMIC MT6397 MFD core and its regulator driver. This is hardware layout for access PMIC MT6397 from AP SoC MT8135. Between PMIC MT6397 and MT8135, the physical signal channel is SPI bus. A specific hardware called PMIC Wrapper or PWRAP to handle access protocols in both PMIC and AP side. +-+ +---+ | | | | | Mediatek AP SoC | | | | (ex. MT8135)| |MT6397 | | | | | | ++ | (SPI bus) | ++| | || |---| ||| | | PMIC | |---| | PMIC || | | Wrapper| |---| | Wrapper|| | || |---| ||| | ++ | | ++| | | | | +-+ +---+ Changes since v2 (1) Patch 1/8: Update kernel config of MT8135 PMIC Wrapper. It needs to select REGMAP. (2) Patch 2/8: Update patch of MT6397 MFD driver to fix defeat of coding styles. (3) Patch 3/8: Update MT6397 regulator driver - use standard helpers for ops ".set_voltage_sel", ".get_voltage_sel" and ".is_enabled" - remove regulator's DT matching codes in the driver. - fix defeat of coding styles. (4) Patch 4/8: Update document for MT8135 PMIC wrapper. (5) Patch 5/8: Update document for MT6397 MFD. (6) Patch 6/8: Update document for MT6397 regulators. (7) Patch 7/8: Update device tree for MT8135 PMIC wrapper in mt8135.dtsi. (8) Patch 8/8: Add device tree for MT6397 MFD and regulators in mt8135-evbp1.dts board file. Second version (v2): http://lists.infradead.org/pipermail/linux-arm-kernel/2014-November/307069.html Changes since v1 (1) Patch 1/8: Add MT8135 PMIC wrapper driver for SoC's proprietary hardware. (2) Patch 2/8: Update patch of MT6397 MFD driver to contain only MFD related codes and fix defeat of coding styles. (3) Patch 3/8: Update MT6397 regulator driver - use helpers and standard ways for specifying data in regulator description. - add more comments to explaining why the driver implement its own regulator_ops for ".is_enabled", ".set_voltage_sel" and ".get_voltage_sel". - update driver implement for coding styles. (4) Patch 4/8: Add document for MT8135 PMIC wrapper. (5) Patch 5/8: Update document for MT6397 MFD. (6) Patch 6/8: Update document for MT6397 regulators. (7) Patch 7/8: Add device tree for MT6397 MFD in mt8135.dtsi. (8) Patch 8/8: Update device tree for MT6397 regulators in mt8135.dtsi. Initial version (v1): http://lists.infradead.org/pipermail/linux-arm-kernel/2014-November/302984.html This driver is based on 3.18-rc1. Flora Fu (8): soc: mediatek: Add PMIC wrapper for MT8135 and MT6397 SoC mfd: MT6397: Add support for PMIC MT6397 MFD regulator: MT6397: Add support for MT6397 regulator dt-bindings:: Add document for MT8135 PMIC Wrapper dt-bindings: Add document for MT6397 MFD dt-bindings: Add document for MT6397 regulator ARM: dts: mt8135: Add support for MT8135 PMIC wrapper ARM: dts: mt8135: Add support for MT6397 MFD and regulator Documentation/devicetree/bindings/mfd/mt6397.txt | 75 ++ .../bindings/regulator/mt6397-regulator.txt| 217 ++ .../soc/mediatek/mediatek,mt8135-pwrap.txt | 51 ++ arch/arm/boot/dts/mt8135-evbp1.dts | 193 + arch/arm/boot/dts/mt8135.dtsi | 14 + drivers/mfd/Kconfig| 10 + drivers/mfd/Makefile | 1 + drivers/mfd/mt6397-core.c | 87 +++ drivers/regulator/Kconfig | 9 + drivers/regulator/Makefile | 1 + drivers/regulator/mt6397-regulator.c | 332 drivers/soc/Kconfig| 1 + drivers/soc/Makefile | 1 + drivers/soc/mediatek/Kconfig | 12 + drivers/soc/mediatek/Makefile | 1 + drivers/soc/mediatek/mt8135-pmic-wrap.c| 844 + drivers/soc/mediatek/mt8135-pmic-wrap.h| 138 include/linux/mfd/mt6397/core.h| 23 + include/linux/mfd/mt6397/registers.h | 362 + include/linux/regulator/mt6397-regulator.h | 49 ++ include/linux/soc/mediatek/mtk-pmic-wrap.h | 25 + 21 files changed, 2446 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/mt6397.txt create mode 100644 Documentation/devicetree/bindings/regulator/mt6397-regulator.txt create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,mt8135-pwrap.txt create mode 100644 drivers/mfd/mt6397-core.c create mode 100644 driv
[PATCH v3 0/8] Add Support for MediaTek PMIC MT6397 MFD Core and Regulator
Hi, The patch sets add support for MediaTek PMIC MT6397 MFD core and its regulator driver. This is hardware layout for access PMIC MT6397 from AP SoC MT8135. Between PMIC MT6397 and MT8135, the physical signal channel is SPI bus. A specific hardware called PMIC Wrapper or PWRAP to handle access protocols in both PMIC and AP side. +-+ +---+ | | | | | Mediatek AP SoC | | | | (ex. MT8135)| |MT6397 | | | | | | ++ | (SPI bus) | ++| | || |---| ||| | | PMIC | |---| | PMIC || | | Wrapper| |---| | Wrapper|| | || |---| ||| | ++ | | ++| | | | | +-+ +---+ Changes since v2 (1) Patch 1/8: Update kernel config of MT8135 PMIC Wrapper. It needs to select REGMAP. (2) Patch 2/8: Update patch of MT6397 MFD driver to fix defeat of coding styles. (3) Patch 3/8: Update MT6397 regulator driver - use standard helpers for ops ".set_voltage_sel", ".get_voltage_sel" and ".is_enabled" - remove regulator's DT matching codes in the driver. - fix defeat of coding styles. (4) Patch 4/8: Update document for MT8135 PMIC wrapper. (5) Patch 5/8: Update document for MT6397 MFD. (6) Patch 6/8: Update document for MT6397 regulators. (7) Patch 7/8: Update device tree for MT8135 PMIC wrapper in mt8135.dtsi. (8) Patch 8/8: Add device tree for MT6397 MFD and regulators in mt8135-evbp1.dts board file. Second version (v2): http://lists.infradead.org/pipermail/linux-arm-kernel/2014-November/307069.html Changes since v1 (1) Patch 1/8: Add MT8135 PMIC wrapper driver for SoC's proprietary hardware. (2) Patch 2/8: Update patch of MT6397 MFD driver to contain only MFD related codes and fix defeat of coding styles. (3) Patch 3/8: Update MT6397 regulator driver - use helpers and standard ways for specifying data in regulator description. - add more comments to explaining why the driver implement its own regulator_ops for ".is_enabled", ".set_voltage_sel" and ".get_voltage_sel". - update driver implement for coding styles. (4) Patch 4/8: Add document for MT8135 PMIC wrapper. (5) Patch 5/8: Update document for MT6397 MFD. (6) Patch 6/8: Update document for MT6397 regulators. (7) Patch 7/8: Add device tree for MT6397 MFD in mt8135.dtsi. (8) Patch 8/8: Update device tree for MT6397 regulators in mt8135.dtsi. Initial version (v1): http://lists.infradead.org/pipermail/linux-arm-kernel/2014-November/302984.html This driver is based on 3.18-rc1. Flora Fu (8): soc: mediatek: Add PMIC wrapper for MT8135 and MT6397 SoC mfd: MT6397: Add support for PMIC MT6397 MFD regulator: MT6397: Add support for MT6397 regulator dt-bindings:: Add document for MT8135 PMIC Wrapper dt-bindings: Add document for MT6397 MFD dt-bindings: Add document for MT6397 regulator ARM: dts: mt8135: Add support for MT8135 PMIC wrapper ARM: dts: mt8135: Add support for MT6397 MFD and regulator Documentation/devicetree/bindings/mfd/mt6397.txt | 75 ++ .../bindings/regulator/mt6397-regulator.txt| 217 ++ .../soc/mediatek/mediatek,mt8135-pwrap.txt | 51 ++ arch/arm/boot/dts/mt8135-evbp1.dts | 193 + arch/arm/boot/dts/mt8135.dtsi | 14 + drivers/mfd/Kconfig| 10 + drivers/mfd/Makefile | 1 + drivers/mfd/mt6397-core.c | 87 +++ drivers/regulator/Kconfig | 9 + drivers/regulator/Makefile | 1 + drivers/regulator/mt6397-regulator.c | 332 drivers/soc/Kconfig| 1 + drivers/soc/Makefile | 1 + drivers/soc/mediatek/Kconfig | 12 + drivers/soc/mediatek/Makefile | 1 + drivers/soc/mediatek/mt8135-pmic-wrap.c| 844 + drivers/soc/mediatek/mt8135-pmic-wrap.h| 138 include/linux/mfd/mt6397/core.h| 23 + include/linux/mfd/mt6397/registers.h | 362 + include/linux/regulator/mt6397-regulator.h | 49 ++ include/linux/soc/mediatek/mtk-pmic-wrap.h | 25 + 21 files changed, 2446 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/mt6397.txt create mode 100644 Documentation/devicetree/bindings/regulator/mt6397-regulator.txt create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,mt8135-pwrap.txt create mode 100644 drivers/mfd/mt6397-core.c create mode 100644 driv
[PATCH v3 0/8] Add Support for MediaTek PMIC MT6397 MFD Core and Regulator
Hi, The patch sets add support for MediaTek PMIC MT6397 MFD core and its regulator driver. This is hardware layout for access PMIC MT6397 from AP SoC MT8135. Between PMIC MT6397 and MT8135, the physical signal channel is SPI bus. A specific hardware called PMIC Wrapper or PWRAP to handle access protocols in both PMIC and AP side. +-+ +---+ | | | | | Mediatek AP SoC | | | | (ex. MT8135)| |MT6397 | | | | | | ++ | (SPI bus) | ++| | || |---| ||| | | PMIC | |---| | PMIC || | | Wrapper| |---| | Wrapper|| | || |---| ||| | ++ | | ++| | | | | +-+ +---+ Changes since v2 (1) Patch 1/8: Update kernel config of MT8135 PMIC Wrapper. It needs to select REGMAP. (2) Patch 2/8: Update patch of MT6397 MFD driver to fix defeat of coding styles. (3) Patch 3/8: Update MT6397 regulator driver - use standard helpers for ops .set_voltage_sel, .get_voltage_sel and .is_enabled - remove regulator's DT matching codes in the driver. - fix defeat of coding styles. (4) Patch 4/8: Update document for MT8135 PMIC wrapper. (5) Patch 5/8: Update document for MT6397 MFD. (6) Patch 6/8: Update document for MT6397 regulators. (7) Patch 7/8: Update device tree for MT8135 PMIC wrapper in mt8135.dtsi. (8) Patch 8/8: Add device tree for MT6397 MFD and regulators in mt8135-evbp1.dts board file. Second version (v2): http://lists.infradead.org/pipermail/linux-arm-kernel/2014-November/307069.html Changes since v1 (1) Patch 1/8: Add MT8135 PMIC wrapper driver for SoC's proprietary hardware. (2) Patch 2/8: Update patch of MT6397 MFD driver to contain only MFD related codes and fix defeat of coding styles. (3) Patch 3/8: Update MT6397 regulator driver - use helpers and standard ways for specifying data in regulator description. - add more comments to explaining why the driver implement its own regulator_ops for .is_enabled, .set_voltage_sel and .get_voltage_sel. - update driver implement for coding styles. (4) Patch 4/8: Add document for MT8135 PMIC wrapper. (5) Patch 5/8: Update document for MT6397 MFD. (6) Patch 6/8: Update document for MT6397 regulators. (7) Patch 7/8: Add device tree for MT6397 MFD in mt8135.dtsi. (8) Patch 8/8: Update device tree for MT6397 regulators in mt8135.dtsi. Initial version (v1): http://lists.infradead.org/pipermail/linux-arm-kernel/2014-November/302984.html This driver is based on 3.18-rc1. Flora Fu (8): soc: mediatek: Add PMIC wrapper for MT8135 and MT6397 SoC mfd: MT6397: Add support for PMIC MT6397 MFD regulator: MT6397: Add support for MT6397 regulator dt-bindings:: Add document for MT8135 PMIC Wrapper dt-bindings: Add document for MT6397 MFD dt-bindings: Add document for MT6397 regulator ARM: dts: mt8135: Add support for MT8135 PMIC wrapper ARM: dts: mt8135: Add support for MT6397 MFD and regulator Documentation/devicetree/bindings/mfd/mt6397.txt | 75 ++ .../bindings/regulator/mt6397-regulator.txt| 217 ++ .../soc/mediatek/mediatek,mt8135-pwrap.txt | 51 ++ arch/arm/boot/dts/mt8135-evbp1.dts | 193 + arch/arm/boot/dts/mt8135.dtsi | 14 + drivers/mfd/Kconfig| 10 + drivers/mfd/Makefile | 1 + drivers/mfd/mt6397-core.c | 87 +++ drivers/regulator/Kconfig | 9 + drivers/regulator/Makefile | 1 + drivers/regulator/mt6397-regulator.c | 332 drivers/soc/Kconfig| 1 + drivers/soc/Makefile | 1 + drivers/soc/mediatek/Kconfig | 12 + drivers/soc/mediatek/Makefile | 1 + drivers/soc/mediatek/mt8135-pmic-wrap.c| 844 + drivers/soc/mediatek/mt8135-pmic-wrap.h| 138 include/linux/mfd/mt6397/core.h| 23 + include/linux/mfd/mt6397/registers.h | 362 + include/linux/regulator/mt6397-regulator.h | 49 ++ include/linux/soc/mediatek/mtk-pmic-wrap.h | 25 + 21 files changed, 2446 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/mt6397.txt create mode 100644 Documentation/devicetree/bindings/regulator/mt6397-regulator.txt create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,mt8135-pwrap.txt create mode 100644 drivers/mfd/mt6397-core.c create mode 100644 drivers/regulator/mt6397-regulator.c create mode 100644 drivers/soc/mediatek
[PATCH v3 0/8] Add Support for MediaTek PMIC MT6397 MFD Core and Regulator
Hi, The patch sets add support for MediaTek PMIC MT6397 MFD core and its regulator driver. This is hardware layout for access PMIC MT6397 from AP SoC MT8135. Between PMIC MT6397 and MT8135, the physical signal channel is SPI bus. A specific hardware called PMIC Wrapper or PWRAP to handle access protocols in both PMIC and AP side. +-+ +---+ | | | | | Mediatek AP SoC | | | | (ex. MT8135)| |MT6397 | | | | | | ++ | (SPI bus) | ++| | || |---| ||| | | PMIC | |---| | PMIC || | | Wrapper| |---| | Wrapper|| | || |---| ||| | ++ | | ++| | | | | +-+ +---+ Changes since v2 (1) Patch 1/8: Update kernel config of MT8135 PMIC Wrapper. It needs to select REGMAP. (2) Patch 2/8: Update patch of MT6397 MFD driver to fix defeat of coding styles. (3) Patch 3/8: Update MT6397 regulator driver - use standard helpers for ops .set_voltage_sel, .get_voltage_sel and .is_enabled - remove regulator's DT matching codes in the driver. - fix defeat of coding styles. (4) Patch 4/8: Update document for MT8135 PMIC wrapper. (5) Patch 5/8: Update document for MT6397 MFD. (6) Patch 6/8: Update document for MT6397 regulators. (7) Patch 7/8: Update device tree for MT8135 PMIC wrapper in mt8135.dtsi. (8) Patch 8/8: Add device tree for MT6397 MFD and regulators in mt8135-evbp1.dts board file. Second version (v2): http://lists.infradead.org/pipermail/linux-arm-kernel/2014-November/307069.html Changes since v1 (1) Patch 1/8: Add MT8135 PMIC wrapper driver for SoC's proprietary hardware. (2) Patch 2/8: Update patch of MT6397 MFD driver to contain only MFD related codes and fix defeat of coding styles. (3) Patch 3/8: Update MT6397 regulator driver - use helpers and standard ways for specifying data in regulator description. - add more comments to explaining why the driver implement its own regulator_ops for .is_enabled, .set_voltage_sel and .get_voltage_sel. - update driver implement for coding styles. (4) Patch 4/8: Add document for MT8135 PMIC wrapper. (5) Patch 5/8: Update document for MT6397 MFD. (6) Patch 6/8: Update document for MT6397 regulators. (7) Patch 7/8: Add device tree for MT6397 MFD in mt8135.dtsi. (8) Patch 8/8: Update device tree for MT6397 regulators in mt8135.dtsi. Initial version (v1): http://lists.infradead.org/pipermail/linux-arm-kernel/2014-November/302984.html This driver is based on 3.18-rc1. Flora Fu (8): soc: mediatek: Add PMIC wrapper for MT8135 and MT6397 SoC mfd: MT6397: Add support for PMIC MT6397 MFD regulator: MT6397: Add support for MT6397 regulator dt-bindings:: Add document for MT8135 PMIC Wrapper dt-bindings: Add document for MT6397 MFD dt-bindings: Add document for MT6397 regulator ARM: dts: mt8135: Add support for MT8135 PMIC wrapper ARM: dts: mt8135: Add support for MT6397 MFD and regulator Documentation/devicetree/bindings/mfd/mt6397.txt | 75 ++ .../bindings/regulator/mt6397-regulator.txt| 217 ++ .../soc/mediatek/mediatek,mt8135-pwrap.txt | 51 ++ arch/arm/boot/dts/mt8135-evbp1.dts | 193 + arch/arm/boot/dts/mt8135.dtsi | 14 + drivers/mfd/Kconfig| 10 + drivers/mfd/Makefile | 1 + drivers/mfd/mt6397-core.c | 87 +++ drivers/regulator/Kconfig | 9 + drivers/regulator/Makefile | 1 + drivers/regulator/mt6397-regulator.c | 332 drivers/soc/Kconfig| 1 + drivers/soc/Makefile | 1 + drivers/soc/mediatek/Kconfig | 12 + drivers/soc/mediatek/Makefile | 1 + drivers/soc/mediatek/mt8135-pmic-wrap.c| 844 + drivers/soc/mediatek/mt8135-pmic-wrap.h| 138 include/linux/mfd/mt6397/core.h| 23 + include/linux/mfd/mt6397/registers.h | 362 + include/linux/regulator/mt6397-regulator.h | 49 ++ include/linux/soc/mediatek/mtk-pmic-wrap.h | 25 + 21 files changed, 2446 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/mt6397.txt create mode 100644 Documentation/devicetree/bindings/regulator/mt6397-regulator.txt create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,mt8135-pwrap.txt create mode 100644 drivers/mfd/mt6397-core.c create mode 100644 drivers/regulator/mt6397-regulator.c create mode 100644 drivers/soc/mediatek
[PATCH v3 6/8] dt-bindings: Add document for MT6397 regulator
Signed-off-by: Flora Fu flora...@mediatek.com
---
.../bindings/regulator/mt6397-regulator.txt| 217 +
1 file changed, 217 insertions(+)
create mode 100644
Documentation/devicetree/bindings/regulator/mt6397-regulator.txt
diff --git a/Documentation/devicetree/bindings/regulator/mt6397-regulator.txt
b/Documentation/devicetree/bindings/regulator/mt6397-regulator.txt
new file mode 100644
index 000..a42b1d6
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/mt6397-regulator.txt
@@ -0,0 +1,217 @@
+Mediatek MT6397 Regulator Driver
+
+Required properties:
+- compatible: mediatek,mt6397-regulator
+- mt6397regulator: List of regulators provided by this controller. It is named
+ according to its regulator type, buck_name and ldo_name.
+ The definition for each of these nodes is defined using the standard binding
+ for regulators at Documentation/devicetree/bindings/regulator/regulator.txt.
+
+The valid names for regulators are::
+BUCK:
+ buck_vpca15, buck_vpca7, buck_vsramca15, buck_vsramca7, buck_vcore,
buck_vgpu,
+ buck_vdrm, buck_vio18
+LDO:
+ ldo_vtcxo, ldo_va28, ldo_vcama, ldo_vio28, ldo_vusb, ldo_vmc, ldo_vmch,
+ ldo_vemc3v3, ldo_vgp1, ldo_vgp2, ldo_vgp3, ldo_vgp4, ldo_vgp5, ldo_vgp6,
+ ldo_vibr
+
+Example:
+ pmic {
+ compatible = mediatek,mt6397;
+
+ mt6397regulator: mt6397regulator {
+ compatible = mediatek,mt6397-regulator;
+
+ mt6397_vpca15_reg: buck_vpca15 {
+ regulator-compatible = buck_vpca15;
+ regulator-name = vpca15;
+ regulator-min-microvolt = 85;
+ regulator-max-microvolt = 135;
+ regulator-ramp-delay = 12500;
+ regulator-enable-ramp-delay = 200;
+ };
+
+ mt6397_vpca7_reg: buck_vpca7 {
+ regulator-compatible = buck_vpca7;
+ regulator-name = vpca7;
+ regulator-min-microvolt = 85;
+ regulator-max-microvolt = 135;
+ regulator-ramp-delay = 12500;
+ regulator-enable-ramp-delay = 115;
+ };
+
+ mt6397_vsramca15_reg: buck_vsramca15 {
+ regulator-compatible = buck_vsramca15;
+ regulator-name = vsramca15;
+ regulator-min-microvolt = 85;
+ regulator-max-microvolt = 135;
+ regulator-ramp-delay = 12500;
+ regulator-enable-ramp-delay = 115;
+
+ };
+
+ mt6397_vsramca7_reg: buck_vsramca7 {
+ regulator-compatible = buck_vsramca7;
+ regulator-name = vsramca7;
+ regulator-min-microvolt = 85;
+ regulator-max-microvolt = 135;
+ regulator-ramp-delay = 12500;
+ regulator-enable-ramp-delay = 115;
+
+ };
+
+ mt6397_vcore_reg: buck_vcore {
+ regulator-compatible = buck_vcore;
+ regulator-name = vcore;
+ regulator-min-microvolt = 85;
+ regulator-max-microvolt = 135;
+ regulator-ramp-delay = 12500;
+ regulator-enable-ramp-delay = 115;
+ };
+
+ mt6397_vgpu_reg: buck_vgpu {
+ regulator-compatible = buck_vgpu;
+ regulator-name = vgpu;
+ regulator-min-microvolt = 70;
+ regulator-max-microvolt = 135;
+ regulator-ramp-delay = 12500;
+ regulator-enable-ramp-delay = 115;
+ };
+
+ mt6397_vdrm_reg: buck_vdrm {
+ regulator-compatible = buck_vdrm;
+ regulator-name = vdrm;
+ regulator-min-microvolt = 80;
+ regulator-max-microvolt = 140;
+ regulator-ramp-delay = 12500;
+ regulator-enable-ramp-delay = 500;
+ };
+
+ mt6397_vio18_reg: buck_vio18 {
+ regulator-compatible = buck_vio18;
+ regulator-name = vio18;
+ regulator
[PATCH v3 8/8] ARM: dts: mt8135: Add support for MT6397 MFD and regulator
Add device tree for MT6397 MFD and regulator in mt8135-evbp1.dts board file
Signed-off-by: Flora Fu flora...@mediatek.com
---
arch/arm/boot/dts/mt8135-evbp1.dts | 193 +
1 file changed, 193 insertions(+)
diff --git a/arch/arm/boot/dts/mt8135-evbp1.dts
b/arch/arm/boot/dts/mt8135-evbp1.dts
index cba80b8..627cc47 100644
--- a/arch/arm/boot/dts/mt8135-evbp1.dts
+++ b/arch/arm/boot/dts/mt8135-evbp1.dts
@@ -22,3 +22,196 @@
reg = 0 0x8000 0 0x4000;
};
};
+
+pwrap {
+ pmic {
+ compatible = mediatek,mt6397;
+
+ mt6397regulator: mt6397regulator {
+ compatible = mediatek,mt6397-regulator;
+
+ mt6397_vpca15_reg: buck_vpca15 {
+ regulator-compatible = buck_vpca15;
+ regulator-name = vpca15;
+ regulator-min-microvolt = 85;
+ regulator-max-microvolt = 135;
+ regulator-ramp-delay = 12500;
+ regulator-always-on;
+ };
+
+ mt6397_vpca7_reg: buck_vpca7 {
+ regulator-compatible = buck_vpca7;
+ regulator-name = vpca7;
+ regulator-min-microvolt = 85;
+ regulator-max-microvolt = 135;
+ regulator-ramp-delay = 12500;
+ regulator-always-on;
+ };
+
+ mt6397_vsramca15_reg: buck_vsramca15 {
+ regulator-compatible = buck_vsramca15;
+ regulator-name = vsramca15;
+ regulator-min-microvolt = 85;
+ regulator-max-microvolt = 135;
+ regulator-ramp-delay = 12500;
+ regulator-always-on;
+ };
+
+ mt6397_vsramca7_reg: buck_vsramca7 {
+ regulator-compatible = buck_vsramca7;
+ regulator-name = vsramca7;
+ regulator-min-microvolt = 85;
+ regulator-max-microvolt = 135;
+ regulator-ramp-delay = 12500;
+ regulator-always-on;
+ };
+
+ mt6397_vcore_reg: buck_vcore {
+ regulator-compatible = buck_vcore;
+ regulator-name = vcore;
+ regulator-min-microvolt = 85;
+ regulator-max-microvolt = 135;
+ regulator-ramp-delay = 12500;
+ regulator-always-on;
+ };
+
+ mt6397_vgpu_reg: buck_vgpu {
+ regulator-compatible = buck_vgpu;
+ regulator-name = vgpu;
+ regulator-min-microvolt = 70;
+ regulator-max-microvolt = 135;
+ regulator-ramp-delay = 12500;
+ regulator-enable-ramp-delay = 115;
+ };
+
+ mt6397_vdrm_reg: buck_vdrm {
+ regulator-compatible = buck_vdrm;
+ regulator-name = vdrm;
+ regulator-min-microvolt = 120;
+ regulator-max-microvolt = 140;
+ regulator-ramp-delay = 12500;
+ regulator-always-on;
+ };
+
+ mt6397_vio18_reg: buck_vio18 {
+ regulator-compatible = buck_vio18;
+ regulator-name = vio18;
+ regulator-min-microvolt = 162;
+ regulator-max-microvolt = 198;
+ regulator-ramp-delay = 12500;
+ regulator-always-on;
+ };
+
+ mt6397_vtcxo_reg: ldo_vtcxo {
+ regulator-compatible = ldo_vtcxo;
+ regulator-name = vtcxo;
+ regulator-always-on;
+ };
+
+ mt6397_va28_reg: ldo_va28 {
+ regulator-compatible = ldo_va28;
+ regulator-name = va28;
+ regulator-always-on;
+ };
+
+ mt6397_vcama_reg: ldo_vcama
[PATCH v3 2/8] mfd: MT6397: Add support for PMIC MT6397 MFD
Add core files for MT6397 MFD driver.
Signed-off-by: Flora Fu flora...@mediatek.com
---
drivers/mfd/Kconfig | 10 +
drivers/mfd/Makefile | 1 +
drivers/mfd/mt6397-core.c| 87 +
include/linux/mfd/mt6397/core.h | 23 +++
include/linux/mfd/mt6397/registers.h | 362 +++
5 files changed, 483 insertions(+)
create mode 100644 drivers/mfd/mt6397-core.c
create mode 100644 include/linux/mfd/mt6397/core.h
create mode 100644 include/linux/mfd/mt6397/registers.h
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 1456ea7..f0b3efc 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -1318,6 +1318,16 @@ config MFD_STW481X
in various ST Microelectronics and ST-Ericsson embedded
Nomadik series.
+config MFD_MT6397
+ tristate MediaTek MT6397 PMIC Support
+ select MFD_CORE
+ select IRQ_DOMAIN
+ help
+ Say yes here to add support for MediaTek MT6397 PMIC. This is
+ a Power Management IC. This driver provides common support for
+ accessing the device; additional drivers must be enabled in order
+ to use the functionality of the device.
+
menu Multimedia Capabilities Port drivers
depends on ARCH_SA1100
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 8bd54b1..7168193 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -177,3 +177,4 @@ obj-$(CONFIG_MFD_HI6421_PMIC) += hi6421-pmic-core.o
intel-soc-pmic-objs:= intel_soc_pmic_core.o intel_soc_pmic_crc.o
obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o
+obj-$(CONFIG_MFD_MT6397) += mt6397-core.o
diff --git a/drivers/mfd/mt6397-core.c b/drivers/mfd/mt6397-core.c
new file mode 100644
index 000..85631e0
--- /dev/null
+++ b/drivers/mfd/mt6397-core.c
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Flora Fu flora...@mediatek.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/module.h
+#include linux/of_device.h
+#include linux/mfd/core.h
+#include linux/mfd/mt6397/core.h
+#include linux/soc/mediatek/mtk-pmic-wrap.h
+
+static const struct mfd_cell mt6397_devs[] = {
+ { .name = mt6397-rtc },
+ {
+ .name = mt6397-regulator,
+ .of_compatible = mediatek,mt6397-regulator,
+ },
+ {
+ .name = mt6397-codec,
+ .of_compatible = mediatek,mt6397-codec,
+ },
+};
+
+static int mt6397_probe(struct platform_device *pdev)
+{
+ u32 ret;
+ struct mt6397_chip *mt6397;
+ struct pmic_wrapper *wrp;
+
+ /* mt6397 MFD is child device of soc pmic wrapper. */
+ if (!pdev-dev.parent)
+ return -ENODEV;
+
+ wrp = dev_get_drvdata(pdev-dev.parent);
+ mt6397 = devm_kzalloc(pdev-dev, sizeof(*mt6397), GFP_KERNEL);
+ if (!mt6397)
+ return -ENOMEM;
+
+ mt6397-dev = pdev-dev;
+ mt6397-regmap = wrp-regmap;
+ platform_set_drvdata(pdev, mt6397);
+
+ ret = mfd_add_devices(pdev-dev, -1, mt6397_devs[0],
+ ARRAY_SIZE(mt6397_devs), NULL, 0, NULL);
+ if (ret)
+ dev_err(pdev-dev, failed to add child devices: %d\n, ret);
+
+ return ret;
+}
+
+static int mt6397_remove(struct platform_device *pdev)
+{
+ mfd_remove_devices(pdev-dev);
+
+ return 0;
+}
+
+static const struct of_device_id mt6397_of_match[] = {
+ { .compatible = mediatek,mt6397 },
+ { }
+};
+MODULE_DEVICE_TABLE(of, mt6397_of_match);
+
+static struct platform_driver mt6397_driver = {
+ .probe = mt6397_probe,
+ .remove = mt6397_remove,
+ .driver = {
+ .name = mt6397,
+ .of_match_table = of_match_ptr(mt6397_of_match),
+ },
+};
+
+module_platform_driver(mt6397_driver);
+
+MODULE_AUTHOR(Flora Fu flora...@mediatek.com);
+MODULE_DESCRIPTION(Driver for MediaTek MT6397 PMIC);
+MODULE_LICENSE(GPL);
+MODULE_ALIAS(platform:mt6397);
diff --git a/include/linux/mfd/mt6397/core.h b/include/linux/mfd/mt6397/core.h
new file mode 100644
index 000..567164e
--- /dev/null
+++ b/include/linux/mfd/mt6397/core.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Flora Fu flora...@mediatek.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY
[PATCH v3 5/8] dt-bindings: Add document for MT6397 MFD
Signed-off-by: Flora Fu flora...@mediatek.com
---
Documentation/devicetree/bindings/mfd/mt6397.txt | 75
1 file changed, 75 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mfd/mt6397.txt
diff --git a/Documentation/devicetree/bindings/mfd/mt6397.txt
b/Documentation/devicetree/bindings/mfd/mt6397.txt
new file mode 100644
index 000..64ef408
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/mt6397.txt
@@ -0,0 +1,75 @@
+MediaTek MT6397 Multifunction Device Driver
+
+MT6397 is a multifunction device with the following sub modules:
+- Regulator
+- RTC
+- Audio codec
+- GPIO
+- Clock
+
+It is interfaced to host controller using SPI interface by a proprietary
hardware
+called PMIC wrapper or pwrap. MT6397 MFD is a child device of pwrap.
+See the following for pwarp node definitions:
+Documentation/devicetree/bindings/soc/mediatek,mt8135-pwrap.txt
+
+This document describes the binding for mfd device and its sub module.
+
+Required properties:
+compatible: mediatek,mt6397
+
+Optional properties:
+- codec: Audio codec
+- pinctrl: GPIO in mt6397
+- rtc: RTC
+- clock: clocks in mt6397
+- regulators: regulators in mt6397
+
+Example:
+ pwrap: pwrap@1000f000 {
+ compatible = mediatek,mt8135-pwrap;
+ reg = 0 0x1000f000 0 0x1000,
+ 0 0x11017000 0 0x1000;
+ reg-names = pwrap-base, pwrap-bridge-base;
+ interrupts = GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH;
+ resets = infrarst MT8135_INFRA_PMIC_WRAP_RST,
+ perirst MT8135_PERI_PWRAP_BRIDGE_SW_RST;
+ reset-names = infra-pwrap-rst,
+ peri-pwrap-bridge-rst;
+ clocks = pmicspi_sel, clk26m;
+ clock-names = pmicspi-sel, pmicspi-parent;
+
+ pmic {
+ compatible = mediatek,mt6397;
+
+ codec: mt6397codec {
+ compatible = mediatek,mt6397-codec;
+ };
+
+ pinctrl@0xC000 {
+ compatible = mediatek,mt6397-pinctrl;
+ reg = 0 0xC000 0 0x0108;
+ gpio-controller;
+ };
+
+ mt6397regulator: mt6397regulator {
+ compatible = mediatek,mt6397-regulator;
+
+ mt6397_vpca15_reg: buck_vpca15 {
+ regulator-compatible = buck_vpca15;
+ regulator-name = vpca15;
+ regulator-min-microvolt = 85;
+ regulator-max-microvolt = 140;
+ regulator-ramp-delay = 12500;
+ regulator-always-on;
+ };
+
+ mt6397_vgp4_reg: ldo_vgp4 {
+ regulator-compatible = ldo_vgp4;
+ regulator-name = vgp4;
+ regulator-min-microvolt = 120;
+ regulator-max-microvolt = 330;
+ regulator-enable-ramp-delay = 218;
+ };
+ };
+ };
+ };
--
1.8.1.1.dirty
--
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[PATCH v3 7/8] ARM: dts: mt8135: Add support for MT8135 PMIC wrapper
Add device tree for MT8135 PMIC wrapper in mt8135.dtsi.
Signed-off-by: Flora Fu flora...@mediatek.com
---
arch/arm/boot/dts/mt8135.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi
index 90a56ad..86b1326 100644
--- a/arch/arm/boot/dts/mt8135.dtsi
+++ b/arch/arm/boot/dts/mt8135.dtsi
@@ -102,6 +102,20 @@
clock-names = system-clk, rtc-clk;
};
+ pwrap: pwrap@1000f000 {
+ compatible = mediatek,mt8135-pwrap;
+ reg = 0 0x1000f000 0 0x1000,
+ 0 0x11017000 0 0x1000;
+ reg-names = pwrap-base, pwrap-bridge-base;
+ interrupts = GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH;
+ resets = infrarst MT8135_INFRA_PMIC_WRAP_RST,
+ perirst
MT8135_PERI_PWRAP_BRIDGE_SW_RST;
+ reset-names = infra-pwrap-rst,
+ peri-pwrap-bridge-rst;
+ clocks = pmicspi_sel, clk26m ;
+ clock-names = pmicspi-sel, pmicspi-parent;
+ };
+
gic: interrupt-controller@10211000 {
compatible = arm,cortex-a15-gic;
interrupt-controller;
--
1.8.1.1.dirty
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[PATCH v3 4/8] dt-bindings:: Add document for MT8135 PMIC Wrapper
Signed-off-by: Flora Fu flora...@mediatek.com
---
.../soc/mediatek/mediatek,mt8135-pwrap.txt | 51 ++
1 file changed, 51 insertions(+)
create mode 100644
Documentation/devicetree/bindings/soc/mediatek/mediatek,mt8135-pwrap.txt
diff --git
a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mt8135-pwrap.txt
b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mt8135-pwrap.txt
new file mode 100644
index 000..d630fa0
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mt8135-pwrap.txt
@@ -0,0 +1,51 @@
+MediaTek MT8135 PMIC Wrapper Driver
+
+MediaTek PMIC MFD is interfaced to host controller using SPI interface
+by a proprietary hardware called PMIC wrapper or pwrap.
+
++-+ +---+
+| | | |
+| Mediatek AP SoC | | |
+| (ex. MT8135)| |MT6397 |
+| | | |
+| ++ | (SPI bus) | ++|
+| || |---| |||
+| | PMIC | |---| | PMIC ||
+| | Wrapper| |---| | Wrapper||
+| || |---| |||
+| ++ | | ++|
+| | | |
++-+ +---+
+
+This document describes the binding for MT8135 PMIC wrapper.
+
+Required properties in pwrap device node.
+- compatible:mediatek,mt8135-pwrap
+- interrupts: IRQ for pwrap in SOC
+- reg: address range for pwrap registers
+- resets: reset bit for pwrap
+- clock: clock frequency selection in SPI bus
+
+Optional properities:
+- pmic: Mediatek PMIC MFD is the child device of pwrap
+ See the following for child node definitions:
+ Documentation/devicetree/bindings/mfd/mt6397.txt
+
+Example:
+ pwrap: pwrap@1000f000 {
+ compatible = mediatek,mt8135-pwrap;
+ reg = 0 0x1000f000 0 0x1000,
+ 0 0x11017000 0 0x1000;
+ reg-names = pwrap-base, pwrap-bridge-base;
+ interrupts = GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH;
+ resets = infrarst MT8135_INFRA_PMIC_WRAP_RST,
+ perirst MT8135_PERI_PWRAP_BRIDGE_SW_RST;
+ reset-names = infra-pwrap-rst,
+ peri-pwrap-bridge-rst;
+ clocks = pmicspi_sel, clk26m;
+ clock-names = pmicspi-sel, pmicspi-parent;
+
+ pmic {
+ compatible = mediatek,mt6397;
+ };
+ };
--
1.8.1.1.dirty
--
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[PATCH v3 3/8] regulator: MT6397: Add support for MT6397 regulator
Add MT6397 regulator driver.
Signed-off-by: Flora Fu flora...@mediatek.com
---
drivers/regulator/Kconfig | 9 +
drivers/regulator/Makefile | 1 +
drivers/regulator/mt6397-regulator.c | 332 +
include/linux/regulator/mt6397-regulator.h | 49 +
4 files changed, 391 insertions(+)
create mode 100644 drivers/regulator/mt6397-regulator.c
create mode 100644 include/linux/regulator/mt6397-regulator.h
diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index 55d7b7b..38a8d84 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -433,6 +433,15 @@ config REGULATOR_MC13892
Say y here to support the regulators found on the Freescale MC13892
PMIC.
+config REGULATOR_MT6397
+ tristate MediaTek MT6397 PMIC
+ depends on MFD_MT6397
+ help
+ Say y here to select this option to enable the power regulator of
+ MediaTek MT6397 PMIC.
+ This driver supports the control of different power rails of device
+ through regulator interface.
+
config REGULATOR_PALMAS
tristate TI Palmas PMIC Regulators
depends on MFD_PALMAS
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index 1029ed3..bad280e 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -58,6 +58,7 @@ obj-$(CONFIG_REGULATOR_MAX77802) += max77802.o
obj-$(CONFIG_REGULATOR_MC13783) += mc13783-regulator.o
obj-$(CONFIG_REGULATOR_MC13892) += mc13892-regulator.o
obj-$(CONFIG_REGULATOR_MC13XXX_CORE) += mc13xxx-regulator-core.o
+obj-$(CONFIG_REGULATOR_MT6397) += mt6397-regulator.o
obj-$(CONFIG_REGULATOR_QCOM_RPM) += qcom_rpm-regulator.o
obj-$(CONFIG_REGULATOR_PALMAS) += palmas-regulator.o
obj-$(CONFIG_REGULATOR_PFUZE100) += pfuze100-regulator.o
diff --git a/drivers/regulator/mt6397-regulator.c
b/drivers/regulator/mt6397-regulator.c
new file mode 100644
index 000..a5b2f47
--- /dev/null
+++ b/drivers/regulator/mt6397-regulator.c
@@ -0,0 +1,332 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Flora Fu flora...@mediatek.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/module.h
+#include linux/of.h
+#include linux/platform_device.h
+#include linux/regmap.h
+#include linux/mfd/mt6397/core.h
+#include linux/mfd/mt6397/registers.h
+#include linux/regulator/driver.h
+#include linux/regulator/machine.h
+#include linux/regulator/mt6397-regulator.h
+#include linux/regulator/of_regulator.h
+
+/*
+ * MT6397 regulators' information
+ *
+ * @desc: standard fields of regulator description.
+ * @qi: Mask for query enable signal status of regulators
+ * @vselon_reg: Register sections for hardware control mode of bucks
+ * @vselctrl_reg: Register for controlling the buck control mode.
+ * @vselctrl_mask: Mask for query buck's voltage control mode.
+ */
+struct mt6397_regulator_info {
+ struct regulator_desc desc;
+ u32 qi;
+ u32 vselon_reg;
+ u32 vselctrl_reg;
+ u32 vselctrl_mask;
+};
+
+#define MT6397_BUCK(match, vreg, min, max, step, volt_ranges, enreg, \
+ vosel, vosel_mask, voselon, vosel_ctrl) \
+[MT6397_ID_##vreg] = { \
+ .desc = { \
+ .name = #vreg, \
+ .of_match = of_match_ptr(match),\
+ .ops = mt6397_volt_range_ops, \
+ .type = REGULATOR_VOLTAGE, \
+ .id = MT6397_ID_##vreg, \
+ .owner = THIS_MODULE, \
+ .n_voltages = (max - min)/step + 1, \
+ .linear_ranges = volt_ranges, \
+ .n_linear_ranges = ARRAY_SIZE(volt_ranges), \
+ .vsel_reg = vosel, \
+ .vsel_mask = vosel_mask,\
+ .enable_reg = enreg,\
+ .enable_mask = BIT(0), \
+ }, \
+ .qi = BIT(13), \
+ .vselon_reg = voselon, \
+ .vselctrl_reg = vosel_ctrl
[PATCH v3 1/8] soc: mediatek: Add PMIC wrapper for MT8135 and MT6397 SoC
Add PMIC wrapper of MT8135 to access MT6397 MFD.
Signed-off-by: Flora Fu flora...@mediatek.com
---
drivers/soc/Kconfig| 1 +
drivers/soc/Makefile | 1 +
drivers/soc/mediatek/Kconfig | 12 +
drivers/soc/mediatek/Makefile | 1 +
drivers/soc/mediatek/mt8135-pmic-wrap.c| 844 +
drivers/soc/mediatek/mt8135-pmic-wrap.h| 138 +
include/linux/soc/mediatek/mtk-pmic-wrap.h | 25 +
7 files changed, 1022 insertions(+)
create mode 100644 drivers/soc/mediatek/Kconfig
create mode 100644 drivers/soc/mediatek/Makefile
create mode 100644 drivers/soc/mediatek/mt8135-pmic-wrap.c
create mode 100644 drivers/soc/mediatek/mt8135-pmic-wrap.h
create mode 100644 include/linux/soc/mediatek/mtk-pmic-wrap.h
diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
index 76d6bd4..d8bde82 100644
--- a/drivers/soc/Kconfig
+++ b/drivers/soc/Kconfig
@@ -1,5 +1,6 @@
menu SOC (System On Chip) specific Drivers
+source drivers/soc/mediatek/Kconfig
source drivers/soc/qcom/Kconfig
source drivers/soc/ti/Kconfig
source drivers/soc/versatile/Kconfig
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index 063113d..70042b2 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -2,6 +2,7 @@
# Makefile for the Linux Kernel SOC specific device drivers.
#
+obj-$(CONFIG_ARCH_MEDIATEK)+= mediatek/
obj-$(CONFIG_ARCH_QCOM)+= qcom/
obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-$(CONFIG_SOC_TI) += ti/
diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
new file mode 100644
index 000..746e030
--- /dev/null
+++ b/drivers/soc/mediatek/Kconfig
@@ -0,0 +1,12 @@
+#
+# MediaTek SoC drivers
+#
+config MT8135_PMIC_WRAP
+ tristate MediaTek MT8135 PMIC Wrapper Support
+ depends on ARCH_MEDIATEK
+ select REGMAP
+ help
+ Say yes here to add support for MediaTek MT8135 PMIC Wrapper.
+ PMIC wrapper is a proprietary hardware in MT8135 to make
+ communication protocols to access PMIC device.
+ This driver implement access protocols for MT8135.
diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
new file mode 100644
index 000..49b9588
--- /dev/null
+++ b/drivers/soc/mediatek/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_MT8135_PMIC_WRAP) += mt8135-pmic-wrap.o
diff --git a/drivers/soc/mediatek/mt8135-pmic-wrap.c
b/drivers/soc/mediatek/mt8135-pmic-wrap.c
new file mode 100644
index 000..75aa28e
--- /dev/null
+++ b/drivers/soc/mediatek/mt8135-pmic-wrap.c
@@ -0,0 +1,844 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Flora Fu flora...@mediatek.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/clk.h
+#include linux/interrupt.h
+#include linux/io.h
+#include linux/kernel.h
+#include linux/module.h
+#include linux/of_device.h
+#include linux/platform_device.h
+#include linux/regmap.h
+#include linux/reset.h
+#include linux/mfd/mt6397/registers.h
+#include linux/soc/mediatek/mtk-pmic-wrap.h
+#include mt8135-pmic-wrap.h
+
+/* macro for wrapper status */
+#define PWRAP_GET_WACS0_WDATA(x) (((x) 0) 0x)
+#define PWRAP_GET_WACS0_ADR(x) (((x) 16) 0x7fff)
+#define PWRAP_GET_WACS0_WRITE(x) (((x) 31) 0x0001)
+#define PWRAP_GET_WACS0_RDATA(x) (((x) 0) 0x)
+#define PWRAP_GET_WACS0_FSM(x) (((x) 16) 0x0007)
+#define PWRAP_STATE_SYNC_IDLE0 (1 20)
+#define PWRAP_STATE_INIT_DONE0 (1 21)
+
+/* macro for WACS FSM */
+#define PWRAP_WACS_FSM_IDLE0x00
+#define PWRAP_WACS_FSM_REQ 0x02
+#define PWRAP_WACS_FSM_WFDLE 0x04
+#define PWRAP_WACS_FSM_WFVLDCLR0x06
+#define PWRAP_WACS_INIT_DONE 0x01
+#define PWRAP_WACS_WACS_SYNC_IDLE 0x01
+
+/* macro for device wrapper default value */
+#define PWRAP_DEW_READ_TEST_VAL0x5aa5
+#define PWRAP_DEW_WRITE_TEST_VAL 0xa55a
+
+/* macro for manual command */
+#define PWRAP_OP_WR0x1
+#define PWRAP_OP_RD0x0
+#define PWRAP_OP_CSH 0x0
+#define PWRAP_OP_CSL 0x1
+#define PWRAP_OP_OUTS 0x8
+#define PWRAP_OP_OUTD 0x9
+#define PWRAP_OP_OUTQ 0xA
+
+static bool is_fsm_idle(u32 x)
+{
+ return PWRAP_GET_WACS0_FSM(x) == PWRAP_WACS_FSM_IDLE;
+}
+
+static bool is_fsm_vldclr(u32 x)
+{
+ return PWRAP_GET_WACS0_FSM(x) == PWRAP_WACS_FSM_WFVLDCLR;
+}
+
+static bool
Re: [PATCH v2 2/8] mfd: MT6397: Add support for PMIC MT6397 MFD
On Mon, 2014-12-01 at 11:47 +, Lee Jones wrote: > On Fri, 28 Nov 2014, Flora Fu wrote: > > > + if (!mt6397) > > + return -ENOMEM; > > + > > + mt6397->dev = >dev; > > Is this used else where? If not, I think you can remove it. No one is used it in this patch sets but it will be used for irq functions to get irq id or print logs for error case in the future. Can I keep it in the patch? > > > + mt6397->regmap = wrp->regmap; > > + platform_set_drvdata(pdev, mt6397); > > Then you can platform_set_drvdata(pdev, regmap); > > Although I don't see this being used either. Is it used in the child > devices? > Yes, it is used to provide regmap handle for its child device. In the patch set, regulator uses it. Thanks, Flora -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v2 2/8] mfd: MT6397: Add support for PMIC MT6397 MFD
On Mon, 2014-12-01 at 11:47 +, Lee Jones wrote: On Fri, 28 Nov 2014, Flora Fu wrote: + if (!mt6397) + return -ENOMEM; + + mt6397-dev = pdev-dev; Is this used else where? If not, I think you can remove it. No one is used it in this patch sets but it will be used for irq functions to get irq id or print logs for error case in the future. Can I keep it in the patch? + mt6397-regmap = wrp-regmap; + platform_set_drvdata(pdev, mt6397); Then you can platform_set_drvdata(pdev, regmap); Although I don't see this being used either. Is it used in the child devices? Yes, it is used to provide regmap handle for its child device. In the patch set, regulator uses it. Thanks, Flora -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v2] mfd: syscon: add child device support
Hi, Philipp,
How is the status of syscon patch in
https://lkml.org/lkml/2014/5/27/422 ?
Will this patch be accepted in feature release 3.19?
Thanks,
Flora
On Mon, 2014-11-03 at 10:16 +0100, Philipp Zabel wrote:
> For devices which have a complete register for themselves, it is possible to
> place them next to the syscon device with overlapping reg ranges. The same is
> not possible for devices which only occupy bitfields in registers shared with
> other users.
> For devices that are completely controlled by bitfields in the syscon address
> range, such as multiplexers or voltage regulators, allow to put child devices
> into the syscon device node.
>
> Signed-off-by: Philipp Zabel
> ---
> Changes since v1:
> - Reworded binding documentation to allow #size-cells = <1>, which is useful
>for syscon children that are controlled through a (possibly shared)
> register
>range.
> ---
> Documentation/devicetree/bindings/mfd/syscon.txt | 13 +
> drivers/mfd/syscon.c | 3 +++
> 2 files changed, 16 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mfd/syscon.txt
> b/Documentation/devicetree/bindings/mfd/syscon.txt
> index fe8150b..0c6b497 100644
> --- a/Documentation/devicetree/bindings/mfd/syscon.txt
> +++ b/Documentation/devicetree/bindings/mfd/syscon.txt
> @@ -9,12 +9,25 @@ using a specific compatible value), interrogate the node
> (or associated
> OS driver) to determine the location of the registers, and access the
> registers directly.
>
> +Optionally, devices that are controlled exclusively through syscon registers,
> +or even bitfields in shared syscon registers, can also be added as child
> nodes
> +to the syscon device node. These devices can implicitly assume their parent
> +node is a syscon provider without referencing it explicitly via phandle.
> +In this case, the syscon node should have #address-cells = <1> and
> +#size-cells = <0> or <1> and no ranges property.
> +
> Required properties:
> - compatible: Should contain "syscon".
> - reg: the register region can be accessed from syscon
>
> +Optional properties:
> +- #address-cells: Should be 1.
> +- #size-cells: Should be 0 or 1.
> +
> Examples:
> gpr: iomuxc-gpr@020e {
> + #address-cells = <1>;
> + #size-cells = <0>;
> compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
> reg = <0x020e 0x38>;
> };
> diff --git a/drivers/mfd/syscon.c b/drivers/mfd/syscon.c
> index ca15878..38da178 100644
> --- a/drivers/mfd/syscon.c
> +++ b/drivers/mfd/syscon.c
> @@ -155,6 +155,9 @@ static int syscon_probe(struct platform_device *pdev)
>
> dev_dbg(dev, "regmap %pR registered\n", res);
>
> + if (!of_device_is_compatible(pdev->dev.of_node, "simple-bus"))
> + of_platform_populate(pdev->dev.of_node, NULL, NULL, >dev);
> +
> return 0;
> }
>
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Re: [PATCH v2] mfd: syscon: add child device support
Hi, Philipp,
How is the status of syscon patch in
https://lkml.org/lkml/2014/5/27/422 ?
Will this patch be accepted in feature release 3.19?
Thanks,
Flora
On Mon, 2014-11-03 at 10:16 +0100, Philipp Zabel wrote:
For devices which have a complete register for themselves, it is possible to
place them next to the syscon device with overlapping reg ranges. The same is
not possible for devices which only occupy bitfields in registers shared with
other users.
For devices that are completely controlled by bitfields in the syscon address
range, such as multiplexers or voltage regulators, allow to put child devices
into the syscon device node.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
Changes since v1:
- Reworded binding documentation to allow #size-cells = 1, which is useful
for syscon children that are controlled through a (possibly shared)
register
range.
---
Documentation/devicetree/bindings/mfd/syscon.txt | 13 +
drivers/mfd/syscon.c | 3 +++
2 files changed, 16 insertions(+)
diff --git a/Documentation/devicetree/bindings/mfd/syscon.txt
b/Documentation/devicetree/bindings/mfd/syscon.txt
index fe8150b..0c6b497 100644
--- a/Documentation/devicetree/bindings/mfd/syscon.txt
+++ b/Documentation/devicetree/bindings/mfd/syscon.txt
@@ -9,12 +9,25 @@ using a specific compatible value), interrogate the node
(or associated
OS driver) to determine the location of the registers, and access the
registers directly.
+Optionally, devices that are controlled exclusively through syscon registers,
+or even bitfields in shared syscon registers, can also be added as child
nodes
+to the syscon device node. These devices can implicitly assume their parent
+node is a syscon provider without referencing it explicitly via phandle.
+In this case, the syscon node should have #address-cells = 1 and
+#size-cells = 0 or 1 and no ranges property.
+
Required properties:
- compatible: Should contain syscon.
- reg: the register region can be accessed from syscon
+Optional properties:
+- #address-cells: Should be 1.
+- #size-cells: Should be 0 or 1.
+
Examples:
gpr: iomuxc-gpr@020e {
+ #address-cells = 1;
+ #size-cells = 0;
compatible = fsl,imx6q-iomuxc-gpr, syscon;
reg = 0x020e 0x38;
};
diff --git a/drivers/mfd/syscon.c b/drivers/mfd/syscon.c
index ca15878..38da178 100644
--- a/drivers/mfd/syscon.c
+++ b/drivers/mfd/syscon.c
@@ -155,6 +155,9 @@ static int syscon_probe(struct platform_device *pdev)
dev_dbg(dev, regmap %pR registered\n, res);
+ if (!of_device_is_compatible(pdev-dev.of_node, simple-bus))
+ of_platform_populate(pdev-dev.of_node, NULL, NULL, pdev-dev);
+
return 0;
}
--
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[PATCH v3 1/3] ARM: mediatek: Add Reset Controller for MediaTek SoC
Add a driver in reset controller.
Signed-off-by: Flora Fu
---
drivers/reset/Makefile| 1 +
drivers/reset/reset-mtk.c | 131 ++
2 files changed, 132 insertions(+)
create mode 100644 drivers/reset/reset-mtk.c
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 60fed3d..adcebdf 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -2,3 +2,4 @@ obj-$(CONFIG_RESET_CONTROLLER) += core.o
obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o
obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o
obj-$(CONFIG_ARCH_STI) += sti/
+obj-$(CONFIG_ARCH_MEDIATEK) += reset-mtk.o
diff --git a/drivers/reset/reset-mtk.c b/drivers/reset/reset-mtk.c
new file mode 100644
index 000..7d792ec
--- /dev/null
+++ b/drivers/reset/reset-mtk.c
@@ -0,0 +1,131 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Flora.Fu
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct mtk_reset_data {
+ struct regmap *regmap;
+ u32 resetbase;
+ u32 num_regs;
+ struct reset_controller_dev rcdev;
+};
+
+static int mtk_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct regmap *regmap;
+ u32 addr;
+ u32 mask;
+ struct mtk_reset_data *data = container_of(rcdev,
+struct mtk_reset_data,
+rcdev);
+ regmap = data->regmap;
+ addr = data->resetbase + ((id / 32) << 2);
+ mask = BIT(id % 32);
+
+ return regmap_update_bits(regmap, addr, mask, mask);
+}
+
+static int mtk_reset_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct regmap *regmap;
+ u32 addr;
+ u32 mask;
+ struct mtk_reset_data *data = container_of(rcdev,
+struct mtk_reset_data,
+rcdev);
+
+ regmap = data->regmap;
+ addr = data->resetbase + ((id / 32) << 2);
+ mask = BIT(id % 32);
+
+ return regmap_update_bits(regmap, addr, mask, ~mask);
+}
+
+static struct reset_control_ops mtk_reset_ops = {
+ .assert = mtk_reset_assert,
+ .deassert = mtk_reset_deassert,
+};
+
+static int mtk_reset_probe(struct platform_device *pdev)
+{
+ struct mtk_reset_data *data;
+ struct device_node *np = pdev->dev.of_node;
+ struct device_node *syscon_np;
+ u32 reg[2];
+ int ret;
+
+ data = devm_kzalloc(>dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ syscon_np = of_get_parent(np);
+ data->regmap = syscon_node_to_regmap(syscon_np);
+ of_node_put(syscon_np);
+ if (IS_ERR(data->regmap)) {
+ dev_err(>dev, "couldn't get syscon-reset regmap\n");
+ return PTR_ERR(data->regmap);
+ }
+ ret = of_property_read_u32_array(np, "reg", reg, 2);
+ if (ret) {
+ dev_err(>dev, "couldn't read reset base from syscon!\n");
+ return -EINVAL;
+ }
+
+ data->resetbase = reg[0];
+ data->num_regs = reg[1] >> 2;
+ data->rcdev.owner = THIS_MODULE;
+ data->rcdev.nr_resets = data->num_regs * 32;
+ data->rcdev.ops = _reset_ops;
+ data->rcdev.of_node = pdev->dev.of_node;
+
+ return reset_controller_register(>rcdev);
+}
+
+static int mtk_reset_remove(struct platform_device *pdev)
+{
+ struct mtk_reset_data *data = platform_get_drvdata(pdev);
+
+ reset_controller_unregister(>rcdev);
+
+ return 0;
+}
+
+static const struct of_device_id mtk_reset_dt_ids[] = {
+ { .compatible = "mediatek,reset", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, mtk_reset_dt_ids);
+
+static struct platform_driver mtk_reset_driver = {
+ .probe = mtk_reset_probe,
+ .remove = mtk_reset_remove,
+ .driver = {
+ .name = "mtk-reset",
+ .owner = THIS_MODULE,
+ .of_match_table = mtk_reset_dt_ids,
+ },
+};
+
+module_platform_driver(mtk_reset_driver);
+
+MODULE_AUTHOR("Flora Fu ");
+MODULE_DESCRIPTION("MediaTek SoC Generic Reset Controller");
+MODULE_LICENSE("GPL");
--
1.8.1.1.dirty
--
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[PATCH v3 3/3] ARM: dts: mt8135: Add Reset Controller for MediaTek SoC
Add reset controller to MT8135 board dts.
Signed-off-by: Flora Fu
---
arch/arm/boot/dts/mt8135.dtsi | 27 +
.../dt-bindings/reset-controller/mt8135-resets.h | 64 ++
2 files changed, 91 insertions(+)
create mode 100644 include/dt-bindings/reset-controller/mt8135-resets.h
diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi
index 90a56ad..370c8fc 100644
--- a/arch/arm/boot/dts/mt8135.dtsi
+++ b/arch/arm/boot/dts/mt8135.dtsi
@@ -14,6 +14,7 @@
#include
#include
+#include
#include "skeleton64.dtsi"
/ {
@@ -102,6 +103,32 @@
clock-names = "system-clk", "rtc-clk";
};
+ infracfg: syscon@10001000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mediatek,mt8135-infracfg", "syscon";
+ reg = <0 0x10001000 0 0x1000>;
+
+ infrarst: reset-controller@30 {
+ #reset-cells = <1>;
+ compatible = "mediatek,mt8135-infracfg-reset",
"mediatek,reset";
+ reg = <0x30 0x8>;
+ };
+ };
+
+ pericfg: syscon@10003000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mediatek,mt8135-pericfg", "syscon";
+ reg = <0 0x10003000 0 0x1000>;
+
+ perirst: reset-controller@00 {
+ #reset-cells = <1>;
+ compatible = "mediatek,mt8135-pericfg-reset",
"mediatek,reset";
+ reg = <0x00 0x8>;
+ };
+ };
+
gic: interrupt-controller@10211000 {
compatible = "arm,cortex-a15-gic";
interrupt-controller;
diff --git a/include/dt-bindings/reset-controller/mt8135-resets.h
b/include/dt-bindings/reset-controller/mt8135-resets.h
new file mode 100644
index 000..1bd15fe
--- /dev/null
+++ b/include/dt-bindings/reset-controller/mt8135-resets.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Flora.Fu
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8135
+#define _DT_BINDINGS_RESET_CONTROLLER_MT8135
+
+/* INFRACFG RESETS */
+#define MT8135_INFRA_EMI_REG_RST0
+#define MT8135_INFRA_DRAMC0_A0_RST 1
+#define MT8135_INFRA_CCIF0_RST 2
+#define MT8135_INFRA_APCIRQ_EINT_RST3
+#define MT8135_INFRA_APXGPT_RST 4
+#define MT8135_INFRA_SCPSYS_RST 5
+#define MT8135_INFRA_CCIF1_RST 6
+#define MT8135_INFRA_PMIC_WRAP_RST 7
+#define MT8135_INFRA_KP_RST 8
+#define MT8135_INFRA_EMI_RST32
+#define MT8135_INFRA_DRAMC0_RST 34
+#define MT8135_INFRA_SMI_RST35
+#define MT8135_INFRA_M4U_RST36
+
+/* PERICFG RESETS */
+#define MT8135_PERI_UART0_SW_RST0
+#define MT8135_PERI_UART1_SW_RST1
+#define MT8135_PERI_UART2_SW_RST2
+#define MT8135_PERI_UART3_SW_RST3
+#define MT8135_PERI_IRDA_SW_RST 4
+#define MT8135_PERI_PTP_SW_RST 5
+#define MT8135_PERI_AP_HIF_SW_RST 6
+#define MT8135_PERI_GPCU_SW_RST 7
+#define MT8135_PERI_MD_HIF_SW_RST 8
+#define MT8135_PERI_NLI_SW_RST 9
+#define MT8135_PERI_AUXADC_SW_RST 10
+#define MT8135_PERI_DMA_SW_RST 11
+#define MT8135_PERI_NFI_SW_RST 14
+#define MT8135_PERI_PWM_SW_RST 15
+#define MT8135_PERI_THERM_SW_RST16
+#define MT8135_PERI_MSDC0_SW_RST17
+#define MT8135_PERI_MSDC1_SW_RST18
+#define MT8135_PERI_MSDC2_SW_RST19
+#define MT8135_PERI_MSDC3_SW_RST20
+#define MT8135_PERI_I2C0_SW_RST 22
+#define MT8135_PERI_I2C1_SW_RST 23
+#define MT8135_PERI_I2C2_SW_RST 24
+#define MT8135_PERI_I2C3_SW_RST 25
+#define MT8135_PERI_I2C4_SW_RST 26
+#define MT8135_PERI_I2C5_SW_RST 27
+#define MT8135_PERI_I2C6_SW_RST 28
+#define MT8135_PERI_USB_SW_RST 29
+#define MT8135_PERI_SPI1_SW_RST 33
+#define MT8135_PERI_PWRAP_BRIDGE_SW_RST 34
+
+#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8135 */
\ No newline at end of f
[PATCH v3 2/3] dt-bindings: Add Reset Controller for MediaTek SoC
Add device tree bindings.
Signed-off-by: Flora Fu
---
.../devicetree/bindings/reset/mediatek,reset.txt | 50 ++
1 file changed, 50 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/mediatek,reset.txt
diff --git a/Documentation/devicetree/bindings/reset/mediatek,reset.txt
b/Documentation/devicetree/bindings/reset/mediatek,reset.txt
new file mode 100644
index 000..a876407
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/mediatek,reset.txt
@@ -0,0 +1,50 @@
+MediaTek SoC Reset Controller
+==
+The reset controller driver accesses registers through the syscon regmap. It
+is a child node of syscon.
+
+Required properties:
+- compatible : "mediatek,reset"
+- #reset-cells: 1
+- reg: The register region can be accessed from syscon. The first parameter is
+ reset base address offset. The second parameter is byte width of reset
registers.
+
+example:
+infracfg: syscon@10001000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mediatek,mt8135-infracfg", "syscon";
+ reg = <0 0x10001000 0 0x1000>;
+
+ infrarst: reset-controller@30 {
+ #reset-cells = <1>;
+ compatible = "mediatek,mt8135-infracfg-reset", "mediatek,reset";
+ reg = <0x30 0x8>;
+ };
+};
+
+Specifying reset lines connected to IP modules
+==
+
+The reset controller(mtk-reset) manages various reset sources. Those device
nodes should
+specify the reset line on the rstc in their resets property, containing a
phandle to the
+rstc device node and a RESET_INDEX specifying which module to reset, as
described in
+reset.txt.
+
+For MediaTek SoC, RESET_INDEX is reset bit defined in INFRACFG or PERICFG
registers.
+
+example:
+pwrap: pwrap@1000f000 {
+ compatible = "mediatek,mt8135-pwrap";
+ reg = <0 0x1000f000 0 0x1000>,
+ <0 0x11017000 0 0x1000>;
+ reg-names = "pwrap-base",
+ "pwrap-bridge-base";
+ resets = < MT8135_INFRA_PMIC_WRAP_RST>,
+ < MT8135_PERI_PWRAP_BRIDGE_SW_RST>;
+ reset-names = "infrarst", "perirst";
+};
+
+Definitions for the supported resets by IC:
+MT8135:
+include/dt-bindings/reset-controller/mt8135-resets.h
--
1.8.1.1.dirty
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[PATCH v3 0/3] Add Reset Controller for MediaTek SoC
Hi, The patch is based on https://lkml.org/lkml/2014/5/27/422 Changes since v2 - Correct #size-cell to be 1. - Add header file "mt8135-resets.h" for supported resets in MT8135. Changes since v1 (1) Patch 1/3: Update reset controller driver's implementation. - rename mt_ prefixes to the prefix mtk_ - use module_platform_driver() macro for driver init. - clean up includes of header files. - reset controll is a child of syscon. Get regamp through its parent node. - rename data->size to data->num_regs. It is number of registers in syscon for reset usage. (2) Patch 2/3: update bindings document according to new dts layout of reset-controller. (3) Patch 3/3: change reset-controller device node as child of syscon. This driver is based on 3.18-rc1. Flora Fu (3): ARM: mediatek: Add Reset Controller for MediaTek SoC dt-bindings: Add Reset Controller for MediaTek SoC ARM: dts: mt8135: Add Reset Controller for MediaTek SoC .../devicetree/bindings/reset/mediatek,reset.txt | 50 arch/arm/boot/dts/mt8135.dtsi | 27 + drivers/reset/Makefile | 1 + drivers/reset/reset-mtk.c | 131 + .../dt-bindings/reset-controller/mt8135-resets.h | 64 ++ 5 files changed, 273 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/mediatek,reset.txt create mode 100644 drivers/reset/reset-mtk.c create mode 100644 include/dt-bindings/reset-controller/mt8135-resets.h -- 1.8.1.1.dirty -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v3 0/3] Add Reset Controller for MediaTek SoC
Hi, The patch is based on https://lkml.org/lkml/2014/5/27/422 Changes since v2 - Correct #size-cell to be 1. - Add header file mt8135-resets.h for supported resets in MT8135. Changes since v1 (1) Patch 1/3: Update reset controller driver's implementation. - rename mt_ prefixes to the prefix mtk_ - use module_platform_driver() macro for driver init. - clean up includes of header files. - reset controll is a child of syscon. Get regamp through its parent node. - rename data-size to data-num_regs. It is number of registers in syscon for reset usage. (2) Patch 2/3: update bindings document according to new dts layout of reset-controller. (3) Patch 3/3: change reset-controller device node as child of syscon. This driver is based on 3.18-rc1. Flora Fu (3): ARM: mediatek: Add Reset Controller for MediaTek SoC dt-bindings: Add Reset Controller for MediaTek SoC ARM: dts: mt8135: Add Reset Controller for MediaTek SoC .../devicetree/bindings/reset/mediatek,reset.txt | 50 arch/arm/boot/dts/mt8135.dtsi | 27 + drivers/reset/Makefile | 1 + drivers/reset/reset-mtk.c | 131 + .../dt-bindings/reset-controller/mt8135-resets.h | 64 ++ 5 files changed, 273 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/mediatek,reset.txt create mode 100644 drivers/reset/reset-mtk.c create mode 100644 include/dt-bindings/reset-controller/mt8135-resets.h -- 1.8.1.1.dirty -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v3 2/3] dt-bindings: Add Reset Controller for MediaTek SoC
Add device tree bindings.
Signed-off-by: Flora Fu flora...@mediatek.com
---
.../devicetree/bindings/reset/mediatek,reset.txt | 50 ++
1 file changed, 50 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/mediatek,reset.txt
diff --git a/Documentation/devicetree/bindings/reset/mediatek,reset.txt
b/Documentation/devicetree/bindings/reset/mediatek,reset.txt
new file mode 100644
index 000..a876407
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/mediatek,reset.txt
@@ -0,0 +1,50 @@
+MediaTek SoC Reset Controller
+==
+The reset controller driver accesses registers through the syscon regmap. It
+is a child node of syscon.
+
+Required properties:
+- compatible : mediatek,reset
+- #reset-cells: 1
+- reg: The register region can be accessed from syscon. The first parameter is
+ reset base address offset. The second parameter is byte width of reset
registers.
+
+example:
+infracfg: syscon@10001000 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = mediatek,mt8135-infracfg, syscon;
+ reg = 0 0x10001000 0 0x1000;
+
+ infrarst: reset-controller@30 {
+ #reset-cells = 1;
+ compatible = mediatek,mt8135-infracfg-reset, mediatek,reset;
+ reg = 0x30 0x8;
+ };
+};
+
+Specifying reset lines connected to IP modules
+==
+
+The reset controller(mtk-reset) manages various reset sources. Those device
nodes should
+specify the reset line on the rstc in their resets property, containing a
phandle to the
+rstc device node and a RESET_INDEX specifying which module to reset, as
described in
+reset.txt.
+
+For MediaTek SoC, RESET_INDEX is reset bit defined in INFRACFG or PERICFG
registers.
+
+example:
+pwrap: pwrap@1000f000 {
+ compatible = mediatek,mt8135-pwrap;
+ reg = 0 0x1000f000 0 0x1000,
+ 0 0x11017000 0 0x1000;
+ reg-names = pwrap-base,
+ pwrap-bridge-base;
+ resets = infrarst MT8135_INFRA_PMIC_WRAP_RST,
+ perirst MT8135_PERI_PWRAP_BRIDGE_SW_RST;
+ reset-names = infrarst, perirst;
+};
+
+Definitions for the supported resets by IC:
+MT8135:
+include/dt-bindings/reset-controller/mt8135-resets.h
--
1.8.1.1.dirty
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[PATCH v3 1/3] ARM: mediatek: Add Reset Controller for MediaTek SoC
Add a driver in reset controller.
Signed-off-by: Flora Fu flora...@mediatek.com
---
drivers/reset/Makefile| 1 +
drivers/reset/reset-mtk.c | 131 ++
2 files changed, 132 insertions(+)
create mode 100644 drivers/reset/reset-mtk.c
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 60fed3d..adcebdf 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -2,3 +2,4 @@ obj-$(CONFIG_RESET_CONTROLLER) += core.o
obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o
obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o
obj-$(CONFIG_ARCH_STI) += sti/
+obj-$(CONFIG_ARCH_MEDIATEK) += reset-mtk.o
diff --git a/drivers/reset/reset-mtk.c b/drivers/reset/reset-mtk.c
new file mode 100644
index 000..7d792ec
--- /dev/null
+++ b/drivers/reset/reset-mtk.c
@@ -0,0 +1,131 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Flora.Fu flora...@mediatek.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/mfd/syscon.h
+#include linux/module.h
+#include linux/of.h
+#include linux/platform_device.h
+#include linux/regmap.h
+#include linux/reset-controller.h
+
+struct mtk_reset_data {
+ struct regmap *regmap;
+ u32 resetbase;
+ u32 num_regs;
+ struct reset_controller_dev rcdev;
+};
+
+static int mtk_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct regmap *regmap;
+ u32 addr;
+ u32 mask;
+ struct mtk_reset_data *data = container_of(rcdev,
+struct mtk_reset_data,
+rcdev);
+ regmap = data-regmap;
+ addr = data-resetbase + ((id / 32) 2);
+ mask = BIT(id % 32);
+
+ return regmap_update_bits(regmap, addr, mask, mask);
+}
+
+static int mtk_reset_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct regmap *regmap;
+ u32 addr;
+ u32 mask;
+ struct mtk_reset_data *data = container_of(rcdev,
+struct mtk_reset_data,
+rcdev);
+
+ regmap = data-regmap;
+ addr = data-resetbase + ((id / 32) 2);
+ mask = BIT(id % 32);
+
+ return regmap_update_bits(regmap, addr, mask, ~mask);
+}
+
+static struct reset_control_ops mtk_reset_ops = {
+ .assert = mtk_reset_assert,
+ .deassert = mtk_reset_deassert,
+};
+
+static int mtk_reset_probe(struct platform_device *pdev)
+{
+ struct mtk_reset_data *data;
+ struct device_node *np = pdev-dev.of_node;
+ struct device_node *syscon_np;
+ u32 reg[2];
+ int ret;
+
+ data = devm_kzalloc(pdev-dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ syscon_np = of_get_parent(np);
+ data-regmap = syscon_node_to_regmap(syscon_np);
+ of_node_put(syscon_np);
+ if (IS_ERR(data-regmap)) {
+ dev_err(pdev-dev, couldn't get syscon-reset regmap\n);
+ return PTR_ERR(data-regmap);
+ }
+ ret = of_property_read_u32_array(np, reg, reg, 2);
+ if (ret) {
+ dev_err(pdev-dev, couldn't read reset base from syscon!\n);
+ return -EINVAL;
+ }
+
+ data-resetbase = reg[0];
+ data-num_regs = reg[1] 2;
+ data-rcdev.owner = THIS_MODULE;
+ data-rcdev.nr_resets = data-num_regs * 32;
+ data-rcdev.ops = mtk_reset_ops;
+ data-rcdev.of_node = pdev-dev.of_node;
+
+ return reset_controller_register(data-rcdev);
+}
+
+static int mtk_reset_remove(struct platform_device *pdev)
+{
+ struct mtk_reset_data *data = platform_get_drvdata(pdev);
+
+ reset_controller_unregister(data-rcdev);
+
+ return 0;
+}
+
+static const struct of_device_id mtk_reset_dt_ids[] = {
+ { .compatible = mediatek,reset, },
+ {},
+};
+MODULE_DEVICE_TABLE(of, mtk_reset_dt_ids);
+
+static struct platform_driver mtk_reset_driver = {
+ .probe = mtk_reset_probe,
+ .remove = mtk_reset_remove,
+ .driver = {
+ .name = mtk-reset,
+ .owner = THIS_MODULE,
+ .of_match_table = mtk_reset_dt_ids,
+ },
+};
+
+module_platform_driver(mtk_reset_driver);
+
+MODULE_AUTHOR(Flora Fu flora...@mediatek.com);
+MODULE_DESCRIPTION(MediaTek SoC Generic Reset Controller);
+MODULE_LICENSE(GPL);
--
1.8.1.1.dirty
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[PATCH v3 3/3] ARM: dts: mt8135: Add Reset Controller for MediaTek SoC
Add reset controller to MT8135 board dts.
Signed-off-by: Flora Fu flora...@mediatek.com
---
arch/arm/boot/dts/mt8135.dtsi | 27 +
.../dt-bindings/reset-controller/mt8135-resets.h | 64 ++
2 files changed, 91 insertions(+)
create mode 100644 include/dt-bindings/reset-controller/mt8135-resets.h
diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi
index 90a56ad..370c8fc 100644
--- a/arch/arm/boot/dts/mt8135.dtsi
+++ b/arch/arm/boot/dts/mt8135.dtsi
@@ -14,6 +14,7 @@
#include dt-bindings/interrupt-controller/irq.h
#include dt-bindings/interrupt-controller/arm-gic.h
+#include dt-bindings/reset-controller/mt8135-resets.h
#include skeleton64.dtsi
/ {
@@ -102,6 +103,32 @@
clock-names = system-clk, rtc-clk;
};
+ infracfg: syscon@10001000 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = mediatek,mt8135-infracfg, syscon;
+ reg = 0 0x10001000 0 0x1000;
+
+ infrarst: reset-controller@30 {
+ #reset-cells = 1;
+ compatible = mediatek,mt8135-infracfg-reset,
mediatek,reset;
+ reg = 0x30 0x8;
+ };
+ };
+
+ pericfg: syscon@10003000 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = mediatek,mt8135-pericfg, syscon;
+ reg = 0 0x10003000 0 0x1000;
+
+ perirst: reset-controller@00 {
+ #reset-cells = 1;
+ compatible = mediatek,mt8135-pericfg-reset,
mediatek,reset;
+ reg = 0x00 0x8;
+ };
+ };
+
gic: interrupt-controller@10211000 {
compatible = arm,cortex-a15-gic;
interrupt-controller;
diff --git a/include/dt-bindings/reset-controller/mt8135-resets.h
b/include/dt-bindings/reset-controller/mt8135-resets.h
new file mode 100644
index 000..1bd15fe
--- /dev/null
+++ b/include/dt-bindings/reset-controller/mt8135-resets.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Flora.Fu flora...@mediatek.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8135
+#define _DT_BINDINGS_RESET_CONTROLLER_MT8135
+
+/* INFRACFG RESETS */
+#define MT8135_INFRA_EMI_REG_RST0
+#define MT8135_INFRA_DRAMC0_A0_RST 1
+#define MT8135_INFRA_CCIF0_RST 2
+#define MT8135_INFRA_APCIRQ_EINT_RST3
+#define MT8135_INFRA_APXGPT_RST 4
+#define MT8135_INFRA_SCPSYS_RST 5
+#define MT8135_INFRA_CCIF1_RST 6
+#define MT8135_INFRA_PMIC_WRAP_RST 7
+#define MT8135_INFRA_KP_RST 8
+#define MT8135_INFRA_EMI_RST32
+#define MT8135_INFRA_DRAMC0_RST 34
+#define MT8135_INFRA_SMI_RST35
+#define MT8135_INFRA_M4U_RST36
+
+/* PERICFG RESETS */
+#define MT8135_PERI_UART0_SW_RST0
+#define MT8135_PERI_UART1_SW_RST1
+#define MT8135_PERI_UART2_SW_RST2
+#define MT8135_PERI_UART3_SW_RST3
+#define MT8135_PERI_IRDA_SW_RST 4
+#define MT8135_PERI_PTP_SW_RST 5
+#define MT8135_PERI_AP_HIF_SW_RST 6
+#define MT8135_PERI_GPCU_SW_RST 7
+#define MT8135_PERI_MD_HIF_SW_RST 8
+#define MT8135_PERI_NLI_SW_RST 9
+#define MT8135_PERI_AUXADC_SW_RST 10
+#define MT8135_PERI_DMA_SW_RST 11
+#define MT8135_PERI_NFI_SW_RST 14
+#define MT8135_PERI_PWM_SW_RST 15
+#define MT8135_PERI_THERM_SW_RST16
+#define MT8135_PERI_MSDC0_SW_RST17
+#define MT8135_PERI_MSDC1_SW_RST18
+#define MT8135_PERI_MSDC2_SW_RST19
+#define MT8135_PERI_MSDC3_SW_RST20
+#define MT8135_PERI_I2C0_SW_RST 22
+#define MT8135_PERI_I2C1_SW_RST 23
+#define MT8135_PERI_I2C2_SW_RST 24
+#define MT8135_PERI_I2C3_SW_RST 25
+#define MT8135_PERI_I2C4_SW_RST 26
+#define MT8135_PERI_I2C5_SW_RST 27
+#define MT8135_PERI_I2C6_SW_RST 28
+#define MT8135_PERI_USB_SW_RST 29
+#define MT8135_PERI_SPI1_SW_RST 33
+#define MT8135_PERI_PWRAP_BRIDGE_SW_RST 34
+
+#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8135 */
\ No newline at end of file
--
1.8.1.1.dirty
--
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[PATCH v2 2/3] dt-bindings: Add Reset Controller for MediaTek SoC
Add device tree bindings.
Signed-off-by: Flora Fu
---
.../devicetree/bindings/reset/mediatek,reset.txt | 45 ++
1 file changed, 45 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/mediatek,reset.txt
diff --git a/Documentation/devicetree/bindings/reset/mediatek,reset.txt
b/Documentation/devicetree/bindings/reset/mediatek,reset.txt
new file mode 100644
index 000..3c5687b
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/mediatek,reset.txt
@@ -0,0 +1,45 @@
+MediaTek SoC Reset Controller
+==
+The reset controller driver accesses registers through the syscon regmap. It
+is a child node of syscon.
+
+Required properties:
+- compatible : "mediatek,reset"
+- #reset-cells: 1
+- reg: The register region can be accessed from syscon. The first parameter is
+ reset base address offset. The second parameter is byte width of reset
registers.
+
+example:
+infracfg: syscon@10001000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mediatek,mt8135-infracfg", "syscon";
+ reg = <0 0x10001000 0 0x1000>;
+
+ infrarst: reset-controller@30 {
+ #reset-cells = <1>;
+ compatible = "mediatek,mt8135-infracfg-reset", "mediatek,reset";
+ reg = <0x30 0x8>;
+ };
+};
+
+Specifying reset lines connected to IP modules
+==
+
+The reset controller(mtk-reset) manages various reset sources. Those device
nodes should
+specify the reset line on the rstc in their resets property, containing a
phandle to the
+rstc device node and a RESET_INDEX specifying which module to reset, as
described in
+reset.txt.
+
+For MediaTek SoC, RESET_INDEX is reset bit defined in INFRACFG or PERICFG
registers.
+
+example:
+pwrap: pwrap@1000f000 {
+ compatible = "mediatek,mt8135-pwrap";
+ reg = <0 0x1000f000 0 0x1000>,
+ <0 0x11017000 0 0x1000>;
+ reg-names = "pwrap-base",
+ "pwrap-bridge-base";
+ resets = < 7>, < 34>;
+ reset-names = "infrarst", "perirst";
+};
--
1.8.1.1.dirty
--
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More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[PATCH v2 3/3] ARM: dts: mt8135: Add Reset Controller for MediaTek SoC
Add reset controller to MT8135 board dts.
Signed-off-by: Flora Fu
---
arch/arm/boot/dts/mt8135.dtsi | 26 ++
1 file changed, 26 insertions(+)
diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi
index 90a56ad..259a2b5 100644
--- a/arch/arm/boot/dts/mt8135.dtsi
+++ b/arch/arm/boot/dts/mt8135.dtsi
@@ -102,6 +102,32 @@
clock-names = "system-clk", "rtc-clk";
};
+ infracfg: syscon@10001000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mediatek,mt8135-infracfg", "syscon";
+ reg = <0 0x10001000 0 0x1000>;
+
+ infrarst: reset-controller@30 {
+ #reset-cells = <1>;
+ compatible = "mediatek,mt8135-infracfg-reset",
"mediatek,reset";
+ reg = <0x30 0x8>;
+ };
+ };
+
+ pericfg: syscon@10003000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mediatek,mt8135-pericfg", "syscon";
+ reg = <0 0x10003000 0 0x1000>;
+
+ perirst: reset-controller@00 {
+ #reset-cells = <1>;
+ compatible = "mediatek,mt8135-pericfg-reset",
"mediatek,reset";
+ reg = <0x00 0x8>;
+ };
+ };
+
gic: interrupt-controller@10211000 {
compatible = "arm,cortex-a15-gic";
interrupt-controller;
--
1.8.1.1.dirty
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Please read the FAQ at http://www.tux.org/lkml/
[PATCH v2 1/3] ARM: mediatek: Add Reset Controller for MediaTek SoC
Add a driver in reset controller.
Signed-off-by: Flora Fu
---
drivers/reset/Makefile| 1 +
drivers/reset/reset-mtk.c | 131 ++
2 files changed, 132 insertions(+)
create mode 100644 drivers/reset/reset-mtk.c
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 60fed3d..adcebdf 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -2,3 +2,4 @@ obj-$(CONFIG_RESET_CONTROLLER) += core.o
obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o
obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o
obj-$(CONFIG_ARCH_STI) += sti/
+obj-$(CONFIG_ARCH_MEDIATEK) += reset-mtk.o
diff --git a/drivers/reset/reset-mtk.c b/drivers/reset/reset-mtk.c
new file mode 100644
index 000..7d792ec
--- /dev/null
+++ b/drivers/reset/reset-mtk.c
@@ -0,0 +1,131 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Flora.Fu
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct mtk_reset_data {
+ struct regmap *regmap;
+ u32 resetbase;
+ u32 num_regs;
+ struct reset_controller_dev rcdev;
+};
+
+static int mtk_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct regmap *regmap;
+ u32 addr;
+ u32 mask;
+ struct mtk_reset_data *data = container_of(rcdev,
+struct mtk_reset_data,
+rcdev);
+ regmap = data->regmap;
+ addr = data->resetbase + ((id / 32) << 2);
+ mask = BIT(id % 32);
+
+ return regmap_update_bits(regmap, addr, mask, mask);
+}
+
+static int mtk_reset_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct regmap *regmap;
+ u32 addr;
+ u32 mask;
+ struct mtk_reset_data *data = container_of(rcdev,
+struct mtk_reset_data,
+rcdev);
+
+ regmap = data->regmap;
+ addr = data->resetbase + ((id / 32) << 2);
+ mask = BIT(id % 32);
+
+ return regmap_update_bits(regmap, addr, mask, ~mask);
+}
+
+static struct reset_control_ops mtk_reset_ops = {
+ .assert = mtk_reset_assert,
+ .deassert = mtk_reset_deassert,
+};
+
+static int mtk_reset_probe(struct platform_device *pdev)
+{
+ struct mtk_reset_data *data;
+ struct device_node *np = pdev->dev.of_node;
+ struct device_node *syscon_np;
+ u32 reg[2];
+ int ret;
+
+ data = devm_kzalloc(>dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ syscon_np = of_get_parent(np);
+ data->regmap = syscon_node_to_regmap(syscon_np);
+ of_node_put(syscon_np);
+ if (IS_ERR(data->regmap)) {
+ dev_err(>dev, "couldn't get syscon-reset regmap\n");
+ return PTR_ERR(data->regmap);
+ }
+ ret = of_property_read_u32_array(np, "reg", reg, 2);
+ if (ret) {
+ dev_err(>dev, "couldn't read reset base from syscon!\n");
+ return -EINVAL;
+ }
+
+ data->resetbase = reg[0];
+ data->num_regs = reg[1] >> 2;
+ data->rcdev.owner = THIS_MODULE;
+ data->rcdev.nr_resets = data->num_regs * 32;
+ data->rcdev.ops = _reset_ops;
+ data->rcdev.of_node = pdev->dev.of_node;
+
+ return reset_controller_register(>rcdev);
+}
+
+static int mtk_reset_remove(struct platform_device *pdev)
+{
+ struct mtk_reset_data *data = platform_get_drvdata(pdev);
+
+ reset_controller_unregister(>rcdev);
+
+ return 0;
+}
+
+static const struct of_device_id mtk_reset_dt_ids[] = {
+ { .compatible = "mediatek,reset", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, mtk_reset_dt_ids);
+
+static struct platform_driver mtk_reset_driver = {
+ .probe = mtk_reset_probe,
+ .remove = mtk_reset_remove,
+ .driver = {
+ .name = "mtk-reset",
+ .owner = THIS_MODULE,
+ .of_match_table = mtk_reset_dt_ids,
+ },
+};
+
+module_platform_driver(mtk_reset_driver);
+
+MODULE_AUTHOR("Flora Fu ");
+MODULE_DESCRIPTION("MediaTek SoC Generic Reset Controller");
+MODULE_LICENSE("GPL");
--
1.8.1.1.dirty
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[PATCH v2 0/3] Add Reset Controller for MediaTek SoC
Hi, The patch modification is base on https://lkml.org/lkml/2014/5/27/422 Changes since v1 (1) Patch 1/3: Update reset controller driver's implementation. - rename mt_ prefixes to the prefix mtk_ - use module_platform_driver() macro for driver init. - clean up includes of header files. - reset controll is a child of syscon. Get regamp through its parent node. - rename data->size to data->num_regs. It is number of registers in syscon for reset usage. (2) Patch 2/3: update bindings document according to new dts layout of reset-controller. (3) Patch 3/3: change reset-controller device node as child of syscon. This driver is based on 3.18-rc1. Flora Fu (3): ARM: mediatek: Add Reset Controller for MediaTek SoC dt-bindings: Add Reset Controller for MediaTek SoC ARM: dts: mt8135: Add Reset Controller for MediaTek SoC .../devicetree/bindings/reset/mediatek,reset.txt | 45 +++ arch/arm/boot/dts/mt8135.dtsi | 26 drivers/reset/Makefile | 1 + drivers/reset/reset-mtk.c | 131 + 4 files changed, 203 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/mediatek,reset.txt create mode 100644 drivers/reset/reset-mtk.c -- 1.8.1.1.dirty -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v2 0/3] Add Reset Controller for MediaTek SoC
Hi, The patch modification is base on https://lkml.org/lkml/2014/5/27/422 Changes since v1 (1) Patch 1/3: Update reset controller driver's implementation. - rename mt_ prefixes to the prefix mtk_ - use module_platform_driver() macro for driver init. - clean up includes of header files. - reset controll is a child of syscon. Get regamp through its parent node. - rename data-size to data-num_regs. It is number of registers in syscon for reset usage. (2) Patch 2/3: update bindings document according to new dts layout of reset-controller. (3) Patch 3/3: change reset-controller device node as child of syscon. This driver is based on 3.18-rc1. Flora Fu (3): ARM: mediatek: Add Reset Controller for MediaTek SoC dt-bindings: Add Reset Controller for MediaTek SoC ARM: dts: mt8135: Add Reset Controller for MediaTek SoC .../devicetree/bindings/reset/mediatek,reset.txt | 45 +++ arch/arm/boot/dts/mt8135.dtsi | 26 drivers/reset/Makefile | 1 + drivers/reset/reset-mtk.c | 131 + 4 files changed, 203 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/mediatek,reset.txt create mode 100644 drivers/reset/reset-mtk.c -- 1.8.1.1.dirty -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v2 1/3] ARM: mediatek: Add Reset Controller for MediaTek SoC
Add a driver in reset controller.
Signed-off-by: Flora Fu flora...@mediatek.com
---
drivers/reset/Makefile| 1 +
drivers/reset/reset-mtk.c | 131 ++
2 files changed, 132 insertions(+)
create mode 100644 drivers/reset/reset-mtk.c
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 60fed3d..adcebdf 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -2,3 +2,4 @@ obj-$(CONFIG_RESET_CONTROLLER) += core.o
obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o
obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o
obj-$(CONFIG_ARCH_STI) += sti/
+obj-$(CONFIG_ARCH_MEDIATEK) += reset-mtk.o
diff --git a/drivers/reset/reset-mtk.c b/drivers/reset/reset-mtk.c
new file mode 100644
index 000..7d792ec
--- /dev/null
+++ b/drivers/reset/reset-mtk.c
@@ -0,0 +1,131 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Flora.Fu flora...@mediatek.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/mfd/syscon.h
+#include linux/module.h
+#include linux/of.h
+#include linux/platform_device.h
+#include linux/regmap.h
+#include linux/reset-controller.h
+
+struct mtk_reset_data {
+ struct regmap *regmap;
+ u32 resetbase;
+ u32 num_regs;
+ struct reset_controller_dev rcdev;
+};
+
+static int mtk_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct regmap *regmap;
+ u32 addr;
+ u32 mask;
+ struct mtk_reset_data *data = container_of(rcdev,
+struct mtk_reset_data,
+rcdev);
+ regmap = data-regmap;
+ addr = data-resetbase + ((id / 32) 2);
+ mask = BIT(id % 32);
+
+ return regmap_update_bits(regmap, addr, mask, mask);
+}
+
+static int mtk_reset_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct regmap *regmap;
+ u32 addr;
+ u32 mask;
+ struct mtk_reset_data *data = container_of(rcdev,
+struct mtk_reset_data,
+rcdev);
+
+ regmap = data-regmap;
+ addr = data-resetbase + ((id / 32) 2);
+ mask = BIT(id % 32);
+
+ return regmap_update_bits(regmap, addr, mask, ~mask);
+}
+
+static struct reset_control_ops mtk_reset_ops = {
+ .assert = mtk_reset_assert,
+ .deassert = mtk_reset_deassert,
+};
+
+static int mtk_reset_probe(struct platform_device *pdev)
+{
+ struct mtk_reset_data *data;
+ struct device_node *np = pdev-dev.of_node;
+ struct device_node *syscon_np;
+ u32 reg[2];
+ int ret;
+
+ data = devm_kzalloc(pdev-dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ syscon_np = of_get_parent(np);
+ data-regmap = syscon_node_to_regmap(syscon_np);
+ of_node_put(syscon_np);
+ if (IS_ERR(data-regmap)) {
+ dev_err(pdev-dev, couldn't get syscon-reset regmap\n);
+ return PTR_ERR(data-regmap);
+ }
+ ret = of_property_read_u32_array(np, reg, reg, 2);
+ if (ret) {
+ dev_err(pdev-dev, couldn't read reset base from syscon!\n);
+ return -EINVAL;
+ }
+
+ data-resetbase = reg[0];
+ data-num_regs = reg[1] 2;
+ data-rcdev.owner = THIS_MODULE;
+ data-rcdev.nr_resets = data-num_regs * 32;
+ data-rcdev.ops = mtk_reset_ops;
+ data-rcdev.of_node = pdev-dev.of_node;
+
+ return reset_controller_register(data-rcdev);
+}
+
+static int mtk_reset_remove(struct platform_device *pdev)
+{
+ struct mtk_reset_data *data = platform_get_drvdata(pdev);
+
+ reset_controller_unregister(data-rcdev);
+
+ return 0;
+}
+
+static const struct of_device_id mtk_reset_dt_ids[] = {
+ { .compatible = mediatek,reset, },
+ {},
+};
+MODULE_DEVICE_TABLE(of, mtk_reset_dt_ids);
+
+static struct platform_driver mtk_reset_driver = {
+ .probe = mtk_reset_probe,
+ .remove = mtk_reset_remove,
+ .driver = {
+ .name = mtk-reset,
+ .owner = THIS_MODULE,
+ .of_match_table = mtk_reset_dt_ids,
+ },
+};
+
+module_platform_driver(mtk_reset_driver);
+
+MODULE_AUTHOR(Flora Fu flora...@mediatek.com);
+MODULE_DESCRIPTION(MediaTek SoC Generic Reset Controller);
+MODULE_LICENSE(GPL);
--
1.8.1.1.dirty
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[PATCH v2 2/3] dt-bindings: Add Reset Controller for MediaTek SoC
Add device tree bindings.
Signed-off-by: Flora Fu flora...@mediatek.com
---
.../devicetree/bindings/reset/mediatek,reset.txt | 45 ++
1 file changed, 45 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/mediatek,reset.txt
diff --git a/Documentation/devicetree/bindings/reset/mediatek,reset.txt
b/Documentation/devicetree/bindings/reset/mediatek,reset.txt
new file mode 100644
index 000..3c5687b
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/mediatek,reset.txt
@@ -0,0 +1,45 @@
+MediaTek SoC Reset Controller
+==
+The reset controller driver accesses registers through the syscon regmap. It
+is a child node of syscon.
+
+Required properties:
+- compatible : mediatek,reset
+- #reset-cells: 1
+- reg: The register region can be accessed from syscon. The first parameter is
+ reset base address offset. The second parameter is byte width of reset
registers.
+
+example:
+infracfg: syscon@10001000 {
+ #address-cells = 1;
+ #size-cells = 0;
+ compatible = mediatek,mt8135-infracfg, syscon;
+ reg = 0 0x10001000 0 0x1000;
+
+ infrarst: reset-controller@30 {
+ #reset-cells = 1;
+ compatible = mediatek,mt8135-infracfg-reset, mediatek,reset;
+ reg = 0x30 0x8;
+ };
+};
+
+Specifying reset lines connected to IP modules
+==
+
+The reset controller(mtk-reset) manages various reset sources. Those device
nodes should
+specify the reset line on the rstc in their resets property, containing a
phandle to the
+rstc device node and a RESET_INDEX specifying which module to reset, as
described in
+reset.txt.
+
+For MediaTek SoC, RESET_INDEX is reset bit defined in INFRACFG or PERICFG
registers.
+
+example:
+pwrap: pwrap@1000f000 {
+ compatible = mediatek,mt8135-pwrap;
+ reg = 0 0x1000f000 0 0x1000,
+ 0 0x11017000 0 0x1000;
+ reg-names = pwrap-base,
+ pwrap-bridge-base;
+ resets = infrarst 7, perirst 34;
+ reset-names = infrarst, perirst;
+};
--
1.8.1.1.dirty
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[PATCH v2 3/3] ARM: dts: mt8135: Add Reset Controller for MediaTek SoC
Add reset controller to MT8135 board dts.
Signed-off-by: Flora Fu flora...@mediatek.com
---
arch/arm/boot/dts/mt8135.dtsi | 26 ++
1 file changed, 26 insertions(+)
diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi
index 90a56ad..259a2b5 100644
--- a/arch/arm/boot/dts/mt8135.dtsi
+++ b/arch/arm/boot/dts/mt8135.dtsi
@@ -102,6 +102,32 @@
clock-names = system-clk, rtc-clk;
};
+ infracfg: syscon@10001000 {
+ #address-cells = 1;
+ #size-cells = 0;
+ compatible = mediatek,mt8135-infracfg, syscon;
+ reg = 0 0x10001000 0 0x1000;
+
+ infrarst: reset-controller@30 {
+ #reset-cells = 1;
+ compatible = mediatek,mt8135-infracfg-reset,
mediatek,reset;
+ reg = 0x30 0x8;
+ };
+ };
+
+ pericfg: syscon@10003000 {
+ #address-cells = 1;
+ #size-cells = 0;
+ compatible = mediatek,mt8135-pericfg, syscon;
+ reg = 0 0x10003000 0 0x1000;
+
+ perirst: reset-controller@00 {
+ #reset-cells = 1;
+ compatible = mediatek,mt8135-pericfg-reset,
mediatek,reset;
+ reg = 0x00 0x8;
+ };
+ };
+
gic: interrupt-controller@10211000 {
compatible = arm,cortex-a15-gic;
interrupt-controller;
--
1.8.1.1.dirty
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Re: [PATCH 3/3] ARM: dts: mt8135: Add Reset Controller for MediaTek SoC
Hi, Philipp,
On Thu, 2014-10-30 at 10:02 +0100, Philipp Zabel wrote:
> Since the reset controller driver accesses registers solely through the
> syscon regmap, I'd prefer to keep with the device tree control graph
> concept and make the reset-controller nodes children of the syscon
> nodes. I've brought this up before: https://lkml.org/lkml/2014/5/27/422,
> and I think this is another case where child node support for syscon
> makes sense:
>
> infracfg: syscon@10001000 {
> compatible = "mediatek,mt8135-infracfg", "syscon";
> reg = <0 0x10001000 0 0x1000>;
>
> infrarst: reset-controller@30 {
> #reset-cells = <1>;
> compatible = "mediatek,mt8135-infracfg-reset",
> "mediatek,reset";
> reg = <0x30 0x8>;
> };
> };
>
> pericfg: syscon@10003000 {
> compatible = "mediatek,mt8135-pericfg", "syscon";
> reg = <0 0x10003000 0 0x1000>;
>
> perirst: reset-controller@00 {
>
> #reset-cells = <1>;
> compatible = "mediatek,mt8135-pericfg-reset",
> "mediatek,reset";
> reg = <0x00 0x8>;
> };
> };
>
> regards
> Philipp
>
Yes, such dts arrangement looks better to me. Implementation in this
version is trying to doing the same thing as your proposal. The new
property "mediatek,syscon-reset = < 0x30 0x8>;" specifies base
address of reset and byte width for controlling resets.
If https://lkml.org/lkml/2014/5/27/422 is adopt into kernel release, it
will be well organized to configure reset controller as child of regmap
which is compatible to syscon.
In reset driver, it is able to get syscon regmap from parent node and
retrieve the address offset and byte with for controlling resets.
---
syscon_np = of_get_parent(np);
data->regmap = syscon_node_to_regmap(syscon_np);
if (IS_ERR(data->regmap)) {
dev_err(>dev, "couldn't get syscon-reset regmap\n");
return PTR_ERR(data->regmap);
}
ret = of_property_read_u32_array(np, "reg", reg, 2);
if (ret) {
dev_err(>dev, "couldn't read reset base from syscon!\n");
return -EINVAL;
}
---
Thanks,
Flora
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Re: [PATCH 3/3] ARM: dts: mt8135: Add Reset Controller for MediaTek SoC
Hi, Philipp,
On Thu, 2014-10-30 at 10:02 +0100, Philipp Zabel wrote:
Since the reset controller driver accesses registers solely through the
syscon regmap, I'd prefer to keep with the device tree control graph
concept and make the reset-controller nodes children of the syscon
nodes. I've brought this up before: https://lkml.org/lkml/2014/5/27/422,
and I think this is another case where child node support for syscon
makes sense:
infracfg: syscon@10001000 {
compatible = mediatek,mt8135-infracfg, syscon;
reg = 0 0x10001000 0 0x1000;
infrarst: reset-controller@30 {
#reset-cells = 1;
compatible = mediatek,mt8135-infracfg-reset,
mediatek,reset;
reg = 0x30 0x8;
};
};
pericfg: syscon@10003000 {
compatible = mediatek,mt8135-pericfg, syscon;
reg = 0 0x10003000 0 0x1000;
perirst: reset-controller@00 {
#reset-cells = 1;
compatible = mediatek,mt8135-pericfg-reset,
mediatek,reset;
reg = 0x00 0x8;
};
};
regards
Philipp
Yes, such dts arrangement looks better to me. Implementation in this
version is trying to doing the same thing as your proposal. The new
property mediatek,syscon-reset = infracfg 0x30 0x8; specifies base
address of reset and byte width for controlling resets.
If https://lkml.org/lkml/2014/5/27/422 is adopt into kernel release, it
will be well organized to configure reset controller as child of regmap
which is compatible to syscon.
In reset driver, it is able to get syscon regmap from parent node and
retrieve the address offset and byte with for controlling resets.
---
syscon_np = of_get_parent(np);
data-regmap = syscon_node_to_regmap(syscon_np);
if (IS_ERR(data-regmap)) {
dev_err(pdev-dev, couldn't get syscon-reset regmap\n);
return PTR_ERR(data-regmap);
}
ret = of_property_read_u32_array(np, reg, reg, 2);
if (ret) {
dev_err(pdev-dev, couldn't read reset base from syscon!\n);
return -EINVAL;
}
---
Thanks,
Flora
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