Re: [PATCH v8 2/2] PCI: amlogic: Add the Amlogic Meson PCIe controller driver
On 2018/12/19 6:47, Bjorn Helgaas wrote:
> On Tue, Dec 18, 2018 at 04:04:46PM +0800, Hanjie Lin wrote:
>> From: Yue Wang
>>
>> The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare
>> PCI core. This patch adds the driver support for Meson PCIe controller.
>
> I don't have any comments on the code itself; just the trivial things
> below. No need to repost for these unless you're changing something
> else.
>
> I thought it looked very pretty overall, thanks for paying attention
> to that!
>
>> +static int meson_size_to_payload(struct meson_pcie *mp, int size)
>> +{
>> +struct device *dev = mp->pci.dev;
>> +
>> +/*
>> + * dwc supports 2^(val+7) payload size, which val is 0~5 default to 1.
>> + * So if input size is not 2^order alignment or less than 2^7 or bigger
>> + * than 2^12, just set to default size 2^(1+7).
>> + */
>> +if (!is_power_of_2(size) || size < 128 || size > 4096) {
>> +dev_warn(dev, "playload size %d, set to default 256\n", size);
>
> s/playload/payload/
>
>> +static void meson_set_max_payload(struct meson_pcie *mp, int size)
>> +{
>> +u32 val = 0;
>
> Unnecessary initialization.
>
>> +int max_payload_size = meson_size_to_payload(mp, size);
>> +
>> +val = meson_elb_readl(mp, PCIE_DEV_CTRL_DEV_STUS);
>
>> +static int meson_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
>> + u32 *val)
>> +{
>> +struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>> +int ret;
>> +
>> +ret = dw_pcie_read(pci->dbi_base + where, size, val);
>> +if (ret != PCIBIOS_SUCCESSFUL)
>> +return ret;
>> +
>> +/*
>> + * There is a bug in the MESON AXG pcie controller whereby software
>> + * cannot programme the PCI_CLASS_DEVICE register, so we must fabricate
>> + * the return value in the config accessors.
>
> s/pcie/PCIe/
> s/programme/program/ (IIUC, "programme" is British and only used as a
> noun, where here you need a verb)
>
>> +static int meson_pcie_link_up(struct dw_pcie *pci)
>> +{
>> +struct meson_pcie *mp = to_meson_pcie(pci);
>> +struct device *dev = pci->dev;
>> +u32 smlh_up = 0;
>> +u32 ltssm_up = 0;
>> +u32 rdlh_up = 0;
>
> Unnecessary initialization of smlh_up, ltssm_up, and rdlh_up.
>
>> +u32 speed_okay = 0;
>> +u32 cnt = 0;
>> +u32 state12, state17;
>> +
>> +do {
>> +state12 = meson_cfg_readl(mp, PCIE_CFG_STATUS12);
>> +state17 = meson_cfg_readl(mp, PCIE_CFG_STATUS17);
>> +smlh_up = IS_SMLH_LINK_UP(state12);
>> +rdlh_up = IS_RDLH_LINK_UP(state12);
>> +ltssm_up = IS_LTSSM_UP(state12);
>
>> +dev_err(dev, "Error: Wait linkup timeout.\n");
>
> Message doesn't match others from driver (capitalization and trailing
> period).
>
>> +dev_err(dev, "failed to get msi irq\n");
>
> s/msi irq/MSI IRQ/
>
>> +ret = meson_add_pcie_port(mp, pdev);
>> +if (ret < 0) {
>> +dev_err(dev, "Add PCIE port failed, %d\n", ret);
>
> s/PCIE/PCIe/
>
> All the messages in this function are capitalized differently than
> other messages in the driver.
>
> Bjorn
>
> .
>
hi Bjorn:
Thanks for the all suggestions and corrections.
There were too many code details unnecessary initialization, typing errors
and coding style etc. I will pay more attention to these rules and code-details
in the future patches also my daily work.
thanks again
hanjie.
Re: [PATCH v8 1/2] dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller
On 2018/12/19 7:14, Martin Blumenstingl wrote: > Hi Rob, Hi Hanjie, > > (sorry for being late with my question) > > On Tue, Dec 18, 2018 at 9:05 AM Hanjie Lin wrote: > [...] >> +- reg-names: Must be >> + - "elbi"External local bus interface registers >> + - "cfg" Meson specific registers >> + - "phy" Meson PCIE PHY registers > I have learned that there are two PHY register designs: > - AXG only has a PCIe PHY > - G12A has a PHY which supports PCIe and USB 3.0. The PCIe part of > this PHY design is compatible with AXG, but this design also supports > a USB 3.0 port (it's an exclusive choice: either PCIe *or* USB 3.0) > > The PCIe controller itself is identical on both, AXG and G12A. > This patch adds support for the AXG PCIe controller and PHY within one > device-tree node. > > For G12A I propose to add a separate "phys" property with a phandle to > the "combo" PCIe and USB3.0 PHY - this can be part of a separate patch > though. > I would like to know whether it's OK that for AXG the PCIe PHY is > described in the same device-tree node as the PCIe controller (in > other words: we're not using a "phys" property here)? > > > Kind Regards > Martin > > . > hi matrin, We do had a dedicated PHY driver for a time at the begining of this patch series, but we decided to remove it and integrate into the controller driver after series reviews and disscussions, and the main reason is it's too overkill to have a dedicated PHY driver which only do the RESET job. Of course we can consider the dedicated PHY driver for G12A upstream in future. thanks hanjie
[PATCH v8 1/2] dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller
From: Yue Wang
The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare
PCI core. This patch adds documentation for the DT bindings in Meson PCIe
controller.
Signed-off-by: Yue Wang
Signed-off-by: Hanjie Lin
Reviewed-by: Rob Herring
---
.../devicetree/bindings/pci/amlogic,meson-pcie.txt | 70 ++
1 file changed, 70 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
diff --git a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
new file mode 100644
index 000..12b18f8
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
@@ -0,0 +1,70 @@
+Amlogic Meson AXG DWC PCIE SoC controller
+
+Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI
core.
+It shares common functions with the PCIe DesignWare core driver and
+inherits common properties defined in
+Documentation/devicetree/bindings/pci/designware-pci.txt.
+
+Additional properties are described here:
+
+Required properties:
+- compatible:
+ should contain "amlogic,axg-pcie" to identify the core.
+- reg:
+ should contain the configuration address space.
+- reg-names: Must be
+ - "elbi"External local bus interface registers
+ - "cfg" Meson specific registers
+ - "phy" Meson PCIE PHY registers
+ - "config" PCIe configuration space
+- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
+- clocks: Must contain an entry for each entry in clock-names.
+- clock-names: Must include the following entries:
+ - "pclk" PCIe GEN 100M PLL clock
+ - "port" PCIe_x(A or B) RC clock gate
+ - "general"PCIe Phy clock
+ - "mipi" PCIe_x(A or B) 100M ref clock gate
+- resets: phandle to the reset lines.
+- reset-names: must contain "phy" "port" and "apb"
+ - "phy" Share PHY reset
+ - "port"Port A or B reset
+ - "apb" Share APB reset
+- device_type:
+ should be "pci". As specified in designware-pcie.txt
+
+
+Example configuration:
+
+ pcie: pcie@f980 {
+ compatible = "amlogic,axg-pcie", "snps,dw-pcie";
+ reg = <0x0 0xf980 0x0 0x40
+ 0x0 0xff646000 0x0 0x2000
+ 0x0 0xff644000 0x0 0x2000
+ 0x0 0xf9f0 0x0 0x10>;
+ reg-names = "elbi", "cfg", "phy", "config";
+ reset-gpios = < GPIOX_19 GPIO_ACTIVE_HIGH>;
+ interrupts = ;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 GIC_SPI 179
IRQ_TYPE_EDGE_RISING>;
+ bus-range = <0x0 0xff>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x8200 0 0 0x0 0xf9c0 0 0x0030>;
+
+ clocks = < CLKID_USB
+CLKID_MIPI_ENABLE
+CLKID_PCIE_A
+CLKID_PCIE_CML_EN0>;
+ clock-names = "general",
+ "mipi",
+ "pclk",
+ "port";
+ resets = < RESET_PCIE_PHY>,
+ < RESET_PCIE_A>,
+ < RESET_PCIE_APB>;
+ reset-names = "phy",
+ "port",
+ "apb";
+ };
--
2.7.4
[PATCH v8 2/2] PCI: amlogic: Add the Amlogic Meson PCIe controller driver
From: Yue Wang The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core. This patch adds the driver support for Meson PCIe controller. Signed-off-by: Yue Wang Signed-off-by: Hanjie Lin --- MAINTAINERS| 7 + drivers/pci/controller/dwc/Kconfig | 10 + drivers/pci/controller/dwc/Makefile| 1 + drivers/pci/controller/dwc/pci-meson.c | 595 + 4 files changed, 613 insertions(+) create mode 100644 drivers/pci/controller/dwc/pci-meson.c diff --git a/MAINTAINERS b/MAINTAINERS index 7fe120f..21ed916 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11600,6 +11600,13 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/lpieralisi/pci.git/ S: Supported F: drivers/pci/controller/ +PCIE DRIVER FOR AMLOGIC MESON +M: Yue Wang +L: linux-...@vger.kernel.org +L: linux-amlo...@lists.infradead.org +S: Maintained +F: drivers/pci/controller/dwc/pci-meson.c + PCIE DRIVER FOR AXIS ARTPEC M: Jesper Nilsson L: linux-arm-ker...@axis.com diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index 91b0194..7800322 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -193,4 +193,14 @@ config PCIE_HISI_STB help Say Y here if you want PCIe controller support on HiSilicon STB SoCs +config PCI_MESON + bool "MESON PCIe controller" + depends on PCI_MSI_IRQ_DOMAIN + select PCIE_DW_HOST + help + Say Y here if you want to enable PCI controller support on Amlogic + SoCs. The PCI controller on Amlogic is based on DesignWare hardware + and therefore the driver re-uses the DesignWare core functions to + implement the driver. + endmenu diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile index fcf91ea..e05a015 100644 --- a/drivers/pci/controller/dwc/Makefile +++ b/drivers/pci/controller/dwc/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o +obj-$(CONFIG_PCI_MESON) += pci-meson.o # The following drivers are for devices that use the generic ACPI # pci_root.c driver but don't support standard ECAM config access. diff --git a/drivers/pci/controller/dwc/pci-meson.c b/drivers/pci/controller/dwc/pci-meson.c new file mode 100644 index 000..7993f9d --- /dev/null +++ b/drivers/pci/controller/dwc/pci-meson.c @@ -0,0 +1,595 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PCIe host controller driver for Amlogic MESON SoCs + * + * Copyright (c) 2018 Amlogic, inc. + * Author: Yue Wang + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pcie-designware.h" + +#define to_meson_pcie(x) dev_get_drvdata((x)->dev) + +/* External local bus interface registers */ +#define PLR_OFFSET 0x700 +#define PCIE_PORT_LINK_CTRL_OFF(PLR_OFFSET + 0x10) +#define FAST_LINK_MODE BIT(7) +#define LINK_CAPABLE_MASK GENMASK(21, 16) +#define LINK_CAPABLE_X1BIT(16) + +#define PCIE_GEN2_CTRL_OFF (PLR_OFFSET + 0x10c) +#define NUM_OF_LANES_MASK GENMASK(12, 8) +#define NUM_OF_LANES_X1BIT(8) +#define DIRECT_SPEED_CHANGEBIT(17) + +#define TYPE1_HDR_OFFSET 0x0 +#define PCIE_STATUS_COMMAND(TYPE1_HDR_OFFSET + 0x04) +#define PCI_IO_EN BIT(0) +#define PCI_MEM_SPACE_EN BIT(1) +#define PCI_BUS_MASTER_EN BIT(2) + +#define PCIE_BASE_ADDR0(TYPE1_HDR_OFFSET + 0x10) +#define PCIE_BASE_ADDR1(TYPE1_HDR_OFFSET + 0x14) + +#define PCIE_CAP_OFFSET0x70 +#define PCIE_DEV_CTRL_DEV_STUS (PCIE_CAP_OFFSET + 0x08) +#define PCIE_CAP_MAX_PAYLOAD_MASK GENMASK(7, 5) +#define PCIE_CAP_MAX_PAYLOAD_SIZE(x) ((x) << 5) +#define PCIE_CAP_MAX_READ_REQ_MASK GENMASK(14, 12) +#define PCIE_CAP_MAX_READ_REQ_SIZE(x) ((x) << 12) + +/* PCIe specific config registers */ +#define PCIE_CFG0 0x0 +#define APP_LTSSM_ENABLE BIT(7) + +#define PCIE_CFG_STATUS12 0x30 +#define IS_SMLH_LINK_UP(x) ((x) & (1 << 6)) +#define IS_RDLH_LINK_UP(x) ((x) & (1 << 16)) +#define IS_LTSSM_UP(x) x) >> 10) & 0x1f) == 0x11) + +#define PCIE_CFG_STATUS17 0x44 +#define PM_CURRENT_STATE(x)(((x) >> 7) & 0x1) + +#define WAIT_LINKUP_TIMEOUT4000 +#define PORT_CLK_RATE 1UL +#define MAX_PAYLOAD_SIZE 256 +#define MAX_READ_REQ_SIZE 256 +#define MESO
[PATCH v8 0/2 RESEND] add the Amlogic Meson PCIe controller driver
The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core. This patchset add the driver and dt-bindings of the controller. Changes since v7: [6] - include files in alphabetical order - get rid of unused MACROs and variables - optimize meson_pcie_link_up() while loop - correct cover-letter version Changes since v6: [5] - fix bad usage of ERR_PTR(ENXIO) - fix meson_pcie_rd_own_conf() when read PCI_CLASS_DEVICE reg Changes since v5: [4] - update MAINTAINER file in alphabetical order - remove meaningless comment - use ERR_PTR function instead of (void *) cast - use is_power_of_2(size) instead of size & (size - 1) - add comment for PCI_CLASS_REVISION register operation Changes since v4: [3] - fix kbuild test robot and compile warnings Changes since v3: [2] - modify subject format - update Kconfig - update MAINTAINER file - add comment and error handle for meson_pcie_get_mem_shared() - drop useless initialization code - add comment for meson_size_to_payload() - optimize meson_pcie_establish_link() return code - optimize meson_pcie_enable_interrupts() redundant function - drop device_attch related code - drop dw_pcie_ops read_dbi and write_dbi function - add error handle for meson_add_pcie_port() when probe Changes since v2: [1] - abandon phy driver, move reset to the controller - use devm_add_action_or_reset() to use clock res - format correcting Changes since v1: [0] - use gpio lib instead open code - move 'apb' and 'port' reset from phy driver - format correcting [0] : https://lkml.kernel.org/r/1534227522-186798-1-git-send-email-hanjie@amlogic.com [1] : https://lkml.kernel.org/r/1535096165-45827-1-git-send-email-hanjie@amlogic.com [2] : https://lkml.kernel.org/r/1537509820-52040-1-git-send-email-hanjie@amlogic.com [3] : https://lkml.kernel.org/r/1538999834-156423-3-git-send-email-hanjie@amlogic.com [4] : https://lkml.kernel.org/r/1539049990-30810-1-git-send-email-hanjie@amlogic.com [5] : https://lkml.kernel.org/r/1542876836-191355-1-git-send-email-hanjie@amlogic.com [6] : https://lkml.kernel.org/r/1544097760-85834-1-git-send-email-hanjie@amlogic.com Yue Wang (2): dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller PCI: amlogic: Add the Amlogic Meson PCIe controller driver .../devicetree/bindings/pci/amlogic,meson-pcie.txt | 70 +++ MAINTAINERS| 7 + drivers/pci/controller/dwc/Kconfig | 10 + drivers/pci/controller/dwc/Makefile| 1 + drivers/pci/controller/dwc/pci-meson.c | 595 + 5 files changed, 683 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt create mode 100644 drivers/pci/controller/dwc/pci-meson.c -- 2.7.4
[PATCH v8 1/2] dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller
From: Yue Wang
The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare
PCI core. This patch adds documentation for the DT bindings in Meson PCIe
controller.
Signed-off-by: Yue Wang
Signed-off-by: Hanjie Lin
Reviewed-by: Rob Herring
---
.../devicetree/bindings/pci/amlogic,meson-pcie.txt | 70 ++
1 file changed, 70 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
diff --git a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
new file mode 100644
index 000..12b18f8
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
@@ -0,0 +1,70 @@
+Amlogic Meson AXG DWC PCIE SoC controller
+
+Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI
core.
+It shares common functions with the PCIe DesignWare core driver and
+inherits common properties defined in
+Documentation/devicetree/bindings/pci/designware-pci.txt.
+
+Additional properties are described here:
+
+Required properties:
+- compatible:
+ should contain "amlogic,axg-pcie" to identify the core.
+- reg:
+ should contain the configuration address space.
+- reg-names: Must be
+ - "elbi"External local bus interface registers
+ - "cfg" Meson specific registers
+ - "phy" Meson PCIE PHY registers
+ - "config" PCIe configuration space
+- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
+- clocks: Must contain an entry for each entry in clock-names.
+- clock-names: Must include the following entries:
+ - "pclk" PCIe GEN 100M PLL clock
+ - "port" PCIe_x(A or B) RC clock gate
+ - "general"PCIe Phy clock
+ - "mipi" PCIe_x(A or B) 100M ref clock gate
+- resets: phandle to the reset lines.
+- reset-names: must contain "phy" "port" and "apb"
+ - "phy" Share PHY reset
+ - "port"Port A or B reset
+ - "apb" Share APB reset
+- device_type:
+ should be "pci". As specified in designware-pcie.txt
+
+
+Example configuration:
+
+ pcie: pcie@f980 {
+ compatible = "amlogic,axg-pcie", "snps,dw-pcie";
+ reg = <0x0 0xf980 0x0 0x40
+ 0x0 0xff646000 0x0 0x2000
+ 0x0 0xff644000 0x0 0x2000
+ 0x0 0xf9f0 0x0 0x10>;
+ reg-names = "elbi", "cfg", "phy", "config";
+ reset-gpios = < GPIOX_19 GPIO_ACTIVE_HIGH>;
+ interrupts = ;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 GIC_SPI 179
IRQ_TYPE_EDGE_RISING>;
+ bus-range = <0x0 0xff>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x8200 0 0 0x0 0xf9c0 0 0x0030>;
+
+ clocks = < CLKID_USB
+CLKID_MIPI_ENABLE
+CLKID_PCIE_A
+CLKID_PCIE_CML_EN0>;
+ clock-names = "general",
+ "mipi",
+ "pclk",
+ "port";
+ resets = < RESET_PCIE_PHY>,
+ < RESET_PCIE_A>,
+ < RESET_PCIE_APB>;
+ reset-names = "phy",
+ "port",
+ "apb";
+ };
--
2.7.4
[PATCH v7 0/2] add the Amlogic Meson PCIe controller driver
The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core. This patchset add the driver and dt-bindings of the controller. Changes since v7: [6] - include files in alphabetical order - get rid of unused MACROs and variables - optimize meson_pcie_link_up() while loop Changes since v6: [5] - fix bad usage of ERR_PTR(ENXIO) - fix meson_pcie_rd_own_conf() when read PCI_CLASS_DEVICE reg Changes since v5: [4] - update MAINTAINER file in alphabetical order - remove meaningless comment - use ERR_PTR function instead of (void *) cast - use is_power_of_2(size) instead of size & (size - 1) - add comment for PCI_CLASS_REVISION register operation Changes since v4: [3] - fix kbuild test robot and compile warnings Changes since v3: [2] - modify subject format - update Kconfig - update MAINTAINER file - add comment and error handle for meson_pcie_get_mem_shared() - drop useless initialization code - add comment for meson_size_to_payload() - optimize meson_pcie_establish_link() return code - optimize meson_pcie_enable_interrupts() redundant function - drop device_attch related code - drop dw_pcie_ops read_dbi and write_dbi function - add error handle for meson_add_pcie_port() when probe Changes since v2: [1] - abandon phy driver, move reset to the controller - use devm_add_action_or_reset() to use clock res - format correcting Changes since v1: [0] - use gpio lib instead open code - move 'apb' and 'port' reset from phy driver - format correcting [0] : https://lkml.kernel.org/r/1534227522-186798-1-git-send-email-hanjie@amlogic.com [1] : https://lkml.kernel.org/r/1535096165-45827-1-git-send-email-hanjie@amlogic.com [2] : https://lkml.kernel.org/r/1537509820-52040-1-git-send-email-hanjie@amlogic.com [3] : https://lkml.kernel.org/r/1538999834-156423-3-git-send-email-hanjie@amlogic.com [4] : https://lkml.kernel.org/r/1539049990-30810-1-git-send-email-hanjie@amlogic.com [5] : https://lkml.kernel.org/r/1542876836-191355-1-git-send-email-hanjie@amlogic.com Yue Wang (2): dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller PCI: amlogic: Add the Amlogic Meson PCIe controller driver .../devicetree/bindings/pci/amlogic,meson-pcie.txt | 70 +++ MAINTAINERS| 7 + drivers/pci/controller/dwc/Kconfig | 10 + drivers/pci/controller/dwc/Makefile| 1 + drivers/pci/controller/dwc/pci-meson.c | 595 + 5 files changed, 683 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt create mode 100644 drivers/pci/controller/dwc/pci-meson.c -- 2.7.4
[PATCH v8 2/2] PCI: amlogic: Add the Amlogic Meson PCIe controller driver
From: Yue Wang The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core. This patch adds the driver support for Meson PCIe controller. Signed-off-by: Yue Wang Signed-off-by: Hanjie Lin --- MAINTAINERS| 7 + drivers/pci/controller/dwc/Kconfig | 10 + drivers/pci/controller/dwc/Makefile| 1 + drivers/pci/controller/dwc/pci-meson.c | 595 + 4 files changed, 613 insertions(+) create mode 100644 drivers/pci/controller/dwc/pci-meson.c diff --git a/MAINTAINERS b/MAINTAINERS index 7fe120f..21ed916 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11600,6 +11600,13 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/lpieralisi/pci.git/ S: Supported F: drivers/pci/controller/ +PCIE DRIVER FOR AMLOGIC MESON +M: Yue Wang +L: linux-...@vger.kernel.org +L: linux-amlo...@lists.infradead.org +S: Maintained +F: drivers/pci/controller/dwc/pci-meson.c + PCIE DRIVER FOR AXIS ARTPEC M: Jesper Nilsson L: linux-arm-ker...@axis.com diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index 91b0194..7800322 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -193,4 +193,14 @@ config PCIE_HISI_STB help Say Y here if you want PCIe controller support on HiSilicon STB SoCs +config PCI_MESON + bool "MESON PCIe controller" + depends on PCI_MSI_IRQ_DOMAIN + select PCIE_DW_HOST + help + Say Y here if you want to enable PCI controller support on Amlogic + SoCs. The PCI controller on Amlogic is based on DesignWare hardware + and therefore the driver re-uses the DesignWare core functions to + implement the driver. + endmenu diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile index fcf91ea..e05a015 100644 --- a/drivers/pci/controller/dwc/Makefile +++ b/drivers/pci/controller/dwc/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o +obj-$(CONFIG_PCI_MESON) += pci-meson.o # The following drivers are for devices that use the generic ACPI # pci_root.c driver but don't support standard ECAM config access. diff --git a/drivers/pci/controller/dwc/pci-meson.c b/drivers/pci/controller/dwc/pci-meson.c new file mode 100644 index 000..7993f9d --- /dev/null +++ b/drivers/pci/controller/dwc/pci-meson.c @@ -0,0 +1,595 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PCIe host controller driver for Amlogic MESON SoCs + * + * Copyright (c) 2018 Amlogic, inc. + * Author: Yue Wang + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pcie-designware.h" + +#define to_meson_pcie(x) dev_get_drvdata((x)->dev) + +/* External local bus interface registers */ +#define PLR_OFFSET 0x700 +#define PCIE_PORT_LINK_CTRL_OFF(PLR_OFFSET + 0x10) +#define FAST_LINK_MODE BIT(7) +#define LINK_CAPABLE_MASK GENMASK(21, 16) +#define LINK_CAPABLE_X1BIT(16) + +#define PCIE_GEN2_CTRL_OFF (PLR_OFFSET + 0x10c) +#define NUM_OF_LANES_MASK GENMASK(12, 8) +#define NUM_OF_LANES_X1BIT(8) +#define DIRECT_SPEED_CHANGEBIT(17) + +#define TYPE1_HDR_OFFSET 0x0 +#define PCIE_STATUS_COMMAND(TYPE1_HDR_OFFSET + 0x04) +#define PCI_IO_EN BIT(0) +#define PCI_MEM_SPACE_EN BIT(1) +#define PCI_BUS_MASTER_EN BIT(2) + +#define PCIE_BASE_ADDR0(TYPE1_HDR_OFFSET + 0x10) +#define PCIE_BASE_ADDR1(TYPE1_HDR_OFFSET + 0x14) + +#define PCIE_CAP_OFFSET0x70 +#define PCIE_DEV_CTRL_DEV_STUS (PCIE_CAP_OFFSET + 0x08) +#define PCIE_CAP_MAX_PAYLOAD_MASK GENMASK(7, 5) +#define PCIE_CAP_MAX_PAYLOAD_SIZE(x) ((x) << 5) +#define PCIE_CAP_MAX_READ_REQ_MASK GENMASK(14, 12) +#define PCIE_CAP_MAX_READ_REQ_SIZE(x) ((x) << 12) + +/* PCIe specific config registers */ +#define PCIE_CFG0 0x0 +#define APP_LTSSM_ENABLE BIT(7) + +#define PCIE_CFG_STATUS12 0x30 +#define IS_SMLH_LINK_UP(x) ((x) & (1 << 6)) +#define IS_RDLH_LINK_UP(x) ((x) & (1 << 16)) +#define IS_LTSSM_UP(x) x) >> 10) & 0x1f) == 0x11) + +#define PCIE_CFG_STATUS17 0x44 +#define PM_CURRENT_STATE(x)(((x) >> 7) & 0x1) + +#define WAIT_LINKUP_TIMEOUT4000 +#define PORT_CLK_RATE 1UL +#define MAX_PAYLOAD_SIZE 256 +#define MAX_READ_REQ_SIZE 256 +#define MESO
Re: [PATCH v7 2/2] PCI: amlogic: Add the Amlogic Meson PCIe controller driver
On 2018/12/14 0:34, Lorenzo Pieralisi wrote: > On Thu, Dec 06, 2018 at 08:02:38PM +0800, Hanjie Lin wrote: >> From: Yue Wang >> >> The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare >> PCI core. This patch adds the driver support for Meson PCIe controller. >> >> Signed-off-by: Yue Wang >> Signed-off-by: Hanjie Lin >> --- >> MAINTAINERS| 7 + >> drivers/pci/controller/dwc/Kconfig | 10 + >> drivers/pci/controller/dwc/Makefile| 1 + >> drivers/pci/controller/dwc/pci-meson.c | 603 >> + >> 4 files changed, 621 insertions(+) >> create mode 100644 drivers/pci/controller/dwc/pci-meson.c >> >> diff --git a/MAINTAINERS b/MAINTAINERS >> index 7fe120f..21ed916 100644 >> --- a/MAINTAINERS >> +++ b/MAINTAINERS >> @@ -11600,6 +11600,13 @@ T: git >> git://git.kernel.org/pub/scm/linux/kernel/git/lpieralisi/pci.git/ >> S: Supported >> F: drivers/pci/controller/ >> >> +PCIE DRIVER FOR AMLOGIC MESON >> +M: Yue Wang >> +L: linux-...@vger.kernel.org >> +L: linux-amlo...@lists.infradead.org >> +S: Maintained >> +F: drivers/pci/controller/dwc/pci-meson.c >> + >> PCIE DRIVER FOR AXIS ARTPEC >> M: Jesper Nilsson >> L: linux-arm-ker...@axis.com >> diff --git a/drivers/pci/controller/dwc/Kconfig >> b/drivers/pci/controller/dwc/Kconfig >> index 91b0194..7800322 100644 >> --- a/drivers/pci/controller/dwc/Kconfig >> +++ b/drivers/pci/controller/dwc/Kconfig >> @@ -193,4 +193,14 @@ config PCIE_HISI_STB >> help >>Say Y here if you want PCIe controller support on HiSilicon STB >> SoCs >> >> +config PCI_MESON >> +bool "MESON PCIe controller" >> +depends on PCI_MSI_IRQ_DOMAIN >> +select PCIE_DW_HOST >> +help >> + Say Y here if you want to enable PCI controller support on Amlogic >> + SoCs. The PCI controller on Amlogic is based on DesignWare hardware >> + and therefore the driver re-uses the DesignWare core functions to >> + implement the driver. >> + >> endmenu >> diff --git a/drivers/pci/controller/dwc/Makefile >> b/drivers/pci/controller/dwc/Makefile >> index fcf91ea..e05a015 100644 >> --- a/drivers/pci/controller/dwc/Makefile >> +++ b/drivers/pci/controller/dwc/Makefile >> @@ -14,6 +14,7 @@ obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o >> obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o >> obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o >> obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o >> +obj-$(CONFIG_PCI_MESON) += pci-meson.o >> >> # The following drivers are for devices that use the generic ACPI >> # pci_root.c driver but don't support standard ECAM config access. >> diff --git a/drivers/pci/controller/dwc/pci-meson.c >> b/drivers/pci/controller/dwc/pci-meson.c >> new file mode 100644 >> index 000..428ed42 >> --- /dev/null >> +++ b/drivers/pci/controller/dwc/pci-meson.c >> @@ -0,0 +1,603 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * PCIe host controller driver for Amlogic MESON SoCs >> + * >> + * Copyright (c) 2018 Amlogic, inc. >> + * Author: Yue Wang >> + */ >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include > > Alphabetical order. > ok, I will modify and pay attention to this later. >> +#include "pcie-designware.h" >> + >> +#define to_meson_pcie(x) dev_get_drvdata((x)->dev) >> + >> +/* External local bus interface registers */ >> +#define PLR_OFFSET 0x700 >> +#define PCIE_PORT_LINK_CTRL_OFF (PLR_OFFSET + 0x10) >> +#define FAST_LINK_MODE BIT(7) >> +#define LINK_CAPABLE_MASK GENMASK(21, 16) >> +#define LINK_CAPABLE_X1 BIT(16) >> + >> +#define PCIE_GEN2_CTRL_OFF (PLR_OFFSET + 0x10c) >> +#define NUM_OF_LANES_MASK GENMASK(12, 8) >> +#define NUM_OF_LANES_X1 BIT(8) >> +#define DIRECT_SPEED_CHANGE BIT(17) >> + >> +#define TYPE1_HDR_OFFSET0x0 >> +#define PCIE_STATUS_COMMAND (TYPE1_HDR_OFFSET + 0x04) >> +#define PCI_IO_EN BIT(0) >> +#define PCI_MEM_SPACE_ENBIT(1) >> +#define PCI_BUS_MASTER_EN BIT(2) >> + >> +#define PCIE_BASE_ADDR0 (TYPE
[PATCH v7 2/2] PCI: amlogic: Add the Amlogic Meson PCIe controller driver
From: Yue Wang The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core. This patch adds the driver support for Meson PCIe controller. Signed-off-by: Yue Wang Signed-off-by: Hanjie Lin --- MAINTAINERS| 7 + drivers/pci/controller/dwc/Kconfig | 10 + drivers/pci/controller/dwc/Makefile| 1 + drivers/pci/controller/dwc/pci-meson.c | 603 + 4 files changed, 621 insertions(+) create mode 100644 drivers/pci/controller/dwc/pci-meson.c diff --git a/MAINTAINERS b/MAINTAINERS index 7fe120f..21ed916 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11600,6 +11600,13 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/lpieralisi/pci.git/ S: Supported F: drivers/pci/controller/ +PCIE DRIVER FOR AMLOGIC MESON +M: Yue Wang +L: linux-...@vger.kernel.org +L: linux-amlo...@lists.infradead.org +S: Maintained +F: drivers/pci/controller/dwc/pci-meson.c + PCIE DRIVER FOR AXIS ARTPEC M: Jesper Nilsson L: linux-arm-ker...@axis.com diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index 91b0194..7800322 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -193,4 +193,14 @@ config PCIE_HISI_STB help Say Y here if you want PCIe controller support on HiSilicon STB SoCs +config PCI_MESON + bool "MESON PCIe controller" + depends on PCI_MSI_IRQ_DOMAIN + select PCIE_DW_HOST + help + Say Y here if you want to enable PCI controller support on Amlogic + SoCs. The PCI controller on Amlogic is based on DesignWare hardware + and therefore the driver re-uses the DesignWare core functions to + implement the driver. + endmenu diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile index fcf91ea..e05a015 100644 --- a/drivers/pci/controller/dwc/Makefile +++ b/drivers/pci/controller/dwc/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o +obj-$(CONFIG_PCI_MESON) += pci-meson.o # The following drivers are for devices that use the generic ACPI # pci_root.c driver but don't support standard ECAM config access. diff --git a/drivers/pci/controller/dwc/pci-meson.c b/drivers/pci/controller/dwc/pci-meson.c new file mode 100644 index 000..428ed42 --- /dev/null +++ b/drivers/pci/controller/dwc/pci-meson.c @@ -0,0 +1,603 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PCIe host controller driver for Amlogic MESON SoCs + * + * Copyright (c) 2018 Amlogic, inc. + * Author: Yue Wang + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pcie-designware.h" + +#define to_meson_pcie(x) dev_get_drvdata((x)->dev) + +/* External local bus interface registers */ +#define PLR_OFFSET 0x700 +#define PCIE_PORT_LINK_CTRL_OFF(PLR_OFFSET + 0x10) +#define FAST_LINK_MODE BIT(7) +#define LINK_CAPABLE_MASK GENMASK(21, 16) +#define LINK_CAPABLE_X1BIT(16) + +#define PCIE_GEN2_CTRL_OFF (PLR_OFFSET + 0x10c) +#define NUM_OF_LANES_MASK GENMASK(12, 8) +#define NUM_OF_LANES_X1BIT(8) +#define DIRECT_SPEED_CHANGEBIT(17) + +#define TYPE1_HDR_OFFSET 0x0 +#define PCIE_STATUS_COMMAND(TYPE1_HDR_OFFSET + 0x04) +#define PCI_IO_EN BIT(0) +#define PCI_MEM_SPACE_EN BIT(1) +#define PCI_BUS_MASTER_EN BIT(2) + +#define PCIE_BASE_ADDR0(TYPE1_HDR_OFFSET + 0x10) +#define PCIE_BASE_ADDR1(TYPE1_HDR_OFFSET + 0x14) + +#define PCIE_CAP_OFFSET0x70 +#define PCIE_DEV_CTRL_DEV_STUS (PCIE_CAP_OFFSET + 0x08) +#define PCIE_CAP_MAX_PAYLOAD_MASK GENMASK(7, 5) +#define PCIE_CAP_MAX_PAYLOAD_SIZE(x) ((x) << 5) +#define PCIE_CAP_MAX_READ_REQ_MASK GENMASK(14, 12) +#define PCIE_CAP_MAX_READ_REQ_SIZE(x) ((x) << 12) + +#define PCI_CLASS_REVISION_MASKGENMASK(7, 0) + +/* PCIe specific config registers */ +#define PCIE_CFG0 0x0 +#define APP_LTSSM_ENABLE BIT(7) + +#define PCIE_CFG_STATUS12 0x30 +#define IS_SMLH_LINK_UP(x) ((x) & (1 << 6)) +#define IS_RDLH_LINK_UP(x) ((x) & (1 << 16)) +#define IS_LTSSM_UP(x) x) >> 10) & 0x1f) == 0x11) + +#define PCIE_CFG_STATUS17 0x44 +#define PM_CURRENT_STATE(x)(((x) >> 7) & 0x1) + +#define WAIT_LINKUP_TIMEOUT2000 +#define PORT_CLK_RATE 1UL +#define MAX_PAYLOAD_SIZE 256
[PATCH v7 2/2] PCI: amlogic: Add the Amlogic Meson PCIe controller driver
From: Yue Wang The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core. This patch adds the driver support for Meson PCIe controller. Signed-off-by: Yue Wang Signed-off-by: Hanjie Lin --- MAINTAINERS| 7 + drivers/pci/controller/dwc/Kconfig | 10 + drivers/pci/controller/dwc/Makefile| 1 + drivers/pci/controller/dwc/pci-meson.c | 603 + 4 files changed, 621 insertions(+) create mode 100644 drivers/pci/controller/dwc/pci-meson.c diff --git a/MAINTAINERS b/MAINTAINERS index 7fe120f..21ed916 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11600,6 +11600,13 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/lpieralisi/pci.git/ S: Supported F: drivers/pci/controller/ +PCIE DRIVER FOR AMLOGIC MESON +M: Yue Wang +L: linux-...@vger.kernel.org +L: linux-amlo...@lists.infradead.org +S: Maintained +F: drivers/pci/controller/dwc/pci-meson.c + PCIE DRIVER FOR AXIS ARTPEC M: Jesper Nilsson L: linux-arm-ker...@axis.com diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index 91b0194..7800322 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -193,4 +193,14 @@ config PCIE_HISI_STB help Say Y here if you want PCIe controller support on HiSilicon STB SoCs +config PCI_MESON + bool "MESON PCIe controller" + depends on PCI_MSI_IRQ_DOMAIN + select PCIE_DW_HOST + help + Say Y here if you want to enable PCI controller support on Amlogic + SoCs. The PCI controller on Amlogic is based on DesignWare hardware + and therefore the driver re-uses the DesignWare core functions to + implement the driver. + endmenu diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile index fcf91ea..e05a015 100644 --- a/drivers/pci/controller/dwc/Makefile +++ b/drivers/pci/controller/dwc/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o +obj-$(CONFIG_PCI_MESON) += pci-meson.o # The following drivers are for devices that use the generic ACPI # pci_root.c driver but don't support standard ECAM config access. diff --git a/drivers/pci/controller/dwc/pci-meson.c b/drivers/pci/controller/dwc/pci-meson.c new file mode 100644 index 000..428ed42 --- /dev/null +++ b/drivers/pci/controller/dwc/pci-meson.c @@ -0,0 +1,603 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PCIe host controller driver for Amlogic MESON SoCs + * + * Copyright (c) 2018 Amlogic, inc. + * Author: Yue Wang + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pcie-designware.h" + +#define to_meson_pcie(x) dev_get_drvdata((x)->dev) + +/* External local bus interface registers */ +#define PLR_OFFSET 0x700 +#define PCIE_PORT_LINK_CTRL_OFF(PLR_OFFSET + 0x10) +#define FAST_LINK_MODE BIT(7) +#define LINK_CAPABLE_MASK GENMASK(21, 16) +#define LINK_CAPABLE_X1BIT(16) + +#define PCIE_GEN2_CTRL_OFF (PLR_OFFSET + 0x10c) +#define NUM_OF_LANES_MASK GENMASK(12, 8) +#define NUM_OF_LANES_X1BIT(8) +#define DIRECT_SPEED_CHANGEBIT(17) + +#define TYPE1_HDR_OFFSET 0x0 +#define PCIE_STATUS_COMMAND(TYPE1_HDR_OFFSET + 0x04) +#define PCI_IO_EN BIT(0) +#define PCI_MEM_SPACE_EN BIT(1) +#define PCI_BUS_MASTER_EN BIT(2) + +#define PCIE_BASE_ADDR0(TYPE1_HDR_OFFSET + 0x10) +#define PCIE_BASE_ADDR1(TYPE1_HDR_OFFSET + 0x14) + +#define PCIE_CAP_OFFSET0x70 +#define PCIE_DEV_CTRL_DEV_STUS (PCIE_CAP_OFFSET + 0x08) +#define PCIE_CAP_MAX_PAYLOAD_MASK GENMASK(7, 5) +#define PCIE_CAP_MAX_PAYLOAD_SIZE(x) ((x) << 5) +#define PCIE_CAP_MAX_READ_REQ_MASK GENMASK(14, 12) +#define PCIE_CAP_MAX_READ_REQ_SIZE(x) ((x) << 12) + +#define PCI_CLASS_REVISION_MASKGENMASK(7, 0) + +/* PCIe specific config registers */ +#define PCIE_CFG0 0x0 +#define APP_LTSSM_ENABLE BIT(7) + +#define PCIE_CFG_STATUS12 0x30 +#define IS_SMLH_LINK_UP(x) ((x) & (1 << 6)) +#define IS_RDLH_LINK_UP(x) ((x) & (1 << 16)) +#define IS_LTSSM_UP(x) x) >> 10) & 0x1f) == 0x11) + +#define PCIE_CFG_STATUS17 0x44 +#define PM_CURRENT_STATE(x)(((x) >> 7) & 0x1) + +#define WAIT_LINKUP_TIMEOUT2000 +#define PORT_CLK_RATE 1UL +#define MAX_PAYLOAD_SIZE 256
[PATCH v7 0/2] add the Amlogic Meson PCIe controller driver
The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core. This patchset add the driver and dt-bindings of the controller. Changes since v6: [5] - fix bad usage of ERR_PTR(ENXIO) - fix meson_pcie_rd_own_conf() when read PCI_CLASS_DEVICE reg Changes since v5: [4] - update MAINTAINER file in alphabetical order - remove meaningless comment - use ERR_PTR function instead of (void *) cast - use is_power_of_2(size) instead of size & (size - 1) - add comment for PCI_CLASS_REVISION register operation Changes since v4: [3] - fix kbuild test robot and compile warnings Changes since v3: [2] - modify subject format - update Kconfig - update MAINTAINER file - add comment and error handle for meson_pcie_get_mem_shared() - drop useless initialization code - add comment for meson_size_to_payload() - optimize meson_pcie_establish_link() return code - optimize meson_pcie_enable_interrupts() redundant function - drop device_attch related code - drop dw_pcie_ops read_dbi and write_dbi function - add error handle for meson_add_pcie_port() when probe Changes since v2: [1] - abandon phy driver, move reset to the controller - use devm_add_action_or_reset() to use clock res - format correcting Changes since v1: [0] - use gpio lib instead open code - move 'apb' and 'port' reset from phy driver - format correcting [0] : https://lkml.kernel.org/r/1534227522-186798-1-git-send-email-hanjie@amlogic.com [1] : https://lkml.kernel.org/r/1535096165-45827-1-git-send-email-hanjie@amlogic.com [2] : https://lkml.kernel.org/r/1537509820-52040-1-git-send-email-hanjie@amlogic.com [3] : https://lkml.kernel.org/r/1538999834-156423-3-git-send-email-hanjie@amlogic.com [4] : https://lkml.kernel.org/r/1539049990-30810-1-git-send-email-hanjie@amlogic.com [5] : https://lkml.kernel.org/r/1542876836-191355-1-git-send-email-hanjie@amlogic.com Yue Wang (2): dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller PCI: amlogic: Add the Amlogic Meson PCIe controller driver .../devicetree/bindings/pci/amlogic,meson-pcie.txt | 70 +++ MAINTAINERS| 7 + drivers/pci/controller/dwc/Kconfig | 10 + drivers/pci/controller/dwc/Makefile| 1 + drivers/pci/controller/dwc/pci-meson.c | 603 + 5 files changed, 691 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt create mode 100644 drivers/pci/controller/dwc/pci-meson.c -- 2.7.4
[PATCH v7 1/2] dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller
From: Yue Wang
The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare
PCI core. This patch adds documentation for the DT bindings in Meson PCIe
controller.
Signed-off-by: Yue Wang
Signed-off-by: Hanjie Lin
Reviewed-by: Rob Herring
---
.../devicetree/bindings/pci/amlogic,meson-pcie.txt | 70 ++
1 file changed, 70 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
diff --git a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
new file mode 100644
index 000..12b18f8
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
@@ -0,0 +1,70 @@
+Amlogic Meson AXG DWC PCIE SoC controller
+
+Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI
core.
+It shares common functions with the PCIe DesignWare core driver and
+inherits common properties defined in
+Documentation/devicetree/bindings/pci/designware-pci.txt.
+
+Additional properties are described here:
+
+Required properties:
+- compatible:
+ should contain "amlogic,axg-pcie" to identify the core.
+- reg:
+ should contain the configuration address space.
+- reg-names: Must be
+ - "elbi"External local bus interface registers
+ - "cfg" Meson specific registers
+ - "phy" Meson PCIE PHY registers
+ - "config" PCIe configuration space
+- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
+- clocks: Must contain an entry for each entry in clock-names.
+- clock-names: Must include the following entries:
+ - "pclk" PCIe GEN 100M PLL clock
+ - "port" PCIe_x(A or B) RC clock gate
+ - "general"PCIe Phy clock
+ - "mipi" PCIe_x(A or B) 100M ref clock gate
+- resets: phandle to the reset lines.
+- reset-names: must contain "phy" "port" and "apb"
+ - "phy" Share PHY reset
+ - "port"Port A or B reset
+ - "apb" Share APB reset
+- device_type:
+ should be "pci". As specified in designware-pcie.txt
+
+
+Example configuration:
+
+ pcie: pcie@f980 {
+ compatible = "amlogic,axg-pcie", "snps,dw-pcie";
+ reg = <0x0 0xf980 0x0 0x40
+ 0x0 0xff646000 0x0 0x2000
+ 0x0 0xff644000 0x0 0x2000
+ 0x0 0xf9f0 0x0 0x10>;
+ reg-names = "elbi", "cfg", "phy", "config";
+ reset-gpios = < GPIOX_19 GPIO_ACTIVE_HIGH>;
+ interrupts = ;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 GIC_SPI 179
IRQ_TYPE_EDGE_RISING>;
+ bus-range = <0x0 0xff>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x8200 0 0 0x0 0xf9c0 0 0x0030>;
+
+ clocks = < CLKID_USB
+CLKID_MIPI_ENABLE
+CLKID_PCIE_A
+CLKID_PCIE_CML_EN0>;
+ clock-names = "general",
+ "mipi",
+ "pclk",
+ "port";
+ resets = < RESET_PCIE_PHY>,
+ < RESET_PCIE_A>,
+ < RESET_PCIE_APB>;
+ reset-names = "phy",
+ "port",
+ "apb";
+ };
--
2.7.4
[PATCH v7 0/2] add the Amlogic Meson PCIe controller driver
The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core. This patchset add the driver and dt-bindings of the controller. Changes since v6: [5] - fix bad usage of ERR_PTR(ENXIO) - fix meson_pcie_rd_own_conf() when read PCI_CLASS_DEVICE reg Changes since v5: [4] - update MAINTAINER file in alphabetical order - remove meaningless comment - use ERR_PTR function instead of (void *) cast - use is_power_of_2(size) instead of size & (size - 1) - add comment for PCI_CLASS_REVISION register operation Changes since v4: [3] - fix kbuild test robot and compile warnings Changes since v3: [2] - modify subject format - update Kconfig - update MAINTAINER file - add comment and error handle for meson_pcie_get_mem_shared() - drop useless initialization code - add comment for meson_size_to_payload() - optimize meson_pcie_establish_link() return code - optimize meson_pcie_enable_interrupts() redundant function - drop device_attch related code - drop dw_pcie_ops read_dbi and write_dbi function - add error handle for meson_add_pcie_port() when probe Changes since v2: [1] - abandon phy driver, move reset to the controller - use devm_add_action_or_reset() to use clock res - format correcting Changes since v1: [0] - use gpio lib instead open code - move 'apb' and 'port' reset from phy driver - format correcting [0] : https://lkml.kernel.org/r/1534227522-186798-1-git-send-email-hanjie@amlogic.com [1] : https://lkml.kernel.org/r/1535096165-45827-1-git-send-email-hanjie@amlogic.com [2] : https://lkml.kernel.org/r/1537509820-52040-1-git-send-email-hanjie@amlogic.com [3] : https://lkml.kernel.org/r/1538999834-156423-3-git-send-email-hanjie@amlogic.com [4] : https://lkml.kernel.org/r/1539049990-30810-1-git-send-email-hanjie@amlogic.com [5] : https://lkml.kernel.org/r/1542876836-191355-1-git-send-email-hanjie@amlogic.com Yue Wang (2): dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller PCI: amlogic: Add the Amlogic Meson PCIe controller driver .../devicetree/bindings/pci/amlogic,meson-pcie.txt | 70 +++ MAINTAINERS| 7 + drivers/pci/controller/dwc/Kconfig | 10 + drivers/pci/controller/dwc/Makefile| 1 + drivers/pci/controller/dwc/pci-meson.c | 603 + 5 files changed, 691 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt create mode 100644 drivers/pci/controller/dwc/pci-meson.c -- 2.7.4
[PATCH v7 1/2] dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller
From: Yue Wang
The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare
PCI core. This patch adds documentation for the DT bindings in Meson PCIe
controller.
Signed-off-by: Yue Wang
Signed-off-by: Hanjie Lin
Reviewed-by: Rob Herring
---
.../devicetree/bindings/pci/amlogic,meson-pcie.txt | 70 ++
1 file changed, 70 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
diff --git a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
new file mode 100644
index 000..12b18f8
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
@@ -0,0 +1,70 @@
+Amlogic Meson AXG DWC PCIE SoC controller
+
+Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI
core.
+It shares common functions with the PCIe DesignWare core driver and
+inherits common properties defined in
+Documentation/devicetree/bindings/pci/designware-pci.txt.
+
+Additional properties are described here:
+
+Required properties:
+- compatible:
+ should contain "amlogic,axg-pcie" to identify the core.
+- reg:
+ should contain the configuration address space.
+- reg-names: Must be
+ - "elbi"External local bus interface registers
+ - "cfg" Meson specific registers
+ - "phy" Meson PCIE PHY registers
+ - "config" PCIe configuration space
+- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
+- clocks: Must contain an entry for each entry in clock-names.
+- clock-names: Must include the following entries:
+ - "pclk" PCIe GEN 100M PLL clock
+ - "port" PCIe_x(A or B) RC clock gate
+ - "general"PCIe Phy clock
+ - "mipi" PCIe_x(A or B) 100M ref clock gate
+- resets: phandle to the reset lines.
+- reset-names: must contain "phy" "port" and "apb"
+ - "phy" Share PHY reset
+ - "port"Port A or B reset
+ - "apb" Share APB reset
+- device_type:
+ should be "pci". As specified in designware-pcie.txt
+
+
+Example configuration:
+
+ pcie: pcie@f980 {
+ compatible = "amlogic,axg-pcie", "snps,dw-pcie";
+ reg = <0x0 0xf980 0x0 0x40
+ 0x0 0xff646000 0x0 0x2000
+ 0x0 0xff644000 0x0 0x2000
+ 0x0 0xf9f0 0x0 0x10>;
+ reg-names = "elbi", "cfg", "phy", "config";
+ reset-gpios = < GPIOX_19 GPIO_ACTIVE_HIGH>;
+ interrupts = ;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 GIC_SPI 179
IRQ_TYPE_EDGE_RISING>;
+ bus-range = <0x0 0xff>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x8200 0 0 0x0 0xf9c0 0 0x0030>;
+
+ clocks = < CLKID_USB
+CLKID_MIPI_ENABLE
+CLKID_PCIE_A
+CLKID_PCIE_CML_EN0>;
+ clock-names = "general",
+ "mipi",
+ "pclk",
+ "port";
+ resets = < RESET_PCIE_PHY>,
+ < RESET_PCIE_A>,
+ < RESET_PCIE_APB>;
+ reset-names = "phy",
+ "port",
+ "apb";
+ };
--
2.7.4
Re: [PATCH v6 2/2] PCI: amlogic: Add the Amlogic Meson PCIe controller driver
On 2018/12/4 20:00, Lorenzo Pieralisi wrote:
> On Tue, Dec 04, 2018 at 06:40:55PM +0800, Hanjie Lin wrote:
>>
>>
>> On 2018/12/4 6:57, Bjorn Helgaas wrote:
>>> On Mon, Dec 03, 2018 at 04:41:50PM +, Lorenzo Pieralisi wrote:
>>>> On Thu, Nov 22, 2018 at 04:53:54PM +0800, Hanjie Lin wrote:
>>>>
>>>> [...]
>>>>
>>>>> +static int meson_pcie_rd_own_conf(struct pcie_port *pp, int where, int
>>>>> size,
>>>>> + u32 *val)
>>>>> +{
>>>>> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>>>>> +
>>>>> + /*
>>>>> + * there is a bug of MESON AXG pcie controller that software can not
>>>>> + * programe PCI_CLASS_DEVICE register, so we must return a fake right
>>>>> + * value to ensure driver could probe successfully.
>>>>> + */
>>>>> + if (where == PCI_CLASS_REVISION) {
>>>>> + *val = readl(pci->dbi_base + PCI_CLASS_REVISION);
>>>>> + /* keep revision id */
>>>>> + *val &= PCI_CLASS_REVISION_MASK;
>>>>> + *val |= PCI_CLASS_BRIDGE_PCI << 16;
>>>>> + return PCIBIOS_SUCCESSFUL;
>>>>> + }
>>>>
>>>> As I said before, this looks broken. If this code (or other drivers with
>>>> the same broken assumptions, eg dwc/pcie-qcom.c) carries out a, say,
>>>> byte sized config access of eg PCI_CLASS_DEVICE you will get junk out of
>>>> it according to your comment above.
>>>>
>>>> I would like to pick Bjorn's brain on this to see what we can really do
>>>> to fix this (and other) drivers.
>>>
>>> - Check to see whether you're reading anything in the 32-bit dword at
>>> offset 0x08.
>>>
>>> - Do the 32-bit readl().
>>>
>>> - Insert the correct Sub-Class and Base Class code (you also throw
>>> away the Programming Interface; not sure why that is)
>>>
>>> - If you're reading something smaller than 32 bits, mask & shift as
>>> needed. pci_bridge_emul_conf_read() does something similar that
>>> you might be able to copy.
>>>
>>> Out of curiosity, what code depends on PCI_CLASS_BRIDGE_PCI? There
>>> are several places in the kernel that currently depend on it, but I
>>> think several of them *should* be checking dev->hdr_type to identify a
>>> type 1 header instead.
>>>
>>> Bjorn
>>>
>>> .
>>>
>>
>> Yes, it would be broken in particular scenes(eg: read 1 or 2 bytes from
>> 0xa/PCI_CLASS_DEVICE)
>> that I didn't considered.
>>
>> As your suggestion, I consider some code below may help this issue:
>> 1, First call dw_pcie_read() help to read 1/2/4 bytes from register,
>>request all other *size* bytes will return error and dw_pcie_read()
>>will also check register alignment.
>>
>> 2, If dw_pcie_read() return success and *where* is 0x8/PCI_CLASS_DEVICE or
>> 0xa/PCI_CLASS_REVISION,
>>we may need to correct class code.
>>As PCI_CLASS_REVISION is two-bytes register, so only when read 4 bytes
>> from 0x8/PCI_CLASS_DEVICE
>>or read 2 bytes from 0xa/PCI_CLASS_REVISION we should correct the class
>> code.
>>
>> ps: read 1 byte from 0xa/PCI_CLASS_REVISION or 0xb will get incorrect value.
>
> You can fix this too.
>
>> static int meson_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
>> u32 *val)
>> {
>> struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>> int ret;
>>
>> ret = dw_pcie_read(pci->dbi_base + where, size, val);
>> if (ret != PCIBIOS_SUCCESSFUL)
>> return ret;
>>
>> /*
>> * there is a bug of MESON AXG pcie controller that software can not
>> * programe PCI_CLASS_DEVICE register, so we must return a fake right
>
> "There is a bug in the MESON AXG pcie controller whereby software cannot
> programme the PCI_CLASS_DEVICE register, so we must fabricate the return
> value in the config accessors."
>
Ok, it's more clear :)
>> * value to ensure driver could probe successfully.
>> */
>> if (where == PCI_CLASS_REVISION && size == 4)
>> *val = (PCI_CLASS_BRIDGE_PCI << 16) | (*val & 0x);
>> else if (where == PCI_CLASS_DEVICE && size == 2)
>> *val = PCI_CLASS_BRIDGE_PCI;
>
> You can further filter it with (where & 0x1) == PCI_CLASS_DEVICE
> and handle the size accordingly, so that even a byte access would
> work, for completeness.
>
> Lorenzo
>
Of course, I will add process to handle one-byte access from 0xa/0xb register
in next-version.
thanks.
hanjie
>> return PCIBIOS_SUCCESSFUL;
>> }
>>
>> 3, We must ensure class is PCI_CLASS_BRIDGE_PCI except right hdr_type,
>>or pci_setup_device() will get failed:
>>
>>...
>>class = pci_class(dev);
>>dev->revision = class & 0xff;
>>dev->class = class >> 8; /* upper 3 bytes */
>>
>>switch (dev->hdr_type) { /* header type */
>>...
>>case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
>> if (class != PCI_CLASS_BRIDGE_PCI) /* class must be
>> PCI_CLASS_BRIDGE_PCI */
>> goto bad;
>>
>>
>> thanks.
>>
>> hanjie
>
> .
>
Re: [PATCH v6 2/2] PCI: amlogic: Add the Amlogic Meson PCIe controller driver
On 2018/12/4 20:00, Lorenzo Pieralisi wrote:
> On Tue, Dec 04, 2018 at 06:40:55PM +0800, Hanjie Lin wrote:
>>
>>
>> On 2018/12/4 6:57, Bjorn Helgaas wrote:
>>> On Mon, Dec 03, 2018 at 04:41:50PM +, Lorenzo Pieralisi wrote:
>>>> On Thu, Nov 22, 2018 at 04:53:54PM +0800, Hanjie Lin wrote:
>>>>
>>>> [...]
>>>>
>>>>> +static int meson_pcie_rd_own_conf(struct pcie_port *pp, int where, int
>>>>> size,
>>>>> + u32 *val)
>>>>> +{
>>>>> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>>>>> +
>>>>> + /*
>>>>> + * there is a bug of MESON AXG pcie controller that software can not
>>>>> + * programe PCI_CLASS_DEVICE register, so we must return a fake right
>>>>> + * value to ensure driver could probe successfully.
>>>>> + */
>>>>> + if (where == PCI_CLASS_REVISION) {
>>>>> + *val = readl(pci->dbi_base + PCI_CLASS_REVISION);
>>>>> + /* keep revision id */
>>>>> + *val &= PCI_CLASS_REVISION_MASK;
>>>>> + *val |= PCI_CLASS_BRIDGE_PCI << 16;
>>>>> + return PCIBIOS_SUCCESSFUL;
>>>>> + }
>>>>
>>>> As I said before, this looks broken. If this code (or other drivers with
>>>> the same broken assumptions, eg dwc/pcie-qcom.c) carries out a, say,
>>>> byte sized config access of eg PCI_CLASS_DEVICE you will get junk out of
>>>> it according to your comment above.
>>>>
>>>> I would like to pick Bjorn's brain on this to see what we can really do
>>>> to fix this (and other) drivers.
>>>
>>> - Check to see whether you're reading anything in the 32-bit dword at
>>> offset 0x08.
>>>
>>> - Do the 32-bit readl().
>>>
>>> - Insert the correct Sub-Class and Base Class code (you also throw
>>> away the Programming Interface; not sure why that is)
>>>
>>> - If you're reading something smaller than 32 bits, mask & shift as
>>> needed. pci_bridge_emul_conf_read() does something similar that
>>> you might be able to copy.
>>>
>>> Out of curiosity, what code depends on PCI_CLASS_BRIDGE_PCI? There
>>> are several places in the kernel that currently depend on it, but I
>>> think several of them *should* be checking dev->hdr_type to identify a
>>> type 1 header instead.
>>>
>>> Bjorn
>>>
>>> .
>>>
>>
>> Yes, it would be broken in particular scenes(eg: read 1 or 2 bytes from
>> 0xa/PCI_CLASS_DEVICE)
>> that I didn't considered.
>>
>> As your suggestion, I consider some code below may help this issue:
>> 1, First call dw_pcie_read() help to read 1/2/4 bytes from register,
>>request all other *size* bytes will return error and dw_pcie_read()
>>will also check register alignment.
>>
>> 2, If dw_pcie_read() return success and *where* is 0x8/PCI_CLASS_DEVICE or
>> 0xa/PCI_CLASS_REVISION,
>>we may need to correct class code.
>>As PCI_CLASS_REVISION is two-bytes register, so only when read 4 bytes
>> from 0x8/PCI_CLASS_DEVICE
>>or read 2 bytes from 0xa/PCI_CLASS_REVISION we should correct the class
>> code.
>>
>> ps: read 1 byte from 0xa/PCI_CLASS_REVISION or 0xb will get incorrect value.
>
> You can fix this too.
>
>> static int meson_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
>> u32 *val)
>> {
>> struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>> int ret;
>>
>> ret = dw_pcie_read(pci->dbi_base + where, size, val);
>> if (ret != PCIBIOS_SUCCESSFUL)
>> return ret;
>>
>> /*
>> * there is a bug of MESON AXG pcie controller that software can not
>> * programe PCI_CLASS_DEVICE register, so we must return a fake right
>
> "There is a bug in the MESON AXG pcie controller whereby software cannot
> programme the PCI_CLASS_DEVICE register, so we must fabricate the return
> value in the config accessors."
>
Ok, it's more clear :)
>> * value to ensure driver could probe successfully.
>> */
>> if (where == PCI_CLASS_REVISION && size == 4)
>> *val = (PCI_CLASS_BRIDGE_PCI << 16) | (*val & 0x);
>> else if (where == PCI_CLASS_DEVICE && size == 2)
>> *val = PCI_CLASS_BRIDGE_PCI;
>
> You can further filter it with (where & 0x1) == PCI_CLASS_DEVICE
> and handle the size accordingly, so that even a byte access would
> work, for completeness.
>
> Lorenzo
>
Of course, I will add process to handle one-byte access from 0xa/0xb register
in next-version.
thanks.
hanjie
>> return PCIBIOS_SUCCESSFUL;
>> }
>>
>> 3, We must ensure class is PCI_CLASS_BRIDGE_PCI except right hdr_type,
>>or pci_setup_device() will get failed:
>>
>>...
>>class = pci_class(dev);
>>dev->revision = class & 0xff;
>>dev->class = class >> 8; /* upper 3 bytes */
>>
>>switch (dev->hdr_type) { /* header type */
>>...
>>case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
>> if (class != PCI_CLASS_BRIDGE_PCI) /* class must be
>> PCI_CLASS_BRIDGE_PCI */
>> goto bad;
>>
>>
>> thanks.
>>
>> hanjie
>
> .
>
Re: [PATCH v6 2/2] PCI: amlogic: Add the Amlogic Meson PCIe controller driver
On 2018/12/4 6:57, Bjorn Helgaas wrote:
> On Mon, Dec 03, 2018 at 04:41:50PM +, Lorenzo Pieralisi wrote:
>> On Thu, Nov 22, 2018 at 04:53:54PM +0800, Hanjie Lin wrote:
>>
>> [...]
>>
>>> +static int meson_pcie_rd_own_conf(struct pcie_port *pp, int where, int
>>> size,
>>> + u32 *val)
>>> +{
>>> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>>> +
>>> + /*
>>> +* there is a bug of MESON AXG pcie controller that software can not
>>> +* programe PCI_CLASS_DEVICE register, so we must return a fake right
>>> +* value to ensure driver could probe successfully.
>>> +*/
>>> + if (where == PCI_CLASS_REVISION) {
>>> + *val = readl(pci->dbi_base + PCI_CLASS_REVISION);
>>> + /* keep revision id */
>>> + *val &= PCI_CLASS_REVISION_MASK;
>>> + *val |= PCI_CLASS_BRIDGE_PCI << 16;
>>> + return PCIBIOS_SUCCESSFUL;
>>> + }
>>
>> As I said before, this looks broken. If this code (or other drivers with
>> the same broken assumptions, eg dwc/pcie-qcom.c) carries out a, say,
>> byte sized config access of eg PCI_CLASS_DEVICE you will get junk out of
>> it according to your comment above.
>>
>> I would like to pick Bjorn's brain on this to see what we can really do
>> to fix this (and other) drivers.
>
> - Check to see whether you're reading anything in the 32-bit dword at
> offset 0x08.
>
> - Do the 32-bit readl().
>
> - Insert the correct Sub-Class and Base Class code (you also throw
> away the Programming Interface; not sure why that is)
>
> - If you're reading something smaller than 32 bits, mask & shift as
> needed. pci_bridge_emul_conf_read() does something similar that
> you might be able to copy.
>
> Out of curiosity, what code depends on PCI_CLASS_BRIDGE_PCI? There
> are several places in the kernel that currently depend on it, but I
> think several of them *should* be checking dev->hdr_type to identify a
> type 1 header instead.
>
> Bjorn
>
> .
>
Yes, it would be broken in particular scenes(eg: read 1 or 2 bytes from
0xa/PCI_CLASS_DEVICE)
that I didn't considered.
As your suggestion, I consider some code below may help this issue:
1, First call dw_pcie_read() help to read 1/2/4 bytes from register,
request all other *size* bytes will return error and dw_pcie_read()
will also check register alignment.
2, If dw_pcie_read() return success and *where* is 0x8/PCI_CLASS_DEVICE or
0xa/PCI_CLASS_REVISION,
we may need to correct class code.
As PCI_CLASS_REVISION is two-bytes register, so only when read 4 bytes from
0x8/PCI_CLASS_DEVICE
or read 2 bytes from 0xa/PCI_CLASS_REVISION we should correct the class code.
ps: read 1 byte from 0xa/PCI_CLASS_REVISION or 0xb will get incorrect value.
static int meson_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
u32 *val)
{
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
int ret;
ret = dw_pcie_read(pci->dbi_base + where, size, val);
if (ret != PCIBIOS_SUCCESSFUL)
return ret;
/*
* there is a bug of MESON AXG pcie controller that software can not
* programe PCI_CLASS_DEVICE register, so we must return a fake right
* value to ensure driver could probe successfully.
*/
if (where == PCI_CLASS_REVISION && size == 4)
*val = (PCI_CLASS_BRIDGE_PCI << 16) | (*val & 0x);
else if (where == PCI_CLASS_DEVICE && size == 2)
*val = PCI_CLASS_BRIDGE_PCI;
return PCIBIOS_SUCCESSFUL;
}
3, We must ensure class is PCI_CLASS_BRIDGE_PCI except right hdr_type,
or pci_setup_device() will get failed:
...
class = pci_class(dev);
dev->revision = class & 0xff;
dev->class = class >> 8; /* upper 3 bytes */
switch (dev->hdr_type) { /* header type */
...
case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
if (class != PCI_CLASS_BRIDGE_PCI) /* class must be PCI_CLASS_BRIDGE_PCI
*/
goto bad;
thanks.
hanjie
Re: [PATCH v6 2/2] PCI: amlogic: Add the Amlogic Meson PCIe controller driver
On 2018/12/4 6:57, Bjorn Helgaas wrote:
> On Mon, Dec 03, 2018 at 04:41:50PM +, Lorenzo Pieralisi wrote:
>> On Thu, Nov 22, 2018 at 04:53:54PM +0800, Hanjie Lin wrote:
>>
>> [...]
>>
>>> +static int meson_pcie_rd_own_conf(struct pcie_port *pp, int where, int
>>> size,
>>> + u32 *val)
>>> +{
>>> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>>> +
>>> + /*
>>> +* there is a bug of MESON AXG pcie controller that software can not
>>> +* programe PCI_CLASS_DEVICE register, so we must return a fake right
>>> +* value to ensure driver could probe successfully.
>>> +*/
>>> + if (where == PCI_CLASS_REVISION) {
>>> + *val = readl(pci->dbi_base + PCI_CLASS_REVISION);
>>> + /* keep revision id */
>>> + *val &= PCI_CLASS_REVISION_MASK;
>>> + *val |= PCI_CLASS_BRIDGE_PCI << 16;
>>> + return PCIBIOS_SUCCESSFUL;
>>> + }
>>
>> As I said before, this looks broken. If this code (or other drivers with
>> the same broken assumptions, eg dwc/pcie-qcom.c) carries out a, say,
>> byte sized config access of eg PCI_CLASS_DEVICE you will get junk out of
>> it according to your comment above.
>>
>> I would like to pick Bjorn's brain on this to see what we can really do
>> to fix this (and other) drivers.
>
> - Check to see whether you're reading anything in the 32-bit dword at
> offset 0x08.
>
> - Do the 32-bit readl().
>
> - Insert the correct Sub-Class and Base Class code (you also throw
> away the Programming Interface; not sure why that is)
>
> - If you're reading something smaller than 32 bits, mask & shift as
> needed. pci_bridge_emul_conf_read() does something similar that
> you might be able to copy.
>
> Out of curiosity, what code depends on PCI_CLASS_BRIDGE_PCI? There
> are several places in the kernel that currently depend on it, but I
> think several of them *should* be checking dev->hdr_type to identify a
> type 1 header instead.
>
> Bjorn
>
> .
>
Yes, it would be broken in particular scenes(eg: read 1 or 2 bytes from
0xa/PCI_CLASS_DEVICE)
that I didn't considered.
As your suggestion, I consider some code below may help this issue:
1, First call dw_pcie_read() help to read 1/2/4 bytes from register,
request all other *size* bytes will return error and dw_pcie_read()
will also check register alignment.
2, If dw_pcie_read() return success and *where* is 0x8/PCI_CLASS_DEVICE or
0xa/PCI_CLASS_REVISION,
we may need to correct class code.
As PCI_CLASS_REVISION is two-bytes register, so only when read 4 bytes from
0x8/PCI_CLASS_DEVICE
or read 2 bytes from 0xa/PCI_CLASS_REVISION we should correct the class code.
ps: read 1 byte from 0xa/PCI_CLASS_REVISION or 0xb will get incorrect value.
static int meson_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
u32 *val)
{
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
int ret;
ret = dw_pcie_read(pci->dbi_base + where, size, val);
if (ret != PCIBIOS_SUCCESSFUL)
return ret;
/*
* there is a bug of MESON AXG pcie controller that software can not
* programe PCI_CLASS_DEVICE register, so we must return a fake right
* value to ensure driver could probe successfully.
*/
if (where == PCI_CLASS_REVISION && size == 4)
*val = (PCI_CLASS_BRIDGE_PCI << 16) | (*val & 0x);
else if (where == PCI_CLASS_DEVICE && size == 2)
*val = PCI_CLASS_BRIDGE_PCI;
return PCIBIOS_SUCCESSFUL;
}
3, We must ensure class is PCI_CLASS_BRIDGE_PCI except right hdr_type,
or pci_setup_device() will get failed:
...
class = pci_class(dev);
dev->revision = class & 0xff;
dev->class = class >> 8; /* upper 3 bytes */
switch (dev->hdr_type) { /* header type */
...
case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
if (class != PCI_CLASS_BRIDGE_PCI) /* class must be PCI_CLASS_BRIDGE_PCI
*/
goto bad;
thanks.
hanjie
Re: [PATCH v6 2/2] PCI: amlogic: Add the Amlogic Meson PCIe controller driver
On 2018/11/29 17:03, Dan Carpenter wrote:
> Hi Yue,
>
> url:
> https://github.com/0day-ci/linux/commits/Hanjie-Lin/dt-bindings-PCI-meson-add-DT-bindings-for-Amlogic-Meson-PCIe-controller/20181122-225955
> base: https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git next
>
> smatch warnings:
> drivers/pci/controller/dwc/pci-meson.c:171 meson_pcie_get_mem_shared() error:
> passing non negative 6 to ERR_PTR
>
> #
> https://github.com/0day-ci/linux/commit/c882cdc75e49b6de65cd3d95ebf688272af6b5f9
> git remote add linux-review https://github.com/0day-ci/linux
> git remote update linux-review
> git checkout c882cdc75e49b6de65cd3d95ebf688272af6b5f9
> vim +171 drivers/pci/controller/dwc/pci-meson.c
>
> c882cdc75 Yue Wang 2018-11-22 160
> c882cdc75 Yue Wang 2018-11-22 161 static void __iomem
> *meson_pcie_get_mem_shared(struct platform_device *pdev,
> c882cdc75 Yue Wang 2018-11-22 162
> struct meson_pcie *mp,
> c882cdc75 Yue Wang 2018-11-22 163
> const char *id)
> c882cdc75 Yue Wang 2018-11-22 164 {
> c882cdc75 Yue Wang 2018-11-22 165struct device *dev = mp->pci.dev;
> c882cdc75 Yue Wang 2018-11-22 166struct resource *res;
> c882cdc75 Yue Wang 2018-11-22 167
> c882cdc75 Yue Wang 2018-11-22 168res =
> platform_get_resource_byname(pdev, IORESOURCE_MEM, id);
> c882cdc75 Yue Wang 2018-11-22 169if (!res) {
> c882cdc75 Yue Wang 2018-11-22 170dev_err(dev, "No REG resource
> %s\n", id);
> c882cdc75 Yue Wang 2018-11-22 @171return ERR_PTR(ENXIO);
>^
>-ENXIO
>
> c882cdc75 Yue Wang 2018-11-22 172}
> c882cdc75 Yue Wang 2018-11-22 173
> c882cdc75 Yue Wang 2018-11-22 174return devm_ioremap(dev, res->start,
> resource_size(res));
> c882cdc75 Yue Wang 2018-11-22 175 }
> c882cdc75 Yue Wang 2018-11-22 176
>
> ---
> 0-DAY kernel test infrastructureOpen Source Technology Center
> https://lists.01.org/pipermail/kbuild-all Intel Corporation
>
> .
>
Yes, it's really a silly mistake.
I'll fix it.
thanks.
Re: [PATCH v6 2/2] PCI: amlogic: Add the Amlogic Meson PCIe controller driver
On 2018/11/29 17:03, Dan Carpenter wrote:
> Hi Yue,
>
> url:
> https://github.com/0day-ci/linux/commits/Hanjie-Lin/dt-bindings-PCI-meson-add-DT-bindings-for-Amlogic-Meson-PCIe-controller/20181122-225955
> base: https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git next
>
> smatch warnings:
> drivers/pci/controller/dwc/pci-meson.c:171 meson_pcie_get_mem_shared() error:
> passing non negative 6 to ERR_PTR
>
> #
> https://github.com/0day-ci/linux/commit/c882cdc75e49b6de65cd3d95ebf688272af6b5f9
> git remote add linux-review https://github.com/0day-ci/linux
> git remote update linux-review
> git checkout c882cdc75e49b6de65cd3d95ebf688272af6b5f9
> vim +171 drivers/pci/controller/dwc/pci-meson.c
>
> c882cdc75 Yue Wang 2018-11-22 160
> c882cdc75 Yue Wang 2018-11-22 161 static void __iomem
> *meson_pcie_get_mem_shared(struct platform_device *pdev,
> c882cdc75 Yue Wang 2018-11-22 162
> struct meson_pcie *mp,
> c882cdc75 Yue Wang 2018-11-22 163
> const char *id)
> c882cdc75 Yue Wang 2018-11-22 164 {
> c882cdc75 Yue Wang 2018-11-22 165struct device *dev = mp->pci.dev;
> c882cdc75 Yue Wang 2018-11-22 166struct resource *res;
> c882cdc75 Yue Wang 2018-11-22 167
> c882cdc75 Yue Wang 2018-11-22 168res =
> platform_get_resource_byname(pdev, IORESOURCE_MEM, id);
> c882cdc75 Yue Wang 2018-11-22 169if (!res) {
> c882cdc75 Yue Wang 2018-11-22 170dev_err(dev, "No REG resource
> %s\n", id);
> c882cdc75 Yue Wang 2018-11-22 @171return ERR_PTR(ENXIO);
>^
>-ENXIO
>
> c882cdc75 Yue Wang 2018-11-22 172}
> c882cdc75 Yue Wang 2018-11-22 173
> c882cdc75 Yue Wang 2018-11-22 174return devm_ioremap(dev, res->start,
> resource_size(res));
> c882cdc75 Yue Wang 2018-11-22 175 }
> c882cdc75 Yue Wang 2018-11-22 176
>
> ---
> 0-DAY kernel test infrastructureOpen Source Technology Center
> https://lists.01.org/pipermail/kbuild-all Intel Corporation
>
> .
>
Yes, it's really a silly mistake.
I'll fix it.
thanks.
[PATCH v6 2/2] PCI: amlogic: Add the Amlogic Meson PCIe controller driver
From: Yue Wang The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core. This patch adds the driver support for Meson PCIe controller. Signed-off-by: Yue Wang Signed-off-by: Hanjie Lin --- MAINTAINERS| 7 + drivers/pci/controller/dwc/Kconfig | 10 + drivers/pci/controller/dwc/Makefile| 1 + drivers/pci/controller/dwc/pci-meson.c | 597 + 4 files changed, 615 insertions(+) create mode 100644 drivers/pci/controller/dwc/pci-meson.c diff --git a/MAINTAINERS b/MAINTAINERS index 77b1174..4fb9098 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11530,6 +11530,13 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/lpieralisi/pci.git/ S: Supported F: drivers/pci/controller/ +PCIE DRIVER FOR AMLOGIC MESON +M: Yue Wang +L: linux-...@vger.kernel.org +L: linux-amlo...@lists.infradead.org +S: Maintained +F: drivers/pci/controller/dwc/pci-meson.c + PCIE DRIVER FOR AXIS ARTPEC M: Jesper Nilsson L: linux-arm-ker...@axis.com diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index 91b0194..7800322 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -193,4 +193,14 @@ config PCIE_HISI_STB help Say Y here if you want PCIe controller support on HiSilicon STB SoCs +config PCI_MESON + bool "MESON PCIe controller" + depends on PCI_MSI_IRQ_DOMAIN + select PCIE_DW_HOST + help + Say Y here if you want to enable PCI controller support on Amlogic + SoCs. The PCI controller on Amlogic is based on DesignWare hardware + and therefore the driver re-uses the DesignWare core functions to + implement the driver. + endmenu diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile index fcf91ea..e05a015 100644 --- a/drivers/pci/controller/dwc/Makefile +++ b/drivers/pci/controller/dwc/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o +obj-$(CONFIG_PCI_MESON) += pci-meson.o # The following drivers are for devices that use the generic ACPI # pci_root.c driver but don't support standard ECAM config access. diff --git a/drivers/pci/controller/dwc/pci-meson.c b/drivers/pci/controller/dwc/pci-meson.c new file mode 100644 index 000..ef30a5a --- /dev/null +++ b/drivers/pci/controller/dwc/pci-meson.c @@ -0,0 +1,597 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PCIe host controller driver for Amlogic MESON SoCs + * + * Copyright (c) 2018 Amlogic, inc. + * Author: Yue Wang + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pcie-designware.h" + +#define to_meson_pcie(x) dev_get_drvdata((x)->dev) + +/* External local bus interface registers */ +#define PLR_OFFSET 0x700 +#define PCIE_PORT_LINK_CTRL_OFF(PLR_OFFSET + 0x10) +#define FAST_LINK_MODE BIT(7) +#define LINK_CAPABLE_MASK GENMASK(21, 16) +#define LINK_CAPABLE_X1BIT(16) + +#define PCIE_GEN2_CTRL_OFF (PLR_OFFSET + 0x10c) +#define NUM_OF_LANES_MASK GENMASK(12, 8) +#define NUM_OF_LANES_X1BIT(8) +#define DIRECT_SPEED_CHANGEBIT(17) + +#define TYPE1_HDR_OFFSET 0x0 +#define PCIE_STATUS_COMMAND(TYPE1_HDR_OFFSET + 0x04) +#define PCI_IO_EN BIT(0) +#define PCI_MEM_SPACE_EN BIT(1) +#define PCI_BUS_MASTER_EN BIT(2) + +#define PCIE_BASE_ADDR0(TYPE1_HDR_OFFSET + 0x10) +#define PCIE_BASE_ADDR1(TYPE1_HDR_OFFSET + 0x14) + +#define PCIE_CAP_OFFSET0x70 +#define PCIE_DEV_CTRL_DEV_STUS (PCIE_CAP_OFFSET + 0x08) +#define PCIE_CAP_MAX_PAYLOAD_MASK GENMASK(7, 5) +#define PCIE_CAP_MAX_PAYLOAD_SIZE(x) ((x) << 5) +#define PCIE_CAP_MAX_READ_REQ_MASK GENMASK(14, 12) +#define PCIE_CAP_MAX_READ_REQ_SIZE(x) ((x) << 12) + +#define PCI_CLASS_REVISION_MASKGENMASK(7, 0) + +/* PCIe specific config registers */ +#define PCIE_CFG0 0x0 +#define APP_LTSSM_ENABLE BIT(7) + +#define PCIE_CFG_STATUS12 0x30 +#define IS_SMLH_LINK_UP(x) ((x) & (1 << 6)) +#define IS_RDLH_LINK_UP(x) ((x) & (1 << 16)) +#define IS_LTSSM_UP(x) x) >> 10) & 0x1f) == 0x11) + +#define PCIE_CFG_STATUS17 0x44 +#define PM_CURRENT_STATE(x)(((x) >> 7) & 0x1) + +#define WAIT_LINKUP_TIMEOUT2000 +#define PORT_CLK_RATE 1UL +#define MAX_PAYLOAD_SIZE 256
[PATCH v6 1/2] dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller
From: Yue Wang
The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare
PCI core. This patch adds documentation for the DT bindings in Meson PCIe
controller.
Signed-off-by: Yue Wang
Signed-off-by: Hanjie Lin
Reviewed-by: Rob Herring
---
.../devicetree/bindings/pci/amlogic,meson-pcie.txt | 70 ++
1 file changed, 70 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
diff --git a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
new file mode 100644
index 000..12b18f8
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
@@ -0,0 +1,70 @@
+Amlogic Meson AXG DWC PCIE SoC controller
+
+Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI
core.
+It shares common functions with the PCIe DesignWare core driver and
+inherits common properties defined in
+Documentation/devicetree/bindings/pci/designware-pci.txt.
+
+Additional properties are described here:
+
+Required properties:
+- compatible:
+ should contain "amlogic,axg-pcie" to identify the core.
+- reg:
+ should contain the configuration address space.
+- reg-names: Must be
+ - "elbi"External local bus interface registers
+ - "cfg" Meson specific registers
+ - "phy" Meson PCIE PHY registers
+ - "config" PCIe configuration space
+- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
+- clocks: Must contain an entry for each entry in clock-names.
+- clock-names: Must include the following entries:
+ - "pclk" PCIe GEN 100M PLL clock
+ - "port" PCIe_x(A or B) RC clock gate
+ - "general"PCIe Phy clock
+ - "mipi" PCIe_x(A or B) 100M ref clock gate
+- resets: phandle to the reset lines.
+- reset-names: must contain "phy" "port" and "apb"
+ - "phy" Share PHY reset
+ - "port"Port A or B reset
+ - "apb" Share APB reset
+- device_type:
+ should be "pci". As specified in designware-pcie.txt
+
+
+Example configuration:
+
+ pcie: pcie@f980 {
+ compatible = "amlogic,axg-pcie", "snps,dw-pcie";
+ reg = <0x0 0xf980 0x0 0x40
+ 0x0 0xff646000 0x0 0x2000
+ 0x0 0xff644000 0x0 0x2000
+ 0x0 0xf9f0 0x0 0x10>;
+ reg-names = "elbi", "cfg", "phy", "config";
+ reset-gpios = < GPIOX_19 GPIO_ACTIVE_HIGH>;
+ interrupts = ;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 GIC_SPI 179
IRQ_TYPE_EDGE_RISING>;
+ bus-range = <0x0 0xff>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x8200 0 0 0x0 0xf9c0 0 0x0030>;
+
+ clocks = < CLKID_USB
+CLKID_MIPI_ENABLE
+CLKID_PCIE_A
+CLKID_PCIE_CML_EN0>;
+ clock-names = "general",
+ "mipi",
+ "pclk",
+ "port";
+ resets = < RESET_PCIE_PHY>,
+ < RESET_PCIE_A>,
+ < RESET_PCIE_APB>;
+ reset-names = "phy",
+ "port",
+ "apb";
+ };
--
2.7.4
[PATCH v6 0/2] add the Amlogic Meson PCIe controller driver
The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core. This patchset add the driver and dt-bindings of the controller. Changes since v5: [4] - update MAINTAINER file in alphabetical order - remove meaningless comment - use ERR_PTR function instead of (void *) cast - use is_power_of_2(size) instead of size & (size - 1) - add comment for PCI_CLASS_REVISION register operation Changes since v4: [3] - fix kbuild test robot and compile warnings Changes since v3: [2] - modify subject format - update Kconfig - update MAINTAINER file - add comment and error handle for meson_pcie_get_mem_shared() - drop useless initialization code - add comment for meson_size_to_payload() - optimize meson_pcie_establish_link() return code - optimize meson_pcie_enable_interrupts() redundant function - drop device_attch related code - drop dw_pcie_ops read_dbi and write_dbi function - add error handle for meson_add_pcie_port() when probe Changes since v2: [1] - abandon phy driver, move reset to the controller - use devm_add_action_or_reset() to use clock res - format correcting Changes since v1: [0] - use gpio lib instead open code - move 'apb' and 'port' reset from phy driver - format correcting [0] : https://lkml.kernel.org/r/1534227522-186798-1-git-send-email-hanjie@amlogic.com [1] : https://lkml.kernel.org/r/1535096165-45827-1-git-send-email-hanjie@amlogic.com [2] : https://lkml.kernel.org/r/1537509820-52040-1-git-send-email-hanjie@amlogic.com [3] : https://lkml.kernel.org/r/1538999834-156423-3-git-send-email-hanjie@amlogic.com [4] : https://lkml.kernel.org/r/1539049990-30810-1-git-send-email-hanjie@amlogic.com Yue Wang (2): dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller PCI: amlogic: Add the Amlogic Meson PCIe controller driver .../devicetree/bindings/pci/amlogic,meson-pcie.txt | 70 +++ MAINTAINERS| 7 + drivers/pci/controller/dwc/Kconfig | 10 + drivers/pci/controller/dwc/Makefile| 1 + drivers/pci/controller/dwc/pci-meson.c | 597 + 5 files changed, 685 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt create mode 100644 drivers/pci/controller/dwc/pci-meson.c -- 2.7.4
[PATCH v6 2/2] PCI: amlogic: Add the Amlogic Meson PCIe controller driver
From: Yue Wang The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core. This patch adds the driver support for Meson PCIe controller. Signed-off-by: Yue Wang Signed-off-by: Hanjie Lin --- MAINTAINERS| 7 + drivers/pci/controller/dwc/Kconfig | 10 + drivers/pci/controller/dwc/Makefile| 1 + drivers/pci/controller/dwc/pci-meson.c | 597 + 4 files changed, 615 insertions(+) create mode 100644 drivers/pci/controller/dwc/pci-meson.c diff --git a/MAINTAINERS b/MAINTAINERS index 77b1174..4fb9098 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11530,6 +11530,13 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/lpieralisi/pci.git/ S: Supported F: drivers/pci/controller/ +PCIE DRIVER FOR AMLOGIC MESON +M: Yue Wang +L: linux-...@vger.kernel.org +L: linux-amlo...@lists.infradead.org +S: Maintained +F: drivers/pci/controller/dwc/pci-meson.c + PCIE DRIVER FOR AXIS ARTPEC M: Jesper Nilsson L: linux-arm-ker...@axis.com diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index 91b0194..7800322 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -193,4 +193,14 @@ config PCIE_HISI_STB help Say Y here if you want PCIe controller support on HiSilicon STB SoCs +config PCI_MESON + bool "MESON PCIe controller" + depends on PCI_MSI_IRQ_DOMAIN + select PCIE_DW_HOST + help + Say Y here if you want to enable PCI controller support on Amlogic + SoCs. The PCI controller on Amlogic is based on DesignWare hardware + and therefore the driver re-uses the DesignWare core functions to + implement the driver. + endmenu diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile index fcf91ea..e05a015 100644 --- a/drivers/pci/controller/dwc/Makefile +++ b/drivers/pci/controller/dwc/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o +obj-$(CONFIG_PCI_MESON) += pci-meson.o # The following drivers are for devices that use the generic ACPI # pci_root.c driver but don't support standard ECAM config access. diff --git a/drivers/pci/controller/dwc/pci-meson.c b/drivers/pci/controller/dwc/pci-meson.c new file mode 100644 index 000..ef30a5a --- /dev/null +++ b/drivers/pci/controller/dwc/pci-meson.c @@ -0,0 +1,597 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PCIe host controller driver for Amlogic MESON SoCs + * + * Copyright (c) 2018 Amlogic, inc. + * Author: Yue Wang + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pcie-designware.h" + +#define to_meson_pcie(x) dev_get_drvdata((x)->dev) + +/* External local bus interface registers */ +#define PLR_OFFSET 0x700 +#define PCIE_PORT_LINK_CTRL_OFF(PLR_OFFSET + 0x10) +#define FAST_LINK_MODE BIT(7) +#define LINK_CAPABLE_MASK GENMASK(21, 16) +#define LINK_CAPABLE_X1BIT(16) + +#define PCIE_GEN2_CTRL_OFF (PLR_OFFSET + 0x10c) +#define NUM_OF_LANES_MASK GENMASK(12, 8) +#define NUM_OF_LANES_X1BIT(8) +#define DIRECT_SPEED_CHANGEBIT(17) + +#define TYPE1_HDR_OFFSET 0x0 +#define PCIE_STATUS_COMMAND(TYPE1_HDR_OFFSET + 0x04) +#define PCI_IO_EN BIT(0) +#define PCI_MEM_SPACE_EN BIT(1) +#define PCI_BUS_MASTER_EN BIT(2) + +#define PCIE_BASE_ADDR0(TYPE1_HDR_OFFSET + 0x10) +#define PCIE_BASE_ADDR1(TYPE1_HDR_OFFSET + 0x14) + +#define PCIE_CAP_OFFSET0x70 +#define PCIE_DEV_CTRL_DEV_STUS (PCIE_CAP_OFFSET + 0x08) +#define PCIE_CAP_MAX_PAYLOAD_MASK GENMASK(7, 5) +#define PCIE_CAP_MAX_PAYLOAD_SIZE(x) ((x) << 5) +#define PCIE_CAP_MAX_READ_REQ_MASK GENMASK(14, 12) +#define PCIE_CAP_MAX_READ_REQ_SIZE(x) ((x) << 12) + +#define PCI_CLASS_REVISION_MASKGENMASK(7, 0) + +/* PCIe specific config registers */ +#define PCIE_CFG0 0x0 +#define APP_LTSSM_ENABLE BIT(7) + +#define PCIE_CFG_STATUS12 0x30 +#define IS_SMLH_LINK_UP(x) ((x) & (1 << 6)) +#define IS_RDLH_LINK_UP(x) ((x) & (1 << 16)) +#define IS_LTSSM_UP(x) x) >> 10) & 0x1f) == 0x11) + +#define PCIE_CFG_STATUS17 0x44 +#define PM_CURRENT_STATE(x)(((x) >> 7) & 0x1) + +#define WAIT_LINKUP_TIMEOUT2000 +#define PORT_CLK_RATE 1UL +#define MAX_PAYLOAD_SIZE 256
[PATCH v6 1/2] dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller
From: Yue Wang
The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare
PCI core. This patch adds documentation for the DT bindings in Meson PCIe
controller.
Signed-off-by: Yue Wang
Signed-off-by: Hanjie Lin
Reviewed-by: Rob Herring
---
.../devicetree/bindings/pci/amlogic,meson-pcie.txt | 70 ++
1 file changed, 70 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
diff --git a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
new file mode 100644
index 000..12b18f8
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
@@ -0,0 +1,70 @@
+Amlogic Meson AXG DWC PCIE SoC controller
+
+Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI
core.
+It shares common functions with the PCIe DesignWare core driver and
+inherits common properties defined in
+Documentation/devicetree/bindings/pci/designware-pci.txt.
+
+Additional properties are described here:
+
+Required properties:
+- compatible:
+ should contain "amlogic,axg-pcie" to identify the core.
+- reg:
+ should contain the configuration address space.
+- reg-names: Must be
+ - "elbi"External local bus interface registers
+ - "cfg" Meson specific registers
+ - "phy" Meson PCIE PHY registers
+ - "config" PCIe configuration space
+- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
+- clocks: Must contain an entry for each entry in clock-names.
+- clock-names: Must include the following entries:
+ - "pclk" PCIe GEN 100M PLL clock
+ - "port" PCIe_x(A or B) RC clock gate
+ - "general"PCIe Phy clock
+ - "mipi" PCIe_x(A or B) 100M ref clock gate
+- resets: phandle to the reset lines.
+- reset-names: must contain "phy" "port" and "apb"
+ - "phy" Share PHY reset
+ - "port"Port A or B reset
+ - "apb" Share APB reset
+- device_type:
+ should be "pci". As specified in designware-pcie.txt
+
+
+Example configuration:
+
+ pcie: pcie@f980 {
+ compatible = "amlogic,axg-pcie", "snps,dw-pcie";
+ reg = <0x0 0xf980 0x0 0x40
+ 0x0 0xff646000 0x0 0x2000
+ 0x0 0xff644000 0x0 0x2000
+ 0x0 0xf9f0 0x0 0x10>;
+ reg-names = "elbi", "cfg", "phy", "config";
+ reset-gpios = < GPIOX_19 GPIO_ACTIVE_HIGH>;
+ interrupts = ;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 GIC_SPI 179
IRQ_TYPE_EDGE_RISING>;
+ bus-range = <0x0 0xff>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x8200 0 0 0x0 0xf9c0 0 0x0030>;
+
+ clocks = < CLKID_USB
+CLKID_MIPI_ENABLE
+CLKID_PCIE_A
+CLKID_PCIE_CML_EN0>;
+ clock-names = "general",
+ "mipi",
+ "pclk",
+ "port";
+ resets = < RESET_PCIE_PHY>,
+ < RESET_PCIE_A>,
+ < RESET_PCIE_APB>;
+ reset-names = "phy",
+ "port",
+ "apb";
+ };
--
2.7.4
[PATCH v6 0/2] add the Amlogic Meson PCIe controller driver
The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core. This patchset add the driver and dt-bindings of the controller. Changes since v5: [4] - update MAINTAINER file in alphabetical order - remove meaningless comment - use ERR_PTR function instead of (void *) cast - use is_power_of_2(size) instead of size & (size - 1) - add comment for PCI_CLASS_REVISION register operation Changes since v4: [3] - fix kbuild test robot and compile warnings Changes since v3: [2] - modify subject format - update Kconfig - update MAINTAINER file - add comment and error handle for meson_pcie_get_mem_shared() - drop useless initialization code - add comment for meson_size_to_payload() - optimize meson_pcie_establish_link() return code - optimize meson_pcie_enable_interrupts() redundant function - drop device_attch related code - drop dw_pcie_ops read_dbi and write_dbi function - add error handle for meson_add_pcie_port() when probe Changes since v2: [1] - abandon phy driver, move reset to the controller - use devm_add_action_or_reset() to use clock res - format correcting Changes since v1: [0] - use gpio lib instead open code - move 'apb' and 'port' reset from phy driver - format correcting [0] : https://lkml.kernel.org/r/1534227522-186798-1-git-send-email-hanjie@amlogic.com [1] : https://lkml.kernel.org/r/1535096165-45827-1-git-send-email-hanjie@amlogic.com [2] : https://lkml.kernel.org/r/1537509820-52040-1-git-send-email-hanjie@amlogic.com [3] : https://lkml.kernel.org/r/1538999834-156423-3-git-send-email-hanjie@amlogic.com [4] : https://lkml.kernel.org/r/1539049990-30810-1-git-send-email-hanjie@amlogic.com Yue Wang (2): dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller PCI: amlogic: Add the Amlogic Meson PCIe controller driver .../devicetree/bindings/pci/amlogic,meson-pcie.txt | 70 +++ MAINTAINERS| 7 + drivers/pci/controller/dwc/Kconfig | 10 + drivers/pci/controller/dwc/Makefile| 1 + drivers/pci/controller/dwc/pci-meson.c | 597 + 5 files changed, 685 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt create mode 100644 drivers/pci/controller/dwc/pci-meson.c -- 2.7.4
Re: [PATCH v5 2/2] PCI: amlogic: Add the Amlogic Meson PCIe controller driver
On 2018/11/17 1:49, Lorenzo Pieralisi wrote: > On Tue, Oct 09, 2018 at 09:53:10AM +0800, Hanjie Lin wrote: >> From: Yue Wang >> >> The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare >> PCI core. This patch adds the driver support for Meson PCIe controller. >> >> Signed-off-by: Yue Wang >> Signed-off-by: Hanjie Lin >> --- >> MAINTAINERS| 7 + >> drivers/pci/controller/dwc/Kconfig | 10 + >> drivers/pci/controller/dwc/Makefile| 1 + >> drivers/pci/controller/dwc/pci-meson.c | 593 >> + >> 4 files changed, 611 insertions(+) >> create mode 100644 drivers/pci/controller/dwc/pci-meson.c >> >> diff --git a/MAINTAINERS b/MAINTAINERS >> index 02a3961..da579ef 100644 >> --- a/MAINTAINERS >> +++ b/MAINTAINERS >> @@ -11333,6 +11333,13 @@ L: linux-...@vger.kernel.org >> S: Maintained >> F: drivers/pci/controller/dwc/*spear* >> >> +PCIE DRIVER FOR AMLOGIC MESON > > Entries for PCIe host bridges are in alphabetical order, this one > isn't so you should fix it. > Yes, I will fix it. >> +M: Yue Wang >> +L: linux-...@vger.kernel.org >> +L: linux-amlo...@lists.infradead.org >> +S: Maintained >> +F: drivers/pci/controller/dwc/pci-meson.c >> + >> PCMCIA SUBSYSTEM >> M: Dominik Brodowski >> T: git git://git.kernel.org/pub/scm/linux/kernel/git/brodo/pcmcia.git >> diff --git a/drivers/pci/controller/dwc/Kconfig >> b/drivers/pci/controller/dwc/Kconfig >> index 91b0194..7800322 100644 >> --- a/drivers/pci/controller/dwc/Kconfig >> +++ b/drivers/pci/controller/dwc/Kconfig >> @@ -193,4 +193,14 @@ config PCIE_HISI_STB >> help >>Say Y here if you want PCIe controller support on HiSilicon STB >> SoCs >> >> +config PCI_MESON >> +bool "MESON PCIe controller" >> +depends on PCI_MSI_IRQ_DOMAIN >> +select PCIE_DW_HOST >> +help >> + Say Y here if you want to enable PCI controller support on Amlogic >> + SoCs. The PCI controller on Amlogic is based on DesignWare hardware >> + and therefore the driver re-uses the DesignWare core functions to >> + implement the driver. >> + >> endmenu >> diff --git a/drivers/pci/controller/dwc/Makefile >> b/drivers/pci/controller/dwc/Makefile >> index 5d2ce72..cf676bd 100644 >> --- a/drivers/pci/controller/dwc/Makefile >> +++ b/drivers/pci/controller/dwc/Makefile >> @@ -14,6 +14,7 @@ obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o >> obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o >> obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o >> obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o >> +obj-$(CONFIG_PCI_MESON) += pci-meson.o >> >> # The following drivers are for devices that use the generic ACPI >> # pci_root.c driver but don't support standard ECAM config access. >> diff --git a/drivers/pci/controller/dwc/pci-meson.c >> b/drivers/pci/controller/dwc/pci-meson.c >> new file mode 100644 >> index 000..2278b48 >> --- /dev/null >> +++ b/drivers/pci/controller/dwc/pci-meson.c >> @@ -0,0 +1,593 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * PCIe host controller driver for Amlogic MESON SoCs >> + * >> + * Copyright (c) 2018 Amlogic, inc. >> + * Author: Yue Wang >> + */ >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> + >> +#include "pcie-designware.h" >> + >> +#define to_meson_pcie(x) dev_get_drvdata((x)->dev) >> + >> +/* External local bus interface registers */ >> +#define PLR_OFFSET 0x700 >> +#define PCIE_PORT_LINK_CTRL_OFF (PLR_OFFSET + 0x10) >> +#define FAST_LINK_MODE BIT(7) >> +#define LINK_CAPABLE_MASK GENMASK(21, 16) >> +#define LINK_CAPABLE_X1 BIT(16) >> + >> +#define PCIE_GEN2_CTRL_OFF (PLR_OFFSET + 0x10c) >> +#define NUM_OF_LANES_MASK GENMASK(12, 8) >> +#define NUM_OF_LANES_X1 BIT(8) >> +#define DIRECT_SPEED_CHANGE BIT(17) >> + >> +#define TYPE1_HDR_OFFSET0x0 >> +#define PCIE_STATUS_COMMAND (TYPE1_HDR_OFFSET + 0x04) >> +#define PCI_IO_EN BIT(0) >> +#define PCI_MEM_SPACE_ENBIT(1) >> +#define PCI_BUS_MASTER_EN BIT(2) >> +#define
Re: [PATCH v5 2/2] PCI: amlogic: Add the Amlogic Meson PCIe controller driver
On 2018/11/17 1:49, Lorenzo Pieralisi wrote: > On Tue, Oct 09, 2018 at 09:53:10AM +0800, Hanjie Lin wrote: >> From: Yue Wang >> >> The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare >> PCI core. This patch adds the driver support for Meson PCIe controller. >> >> Signed-off-by: Yue Wang >> Signed-off-by: Hanjie Lin >> --- >> MAINTAINERS| 7 + >> drivers/pci/controller/dwc/Kconfig | 10 + >> drivers/pci/controller/dwc/Makefile| 1 + >> drivers/pci/controller/dwc/pci-meson.c | 593 >> + >> 4 files changed, 611 insertions(+) >> create mode 100644 drivers/pci/controller/dwc/pci-meson.c >> >> diff --git a/MAINTAINERS b/MAINTAINERS >> index 02a3961..da579ef 100644 >> --- a/MAINTAINERS >> +++ b/MAINTAINERS >> @@ -11333,6 +11333,13 @@ L: linux-...@vger.kernel.org >> S: Maintained >> F: drivers/pci/controller/dwc/*spear* >> >> +PCIE DRIVER FOR AMLOGIC MESON > > Entries for PCIe host bridges are in alphabetical order, this one > isn't so you should fix it. > Yes, I will fix it. >> +M: Yue Wang >> +L: linux-...@vger.kernel.org >> +L: linux-amlo...@lists.infradead.org >> +S: Maintained >> +F: drivers/pci/controller/dwc/pci-meson.c >> + >> PCMCIA SUBSYSTEM >> M: Dominik Brodowski >> T: git git://git.kernel.org/pub/scm/linux/kernel/git/brodo/pcmcia.git >> diff --git a/drivers/pci/controller/dwc/Kconfig >> b/drivers/pci/controller/dwc/Kconfig >> index 91b0194..7800322 100644 >> --- a/drivers/pci/controller/dwc/Kconfig >> +++ b/drivers/pci/controller/dwc/Kconfig >> @@ -193,4 +193,14 @@ config PCIE_HISI_STB >> help >>Say Y here if you want PCIe controller support on HiSilicon STB >> SoCs >> >> +config PCI_MESON >> +bool "MESON PCIe controller" >> +depends on PCI_MSI_IRQ_DOMAIN >> +select PCIE_DW_HOST >> +help >> + Say Y here if you want to enable PCI controller support on Amlogic >> + SoCs. The PCI controller on Amlogic is based on DesignWare hardware >> + and therefore the driver re-uses the DesignWare core functions to >> + implement the driver. >> + >> endmenu >> diff --git a/drivers/pci/controller/dwc/Makefile >> b/drivers/pci/controller/dwc/Makefile >> index 5d2ce72..cf676bd 100644 >> --- a/drivers/pci/controller/dwc/Makefile >> +++ b/drivers/pci/controller/dwc/Makefile >> @@ -14,6 +14,7 @@ obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o >> obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o >> obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o >> obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o >> +obj-$(CONFIG_PCI_MESON) += pci-meson.o >> >> # The following drivers are for devices that use the generic ACPI >> # pci_root.c driver but don't support standard ECAM config access. >> diff --git a/drivers/pci/controller/dwc/pci-meson.c >> b/drivers/pci/controller/dwc/pci-meson.c >> new file mode 100644 >> index 000..2278b48 >> --- /dev/null >> +++ b/drivers/pci/controller/dwc/pci-meson.c >> @@ -0,0 +1,593 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * PCIe host controller driver for Amlogic MESON SoCs >> + * >> + * Copyright (c) 2018 Amlogic, inc. >> + * Author: Yue Wang >> + */ >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> + >> +#include "pcie-designware.h" >> + >> +#define to_meson_pcie(x) dev_get_drvdata((x)->dev) >> + >> +/* External local bus interface registers */ >> +#define PLR_OFFSET 0x700 >> +#define PCIE_PORT_LINK_CTRL_OFF (PLR_OFFSET + 0x10) >> +#define FAST_LINK_MODE BIT(7) >> +#define LINK_CAPABLE_MASK GENMASK(21, 16) >> +#define LINK_CAPABLE_X1 BIT(16) >> + >> +#define PCIE_GEN2_CTRL_OFF (PLR_OFFSET + 0x10c) >> +#define NUM_OF_LANES_MASK GENMASK(12, 8) >> +#define NUM_OF_LANES_X1 BIT(8) >> +#define DIRECT_SPEED_CHANGE BIT(17) >> + >> +#define TYPE1_HDR_OFFSET0x0 >> +#define PCIE_STATUS_COMMAND (TYPE1_HDR_OFFSET + 0x04) >> +#define PCI_IO_EN BIT(0) >> +#define PCI_MEM_SPACE_ENBIT(1) >> +#define PCI_BUS_MASTER_EN BIT(2) >> +#define
Re: [PATCH v5 1/2] dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller
On 2018/11/20 4:12, Martin Blumenstingl wrote:
> Hello Hanjie, Hello Yue,
>
> sorry for being late with my comment
>
> On Tue, Oct 9, 2018 at 3:53 AM Hanjie Lin wrote:
>>
>> From: Yue Wang
>>
>> The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare
>> PCI core. This patch adds documentation for the DT bindings in Meson PCIe
>> controller.
>>
>> Signed-off-by: Yue Wang
>> Signed-off-by: Hanjie Lin
>> Reviewed-by: Rob Herring
>> ---
>> .../devicetree/bindings/pci/amlogic,meson-pcie.txt | 70
>> ++
>> 1 file changed, 70 insertions(+)
>> create mode 100644
>> Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
>>
>> diff --git a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
>> b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
>> new file mode 100644
>> index 000..12b18f8
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
>> @@ -0,0 +1,70 @@
>> +Amlogic Meson AXG DWC PCIE SoC controller
>> +
>> +Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI
>> core.
>> +It shares common functions with the PCIe DesignWare core driver and
>> +inherits common properties defined in
>> +Documentation/devicetree/bindings/pci/designware-pci.txt.
>> +
>> +Additional properties are described here:
>> +
>> +Required properties:
>> +- compatible:
>> + should contain "amlogic,axg-pcie" to identify the core.
>> +- reg:
>> + should contain the configuration address space.
>> +- reg-names: Must be
>> + - "elbi"External local bus interface registers
>> + - "cfg" Meson specific registers
>> + - "phy" Meson PCIE PHY registers
> is this only the PCIe PHY registers or is it the registers of the PHY
> which supports USB3.0 and PCIe?
> buildroot_openlinux_kernel_4.9_fbdev_20180706 uses the following
> registers in the pcie_A node for the "phy" registers:
> 0x0 0xff646000 0x0 0x2000
> while the usb3_phy_v2 node uses:
> phy-reg = <0xff646000>;
>
It's correct.
In Meson AXG chip, this phy is dedicated to pcie.
But in Meson G12 chip, this phy is shared by pcie and usb3.0, only one module
can own the phy at one time.
>> + - "config" PCIe configuration space
>> +- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
>> +- clocks: Must contain an entry for each entry in clock-names.
>> +- clock-names: Must include the following entries:
>> + - "pclk" PCIe GEN 100M PLL clock
>> + - "port" PCIe_x(A or B) RC clock gate
>> + - "general"PCIe Phy clock
>> + - "mipi" PCIe_x(A or B) 100M ref clock gate
>> +- resets: phandle to the reset lines.
>> +- reset-names: must contain "phy" "port" and "apb"
>> + - "phy" Share PHY reset
>> + - "port"Port A or B reset
>> + - "apb" Share APB reset
>> +- device_type:
>> + should be "pci". As specified in designware-pcie.txt
>> +
>> +
>> +Example configuration:
>> +
>> + pcie: pcie@f980 {
>> + compatible = "amlogic,axg-pcie", "snps,dw-pcie";
>> + reg = <0x0 0xf980 0x0 0x40
>> + 0x0 0xff646000 0x0 0x2000
>> + 0x0 0xff644000 0x0 0x2000
>> + 0x0 0xf9f0 0x0 0x10>;
>> + reg-names = "elbi", "cfg", "phy", "config";
> is the order of the reg-names correct?
> buildroot_openlinux_kernel_4.9_fbdev_20180706 uses 0xff646000 for the
> PHY (instead of 0xff646000) in mesong12a.dtsi and mesong12b.dtsi
>
It's correct, because memory map of AXG is different from G12.
MESON AXG memory map:
pcie_B: 0xFF648000~0xFF649FFF
pcie_A: 0xFF646000~0xff647FFF
pcie_phy: 0xFF644000~0xFF645FFF
MESON G12 memory map:
pcie_A: 0xFF648000~0xff649fff
pcie_phy: 0xFF646000~0xFF647FFF
Thanks.
>
> Regards
> Martin
>
> .
>
Re: [PATCH v5 1/2] dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller
On 2018/11/20 4:12, Martin Blumenstingl wrote:
> Hello Hanjie, Hello Yue,
>
> sorry for being late with my comment
>
> On Tue, Oct 9, 2018 at 3:53 AM Hanjie Lin wrote:
>>
>> From: Yue Wang
>>
>> The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare
>> PCI core. This patch adds documentation for the DT bindings in Meson PCIe
>> controller.
>>
>> Signed-off-by: Yue Wang
>> Signed-off-by: Hanjie Lin
>> Reviewed-by: Rob Herring
>> ---
>> .../devicetree/bindings/pci/amlogic,meson-pcie.txt | 70
>> ++
>> 1 file changed, 70 insertions(+)
>> create mode 100644
>> Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
>>
>> diff --git a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
>> b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
>> new file mode 100644
>> index 000..12b18f8
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
>> @@ -0,0 +1,70 @@
>> +Amlogic Meson AXG DWC PCIE SoC controller
>> +
>> +Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI
>> core.
>> +It shares common functions with the PCIe DesignWare core driver and
>> +inherits common properties defined in
>> +Documentation/devicetree/bindings/pci/designware-pci.txt.
>> +
>> +Additional properties are described here:
>> +
>> +Required properties:
>> +- compatible:
>> + should contain "amlogic,axg-pcie" to identify the core.
>> +- reg:
>> + should contain the configuration address space.
>> +- reg-names: Must be
>> + - "elbi"External local bus interface registers
>> + - "cfg" Meson specific registers
>> + - "phy" Meson PCIE PHY registers
> is this only the PCIe PHY registers or is it the registers of the PHY
> which supports USB3.0 and PCIe?
> buildroot_openlinux_kernel_4.9_fbdev_20180706 uses the following
> registers in the pcie_A node for the "phy" registers:
> 0x0 0xff646000 0x0 0x2000
> while the usb3_phy_v2 node uses:
> phy-reg = <0xff646000>;
>
It's correct.
In Meson AXG chip, this phy is dedicated to pcie.
But in Meson G12 chip, this phy is shared by pcie and usb3.0, only one module
can own the phy at one time.
>> + - "config" PCIe configuration space
>> +- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
>> +- clocks: Must contain an entry for each entry in clock-names.
>> +- clock-names: Must include the following entries:
>> + - "pclk" PCIe GEN 100M PLL clock
>> + - "port" PCIe_x(A or B) RC clock gate
>> + - "general"PCIe Phy clock
>> + - "mipi" PCIe_x(A or B) 100M ref clock gate
>> +- resets: phandle to the reset lines.
>> +- reset-names: must contain "phy" "port" and "apb"
>> + - "phy" Share PHY reset
>> + - "port"Port A or B reset
>> + - "apb" Share APB reset
>> +- device_type:
>> + should be "pci". As specified in designware-pcie.txt
>> +
>> +
>> +Example configuration:
>> +
>> + pcie: pcie@f980 {
>> + compatible = "amlogic,axg-pcie", "snps,dw-pcie";
>> + reg = <0x0 0xf980 0x0 0x40
>> + 0x0 0xff646000 0x0 0x2000
>> + 0x0 0xff644000 0x0 0x2000
>> + 0x0 0xf9f0 0x0 0x10>;
>> + reg-names = "elbi", "cfg", "phy", "config";
> is the order of the reg-names correct?
> buildroot_openlinux_kernel_4.9_fbdev_20180706 uses 0xff646000 for the
> PHY (instead of 0xff646000) in mesong12a.dtsi and mesong12b.dtsi
>
It's correct, because memory map of AXG is different from G12.
MESON AXG memory map:
pcie_B: 0xFF648000~0xFF649FFF
pcie_A: 0xFF646000~0xff647FFF
pcie_phy: 0xFF644000~0xFF645FFF
MESON G12 memory map:
pcie_A: 0xFF648000~0xff649fff
pcie_phy: 0xFF646000~0xFF647FFF
Thanks.
>
> Regards
> Martin
>
> .
>
[PATCH v5 2/2] PCI: amlogic: Add the Amlogic Meson PCIe controller driver
From: Yue Wang The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core. This patch adds the driver support for Meson PCIe controller. Signed-off-by: Yue Wang Signed-off-by: Hanjie Lin --- MAINTAINERS| 7 + drivers/pci/controller/dwc/Kconfig | 10 + drivers/pci/controller/dwc/Makefile| 1 + drivers/pci/controller/dwc/pci-meson.c | 593 + 4 files changed, 611 insertions(+) create mode 100644 drivers/pci/controller/dwc/pci-meson.c diff --git a/MAINTAINERS b/MAINTAINERS index 02a3961..da579ef 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11333,6 +11333,13 @@ L: linux-...@vger.kernel.org S: Maintained F: drivers/pci/controller/dwc/*spear* +PCIE DRIVER FOR AMLOGIC MESON +M: Yue Wang +L: linux-...@vger.kernel.org +L: linux-amlo...@lists.infradead.org +S: Maintained +F: drivers/pci/controller/dwc/pci-meson.c + PCMCIA SUBSYSTEM M: Dominik Brodowski T: git git://git.kernel.org/pub/scm/linux/kernel/git/brodo/pcmcia.git diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index 91b0194..7800322 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -193,4 +193,14 @@ config PCIE_HISI_STB help Say Y here if you want PCIe controller support on HiSilicon STB SoCs +config PCI_MESON + bool "MESON PCIe controller" + depends on PCI_MSI_IRQ_DOMAIN + select PCIE_DW_HOST + help + Say Y here if you want to enable PCI controller support on Amlogic + SoCs. The PCI controller on Amlogic is based on DesignWare hardware + and therefore the driver re-uses the DesignWare core functions to + implement the driver. + endmenu diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile index 5d2ce72..cf676bd 100644 --- a/drivers/pci/controller/dwc/Makefile +++ b/drivers/pci/controller/dwc/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o +obj-$(CONFIG_PCI_MESON) += pci-meson.o # The following drivers are for devices that use the generic ACPI # pci_root.c driver but don't support standard ECAM config access. diff --git a/drivers/pci/controller/dwc/pci-meson.c b/drivers/pci/controller/dwc/pci-meson.c new file mode 100644 index 000..2278b48 --- /dev/null +++ b/drivers/pci/controller/dwc/pci-meson.c @@ -0,0 +1,593 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PCIe host controller driver for Amlogic MESON SoCs + * + * Copyright (c) 2018 Amlogic, inc. + * Author: Yue Wang + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pcie-designware.h" + +#define to_meson_pcie(x) dev_get_drvdata((x)->dev) + +/* External local bus interface registers */ +#define PLR_OFFSET 0x700 +#define PCIE_PORT_LINK_CTRL_OFF(PLR_OFFSET + 0x10) +#define FAST_LINK_MODE BIT(7) +#define LINK_CAPABLE_MASK GENMASK(21, 16) +#define LINK_CAPABLE_X1BIT(16) + +#define PCIE_GEN2_CTRL_OFF (PLR_OFFSET + 0x10c) +#define NUM_OF_LANES_MASK GENMASK(12, 8) +#define NUM_OF_LANES_X1BIT(8) +#define DIRECT_SPEED_CHANGEBIT(17) + +#define TYPE1_HDR_OFFSET 0x0 +#define PCIE_STATUS_COMMAND(TYPE1_HDR_OFFSET + 0x04) +#define PCI_IO_EN BIT(0) +#define PCI_MEM_SPACE_EN BIT(1) +#define PCI_BUS_MASTER_EN BIT(2) + +#define PCIE_BASE_ADDR0(TYPE1_HDR_OFFSET + 0x10) +#define PCIE_BASE_ADDR1(TYPE1_HDR_OFFSET + 0x14) + +#define PCIE_CAP_OFFSET0x70 +#define PCIE_DEV_CTRL_DEV_STUS (PCIE_CAP_OFFSET + 0x08) +#define PCIE_CAP_MAX_PAYLOAD_MASK GENMASK(7, 5) +#define PCIE_CAP_MAX_PAYLOAD_SIZE(x) ((x) << 5) +#define PCIE_CAP_MAX_READ_REQ_MASK GENMASK(14, 12) +#define PCIE_CAP_MAX_READ_REQ_SIZE(x) ((x) << 12) + +#define PCI_CLASS_REVISION_MASKGENMASK(7, 0) + +/* PCIe specific config registers */ +#define PCIE_CFG0 0x0 +#define APP_LTSSM_ENABLE BIT(7) + +#define PCIE_CFG_STATUS12 0x30 +#define IS_SMLH_LINK_UP(x) ((x) & (1 << 6)) +#define IS_RDLH_LINK_UP(x) ((x) & (1 << 16)) +#define IS_LTSSM_UP(x) x) >> 10) & 0x1f) == 0x11) + +#define PCIE_CFG_STATUS17 0x44 +#define PM_CURRENT_STATE(x)(((x) >> 7) & 0x1) + +#define WAIT_LINKUP_TIMEOUT2000 +#define PORT_CLK_RATE 1UL +#define MAX_PAYLOAD_SIZE 256
[PATCH v5 2/2] PCI: amlogic: Add the Amlogic Meson PCIe controller driver
From: Yue Wang The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core. This patch adds the driver support for Meson PCIe controller. Signed-off-by: Yue Wang Signed-off-by: Hanjie Lin --- MAINTAINERS| 7 + drivers/pci/controller/dwc/Kconfig | 10 + drivers/pci/controller/dwc/Makefile| 1 + drivers/pci/controller/dwc/pci-meson.c | 593 + 4 files changed, 611 insertions(+) create mode 100644 drivers/pci/controller/dwc/pci-meson.c diff --git a/MAINTAINERS b/MAINTAINERS index 02a3961..da579ef 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11333,6 +11333,13 @@ L: linux-...@vger.kernel.org S: Maintained F: drivers/pci/controller/dwc/*spear* +PCIE DRIVER FOR AMLOGIC MESON +M: Yue Wang +L: linux-...@vger.kernel.org +L: linux-amlo...@lists.infradead.org +S: Maintained +F: drivers/pci/controller/dwc/pci-meson.c + PCMCIA SUBSYSTEM M: Dominik Brodowski T: git git://git.kernel.org/pub/scm/linux/kernel/git/brodo/pcmcia.git diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index 91b0194..7800322 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -193,4 +193,14 @@ config PCIE_HISI_STB help Say Y here if you want PCIe controller support on HiSilicon STB SoCs +config PCI_MESON + bool "MESON PCIe controller" + depends on PCI_MSI_IRQ_DOMAIN + select PCIE_DW_HOST + help + Say Y here if you want to enable PCI controller support on Amlogic + SoCs. The PCI controller on Amlogic is based on DesignWare hardware + and therefore the driver re-uses the DesignWare core functions to + implement the driver. + endmenu diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile index 5d2ce72..cf676bd 100644 --- a/drivers/pci/controller/dwc/Makefile +++ b/drivers/pci/controller/dwc/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o +obj-$(CONFIG_PCI_MESON) += pci-meson.o # The following drivers are for devices that use the generic ACPI # pci_root.c driver but don't support standard ECAM config access. diff --git a/drivers/pci/controller/dwc/pci-meson.c b/drivers/pci/controller/dwc/pci-meson.c new file mode 100644 index 000..2278b48 --- /dev/null +++ b/drivers/pci/controller/dwc/pci-meson.c @@ -0,0 +1,593 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PCIe host controller driver for Amlogic MESON SoCs + * + * Copyright (c) 2018 Amlogic, inc. + * Author: Yue Wang + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pcie-designware.h" + +#define to_meson_pcie(x) dev_get_drvdata((x)->dev) + +/* External local bus interface registers */ +#define PLR_OFFSET 0x700 +#define PCIE_PORT_LINK_CTRL_OFF(PLR_OFFSET + 0x10) +#define FAST_LINK_MODE BIT(7) +#define LINK_CAPABLE_MASK GENMASK(21, 16) +#define LINK_CAPABLE_X1BIT(16) + +#define PCIE_GEN2_CTRL_OFF (PLR_OFFSET + 0x10c) +#define NUM_OF_LANES_MASK GENMASK(12, 8) +#define NUM_OF_LANES_X1BIT(8) +#define DIRECT_SPEED_CHANGEBIT(17) + +#define TYPE1_HDR_OFFSET 0x0 +#define PCIE_STATUS_COMMAND(TYPE1_HDR_OFFSET + 0x04) +#define PCI_IO_EN BIT(0) +#define PCI_MEM_SPACE_EN BIT(1) +#define PCI_BUS_MASTER_EN BIT(2) + +#define PCIE_BASE_ADDR0(TYPE1_HDR_OFFSET + 0x10) +#define PCIE_BASE_ADDR1(TYPE1_HDR_OFFSET + 0x14) + +#define PCIE_CAP_OFFSET0x70 +#define PCIE_DEV_CTRL_DEV_STUS (PCIE_CAP_OFFSET + 0x08) +#define PCIE_CAP_MAX_PAYLOAD_MASK GENMASK(7, 5) +#define PCIE_CAP_MAX_PAYLOAD_SIZE(x) ((x) << 5) +#define PCIE_CAP_MAX_READ_REQ_MASK GENMASK(14, 12) +#define PCIE_CAP_MAX_READ_REQ_SIZE(x) ((x) << 12) + +#define PCI_CLASS_REVISION_MASKGENMASK(7, 0) + +/* PCIe specific config registers */ +#define PCIE_CFG0 0x0 +#define APP_LTSSM_ENABLE BIT(7) + +#define PCIE_CFG_STATUS12 0x30 +#define IS_SMLH_LINK_UP(x) ((x) & (1 << 6)) +#define IS_RDLH_LINK_UP(x) ((x) & (1 << 16)) +#define IS_LTSSM_UP(x) x) >> 10) & 0x1f) == 0x11) + +#define PCIE_CFG_STATUS17 0x44 +#define PM_CURRENT_STATE(x)(((x) >> 7) & 0x1) + +#define WAIT_LINKUP_TIMEOUT2000 +#define PORT_CLK_RATE 1UL +#define MAX_PAYLOAD_SIZE 256
[PATCH v5 0/2] add the Amlogic Meson PCIe controller driver
The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core. This patchset add the driver and dt-bindings of the controller. Changes since v4: [3] - fix kbuild test robot and compile warnings Changes since v3: [2] - modify subject format - update Kconfig - update MAINTAINER file - add comment and error handle for meson_pcie_get_mem_shared() - drop useless initialization code - add comment for meson_size_to_payload() - optimize meson_pcie_establish_link() return code - optimize meson_pcie_enable_interrupts() redundant function - drop device_attch related code - drop dw_pcie_ops read_dbi and write_dbi function - add error handle for meson_add_pcie_port() when probe Changes since v2: [1] - abandon phy driver, move reset to the controller - use devm_add_action_or_reset() to use clock res - format correcting Changes since v1: [0] - use gpio lib instead open code - move 'apb' and 'port' reset from phy driver - format correcting [0] : https://lkml.kernel.org/r/1534227522-186798-1-git-send-email-hanjie@amlogic.com [1] : https://lkml.kernel.org/r/1535096165-45827-1-git-send-email-hanjie@amlogic.com [2] : https://lkml.kernel.org/r/1537509820-52040-1-git-send-email-hanjie@amlogic.com [3] : https://lkml.kernel.org/r/1538999834-156423-3-git-send-email-hanjie@amlogic.com Yue Wang (2): dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller PCI: amlogic: Add the Amlogic Meson PCIe controller driver .../devicetree/bindings/pci/amlogic,meson-pcie.txt | 70 +++ MAINTAINERS| 7 + drivers/pci/controller/dwc/Kconfig | 10 + drivers/pci/controller/dwc/Makefile| 1 + drivers/pci/controller/dwc/pci-meson.c | 593 + 5 files changed, 681 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt create mode 100644 drivers/pci/controller/dwc/pci-meson.c -- 2.7.4
[PATCH v5 0/2] add the Amlogic Meson PCIe controller driver
The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core. This patchset add the driver and dt-bindings of the controller. Changes since v4: [3] - fix kbuild test robot and compile warnings Changes since v3: [2] - modify subject format - update Kconfig - update MAINTAINER file - add comment and error handle for meson_pcie_get_mem_shared() - drop useless initialization code - add comment for meson_size_to_payload() - optimize meson_pcie_establish_link() return code - optimize meson_pcie_enable_interrupts() redundant function - drop device_attch related code - drop dw_pcie_ops read_dbi and write_dbi function - add error handle for meson_add_pcie_port() when probe Changes since v2: [1] - abandon phy driver, move reset to the controller - use devm_add_action_or_reset() to use clock res - format correcting Changes since v1: [0] - use gpio lib instead open code - move 'apb' and 'port' reset from phy driver - format correcting [0] : https://lkml.kernel.org/r/1534227522-186798-1-git-send-email-hanjie@amlogic.com [1] : https://lkml.kernel.org/r/1535096165-45827-1-git-send-email-hanjie@amlogic.com [2] : https://lkml.kernel.org/r/1537509820-52040-1-git-send-email-hanjie@amlogic.com [3] : https://lkml.kernel.org/r/1538999834-156423-3-git-send-email-hanjie@amlogic.com Yue Wang (2): dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller PCI: amlogic: Add the Amlogic Meson PCIe controller driver .../devicetree/bindings/pci/amlogic,meson-pcie.txt | 70 +++ MAINTAINERS| 7 + drivers/pci/controller/dwc/Kconfig | 10 + drivers/pci/controller/dwc/Makefile| 1 + drivers/pci/controller/dwc/pci-meson.c | 593 + 5 files changed, 681 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt create mode 100644 drivers/pci/controller/dwc/pci-meson.c -- 2.7.4
[PATCH v5 1/2] dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller
From: Yue Wang
The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare
PCI core. This patch adds documentation for the DT bindings in Meson PCIe
controller.
Signed-off-by: Yue Wang
Signed-off-by: Hanjie Lin
Reviewed-by: Rob Herring
---
.../devicetree/bindings/pci/amlogic,meson-pcie.txt | 70 ++
1 file changed, 70 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
diff --git a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
new file mode 100644
index 000..12b18f8
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
@@ -0,0 +1,70 @@
+Amlogic Meson AXG DWC PCIE SoC controller
+
+Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI
core.
+It shares common functions with the PCIe DesignWare core driver and
+inherits common properties defined in
+Documentation/devicetree/bindings/pci/designware-pci.txt.
+
+Additional properties are described here:
+
+Required properties:
+- compatible:
+ should contain "amlogic,axg-pcie" to identify the core.
+- reg:
+ should contain the configuration address space.
+- reg-names: Must be
+ - "elbi"External local bus interface registers
+ - "cfg" Meson specific registers
+ - "phy" Meson PCIE PHY registers
+ - "config" PCIe configuration space
+- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
+- clocks: Must contain an entry for each entry in clock-names.
+- clock-names: Must include the following entries:
+ - "pclk" PCIe GEN 100M PLL clock
+ - "port" PCIe_x(A or B) RC clock gate
+ - "general"PCIe Phy clock
+ - "mipi" PCIe_x(A or B) 100M ref clock gate
+- resets: phandle to the reset lines.
+- reset-names: must contain "phy" "port" and "apb"
+ - "phy" Share PHY reset
+ - "port"Port A or B reset
+ - "apb" Share APB reset
+- device_type:
+ should be "pci". As specified in designware-pcie.txt
+
+
+Example configuration:
+
+ pcie: pcie@f980 {
+ compatible = "amlogic,axg-pcie", "snps,dw-pcie";
+ reg = <0x0 0xf980 0x0 0x40
+ 0x0 0xff646000 0x0 0x2000
+ 0x0 0xff644000 0x0 0x2000
+ 0x0 0xf9f0 0x0 0x10>;
+ reg-names = "elbi", "cfg", "phy", "config";
+ reset-gpios = < GPIOX_19 GPIO_ACTIVE_HIGH>;
+ interrupts = ;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 GIC_SPI 179
IRQ_TYPE_EDGE_RISING>;
+ bus-range = <0x0 0xff>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x8200 0 0 0x0 0xf9c0 0 0x0030>;
+
+ clocks = < CLKID_USB
+CLKID_MIPI_ENABLE
+CLKID_PCIE_A
+CLKID_PCIE_CML_EN0>;
+ clock-names = "general",
+ "mipi",
+ "pclk",
+ "port";
+ resets = < RESET_PCIE_PHY>,
+ < RESET_PCIE_A>,
+ < RESET_PCIE_APB>;
+ reset-names = "phy",
+ "port",
+ "apb";
+ };
--
2.7.4
[PATCH v5 1/2] dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller
From: Yue Wang
The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare
PCI core. This patch adds documentation for the DT bindings in Meson PCIe
controller.
Signed-off-by: Yue Wang
Signed-off-by: Hanjie Lin
Reviewed-by: Rob Herring
---
.../devicetree/bindings/pci/amlogic,meson-pcie.txt | 70 ++
1 file changed, 70 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
diff --git a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
new file mode 100644
index 000..12b18f8
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
@@ -0,0 +1,70 @@
+Amlogic Meson AXG DWC PCIE SoC controller
+
+Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI
core.
+It shares common functions with the PCIe DesignWare core driver and
+inherits common properties defined in
+Documentation/devicetree/bindings/pci/designware-pci.txt.
+
+Additional properties are described here:
+
+Required properties:
+- compatible:
+ should contain "amlogic,axg-pcie" to identify the core.
+- reg:
+ should contain the configuration address space.
+- reg-names: Must be
+ - "elbi"External local bus interface registers
+ - "cfg" Meson specific registers
+ - "phy" Meson PCIE PHY registers
+ - "config" PCIe configuration space
+- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
+- clocks: Must contain an entry for each entry in clock-names.
+- clock-names: Must include the following entries:
+ - "pclk" PCIe GEN 100M PLL clock
+ - "port" PCIe_x(A or B) RC clock gate
+ - "general"PCIe Phy clock
+ - "mipi" PCIe_x(A or B) 100M ref clock gate
+- resets: phandle to the reset lines.
+- reset-names: must contain "phy" "port" and "apb"
+ - "phy" Share PHY reset
+ - "port"Port A or B reset
+ - "apb" Share APB reset
+- device_type:
+ should be "pci". As specified in designware-pcie.txt
+
+
+Example configuration:
+
+ pcie: pcie@f980 {
+ compatible = "amlogic,axg-pcie", "snps,dw-pcie";
+ reg = <0x0 0xf980 0x0 0x40
+ 0x0 0xff646000 0x0 0x2000
+ 0x0 0xff644000 0x0 0x2000
+ 0x0 0xf9f0 0x0 0x10>;
+ reg-names = "elbi", "cfg", "phy", "config";
+ reset-gpios = < GPIOX_19 GPIO_ACTIVE_HIGH>;
+ interrupts = ;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 GIC_SPI 179
IRQ_TYPE_EDGE_RISING>;
+ bus-range = <0x0 0xff>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x8200 0 0 0x0 0xf9c0 0 0x0030>;
+
+ clocks = < CLKID_USB
+CLKID_MIPI_ENABLE
+CLKID_PCIE_A
+CLKID_PCIE_CML_EN0>;
+ clock-names = "general",
+ "mipi",
+ "pclk",
+ "port";
+ resets = < RESET_PCIE_PHY>,
+ < RESET_PCIE_A>,
+ < RESET_PCIE_APB>;
+ reset-names = "phy",
+ "port",
+ "apb";
+ };
--
2.7.4
[PATCH v4 2/2] PCI: amlogic: Add the Amlogic Meson PCIe controller driver
From: Yue Wang The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core. This patch adds the driver support for Meson PCIe controller. Signed-off-by: Yue Wang Signed-off-by: Hanjie Lin --- MAINTAINERS| 7 + drivers/pci/controller/dwc/Kconfig | 10 + drivers/pci/controller/dwc/Makefile| 1 + drivers/pci/controller/dwc/pci-meson.c | 593 + 4 files changed, 611 insertions(+) create mode 100644 drivers/pci/controller/dwc/pci-meson.c diff --git a/MAINTAINERS b/MAINTAINERS index 02a3961..da579ef 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11333,6 +11333,13 @@ L: linux-...@vger.kernel.org S: Maintained F: drivers/pci/controller/dwc/*spear* +PCIE DRIVER FOR AMLOGIC MESON +M: Yue Wang +L: linux-...@vger.kernel.org +L: linux-amlo...@lists.infradead.org +S: Maintained +F: drivers/pci/controller/dwc/pci-meson.c + PCMCIA SUBSYSTEM M: Dominik Brodowski T: git git://git.kernel.org/pub/scm/linux/kernel/git/brodo/pcmcia.git diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index 91b0194..7800322 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -193,4 +193,14 @@ config PCIE_HISI_STB help Say Y here if you want PCIe controller support on HiSilicon STB SoCs +config PCI_MESON + bool "MESON PCIe controller" + depends on PCI_MSI_IRQ_DOMAIN + select PCIE_DW_HOST + help + Say Y here if you want to enable PCI controller support on Amlogic + SoCs. The PCI controller on Amlogic is based on DesignWare hardware + and therefore the driver re-uses the DesignWare core functions to + implement the driver. + endmenu diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile index 5d2ce72..cf676bd 100644 --- a/drivers/pci/controller/dwc/Makefile +++ b/drivers/pci/controller/dwc/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o +obj-$(CONFIG_PCI_MESON) += pci-meson.o # The following drivers are for devices that use the generic ACPI # pci_root.c driver but don't support standard ECAM config access. diff --git a/drivers/pci/controller/dwc/pci-meson.c b/drivers/pci/controller/dwc/pci-meson.c new file mode 100644 index 000..078d28ad --- /dev/null +++ b/drivers/pci/controller/dwc/pci-meson.c @@ -0,0 +1,593 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PCIe host controller driver for Amlogic MESON SoCs + * + * Copyright (c) 2018 Amlogic, inc. + * Author: Yue Wang + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pcie-designware.h" + +#define to_meson_pcie(x) dev_get_drvdata((x)->dev) + +/* External local bus interface registers */ +#define PLR_OFFSET 0x700 +#define PCIE_PORT_LINK_CTRL_OFF(PLR_OFFSET + 0x10) +#define FAST_LINK_MODE BIT(7) +#define LINK_CAPABLE_MASK GENMASK(21, 16) +#define LINK_CAPABLE_X1BIT(16) + +#define PCIE_GEN2_CTRL_OFF (PLR_OFFSET + 0x10c) +#define NUM_OF_LANES_MASK GENMASK(12, 8) +#define NUM_OF_LANES_X1BIT(8) +#define DIRECT_SPEED_CHANGEBIT(17) + +#define TYPE1_HDR_OFFSET 0x0 +#define PCIE_STATUS_COMMAND(TYPE1_HDR_OFFSET + 0x04) +#define PCI_IO_EN BIT(0) +#define PCI_MEM_SPACE_EN BIT(1) +#define PCI_BUS_MASTER_EN BIT(2) + +#define PCIE_BASE_ADDR0(TYPE1_HDR_OFFSET + 0x10) +#define PCIE_BASE_ADDR1(TYPE1_HDR_OFFSET + 0x14) + +#define PCIE_CAP_OFFSET0x70 +#define PCIE_DEV_CTRL_DEV_STUS (PCIE_CAP_OFFSET + 0x08) +#define PCIE_CAP_MAX_PAYLOAD_MASK GENMASK(7, 5) +#define PCIE_CAP_MAX_PAYLOAD_SIZE(x) ((x) << 5) +#define PCIE_CAP_MAX_READ_REQ_MASK GENMASK(14, 12) +#define PCIE_CAP_MAX_READ_REQ_SIZE(x) ((x) << 12) + +#define PCI_CLASS_REVISION_MASKGENMASK(7, 0) + +/* PCIe specific config registers */ +#define PCIE_CFG0 0x0 +#define APP_LTSSM_ENABLE BIT(7) + +#define PCIE_CFG_STATUS12 0x30 +#define IS_SMLH_LINK_UP(x) ((x) & (1 << 6)) +#define IS_RDLH_LINK_UP(x) ((x) & (1 << 16)) +#define IS_LTSSM_UP(x) x) >> 10) & 0x1f) == 0x11) + +#define PCIE_CFG_STATUS17 0x44 +#define PM_CURRENT_STATE(x)(((x) >> 7) & 0x1) + +#define WAIT_LINKUP_TIMEOUT2000 +#define PORT_CLK_RATE 1UL +#define MAX_PAYLOAD_
[PATCH v4 1/2] dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller
From: Yue Wang
The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare
PCI core. This patch adds documentation for the DT bindings in Meson PCIe
controller.
Signed-off-by: Yue Wang
Signed-off-by: Hanjie Lin
Reviewed-by: Rob Herring
---
.../devicetree/bindings/pci/amlogic,meson-pcie.txt | 70 ++
1 file changed, 70 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
diff --git a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
new file mode 100644
index 000..12b18f8
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
@@ -0,0 +1,70 @@
+Amlogic Meson AXG DWC PCIE SoC controller
+
+Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI
core.
+It shares common functions with the PCIe DesignWare core driver and
+inherits common properties defined in
+Documentation/devicetree/bindings/pci/designware-pci.txt.
+
+Additional properties are described here:
+
+Required properties:
+- compatible:
+ should contain "amlogic,axg-pcie" to identify the core.
+- reg:
+ should contain the configuration address space.
+- reg-names: Must be
+ - "elbi"External local bus interface registers
+ - "cfg" Meson specific registers
+ - "phy" Meson PCIE PHY registers
+ - "config" PCIe configuration space
+- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
+- clocks: Must contain an entry for each entry in clock-names.
+- clock-names: Must include the following entries:
+ - "pclk" PCIe GEN 100M PLL clock
+ - "port" PCIe_x(A or B) RC clock gate
+ - "general"PCIe Phy clock
+ - "mipi" PCIe_x(A or B) 100M ref clock gate
+- resets: phandle to the reset lines.
+- reset-names: must contain "phy" "port" and "apb"
+ - "phy" Share PHY reset
+ - "port"Port A or B reset
+ - "apb" Share APB reset
+- device_type:
+ should be "pci". As specified in designware-pcie.txt
+
+
+Example configuration:
+
+ pcie: pcie@f980 {
+ compatible = "amlogic,axg-pcie", "snps,dw-pcie";
+ reg = <0x0 0xf980 0x0 0x40
+ 0x0 0xff646000 0x0 0x2000
+ 0x0 0xff644000 0x0 0x2000
+ 0x0 0xf9f0 0x0 0x10>;
+ reg-names = "elbi", "cfg", "phy", "config";
+ reset-gpios = < GPIOX_19 GPIO_ACTIVE_HIGH>;
+ interrupts = ;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 GIC_SPI 179
IRQ_TYPE_EDGE_RISING>;
+ bus-range = <0x0 0xff>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x8200 0 0 0x0 0xf9c0 0 0x0030>;
+
+ clocks = < CLKID_USB
+CLKID_MIPI_ENABLE
+CLKID_PCIE_A
+CLKID_PCIE_CML_EN0>;
+ clock-names = "general",
+ "mipi",
+ "pclk",
+ "port";
+ resets = < RESET_PCIE_PHY>,
+ < RESET_PCIE_A>,
+ < RESET_PCIE_APB>;
+ reset-names = "phy",
+ "port",
+ "apb";
+ };
--
2.7.4
[PATCH v4 0/2] add the Amlogic Meson PCIe controller driver
The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core. This patchset add the driver and dt-bindings of the controller. Changes since v3: [2] - modify subject format - update Kconfig - update MAINTAINER file - add comment and error handle for meson_pcie_get_mem_shared() - drop useless initialization code - add comment for meson_size_to_payload() - optimize meson_pcie_establish_link() return code - optimize meson_pcie_enable_interrupts() redundant function - drop device_attch related code - drop dw_pcie_ops read_dbi and write_dbi function - add error handle for meson_add_pcie_port() when probe Changes since v2: [1] - abandon phy driver, move reset to the controller - use devm_add_action_or_reset() to use clock res - format correcting Changes since v1: [0] - use gpio lib instead open code - move 'apb' and 'port' reset from phy driver - format correcting [0] : https://lkml.kernel.org/r/1534227522-186798-1-git-send-email-hanjie@amlogic.com [1] : https://lkml.kernel.org/r/1535096165-45827-1-git-send-email-hanjie@amlogic.com [2] : https://lkml.kernel.org/r/1537509820-52040-1-git-send-email-hanjie@amlogic.com Yue Wang (2): dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller PCI: amlogic: Add the Amlogic Meson PCIe controller driver .../devicetree/bindings/pci/amlogic,meson-pcie.txt | 70 +++ MAINTAINERS| 7 + drivers/pci/controller/dwc/Kconfig | 10 + drivers/pci/controller/dwc/Makefile| 1 + drivers/pci/controller/dwc/pci-meson.c | 593 + 5 files changed, 681 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt create mode 100644 drivers/pci/controller/dwc/pci-meson.c -- 2.7.4
[PATCH v4 1/2] dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller
From: Yue Wang
The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare
PCI core. This patch adds documentation for the DT bindings in Meson PCIe
controller.
Signed-off-by: Yue Wang
Signed-off-by: Hanjie Lin
Reviewed-by: Rob Herring
---
.../devicetree/bindings/pci/amlogic,meson-pcie.txt | 70 ++
1 file changed, 70 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
diff --git a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
new file mode 100644
index 000..12b18f8
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
@@ -0,0 +1,70 @@
+Amlogic Meson AXG DWC PCIE SoC controller
+
+Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI
core.
+It shares common functions with the PCIe DesignWare core driver and
+inherits common properties defined in
+Documentation/devicetree/bindings/pci/designware-pci.txt.
+
+Additional properties are described here:
+
+Required properties:
+- compatible:
+ should contain "amlogic,axg-pcie" to identify the core.
+- reg:
+ should contain the configuration address space.
+- reg-names: Must be
+ - "elbi"External local bus interface registers
+ - "cfg" Meson specific registers
+ - "phy" Meson PCIE PHY registers
+ - "config" PCIe configuration space
+- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
+- clocks: Must contain an entry for each entry in clock-names.
+- clock-names: Must include the following entries:
+ - "pclk" PCIe GEN 100M PLL clock
+ - "port" PCIe_x(A or B) RC clock gate
+ - "general"PCIe Phy clock
+ - "mipi" PCIe_x(A or B) 100M ref clock gate
+- resets: phandle to the reset lines.
+- reset-names: must contain "phy" "port" and "apb"
+ - "phy" Share PHY reset
+ - "port"Port A or B reset
+ - "apb" Share APB reset
+- device_type:
+ should be "pci". As specified in designware-pcie.txt
+
+
+Example configuration:
+
+ pcie: pcie@f980 {
+ compatible = "amlogic,axg-pcie", "snps,dw-pcie";
+ reg = <0x0 0xf980 0x0 0x40
+ 0x0 0xff646000 0x0 0x2000
+ 0x0 0xff644000 0x0 0x2000
+ 0x0 0xf9f0 0x0 0x10>;
+ reg-names = "elbi", "cfg", "phy", "config";
+ reset-gpios = < GPIOX_19 GPIO_ACTIVE_HIGH>;
+ interrupts = ;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 GIC_SPI 179
IRQ_TYPE_EDGE_RISING>;
+ bus-range = <0x0 0xff>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x8200 0 0 0x0 0xf9c0 0 0x0030>;
+
+ clocks = < CLKID_USB
+CLKID_MIPI_ENABLE
+CLKID_PCIE_A
+CLKID_PCIE_CML_EN0>;
+ clock-names = "general",
+ "mipi",
+ "pclk",
+ "port";
+ resets = < RESET_PCIE_PHY>,
+ < RESET_PCIE_A>,
+ < RESET_PCIE_APB>;
+ reset-names = "phy",
+ "port",
+ "apb";
+ };
--
2.7.4
[PATCH v4 0/2] add the Amlogic Meson PCIe controller driver
The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core. This patchset add the driver and dt-bindings of the controller. Changes since v3: [2] - modify subject format - update Kconfig - update MAINTAINER file - add comment and error handle for meson_pcie_get_mem_shared() - drop useless initialization code - add comment for meson_size_to_payload() - optimize meson_pcie_establish_link() return code - optimize meson_pcie_enable_interrupts() redundant function - drop device_attch related code - drop dw_pcie_ops read_dbi and write_dbi function - add error handle for meson_add_pcie_port() when probe Changes since v2: [1] - abandon phy driver, move reset to the controller - use devm_add_action_or_reset() to use clock res - format correcting Changes since v1: [0] - use gpio lib instead open code - move 'apb' and 'port' reset from phy driver - format correcting [0] : https://lkml.kernel.org/r/1534227522-186798-1-git-send-email-hanjie@amlogic.com [1] : https://lkml.kernel.org/r/1535096165-45827-1-git-send-email-hanjie@amlogic.com [2] : https://lkml.kernel.org/r/1537509820-52040-1-git-send-email-hanjie@amlogic.com Yue Wang (2): dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller PCI: amlogic: Add the Amlogic Meson PCIe controller driver .../devicetree/bindings/pci/amlogic,meson-pcie.txt | 70 +++ MAINTAINERS| 7 + drivers/pci/controller/dwc/Kconfig | 10 + drivers/pci/controller/dwc/Makefile| 1 + drivers/pci/controller/dwc/pci-meson.c | 593 + 5 files changed, 681 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt create mode 100644 drivers/pci/controller/dwc/pci-meson.c -- 2.7.4
[PATCH v4 2/2] PCI: amlogic: Add the Amlogic Meson PCIe controller driver
From: Yue Wang The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core. This patch adds the driver support for Meson PCIe controller. Signed-off-by: Yue Wang Signed-off-by: Hanjie Lin --- MAINTAINERS| 7 + drivers/pci/controller/dwc/Kconfig | 10 + drivers/pci/controller/dwc/Makefile| 1 + drivers/pci/controller/dwc/pci-meson.c | 593 + 4 files changed, 611 insertions(+) create mode 100644 drivers/pci/controller/dwc/pci-meson.c diff --git a/MAINTAINERS b/MAINTAINERS index 02a3961..da579ef 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11333,6 +11333,13 @@ L: linux-...@vger.kernel.org S: Maintained F: drivers/pci/controller/dwc/*spear* +PCIE DRIVER FOR AMLOGIC MESON +M: Yue Wang +L: linux-...@vger.kernel.org +L: linux-amlo...@lists.infradead.org +S: Maintained +F: drivers/pci/controller/dwc/pci-meson.c + PCMCIA SUBSYSTEM M: Dominik Brodowski T: git git://git.kernel.org/pub/scm/linux/kernel/git/brodo/pcmcia.git diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index 91b0194..7800322 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -193,4 +193,14 @@ config PCIE_HISI_STB help Say Y here if you want PCIe controller support on HiSilicon STB SoCs +config PCI_MESON + bool "MESON PCIe controller" + depends on PCI_MSI_IRQ_DOMAIN + select PCIE_DW_HOST + help + Say Y here if you want to enable PCI controller support on Amlogic + SoCs. The PCI controller on Amlogic is based on DesignWare hardware + and therefore the driver re-uses the DesignWare core functions to + implement the driver. + endmenu diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile index 5d2ce72..cf676bd 100644 --- a/drivers/pci/controller/dwc/Makefile +++ b/drivers/pci/controller/dwc/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o +obj-$(CONFIG_PCI_MESON) += pci-meson.o # The following drivers are for devices that use the generic ACPI # pci_root.c driver but don't support standard ECAM config access. diff --git a/drivers/pci/controller/dwc/pci-meson.c b/drivers/pci/controller/dwc/pci-meson.c new file mode 100644 index 000..078d28ad --- /dev/null +++ b/drivers/pci/controller/dwc/pci-meson.c @@ -0,0 +1,593 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PCIe host controller driver for Amlogic MESON SoCs + * + * Copyright (c) 2018 Amlogic, inc. + * Author: Yue Wang + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pcie-designware.h" + +#define to_meson_pcie(x) dev_get_drvdata((x)->dev) + +/* External local bus interface registers */ +#define PLR_OFFSET 0x700 +#define PCIE_PORT_LINK_CTRL_OFF(PLR_OFFSET + 0x10) +#define FAST_LINK_MODE BIT(7) +#define LINK_CAPABLE_MASK GENMASK(21, 16) +#define LINK_CAPABLE_X1BIT(16) + +#define PCIE_GEN2_CTRL_OFF (PLR_OFFSET + 0x10c) +#define NUM_OF_LANES_MASK GENMASK(12, 8) +#define NUM_OF_LANES_X1BIT(8) +#define DIRECT_SPEED_CHANGEBIT(17) + +#define TYPE1_HDR_OFFSET 0x0 +#define PCIE_STATUS_COMMAND(TYPE1_HDR_OFFSET + 0x04) +#define PCI_IO_EN BIT(0) +#define PCI_MEM_SPACE_EN BIT(1) +#define PCI_BUS_MASTER_EN BIT(2) + +#define PCIE_BASE_ADDR0(TYPE1_HDR_OFFSET + 0x10) +#define PCIE_BASE_ADDR1(TYPE1_HDR_OFFSET + 0x14) + +#define PCIE_CAP_OFFSET0x70 +#define PCIE_DEV_CTRL_DEV_STUS (PCIE_CAP_OFFSET + 0x08) +#define PCIE_CAP_MAX_PAYLOAD_MASK GENMASK(7, 5) +#define PCIE_CAP_MAX_PAYLOAD_SIZE(x) ((x) << 5) +#define PCIE_CAP_MAX_READ_REQ_MASK GENMASK(14, 12) +#define PCIE_CAP_MAX_READ_REQ_SIZE(x) ((x) << 12) + +#define PCI_CLASS_REVISION_MASKGENMASK(7, 0) + +/* PCIe specific config registers */ +#define PCIE_CFG0 0x0 +#define APP_LTSSM_ENABLE BIT(7) + +#define PCIE_CFG_STATUS12 0x30 +#define IS_SMLH_LINK_UP(x) ((x) & (1 << 6)) +#define IS_RDLH_LINK_UP(x) ((x) & (1 << 16)) +#define IS_LTSSM_UP(x) x) >> 10) & 0x1f) == 0x11) + +#define PCIE_CFG_STATUS17 0x44 +#define PM_CURRENT_STATE(x)(((x) >> 7) & 0x1) + +#define WAIT_LINKUP_TIMEOUT2000 +#define PORT_CLK_RATE 1UL +#define MAX_PAYLOAD_
Re: [RESEND PATCH v3 2/2] PCI: meson: add the Amlogic Meson PCIe controller driver
On 2018/9/24 16:34, Gustavo Pimentel wrote: > Hi Hanjie, > > On 21/09/2018 07:03, Hanjie Lin wrote: >> From: Yue Wang >> >> The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare >> PCI core. This patch adds the driver support for Meson PCIe controller. >> >> Signed-off-by: Yue Wang >> Signed-off-by: Hanjie Lin >> --- >> drivers/pci/controller/dwc/Kconfig | 12 + >> drivers/pci/controller/dwc/Makefile| 1 + >> drivers/pci/controller/dwc/pci-meson.c | 617 >> + >> 3 files changed, 630 insertions(+) >> create mode 100644 drivers/pci/controller/dwc/pci-meson.c >> >> diff --git a/drivers/pci/controller/dwc/Kconfig >> b/drivers/pci/controller/dwc/Kconfig >> index 91b0194..6cb36f6 100644 >> --- a/drivers/pci/controller/dwc/Kconfig >> +++ b/drivers/pci/controller/dwc/Kconfig >> @@ -193,4 +193,16 @@ config PCIE_HISI_STB >> help >>Say Y here if you want PCIe controller support on HiSilicon STB >> SoCs >> >> +config PCI_MESON >> +bool "MESON PCIe controller" >> +depends on PCI >> +depends on PCI_MSI_IRQ_DOMAIN > > I would suggest to compress the previous 2 line into in just one, like: > depends on PCI && PCI_MSI_IRQ_DOMAIN > > Regards, > Gustavo > Right, depends on PCI is unnecessary actually. I will fix it. Thanks, Hanjie >> +select PCIEPORTBUS >> +select PCIE_DW_HOST >> +help >> + Say Y here if you want to enable PCI controller support on Amlogic >> + SoCs. The PCI controller on Amlogic is based on DesignWare hardware >> + and therefore the driver re-uses the DesignWare core functions to >> + implement the driver. >> + >> endmenu >> diff --git a/drivers/pci/controller/dwc/Makefile >> b/drivers/pci/controller/dwc/Makefile >> index 5d2ce72..cf676bd 100644 >> --- a/drivers/pci/controller/dwc/Makefile >> +++ b/drivers/pci/controller/dwc/Makefile >> @@ -14,6 +14,7 @@ obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o >> obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o >> obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o >> obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o >> +obj-$(CONFIG_PCI_MESON) += pci-meson.o >> >> # The following drivers are for devices that use the generic ACPI >> # pci_root.c driver but don't support standard ECAM config access. >> diff --git a/drivers/pci/controller/dwc/pci-meson.c >> b/drivers/pci/controller/dwc/pci-meson.c >> new file mode 100644 >> index 000..9c92a89 >> --- /dev/null >> +++ b/drivers/pci/controller/dwc/pci-meson.c >> @@ -0,0 +1,617 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * PCIe host controller driver for Amlogic MESON SoCs >> + * >> + * Copyright (c) 2018 Amlogic, inc. >> + * Author: Yue Wang >> + */ >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> + >> +#include "pcie-designware.h" >> + >> +#define to_meson_pcie(x) dev_get_drvdata((x)->dev) >> + >> +/* External local bus interface registers */ >> +#define PLR_OFFSET 0x700 >> +#define PCIE_PORT_LINK_CTRL_OFF (PLR_OFFSET + 0x10) >> +#define FAST_LINK_MODE BIT(7) >> +#define LINK_CAPABLE_MASK GENMASK(21, 16) >> +#define LINK_CAPABLE_X1 BIT(16) >> + >> +#define PCIE_GEN2_CTRL_OFF (PLR_OFFSET + 0x10c) >> +#define NUM_OF_LANES_MASK GENMASK(12, 8) >> +#define NUM_OF_LANES_X1 BIT(8) >> +#define DIRECT_SPEED_CHANGE BIT(17) >> + >> +#define TYPE1_HDR_OFFSET0x0 >> +#define PCIE_STATUS_COMMAND (TYPE1_HDR_OFFSET + 0x04) >> +#define PCI_IO_EN BIT(0) >> +#define PCI_MEM_SPACE_ENBIT(1) >> +#define PCI_BUS_MASTER_EN BIT(2) >> + >> +#define PCIE_BASE_ADDR0 (TYPE1_HDR_OFFSET + 0x10) >> +#define PCIE_BASE_ADDR1 (TYPE1_HDR_OFFSET + 0x14) >> + >> +#define PCIE_CAP_OFFSET 0x70 >> +#define PCIE_DEV_CTRL_DEV_STUS (PCIE_CAP_OFFSET + 0x08) >> +#define PCIE_CAP_MAX_PAYLOAD_MASK GENMASK(7, 5) >> +#define PCIE_CAP_MAX_PAYLOAD_SIZE(x)((x) << 5) >> +#define PCIE_CAP_MAX_READ_REQ_MASK GENMASK(14, 12) >> +#define PCIE_CAP_MAX_READ_REQ_SIZE(x)
Re: [RESEND PATCH v3 2/2] PCI: meson: add the Amlogic Meson PCIe controller driver
On 2018/9/24 16:34, Gustavo Pimentel wrote: > Hi Hanjie, > > On 21/09/2018 07:03, Hanjie Lin wrote: >> From: Yue Wang >> >> The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare >> PCI core. This patch adds the driver support for Meson PCIe controller. >> >> Signed-off-by: Yue Wang >> Signed-off-by: Hanjie Lin >> --- >> drivers/pci/controller/dwc/Kconfig | 12 + >> drivers/pci/controller/dwc/Makefile| 1 + >> drivers/pci/controller/dwc/pci-meson.c | 617 >> + >> 3 files changed, 630 insertions(+) >> create mode 100644 drivers/pci/controller/dwc/pci-meson.c >> >> diff --git a/drivers/pci/controller/dwc/Kconfig >> b/drivers/pci/controller/dwc/Kconfig >> index 91b0194..6cb36f6 100644 >> --- a/drivers/pci/controller/dwc/Kconfig >> +++ b/drivers/pci/controller/dwc/Kconfig >> @@ -193,4 +193,16 @@ config PCIE_HISI_STB >> help >>Say Y here if you want PCIe controller support on HiSilicon STB >> SoCs >> >> +config PCI_MESON >> +bool "MESON PCIe controller" >> +depends on PCI >> +depends on PCI_MSI_IRQ_DOMAIN > > I would suggest to compress the previous 2 line into in just one, like: > depends on PCI && PCI_MSI_IRQ_DOMAIN > > Regards, > Gustavo > Right, depends on PCI is unnecessary actually. I will fix it. Thanks, Hanjie >> +select PCIEPORTBUS >> +select PCIE_DW_HOST >> +help >> + Say Y here if you want to enable PCI controller support on Amlogic >> + SoCs. The PCI controller on Amlogic is based on DesignWare hardware >> + and therefore the driver re-uses the DesignWare core functions to >> + implement the driver. >> + >> endmenu >> diff --git a/drivers/pci/controller/dwc/Makefile >> b/drivers/pci/controller/dwc/Makefile >> index 5d2ce72..cf676bd 100644 >> --- a/drivers/pci/controller/dwc/Makefile >> +++ b/drivers/pci/controller/dwc/Makefile >> @@ -14,6 +14,7 @@ obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o >> obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o >> obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o >> obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o >> +obj-$(CONFIG_PCI_MESON) += pci-meson.o >> >> # The following drivers are for devices that use the generic ACPI >> # pci_root.c driver but don't support standard ECAM config access. >> diff --git a/drivers/pci/controller/dwc/pci-meson.c >> b/drivers/pci/controller/dwc/pci-meson.c >> new file mode 100644 >> index 000..9c92a89 >> --- /dev/null >> +++ b/drivers/pci/controller/dwc/pci-meson.c >> @@ -0,0 +1,617 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * PCIe host controller driver for Amlogic MESON SoCs >> + * >> + * Copyright (c) 2018 Amlogic, inc. >> + * Author: Yue Wang >> + */ >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> + >> +#include "pcie-designware.h" >> + >> +#define to_meson_pcie(x) dev_get_drvdata((x)->dev) >> + >> +/* External local bus interface registers */ >> +#define PLR_OFFSET 0x700 >> +#define PCIE_PORT_LINK_CTRL_OFF (PLR_OFFSET + 0x10) >> +#define FAST_LINK_MODE BIT(7) >> +#define LINK_CAPABLE_MASK GENMASK(21, 16) >> +#define LINK_CAPABLE_X1 BIT(16) >> + >> +#define PCIE_GEN2_CTRL_OFF (PLR_OFFSET + 0x10c) >> +#define NUM_OF_LANES_MASK GENMASK(12, 8) >> +#define NUM_OF_LANES_X1 BIT(8) >> +#define DIRECT_SPEED_CHANGE BIT(17) >> + >> +#define TYPE1_HDR_OFFSET0x0 >> +#define PCIE_STATUS_COMMAND (TYPE1_HDR_OFFSET + 0x04) >> +#define PCI_IO_EN BIT(0) >> +#define PCI_MEM_SPACE_ENBIT(1) >> +#define PCI_BUS_MASTER_EN BIT(2) >> + >> +#define PCIE_BASE_ADDR0 (TYPE1_HDR_OFFSET + 0x10) >> +#define PCIE_BASE_ADDR1 (TYPE1_HDR_OFFSET + 0x14) >> + >> +#define PCIE_CAP_OFFSET 0x70 >> +#define PCIE_DEV_CTRL_DEV_STUS (PCIE_CAP_OFFSET + 0x08) >> +#define PCIE_CAP_MAX_PAYLOAD_MASK GENMASK(7, 5) >> +#define PCIE_CAP_MAX_PAYLOAD_SIZE(x)((x) << 5) >> +#define PCIE_CAP_MAX_READ_REQ_MASK GENMASK(14, 12) >> +#define PCIE_CAP_MAX_READ_REQ_SIZE(x)
Re: [RESEND PATCH v3 2/2] PCI: meson: add the Amlogic Meson PCIe controller driver
On 2018/9/21 22:47, Lorenzo Pieralisi wrote: > On Fri, Sep 21, 2018 at 02:03:40PM +0800, Hanjie Lin wrote: >> From: Yue Wang >> >> The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare >> PCI core. This patch adds the driver support for Meson PCIe controller. > > Please read: > > https://marc.info/?l=linux-pci=150905742808166=2 > > update the $SUBJECT accordingly, I can do it but you will repost anyway > so please do it yourself while at it. > OK, I will follow the list and check the patch. >> Signed-off-by: Yue Wang >> Signed-off-by: Hanjie Lin >> --- >> drivers/pci/controller/dwc/Kconfig | 12 + >> drivers/pci/controller/dwc/Makefile| 1 + >> drivers/pci/controller/dwc/pci-meson.c | 617 >> + >> 3 files changed, 630 insertions(+) >> create mode 100644 drivers/pci/controller/dwc/pci-meson.c > > I would request a MAINTAINERS update too. > I will update MAINTAINERS in this patch of next-version. >> diff --git a/drivers/pci/controller/dwc/Kconfig >> b/drivers/pci/controller/dwc/Kconfig >> index 91b0194..6cb36f6 100644 >> --- a/drivers/pci/controller/dwc/Kconfig >> +++ b/drivers/pci/controller/dwc/Kconfig >> @@ -193,4 +193,16 @@ config PCIE_HISI_STB >> help >>Say Y here if you want PCIe controller support on HiSilicon STB >> SoCs >> >> +config PCI_MESON >> +bool "MESON PCIe controller" >> +depends on PCI > > This is redundant, remove it. > Yes, really redundant I will remove it. >> +depends on PCI_MSI_IRQ_DOMAIN >> +select PCIEPORTBUS > > There is no real dependency on it, this should be left to kernel > configuration, remove it. > Yes, I will remove it. >> +select PCIE_DW_HOST >> +help >> + Say Y here if you want to enable PCI controller support on Amlogic >> + SoCs. The PCI controller on Amlogic is based on DesignWare hardware >> + and therefore the driver re-uses the DesignWare core functions to >> + implement the driver. >> + >> endmenu >> diff --git a/drivers/pci/controller/dwc/Makefile >> b/drivers/pci/controller/dwc/Makefile >> index 5d2ce72..cf676bd 100644 >> --- a/drivers/pci/controller/dwc/Makefile >> +++ b/drivers/pci/controller/dwc/Makefile >> @@ -14,6 +14,7 @@ obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o >> obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o >> obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o >> obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o >> +obj-$(CONFIG_PCI_MESON) += pci-meson.o >> >> # The following drivers are for devices that use the generic ACPI >> # pci_root.c driver but don't support standard ECAM config access. >> diff --git a/drivers/pci/controller/dwc/pci-meson.c >> b/drivers/pci/controller/dwc/pci-meson.c >> new file mode 100644 >> index 000..9c92a89 >> --- /dev/null >> +++ b/drivers/pci/controller/dwc/pci-meson.c >> @@ -0,0 +1,617 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * PCIe host controller driver for Amlogic MESON SoCs >> + * >> + * Copyright (c) 2018 Amlogic, inc. >> + * Author: Yue Wang >> + */ >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> + >> +#include "pcie-designware.h" >> + >> +#define to_meson_pcie(x) dev_get_drvdata((x)->dev) > > Side note: this macro can be made dwc global since it is the same for all > dwc based host bridges. > Yes, actually this patch refers to the other drivers in dwc directory. >> +/* External local bus interface registers */ >> +#define PLR_OFFSET 0x700 >> +#define PCIE_PORT_LINK_CTRL_OFF (PLR_OFFSET + 0x10) >> +#define FAST_LINK_MODE BIT(7) >> +#define LINK_CAPABLE_MASK GENMASK(21, 16) >> +#define LINK_CAPABLE_X1 BIT(16) >> + >> +#define PCIE_GEN2_CTRL_OFF (PLR_OFFSET + 0x10c) >> +#define NUM_OF_LANES_MASK GENMASK(12, 8) >> +#define NUM_OF_LANES_X1 BIT(8) >> +#define DIRECT_SPEED_CHANGE BIT(17) >> + >> +#define TYPE1_HDR_OFFSET0x0 >> +#define PCIE_STATUS_COMMAND (TYPE1_HDR_OFFSET + 0x04) >> +#define PCI_IO_EN BIT(0) >> +#define PCI_MEM_SPACE_ENBIT(1) >> +#define PCI_BUS_MASTER_EN BIT(2) >> + >> +#define PCIE_BASE_ADD
Re: [RESEND PATCH v3 2/2] PCI: meson: add the Amlogic Meson PCIe controller driver
On 2018/9/21 22:47, Lorenzo Pieralisi wrote: > On Fri, Sep 21, 2018 at 02:03:40PM +0800, Hanjie Lin wrote: >> From: Yue Wang >> >> The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare >> PCI core. This patch adds the driver support for Meson PCIe controller. > > Please read: > > https://marc.info/?l=linux-pci=150905742808166=2 > > update the $SUBJECT accordingly, I can do it but you will repost anyway > so please do it yourself while at it. > OK, I will follow the list and check the patch. >> Signed-off-by: Yue Wang >> Signed-off-by: Hanjie Lin >> --- >> drivers/pci/controller/dwc/Kconfig | 12 + >> drivers/pci/controller/dwc/Makefile| 1 + >> drivers/pci/controller/dwc/pci-meson.c | 617 >> + >> 3 files changed, 630 insertions(+) >> create mode 100644 drivers/pci/controller/dwc/pci-meson.c > > I would request a MAINTAINERS update too. > I will update MAINTAINERS in this patch of next-version. >> diff --git a/drivers/pci/controller/dwc/Kconfig >> b/drivers/pci/controller/dwc/Kconfig >> index 91b0194..6cb36f6 100644 >> --- a/drivers/pci/controller/dwc/Kconfig >> +++ b/drivers/pci/controller/dwc/Kconfig >> @@ -193,4 +193,16 @@ config PCIE_HISI_STB >> help >>Say Y here if you want PCIe controller support on HiSilicon STB >> SoCs >> >> +config PCI_MESON >> +bool "MESON PCIe controller" >> +depends on PCI > > This is redundant, remove it. > Yes, really redundant I will remove it. >> +depends on PCI_MSI_IRQ_DOMAIN >> +select PCIEPORTBUS > > There is no real dependency on it, this should be left to kernel > configuration, remove it. > Yes, I will remove it. >> +select PCIE_DW_HOST >> +help >> + Say Y here if you want to enable PCI controller support on Amlogic >> + SoCs. The PCI controller on Amlogic is based on DesignWare hardware >> + and therefore the driver re-uses the DesignWare core functions to >> + implement the driver. >> + >> endmenu >> diff --git a/drivers/pci/controller/dwc/Makefile >> b/drivers/pci/controller/dwc/Makefile >> index 5d2ce72..cf676bd 100644 >> --- a/drivers/pci/controller/dwc/Makefile >> +++ b/drivers/pci/controller/dwc/Makefile >> @@ -14,6 +14,7 @@ obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o >> obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o >> obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o >> obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o >> +obj-$(CONFIG_PCI_MESON) += pci-meson.o >> >> # The following drivers are for devices that use the generic ACPI >> # pci_root.c driver but don't support standard ECAM config access. >> diff --git a/drivers/pci/controller/dwc/pci-meson.c >> b/drivers/pci/controller/dwc/pci-meson.c >> new file mode 100644 >> index 000..9c92a89 >> --- /dev/null >> +++ b/drivers/pci/controller/dwc/pci-meson.c >> @@ -0,0 +1,617 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * PCIe host controller driver for Amlogic MESON SoCs >> + * >> + * Copyright (c) 2018 Amlogic, inc. >> + * Author: Yue Wang >> + */ >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> + >> +#include "pcie-designware.h" >> + >> +#define to_meson_pcie(x) dev_get_drvdata((x)->dev) > > Side note: this macro can be made dwc global since it is the same for all > dwc based host bridges. > Yes, actually this patch refers to the other drivers in dwc directory. >> +/* External local bus interface registers */ >> +#define PLR_OFFSET 0x700 >> +#define PCIE_PORT_LINK_CTRL_OFF (PLR_OFFSET + 0x10) >> +#define FAST_LINK_MODE BIT(7) >> +#define LINK_CAPABLE_MASK GENMASK(21, 16) >> +#define LINK_CAPABLE_X1 BIT(16) >> + >> +#define PCIE_GEN2_CTRL_OFF (PLR_OFFSET + 0x10c) >> +#define NUM_OF_LANES_MASK GENMASK(12, 8) >> +#define NUM_OF_LANES_X1 BIT(8) >> +#define DIRECT_SPEED_CHANGE BIT(17) >> + >> +#define TYPE1_HDR_OFFSET0x0 >> +#define PCIE_STATUS_COMMAND (TYPE1_HDR_OFFSET + 0x04) >> +#define PCI_IO_EN BIT(0) >> +#define PCI_MEM_SPACE_ENBIT(1) >> +#define PCI_BUS_MASTER_EN BIT(2) >> + >> +#define PCIE_BASE_ADD
[RESEND PATCH v3 1/2] dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller
From: Yue Wang
The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare
PCI core. This patch adds documentation for the DT bindings in Meson PCIe
controller.
Signed-off-by: Yue Wang
Signed-off-by: Hanjie Lin
Reviewed-by: Rob Herring
---
.../devicetree/bindings/pci/amlogic,meson-pcie.txt | 70 ++
1 file changed, 70 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
diff --git a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
new file mode 100644
index 000..12b18f8
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
@@ -0,0 +1,70 @@
+Amlogic Meson AXG DWC PCIE SoC controller
+
+Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI
core.
+It shares common functions with the PCIe DesignWare core driver and
+inherits common properties defined in
+Documentation/devicetree/bindings/pci/designware-pci.txt.
+
+Additional properties are described here:
+
+Required properties:
+- compatible:
+ should contain "amlogic,axg-pcie" to identify the core.
+- reg:
+ should contain the configuration address space.
+- reg-names: Must be
+ - "elbi"External local bus interface registers
+ - "cfg" Meson specific registers
+ - "phy" Meson PCIE PHY registers
+ - "config" PCIe configuration space
+- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
+- clocks: Must contain an entry for each entry in clock-names.
+- clock-names: Must include the following entries:
+ - "pclk" PCIe GEN 100M PLL clock
+ - "port" PCIe_x(A or B) RC clock gate
+ - "general"PCIe Phy clock
+ - "mipi" PCIe_x(A or B) 100M ref clock gate
+- resets: phandle to the reset lines.
+- reset-names: must contain "phy" "port" and "apb"
+ - "phy" Share PHY reset
+ - "port"Port A or B reset
+ - "apb" Share APB reset
+- device_type:
+ should be "pci". As specified in designware-pcie.txt
+
+
+Example configuration:
+
+ pcie: pcie@f980 {
+ compatible = "amlogic,axg-pcie", "snps,dw-pcie";
+ reg = <0x0 0xf980 0x0 0x40
+ 0x0 0xff646000 0x0 0x2000
+ 0x0 0xff644000 0x0 0x2000
+ 0x0 0xf9f0 0x0 0x10>;
+ reg-names = "elbi", "cfg", "phy", "config";
+ reset-gpios = < GPIOX_19 GPIO_ACTIVE_HIGH>;
+ interrupts = ;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 GIC_SPI 179
IRQ_TYPE_EDGE_RISING>;
+ bus-range = <0x0 0xff>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x8200 0 0 0x0 0xf9c0 0 0x0030>;
+
+ clocks = < CLKID_USB
+CLKID_MIPI_ENABLE
+CLKID_PCIE_A
+CLKID_PCIE_CML_EN0>;
+ clock-names = "general",
+ "mipi",
+ "pclk",
+ "port";
+ resets = < RESET_PCIE_PHY>,
+ < RESET_PCIE_A>,
+ < RESET_PCIE_APB>;
+ reset-names = "phy",
+ "port",
+ "apb";
+ };
--
2.7.4
[RESEND PATCH v3 0/2] add the Amlogic Meson PCIe controller driver
This is v3 post RESEND: [2] - add Rob's Reviewed-by to patch 1/2 - add more to list suggested by get_maintainer.pl The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core. This patchset add the driver and dt-bindings of the controller. Till patch v2, we have a dedicated phy driver which only process reset job. It's too overkill so we integrate phy driver into the controller. Changes since v2: [1] - abandon phy driver, move reset to the controller - use devm_add_action_or_reset() to use clock res - format correcting Changes since v1: [0] - use gpio lib instead open code - move 'apb' and 'port' reset from phy driver - format correcting [0] : https://lkml.kernel.org/r/1534227522-186798-1-git-send-email-hanjie@amlogic.com [1] : https://lkml.kernel.org/r/1535096165-45827-1-git-send-email-hanjie@amlogic.com [2] : https://lkml.kernel.org/r/1535616829-167936-1-git-send-email-hanjie@amlogic.com Yue Wang (2): dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller PCI: meson: add the Amlogic Meson PCIe controller driver .../devicetree/bindings/pci/amlogic,meson-pcie.txt | 70 +++ drivers/pci/controller/dwc/Kconfig | 12 + drivers/pci/controller/dwc/Makefile| 1 + drivers/pci/controller/dwc/pci-meson.c | 617 + 4 files changed, 700 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt create mode 100644 drivers/pci/controller/dwc/pci-meson.c -- 2.7.4
[RESEND PATCH v3 1/2] dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller
From: Yue Wang
The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare
PCI core. This patch adds documentation for the DT bindings in Meson PCIe
controller.
Signed-off-by: Yue Wang
Signed-off-by: Hanjie Lin
Reviewed-by: Rob Herring
---
.../devicetree/bindings/pci/amlogic,meson-pcie.txt | 70 ++
1 file changed, 70 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
diff --git a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
new file mode 100644
index 000..12b18f8
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
@@ -0,0 +1,70 @@
+Amlogic Meson AXG DWC PCIE SoC controller
+
+Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI
core.
+It shares common functions with the PCIe DesignWare core driver and
+inherits common properties defined in
+Documentation/devicetree/bindings/pci/designware-pci.txt.
+
+Additional properties are described here:
+
+Required properties:
+- compatible:
+ should contain "amlogic,axg-pcie" to identify the core.
+- reg:
+ should contain the configuration address space.
+- reg-names: Must be
+ - "elbi"External local bus interface registers
+ - "cfg" Meson specific registers
+ - "phy" Meson PCIE PHY registers
+ - "config" PCIe configuration space
+- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
+- clocks: Must contain an entry for each entry in clock-names.
+- clock-names: Must include the following entries:
+ - "pclk" PCIe GEN 100M PLL clock
+ - "port" PCIe_x(A or B) RC clock gate
+ - "general"PCIe Phy clock
+ - "mipi" PCIe_x(A or B) 100M ref clock gate
+- resets: phandle to the reset lines.
+- reset-names: must contain "phy" "port" and "apb"
+ - "phy" Share PHY reset
+ - "port"Port A or B reset
+ - "apb" Share APB reset
+- device_type:
+ should be "pci". As specified in designware-pcie.txt
+
+
+Example configuration:
+
+ pcie: pcie@f980 {
+ compatible = "amlogic,axg-pcie", "snps,dw-pcie";
+ reg = <0x0 0xf980 0x0 0x40
+ 0x0 0xff646000 0x0 0x2000
+ 0x0 0xff644000 0x0 0x2000
+ 0x0 0xf9f0 0x0 0x10>;
+ reg-names = "elbi", "cfg", "phy", "config";
+ reset-gpios = < GPIOX_19 GPIO_ACTIVE_HIGH>;
+ interrupts = ;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 GIC_SPI 179
IRQ_TYPE_EDGE_RISING>;
+ bus-range = <0x0 0xff>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x8200 0 0 0x0 0xf9c0 0 0x0030>;
+
+ clocks = < CLKID_USB
+CLKID_MIPI_ENABLE
+CLKID_PCIE_A
+CLKID_PCIE_CML_EN0>;
+ clock-names = "general",
+ "mipi",
+ "pclk",
+ "port";
+ resets = < RESET_PCIE_PHY>,
+ < RESET_PCIE_A>,
+ < RESET_PCIE_APB>;
+ reset-names = "phy",
+ "port",
+ "apb";
+ };
--
2.7.4
[RESEND PATCH v3 0/2] add the Amlogic Meson PCIe controller driver
This is v3 post RESEND: [2] - add Rob's Reviewed-by to patch 1/2 - add more to list suggested by get_maintainer.pl The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core. This patchset add the driver and dt-bindings of the controller. Till patch v2, we have a dedicated phy driver which only process reset job. It's too overkill so we integrate phy driver into the controller. Changes since v2: [1] - abandon phy driver, move reset to the controller - use devm_add_action_or_reset() to use clock res - format correcting Changes since v1: [0] - use gpio lib instead open code - move 'apb' and 'port' reset from phy driver - format correcting [0] : https://lkml.kernel.org/r/1534227522-186798-1-git-send-email-hanjie@amlogic.com [1] : https://lkml.kernel.org/r/1535096165-45827-1-git-send-email-hanjie@amlogic.com [2] : https://lkml.kernel.org/r/1535616829-167936-1-git-send-email-hanjie@amlogic.com Yue Wang (2): dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller PCI: meson: add the Amlogic Meson PCIe controller driver .../devicetree/bindings/pci/amlogic,meson-pcie.txt | 70 +++ drivers/pci/controller/dwc/Kconfig | 12 + drivers/pci/controller/dwc/Makefile| 1 + drivers/pci/controller/dwc/pci-meson.c | 617 + 4 files changed, 700 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt create mode 100644 drivers/pci/controller/dwc/pci-meson.c -- 2.7.4
[RESEND PATCH v3 2/2] PCI: meson: add the Amlogic Meson PCIe controller driver
From: Yue Wang
The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare
PCI core. This patch adds the driver support for Meson PCIe controller.
Signed-off-by: Yue Wang
Signed-off-by: Hanjie Lin
---
drivers/pci/controller/dwc/Kconfig | 12 +
drivers/pci/controller/dwc/Makefile| 1 +
drivers/pci/controller/dwc/pci-meson.c | 617 +
3 files changed, 630 insertions(+)
create mode 100644 drivers/pci/controller/dwc/pci-meson.c
diff --git a/drivers/pci/controller/dwc/Kconfig
b/drivers/pci/controller/dwc/Kconfig
index 91b0194..6cb36f6 100644
--- a/drivers/pci/controller/dwc/Kconfig
+++ b/drivers/pci/controller/dwc/Kconfig
@@ -193,4 +193,16 @@ config PCIE_HISI_STB
help
Say Y here if you want PCIe controller support on HiSilicon STB SoCs
+config PCI_MESON
+ bool "MESON PCIe controller"
+ depends on PCI
+ depends on PCI_MSI_IRQ_DOMAIN
+ select PCIEPORTBUS
+ select PCIE_DW_HOST
+ help
+ Say Y here if you want to enable PCI controller support on Amlogic
+ SoCs. The PCI controller on Amlogic is based on DesignWare hardware
+ and therefore the driver re-uses the DesignWare core functions to
+ implement the driver.
+
endmenu
diff --git a/drivers/pci/controller/dwc/Makefile
b/drivers/pci/controller/dwc/Makefile
index 5d2ce72..cf676bd 100644
--- a/drivers/pci/controller/dwc/Makefile
+++ b/drivers/pci/controller/dwc/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o
obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o
+obj-$(CONFIG_PCI_MESON) += pci-meson.o
# The following drivers are for devices that use the generic ACPI
# pci_root.c driver but don't support standard ECAM config access.
diff --git a/drivers/pci/controller/dwc/pci-meson.c
b/drivers/pci/controller/dwc/pci-meson.c
new file mode 100644
index 000..9c92a89
--- /dev/null
+++ b/drivers/pci/controller/dwc/pci-meson.c
@@ -0,0 +1,617 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PCIe host controller driver for Amlogic MESON SoCs
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Yue Wang
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "pcie-designware.h"
+
+#define to_meson_pcie(x) dev_get_drvdata((x)->dev)
+
+/* External local bus interface registers */
+#define PLR_OFFSET 0x700
+#define PCIE_PORT_LINK_CTRL_OFF(PLR_OFFSET + 0x10)
+#define FAST_LINK_MODE BIT(7)
+#define LINK_CAPABLE_MASK GENMASK(21, 16)
+#define LINK_CAPABLE_X1BIT(16)
+
+#define PCIE_GEN2_CTRL_OFF (PLR_OFFSET + 0x10c)
+#define NUM_OF_LANES_MASK GENMASK(12, 8)
+#define NUM_OF_LANES_X1BIT(8)
+#define DIRECT_SPEED_CHANGEBIT(17)
+
+#define TYPE1_HDR_OFFSET 0x0
+#define PCIE_STATUS_COMMAND(TYPE1_HDR_OFFSET + 0x04)
+#define PCI_IO_EN BIT(0)
+#define PCI_MEM_SPACE_EN BIT(1)
+#define PCI_BUS_MASTER_EN BIT(2)
+
+#define PCIE_BASE_ADDR0(TYPE1_HDR_OFFSET + 0x10)
+#define PCIE_BASE_ADDR1(TYPE1_HDR_OFFSET + 0x14)
+
+#define PCIE_CAP_OFFSET0x70
+#define PCIE_DEV_CTRL_DEV_STUS (PCIE_CAP_OFFSET + 0x08)
+#define PCIE_CAP_MAX_PAYLOAD_MASK GENMASK(7, 5)
+#define PCIE_CAP_MAX_PAYLOAD_SIZE(x) ((x) << 5)
+#define PCIE_CAP_MAX_READ_REQ_MASK GENMASK(14, 12)
+#define PCIE_CAP_MAX_READ_REQ_SIZE(x) ((x) << 12)
+
+#define PCI_CLASS_REVISION_MASKGENMASK(7, 0)
+
+/* PCIe specific config registers */
+#define PCIE_CFG0 0x0
+#define APP_LTSSM_ENABLE BIT(7)
+
+#define PCIE_CFG_STATUS12 0x30
+#define IS_SMLH_LINK_UP(x) ((x) & (1 << 6))
+#define IS_RDLH_LINK_UP(x) ((x) & (1 << 16))
+#define IS_LTSSM_UP(x) x) >> 10) & 0x1f) == 0x11)
+
+#define PCIE_CFG_STATUS17 0x44
+#define PM_CURRENT_STATE(x)(((x) >> 7) & 0x1)
+
+#define WAIT_LINKUP_TIMEOUT2000
+#define PORT_CLK_RATE 1UL
+#define MAX_PAYLOAD_SIZE 256
+#define MAX_READ_REQ_SIZE 256
+#define MESON_PCIE_PHY_POWERUP 0x1c
+#define PCIE_RESET_DELAY 500
+#define PCIE_SHARED_RESET 1
+#define PCIE_NORMAL_RESET 0
+
+enum pcie_data_rate {
+ PCIE_GEN1,
+ PCIE_GEN2,
+ PCIE_GEN3,
+ PCIE_GEN4
+};
+
+struct meson_pcie_mem_res {
+ void __iomem *elbi_base; /* DT 0th resource */
+ void __iomem *cfg_base; /* DT 1nd resource */
+ void __iomem *phy_base; /* DT 2nd resource */
+};
+
+struct
[RESEND PATCH v3 2/2] PCI: meson: add the Amlogic Meson PCIe controller driver
From: Yue Wang
The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare
PCI core. This patch adds the driver support for Meson PCIe controller.
Signed-off-by: Yue Wang
Signed-off-by: Hanjie Lin
---
drivers/pci/controller/dwc/Kconfig | 12 +
drivers/pci/controller/dwc/Makefile| 1 +
drivers/pci/controller/dwc/pci-meson.c | 617 +
3 files changed, 630 insertions(+)
create mode 100644 drivers/pci/controller/dwc/pci-meson.c
diff --git a/drivers/pci/controller/dwc/Kconfig
b/drivers/pci/controller/dwc/Kconfig
index 91b0194..6cb36f6 100644
--- a/drivers/pci/controller/dwc/Kconfig
+++ b/drivers/pci/controller/dwc/Kconfig
@@ -193,4 +193,16 @@ config PCIE_HISI_STB
help
Say Y here if you want PCIe controller support on HiSilicon STB SoCs
+config PCI_MESON
+ bool "MESON PCIe controller"
+ depends on PCI
+ depends on PCI_MSI_IRQ_DOMAIN
+ select PCIEPORTBUS
+ select PCIE_DW_HOST
+ help
+ Say Y here if you want to enable PCI controller support on Amlogic
+ SoCs. The PCI controller on Amlogic is based on DesignWare hardware
+ and therefore the driver re-uses the DesignWare core functions to
+ implement the driver.
+
endmenu
diff --git a/drivers/pci/controller/dwc/Makefile
b/drivers/pci/controller/dwc/Makefile
index 5d2ce72..cf676bd 100644
--- a/drivers/pci/controller/dwc/Makefile
+++ b/drivers/pci/controller/dwc/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o
obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o
+obj-$(CONFIG_PCI_MESON) += pci-meson.o
# The following drivers are for devices that use the generic ACPI
# pci_root.c driver but don't support standard ECAM config access.
diff --git a/drivers/pci/controller/dwc/pci-meson.c
b/drivers/pci/controller/dwc/pci-meson.c
new file mode 100644
index 000..9c92a89
--- /dev/null
+++ b/drivers/pci/controller/dwc/pci-meson.c
@@ -0,0 +1,617 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PCIe host controller driver for Amlogic MESON SoCs
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Yue Wang
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "pcie-designware.h"
+
+#define to_meson_pcie(x) dev_get_drvdata((x)->dev)
+
+/* External local bus interface registers */
+#define PLR_OFFSET 0x700
+#define PCIE_PORT_LINK_CTRL_OFF(PLR_OFFSET + 0x10)
+#define FAST_LINK_MODE BIT(7)
+#define LINK_CAPABLE_MASK GENMASK(21, 16)
+#define LINK_CAPABLE_X1BIT(16)
+
+#define PCIE_GEN2_CTRL_OFF (PLR_OFFSET + 0x10c)
+#define NUM_OF_LANES_MASK GENMASK(12, 8)
+#define NUM_OF_LANES_X1BIT(8)
+#define DIRECT_SPEED_CHANGEBIT(17)
+
+#define TYPE1_HDR_OFFSET 0x0
+#define PCIE_STATUS_COMMAND(TYPE1_HDR_OFFSET + 0x04)
+#define PCI_IO_EN BIT(0)
+#define PCI_MEM_SPACE_EN BIT(1)
+#define PCI_BUS_MASTER_EN BIT(2)
+
+#define PCIE_BASE_ADDR0(TYPE1_HDR_OFFSET + 0x10)
+#define PCIE_BASE_ADDR1(TYPE1_HDR_OFFSET + 0x14)
+
+#define PCIE_CAP_OFFSET0x70
+#define PCIE_DEV_CTRL_DEV_STUS (PCIE_CAP_OFFSET + 0x08)
+#define PCIE_CAP_MAX_PAYLOAD_MASK GENMASK(7, 5)
+#define PCIE_CAP_MAX_PAYLOAD_SIZE(x) ((x) << 5)
+#define PCIE_CAP_MAX_READ_REQ_MASK GENMASK(14, 12)
+#define PCIE_CAP_MAX_READ_REQ_SIZE(x) ((x) << 12)
+
+#define PCI_CLASS_REVISION_MASKGENMASK(7, 0)
+
+/* PCIe specific config registers */
+#define PCIE_CFG0 0x0
+#define APP_LTSSM_ENABLE BIT(7)
+
+#define PCIE_CFG_STATUS12 0x30
+#define IS_SMLH_LINK_UP(x) ((x) & (1 << 6))
+#define IS_RDLH_LINK_UP(x) ((x) & (1 << 16))
+#define IS_LTSSM_UP(x) x) >> 10) & 0x1f) == 0x11)
+
+#define PCIE_CFG_STATUS17 0x44
+#define PM_CURRENT_STATE(x)(((x) >> 7) & 0x1)
+
+#define WAIT_LINKUP_TIMEOUT2000
+#define PORT_CLK_RATE 1UL
+#define MAX_PAYLOAD_SIZE 256
+#define MAX_READ_REQ_SIZE 256
+#define MESON_PCIE_PHY_POWERUP 0x1c
+#define PCIE_RESET_DELAY 500
+#define PCIE_SHARED_RESET 1
+#define PCIE_NORMAL_RESET 0
+
+enum pcie_data_rate {
+ PCIE_GEN1,
+ PCIE_GEN2,
+ PCIE_GEN3,
+ PCIE_GEN4
+};
+
+struct meson_pcie_mem_res {
+ void __iomem *elbi_base; /* DT 0th resource */
+ void __iomem *cfg_base; /* DT 1nd resource */
+ void __iomem *phy_base; /* DT 2nd resource */
+};
+
+struct
Re: [PATCH v2 1/2] dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller
On 2018/8/30 21:59, Rob Herring wrote: > On Thu, Aug 30, 2018 at 2:37 AM Hanjie Lin wrote: >> >> >> >> On 2018/8/29 8:41, Rob Herring wrote: >>> On Mon, Aug 27, 2018 at 04:55:20PM +0800, Hanjie Lin wrote: >>>> >>>> >>>> On 2018/8/24 16:22, Jerome Brunet wrote: >>>>> On Fri, 2018-08-24 at 15:36 +0800, Hanjie Lin wrote: >>>>>> From: Yue Wang >>>>>> >>>>>> The Amlogic Meson PCIe host controller is based on the Synopsys >>>>>> DesignWare >>>>>> PCI core. This patch adds documentation for the DT bindings in Meson PCIe >>>>>> controller. >>>>>> >>>>>> Signed-off-by: Yue Wang >>>>>> Signed-off-by: Hanjie Lin >>>>>> --- >>>>>> .../devicetree/bindings/pci/amlogic,meson-pcie.txt | 63 >>>>>> ++ >>>>>> 1 file changed, 63 insertions(+) >>>>>> create mode 100644 >>>>>> Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt >>>>>> >>>>>> diff --git >>>>>> a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt >>>>>> b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt >>>>>> new file mode 100644 >>>>>> index 000..8a831d1 >>>>>> --- /dev/null >>>>>> +++ b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt >>>>>> @@ -0,0 +1,63 @@ >>>>>> +Amlogic Meson AXG DWC PCIE SoC controller >>>>>> + >>>>>> +Amlogic Meson PCIe host controller is based on the Synopsys DesignWare >>>>>> PCI core. >>>>>> +It shares common functions with the PCIe DesignWare core driver and >>>>>> +inherits common properties defined in >>>>>> +Documentation/devicetree/bindings/pci/designware-pci.txt. >>>>>> + >>>>>> +Additional properties are described here: >>>>>> + >>>>>> +Required properties: >>>>>> +- compatible: >>>>>> + should contain "amlogic,axg-pcie" to identify the core. >>>>>> +- reg: >>>>>> + Should contain the configuration address space. >>>>>> +- reg-names: Must be >>>>>> + - "elbi"External local bus interface registers >>>>>> + - "cfg" Meson specific registers >>>>>> + - "config" PCIe configuration space >>>>>> +- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert >>>>>> signal. >>>>>> +- clocks: Must contain an entry for each entry in clock-names. >>>>>> +- clock-names: Must include the following entries: >>>>>> + - "pclk" PCIe GEN 100M PLL clock >>>>>> + - "port" PCIe_x(A or B) RC clock gate >>>>>> + - "general"PCIe Phy clock >>>>>> + - "mipi" PCIe_x(A or B) 100M ref clock gate >>>>>> +- resets: phandle to the reset lines. >>>>>> +- reset-names: must contain "phy" and "peripheral" >>>>>> + - "port" Port A or B reset >>>>>> + - "apb" APB reset >>>>> >>>>> The above description is not coherent (phy <=> port) >>>>> >>>> >>>> Yes, this should be port and apb here. >>>> We'll integrate phy driver into ctrl driver, and move phy reset to here >>>> also. >>> >>> Why? That's the wrong thing to do if they are separate h/w blocks. You >>> can do whatever you like in the drivers, but the DT should reflect the >>> h/w. >>> >>> Rob >>> >>> . >>> >> >> We have the dedicated phy driver which only process reset job, >> and we consider that it's too overkill to do just these things . >> So we will integrate phy reset job into the controller driver int the next >> version. > > What's in the separate register space you had for the phy? > > Rob > > . > As described with 'phy' reg in ctrl patch v3 thread [0] - reg-names: Must be - "elbi"External local bus interface registers - "cfg" Meson specific registers - "phy" Meson PCIE PHY registers - "config" PCIe configuration space When each controller driver probe, we powerup phy by write phy register like below: writel(MESON_PCIE_PHY_POWERUP, mp->mem_res.phy_base); [0] https://lkml.kernel.org/r/1535616829-167936-1-git-send-email-hanjie@amlogic.com
Re: [PATCH v2 1/2] dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller
On 2018/8/30 21:59, Rob Herring wrote: > On Thu, Aug 30, 2018 at 2:37 AM Hanjie Lin wrote: >> >> >> >> On 2018/8/29 8:41, Rob Herring wrote: >>> On Mon, Aug 27, 2018 at 04:55:20PM +0800, Hanjie Lin wrote: >>>> >>>> >>>> On 2018/8/24 16:22, Jerome Brunet wrote: >>>>> On Fri, 2018-08-24 at 15:36 +0800, Hanjie Lin wrote: >>>>>> From: Yue Wang >>>>>> >>>>>> The Amlogic Meson PCIe host controller is based on the Synopsys >>>>>> DesignWare >>>>>> PCI core. This patch adds documentation for the DT bindings in Meson PCIe >>>>>> controller. >>>>>> >>>>>> Signed-off-by: Yue Wang >>>>>> Signed-off-by: Hanjie Lin >>>>>> --- >>>>>> .../devicetree/bindings/pci/amlogic,meson-pcie.txt | 63 >>>>>> ++ >>>>>> 1 file changed, 63 insertions(+) >>>>>> create mode 100644 >>>>>> Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt >>>>>> >>>>>> diff --git >>>>>> a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt >>>>>> b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt >>>>>> new file mode 100644 >>>>>> index 000..8a831d1 >>>>>> --- /dev/null >>>>>> +++ b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt >>>>>> @@ -0,0 +1,63 @@ >>>>>> +Amlogic Meson AXG DWC PCIE SoC controller >>>>>> + >>>>>> +Amlogic Meson PCIe host controller is based on the Synopsys DesignWare >>>>>> PCI core. >>>>>> +It shares common functions with the PCIe DesignWare core driver and >>>>>> +inherits common properties defined in >>>>>> +Documentation/devicetree/bindings/pci/designware-pci.txt. >>>>>> + >>>>>> +Additional properties are described here: >>>>>> + >>>>>> +Required properties: >>>>>> +- compatible: >>>>>> + should contain "amlogic,axg-pcie" to identify the core. >>>>>> +- reg: >>>>>> + Should contain the configuration address space. >>>>>> +- reg-names: Must be >>>>>> + - "elbi"External local bus interface registers >>>>>> + - "cfg" Meson specific registers >>>>>> + - "config" PCIe configuration space >>>>>> +- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert >>>>>> signal. >>>>>> +- clocks: Must contain an entry for each entry in clock-names. >>>>>> +- clock-names: Must include the following entries: >>>>>> + - "pclk" PCIe GEN 100M PLL clock >>>>>> + - "port" PCIe_x(A or B) RC clock gate >>>>>> + - "general"PCIe Phy clock >>>>>> + - "mipi" PCIe_x(A or B) 100M ref clock gate >>>>>> +- resets: phandle to the reset lines. >>>>>> +- reset-names: must contain "phy" and "peripheral" >>>>>> + - "port" Port A or B reset >>>>>> + - "apb" APB reset >>>>> >>>>> The above description is not coherent (phy <=> port) >>>>> >>>> >>>> Yes, this should be port and apb here. >>>> We'll integrate phy driver into ctrl driver, and move phy reset to here >>>> also. >>> >>> Why? That's the wrong thing to do if they are separate h/w blocks. You >>> can do whatever you like in the drivers, but the DT should reflect the >>> h/w. >>> >>> Rob >>> >>> . >>> >> >> We have the dedicated phy driver which only process reset job, >> and we consider that it's too overkill to do just these things . >> So we will integrate phy reset job into the controller driver int the next >> version. > > What's in the separate register space you had for the phy? > > Rob > > . > As described with 'phy' reg in ctrl patch v3 thread [0] - reg-names: Must be - "elbi"External local bus interface registers - "cfg" Meson specific registers - "phy" Meson PCIE PHY registers - "config" PCIe configuration space When each controller driver probe, we powerup phy by write phy register like below: writel(MESON_PCIE_PHY_POWERUP, mp->mem_res.phy_base); [0] https://lkml.kernel.org/r/1535616829-167936-1-git-send-email-hanjie@amlogic.com
[PATCH v3 1/2] dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller
From: Yue Wang
The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare
PCI core. This patch adds documentation for the DT bindings in Meson PCIe
controller.
Signed-off-by: Yue Wang
Signed-off-by: Hanjie Lin
---
.../devicetree/bindings/pci/amlogic,meson-pcie.txt | 70 ++
1 file changed, 70 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
diff --git a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
new file mode 100644
index 000..12b18f8
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
@@ -0,0 +1,70 @@
+Amlogic Meson AXG DWC PCIE SoC controller
+
+Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI
core.
+It shares common functions with the PCIe DesignWare core driver and
+inherits common properties defined in
+Documentation/devicetree/bindings/pci/designware-pci.txt.
+
+Additional properties are described here:
+
+Required properties:
+- compatible:
+ should contain "amlogic,axg-pcie" to identify the core.
+- reg:
+ should contain the configuration address space.
+- reg-names: Must be
+ - "elbi"External local bus interface registers
+ - "cfg" Meson specific registers
+ - "phy" Meson PCIE PHY registers
+ - "config" PCIe configuration space
+- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
+- clocks: Must contain an entry for each entry in clock-names.
+- clock-names: Must include the following entries:
+ - "pclk" PCIe GEN 100M PLL clock
+ - "port" PCIe_x(A or B) RC clock gate
+ - "general"PCIe Phy clock
+ - "mipi" PCIe_x(A or B) 100M ref clock gate
+- resets: phandle to the reset lines.
+- reset-names: must contain "phy" "port" and "apb"
+ - "phy" Share PHY reset
+ - "port"Port A or B reset
+ - "apb" Share APB reset
+- device_type:
+ should be "pci". As specified in designware-pcie.txt
+
+
+Example configuration:
+
+ pcie: pcie@f980 {
+ compatible = "amlogic,axg-pcie", "snps,dw-pcie";
+ reg = <0x0 0xf980 0x0 0x40
+ 0x0 0xff646000 0x0 0x2000
+ 0x0 0xff644000 0x0 0x2000
+ 0x0 0xf9f0 0x0 0x10>;
+ reg-names = "elbi", "cfg", "phy", "config";
+ reset-gpios = < GPIOX_19 GPIO_ACTIVE_HIGH>;
+ interrupts = ;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 GIC_SPI 179
IRQ_TYPE_EDGE_RISING>;
+ bus-range = <0x0 0xff>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x8200 0 0 0x0 0xf9c0 0 0x0030>;
+
+ clocks = < CLKID_USB
+CLKID_MIPI_ENABLE
+CLKID_PCIE_A
+CLKID_PCIE_CML_EN0>;
+ clock-names = "general",
+ "mipi",
+ "pclk",
+ "port";
+ resets = < RESET_PCIE_PHY>,
+ < RESET_PCIE_A>,
+ < RESET_PCIE_APB>;
+ reset-names = "phy",
+ "port",
+ "apb";
+ };
--
2.7.4
[PATCH v3 2/2] PCI: meson: add the Amlogic Meson PCIe controller driver
From: Yue Wang
The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare
PCI core. This patch adds the driver support for Meson PCIe controller.
Signed-off-by: Yue Wang
Signed-off-by: Hanjie Lin
---
drivers/pci/controller/dwc/Kconfig | 12 +
drivers/pci/controller/dwc/Makefile| 1 +
drivers/pci/controller/dwc/pci-meson.c | 617 +
3 files changed, 630 insertions(+)
create mode 100644 drivers/pci/controller/dwc/pci-meson.c
diff --git a/drivers/pci/controller/dwc/Kconfig
b/drivers/pci/controller/dwc/Kconfig
index 91b0194..6cb36f6 100644
--- a/drivers/pci/controller/dwc/Kconfig
+++ b/drivers/pci/controller/dwc/Kconfig
@@ -193,4 +193,16 @@ config PCIE_HISI_STB
help
Say Y here if you want PCIe controller support on HiSilicon STB SoCs
+config PCI_MESON
+ bool "MESON PCIe controller"
+ depends on PCI
+ depends on PCI_MSI_IRQ_DOMAIN
+ select PCIEPORTBUS
+ select PCIE_DW_HOST
+ help
+ Say Y here if you want to enable PCI controller support on Amlogic
+ SoCs. The PCI controller on Amlogic is based on DesignWare hardware
+ and therefore the driver re-uses the DesignWare core functions to
+ implement the driver.
+
endmenu
diff --git a/drivers/pci/controller/dwc/Makefile
b/drivers/pci/controller/dwc/Makefile
index 5d2ce72..cf676bd 100644
--- a/drivers/pci/controller/dwc/Makefile
+++ b/drivers/pci/controller/dwc/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o
obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o
+obj-$(CONFIG_PCI_MESON) += pci-meson.o
# The following drivers are for devices that use the generic ACPI
# pci_root.c driver but don't support standard ECAM config access.
diff --git a/drivers/pci/controller/dwc/pci-meson.c
b/drivers/pci/controller/dwc/pci-meson.c
new file mode 100644
index 000..9c92a89
--- /dev/null
+++ b/drivers/pci/controller/dwc/pci-meson.c
@@ -0,0 +1,617 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PCIe host controller driver for Amlogic MESON SoCs
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Yue Wang
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "pcie-designware.h"
+
+#define to_meson_pcie(x) dev_get_drvdata((x)->dev)
+
+/* External local bus interface registers */
+#define PLR_OFFSET 0x700
+#define PCIE_PORT_LINK_CTRL_OFF(PLR_OFFSET + 0x10)
+#define FAST_LINK_MODE BIT(7)
+#define LINK_CAPABLE_MASK GENMASK(21, 16)
+#define LINK_CAPABLE_X1BIT(16)
+
+#define PCIE_GEN2_CTRL_OFF (PLR_OFFSET + 0x10c)
+#define NUM_OF_LANES_MASK GENMASK(12, 8)
+#define NUM_OF_LANES_X1BIT(8)
+#define DIRECT_SPEED_CHANGEBIT(17)
+
+#define TYPE1_HDR_OFFSET 0x0
+#define PCIE_STATUS_COMMAND(TYPE1_HDR_OFFSET + 0x04)
+#define PCI_IO_EN BIT(0)
+#define PCI_MEM_SPACE_EN BIT(1)
+#define PCI_BUS_MASTER_EN BIT(2)
+
+#define PCIE_BASE_ADDR0(TYPE1_HDR_OFFSET + 0x10)
+#define PCIE_BASE_ADDR1(TYPE1_HDR_OFFSET + 0x14)
+
+#define PCIE_CAP_OFFSET0x70
+#define PCIE_DEV_CTRL_DEV_STUS (PCIE_CAP_OFFSET + 0x08)
+#define PCIE_CAP_MAX_PAYLOAD_MASK GENMASK(7, 5)
+#define PCIE_CAP_MAX_PAYLOAD_SIZE(x) ((x) << 5)
+#define PCIE_CAP_MAX_READ_REQ_MASK GENMASK(14, 12)
+#define PCIE_CAP_MAX_READ_REQ_SIZE(x) ((x) << 12)
+
+#define PCI_CLASS_REVISION_MASKGENMASK(7, 0)
+
+/* PCIe specific config registers */
+#define PCIE_CFG0 0x0
+#define APP_LTSSM_ENABLE BIT(7)
+
+#define PCIE_CFG_STATUS12 0x30
+#define IS_SMLH_LINK_UP(x) ((x) & (1 << 6))
+#define IS_RDLH_LINK_UP(x) ((x) & (1 << 16))
+#define IS_LTSSM_UP(x) x) >> 10) & 0x1f) == 0x11)
+
+#define PCIE_CFG_STATUS17 0x44
+#define PM_CURRENT_STATE(x)(((x) >> 7) & 0x1)
+
+#define WAIT_LINKUP_TIMEOUT2000
+#define PORT_CLK_RATE 1UL
+#define MAX_PAYLOAD_SIZE 256
+#define MAX_READ_REQ_SIZE 256
+#define MESON_PCIE_PHY_POWERUP 0x1c
+#define PCIE_RESET_DELAY 500
+#define PCIE_SHARED_RESET 1
+#define PCIE_NORMAL_RESET 0
+
+enum pcie_data_rate {
+ PCIE_GEN1,
+ PCIE_GEN2,
+ PCIE_GEN3,
+ PCIE_GEN4
+};
+
+struct meson_pcie_mem_res {
+ void __iomem *elbi_base; /* DT 0th resource */
+ void __iomem *cfg_base; /* DT 1nd resource */
+ void __iomem *phy_base; /* DT 2nd resource */
+};
+
+struct
[PATCH v3 0/2] add the Amlogic Meson PCIe controller driver
The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core. This patchset add the driver and dt-bindings of the controller. Till patch v2, we have a dedicated phy driver which only process reset job. It's too overkill so we integrate phy driver into the controller. Changes since v2: [1] - abandon phy driver, move reset to the controller - use devm_add_action_or_reset() to use clock res - format correcting Changes since v1: [0] - use gpio lib instead open code - move 'apb' and 'port' reset from phy driver - format correcting [0] : https://lkml.kernel.org/r/1534227522-186798-1-git-send-email-hanjie@amlogic.com [1] : https://lkml.kernel.org/r/1535096165-45827-1-git-send-email-hanjie@amlogic.com Yue Wang (2): dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller PCI: meson: add the Amlogic Meson PCIe controller driver .../devicetree/bindings/pci/amlogic,meson-pcie.txt | 70 +++ drivers/pci/controller/dwc/Kconfig | 12 + drivers/pci/controller/dwc/Makefile| 1 + drivers/pci/controller/dwc/pci-meson.c | 617 + 4 files changed, 700 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt create mode 100644 drivers/pci/controller/dwc/pci-meson.c -- 2.7.4
[PATCH v3 1/2] dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller
From: Yue Wang
The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare
PCI core. This patch adds documentation for the DT bindings in Meson PCIe
controller.
Signed-off-by: Yue Wang
Signed-off-by: Hanjie Lin
---
.../devicetree/bindings/pci/amlogic,meson-pcie.txt | 70 ++
1 file changed, 70 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
diff --git a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
new file mode 100644
index 000..12b18f8
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
@@ -0,0 +1,70 @@
+Amlogic Meson AXG DWC PCIE SoC controller
+
+Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI
core.
+It shares common functions with the PCIe DesignWare core driver and
+inherits common properties defined in
+Documentation/devicetree/bindings/pci/designware-pci.txt.
+
+Additional properties are described here:
+
+Required properties:
+- compatible:
+ should contain "amlogic,axg-pcie" to identify the core.
+- reg:
+ should contain the configuration address space.
+- reg-names: Must be
+ - "elbi"External local bus interface registers
+ - "cfg" Meson specific registers
+ - "phy" Meson PCIE PHY registers
+ - "config" PCIe configuration space
+- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
+- clocks: Must contain an entry for each entry in clock-names.
+- clock-names: Must include the following entries:
+ - "pclk" PCIe GEN 100M PLL clock
+ - "port" PCIe_x(A or B) RC clock gate
+ - "general"PCIe Phy clock
+ - "mipi" PCIe_x(A or B) 100M ref clock gate
+- resets: phandle to the reset lines.
+- reset-names: must contain "phy" "port" and "apb"
+ - "phy" Share PHY reset
+ - "port"Port A or B reset
+ - "apb" Share APB reset
+- device_type:
+ should be "pci". As specified in designware-pcie.txt
+
+
+Example configuration:
+
+ pcie: pcie@f980 {
+ compatible = "amlogic,axg-pcie", "snps,dw-pcie";
+ reg = <0x0 0xf980 0x0 0x40
+ 0x0 0xff646000 0x0 0x2000
+ 0x0 0xff644000 0x0 0x2000
+ 0x0 0xf9f0 0x0 0x10>;
+ reg-names = "elbi", "cfg", "phy", "config";
+ reset-gpios = < GPIOX_19 GPIO_ACTIVE_HIGH>;
+ interrupts = ;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 GIC_SPI 179
IRQ_TYPE_EDGE_RISING>;
+ bus-range = <0x0 0xff>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x8200 0 0 0x0 0xf9c0 0 0x0030>;
+
+ clocks = < CLKID_USB
+CLKID_MIPI_ENABLE
+CLKID_PCIE_A
+CLKID_PCIE_CML_EN0>;
+ clock-names = "general",
+ "mipi",
+ "pclk",
+ "port";
+ resets = < RESET_PCIE_PHY>,
+ < RESET_PCIE_A>,
+ < RESET_PCIE_APB>;
+ reset-names = "phy",
+ "port",
+ "apb";
+ };
--
2.7.4
[PATCH v3 2/2] PCI: meson: add the Amlogic Meson PCIe controller driver
From: Yue Wang
The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare
PCI core. This patch adds the driver support for Meson PCIe controller.
Signed-off-by: Yue Wang
Signed-off-by: Hanjie Lin
---
drivers/pci/controller/dwc/Kconfig | 12 +
drivers/pci/controller/dwc/Makefile| 1 +
drivers/pci/controller/dwc/pci-meson.c | 617 +
3 files changed, 630 insertions(+)
create mode 100644 drivers/pci/controller/dwc/pci-meson.c
diff --git a/drivers/pci/controller/dwc/Kconfig
b/drivers/pci/controller/dwc/Kconfig
index 91b0194..6cb36f6 100644
--- a/drivers/pci/controller/dwc/Kconfig
+++ b/drivers/pci/controller/dwc/Kconfig
@@ -193,4 +193,16 @@ config PCIE_HISI_STB
help
Say Y here if you want PCIe controller support on HiSilicon STB SoCs
+config PCI_MESON
+ bool "MESON PCIe controller"
+ depends on PCI
+ depends on PCI_MSI_IRQ_DOMAIN
+ select PCIEPORTBUS
+ select PCIE_DW_HOST
+ help
+ Say Y here if you want to enable PCI controller support on Amlogic
+ SoCs. The PCI controller on Amlogic is based on DesignWare hardware
+ and therefore the driver re-uses the DesignWare core functions to
+ implement the driver.
+
endmenu
diff --git a/drivers/pci/controller/dwc/Makefile
b/drivers/pci/controller/dwc/Makefile
index 5d2ce72..cf676bd 100644
--- a/drivers/pci/controller/dwc/Makefile
+++ b/drivers/pci/controller/dwc/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o
obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o
+obj-$(CONFIG_PCI_MESON) += pci-meson.o
# The following drivers are for devices that use the generic ACPI
# pci_root.c driver but don't support standard ECAM config access.
diff --git a/drivers/pci/controller/dwc/pci-meson.c
b/drivers/pci/controller/dwc/pci-meson.c
new file mode 100644
index 000..9c92a89
--- /dev/null
+++ b/drivers/pci/controller/dwc/pci-meson.c
@@ -0,0 +1,617 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PCIe host controller driver for Amlogic MESON SoCs
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Yue Wang
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "pcie-designware.h"
+
+#define to_meson_pcie(x) dev_get_drvdata((x)->dev)
+
+/* External local bus interface registers */
+#define PLR_OFFSET 0x700
+#define PCIE_PORT_LINK_CTRL_OFF(PLR_OFFSET + 0x10)
+#define FAST_LINK_MODE BIT(7)
+#define LINK_CAPABLE_MASK GENMASK(21, 16)
+#define LINK_CAPABLE_X1BIT(16)
+
+#define PCIE_GEN2_CTRL_OFF (PLR_OFFSET + 0x10c)
+#define NUM_OF_LANES_MASK GENMASK(12, 8)
+#define NUM_OF_LANES_X1BIT(8)
+#define DIRECT_SPEED_CHANGEBIT(17)
+
+#define TYPE1_HDR_OFFSET 0x0
+#define PCIE_STATUS_COMMAND(TYPE1_HDR_OFFSET + 0x04)
+#define PCI_IO_EN BIT(0)
+#define PCI_MEM_SPACE_EN BIT(1)
+#define PCI_BUS_MASTER_EN BIT(2)
+
+#define PCIE_BASE_ADDR0(TYPE1_HDR_OFFSET + 0x10)
+#define PCIE_BASE_ADDR1(TYPE1_HDR_OFFSET + 0x14)
+
+#define PCIE_CAP_OFFSET0x70
+#define PCIE_DEV_CTRL_DEV_STUS (PCIE_CAP_OFFSET + 0x08)
+#define PCIE_CAP_MAX_PAYLOAD_MASK GENMASK(7, 5)
+#define PCIE_CAP_MAX_PAYLOAD_SIZE(x) ((x) << 5)
+#define PCIE_CAP_MAX_READ_REQ_MASK GENMASK(14, 12)
+#define PCIE_CAP_MAX_READ_REQ_SIZE(x) ((x) << 12)
+
+#define PCI_CLASS_REVISION_MASKGENMASK(7, 0)
+
+/* PCIe specific config registers */
+#define PCIE_CFG0 0x0
+#define APP_LTSSM_ENABLE BIT(7)
+
+#define PCIE_CFG_STATUS12 0x30
+#define IS_SMLH_LINK_UP(x) ((x) & (1 << 6))
+#define IS_RDLH_LINK_UP(x) ((x) & (1 << 16))
+#define IS_LTSSM_UP(x) x) >> 10) & 0x1f) == 0x11)
+
+#define PCIE_CFG_STATUS17 0x44
+#define PM_CURRENT_STATE(x)(((x) >> 7) & 0x1)
+
+#define WAIT_LINKUP_TIMEOUT2000
+#define PORT_CLK_RATE 1UL
+#define MAX_PAYLOAD_SIZE 256
+#define MAX_READ_REQ_SIZE 256
+#define MESON_PCIE_PHY_POWERUP 0x1c
+#define PCIE_RESET_DELAY 500
+#define PCIE_SHARED_RESET 1
+#define PCIE_NORMAL_RESET 0
+
+enum pcie_data_rate {
+ PCIE_GEN1,
+ PCIE_GEN2,
+ PCIE_GEN3,
+ PCIE_GEN4
+};
+
+struct meson_pcie_mem_res {
+ void __iomem *elbi_base; /* DT 0th resource */
+ void __iomem *cfg_base; /* DT 1nd resource */
+ void __iomem *phy_base; /* DT 2nd resource */
+};
+
+struct
[PATCH v3 0/2] add the Amlogic Meson PCIe controller driver
The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core. This patchset add the driver and dt-bindings of the controller. Till patch v2, we have a dedicated phy driver which only process reset job. It's too overkill so we integrate phy driver into the controller. Changes since v2: [1] - abandon phy driver, move reset to the controller - use devm_add_action_or_reset() to use clock res - format correcting Changes since v1: [0] - use gpio lib instead open code - move 'apb' and 'port' reset from phy driver - format correcting [0] : https://lkml.kernel.org/r/1534227522-186798-1-git-send-email-hanjie@amlogic.com [1] : https://lkml.kernel.org/r/1535096165-45827-1-git-send-email-hanjie@amlogic.com Yue Wang (2): dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller PCI: meson: add the Amlogic Meson PCIe controller driver .../devicetree/bindings/pci/amlogic,meson-pcie.txt | 70 +++ drivers/pci/controller/dwc/Kconfig | 12 + drivers/pci/controller/dwc/Makefile| 1 + drivers/pci/controller/dwc/pci-meson.c | 617 + 4 files changed, 700 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt create mode 100644 drivers/pci/controller/dwc/pci-meson.c -- 2.7.4
Re: [PATCH v2 1/2] dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller
On 2018/8/29 8:41, Rob Herring wrote: > On Mon, Aug 27, 2018 at 04:55:20PM +0800, Hanjie Lin wrote: >> >> >> On 2018/8/24 16:22, Jerome Brunet wrote: >>> On Fri, 2018-08-24 at 15:36 +0800, Hanjie Lin wrote: >>>> From: Yue Wang >>>> >>>> The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare >>>> PCI core. This patch adds documentation for the DT bindings in Meson PCIe >>>> controller. >>>> >>>> Signed-off-by: Yue Wang >>>> Signed-off-by: Hanjie Lin >>>> --- >>>> .../devicetree/bindings/pci/amlogic,meson-pcie.txt | 63 >>>> ++ >>>> 1 file changed, 63 insertions(+) >>>> create mode 100644 >>>> Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt >>>> >>>> diff --git a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt >>>> b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt >>>> new file mode 100644 >>>> index 000..8a831d1 >>>> --- /dev/null >>>> +++ b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt >>>> @@ -0,0 +1,63 @@ >>>> +Amlogic Meson AXG DWC PCIE SoC controller >>>> + >>>> +Amlogic Meson PCIe host controller is based on the Synopsys DesignWare >>>> PCI core. >>>> +It shares common functions with the PCIe DesignWare core driver and >>>> +inherits common properties defined in >>>> +Documentation/devicetree/bindings/pci/designware-pci.txt. >>>> + >>>> +Additional properties are described here: >>>> + >>>> +Required properties: >>>> +- compatible: >>>> + should contain "amlogic,axg-pcie" to identify the core. >>>> +- reg: >>>> + Should contain the configuration address space. >>>> +- reg-names: Must be >>>> + - "elbi"External local bus interface registers >>>> + - "cfg" Meson specific registers >>>> + - "config" PCIe configuration space >>>> +- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert >>>> signal. >>>> +- clocks: Must contain an entry for each entry in clock-names. >>>> +- clock-names: Must include the following entries: >>>> + - "pclk" PCIe GEN 100M PLL clock >>>> + - "port" PCIe_x(A or B) RC clock gate >>>> + - "general"PCIe Phy clock >>>> + - "mipi" PCIe_x(A or B) 100M ref clock gate >>>> +- resets: phandle to the reset lines. >>>> +- reset-names: must contain "phy" and "peripheral" >>>> + - "port" Port A or B reset >>>> + - "apb" APB reset >>> >>> The above description is not coherent (phy <=> port) >>> >> >> Yes, this should be port and apb here. >> We'll integrate phy driver into ctrl driver, and move phy reset to here also. > > Why? That's the wrong thing to do if they are separate h/w blocks. You > can do whatever you like in the drivers, but the DT should reflect the > h/w. > > Rob > > . > We have the dedicated phy driver which only process reset job, and we consider that it's too overkill to do just these things . So we will integrate phy reset job into the controller driver int the next version. thanks.
Re: [PATCH v2 1/2] dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller
On 2018/8/29 8:41, Rob Herring wrote: > On Mon, Aug 27, 2018 at 04:55:20PM +0800, Hanjie Lin wrote: >> >> >> On 2018/8/24 16:22, Jerome Brunet wrote: >>> On Fri, 2018-08-24 at 15:36 +0800, Hanjie Lin wrote: >>>> From: Yue Wang >>>> >>>> The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare >>>> PCI core. This patch adds documentation for the DT bindings in Meson PCIe >>>> controller. >>>> >>>> Signed-off-by: Yue Wang >>>> Signed-off-by: Hanjie Lin >>>> --- >>>> .../devicetree/bindings/pci/amlogic,meson-pcie.txt | 63 >>>> ++ >>>> 1 file changed, 63 insertions(+) >>>> create mode 100644 >>>> Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt >>>> >>>> diff --git a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt >>>> b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt >>>> new file mode 100644 >>>> index 000..8a831d1 >>>> --- /dev/null >>>> +++ b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt >>>> @@ -0,0 +1,63 @@ >>>> +Amlogic Meson AXG DWC PCIE SoC controller >>>> + >>>> +Amlogic Meson PCIe host controller is based on the Synopsys DesignWare >>>> PCI core. >>>> +It shares common functions with the PCIe DesignWare core driver and >>>> +inherits common properties defined in >>>> +Documentation/devicetree/bindings/pci/designware-pci.txt. >>>> + >>>> +Additional properties are described here: >>>> + >>>> +Required properties: >>>> +- compatible: >>>> + should contain "amlogic,axg-pcie" to identify the core. >>>> +- reg: >>>> + Should contain the configuration address space. >>>> +- reg-names: Must be >>>> + - "elbi"External local bus interface registers >>>> + - "cfg" Meson specific registers >>>> + - "config" PCIe configuration space >>>> +- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert >>>> signal. >>>> +- clocks: Must contain an entry for each entry in clock-names. >>>> +- clock-names: Must include the following entries: >>>> + - "pclk" PCIe GEN 100M PLL clock >>>> + - "port" PCIe_x(A or B) RC clock gate >>>> + - "general"PCIe Phy clock >>>> + - "mipi" PCIe_x(A or B) 100M ref clock gate >>>> +- resets: phandle to the reset lines. >>>> +- reset-names: must contain "phy" and "peripheral" >>>> + - "port" Port A or B reset >>>> + - "apb" APB reset >>> >>> The above description is not coherent (phy <=> port) >>> >> >> Yes, this should be port and apb here. >> We'll integrate phy driver into ctrl driver, and move phy reset to here also. > > Why? That's the wrong thing to do if they are separate h/w blocks. You > can do whatever you like in the drivers, but the DT should reflect the > h/w. > > Rob > > . > We have the dedicated phy driver which only process reset job, and we consider that it's too overkill to do just these things . So we will integrate phy reset job into the controller driver int the next version. thanks.
Re: [PATCH v2 2/2] PCI: meson: add the Amlogic Meson PCIe controller driver
On 2018/8/24 16:22, Jerome Brunet wrote: > On Fri, 2018-08-24 at 15:36 +0800, Hanjie Lin wrote: >> From: Yue Wang >> >> The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare >> PCI core. This patch adds the driver support for Meson PCIe controller. >> >> Signed-off-by: Yue Wang >> Signed-off-by: Hanjie Lin >> --- >> drivers/pci/controller/dwc/Kconfig | 12 + >> drivers/pci/controller/dwc/Makefile| 1 + >> drivers/pci/controller/dwc/pci-meson.c | 613 >> + >> 3 files changed, 626 insertions(+) >> create mode 100644 drivers/pci/controller/dwc/pci-meson.c >> >> diff --git a/drivers/pci/controller/dwc/Kconfig >> b/drivers/pci/controller/dwc/Kconfig >> index 91b0194..6cb36f6 100644 >> --- a/drivers/pci/controller/dwc/Kconfig >> +++ b/drivers/pci/controller/dwc/Kconfig >> @@ -193,4 +193,16 @@ config PCIE_HISI_STB >> help >>Say Y here if you want PCIe controller support on HiSilicon STB >> SoCs >> >> +config PCI_MESON >> +bool "MESON PCIe controller" >> +depends on PCI >> +depends on PCI_MSI_IRQ_DOMAIN >> +select PCIEPORTBUS >> +select PCIE_DW_HOST >> +help >> + Say Y here if you want to enable PCI controller support on Amlogic >> + SoCs. The PCI controller on Amlogic is based on DesignWare hardware >> + and therefore the driver re-uses the DesignWare core functions to >> + implement the driver. >> + >> endmenu >> diff --git a/drivers/pci/controller/dwc/Makefile >> b/drivers/pci/controller/dwc/Makefile >> index 5d2ce72..cf676bd 100644 >> --- a/drivers/pci/controller/dwc/Makefile >> +++ b/drivers/pci/controller/dwc/Makefile >> @@ -14,6 +14,7 @@ obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o >> obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o >> obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o >> obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o >> +obj-$(CONFIG_PCI_MESON) += pci-meson.o >> >> # The following drivers are for devices that use the generic ACPI >> # pci_root.c driver but don't support standard ECAM config access. >> diff --git a/drivers/pci/controller/dwc/pci-meson.c >> b/drivers/pci/controller/dwc/pci-meson.c >> new file mode 100644 >> index 000..a9edf20 >> --- /dev/null >> +++ b/drivers/pci/controller/dwc/pci-meson.c >> @@ -0,0 +1,613 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * PCIe host controller driver for Amlogic MESON SoCs >> + * >> + * Copyright (c) 2018 Amlogic, inc. >> + * Author: Yue Wang >> + */ >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> + >> +#include "pcie-designware.h" >> + >> +#define to_meson_pcie(x) dev_get_drvdata((x)->dev) >> + >> +/* External local bus interface registers */ >> +#define PLR_OFFSET 0x700 >> +#define PCIE_PORT_LINK_CTRL_OFF (PLR_OFFSET + 0x10) >> +#define FAST_LINK_MODE BIT(7) >> +#define LINK_CAPABLE_MASK GENMASK(21, 16) >> +#define LINK_CAPABLE_X1 BIT(16) >> + >> +#define PCIE_GEN2_CTRL_OFF (PLR_OFFSET + 0x10c) >> +#define NUM_OF_LANES_MASK GENMASK(12, 8) >> +#define NUM_OF_LANES_X1 BIT(8) >> +#define DIRECT_SPEED_CHANGE BIT(17) >> + >> +#define TYPE1_HDR_OFFSET0x0 >> +#define PCIE_STATUS_COMMAND (TYPE1_HDR_OFFSET + 0x04) >> +#define PCI_IO_EN BIT(0) >> +#define PCI_MEM_SPACE_ENBIT(1) >> +#define PCI_BUS_MASTER_EN BIT(2) >> + >> +#define PCIE_BASE_ADDR0 (TYPE1_HDR_OFFSET + 0x10) >> +#define PCIE_BASE_ADDR1 (TYPE1_HDR_OFFSET + 0x14) >> + >> +#define PCIE_CAP_OFFSET 0x70 >> +#define PCIE_DEV_CTRL_DEV_STUS (PCIE_CAP_OFFSET + 0x08) >> +#define PCIE_CAP_MAX_PAYLOAD_MASK GENMASK(7, 5) >> +#define PCIE_CAP_MAX_PAYLOAD_SIZE(x)((x) << 5) >> +#define PCIE_CAP_MAX_READ_REQ_MASK GENMASK(14, 12) >> +#define PCIE_CAP_MAX_READ_REQ_SIZE(x) ((x) << 12) >> + >> +#define PCI_CLASS_REVISION_MASK GENMASK(7, 0) >> + >> +/* PCIe specific config registers */ >> +#define PCIE_CFG0 0x0 >> +#define APP_LTSSM_ENABLE
Re: [PATCH v2 2/2] PCI: meson: add the Amlogic Meson PCIe controller driver
On 2018/8/24 16:22, Jerome Brunet wrote: > On Fri, 2018-08-24 at 15:36 +0800, Hanjie Lin wrote: >> From: Yue Wang >> >> The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare >> PCI core. This patch adds the driver support for Meson PCIe controller. >> >> Signed-off-by: Yue Wang >> Signed-off-by: Hanjie Lin >> --- >> drivers/pci/controller/dwc/Kconfig | 12 + >> drivers/pci/controller/dwc/Makefile| 1 + >> drivers/pci/controller/dwc/pci-meson.c | 613 >> + >> 3 files changed, 626 insertions(+) >> create mode 100644 drivers/pci/controller/dwc/pci-meson.c >> >> diff --git a/drivers/pci/controller/dwc/Kconfig >> b/drivers/pci/controller/dwc/Kconfig >> index 91b0194..6cb36f6 100644 >> --- a/drivers/pci/controller/dwc/Kconfig >> +++ b/drivers/pci/controller/dwc/Kconfig >> @@ -193,4 +193,16 @@ config PCIE_HISI_STB >> help >>Say Y here if you want PCIe controller support on HiSilicon STB >> SoCs >> >> +config PCI_MESON >> +bool "MESON PCIe controller" >> +depends on PCI >> +depends on PCI_MSI_IRQ_DOMAIN >> +select PCIEPORTBUS >> +select PCIE_DW_HOST >> +help >> + Say Y here if you want to enable PCI controller support on Amlogic >> + SoCs. The PCI controller on Amlogic is based on DesignWare hardware >> + and therefore the driver re-uses the DesignWare core functions to >> + implement the driver. >> + >> endmenu >> diff --git a/drivers/pci/controller/dwc/Makefile >> b/drivers/pci/controller/dwc/Makefile >> index 5d2ce72..cf676bd 100644 >> --- a/drivers/pci/controller/dwc/Makefile >> +++ b/drivers/pci/controller/dwc/Makefile >> @@ -14,6 +14,7 @@ obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o >> obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o >> obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o >> obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o >> +obj-$(CONFIG_PCI_MESON) += pci-meson.o >> >> # The following drivers are for devices that use the generic ACPI >> # pci_root.c driver but don't support standard ECAM config access. >> diff --git a/drivers/pci/controller/dwc/pci-meson.c >> b/drivers/pci/controller/dwc/pci-meson.c >> new file mode 100644 >> index 000..a9edf20 >> --- /dev/null >> +++ b/drivers/pci/controller/dwc/pci-meson.c >> @@ -0,0 +1,613 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * PCIe host controller driver for Amlogic MESON SoCs >> + * >> + * Copyright (c) 2018 Amlogic, inc. >> + * Author: Yue Wang >> + */ >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> + >> +#include "pcie-designware.h" >> + >> +#define to_meson_pcie(x) dev_get_drvdata((x)->dev) >> + >> +/* External local bus interface registers */ >> +#define PLR_OFFSET 0x700 >> +#define PCIE_PORT_LINK_CTRL_OFF (PLR_OFFSET + 0x10) >> +#define FAST_LINK_MODE BIT(7) >> +#define LINK_CAPABLE_MASK GENMASK(21, 16) >> +#define LINK_CAPABLE_X1 BIT(16) >> + >> +#define PCIE_GEN2_CTRL_OFF (PLR_OFFSET + 0x10c) >> +#define NUM_OF_LANES_MASK GENMASK(12, 8) >> +#define NUM_OF_LANES_X1 BIT(8) >> +#define DIRECT_SPEED_CHANGE BIT(17) >> + >> +#define TYPE1_HDR_OFFSET0x0 >> +#define PCIE_STATUS_COMMAND (TYPE1_HDR_OFFSET + 0x04) >> +#define PCI_IO_EN BIT(0) >> +#define PCI_MEM_SPACE_ENBIT(1) >> +#define PCI_BUS_MASTER_EN BIT(2) >> + >> +#define PCIE_BASE_ADDR0 (TYPE1_HDR_OFFSET + 0x10) >> +#define PCIE_BASE_ADDR1 (TYPE1_HDR_OFFSET + 0x14) >> + >> +#define PCIE_CAP_OFFSET 0x70 >> +#define PCIE_DEV_CTRL_DEV_STUS (PCIE_CAP_OFFSET + 0x08) >> +#define PCIE_CAP_MAX_PAYLOAD_MASK GENMASK(7, 5) >> +#define PCIE_CAP_MAX_PAYLOAD_SIZE(x)((x) << 5) >> +#define PCIE_CAP_MAX_READ_REQ_MASK GENMASK(14, 12) >> +#define PCIE_CAP_MAX_READ_REQ_SIZE(x) ((x) << 12) >> + >> +#define PCI_CLASS_REVISION_MASK GENMASK(7, 0) >> + >> +/* PCIe specific config registers */ >> +#define PCIE_CFG0 0x0 >> +#define APP_LTSSM_ENABLE
Re: [PATCH v2 1/2] dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller
On 2018/8/24 16:22, Jerome Brunet wrote:
> On Fri, 2018-08-24 at 15:36 +0800, Hanjie Lin wrote:
>> From: Yue Wang
>>
>> The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare
>> PCI core. This patch adds documentation for the DT bindings in Meson PCIe
>> controller.
>>
>> Signed-off-by: Yue Wang
>> Signed-off-by: Hanjie Lin
>> ---
>> .../devicetree/bindings/pci/amlogic,meson-pcie.txt | 63
>> ++
>> 1 file changed, 63 insertions(+)
>> create mode 100644
>> Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
>>
>> diff --git a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
>> b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
>> new file mode 100644
>> index 000..8a831d1
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
>> @@ -0,0 +1,63 @@
>> +Amlogic Meson AXG DWC PCIE SoC controller
>> +
>> +Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI
>> core.
>> +It shares common functions with the PCIe DesignWare core driver and
>> +inherits common properties defined in
>> +Documentation/devicetree/bindings/pci/designware-pci.txt.
>> +
>> +Additional properties are described here:
>> +
>> +Required properties:
>> +- compatible:
>> +should contain "amlogic,axg-pcie" to identify the core.
>> +- reg:
>> +Should contain the configuration address space.
>> +- reg-names: Must be
>> +- "elbi"External local bus interface registers
>> +- "cfg" Meson specific registers
>> +- "config" PCIe configuration space
>> +- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
>> +- clocks: Must contain an entry for each entry in clock-names.
>> +- clock-names: Must include the following entries:
>> +- "pclk" PCIe GEN 100M PLL clock
>> +- "port" PCIe_x(A or B) RC clock gate
>> +- "general"PCIe Phy clock
>> +- "mipi" PCIe_x(A or B) 100M ref clock gate
>> +- resets: phandle to the reset lines.
>> +- reset-names: must contain "phy" and "peripheral"
>> + - "port" Port A or B reset
>> + - "apb" APB reset
>
> The above description is not coherent (phy <=> port)
>
Yes, this should be port and apb here.
We'll integrate phy driver into ctrl driver, and move phy reset to here also.
>> +
>> +Example configuration:
>> +
>> +pcie: pcie@f980 {
>> +compatible = "amlogic,axg-pcie", "snps,dw-pcie";
>> +reg = <0x0 0xf980 0x0 0x40
>> +0x0 0xff646000 0x0 0x2000
>> +0x0 0xf9f0 0x0 0x10>;
>> +reg-names = "elbi", "cfg", "config";
>> +reset-gpios = < GPIOX_19 GPIO_ACTIVE_HIGH>;
>> +interrupts = ;
>> +#interrupt-cells = <1>;
>> +interrupt-map-mask = <0 0 0 0>;
>> +interrupt-map = <0 0 0 0 GIC_SPI 179
>> IRQ_TYPE_EDGE_RISING>;
>> +bus-range = <0x0 0xff>;
>> +#address-cells = <3>;
>> +#size-cells = <2>;
>> +device_type = "pci";
>
> Not described above - is it even used ?
>
It's necessary, specified in designware-pcie.txt:
- device_type:
Usage: required
Value type:
Definition: Should be "pci".
>> +phys = <_phy>;
>
> Not documented and not necessary. Please remove this.
>
We'll remove phy driver and this also.
>> +ranges = <0x8200 0 0 0x0 0xf9c0 0 0x0030>;
>> +
>> +clocks = < CLKID_USB
>> + CLKID_MIPI_ENABLE
>> + CLKID_PCIE_A
>> + CLKID_PCIE_CML_EN0>;
>> +clock-names = "general",
>> +"mipi",
>> +"pclk",
>> +"port";
>> +resets = < RESET_PCIE_A>,
>> +< RESET_PCIE_APB>;
>> +reset-names = "port",
>> +"apb";
>> +};
>
>
> .
>
Re: [PATCH v2 1/2] dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller
On 2018/8/24 16:22, Jerome Brunet wrote:
> On Fri, 2018-08-24 at 15:36 +0800, Hanjie Lin wrote:
>> From: Yue Wang
>>
>> The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare
>> PCI core. This patch adds documentation for the DT bindings in Meson PCIe
>> controller.
>>
>> Signed-off-by: Yue Wang
>> Signed-off-by: Hanjie Lin
>> ---
>> .../devicetree/bindings/pci/amlogic,meson-pcie.txt | 63
>> ++
>> 1 file changed, 63 insertions(+)
>> create mode 100644
>> Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
>>
>> diff --git a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
>> b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
>> new file mode 100644
>> index 000..8a831d1
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
>> @@ -0,0 +1,63 @@
>> +Amlogic Meson AXG DWC PCIE SoC controller
>> +
>> +Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI
>> core.
>> +It shares common functions with the PCIe DesignWare core driver and
>> +inherits common properties defined in
>> +Documentation/devicetree/bindings/pci/designware-pci.txt.
>> +
>> +Additional properties are described here:
>> +
>> +Required properties:
>> +- compatible:
>> +should contain "amlogic,axg-pcie" to identify the core.
>> +- reg:
>> +Should contain the configuration address space.
>> +- reg-names: Must be
>> +- "elbi"External local bus interface registers
>> +- "cfg" Meson specific registers
>> +- "config" PCIe configuration space
>> +- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
>> +- clocks: Must contain an entry for each entry in clock-names.
>> +- clock-names: Must include the following entries:
>> +- "pclk" PCIe GEN 100M PLL clock
>> +- "port" PCIe_x(A or B) RC clock gate
>> +- "general"PCIe Phy clock
>> +- "mipi" PCIe_x(A or B) 100M ref clock gate
>> +- resets: phandle to the reset lines.
>> +- reset-names: must contain "phy" and "peripheral"
>> + - "port" Port A or B reset
>> + - "apb" APB reset
>
> The above description is not coherent (phy <=> port)
>
Yes, this should be port and apb here.
We'll integrate phy driver into ctrl driver, and move phy reset to here also.
>> +
>> +Example configuration:
>> +
>> +pcie: pcie@f980 {
>> +compatible = "amlogic,axg-pcie", "snps,dw-pcie";
>> +reg = <0x0 0xf980 0x0 0x40
>> +0x0 0xff646000 0x0 0x2000
>> +0x0 0xf9f0 0x0 0x10>;
>> +reg-names = "elbi", "cfg", "config";
>> +reset-gpios = < GPIOX_19 GPIO_ACTIVE_HIGH>;
>> +interrupts = ;
>> +#interrupt-cells = <1>;
>> +interrupt-map-mask = <0 0 0 0>;
>> +interrupt-map = <0 0 0 0 GIC_SPI 179
>> IRQ_TYPE_EDGE_RISING>;
>> +bus-range = <0x0 0xff>;
>> +#address-cells = <3>;
>> +#size-cells = <2>;
>> +device_type = "pci";
>
> Not described above - is it even used ?
>
It's necessary, specified in designware-pcie.txt:
- device_type:
Usage: required
Value type:
Definition: Should be "pci".
>> +phys = <_phy>;
>
> Not documented and not necessary. Please remove this.
>
We'll remove phy driver and this also.
>> +ranges = <0x8200 0 0 0x0 0xf9c0 0 0x0030>;
>> +
>> +clocks = < CLKID_USB
>> + CLKID_MIPI_ENABLE
>> + CLKID_PCIE_A
>> + CLKID_PCIE_CML_EN0>;
>> +clock-names = "general",
>> +"mipi",
>> +"pclk",
>> +"port";
>> +resets = < RESET_PCIE_A>,
>> +< RESET_PCIE_APB>;
>> +reset-names = "port",
>> +"apb";
>> +};
>
>
> .
>
[PATCH v2 1/2] dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller
From: Yue Wang
The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare
PCI core. This patch adds documentation for the DT bindings in Meson PCIe
controller.
Signed-off-by: Yue Wang
Signed-off-by: Hanjie Lin
---
.../devicetree/bindings/pci/amlogic,meson-pcie.txt | 63 ++
1 file changed, 63 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
diff --git a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
new file mode 100644
index 000..8a831d1
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
@@ -0,0 +1,63 @@
+Amlogic Meson AXG DWC PCIE SoC controller
+
+Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI
core.
+It shares common functions with the PCIe DesignWare core driver and
+inherits common properties defined in
+Documentation/devicetree/bindings/pci/designware-pci.txt.
+
+Additional properties are described here:
+
+Required properties:
+- compatible:
+ should contain "amlogic,axg-pcie" to identify the core.
+- reg:
+ Should contain the configuration address space.
+- reg-names: Must be
+ - "elbi"External local bus interface registers
+ - "cfg" Meson specific registers
+ - "config" PCIe configuration space
+- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
+- clocks: Must contain an entry for each entry in clock-names.
+- clock-names: Must include the following entries:
+ - "pclk" PCIe GEN 100M PLL clock
+ - "port" PCIe_x(A or B) RC clock gate
+ - "general"PCIe Phy clock
+ - "mipi" PCIe_x(A or B) 100M ref clock gate
+- resets: phandle to the reset lines.
+- reset-names: must contain "phy" and "peripheral"
+ - "port" Port A or B reset
+ - "apb" APB reset
+
+Example configuration:
+
+ pcie: pcie@f980 {
+ compatible = "amlogic,axg-pcie", "snps,dw-pcie";
+ reg = <0x0 0xf980 0x0 0x40
+ 0x0 0xff646000 0x0 0x2000
+ 0x0 0xf9f0 0x0 0x10>;
+ reg-names = "elbi", "cfg", "config";
+ reset-gpios = < GPIOX_19 GPIO_ACTIVE_HIGH>;
+ interrupts = ;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 GIC_SPI 179
IRQ_TYPE_EDGE_RISING>;
+ bus-range = <0x0 0xff>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ phys = <_phy>;
+ ranges = <0x8200 0 0 0x0 0xf9c0 0 0x0030>;
+
+ clocks = < CLKID_USB
+CLKID_MIPI_ENABLE
+CLKID_PCIE_A
+CLKID_PCIE_CML_EN0>;
+ clock-names = "general",
+ "mipi",
+ "pclk",
+ "port";
+ resets = < RESET_PCIE_A>,
+ < RESET_PCIE_APB>;
+ reset-names = "port",
+ "apb";
+ };
--
2.7.4
[PATCH v2 1/2] dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller
From: Yue Wang
The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare
PCI core. This patch adds documentation for the DT bindings in Meson PCIe
controller.
Signed-off-by: Yue Wang
Signed-off-by: Hanjie Lin
---
.../devicetree/bindings/pci/amlogic,meson-pcie.txt | 63 ++
1 file changed, 63 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
diff --git a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
new file mode 100644
index 000..8a831d1
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
@@ -0,0 +1,63 @@
+Amlogic Meson AXG DWC PCIE SoC controller
+
+Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI
core.
+It shares common functions with the PCIe DesignWare core driver and
+inherits common properties defined in
+Documentation/devicetree/bindings/pci/designware-pci.txt.
+
+Additional properties are described here:
+
+Required properties:
+- compatible:
+ should contain "amlogic,axg-pcie" to identify the core.
+- reg:
+ Should contain the configuration address space.
+- reg-names: Must be
+ - "elbi"External local bus interface registers
+ - "cfg" Meson specific registers
+ - "config" PCIe configuration space
+- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
+- clocks: Must contain an entry for each entry in clock-names.
+- clock-names: Must include the following entries:
+ - "pclk" PCIe GEN 100M PLL clock
+ - "port" PCIe_x(A or B) RC clock gate
+ - "general"PCIe Phy clock
+ - "mipi" PCIe_x(A or B) 100M ref clock gate
+- resets: phandle to the reset lines.
+- reset-names: must contain "phy" and "peripheral"
+ - "port" Port A or B reset
+ - "apb" APB reset
+
+Example configuration:
+
+ pcie: pcie@f980 {
+ compatible = "amlogic,axg-pcie", "snps,dw-pcie";
+ reg = <0x0 0xf980 0x0 0x40
+ 0x0 0xff646000 0x0 0x2000
+ 0x0 0xf9f0 0x0 0x10>;
+ reg-names = "elbi", "cfg", "config";
+ reset-gpios = < GPIOX_19 GPIO_ACTIVE_HIGH>;
+ interrupts = ;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 GIC_SPI 179
IRQ_TYPE_EDGE_RISING>;
+ bus-range = <0x0 0xff>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ phys = <_phy>;
+ ranges = <0x8200 0 0 0x0 0xf9c0 0 0x0030>;
+
+ clocks = < CLKID_USB
+CLKID_MIPI_ENABLE
+CLKID_PCIE_A
+CLKID_PCIE_CML_EN0>;
+ clock-names = "general",
+ "mipi",
+ "pclk",
+ "port";
+ resets = < RESET_PCIE_A>,
+ < RESET_PCIE_APB>;
+ reset-names = "port",
+ "apb";
+ };
--
2.7.4
[PATCH v2 2/2] PCI: meson: add the Amlogic Meson PCIe controller driver
From: Yue Wang
The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare
PCI core. This patch adds the driver support for Meson PCIe controller.
Signed-off-by: Yue Wang
Signed-off-by: Hanjie Lin
---
drivers/pci/controller/dwc/Kconfig | 12 +
drivers/pci/controller/dwc/Makefile| 1 +
drivers/pci/controller/dwc/pci-meson.c | 613 +
3 files changed, 626 insertions(+)
create mode 100644 drivers/pci/controller/dwc/pci-meson.c
diff --git a/drivers/pci/controller/dwc/Kconfig
b/drivers/pci/controller/dwc/Kconfig
index 91b0194..6cb36f6 100644
--- a/drivers/pci/controller/dwc/Kconfig
+++ b/drivers/pci/controller/dwc/Kconfig
@@ -193,4 +193,16 @@ config PCIE_HISI_STB
help
Say Y here if you want PCIe controller support on HiSilicon STB SoCs
+config PCI_MESON
+ bool "MESON PCIe controller"
+ depends on PCI
+ depends on PCI_MSI_IRQ_DOMAIN
+ select PCIEPORTBUS
+ select PCIE_DW_HOST
+ help
+ Say Y here if you want to enable PCI controller support on Amlogic
+ SoCs. The PCI controller on Amlogic is based on DesignWare hardware
+ and therefore the driver re-uses the DesignWare core functions to
+ implement the driver.
+
endmenu
diff --git a/drivers/pci/controller/dwc/Makefile
b/drivers/pci/controller/dwc/Makefile
index 5d2ce72..cf676bd 100644
--- a/drivers/pci/controller/dwc/Makefile
+++ b/drivers/pci/controller/dwc/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o
obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o
+obj-$(CONFIG_PCI_MESON) += pci-meson.o
# The following drivers are for devices that use the generic ACPI
# pci_root.c driver but don't support standard ECAM config access.
diff --git a/drivers/pci/controller/dwc/pci-meson.c
b/drivers/pci/controller/dwc/pci-meson.c
new file mode 100644
index 000..a9edf20
--- /dev/null
+++ b/drivers/pci/controller/dwc/pci-meson.c
@@ -0,0 +1,613 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PCIe host controller driver for Amlogic MESON SoCs
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Yue Wang
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "pcie-designware.h"
+
+#define to_meson_pcie(x) dev_get_drvdata((x)->dev)
+
+/* External local bus interface registers */
+#define PLR_OFFSET 0x700
+#define PCIE_PORT_LINK_CTRL_OFF(PLR_OFFSET + 0x10)
+#define FAST_LINK_MODE BIT(7)
+#define LINK_CAPABLE_MASK GENMASK(21, 16)
+#define LINK_CAPABLE_X1BIT(16)
+
+#define PCIE_GEN2_CTRL_OFF (PLR_OFFSET + 0x10c)
+#define NUM_OF_LANES_MASK GENMASK(12, 8)
+#define NUM_OF_LANES_X1BIT(8)
+#define DIRECT_SPEED_CHANGEBIT(17)
+
+#define TYPE1_HDR_OFFSET 0x0
+#define PCIE_STATUS_COMMAND(TYPE1_HDR_OFFSET + 0x04)
+#define PCI_IO_EN BIT(0)
+#define PCI_MEM_SPACE_EN BIT(1)
+#define PCI_BUS_MASTER_EN BIT(2)
+
+#define PCIE_BASE_ADDR0(TYPE1_HDR_OFFSET + 0x10)
+#define PCIE_BASE_ADDR1(TYPE1_HDR_OFFSET + 0x14)
+
+#define PCIE_CAP_OFFSET0x70
+#define PCIE_DEV_CTRL_DEV_STUS (PCIE_CAP_OFFSET + 0x08)
+#define PCIE_CAP_MAX_PAYLOAD_MASK GENMASK(7, 5)
+#define PCIE_CAP_MAX_PAYLOAD_SIZE(x) ((x) << 5)
+#define PCIE_CAP_MAX_READ_REQ_MASK GENMASK(14, 12)
+#define PCIE_CAP_MAX_READ_REQ_SIZE(x) ((x) << 12)
+
+#define PCI_CLASS_REVISION_MASKGENMASK(7, 0)
+
+/* PCIe specific config registers */
+#define PCIE_CFG0 0x0
+#define APP_LTSSM_ENABLE BIT(7)
+
+#define PCIE_CFG_STATUS12 0x30
+#define IS_SMLH_LINK_UP(x) ((x) & (1 << 6))
+#define IS_RDLH_LINK_UP(x) ((x) & (1 << 16))
+#define IS_LTSSM_UP(x) x) >> 10) & 0x1f) == 0x11)
+
+#define PCIE_CFG_STATUS17 0x44
+#define PM_CURRENT_STATE(x)(((x) >> 7) & 0x1)
+
+#define WAIT_LINKUP_TIMEOUT2000
+#define PORT_CLK_RATE 1UL
+#define MAX_PAYLOAD_SIZE 256
+#define MAX_READ_REQ_SIZE 256
+
+enum pcie_data_rate {
+ PCIE_GEN1,
+ PCIE_GEN2,
+ PCIE_GEN3,
+ PCIE_GEN4
+};
+
+struct meson_pcie_mem_res {
+ void __iomem *elbi_base; /* DT 0th resource */
+ void __iomem *cfg_base; /* DT 2nd resource */
+};
+
+struct meson_pcie_clk_res {
+ struct clk *clk;
+ struct clk *mipi_gate;
+ struct clk *port_clk;
+ struct clk *general_clk;
+};
+
+struct meson_pcie_rc_reset {
+ struct reset_control *port;
+ struc
[PATCH v2 0/2] add the Amlogic Meson PCIe controller driver.
The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core. This patchset add the driver and dt-bindings of the controller. Changes since v1: [0] - use gpio lib instead open code - move 'apb' and 'port' reset from phy driver - format correcting [0] : https://lkml.org/lkml/2018/8/14/70 Yue Wang (2): dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller PCI: meson: add the Amlogic Meson PCIe controller driver .../devicetree/bindings/pci/amlogic,meson-pcie.txt | 63 +++ drivers/pci/controller/dwc/Kconfig | 12 + drivers/pci/controller/dwc/Makefile| 1 + drivers/pci/controller/dwc/pci-meson.c | 613 + 4 files changed, 689 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt create mode 100644 drivers/pci/controller/dwc/pci-meson.c -- 2.7.4
[PATCH v2 2/2] PCI: meson: add the Amlogic Meson PCIe controller driver
From: Yue Wang
The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare
PCI core. This patch adds the driver support for Meson PCIe controller.
Signed-off-by: Yue Wang
Signed-off-by: Hanjie Lin
---
drivers/pci/controller/dwc/Kconfig | 12 +
drivers/pci/controller/dwc/Makefile| 1 +
drivers/pci/controller/dwc/pci-meson.c | 613 +
3 files changed, 626 insertions(+)
create mode 100644 drivers/pci/controller/dwc/pci-meson.c
diff --git a/drivers/pci/controller/dwc/Kconfig
b/drivers/pci/controller/dwc/Kconfig
index 91b0194..6cb36f6 100644
--- a/drivers/pci/controller/dwc/Kconfig
+++ b/drivers/pci/controller/dwc/Kconfig
@@ -193,4 +193,16 @@ config PCIE_HISI_STB
help
Say Y here if you want PCIe controller support on HiSilicon STB SoCs
+config PCI_MESON
+ bool "MESON PCIe controller"
+ depends on PCI
+ depends on PCI_MSI_IRQ_DOMAIN
+ select PCIEPORTBUS
+ select PCIE_DW_HOST
+ help
+ Say Y here if you want to enable PCI controller support on Amlogic
+ SoCs. The PCI controller on Amlogic is based on DesignWare hardware
+ and therefore the driver re-uses the DesignWare core functions to
+ implement the driver.
+
endmenu
diff --git a/drivers/pci/controller/dwc/Makefile
b/drivers/pci/controller/dwc/Makefile
index 5d2ce72..cf676bd 100644
--- a/drivers/pci/controller/dwc/Makefile
+++ b/drivers/pci/controller/dwc/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o
obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o
+obj-$(CONFIG_PCI_MESON) += pci-meson.o
# The following drivers are for devices that use the generic ACPI
# pci_root.c driver but don't support standard ECAM config access.
diff --git a/drivers/pci/controller/dwc/pci-meson.c
b/drivers/pci/controller/dwc/pci-meson.c
new file mode 100644
index 000..a9edf20
--- /dev/null
+++ b/drivers/pci/controller/dwc/pci-meson.c
@@ -0,0 +1,613 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PCIe host controller driver for Amlogic MESON SoCs
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Yue Wang
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "pcie-designware.h"
+
+#define to_meson_pcie(x) dev_get_drvdata((x)->dev)
+
+/* External local bus interface registers */
+#define PLR_OFFSET 0x700
+#define PCIE_PORT_LINK_CTRL_OFF(PLR_OFFSET + 0x10)
+#define FAST_LINK_MODE BIT(7)
+#define LINK_CAPABLE_MASK GENMASK(21, 16)
+#define LINK_CAPABLE_X1BIT(16)
+
+#define PCIE_GEN2_CTRL_OFF (PLR_OFFSET + 0x10c)
+#define NUM_OF_LANES_MASK GENMASK(12, 8)
+#define NUM_OF_LANES_X1BIT(8)
+#define DIRECT_SPEED_CHANGEBIT(17)
+
+#define TYPE1_HDR_OFFSET 0x0
+#define PCIE_STATUS_COMMAND(TYPE1_HDR_OFFSET + 0x04)
+#define PCI_IO_EN BIT(0)
+#define PCI_MEM_SPACE_EN BIT(1)
+#define PCI_BUS_MASTER_EN BIT(2)
+
+#define PCIE_BASE_ADDR0(TYPE1_HDR_OFFSET + 0x10)
+#define PCIE_BASE_ADDR1(TYPE1_HDR_OFFSET + 0x14)
+
+#define PCIE_CAP_OFFSET0x70
+#define PCIE_DEV_CTRL_DEV_STUS (PCIE_CAP_OFFSET + 0x08)
+#define PCIE_CAP_MAX_PAYLOAD_MASK GENMASK(7, 5)
+#define PCIE_CAP_MAX_PAYLOAD_SIZE(x) ((x) << 5)
+#define PCIE_CAP_MAX_READ_REQ_MASK GENMASK(14, 12)
+#define PCIE_CAP_MAX_READ_REQ_SIZE(x) ((x) << 12)
+
+#define PCI_CLASS_REVISION_MASKGENMASK(7, 0)
+
+/* PCIe specific config registers */
+#define PCIE_CFG0 0x0
+#define APP_LTSSM_ENABLE BIT(7)
+
+#define PCIE_CFG_STATUS12 0x30
+#define IS_SMLH_LINK_UP(x) ((x) & (1 << 6))
+#define IS_RDLH_LINK_UP(x) ((x) & (1 << 16))
+#define IS_LTSSM_UP(x) x) >> 10) & 0x1f) == 0x11)
+
+#define PCIE_CFG_STATUS17 0x44
+#define PM_CURRENT_STATE(x)(((x) >> 7) & 0x1)
+
+#define WAIT_LINKUP_TIMEOUT2000
+#define PORT_CLK_RATE 1UL
+#define MAX_PAYLOAD_SIZE 256
+#define MAX_READ_REQ_SIZE 256
+
+enum pcie_data_rate {
+ PCIE_GEN1,
+ PCIE_GEN2,
+ PCIE_GEN3,
+ PCIE_GEN4
+};
+
+struct meson_pcie_mem_res {
+ void __iomem *elbi_base; /* DT 0th resource */
+ void __iomem *cfg_base; /* DT 2nd resource */
+};
+
+struct meson_pcie_clk_res {
+ struct clk *clk;
+ struct clk *mipi_gate;
+ struct clk *port_clk;
+ struct clk *general_clk;
+};
+
+struct meson_pcie_rc_reset {
+ struct reset_control *port;
+ struc
[PATCH v2 0/2] add the Amlogic Meson PCIe controller driver.
The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core. This patchset add the driver and dt-bindings of the controller. Changes since v1: [0] - use gpio lib instead open code - move 'apb' and 'port' reset from phy driver - format correcting [0] : https://lkml.org/lkml/2018/8/14/70 Yue Wang (2): dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller PCI: meson: add the Amlogic Meson PCIe controller driver .../devicetree/bindings/pci/amlogic,meson-pcie.txt | 63 +++ drivers/pci/controller/dwc/Kconfig | 12 + drivers/pci/controller/dwc/Makefile| 1 + drivers/pci/controller/dwc/pci-meson.c | 613 + 4 files changed, 689 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt create mode 100644 drivers/pci/controller/dwc/pci-meson.c -- 2.7.4
Re: [PATCH 2/2] PCI: meson: add the Amlogic Meson PCIe phy driver
On 2018/8/17 16:09, Jerome Brunet wrote: > On Fri, 2018-08-17 at 14:12 +0800, Hanjie Lin wrote: >> >> On 2018/8/16 16:33, Jerome Brunet wrote: >>> On Thu, 2018-08-16 at 11:05 +0800, Hanjie Lin wrote: >>>> >>>> On 2018/8/14 18:41, Jerome Brunet wrote: >>>>> On Tue, 2018-08-14 at 02:12 -0400, Hanjie Lin wrote: >>>>>> From: Yue Wang >>>>>> >>>>>> The Meson-PCIE-PHY controller supports the 5-Gbps data rate >>>>>> of the PCI Express Gen 2 specification and is backwardcompatible >>>>>> with the 2.5-Gbps Gen 1.1 specification with only >>>>>> inferred idle detection supported on AMLOGIC SoCs. >>>>> >>>>> It looks like the sole purpose of this driver is to provide the reset >>>>> lines to >>>>> pcie driver. >>>>> >>>>> I wonder why we need this ? Can't the pcie driver claim the reset lines >>>>> itself. >>>>> >>>>> Also, an init of this phy will always reset both port. What will happen >>>>> if the >>>>> first port is in use and the 2nd port comes up ?? >>>>> >>>>> Looks the the pcie driver should claim 'apb' and 'phy' reset lines as >>>>> "shared" >>>>> reset and the required 'port' as 'exclusive' >>>>> >>>> >>>> Thank you for your response. >>>> >>>> Yes, 'apb' and 'phy' reset lines are shared, and ‘port' reset line is >>>> exclusive. >>>> If we handle all reset lines during the first port initial sequence, >>>> and when the second port comes up, we will do nothing about the rest >>>> lines, >>>> and don't need a extra API to do ‘port' reset; >>> >>> With which other driver are your control shared ? >>> >>> Looks it is the answer is none since this phy driver will reset both port >>> already, even if one is used. >>> >>> In this case the fact that you are using shared control is just abusing the >>> framework to reset once. >>> >>> As far as I can tell, this driver makes no sense. The appropriate reset >>> lines >>> should be given directly to your pcie driver. >>> >>> >>> >>> . >>> >> >> Amlogic AXG SOC includes two pcie controllers and pipes when only one pcie >> phy: >> >> (port_a reset) >> |PCIE_RC_A>PCIE_PIPE_A--| >> (apb_reset) | | (phy reset) >> APB BUS---> | | PCIE_PHY >> | | >> | (port_b_reset)| >> |PCIE_RC_B>PCIE_PIPE_B--| >> >> The phy_reset affect the PCIE_PHY. >> The port_a_reset affect the PCIE_PIPE_A, port_b_reset affect the >> PCIE_PIPE_B. >> >> As your suggestion we will move the 'port' reset to controller driver, >> and keeping the phy driver to process the 'apb' and 'phy' reset or any >> more changes of the phy in future. > > As far as I can tell from this diagram, It would only make sense for the "phy" > reset line to be controlled by your phy driver. > > The apb and port is obviously related to the pcie device/driver itself, not > the > PHY. And whether you 1 or 2 reset lines in it, IMO it is overkill and > unnecessary to make a phy driver for this. > Yeah, that makes sense. We will move 'apb' reset to controller driver in next version too. Thanks. >> > > > . >
Re: [PATCH 2/2] PCI: meson: add the Amlogic Meson PCIe phy driver
On 2018/8/17 16:09, Jerome Brunet wrote: > On Fri, 2018-08-17 at 14:12 +0800, Hanjie Lin wrote: >> >> On 2018/8/16 16:33, Jerome Brunet wrote: >>> On Thu, 2018-08-16 at 11:05 +0800, Hanjie Lin wrote: >>>> >>>> On 2018/8/14 18:41, Jerome Brunet wrote: >>>>> On Tue, 2018-08-14 at 02:12 -0400, Hanjie Lin wrote: >>>>>> From: Yue Wang >>>>>> >>>>>> The Meson-PCIE-PHY controller supports the 5-Gbps data rate >>>>>> of the PCI Express Gen 2 specification and is backwardcompatible >>>>>> with the 2.5-Gbps Gen 1.1 specification with only >>>>>> inferred idle detection supported on AMLOGIC SoCs. >>>>> >>>>> It looks like the sole purpose of this driver is to provide the reset >>>>> lines to >>>>> pcie driver. >>>>> >>>>> I wonder why we need this ? Can't the pcie driver claim the reset lines >>>>> itself. >>>>> >>>>> Also, an init of this phy will always reset both port. What will happen >>>>> if the >>>>> first port is in use and the 2nd port comes up ?? >>>>> >>>>> Looks the the pcie driver should claim 'apb' and 'phy' reset lines as >>>>> "shared" >>>>> reset and the required 'port' as 'exclusive' >>>>> >>>> >>>> Thank you for your response. >>>> >>>> Yes, 'apb' and 'phy' reset lines are shared, and ‘port' reset line is >>>> exclusive. >>>> If we handle all reset lines during the first port initial sequence, >>>> and when the second port comes up, we will do nothing about the rest >>>> lines, >>>> and don't need a extra API to do ‘port' reset; >>> >>> With which other driver are your control shared ? >>> >>> Looks it is the answer is none since this phy driver will reset both port >>> already, even if one is used. >>> >>> In this case the fact that you are using shared control is just abusing the >>> framework to reset once. >>> >>> As far as I can tell, this driver makes no sense. The appropriate reset >>> lines >>> should be given directly to your pcie driver. >>> >>> >>> >>> . >>> >> >> Amlogic AXG SOC includes two pcie controllers and pipes when only one pcie >> phy: >> >> (port_a reset) >> |PCIE_RC_A>PCIE_PIPE_A--| >> (apb_reset) | | (phy reset) >> APB BUS---> | | PCIE_PHY >> | | >> | (port_b_reset)| >> |PCIE_RC_B>PCIE_PIPE_B--| >> >> The phy_reset affect the PCIE_PHY. >> The port_a_reset affect the PCIE_PIPE_A, port_b_reset affect the >> PCIE_PIPE_B. >> >> As your suggestion we will move the 'port' reset to controller driver, >> and keeping the phy driver to process the 'apb' and 'phy' reset or any >> more changes of the phy in future. > > As far as I can tell from this diagram, It would only make sense for the "phy" > reset line to be controlled by your phy driver. > > The apb and port is obviously related to the pcie device/driver itself, not > the > PHY. And whether you 1 or 2 reset lines in it, IMO it is overkill and > unnecessary to make a phy driver for this. > Yeah, that makes sense. We will move 'apb' reset to controller driver in next version too. Thanks. >> > > > . >
Re: [PATCH 2/2] PCI: meson: add the Amlogic Meson PCIe phy driver
On 2018/8/16 16:33, Jerome Brunet wrote: > On Thu, 2018-08-16 at 11:05 +0800, Hanjie Lin wrote: >> >> On 2018/8/14 18:41, Jerome Brunet wrote: >>> On Tue, 2018-08-14 at 02:12 -0400, Hanjie Lin wrote: >>>> From: Yue Wang >>>> >>>> The Meson-PCIE-PHY controller supports the 5-Gbps data rate >>>> of the PCI Express Gen 2 specification and is backwardcompatible >>>> with the 2.5-Gbps Gen 1.1 specification with only >>>> inferred idle detection supported on AMLOGIC SoCs. >>> >>> It looks like the sole purpose of this driver is to provide the reset lines >>> to >>> pcie driver. >>> >>> I wonder why we need this ? Can't the pcie driver claim the reset lines >>> itself. >>> >>> Also, an init of this phy will always reset both port. What will happen if >>> the >>> first port is in use and the 2nd port comes up ?? >>> >>> Looks the the pcie driver should claim 'apb' and 'phy' reset lines as >>> "shared" >>> reset and the required 'port' as 'exclusive' >>> >> >> Thank you for your response. >> >> Yes, 'apb' and 'phy' reset lines are shared, and ‘port' reset line is >> exclusive. >> If we handle all reset lines during the first port initial sequence, >> and when the second port comes up, we will do nothing about the rest lines, >> and don't need a extra API to do ‘port' reset; > > With which other driver are your control shared ? > > Looks it is the answer is none since this phy driver will reset both port > already, even if one is used. > > In this case the fact that you are using shared control is just abusing the > framework to reset once. > > As far as I can tell, this driver makes no sense. The appropriate reset lines > should be given directly to your pcie driver. > > > > . > Amlogic AXG SOC includes two pcie controllers and pipes when only one pcie phy: (port_a reset) |PCIE_RC_A>PCIE_PIPE_A--| (apb_reset) | | (phy reset) APB BUS---> | | PCIE_PHY | | | (port_b_reset)| |PCIE_RC_B>PCIE_PIPE_B--| The phy_reset affect the PCIE_PHY. The port_a_reset affect the PCIE_PIPE_A, port_b_reset affect the PCIE_PIPE_B. As your suggestion we will move the 'port' reset to controller driver, and keeping the phy driver to process the 'apb' and 'phy' reset or any more changes of the phy in future.
Re: [PATCH 2/2] PCI: meson: add the Amlogic Meson PCIe phy driver
On 2018/8/16 16:33, Jerome Brunet wrote: > On Thu, 2018-08-16 at 11:05 +0800, Hanjie Lin wrote: >> >> On 2018/8/14 18:41, Jerome Brunet wrote: >>> On Tue, 2018-08-14 at 02:12 -0400, Hanjie Lin wrote: >>>> From: Yue Wang >>>> >>>> The Meson-PCIE-PHY controller supports the 5-Gbps data rate >>>> of the PCI Express Gen 2 specification and is backwardcompatible >>>> with the 2.5-Gbps Gen 1.1 specification with only >>>> inferred idle detection supported on AMLOGIC SoCs. >>> >>> It looks like the sole purpose of this driver is to provide the reset lines >>> to >>> pcie driver. >>> >>> I wonder why we need this ? Can't the pcie driver claim the reset lines >>> itself. >>> >>> Also, an init of this phy will always reset both port. What will happen if >>> the >>> first port is in use and the 2nd port comes up ?? >>> >>> Looks the the pcie driver should claim 'apb' and 'phy' reset lines as >>> "shared" >>> reset and the required 'port' as 'exclusive' >>> >> >> Thank you for your response. >> >> Yes, 'apb' and 'phy' reset lines are shared, and ‘port' reset line is >> exclusive. >> If we handle all reset lines during the first port initial sequence, >> and when the second port comes up, we will do nothing about the rest lines, >> and don't need a extra API to do ‘port' reset; > > With which other driver are your control shared ? > > Looks it is the answer is none since this phy driver will reset both port > already, even if one is used. > > In this case the fact that you are using shared control is just abusing the > framework to reset once. > > As far as I can tell, this driver makes no sense. The appropriate reset lines > should be given directly to your pcie driver. > > > > . > Amlogic AXG SOC includes two pcie controllers and pipes when only one pcie phy: (port_a reset) |PCIE_RC_A>PCIE_PIPE_A--| (apb_reset) | | (phy reset) APB BUS---> | | PCIE_PHY | | | (port_b_reset)| |PCIE_RC_B>PCIE_PIPE_B--| The phy_reset affect the PCIE_PHY. The port_a_reset affect the PCIE_PIPE_A, port_b_reset affect the PCIE_PIPE_B. As your suggestion we will move the 'port' reset to controller driver, and keeping the phy driver to process the 'apb' and 'phy' reset or any more changes of the phy in future.
Re: [PATCH 2/2] PCI: meson: add the Amlogic Meson PCIe controller driver
On 2018/8/14 18:41, Jerome Brunet wrote: > On Tue, 2018-08-14 at 02:18 -0400, Hanjie Lin wrote: >> From: Yue Wang >> >> The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare >> PCI core. This patch adds the driver support for Meson PCIe controller. >> >> Signed-off-by: Yue Wang >> Signed-off-by: Hanjie Lin >> --- >> drivers/pci/controller/dwc/Kconfig | 12 + >> drivers/pci/controller/dwc/Makefile| 1 + >> drivers/pci/controller/dwc/pci-meson.c | 588 >> + >> 3 files changed, 601 insertions(+) >> create mode 100644 drivers/pci/controller/dwc/pci-meson.c >> >> diff --git a/drivers/pci/controller/dwc/Kconfig >> b/drivers/pci/controller/dwc/Kconfig >> index 91b0194..6cb36f6 100644 >> --- a/drivers/pci/controller/dwc/Kconfig >> +++ b/drivers/pci/controller/dwc/Kconfig >> @@ -193,4 +193,16 @@ config PCIE_HISI_STB >> help >>Say Y here if you want PCIe controller support on HiSilicon STB >> SoCs >> >> +config PCI_MESON >> +bool "MESON PCIe controller" >> +depends on PCI >> +depends on PCI_MSI_IRQ_DOMAIN >> +select PCIEPORTBUS >> +select PCIE_DW_HOST >> +help >> + Say Y here if you want to enable PCI controller support on Amlogic >> + SoCs. The PCI controller on Amlogic is based on DesignWare hardware >> + and therefore the driver re-uses the DesignWare core functions to >> + implement the driver. >> + >> endmenu >> diff --git a/drivers/pci/controller/dwc/Makefile >> b/drivers/pci/controller/dwc/Makefile >> index 5d2ce72..cf676bd 100644 >> --- a/drivers/pci/controller/dwc/Makefile >> +++ b/drivers/pci/controller/dwc/Makefile >> @@ -14,6 +14,7 @@ obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o >> obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o >> obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o >> obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o >> +obj-$(CONFIG_PCI_MESON) += pci-meson.o >> >> # The following drivers are for devices that use the generic ACPI >> # pci_root.c driver but don't support standard ECAM config access. >> diff --git a/drivers/pci/controller/dwc/pci-meson.c >> b/drivers/pci/controller/dwc/pci-meson.c >> new file mode 100644 >> index 000..1e96e45 >> --- /dev/null >> +++ b/drivers/pci/controller/dwc/pci-meson.c >> @@ -0,0 +1,588 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * PCIe host controller driver for Amlogic MESON SoCs >> + * >> + * Copyright (c) 2018 Amlogic, inc. >> + * Author: Yue Wang >> + */ >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> + >> +#include "pcie-designware.h" >> + >> +#define to_meson_pcie(x) dev_get_drvdata((x)->dev) >> + >> +/* External local bus interface registers */ >> +#define PLR_OFFSET 0x700 >> +#define PCIE_PORT_LINK_CTRL_OFF (PLR_OFFSET + 0x10) >> +#define FAST_LINK_MODE BIT(7) >> +#define LINK_CAPABLE_MASK GENMASK(21, 16) >> +#define LINK_CAPABLE_X1 BIT(16) >> + >> +#define PCIE_GEN2_CTRL_OFF (PLR_OFFSET + 0x10c) >> +#define NUM_OF_LANES_MASK GENMASK(12, 8) >> +#define NUM_OF_LANES_X1 BIT(8) >> +#define DIRECT_SPEED_CHANGE BIT(17) >> + >> +#define TYPE1_HDR_OFFSET0x0 >> +#define PCIE_STATUS_COMMAND (TYPE1_HDR_OFFSET + 0x04) >> +#define PCI_IO_EN BIT(0) >> +#define PCI_MEM_SPACE_ENBIT(1) >> +#define PCI_BUS_MASTER_EN BIT(2) >> + >> +#define PCIE_BASE_ADDR0 (TYPE1_HDR_OFFSET + 0x10) >> +#define PCIE_BASE_ADDR1 (TYPE1_HDR_OFFSET + 0x14) >> + >> +#define PCIE_CAP_OFFSET 0x70 >> +#define PCIE_DEV_CTRL_DEV_STUS (PCIE_CAP_OFFSET + 0x08) >> +#define PCIE_CAP_MAX_PAYLOAD_MASK GENMASK(7, 5) >> +#define PCIE_CAP_MAX_PAYLOAD_SIZE(x)((x) << 5) >> +#define PCIE_CAP_MAX_READ_REQ_MASK GENMASK(14, 12) >> +#define PCIE_CAP_MAX_READ_REQ_SIZE(x) ((x) << 12) >> + >> +#define PCI_CLASS_REVISION_MASK GENMASK(7, 0) >> + >> +/* PCIe specific config registers */ >> +#define PCIE_CFG0 0x0 >> +#define APP_LTSSM_ENABLEBIT(7) >> + &
Re: [PATCH 2/2] PCI: meson: add the Amlogic Meson PCIe controller driver
On 2018/8/14 18:41, Jerome Brunet wrote: > On Tue, 2018-08-14 at 02:18 -0400, Hanjie Lin wrote: >> From: Yue Wang >> >> The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare >> PCI core. This patch adds the driver support for Meson PCIe controller. >> >> Signed-off-by: Yue Wang >> Signed-off-by: Hanjie Lin >> --- >> drivers/pci/controller/dwc/Kconfig | 12 + >> drivers/pci/controller/dwc/Makefile| 1 + >> drivers/pci/controller/dwc/pci-meson.c | 588 >> + >> 3 files changed, 601 insertions(+) >> create mode 100644 drivers/pci/controller/dwc/pci-meson.c >> >> diff --git a/drivers/pci/controller/dwc/Kconfig >> b/drivers/pci/controller/dwc/Kconfig >> index 91b0194..6cb36f6 100644 >> --- a/drivers/pci/controller/dwc/Kconfig >> +++ b/drivers/pci/controller/dwc/Kconfig >> @@ -193,4 +193,16 @@ config PCIE_HISI_STB >> help >>Say Y here if you want PCIe controller support on HiSilicon STB >> SoCs >> >> +config PCI_MESON >> +bool "MESON PCIe controller" >> +depends on PCI >> +depends on PCI_MSI_IRQ_DOMAIN >> +select PCIEPORTBUS >> +select PCIE_DW_HOST >> +help >> + Say Y here if you want to enable PCI controller support on Amlogic >> + SoCs. The PCI controller on Amlogic is based on DesignWare hardware >> + and therefore the driver re-uses the DesignWare core functions to >> + implement the driver. >> + >> endmenu >> diff --git a/drivers/pci/controller/dwc/Makefile >> b/drivers/pci/controller/dwc/Makefile >> index 5d2ce72..cf676bd 100644 >> --- a/drivers/pci/controller/dwc/Makefile >> +++ b/drivers/pci/controller/dwc/Makefile >> @@ -14,6 +14,7 @@ obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o >> obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o >> obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o >> obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o >> +obj-$(CONFIG_PCI_MESON) += pci-meson.o >> >> # The following drivers are for devices that use the generic ACPI >> # pci_root.c driver but don't support standard ECAM config access. >> diff --git a/drivers/pci/controller/dwc/pci-meson.c >> b/drivers/pci/controller/dwc/pci-meson.c >> new file mode 100644 >> index 000..1e96e45 >> --- /dev/null >> +++ b/drivers/pci/controller/dwc/pci-meson.c >> @@ -0,0 +1,588 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * PCIe host controller driver for Amlogic MESON SoCs >> + * >> + * Copyright (c) 2018 Amlogic, inc. >> + * Author: Yue Wang >> + */ >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> + >> +#include "pcie-designware.h" >> + >> +#define to_meson_pcie(x) dev_get_drvdata((x)->dev) >> + >> +/* External local bus interface registers */ >> +#define PLR_OFFSET 0x700 >> +#define PCIE_PORT_LINK_CTRL_OFF (PLR_OFFSET + 0x10) >> +#define FAST_LINK_MODE BIT(7) >> +#define LINK_CAPABLE_MASK GENMASK(21, 16) >> +#define LINK_CAPABLE_X1 BIT(16) >> + >> +#define PCIE_GEN2_CTRL_OFF (PLR_OFFSET + 0x10c) >> +#define NUM_OF_LANES_MASK GENMASK(12, 8) >> +#define NUM_OF_LANES_X1 BIT(8) >> +#define DIRECT_SPEED_CHANGE BIT(17) >> + >> +#define TYPE1_HDR_OFFSET0x0 >> +#define PCIE_STATUS_COMMAND (TYPE1_HDR_OFFSET + 0x04) >> +#define PCI_IO_EN BIT(0) >> +#define PCI_MEM_SPACE_ENBIT(1) >> +#define PCI_BUS_MASTER_EN BIT(2) >> + >> +#define PCIE_BASE_ADDR0 (TYPE1_HDR_OFFSET + 0x10) >> +#define PCIE_BASE_ADDR1 (TYPE1_HDR_OFFSET + 0x14) >> + >> +#define PCIE_CAP_OFFSET 0x70 >> +#define PCIE_DEV_CTRL_DEV_STUS (PCIE_CAP_OFFSET + 0x08) >> +#define PCIE_CAP_MAX_PAYLOAD_MASK GENMASK(7, 5) >> +#define PCIE_CAP_MAX_PAYLOAD_SIZE(x)((x) << 5) >> +#define PCIE_CAP_MAX_READ_REQ_MASK GENMASK(14, 12) >> +#define PCIE_CAP_MAX_READ_REQ_SIZE(x) ((x) << 12) >> + >> +#define PCI_CLASS_REVISION_MASK GENMASK(7, 0) >> + >> +/* PCIe specific config registers */ >> +#define PCIE_CFG0 0x0 >> +#define APP_LTSSM_ENABLEBIT(7) >> + &
Re: [PATCH 1/2] dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller
On 2018/8/15 6:53, Rob Herring wrote:
> On Tue, Aug 14, 2018 at 02:18:41AM -0400, Hanjie Lin wrote:
>> From: Yue Wang
>>
>> The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare
>> PCI core. This patch adds documentation for the DT bindings in Meson PCIe
>> controller.
>>
>> Signed-off-by: Yue Wang
>> Signed-off-by: Hanjie Lin
>> ---
>> .../devicetree/bindings/pci/amlogic,meson-pcie.txt | 57
>> ++
>> 1 file changed, 57 insertions(+)
>> create mode 100644
>> Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
>>
>> diff --git a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
>> b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
>> new file mode 100644
>> index 000..48233e4
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
>> @@ -0,0 +1,57 @@
>> +Amlogic Meson AXG DWC PCIE SoC controller
>> +
>> +Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI
>> core.
>> +It shares common functions with the PCIe DesignWare core driver and
>> +inherits common properties defined in
>> +Documentation/devicetree/bindings/pci/designware-pci.txt.
>> +
>> +Additional properties are described here:
>> +
>> +Required properties:
>> +- compatible:
>> +should contain "amlogic,axg-pcie" to identify the core.
>> +- reg:
>> +Should contain the configuration address space.
>> +- reg-names: Must be
>> +- "elbi"External local bus interface registers
>> +- "cfg" Meson specific registers
>> +- "config" PCIe configuration space
>> +- clocks: Must contain an entry for each entry in clock-names.
>> +- clock-names: Must include the following entries:
>> +- "pcie"
>> +- "pcie_bus"
>> +- "pcie_general"
>> +- "pcie_mipi_en"
>> +
>> +Example configuration:
>> +
>> +pcie: pcie@d000 {
>
> Unit-address is wrong.
Yes, I will fix it.
>
>> +compatible = "amlogic,axg-pcie", "snps,dw-pcie";
>> +reg = <0x0 0xf980 0x0 0x40
>> +0x0 0xff646000 0x0 0x2000
>> +0x0 0xf9f0 0x0 0x10>;
>> +reg-names = "elbi", "cfg", "config";
>> +reset-gpio = < GPIOX_19 GPIO_ACTIVE_HIGH>;
>
> Not documented and should be reset-gpios.
Yes, is this more clear?
reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
>
>> +interrupts = <0 177 IRQ_TYPE_EDGE_RISING>;
>> +#interrupt-cells = <1>;
>> +interrupt-map-mask = <0 0 0 0>;
>> +interrupt-map = <0 0 0 0 GIC_SPI 179
>> IRQ_TYPE_EDGE_RISING>;
>> +bus-range = <0x0 0xff>;
>> +#address-cells = <3>;
>> +#size-cells = <2>;
>> +device_type = "pci";
>> +phys = <_phy>;
>> +ranges = <0x8200 0 0 0x0 0xf9c0 0 0x0030>;
>> +num-lanes = <1>;
>> +pcie-num = <1>;
>
> Not documented. What's this?
Yes, pcie-num is an useless parameter. I will delete it.
Thanks for your comments.
>
>> +
>> +clocks = < CLKID_USB
>> + CLKID_MIPI_ENABLE
>> + CLKID_PCIE_A
>> + CLKID_PCIE_CML_EN0>;
>> +clock-names = "pcie_general",
>> +"pcie_refpll",
>> +"pcie_mipi_en",
>> +"pcie",
>> +"port";
>> +};
>> --
>> 2.7.4
>>
>
> .
>
Re: [PATCH 1/2] dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller
On 2018/8/15 6:53, Rob Herring wrote:
> On Tue, Aug 14, 2018 at 02:18:41AM -0400, Hanjie Lin wrote:
>> From: Yue Wang
>>
>> The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare
>> PCI core. This patch adds documentation for the DT bindings in Meson PCIe
>> controller.
>>
>> Signed-off-by: Yue Wang
>> Signed-off-by: Hanjie Lin
>> ---
>> .../devicetree/bindings/pci/amlogic,meson-pcie.txt | 57
>> ++
>> 1 file changed, 57 insertions(+)
>> create mode 100644
>> Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
>>
>> diff --git a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
>> b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
>> new file mode 100644
>> index 000..48233e4
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
>> @@ -0,0 +1,57 @@
>> +Amlogic Meson AXG DWC PCIE SoC controller
>> +
>> +Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI
>> core.
>> +It shares common functions with the PCIe DesignWare core driver and
>> +inherits common properties defined in
>> +Documentation/devicetree/bindings/pci/designware-pci.txt.
>> +
>> +Additional properties are described here:
>> +
>> +Required properties:
>> +- compatible:
>> +should contain "amlogic,axg-pcie" to identify the core.
>> +- reg:
>> +Should contain the configuration address space.
>> +- reg-names: Must be
>> +- "elbi"External local bus interface registers
>> +- "cfg" Meson specific registers
>> +- "config" PCIe configuration space
>> +- clocks: Must contain an entry for each entry in clock-names.
>> +- clock-names: Must include the following entries:
>> +- "pcie"
>> +- "pcie_bus"
>> +- "pcie_general"
>> +- "pcie_mipi_en"
>> +
>> +Example configuration:
>> +
>> +pcie: pcie@d000 {
>
> Unit-address is wrong.
Yes, I will fix it.
>
>> +compatible = "amlogic,axg-pcie", "snps,dw-pcie";
>> +reg = <0x0 0xf980 0x0 0x40
>> +0x0 0xff646000 0x0 0x2000
>> +0x0 0xf9f0 0x0 0x10>;
>> +reg-names = "elbi", "cfg", "config";
>> +reset-gpio = < GPIOX_19 GPIO_ACTIVE_HIGH>;
>
> Not documented and should be reset-gpios.
Yes, is this more clear?
reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
>
>> +interrupts = <0 177 IRQ_TYPE_EDGE_RISING>;
>> +#interrupt-cells = <1>;
>> +interrupt-map-mask = <0 0 0 0>;
>> +interrupt-map = <0 0 0 0 GIC_SPI 179
>> IRQ_TYPE_EDGE_RISING>;
>> +bus-range = <0x0 0xff>;
>> +#address-cells = <3>;
>> +#size-cells = <2>;
>> +device_type = "pci";
>> +phys = <_phy>;
>> +ranges = <0x8200 0 0 0x0 0xf9c0 0 0x0030>;
>> +num-lanes = <1>;
>> +pcie-num = <1>;
>
> Not documented. What's this?
Yes, pcie-num is an useless parameter. I will delete it.
Thanks for your comments.
>
>> +
>> +clocks = < CLKID_USB
>> + CLKID_MIPI_ENABLE
>> + CLKID_PCIE_A
>> + CLKID_PCIE_CML_EN0>;
>> +clock-names = "pcie_general",
>> +"pcie_refpll",
>> +"pcie_mipi_en",
>> +"pcie",
>> +"port";
>> +};
>> --
>> 2.7.4
>>
>
> .
>
Re: [PATCH 1/2] dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller
On 2018/8/14 18:41, Jerome Brunet wrote:
> On Tue, 2018-08-14 at 02:18 -0400, Hanjie Lin wrote:
>> From: Yue Wang
>>
>> The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare
>> PCI core. This patch adds documentation for the DT bindings in Meson PCIe
>> controller.
>>
>> Signed-off-by: Yue Wang
>> Signed-off-by: Hanjie Lin
>> ---
>> .../devicetree/bindings/pci/amlogic,meson-pcie.txt | 57
>> ++
>> 1 file changed, 57 insertions(+)
>> create mode 100644
>> Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
>>
>> diff --git a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
>> b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
>> new file mode 100644
>> index 000..48233e4
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
>> @@ -0,0 +1,57 @@
>> +Amlogic Meson AXG DWC PCIE SoC controller
>> +
>> +Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI
>> core.
>> +It shares common functions with the PCIe DesignWare core driver and
>> +inherits common properties defined in
>> +Documentation/devicetree/bindings/pci/designware-pci.txt.
>> +
>> +Additional properties are described here:
>> +
>> +Required properties:
>> +- compatible:
>> +should contain "amlogic,axg-pcie" to identify the core.
>> +- reg:
>> +Should contain the configuration address space.
>> +- reg-names: Must be
>> +- "elbi"External local bus interface registers
>> +- "cfg" Meson specific registers
>> +- "config" PCIe configuration space
>> +- clocks: Must contain an entry for each entry in clock-names.
>> +- clock-names: Must include the following entries:
>> +- "pcie"
>> +- "pcie_bus"
>> +- "pcie_general"
>> +- "pcie_mipi_en"
>
> Could you briefly describe what each clock is needed for ?
>
Yes, is this more clear?
- clock-names: Amlogic Meson AXG
Usage: required for
Value type:
Definition: Should contain the following entries
- "pclk" PCIe GEN 100M PLL clock
- "port" PCIe_x(A 0r B) RC clock gate
- "general"PCIe Phy clock
- "mipi" PCIe_x(A or B) 100M ref clock gate
>> +
>> +Example configuration:
>> +
>> +pcie: pcie@d000 {
>> +compatible = "amlogic,axg-pcie", "snps,dw-pcie";
>> +reg = <0x0 0xf980 0x0 0x40
>> +0x0 0xff646000 0x0 0x2000
>> +0x0 0xf9f0 0x0 0x10>;
>> +reg-names = "elbi", "cfg", "config";
>> +reset-gpio = < GPIOX_19 GPIO_ACTIVE_HIGH>;
>> +interrupts = <0 177 IRQ_TYPE_EDGE_RISING>;
>
> replace 0 with GIC_SPI please
Right, I will fix it.
>
>> +#interrupt-cells = <1>;
>> +interrupt-map-mask = <0 0 0 0>;
>> +interrupt-map = <0 0 0 0 GIC_SPI 179
>> IRQ_TYPE_EDGE_RISING>;
>> +bus-range = <0x0 0xff>;
>> +#address-cells = <3>;
>> +#size-cells = <2>;
>> +device_type = "pci";
>> +phys = <_phy>;
>> +ranges = <0x8200 0 0 0x0 0xf9c0 0 0x0030>;
>> +num-lanes = <1>;
>> +pcie-num = <1>;
>> +
>> +clocks = < CLKID_USB
>> + CLKID_MIPI_ENABLE
>> + CLKID_PCIE_A
>> + CLKID_PCIE_CML_EN0>;
>> +clock-names = "pcie_general",
>> +"pcie_refpll",
>> +"pcie_mipi_en",
>> +"pcie",
>> +"port";
>
> Several things are disturbing above:
> * pcie_general is provided by the USB clock gate ???
> * pcie_refpll: I suppose this is a copy/paste error, not used in your driver
> (and shouldn't be need BTW)
>
> suggested names:
> * pcie_general -> general
> * pcie_mipi_en -> mipi
> * pcie -> pclk
> * port (OK)
>
Thanks, we will follow your suggestion.
>> +};
>
>
> .
>
Re: [PATCH 1/2] dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller
On 2018/8/14 18:41, Jerome Brunet wrote:
> On Tue, 2018-08-14 at 02:18 -0400, Hanjie Lin wrote:
>> From: Yue Wang
>>
>> The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare
>> PCI core. This patch adds documentation for the DT bindings in Meson PCIe
>> controller.
>>
>> Signed-off-by: Yue Wang
>> Signed-off-by: Hanjie Lin
>> ---
>> .../devicetree/bindings/pci/amlogic,meson-pcie.txt | 57
>> ++
>> 1 file changed, 57 insertions(+)
>> create mode 100644
>> Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
>>
>> diff --git a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
>> b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
>> new file mode 100644
>> index 000..48233e4
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
>> @@ -0,0 +1,57 @@
>> +Amlogic Meson AXG DWC PCIE SoC controller
>> +
>> +Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI
>> core.
>> +It shares common functions with the PCIe DesignWare core driver and
>> +inherits common properties defined in
>> +Documentation/devicetree/bindings/pci/designware-pci.txt.
>> +
>> +Additional properties are described here:
>> +
>> +Required properties:
>> +- compatible:
>> +should contain "amlogic,axg-pcie" to identify the core.
>> +- reg:
>> +Should contain the configuration address space.
>> +- reg-names: Must be
>> +- "elbi"External local bus interface registers
>> +- "cfg" Meson specific registers
>> +- "config" PCIe configuration space
>> +- clocks: Must contain an entry for each entry in clock-names.
>> +- clock-names: Must include the following entries:
>> +- "pcie"
>> +- "pcie_bus"
>> +- "pcie_general"
>> +- "pcie_mipi_en"
>
> Could you briefly describe what each clock is needed for ?
>
Yes, is this more clear?
- clock-names: Amlogic Meson AXG
Usage: required for
Value type:
Definition: Should contain the following entries
- "pclk" PCIe GEN 100M PLL clock
- "port" PCIe_x(A 0r B) RC clock gate
- "general"PCIe Phy clock
- "mipi" PCIe_x(A or B) 100M ref clock gate
>> +
>> +Example configuration:
>> +
>> +pcie: pcie@d000 {
>> +compatible = "amlogic,axg-pcie", "snps,dw-pcie";
>> +reg = <0x0 0xf980 0x0 0x40
>> +0x0 0xff646000 0x0 0x2000
>> +0x0 0xf9f0 0x0 0x10>;
>> +reg-names = "elbi", "cfg", "config";
>> +reset-gpio = < GPIOX_19 GPIO_ACTIVE_HIGH>;
>> +interrupts = <0 177 IRQ_TYPE_EDGE_RISING>;
>
> replace 0 with GIC_SPI please
Right, I will fix it.
>
>> +#interrupt-cells = <1>;
>> +interrupt-map-mask = <0 0 0 0>;
>> +interrupt-map = <0 0 0 0 GIC_SPI 179
>> IRQ_TYPE_EDGE_RISING>;
>> +bus-range = <0x0 0xff>;
>> +#address-cells = <3>;
>> +#size-cells = <2>;
>> +device_type = "pci";
>> +phys = <_phy>;
>> +ranges = <0x8200 0 0 0x0 0xf9c0 0 0x0030>;
>> +num-lanes = <1>;
>> +pcie-num = <1>;
>> +
>> +clocks = < CLKID_USB
>> + CLKID_MIPI_ENABLE
>> + CLKID_PCIE_A
>> + CLKID_PCIE_CML_EN0>;
>> +clock-names = "pcie_general",
>> +"pcie_refpll",
>> +"pcie_mipi_en",
>> +"pcie",
>> +"port";
>
> Several things are disturbing above:
> * pcie_general is provided by the USB clock gate ???
> * pcie_refpll: I suppose this is a copy/paste error, not used in your driver
> (and shouldn't be need BTW)
>
> suggested names:
> * pcie_general -> general
> * pcie_mipi_en -> mipi
> * pcie -> pclk
> * port (OK)
>
Thanks, we will follow your suggestion.
>> +};
>
>
> .
>
Re: [PATCH 2/2] PCI: meson: add the Amlogic Meson PCIe phy driver
On 2018/8/14 18:41, Jerome Brunet wrote:
> On Tue, 2018-08-14 at 02:12 -0400, Hanjie Lin wrote:
>> From: Yue Wang
>>
>> The Meson-PCIE-PHY controller supports the 5-Gbps data rate
>> of the PCI Express Gen 2 specification and is backwardcompatible
>> with the 2.5-Gbps Gen 1.1 specification with only
>> inferred idle detection supported on AMLOGIC SoCs.
>
> It looks like the sole purpose of this driver is to provide the reset lines to
> pcie driver.
>
> I wonder why we need this ? Can't the pcie driver claim the reset lines
> itself.
>
> Also, an init of this phy will always reset both port. What will happen if the
> first port is in use and the 2nd port comes up ??
>
> Looks the the pcie driver should claim 'apb' and 'phy' reset lines as "shared"
> reset and the required 'port' as 'exclusive'
>
Thank you for your response.
Yes, 'apb' and 'phy' reset lines are shared, and ‘port' reset line is exclusive.
If we handle all reset lines during the first port initial sequence,
and when the second port comes up, we will do nothing about the rest lines,
and don't need a extra API to do ‘port' reset;
>>
>> Signed-off-by: Yue Wang
>> Signed-off-by: Hanjie Lin
>> ---
>> drivers/phy/amlogic/Kconfig | 8 ++
>> drivers/phy/amlogic/Makefile | 1 +
>> drivers/phy/amlogic/phy-meson-axg-pcie.c | 160
>> +++
>> 3 files changed, 169 insertions(+)
>> create mode 100644 drivers/phy/amlogic/phy-meson-axg-pcie.c
>>
>> diff --git a/drivers/phy/amlogic/Kconfig b/drivers/phy/amlogic/Kconfig
>> index 23fe1cd..3ab07f9 100644
>> --- a/drivers/phy/amlogic/Kconfig
>> +++ b/drivers/phy/amlogic/Kconfig
>> @@ -36,3 +36,11 @@ config PHY_MESON_GXL_USB3
>>Enable this to support the Meson USB3 PHY and OTG detection
>>IP block found in Meson GXL and GXM SoCs.
>>If unsure, say N.
>> +
>> +config PHY_MESON_AXG_PCIE
>> +bool "Meson AXG PCIe PHY driver"
>> +depends on OF && (ARCH_MESON || COMPILE_TEST)
>> +select GENERIC_PHY
>> +help
>> + Enable PCIe PHY support for Meson AXG SoC series.
>> + This driver provides PHY interface for Meson PCIe controller.
>> \ No newline at end of file
>> diff --git a/drivers/phy/amlogic/Makefile b/drivers/phy/amlogic/Makefile
>> index 4fd8848..5ab8578 100644
>> --- a/drivers/phy/amlogic/Makefile
>> +++ b/drivers/phy/amlogic/Makefile
>> @@ -1,3 +1,4 @@
>> obj-$(CONFIG_PHY_MESON8B_USB2) += phy-meson8b-usb2.o
>> obj-$(CONFIG_PHY_MESON_GXL_USB2)+= phy-meson-gxl-usb2.o
>> obj-$(CONFIG_PHY_MESON_GXL_USB3)+= phy-meson-gxl-usb3.o
>> +obj-$(CONFIG_PHY_MESON_AXG_PCIE)+= phy-meson-axg-pcie.o
>> diff --git a/drivers/phy/amlogic/phy-meson-axg-pcie.c
>> b/drivers/phy/amlogic/phy-meson-axg-pcie.c
>> new file mode 100644
>> index 000..8bc5c49
>> --- /dev/null
>> +++ b/drivers/phy/amlogic/phy-meson-axg-pcie.c
>> @@ -0,0 +1,160 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
>> +/*
>> + * Amlogic MESON SoC series PCIe PHY driver
>> + *
>> + * Phy provider for PCIe controller on MESON SoC series
>> + *
>> + * Copyright (c) 2018 Amlogic, inc.
>> + * Yue Wang
>> + */
>> +
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +
>> +struct meson_pcie_phy_data {
>> +const struct phy_ops*ops;
>> +};
>> +
>> +struct meson_pcie_reset {
>> +struct reset_control*port_a;
>> +struct reset_control*port_b;
>> +struct reset_control*phy;
>> +struct reset_control*apb;
>> +};
>> +
>> +struct meson_pcie_phy {
>> +const struct meson_pcie_phy_data*data;
>> +struct meson_pcie_reset reset;
>> +void __iomem*phy_base;
>> +};
>> +
>> +static int meson_pcie_phy_init(struct phy *phy)
>> +{
>> +struct meson_pcie_phy *mphy = phy_get_drvdata(phy);
>> +struct meson_pcie_reset *mrst = >reset;
>> +
>> +writel(0x1c, mphy->phy_base);
>> +reset_control_assert(mrst->port_a);
>> +reset_control_assert(mrst->port_b);
>> +reset_control_assert(mrst->phy);
>> +reset_control_assert(mrst->apb);
>> +udelay(400);
>> +reset_control_deassert(mrst->port_a);
>> +reset_control_deassert(mrst->port_b);
>> +reset_control_deassert(mrst->phy);
>> +reset_control_deassert(mrst->apb);
>
Re: [PATCH 2/2] PCI: meson: add the Amlogic Meson PCIe phy driver
On 2018/8/14 18:41, Jerome Brunet wrote:
> On Tue, 2018-08-14 at 02:12 -0400, Hanjie Lin wrote:
>> From: Yue Wang
>>
>> The Meson-PCIE-PHY controller supports the 5-Gbps data rate
>> of the PCI Express Gen 2 specification and is backwardcompatible
>> with the 2.5-Gbps Gen 1.1 specification with only
>> inferred idle detection supported on AMLOGIC SoCs.
>
> It looks like the sole purpose of this driver is to provide the reset lines to
> pcie driver.
>
> I wonder why we need this ? Can't the pcie driver claim the reset lines
> itself.
>
> Also, an init of this phy will always reset both port. What will happen if the
> first port is in use and the 2nd port comes up ??
>
> Looks the the pcie driver should claim 'apb' and 'phy' reset lines as "shared"
> reset and the required 'port' as 'exclusive'
>
Thank you for your response.
Yes, 'apb' and 'phy' reset lines are shared, and ‘port' reset line is exclusive.
If we handle all reset lines during the first port initial sequence,
and when the second port comes up, we will do nothing about the rest lines,
and don't need a extra API to do ‘port' reset;
>>
>> Signed-off-by: Yue Wang
>> Signed-off-by: Hanjie Lin
>> ---
>> drivers/phy/amlogic/Kconfig | 8 ++
>> drivers/phy/amlogic/Makefile | 1 +
>> drivers/phy/amlogic/phy-meson-axg-pcie.c | 160
>> +++
>> 3 files changed, 169 insertions(+)
>> create mode 100644 drivers/phy/amlogic/phy-meson-axg-pcie.c
>>
>> diff --git a/drivers/phy/amlogic/Kconfig b/drivers/phy/amlogic/Kconfig
>> index 23fe1cd..3ab07f9 100644
>> --- a/drivers/phy/amlogic/Kconfig
>> +++ b/drivers/phy/amlogic/Kconfig
>> @@ -36,3 +36,11 @@ config PHY_MESON_GXL_USB3
>>Enable this to support the Meson USB3 PHY and OTG detection
>>IP block found in Meson GXL and GXM SoCs.
>>If unsure, say N.
>> +
>> +config PHY_MESON_AXG_PCIE
>> +bool "Meson AXG PCIe PHY driver"
>> +depends on OF && (ARCH_MESON || COMPILE_TEST)
>> +select GENERIC_PHY
>> +help
>> + Enable PCIe PHY support for Meson AXG SoC series.
>> + This driver provides PHY interface for Meson PCIe controller.
>> \ No newline at end of file
>> diff --git a/drivers/phy/amlogic/Makefile b/drivers/phy/amlogic/Makefile
>> index 4fd8848..5ab8578 100644
>> --- a/drivers/phy/amlogic/Makefile
>> +++ b/drivers/phy/amlogic/Makefile
>> @@ -1,3 +1,4 @@
>> obj-$(CONFIG_PHY_MESON8B_USB2) += phy-meson8b-usb2.o
>> obj-$(CONFIG_PHY_MESON_GXL_USB2)+= phy-meson-gxl-usb2.o
>> obj-$(CONFIG_PHY_MESON_GXL_USB3)+= phy-meson-gxl-usb3.o
>> +obj-$(CONFIG_PHY_MESON_AXG_PCIE)+= phy-meson-axg-pcie.o
>> diff --git a/drivers/phy/amlogic/phy-meson-axg-pcie.c
>> b/drivers/phy/amlogic/phy-meson-axg-pcie.c
>> new file mode 100644
>> index 000..8bc5c49
>> --- /dev/null
>> +++ b/drivers/phy/amlogic/phy-meson-axg-pcie.c
>> @@ -0,0 +1,160 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
>> +/*
>> + * Amlogic MESON SoC series PCIe PHY driver
>> + *
>> + * Phy provider for PCIe controller on MESON SoC series
>> + *
>> + * Copyright (c) 2018 Amlogic, inc.
>> + * Yue Wang
>> + */
>> +
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +
>> +struct meson_pcie_phy_data {
>> +const struct phy_ops*ops;
>> +};
>> +
>> +struct meson_pcie_reset {
>> +struct reset_control*port_a;
>> +struct reset_control*port_b;
>> +struct reset_control*phy;
>> +struct reset_control*apb;
>> +};
>> +
>> +struct meson_pcie_phy {
>> +const struct meson_pcie_phy_data*data;
>> +struct meson_pcie_reset reset;
>> +void __iomem*phy_base;
>> +};
>> +
>> +static int meson_pcie_phy_init(struct phy *phy)
>> +{
>> +struct meson_pcie_phy *mphy = phy_get_drvdata(phy);
>> +struct meson_pcie_reset *mrst = >reset;
>> +
>> +writel(0x1c, mphy->phy_base);
>> +reset_control_assert(mrst->port_a);
>> +reset_control_assert(mrst->port_b);
>> +reset_control_assert(mrst->phy);
>> +reset_control_assert(mrst->apb);
>> +udelay(400);
>> +reset_control_deassert(mrst->port_a);
>> +reset_control_deassert(mrst->port_b);
>> +reset_control_deassert(mrst->phy);
>> +reset_control_deassert(mrst->apb);
>
Re: [PATCH 1/2] dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe Phy controller
On 2018/8/15 6:50, Rob Herring wrote:
> On Tue, Aug 14, 2018 at 02:12:13AM -0400, Hanjie Lin wrote:
>> From: Yue Wang
>
> Subject should be "dt-bindings: phy: ..."
>
>> The Meson-PCIE-PHY controller supports the 5-Gbps data rate
>> of the PCI Express Gen 2 specification and is backwardcompatible
>
> space
yes, I will fix
^
>
>> with the 2.5-Gbps Gen 1.1 specification with only
>> inferred idle detection supported on AMLOGIC SoCs.
>
> AMLOGIC or Amlogic?
>
yes, we will stick to 'Amlogic'
>>
>> Signed-off-by: Hanjie Lin
>> Signed-off-by: Yue Wang
>> ---
>> .../bindings/phy/amlogic,meson-pcie-phy.txt| 31
>> ++
>> 1 file changed, 31 insertions(+)
>> create mode 100644
>> Documentation/devicetree/bindings/phy/amlogic,meson-pcie-phy.txt
>>
>> diff --git
>> a/Documentation/devicetree/bindings/phy/amlogic,meson-pcie-phy.txt
>> b/Documentation/devicetree/bindings/phy/amlogic,meson-pcie-phy.txt
>> new file mode 100644
>> index 000..db99085
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/phy/amlogic,meson-pcie-phy.txt
>> @@ -0,0 +1,31 @@
>> +* Amlogic Meson AXG PCIE PHY binding
>> +
>> +Required properties:
>> +- compatible: Should be
>> +- "amlogic,axg-pcie-phy"
>> +- #phys-cells: must be 0 (see phy-bindings.txt in this directory)
>
> You don't need to distinguish port A and B?
No, we don't. Theoretically there is only one phy in the chip,
and we have distinguished ports by reset lines.
Thanks for all corrections and suggestions.
>
>> +- reg: The base address and length of the registers
>> +- resets: phandle to the reset lines
>> +- reset-names: must contain "phy" and "peripheral"
>> +- "port_a" Port A reset
>> +- "port_b" Port B reset
>> +- "phy" PHY reset
>> +- "apb" APB reset
>> +Optional properties:
>> +- phy-supply: see phy-bindings.txt in this directory
>> +
>> +Example:
>> +pcie_phy: pcie-phy@ff644000 {
>> +#phy-cells = <0>;
>> +compatible = "amlogic,axg-pcie-phy";
>> +reg = <0x0 0xff644000 0x0 0x2000>;
>> +resets = < RESET_PCIE_A>,
>> +< RESET_PCIE_B>,
>> +< RESET_PCIE_PHY>,
>> +< RESET_PCIE_APB>;
>> +reset-names =
>> +"port_a",
>> +"port_b",
>> +"phy",
>> +"apb";
>> +};
>> --
>> 2.7.4
>>
>
> .
>
Re: [PATCH 1/2] dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe Phy controller
On 2018/8/15 6:50, Rob Herring wrote:
> On Tue, Aug 14, 2018 at 02:12:13AM -0400, Hanjie Lin wrote:
>> From: Yue Wang
>
> Subject should be "dt-bindings: phy: ..."
>
>> The Meson-PCIE-PHY controller supports the 5-Gbps data rate
>> of the PCI Express Gen 2 specification and is backwardcompatible
>
> space
yes, I will fix
^
>
>> with the 2.5-Gbps Gen 1.1 specification with only
>> inferred idle detection supported on AMLOGIC SoCs.
>
> AMLOGIC or Amlogic?
>
yes, we will stick to 'Amlogic'
>>
>> Signed-off-by: Hanjie Lin
>> Signed-off-by: Yue Wang
>> ---
>> .../bindings/phy/amlogic,meson-pcie-phy.txt| 31
>> ++
>> 1 file changed, 31 insertions(+)
>> create mode 100644
>> Documentation/devicetree/bindings/phy/amlogic,meson-pcie-phy.txt
>>
>> diff --git
>> a/Documentation/devicetree/bindings/phy/amlogic,meson-pcie-phy.txt
>> b/Documentation/devicetree/bindings/phy/amlogic,meson-pcie-phy.txt
>> new file mode 100644
>> index 000..db99085
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/phy/amlogic,meson-pcie-phy.txt
>> @@ -0,0 +1,31 @@
>> +* Amlogic Meson AXG PCIE PHY binding
>> +
>> +Required properties:
>> +- compatible: Should be
>> +- "amlogic,axg-pcie-phy"
>> +- #phys-cells: must be 0 (see phy-bindings.txt in this directory)
>
> You don't need to distinguish port A and B?
No, we don't. Theoretically there is only one phy in the chip,
and we have distinguished ports by reset lines.
Thanks for all corrections and suggestions.
>
>> +- reg: The base address and length of the registers
>> +- resets: phandle to the reset lines
>> +- reset-names: must contain "phy" and "peripheral"
>> +- "port_a" Port A reset
>> +- "port_b" Port B reset
>> +- "phy" PHY reset
>> +- "apb" APB reset
>> +Optional properties:
>> +- phy-supply: see phy-bindings.txt in this directory
>> +
>> +Example:
>> +pcie_phy: pcie-phy@ff644000 {
>> +#phy-cells = <0>;
>> +compatible = "amlogic,axg-pcie-phy";
>> +reg = <0x0 0xff644000 0x0 0x2000>;
>> +resets = < RESET_PCIE_A>,
>> +< RESET_PCIE_B>,
>> +< RESET_PCIE_PHY>,
>> +< RESET_PCIE_APB>;
>> +reset-names =
>> +"port_a",
>> +"port_b",
>> +"phy",
>> +"apb";
>> +};
>> --
>> 2.7.4
>>
>
> .
>
[PATCH 2/2] PCI: meson: add the Amlogic Meson PCIe controller driver
From: Yue Wang
The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare
PCI core. This patch adds the driver support for Meson PCIe controller.
Signed-off-by: Yue Wang
Signed-off-by: Hanjie Lin
---
drivers/pci/controller/dwc/Kconfig | 12 +
drivers/pci/controller/dwc/Makefile| 1 +
drivers/pci/controller/dwc/pci-meson.c | 588 +
3 files changed, 601 insertions(+)
create mode 100644 drivers/pci/controller/dwc/pci-meson.c
diff --git a/drivers/pci/controller/dwc/Kconfig
b/drivers/pci/controller/dwc/Kconfig
index 91b0194..6cb36f6 100644
--- a/drivers/pci/controller/dwc/Kconfig
+++ b/drivers/pci/controller/dwc/Kconfig
@@ -193,4 +193,16 @@ config PCIE_HISI_STB
help
Say Y here if you want PCIe controller support on HiSilicon STB SoCs
+config PCI_MESON
+ bool "MESON PCIe controller"
+ depends on PCI
+ depends on PCI_MSI_IRQ_DOMAIN
+ select PCIEPORTBUS
+ select PCIE_DW_HOST
+ help
+ Say Y here if you want to enable PCI controller support on Amlogic
+ SoCs. The PCI controller on Amlogic is based on DesignWare hardware
+ and therefore the driver re-uses the DesignWare core functions to
+ implement the driver.
+
endmenu
diff --git a/drivers/pci/controller/dwc/Makefile
b/drivers/pci/controller/dwc/Makefile
index 5d2ce72..cf676bd 100644
--- a/drivers/pci/controller/dwc/Makefile
+++ b/drivers/pci/controller/dwc/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o
obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o
+obj-$(CONFIG_PCI_MESON) += pci-meson.o
# The following drivers are for devices that use the generic ACPI
# pci_root.c driver but don't support standard ECAM config access.
diff --git a/drivers/pci/controller/dwc/pci-meson.c
b/drivers/pci/controller/dwc/pci-meson.c
new file mode 100644
index 000..1e96e45
--- /dev/null
+++ b/drivers/pci/controller/dwc/pci-meson.c
@@ -0,0 +1,588 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PCIe host controller driver for Amlogic MESON SoCs
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Yue Wang
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "pcie-designware.h"
+
+#define to_meson_pcie(x) dev_get_drvdata((x)->dev)
+
+/* External local bus interface registers */
+#define PLR_OFFSET 0x700
+#define PCIE_PORT_LINK_CTRL_OFF(PLR_OFFSET + 0x10)
+#define FAST_LINK_MODE BIT(7)
+#define LINK_CAPABLE_MASK GENMASK(21, 16)
+#define LINK_CAPABLE_X1BIT(16)
+
+#define PCIE_GEN2_CTRL_OFF (PLR_OFFSET + 0x10c)
+#define NUM_OF_LANES_MASK GENMASK(12, 8)
+#define NUM_OF_LANES_X1BIT(8)
+#define DIRECT_SPEED_CHANGEBIT(17)
+
+#define TYPE1_HDR_OFFSET 0x0
+#define PCIE_STATUS_COMMAND(TYPE1_HDR_OFFSET + 0x04)
+#define PCI_IO_EN BIT(0)
+#define PCI_MEM_SPACE_EN BIT(1)
+#define PCI_BUS_MASTER_EN BIT(2)
+
+#define PCIE_BASE_ADDR0(TYPE1_HDR_OFFSET + 0x10)
+#define PCIE_BASE_ADDR1(TYPE1_HDR_OFFSET + 0x14)
+
+#define PCIE_CAP_OFFSET0x70
+#define PCIE_DEV_CTRL_DEV_STUS (PCIE_CAP_OFFSET + 0x08)
+#define PCIE_CAP_MAX_PAYLOAD_MASK GENMASK(7, 5)
+#define PCIE_CAP_MAX_PAYLOAD_SIZE(x) ((x) << 5)
+#define PCIE_CAP_MAX_READ_REQ_MASK GENMASK(14, 12)
+#define PCIE_CAP_MAX_READ_REQ_SIZE(x) ((x) << 12)
+
+#define PCI_CLASS_REVISION_MASKGENMASK(7, 0)
+
+/* PCIe specific config registers */
+#define PCIE_CFG0 0x0
+#define APP_LTSSM_ENABLE BIT(7)
+
+#define PCIE_CFG_STATUS12 0x30
+#define IS_SMLH_LINK_UP(x) ((x) & (1 << 6) ? 1 : 0)
+#define IS_RDLH_LINK_UP(x) ((x) & (1 << 16) ? 1 : 0)
+#define IS_LTSSM_UP(x) x) >> 10) & 0x1f) == 0x11 ? 1 : 0)
+
+#define PCIE_CFG_STATUS17 0x44
+#define PM_CURRENT_STATE(x)(((x) >> 7) & 0x1)
+
+#define WAIT_LINKUP_TIMEOUT2000
+#define PORT_CLK_RATE 1UL
+#define MAX_PAYLOAD_SIZE 256
+#define MAX_READ_REQ_SIZE 256
+
+enum pcie_data_rate {
+ PCIE_GEN1,
+ PCIE_GEN2,
+ PCIE_GEN3,
+ PCIE_GEN4
+};
+
+struct meson_pcie_mem_res {
+ void __iomem *elbi_base; /* DT 0th resource */
+ void __iomem *cfg_base; /* DT 2nd resource */
+};
+
+struct meson_pcie_clk_res {
+ struct clk *clk;
+ struct clk *mipi_gate;
+ struct clk *port_clk;
+ struct clk *general_clk;
+};
+
+struct meson_pcie {
+ struct dw_pcie pci;
+ s
[PATCH 0/2] add the Amlogic Meson PCIe controller driver.
The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core. This patchset add the driver and dt-bindings of the controller. Yue Wang (2): dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller PCI: meson: add the Amlogic Meson PCIe controller driver .../devicetree/bindings/pci/amlogic,meson-pcie.txt | 57 ++ drivers/pci/controller/dwc/Kconfig | 12 + drivers/pci/controller/dwc/Makefile| 1 + drivers/pci/controller/dwc/pci-meson.c | 588 + 4 files changed, 658 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt create mode 100644 drivers/pci/controller/dwc/pci-meson.c -- 2.7.4
[PATCH 1/2] dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller
From: Yue Wang
The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare
PCI core. This patch adds documentation for the DT bindings in Meson PCIe
controller.
Signed-off-by: Yue Wang
Signed-off-by: Hanjie Lin
---
.../devicetree/bindings/pci/amlogic,meson-pcie.txt | 57 ++
1 file changed, 57 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
diff --git a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
new file mode 100644
index 000..48233e4
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
@@ -0,0 +1,57 @@
+Amlogic Meson AXG DWC PCIE SoC controller
+
+Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI
core.
+It shares common functions with the PCIe DesignWare core driver and
+inherits common properties defined in
+Documentation/devicetree/bindings/pci/designware-pci.txt.
+
+Additional properties are described here:
+
+Required properties:
+- compatible:
+ should contain "amlogic,axg-pcie" to identify the core.
+- reg:
+ Should contain the configuration address space.
+- reg-names: Must be
+ - "elbi"External local bus interface registers
+ - "cfg" Meson specific registers
+ - "config" PCIe configuration space
+- clocks: Must contain an entry for each entry in clock-names.
+- clock-names: Must include the following entries:
+ - "pcie"
+ - "pcie_bus"
+ - "pcie_general"
+ - "pcie_mipi_en"
+
+Example configuration:
+
+ pcie: pcie@d000 {
+ compatible = "amlogic,axg-pcie", "snps,dw-pcie";
+ reg = <0x0 0xf980 0x0 0x40
+ 0x0 0xff646000 0x0 0x2000
+ 0x0 0xf9f0 0x0 0x10>;
+ reg-names = "elbi", "cfg", "config";
+ reset-gpio = < GPIOX_19 GPIO_ACTIVE_HIGH>;
+ interrupts = <0 177 IRQ_TYPE_EDGE_RISING>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 GIC_SPI 179
IRQ_TYPE_EDGE_RISING>;
+ bus-range = <0x0 0xff>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ phys = <_phy>;
+ ranges = <0x8200 0 0 0x0 0xf9c0 0 0x0030>;
+ num-lanes = <1>;
+ pcie-num = <1>;
+
+ clocks = < CLKID_USB
+CLKID_MIPI_ENABLE
+CLKID_PCIE_A
+CLKID_PCIE_CML_EN0>;
+ clock-names = "pcie_general",
+ "pcie_refpll",
+ "pcie_mipi_en",
+ "pcie",
+ "port";
+ };
--
2.7.4
[PATCH 0/2] add the Amlogic Meson PCIe controller driver.
The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core. This patchset add the driver and dt-bindings of the controller. Yue Wang (2): dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller PCI: meson: add the Amlogic Meson PCIe controller driver .../devicetree/bindings/pci/amlogic,meson-pcie.txt | 57 ++ drivers/pci/controller/dwc/Kconfig | 12 + drivers/pci/controller/dwc/Makefile| 1 + drivers/pci/controller/dwc/pci-meson.c | 588 + 4 files changed, 658 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt create mode 100644 drivers/pci/controller/dwc/pci-meson.c -- 2.7.4
[PATCH 1/2] dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller
From: Yue Wang
The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare
PCI core. This patch adds documentation for the DT bindings in Meson PCIe
controller.
Signed-off-by: Yue Wang
Signed-off-by: Hanjie Lin
---
.../devicetree/bindings/pci/amlogic,meson-pcie.txt | 57 ++
1 file changed, 57 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
diff --git a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
new file mode 100644
index 000..48233e4
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
@@ -0,0 +1,57 @@
+Amlogic Meson AXG DWC PCIE SoC controller
+
+Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI
core.
+It shares common functions with the PCIe DesignWare core driver and
+inherits common properties defined in
+Documentation/devicetree/bindings/pci/designware-pci.txt.
+
+Additional properties are described here:
+
+Required properties:
+- compatible:
+ should contain "amlogic,axg-pcie" to identify the core.
+- reg:
+ Should contain the configuration address space.
+- reg-names: Must be
+ - "elbi"External local bus interface registers
+ - "cfg" Meson specific registers
+ - "config" PCIe configuration space
+- clocks: Must contain an entry for each entry in clock-names.
+- clock-names: Must include the following entries:
+ - "pcie"
+ - "pcie_bus"
+ - "pcie_general"
+ - "pcie_mipi_en"
+
+Example configuration:
+
+ pcie: pcie@d000 {
+ compatible = "amlogic,axg-pcie", "snps,dw-pcie";
+ reg = <0x0 0xf980 0x0 0x40
+ 0x0 0xff646000 0x0 0x2000
+ 0x0 0xf9f0 0x0 0x10>;
+ reg-names = "elbi", "cfg", "config";
+ reset-gpio = < GPIOX_19 GPIO_ACTIVE_HIGH>;
+ interrupts = <0 177 IRQ_TYPE_EDGE_RISING>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 GIC_SPI 179
IRQ_TYPE_EDGE_RISING>;
+ bus-range = <0x0 0xff>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ phys = <_phy>;
+ ranges = <0x8200 0 0 0x0 0xf9c0 0 0x0030>;
+ num-lanes = <1>;
+ pcie-num = <1>;
+
+ clocks = < CLKID_USB
+CLKID_MIPI_ENABLE
+CLKID_PCIE_A
+CLKID_PCIE_CML_EN0>;
+ clock-names = "pcie_general",
+ "pcie_refpll",
+ "pcie_mipi_en",
+ "pcie",
+ "port";
+ };
--
2.7.4
[PATCH 2/2] PCI: meson: add the Amlogic Meson PCIe controller driver
From: Yue Wang
The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare
PCI core. This patch adds the driver support for Meson PCIe controller.
Signed-off-by: Yue Wang
Signed-off-by: Hanjie Lin
---
drivers/pci/controller/dwc/Kconfig | 12 +
drivers/pci/controller/dwc/Makefile| 1 +
drivers/pci/controller/dwc/pci-meson.c | 588 +
3 files changed, 601 insertions(+)
create mode 100644 drivers/pci/controller/dwc/pci-meson.c
diff --git a/drivers/pci/controller/dwc/Kconfig
b/drivers/pci/controller/dwc/Kconfig
index 91b0194..6cb36f6 100644
--- a/drivers/pci/controller/dwc/Kconfig
+++ b/drivers/pci/controller/dwc/Kconfig
@@ -193,4 +193,16 @@ config PCIE_HISI_STB
help
Say Y here if you want PCIe controller support on HiSilicon STB SoCs
+config PCI_MESON
+ bool "MESON PCIe controller"
+ depends on PCI
+ depends on PCI_MSI_IRQ_DOMAIN
+ select PCIEPORTBUS
+ select PCIE_DW_HOST
+ help
+ Say Y here if you want to enable PCI controller support on Amlogic
+ SoCs. The PCI controller on Amlogic is based on DesignWare hardware
+ and therefore the driver re-uses the DesignWare core functions to
+ implement the driver.
+
endmenu
diff --git a/drivers/pci/controller/dwc/Makefile
b/drivers/pci/controller/dwc/Makefile
index 5d2ce72..cf676bd 100644
--- a/drivers/pci/controller/dwc/Makefile
+++ b/drivers/pci/controller/dwc/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o
obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o
+obj-$(CONFIG_PCI_MESON) += pci-meson.o
# The following drivers are for devices that use the generic ACPI
# pci_root.c driver but don't support standard ECAM config access.
diff --git a/drivers/pci/controller/dwc/pci-meson.c
b/drivers/pci/controller/dwc/pci-meson.c
new file mode 100644
index 000..1e96e45
--- /dev/null
+++ b/drivers/pci/controller/dwc/pci-meson.c
@@ -0,0 +1,588 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PCIe host controller driver for Amlogic MESON SoCs
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Yue Wang
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "pcie-designware.h"
+
+#define to_meson_pcie(x) dev_get_drvdata((x)->dev)
+
+/* External local bus interface registers */
+#define PLR_OFFSET 0x700
+#define PCIE_PORT_LINK_CTRL_OFF(PLR_OFFSET + 0x10)
+#define FAST_LINK_MODE BIT(7)
+#define LINK_CAPABLE_MASK GENMASK(21, 16)
+#define LINK_CAPABLE_X1BIT(16)
+
+#define PCIE_GEN2_CTRL_OFF (PLR_OFFSET + 0x10c)
+#define NUM_OF_LANES_MASK GENMASK(12, 8)
+#define NUM_OF_LANES_X1BIT(8)
+#define DIRECT_SPEED_CHANGEBIT(17)
+
+#define TYPE1_HDR_OFFSET 0x0
+#define PCIE_STATUS_COMMAND(TYPE1_HDR_OFFSET + 0x04)
+#define PCI_IO_EN BIT(0)
+#define PCI_MEM_SPACE_EN BIT(1)
+#define PCI_BUS_MASTER_EN BIT(2)
+
+#define PCIE_BASE_ADDR0(TYPE1_HDR_OFFSET + 0x10)
+#define PCIE_BASE_ADDR1(TYPE1_HDR_OFFSET + 0x14)
+
+#define PCIE_CAP_OFFSET0x70
+#define PCIE_DEV_CTRL_DEV_STUS (PCIE_CAP_OFFSET + 0x08)
+#define PCIE_CAP_MAX_PAYLOAD_MASK GENMASK(7, 5)
+#define PCIE_CAP_MAX_PAYLOAD_SIZE(x) ((x) << 5)
+#define PCIE_CAP_MAX_READ_REQ_MASK GENMASK(14, 12)
+#define PCIE_CAP_MAX_READ_REQ_SIZE(x) ((x) << 12)
+
+#define PCI_CLASS_REVISION_MASKGENMASK(7, 0)
+
+/* PCIe specific config registers */
+#define PCIE_CFG0 0x0
+#define APP_LTSSM_ENABLE BIT(7)
+
+#define PCIE_CFG_STATUS12 0x30
+#define IS_SMLH_LINK_UP(x) ((x) & (1 << 6) ? 1 : 0)
+#define IS_RDLH_LINK_UP(x) ((x) & (1 << 16) ? 1 : 0)
+#define IS_LTSSM_UP(x) x) >> 10) & 0x1f) == 0x11 ? 1 : 0)
+
+#define PCIE_CFG_STATUS17 0x44
+#define PM_CURRENT_STATE(x)(((x) >> 7) & 0x1)
+
+#define WAIT_LINKUP_TIMEOUT2000
+#define PORT_CLK_RATE 1UL
+#define MAX_PAYLOAD_SIZE 256
+#define MAX_READ_REQ_SIZE 256
+
+enum pcie_data_rate {
+ PCIE_GEN1,
+ PCIE_GEN2,
+ PCIE_GEN3,
+ PCIE_GEN4
+};
+
+struct meson_pcie_mem_res {
+ void __iomem *elbi_base; /* DT 0th resource */
+ void __iomem *cfg_base; /* DT 2nd resource */
+};
+
+struct meson_pcie_clk_res {
+ struct clk *clk;
+ struct clk *mipi_gate;
+ struct clk *port_clk;
+ struct clk *general_clk;
+};
+
+struct meson_pcie {
+ struct dw_pcie pci;
+ s
[PATCH 0/2] add the Amlogic Meson PCIe phy driver.
This patcheset add the driver and dt-bindings for the Meson-PCIE-PHY controller. Yue Wang (2): dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe Phy controller PCI: meson: add the Amlogic Meson PCIe phy driver .../bindings/phy/amlogic,meson-pcie-phy.txt| 31 drivers/phy/amlogic/Kconfig| 8 ++ drivers/phy/amlogic/Makefile | 1 + drivers/phy/amlogic/phy-meson-axg-pcie.c | 160 + 4 files changed, 200 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/amlogic,meson-pcie-phy.txt create mode 100644 drivers/phy/amlogic/phy-meson-axg-pcie.c -- 2.7.4
[PATCH 2/2] PCI: meson: add the Amlogic Meson PCIe phy driver
From: Yue Wang
The Meson-PCIE-PHY controller supports the 5-Gbps data rate
of the PCI Express Gen 2 specification and is backwardcompatible
with the 2.5-Gbps Gen 1.1 specification with only
inferred idle detection supported on AMLOGIC SoCs.
Signed-off-by: Yue Wang
Signed-off-by: Hanjie Lin
---
drivers/phy/amlogic/Kconfig | 8 ++
drivers/phy/amlogic/Makefile | 1 +
drivers/phy/amlogic/phy-meson-axg-pcie.c | 160 +++
3 files changed, 169 insertions(+)
create mode 100644 drivers/phy/amlogic/phy-meson-axg-pcie.c
diff --git a/drivers/phy/amlogic/Kconfig b/drivers/phy/amlogic/Kconfig
index 23fe1cd..3ab07f9 100644
--- a/drivers/phy/amlogic/Kconfig
+++ b/drivers/phy/amlogic/Kconfig
@@ -36,3 +36,11 @@ config PHY_MESON_GXL_USB3
Enable this to support the Meson USB3 PHY and OTG detection
IP block found in Meson GXL and GXM SoCs.
If unsure, say N.
+
+config PHY_MESON_AXG_PCIE
+ bool "Meson AXG PCIe PHY driver"
+ depends on OF && (ARCH_MESON || COMPILE_TEST)
+ select GENERIC_PHY
+ help
+ Enable PCIe PHY support for Meson AXG SoC series.
+ This driver provides PHY interface for Meson PCIe controller.
\ No newline at end of file
diff --git a/drivers/phy/amlogic/Makefile b/drivers/phy/amlogic/Makefile
index 4fd8848..5ab8578 100644
--- a/drivers/phy/amlogic/Makefile
+++ b/drivers/phy/amlogic/Makefile
@@ -1,3 +1,4 @@
obj-$(CONFIG_PHY_MESON8B_USB2) += phy-meson8b-usb2.o
obj-$(CONFIG_PHY_MESON_GXL_USB2) += phy-meson-gxl-usb2.o
obj-$(CONFIG_PHY_MESON_GXL_USB3) += phy-meson-gxl-usb3.o
+obj-$(CONFIG_PHY_MESON_AXG_PCIE) += phy-meson-axg-pcie.o
diff --git a/drivers/phy/amlogic/phy-meson-axg-pcie.c
b/drivers/phy/amlogic/phy-meson-axg-pcie.c
new file mode 100644
index 000..8bc5c49
--- /dev/null
+++ b/drivers/phy/amlogic/phy-meson-axg-pcie.c
@@ -0,0 +1,160 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Amlogic MESON SoC series PCIe PHY driver
+ *
+ * Phy provider for PCIe controller on MESON SoC series
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Yue Wang
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct meson_pcie_phy_data {
+ const struct phy_ops*ops;
+};
+
+struct meson_pcie_reset {
+ struct reset_control*port_a;
+ struct reset_control*port_b;
+ struct reset_control*phy;
+ struct reset_control*apb;
+};
+
+struct meson_pcie_phy {
+ const struct meson_pcie_phy_data*data;
+ struct meson_pcie_reset reset;
+ void __iomem*phy_base;
+};
+
+static int meson_pcie_phy_init(struct phy *phy)
+{
+ struct meson_pcie_phy *mphy = phy_get_drvdata(phy);
+ struct meson_pcie_reset *mrst = >reset;
+
+ writel(0x1c, mphy->phy_base);
+ reset_control_assert(mrst->port_a);
+ reset_control_assert(mrst->port_b);
+ reset_control_assert(mrst->phy);
+ reset_control_assert(mrst->apb);
+ udelay(400);
+ reset_control_deassert(mrst->port_a);
+ reset_control_deassert(mrst->port_b);
+ reset_control_deassert(mrst->phy);
+ reset_control_deassert(mrst->apb);
+ udelay(500);
+
+ return 0;
+}
+
+static const struct phy_ops meson_phy_ops = {
+ .init = meson_pcie_phy_init,
+ .owner = THIS_MODULE,
+};
+
+static const struct meson_pcie_phy_data meson_pcie_phy_data = {
+ .ops= _phy_ops,
+};
+
+static const struct of_device_id meson_pcie_phy_match[] = {
+ {
+ .compatible = "amlogic,axg-pcie-phy",
+ .data = _pcie_phy_data,
+ },
+ {},
+};
+
+static int meson_pcie_phy_probe(struct platform_device *pdev)
+{
+ struct device *dev = >dev;
+ struct meson_pcie_phy *mphy;
+ struct meson_pcie_reset *mrst;
+ struct phy *generic_phy;
+ struct phy_provider *phy_provider;
+ struct resource *res;
+ const struct meson_pcie_phy_data *data;
+
+ data = of_device_get_match_data(dev);
+ if (!data)
+ return -ENODEV;
+
+ mphy = devm_kzalloc(dev, sizeof(*mphy), GFP_KERNEL);
+ if (!mphy)
+ return -ENOMEM;
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ mphy->phy_base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(mphy->phy_base))
+ return PTR_ERR(mphy->phy_base);
+
+ mrst = >reset;
+
+ mrst->port_a = devm_reset_control_get_shared(dev, "port_a");
+ if (IS_ERR(mrst->port_a)) {
+ if (PTR_ERR(mrst->port_a) != -EPROBE_DEFER)
+ dev_err(dev, "couldn't get port a reset %ld\n",
+ PTR_ERR(mrst->port_a));
+
+ return PTR_ERR(mrst->port_a);
+ }
+
+ mrst->port_b = devm_reset_
[PATCH 1/2] dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe Phy controller
From: Yue Wang
The Meson-PCIE-PHY controller supports the 5-Gbps data rate
of the PCI Express Gen 2 specification and is backwardcompatible
with the 2.5-Gbps Gen 1.1 specification with only
inferred idle detection supported on AMLOGIC SoCs.
Signed-off-by: Hanjie Lin
Signed-off-by: Yue Wang
---
.../bindings/phy/amlogic,meson-pcie-phy.txt| 31 ++
1 file changed, 31 insertions(+)
create mode 100644
Documentation/devicetree/bindings/phy/amlogic,meson-pcie-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/amlogic,meson-pcie-phy.txt
b/Documentation/devicetree/bindings/phy/amlogic,meson-pcie-phy.txt
new file mode 100644
index 000..db99085
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/amlogic,meson-pcie-phy.txt
@@ -0,0 +1,31 @@
+* Amlogic Meson AXG PCIE PHY binding
+
+Required properties:
+- compatible: Should be
+ - "amlogic,axg-pcie-phy"
+- #phys-cells: must be 0 (see phy-bindings.txt in this directory)
+- reg: The base address and length of the registers
+- resets: phandle to the reset lines
+- reset-names: must contain "phy" and "peripheral"
+ - "port_a" Port A reset
+ - "port_b" Port B reset
+ - "phy" PHY reset
+ - "apb" APB reset
+Optional properties:
+- phy-supply: see phy-bindings.txt in this directory
+
+Example:
+ pcie_phy: pcie-phy@ff644000 {
+ #phy-cells = <0>;
+ compatible = "amlogic,axg-pcie-phy";
+ reg = <0x0 0xff644000 0x0 0x2000>;
+ resets = < RESET_PCIE_A>,
+ < RESET_PCIE_B>,
+ < RESET_PCIE_PHY>,
+ < RESET_PCIE_APB>;
+ reset-names =
+ "port_a",
+ "port_b",
+ "phy",
+ "apb";
+ };
--
2.7.4
[PATCH 0/2] add the Amlogic Meson PCIe phy driver.
This patcheset add the driver and dt-bindings for the Meson-PCIE-PHY controller. Yue Wang (2): dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe Phy controller PCI: meson: add the Amlogic Meson PCIe phy driver .../bindings/phy/amlogic,meson-pcie-phy.txt| 31 drivers/phy/amlogic/Kconfig| 8 ++ drivers/phy/amlogic/Makefile | 1 + drivers/phy/amlogic/phy-meson-axg-pcie.c | 160 + 4 files changed, 200 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/amlogic,meson-pcie-phy.txt create mode 100644 drivers/phy/amlogic/phy-meson-axg-pcie.c -- 2.7.4
[PATCH 2/2] PCI: meson: add the Amlogic Meson PCIe phy driver
From: Yue Wang
The Meson-PCIE-PHY controller supports the 5-Gbps data rate
of the PCI Express Gen 2 specification and is backwardcompatible
with the 2.5-Gbps Gen 1.1 specification with only
inferred idle detection supported on AMLOGIC SoCs.
Signed-off-by: Yue Wang
Signed-off-by: Hanjie Lin
---
drivers/phy/amlogic/Kconfig | 8 ++
drivers/phy/amlogic/Makefile | 1 +
drivers/phy/amlogic/phy-meson-axg-pcie.c | 160 +++
3 files changed, 169 insertions(+)
create mode 100644 drivers/phy/amlogic/phy-meson-axg-pcie.c
diff --git a/drivers/phy/amlogic/Kconfig b/drivers/phy/amlogic/Kconfig
index 23fe1cd..3ab07f9 100644
--- a/drivers/phy/amlogic/Kconfig
+++ b/drivers/phy/amlogic/Kconfig
@@ -36,3 +36,11 @@ config PHY_MESON_GXL_USB3
Enable this to support the Meson USB3 PHY and OTG detection
IP block found in Meson GXL and GXM SoCs.
If unsure, say N.
+
+config PHY_MESON_AXG_PCIE
+ bool "Meson AXG PCIe PHY driver"
+ depends on OF && (ARCH_MESON || COMPILE_TEST)
+ select GENERIC_PHY
+ help
+ Enable PCIe PHY support for Meson AXG SoC series.
+ This driver provides PHY interface for Meson PCIe controller.
\ No newline at end of file
diff --git a/drivers/phy/amlogic/Makefile b/drivers/phy/amlogic/Makefile
index 4fd8848..5ab8578 100644
--- a/drivers/phy/amlogic/Makefile
+++ b/drivers/phy/amlogic/Makefile
@@ -1,3 +1,4 @@
obj-$(CONFIG_PHY_MESON8B_USB2) += phy-meson8b-usb2.o
obj-$(CONFIG_PHY_MESON_GXL_USB2) += phy-meson-gxl-usb2.o
obj-$(CONFIG_PHY_MESON_GXL_USB3) += phy-meson-gxl-usb3.o
+obj-$(CONFIG_PHY_MESON_AXG_PCIE) += phy-meson-axg-pcie.o
diff --git a/drivers/phy/amlogic/phy-meson-axg-pcie.c
b/drivers/phy/amlogic/phy-meson-axg-pcie.c
new file mode 100644
index 000..8bc5c49
--- /dev/null
+++ b/drivers/phy/amlogic/phy-meson-axg-pcie.c
@@ -0,0 +1,160 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Amlogic MESON SoC series PCIe PHY driver
+ *
+ * Phy provider for PCIe controller on MESON SoC series
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Yue Wang
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct meson_pcie_phy_data {
+ const struct phy_ops*ops;
+};
+
+struct meson_pcie_reset {
+ struct reset_control*port_a;
+ struct reset_control*port_b;
+ struct reset_control*phy;
+ struct reset_control*apb;
+};
+
+struct meson_pcie_phy {
+ const struct meson_pcie_phy_data*data;
+ struct meson_pcie_reset reset;
+ void __iomem*phy_base;
+};
+
+static int meson_pcie_phy_init(struct phy *phy)
+{
+ struct meson_pcie_phy *mphy = phy_get_drvdata(phy);
+ struct meson_pcie_reset *mrst = >reset;
+
+ writel(0x1c, mphy->phy_base);
+ reset_control_assert(mrst->port_a);
+ reset_control_assert(mrst->port_b);
+ reset_control_assert(mrst->phy);
+ reset_control_assert(mrst->apb);
+ udelay(400);
+ reset_control_deassert(mrst->port_a);
+ reset_control_deassert(mrst->port_b);
+ reset_control_deassert(mrst->phy);
+ reset_control_deassert(mrst->apb);
+ udelay(500);
+
+ return 0;
+}
+
+static const struct phy_ops meson_phy_ops = {
+ .init = meson_pcie_phy_init,
+ .owner = THIS_MODULE,
+};
+
+static const struct meson_pcie_phy_data meson_pcie_phy_data = {
+ .ops= _phy_ops,
+};
+
+static const struct of_device_id meson_pcie_phy_match[] = {
+ {
+ .compatible = "amlogic,axg-pcie-phy",
+ .data = _pcie_phy_data,
+ },
+ {},
+};
+
+static int meson_pcie_phy_probe(struct platform_device *pdev)
+{
+ struct device *dev = >dev;
+ struct meson_pcie_phy *mphy;
+ struct meson_pcie_reset *mrst;
+ struct phy *generic_phy;
+ struct phy_provider *phy_provider;
+ struct resource *res;
+ const struct meson_pcie_phy_data *data;
+
+ data = of_device_get_match_data(dev);
+ if (!data)
+ return -ENODEV;
+
+ mphy = devm_kzalloc(dev, sizeof(*mphy), GFP_KERNEL);
+ if (!mphy)
+ return -ENOMEM;
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ mphy->phy_base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(mphy->phy_base))
+ return PTR_ERR(mphy->phy_base);
+
+ mrst = >reset;
+
+ mrst->port_a = devm_reset_control_get_shared(dev, "port_a");
+ if (IS_ERR(mrst->port_a)) {
+ if (PTR_ERR(mrst->port_a) != -EPROBE_DEFER)
+ dev_err(dev, "couldn't get port a reset %ld\n",
+ PTR_ERR(mrst->port_a));
+
+ return PTR_ERR(mrst->port_a);
+ }
+
+ mrst->port_b = devm_reset_
[PATCH 1/2] dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe Phy controller
From: Yue Wang
The Meson-PCIE-PHY controller supports the 5-Gbps data rate
of the PCI Express Gen 2 specification and is backwardcompatible
with the 2.5-Gbps Gen 1.1 specification with only
inferred idle detection supported on AMLOGIC SoCs.
Signed-off-by: Hanjie Lin
Signed-off-by: Yue Wang
---
.../bindings/phy/amlogic,meson-pcie-phy.txt| 31 ++
1 file changed, 31 insertions(+)
create mode 100644
Documentation/devicetree/bindings/phy/amlogic,meson-pcie-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/amlogic,meson-pcie-phy.txt
b/Documentation/devicetree/bindings/phy/amlogic,meson-pcie-phy.txt
new file mode 100644
index 000..db99085
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/amlogic,meson-pcie-phy.txt
@@ -0,0 +1,31 @@
+* Amlogic Meson AXG PCIE PHY binding
+
+Required properties:
+- compatible: Should be
+ - "amlogic,axg-pcie-phy"
+- #phys-cells: must be 0 (see phy-bindings.txt in this directory)
+- reg: The base address and length of the registers
+- resets: phandle to the reset lines
+- reset-names: must contain "phy" and "peripheral"
+ - "port_a" Port A reset
+ - "port_b" Port B reset
+ - "phy" PHY reset
+ - "apb" APB reset
+Optional properties:
+- phy-supply: see phy-bindings.txt in this directory
+
+Example:
+ pcie_phy: pcie-phy@ff644000 {
+ #phy-cells = <0>;
+ compatible = "amlogic,axg-pcie-phy";
+ reg = <0x0 0xff644000 0x0 0x2000>;
+ resets = < RESET_PCIE_A>,
+ < RESET_PCIE_B>,
+ < RESET_PCIE_PHY>,
+ < RESET_PCIE_APB>;
+ reset-names =
+ "port_a",
+ "port_b",
+ "phy",
+ "apb";
+ };
--
2.7.4
