Re: [PATCH 1/7] ARM: dts: rockchip: move rk322x mmcx aliases to board dts files
On Wed, 24 Mar 2021 13:22:29 +0100, Heiko Stuebner wrote: > As suggested by Arnd Bergmann, mmc-aliases are supposed to be > board-specific, so move the newly added general aliases to > the board-level on rk322x-based boards. Applied, thanks! [1/7] ARM: dts: rockchip: move rk322x mmcx aliases to board dts files commit: 23a52b0dfebf8b9ae44829c561c3d82d8b9c48e3 [2/7] ARM: dts: rockchip: move rv1108 mmcx aliases to board dts files commit: e89db2b4c706b9ca1293e7025ef5e8730b5d1b5b [3/7] arm64: dts: rockchip: move mmc aliases to board dts on px30 commit: 78b8513b763c121d0ac5ed8fef3188ea065913bb [4/7] arm64: dts: rockchip: move mmc aliases to board dts on rk3308 commit: 3f6c22987c0bdfb42b497e346d77b6cdaed55de3 [5/7] arm64: dts: rockchip: move mmc aliases to board dts on rk3328 commit: 28869aa53506a12d98f6e5ff54b051400be1c2bf [6/7] arm64: dts: rockchip: move mmc aliases to board dts on rk3368 commit: 751a78a8bd25ac2634baa19f6f918912360fba93 [7/7] arm64: dts: rockchip: move mmc aliases to board dts on rk3399 commit: 5dcbe7e3862dfc89d219f37a9ed5e53944fa13c2 Best regards, -- Heiko Stuebner
Re: (subset) [PATCH 1/8] dt-binding: watchdog: add more Rockchip compatibles to snps, dw-wdt.yaml
On Fri, 18 Dec 2020 13:05:27 +0100, Johan Jonker wrote: > The watchdog compatible strings are suppose to be SoC orientated. > In the more recently added Rockchip SoC dtsi files only > the fallback string "snps,dw-wdt" is used, so add the following > compatible strings: > > "rockchip,px30-wdt", "snps,dw-wdt" > "rockchip,rk3228-wdt", "snps,dw-wdt" > "rockchip,rk3308-wdt", "snps,dw-wdt" > "rockchip,rk3328-wdt", "snps,dw-wdt" > "rockchip,rk3399-wdt", "snps,dw-wdt" > "rockchip,rv1108-wdt", "snps,dw-wdt" > > [...] Applied, thanks! [2/8] ARM: dts: rockchip: add new watchdog compatible to rv1108.dtsi commit: 610e4c7215ddfa5c1bb52764717674ea8adb64f9 [3/8] ARM: dts: rockchip: add new watchdog compatible to rk322x.dtsi commit: 9ceb98f1ed19bc68129aa0db9da5adb4a40c0f1c [4/8] arm64: dts: rockchip: add new watchdog compatible to px30.dtsi commit: d16c7082cff5e198f2435f08e2254e40f3058c75 [5/8] arm64: dts: rockchip: add new watchdog compatible to rk3308.dtsi commit: 58ead0c605e8a5f4139ed4dfffcdddac72e2eb31 [6/8] arm64: dts: rockchip: add new watchdog compatible to rk3328.dtsi commit: 2499448c920fc9648350d4f21e1fbd00ccd108ee [7/8] arm64: dts: rockchip: add new watchdog compatible to rk3399.dtsi commit: 6b5c50863b3e6837f856a137fe6880ed4662335b [8/8] ARM: dts: rockchip: remove clock-names property from watchdog node in rv1108.dtsi commit: 398a4087872a44921d0ede2afef53a3c9f779ab6 Best regards, -- Heiko Stuebner
Re: (subset) [PATCH v5 1/8] dt-bindings: usb: convert rockchip,dwc3.txt to yaml
On Tue, 9 Feb 2021 20:23:43 +0100, Johan Jonker wrote: > In the past Rockchip dwc3 usb nodes were manually checked. > With the conversion of snps,dwc3.yaml as common document > we now can convert rockchip,dwc3.txt to yaml as well. > Remove node wrapper. > > Added properties for rk3399 are: > power-domains > resets > reset-names Applied, thanks! [7/8] arm64: dts: rockchip: add rk3328 dwc3 usb controller node commit: 44dd5e2106dc2fd01697b539085818d1d1c58df0 [8/8] dts64: rockchip: enable dwc3 usb for A95X Z2 commit: f227197bdf91a58903753ff18f5d0ad8f170e4b5 Changed the title of the last patch to the more appropriate arm64: dts: rockchip: enable dwc3 usb for A95X Z2 Best regards, -- Heiko Stuebner
[PATCH 2/7] ARM: dts: rockchip: move rv1108 mmcx aliases to board dts files
From: Heiko Stuebner
As suggested by Arnd Bergmann, mmc-aliases are supposed to be
board-specific, so move the newly added general aliases to
the board-level on rv1108-based boards.
Suggested-by: Arnd Bergmann
Signed-off-by: Heiko Stuebner
---
arch/arm/boot/dts/rv1108-elgin-r1.dts | 4
arch/arm/boot/dts/rv1108-evb.dts | 4
arch/arm/boot/dts/rv1108.dtsi | 3 ---
3 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/rv1108-elgin-r1.dts
b/arch/arm/boot/dts/rv1108-elgin-r1.dts
index b1db924710c8..f62c9f7af79d 100644
--- a/arch/arm/boot/dts/rv1108-elgin-r1.dts
+++ b/arch/arm/boot/dts/rv1108-elgin-r1.dts
@@ -12,6 +12,10 @@ / {
model = "Elgin RV1108 R1 board";
compatible = "elgin,rv1108-r1", "rockchip,rv1108";
+ aliases {
+ mmc0 =
+ };
+
memory@6000 {
device_type = "memory";
reg = <0x6000 0x0800>;
diff --git a/arch/arm/boot/dts/rv1108-evb.dts b/arch/arm/boot/dts/rv1108-evb.dts
index 30f3d0470ad9..fe5fc9bf75c9 100644
--- a/arch/arm/boot/dts/rv1108-evb.dts
+++ b/arch/arm/boot/dts/rv1108-evb.dts
@@ -8,6 +8,10 @@ / {
model = "Rockchip RV1108 Evaluation board";
compatible = "rockchip,rv1108-evb", "rockchip,rv1108";
+ aliases {
+ mmc0 =
+ };
+
memory@6000 {
device_type = "memory";
reg = <0x6000 0x0800>;
diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index 7319a2473b80..15fa25585ea4 100644
--- a/arch/arm/boot/dts/rv1108.dtsi
+++ b/arch/arm/boot/dts/rv1108.dtsi
@@ -19,9 +19,6 @@ aliases {
i2c1 =
i2c2 =
i2c3 =
- mmc0 =
- mmc1 =
- mmc2 =
serial0 =
serial1 =
serial2 =
--
2.29.2
[PATCH 5/7] arm64: dts: rockchip: move mmc aliases to board dts on rk3328
From: Heiko Stuebner
As suggested by Arnd Bergmann, the newly added mmc aliases
should be board specific, so move them from the general dtsi
to the individual boards.
Suggested-by: Arnd Bergmann
Signed-off-by: Heiko Stuebner
---
arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts| 6 ++
arch/arm64/boot/dts/rockchip/rk3328-a1.dts | 5 +
arch/arm64/boot/dts/rockchip/rk3328-evb.dts| 6 ++
arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 4
arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 5 +
arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts | 5 +
arch/arm64/boot/dts/rockchip/rk3328-rock64.dts | 5 +
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 3 ---
8 files changed, 36 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts
b/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts
index 30c73ef25370..4e47d995b8d6 100644
--- a/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts
@@ -8,6 +8,12 @@ / {
model = "A95X Z2";
compatible = "zkmagic,a95x-z2", "rockchip,rk3318";
+ aliases {
+ mmc0 =
+ mmc1 =
+ mmc2 =
+ };
+
chosen {
stdout-path = "serial2:150n8";
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
index 37f307cfa4cc..de2d3e88e27f 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts
@@ -8,6 +8,11 @@ / {
model = "Beelink A1";
compatible = "azw,beelink-a1", "rockchip,rk3328";
+ aliases {
+ mmc0 =
+ mmc1 =
+ };
+
/*
* UART pins, as viewed with bottom of case removed:
*
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-evb.dts
b/arch/arm64/boot/dts/rockchip/rk3328-evb.dts
index a48767931af6..ff6b466e0e07 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328-evb.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-evb.dts
@@ -10,6 +10,12 @@ / {
model = "Rockchip RK3328 EVB";
compatible = "rockchip,rk3328-evb", "rockchip,rk3328";
+ aliases {
+ mmc0 =
+ mmc1 =
+ mmc2 =
+ };
+
chosen {
stdout-path = "serial2:150n8";
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
index faf496d789cf..f807bc066ccb 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
@@ -13,6 +13,10 @@ / {
model = "FriendlyElec NanoPi R2S";
compatible = "friendlyarm,nanopi-r2s", "rockchip,rk3328";
+ aliases {
+ mmc0 =
+ };
+
chosen {
stdout-path = "serial2:150n8";
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
index 19959bfba451..a05732b59f38 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
@@ -10,6 +10,11 @@ / {
model = "Firefly roc-rk3328-cc";
compatible = "firefly,roc-rk3328-cc", "rockchip,rk3328";
+ aliases {
+ mmc0 =
+ mmc1 =
+ };
+
chosen {
stdout-path = "serial2:150n8";
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts
b/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts
index 2d71ca7e429c..c7e31efdd2e1 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts
@@ -20,6 +20,11 @@ / {
model = "Radxa ROCK Pi E";
compatible = "radxa,rockpi-e", "rockchip,rk3328";
+ aliases {
+ mmc0 =
+ mmc1 =
+ };
+
chosen {
stdout-path = "serial2:150n8";
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
index c984662043da..3bef1f39bc6e 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
@@ -10,6 +10,11 @@ / {
model = "Pine64 Rock64";
compatible = "pine64,rock64", "rockchip,rk3328";
+ aliases {
+ mmc0 =
+ mmc1 =
+ };
+
chosen {
stdout-path = "serial2:150n8";
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index 063ed0adbec4..708d82bdfd6c 100644
--- a/arch/arm64/boot
[PATCH 1/7] ARM: dts: rockchip: move rk322x mmcx aliases to board dts files
From: Heiko Stuebner
As suggested by Arnd Bergmann, mmc-aliases are supposed to be
board-specific, so move the newly added general aliases to
the board-level on rk322x-based boards.
Suggested-by: Arnd Bergmann
Signed-off-by: Heiko Stuebner
---
arch/arm/boot/dts/rk3228-evb.dts | 4
arch/arm/boot/dts/rk3229-evb.dts | 4
arch/arm/boot/dts/rk3229-xms6.dts | 6 ++
arch/arm/boot/dts/rk322x.dtsi | 3 ---
4 files changed, 14 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/rk3228-evb.dts b/arch/arm/boot/dts/rk3228-evb.dts
index aed879db6c15..69a5e239ed1a 100644
--- a/arch/arm/boot/dts/rk3228-evb.dts
+++ b/arch/arm/boot/dts/rk3228-evb.dts
@@ -8,6 +8,10 @@ / {
model = "Rockchip RK3228 Evaluation board";
compatible = "rockchip,rk3228-evb", "rockchip,rk3228";
+ aliases {
+ mmc0 =
+ };
+
memory@6000 {
device_type = "memory";
reg = <0x6000 0x4000>;
diff --git a/arch/arm/boot/dts/rk3229-evb.dts b/arch/arm/boot/dts/rk3229-evb.dts
index 350497a3ca86..797476e8bef1 100644
--- a/arch/arm/boot/dts/rk3229-evb.dts
+++ b/arch/arm/boot/dts/rk3229-evb.dts
@@ -9,6 +9,10 @@ / {
model = "Rockchip RK3229 Evaluation board";
compatible = "rockchip,rk3229-evb", "rockchip,rk3229";
+ aliases {
+ mmc0 =
+ };
+
memory@6000 {
device_type = "memory";
reg = <0x6000 0x4000>;
diff --git a/arch/arm/boot/dts/rk3229-xms6.dts
b/arch/arm/boot/dts/rk3229-xms6.dts
index 263393ac4fa6..7bfbfd11fb55 100644
--- a/arch/arm/boot/dts/rk3229-xms6.dts
+++ b/arch/arm/boot/dts/rk3229-xms6.dts
@@ -9,6 +9,12 @@ / {
model = "Mecer Xtreme Mini S6";
compatible = "mecer,xms6", "rockchip,rk3229";
+ aliases {
+ mmc0 =
+ mmc1 =
+ mmc2 =
+ };
+
memory@6000 {
device_type = "memory";
reg = <0x6000 0x4000>;
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index a4dd50aaf3fc..4d003afd0e3e 100644
--- a/arch/arm/boot/dts/rk322x.dtsi
+++ b/arch/arm/boot/dts/rk322x.dtsi
@@ -14,9 +14,6 @@ / {
interrupt-parent = <>;
aliases {
- mmc0 =
- mmc1 =
- mmc2 =
serial0 =
serial1 =
serial2 =
--
2.29.2
[PATCH 3/7] arm64: dts: rockchip: move mmc aliases to board dts on px30
From: Heiko Stuebner
As suggested by Arnd Bergmann, the newly added mmc aliases
should be board specific, so move them from the general dtsi
to the individual boards.
For the Engicam-boards this means a split as the core
boards contains the emmc while the commit baseboard handles
sdmmc and sdio.
Suggested-by: Arnd Bergmann
Signed-off-by: Heiko Stuebner
---
arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi| 5 +
arch/arm64/boot/dts/rockchip/px30-engicam-px30-core.dtsi | 4
arch/arm64/boot/dts/rockchip/px30-evb.dts| 6 ++
arch/arm64/boot/dts/rockchip/px30.dtsi | 3 ---
arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts | 4
5 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi
b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi
index 08b0b9fbcbc9..3429e124d95a 100644
--- a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi
+++ b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi
@@ -6,6 +6,11 @@
*/
/ {
+ aliases {
+ mmc1 =
+ mmc2 =
+ };
+
vcc5v0_sys: vcc5v0-sys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys"; /* +5V */
diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core.dtsi
b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core.dtsi
index cdacd3483600..7249871530ab 100644
--- a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core.dtsi
+++ b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core.dtsi
@@ -11,6 +11,10 @@
/ {
compatible = "engicam,px30-core", "rockchip,px30";
+
+ aliases {
+ mmc0 =
+ };
};
{
diff --git a/arch/arm64/boot/dts/rockchip/px30-evb.dts
b/arch/arm64/boot/dts/rockchip/px30-evb.dts
index 52e788e983af..65c016ef5fa5 100644
--- a/arch/arm64/boot/dts/rockchip/px30-evb.dts
+++ b/arch/arm64/boot/dts/rockchip/px30-evb.dts
@@ -13,6 +13,12 @@ / {
model = "Rockchip PX30 EVB";
compatible = "rockchip,px30-evb", "rockchip,px30";
+ aliases {
+ mmc0 =
+ mmc1 =
+ mmc2 =
+ };
+
chosen {
stdout-path = "serial5:115200n8";
};
diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi
b/arch/arm64/boot/dts/rockchip/px30.dtsi
index 04d0399bcd74..2ea8aa1a2c6d 100644
--- a/arch/arm64/boot/dts/rockchip/px30.dtsi
+++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
@@ -25,9 +25,6 @@ aliases {
i2c1 =
i2c2 =
i2c3 =
- mmc0 =
- mmc1 =
- mmc2 =
serial0 =
serial1 =
serial2 =
diff --git a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
index 2638b332409c..63fbe9704141 100644
--- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
@@ -14,6 +14,10 @@ / {
model = "ODROID-GO Advance";
compatible = "hardkernel,rk3326-odroid-go2", "rockchip,rk3326";
+ aliases {
+ mmc0 =
+ };
+
chosen {
stdout-path = "serial2:115200n8";
};
--
2.29.2
[PATCH 7/7] arm64: dts: rockchip: move mmc aliases to board dts on rk3399
From: Heiko Stuebner
As suggested by Arnd Bergmann, the newly added mmc aliases
should be board specific, so move them from the general dtsi
to the individual boards.
Suggested-by: Arnd Bergmann
Signed-off-by: Heiko Stuebner
---
arch/arm64/boot/dts/rockchip/rk3399-evb.dts| 4
arch/arm64/boot/dts/rockchip/rk3399-firefly.dts| 6 ++
arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 5 +
arch/arm64/boot/dts/rockchip/rk3399-hugsun-x99.dts | 6 ++
arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi | 6 ++
arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts | 5 +
arch/arm64/boot/dts/rockchip/rk3399-leez-p710.dts | 6 ++
arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi | 6 ++
arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts | 6 ++
arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts | 6 ++
arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts| 4
arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi | 4
arch/arm64/boot/dts/rockchip/rk3399-roc-pc-mezzanine.dts | 4
arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi| 5 +
arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi | 5 +
arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dts | 4
arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts | 4
arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi | 6 ++
arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi | 6 ++
arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts | 4
arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi | 5 +
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 3 ---
arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi | 5 +
23 files changed, 112 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
index 694b0d08d644..7b717ebec8ff 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
@@ -11,6 +11,10 @@ / {
model = "Rockchip RK3399 Evaluation Board";
compatible = "rockchip,rk3399-evb", "rockchip,rk3399";
+ aliases {
+ mmc0 =
+ };
+
backlight: backlight {
compatible = "pwm-backlight";
brightness-levels = <
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
index 6db18808b9c5..45254be1350d 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
@@ -13,6 +13,12 @@ / {
model = "Firefly-RK3399 Board";
compatible = "firefly,firefly-rk3399", "rockchip,rk3399";
+ aliases {
+ mmc0 =
+ mmc1 =
+ mmc2 =
+ };
+
chosen {
stdout-path = "serial2:150n8";
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
index 32dcaf210085..4002742fed4c 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
@@ -10,6 +10,11 @@
#include "rk3399-op1-opp.dtsi"
/ {
+ aliases {
+ mmc0 =
+ mmc1 =
+ };
+
chosen {
stdout-path = "serial2:115200n8";
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-hugsun-x99.dts
b/arch/arm64/boot/dts/rockchip/rk3399-hugsun-x99.dts
index 341d074ed996..bee45c17e2ca 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-hugsun-x99.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-hugsun-x99.dts
@@ -9,6 +9,12 @@ / {
model = "Hugsun X99 TV BOX";
compatible = "hugsun,x99", "rockchip,rk3399";
+ aliases {
+ mmc0 =
+ mmc1 =
+ mmc2 =
+ };
+
chosen {
stdout-path = "serial2:150n8";
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi
b/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi
index 635afdd99122..d5c7648c841d 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi
@@ -11,6 +11,12 @@
#include "rk3399-opp.dtsi"
/ {
+ aliases {
+ mmc0 =
+ mmc1 =
+ mmc2 =
+ };
+
chosen {
stdout-path = "serial2:150n8";
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts
b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts
index 66c725a34220..19485b552bc4 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts
+++ b/arch/arm64/boot/dts/rock
[PATCH 6/7] arm64: dts: rockchip: move mmc aliases to board dts on rk3368
From: Heiko Stuebner
As suggested by Arnd Bergmann, the newly added mmc aliases
should be board specific, so move them from the general dtsi
to the individual boards.
Suggested-by: Arnd Bergmann
Signed-off-by: Heiko Stuebner
---
arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi | 4
arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts| 4
arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts| 4
arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi | 4
arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts | 5 +
arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts| 5 +
arch/arm64/boot/dts/rockchip/rk3368-r88.dts| 5 +
arch/arm64/boot/dts/rockchip/rk3368.dtsi | 3 ---
8 files changed, 31 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi
b/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi
index 87fabc64cc39..15d1fc541c38 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi
@@ -8,6 +8,10 @@
#include "rk3368.dtsi"
/ {
+ aliases {
+ mmc0 =
+ };
+
chosen {
stdout-path = "serial2:115200n8";
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts
b/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts
index 46357d1d77cd..62aa97a0b8c9 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3368-geekbox.dts
@@ -11,6 +11,10 @@ / {
model = "GeekBox";
compatible = "geekbuying,geekbox", "rockchip,rk3368";
+ aliases {
+ mmc0 =
+ };
+
chosen {
stdout-path = "serial2:115200n8";
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts
b/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts
index f3a397b7eba0..b508b16657d6 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts
@@ -10,6 +10,10 @@ / {
model = "Theobroma Systems RK3368-uQ7 Baseboard";
compatible = "tsd,rk3368-lion-haikou", "rockchip,rk3368";
+ aliases {
+ mmc1 =
+ };
+
chosen {
stdout-path = "serial0:115200n8";
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi
b/arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi
index 2ae5fb4c8516..51da69cfcdde 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi
@@ -7,6 +7,10 @@
#include "rk3368.dtsi"
/ {
+ aliases {
+ mmc0 =
+ };
+
chosen {
stdout-path = "serial0:115200n8";
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts
b/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts
index ecce16ecc9c3..3ebe15e03cf4 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts
@@ -11,6 +11,11 @@ / {
model = "Rockchip Orion R68";
compatible = "tronsmart,orion-r68-meta", "rockchip,rk3368";
+ aliases {
+ mmc0 =
+ mmc1 =
+ };
+
chosen {
stdout-path = "serial2:115200n8";
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts
b/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts
index 5ffd7b4d3036..5ccaa5f7a370 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts
@@ -11,6 +11,11 @@ / {
model = "Rockchip PX5 EVB";
compatible = "rockchip,px5-evb", "rockchip,px5", "rockchip,rk3368";
+ aliases {
+ mmc0 =
+ mmc1 =
+ };
+
chosen {
stdout-path = "serial4:115200n8";
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3368-r88.dts
b/arch/arm64/boot/dts/rockchip/rk3368-r88.dts
index 2582fa4b90e2..959d3cc801f2 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368-r88.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3368-r88.dts
@@ -11,6 +11,11 @@ / {
model = "Rockchip R88";
compatible = "rockchip,r88", "rockchip,rk3368";
+ aliases {
+ mmc0 =
+ mmc1 =
+ };
+
chosen {
stdout-path = "serial2:115200n8";
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index 789b1197fe28..d85242a6a40c 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -26,9 +26,6 @@ aliases {
i2c3 =
i2c4 =
i2c5 =
- mmc0 =
- mmc1 =
- mmc2 =
serial0 =
serial1 =
serial2 =
--
2.29.2
[PATCH 4/7] arm64: dts: rockchip: move mmc aliases to board dts on rk3308
From: Heiko Stuebner
As suggested by Arnd Bergmann, the newly added mmc aliases
should be board specific, so move them from the general dtsi
to the individual boards.
Suggested-by: Arnd Bergmann
Signed-off-by: Heiko Stuebner
---
arch/arm64/boot/dts/rockchip/rk3308-roc-cc.dts | 6 ++
arch/arm64/boot/dts/rockchip/rk3308.dtsi | 3 ---
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3308-roc-cc.dts
b/arch/arm64/boot/dts/rockchip/rk3308-roc-cc.dts
index 7a96be10eaf0..34742c3a 100644
--- a/arch/arm64/boot/dts/rockchip/rk3308-roc-cc.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3308-roc-cc.dts
@@ -9,6 +9,12 @@
/ {
model = "Firefly ROC-RK3308-CC board";
compatible = "firefly,roc-rk3308-cc", "rockchip,rk3308";
+
+ aliases {
+ mmc0 =
+ mmc1 =
+ };
+
chosen {
stdout-path = "serial2:150n8";
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi
b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
index 3a035a189450..4ea32e8f33d2 100644
--- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
@@ -24,9 +24,6 @@ aliases {
i2c1 =
i2c2 =
i2c3 =
- mmc0 =
- mmc1 =
- mmc2 =
serial0 =
serial1 =
serial2 =
--
2.29.2
Re: [PATCH v6 1/2] dt-bindings: Add doc for FriendlyARM NanoPi R4S
On Fri, 19 Mar 2021 13:16:26 +0800, Tianling Shen wrote: > Add devicetree binding documentation for the FriendlyARM NanoPi R4S. > > Changes in v6: > - Fixed format of LED nodes > > Changes in v5: > - Dropped the empty PCIe node > - Dropped useless `/delete-property/` > - Renamed LED nodes > > [...] Applied, thanks! [1/2] dt-bindings: Add doc for FriendlyARM NanoPi R4S commit: 1003888415e83e15ddb63d1d96189b4f2c5f1d48 [2/2] rockchip: rk3399: Add support for FriendlyARM NanoPi R4S commit: db792e9adbf85ffc9d6b0b060ac3c8e3148c8992 Best regards, -- Heiko Stuebner
Re: [PATCH v5 0/4] clk: rockchip: add clock controller for rk3568
On Mon, 15 Mar 2021 16:56:04 +0800, Elaine Zhang wrote:
> Add the clock tree definition for the new rk3568 SoC.
>
> Change in V5:
> [PATCH v5 1/4]: No change.
> [PATCH v5 2/4]: No change.
> [PATCH v5 3/4]: fix up the warning:
> >> drivers/clk/rockchip/clk-rk3188.c:187:67: warning:
> >> missing braces around initializer [-Wmissing-braces]
> 187 | static const struct rockchip_cpuclk_reg_data
> rk3188_cpuclk_data = {
> [PATCH v5 4/4]: No change.
>
> [...]
Applied, thanks!
[1/4] dt-binding: clock: Document rockchip, rk3568-cru bindings
commit: 0cd74eec54a3ec34416bab6cc640a88230472078
[2/4] clk: rockchip: add dt-binding header for rk3568
commit: 0865517926660309b796bd9bd5ba6671704733bc
[3/4] clk: rockchip: support more core div setting
commit: a3561e77cf3ca0937227ba13744d84fc46e5eb4b
[4/4] clk: rockchip: add clock controller for rk3568
commit: cf911d89c4c5e225a2a2cfadf1364838154b2202
Best regards,
--
Heiko Stuebner
Re: [PATCH] arm64: dts: rockchip: add infrared receiver node to rockpro64
On Wed, 10 Mar 2021 13:28:21 +0100, Thomas Schneider wrote: > This adds the RockPro64’s infrared receiver to its dtsi. The configuration is > almost the same as on rk3328-rock64, except for the GPIO pins, and thus > adapted > from there. Applied, thanks! [1/1] arm64: dts: rockchip: add infrared receiver node to rockpro64 commit: 7c7f041309f73b05d21980f88f29305255e126ee Best regards, -- Heiko Stuebner
Re: [PATCH] arm64: dts: rockchip: add phandle to timer0 on rk3368
On Tue, 9 Feb 2021 11:34:08 +0100, Heiko Stuebner wrote: > While the kernel doesn't care su much right now, bootloaders like > u-boot need to refine the node on their side, so to make life easier > for everyone add the timer0 phandle for timer0. Applied, thanks! [1/1] arm64: dts: rockchip: add phandle to timer0 on rk3368 commit: 46f86be0fc6900a13bc27138a72cb7188ef6b4be Best regards, -- Heiko Stuebner
Re: [PATCH 1/3] arm64: dts: rockchip: synchronize rk3399 opps with vendor kernel
On Thu, 25 Feb 2021 14:33:20 +0100, Heiko Stuebner wrote: > The vendor-kernel did increase the minimum voltage for some low frequency > opps to 825mV citing stability reasons. So do that in mainline as well > and also use the ranged notation the vendor-kernel switched to, to give > a bit more flexibility for different regulator setups. Applied, thanks! [1/3] arm64: dts: rockchip: synchronize rk3399 opps with vendor kernel commit: 6daae8ff20b8e9d67c282ba37c63e1a7ee3c2206 [2/3] arm64: dts: rockchip: used range'd gpu opps on rk3399 commit: 6d5989a36e60614e12949c6c2dac368b380bf2ca [3/3] arm64: dts: rockchip: drop separate opp table on rk3399-puma commit: b417764daa2d7e1325fe926144ffcb4b2bbd8d25 Best regards, -- Heiko Stuebner
Re: [PATCH v6 1/2] dt-bindings: Add doc for FriendlyARM NanoPi R4S
Hi, Am Freitag, 19. März 2021, 06:16:26 CET schrieb Tianling Shen: > Add devicetree binding documentation for the FriendlyARM NanoPi R4S. > > Changes in v6: > - Fixed format of LED nodes > > Changes in v5: > - Dropped the empty PCIe node > - Dropped useless `/delete-property/` > - Renamed LED nodes > > Changes in v4: > - Correctly dropped `display-subsystem` node > - Dropped meaningless `pwm-fan` node > - Dropped wrong `sdmmc` node > - Disabled `i2c4` and `uart0` as they don't exist in the design > - Format fixes > > Changes in v3: > - Dropped non-existent node `display_subsystem` > > Changes in v2: > - Disable display for NanoPi R4S (reference commit: 74532de460ec) > - Light "sys" LED on NanoPi R4S (reference commit: 833821eeab91) > > Signed-off-by: Tianling Shen In v4 you received a Acked-by: Rob Herring Please pick these up and carry them over into new versions of your patchset. Otherwise Rob would needlessly review things multiple times. Heiko > --- > Documentation/devicetree/bindings/arm/rockchip.yaml | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml > b/Documentation/devicetree/bindings/arm/rockchip.yaml > index c3036f95c7bc..4a6f772c1043 100644 > --- a/Documentation/devicetree/bindings/arm/rockchip.yaml > +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml > @@ -134,6 +134,7 @@ properties: >- friendlyarm,nanopi-m4 >- friendlyarm,nanopi-m4b >- friendlyarm,nanopi-neo4 > + - friendlyarm,nanopi-r4s >- const: rockchip,rk3399 > >- description: GeekBuying GeekBox >
Re: [PATCH] pinctrl: PINCTRL_ROCKCHIP should depend on ARCH_ROCKCHIP
Am Dienstag, 16. März 2021, 14:40:59 CET schrieb Geert Uytterhoeven:
> The Rockchip GPIO and pin control modules are only present on Rockchip
> SoCs. Hence add a dependency on ARCH_ROCKCHIP, to prevent asking the
> user about this driver when configuring a kernel without Rockchip
> platform support.
>
> Note that before, the PINCTRL_ROCKCHIP symbol was not visible, and
> automatically selected when needed. By making it tristate and
> user-selectable, it became visible for everyone.
>
> Fixes: be786ac5a6c4bf4e ("pinctrl: rockchip: make driver be tristate module")
> Signed-off-by: Geert Uytterhoeven
Reviewed-by: Heiko Stuebner
Re: [PATCH] drm/rockchip: Cope with endpoints that haven't been registered yet
Hi Jonathan,
Am Dienstag, 16. März 2021, 19:27:53 CET schrieb Jonathan McDowell:
> The Rockchip RGB CRTC output driver attempts to avoid probing Rockchip
> subdrivers to see if they're a connected panel or bridge. However part
> of its checks assumes that if no OF platform device is found then it
> can't be a valid bridge or panel. This causes issues with I2C controlled
> bridges that have not yet been registered to the point they can be
> found.
>
> Change this to return EPROBE_DEFER instead of ENODEV and don't ignore
> such devices. The subsequent call to drm_of_find_panel_or_bridge() will
> return EPROBE_DEFER as well if there's actually a valid device we should
> wait for.
>
> Signed-off-by: Jonathan McDowell
> ---
> drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 8 ++--
> drivers/gpu/drm/rockchip/rockchip_rgb.c | 7 ---
> 2 files changed, 10 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
> b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
> index 212bd87c0c4a..b0d63a566501 100644
> --- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
> +++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
> @@ -270,11 +270,15 @@ int rockchip_drm_endpoint_is_subdriver(struct
> device_node *ep)
> if (!node)
> return -ENODEV;
>
> - /* status disabled will prevent creation of platform-devices */
> + /*
> + * status disabled will prevent creation of platform-devices,
> + * but equally we can't rely on the driver having been registered
> + * yet (e.g. I2C bridges).
> + */
> pdev = of_find_device_by_node(node);
> of_node_put(node);
> if (!pdev)
> - return -ENODEV;
> + return -EPROBE_DEFER;
In general, how does that relate to i2c-bridge-drivers, as
of_find_device_by_node supposedly only acts on platform-devices?
Also if that points to a disabled bridge (hdmi, etc) that would likely make
it probe-defer indefinitly, as that device will never become available?
Maybe we could do something like of_device_is_available() which checks
the status property of the node. So something like:
pdev = of_find_device_by_node(node);
if (!pdev) {
bool avail = of_device_is_available(node);
of_node_put(node);
/* if disabled
if (!avail)
return -ENODEV;
else
return -EPROBE_DEFER;
}
of_node_put(node);
Though I still do not understand how that should actually pick up on
i2c devices at all.
Heiko
[PATCH 1/3] arm64: dts: rockchip: synchronize rk3399 opps with vendor kernel
From: Heiko Stuebner
The vendor-kernel did increase the minimum voltage for some low frequency
opps to 825mV citing stability reasons. So do that in mainline as well
and also use the ranged notation the vendor-kernel switched to, to give
a bit more flexibility for different regulator setups.
Signed-off-by: Heiko Stuebner
---
arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi | 32 ++--
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi
b/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi
index d6f1095abb04..20b0d60f7ee3 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi
@@ -10,28 +10,28 @@ cluster0_opp: opp-table0 {
opp00 {
opp-hz = /bits/ 64 <40800>;
- opp-microvolt = <80>;
+ opp-microvolt = <825000 825000 125>;
clock-latency-ns = <4>;
};
opp01 {
opp-hz = /bits/ 64 <6>;
- opp-microvolt = <80>;
+ opp-microvolt = <825000 825000 125>;
};
opp02 {
opp-hz = /bits/ 64 <81600>;
- opp-microvolt = <85>;
+ opp-microvolt = <85 85 125>;
};
opp03 {
opp-hz = /bits/ 64 <100800>;
- opp-microvolt = <925000>;
+ opp-microvolt = <925000 925000 125>;
};
opp04 {
opp-hz = /bits/ 64 <12>;
- opp-microvolt = <100>;
+ opp-microvolt = <100 100 125>;
};
opp05 {
opp-hz = /bits/ 64 <141600>;
- opp-microvolt = <1125000>;
+ opp-microvolt = <1125000 1125000 125>;
};
};
@@ -41,36 +41,36 @@ cluster1_opp: opp-table1 {
opp00 {
opp-hz = /bits/ 64 <40800>;
- opp-microvolt = <80>;
+ opp-microvolt = <825000 825000 125>;
clock-latency-ns = <4>;
};
opp01 {
opp-hz = /bits/ 64 <6>;
- opp-microvolt = <80>;
+ opp-microvolt = <825000 825000 125>;
};
opp02 {
opp-hz = /bits/ 64 <81600>;
- opp-microvolt = <825000>;
+ opp-microvolt = <825000 825000 125>;
};
opp03 {
opp-hz = /bits/ 64 <100800>;
- opp-microvolt = <875000>;
+ opp-microvolt = <875000 875000 125>;
};
opp04 {
opp-hz = /bits/ 64 <12>;
- opp-microvolt = <95>;
+ opp-microvolt = <95 95 125>;
};
opp05 {
opp-hz = /bits/ 64 <141600>;
- opp-microvolt = <1025000>;
+ opp-microvolt = <1025000 1025000 125>;
};
opp06 {
opp-hz = /bits/ 64 <160800>;
- opp-microvolt = <110>;
+ opp-microvolt = <110 110 125>;
};
opp07 {
opp-hz = /bits/ 64 <18>;
- opp-microvolt = <120>;
+ opp-microvolt = <120 120 125>;
};
};
@@ -79,11 +79,11 @@ gpu_opp_table: opp-table2 {
opp00 {
opp-hz = /bits/ 64 <2>;
- opp-microvolt = <80>;
+ opp-microvolt = <825000>;
};
opp01 {
opp-hz = /bits/ 64 <29700>;
- opp-microvolt = <80>;
+ opp-microvolt = <825000>;
};
opp02 {
opp-hz = /bits/ 64 <4>;
--
2.29.2
[PATCH 3/3] arm64: dts: rockchip: drop separate opp table on rk3399-puma
From: Heiko Stuebner
We're using OPPs with a range now, so the fact that the cpu regulator
on puma can't provide the needed 5mV steps requested in the minimal
voltage values can be handled automatically by the opp framework.
Signed-off-by: Heiko Stuebner
---
arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi | 51 ---
1 file changed, 51 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi
b/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi
index 4660416c8f38..6ae9032d85f4 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi
@@ -21,57 +21,6 @@ module_led: led-0 {
};
};
- /*
-* Overwrite the opp-table for CPUB as this board uses a different
-* regulator (FAN53555) that only allows 10mV steps and therefore
-* can't reach the operation point target voltages from rk3399-opp.dtsi
-*/
- /delete-node/ opp-table1;
- cluster1_opp: opp-table1 {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp00 {
- opp-hz = /bits/ 64 <40800>;
- opp-microvolt = <80>;
- clock-latency-ns = <4>;
- };
- opp01 {
- opp-hz = /bits/ 64 <6>;
- opp-microvolt = <80>;
- };
- opp02 {
- opp-hz = /bits/ 64 <81600>;
- opp-microvolt = <83>;
- opp-suspend;
- };
- opp03 {
- opp-hz = /bits/ 64 <100800>;
- opp-microvolt = <88>;
- };
- opp04 {
- opp-hz = /bits/ 64 <12>;
- opp-microvolt = <95>;
- };
- opp05 {
- opp-hz = /bits/ 64 <141600>;
- opp-microvolt = <103>;
- };
- opp06 {
- opp-hz = /bits/ 64 <160800>;
- opp-microvolt = <110>;
- };
- opp07 {
- opp-hz = /bits/ 64 <18>;
- opp-microvolt = <120>;
- };
- opp08 {
- opp-hz = /bits/ 64 <199200>;
- opp-microvolt = <123>;
- turbo-mode;
- };
- };
-
clkin_gmac: external-gmac-clock {
compatible = "fixed-clock";
clock-frequency = <12500>;
--
2.29.2
[PATCH 2/3] arm64: dts: rockchip: used range'd gpu opps on rk3399
From: Heiko Stuebner
Similar to the cpu opps, also use opps with a range on the gpu.
(min, preferred, max). The voltage just needs to be higher than
the minimum and this allows the regulator more freedom if it
can't provide the exact voltage specified, but just say 5mV higher,
as can be seen on rk3399-puma which fails to scale panfrost voltages
nearly completely.
Signed-off-by: Heiko Stuebner
---
arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi
b/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi
index 20b0d60f7ee3..da41cd81ebb7 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi
@@ -79,27 +79,27 @@ gpu_opp_table: opp-table2 {
opp00 {
opp-hz = /bits/ 64 <2>;
- opp-microvolt = <825000>;
+ opp-microvolt = <825000 825000 115>;
};
opp01 {
opp-hz = /bits/ 64 <29700>;
- opp-microvolt = <825000>;
+ opp-microvolt = <825000 825000 115>;
};
opp02 {
opp-hz = /bits/ 64 <4>;
- opp-microvolt = <825000>;
+ opp-microvolt = <825000 825000 115>;
};
opp03 {
opp-hz = /bits/ 64 <5>;
- opp-microvolt = <875000>;
+ opp-microvolt = <875000 875000 115>;
};
opp04 {
opp-hz = /bits/ 64 <6>;
- opp-microvolt = <925000>;
+ opp-microvolt = <925000 925000 115>;
};
opp05 {
opp-hz = /bits/ 64 <8>;
- opp-microvolt = <110>;
+ opp-microvolt = <110 110 115>;
};
};
};
--
2.29.2
Re: [PATCH] drm/panel: kd35t133: allow using non-continuous dsi clock
On Sat, 6 Feb 2021 14:50:20 +0100, Heiko Stuebner wrote:
> The panel is able to work when dsi clock is non-continuous, thus
> the system power consumption can be reduced using such feature.
>
> Add MIPI_DSI_CLOCK_NON_CONTINUOUS to panel's mode_flags.
>
> Also the flag actually becomes necessary after
> commit c6d94e37bdbb ("drm/bridge/synopsys: dsi: add support for
> non-continuous HS clock")
> and without it the panel only emits stripes instead of output.
Applied, thanks!
[1/1] drm/panel: kd35t133: allow using non-continuous dsi clock
commit: 54dab3a718f7094532daf7d25cd14121a0e00e34
Best regards,
--
Heiko Stuebner
Re: [PATCH 0/6] Support second Image Signal Processor on rk3399
Hi Sebastian, Am Samstag, 13. Februar 2021, 12:19:57 CET schrieb Sebastian Fricke: > On 11.02.2021 15:42, Heiko Stübner wrote: > >Am Donnerstag, 11. Februar 2021, 06:25:15 CET schrieb Sebastian Fricke: > >> On 10.02.2021 12:15, Heiko Stübner wrote: > >> >Am Freitag, 5. Februar 2021, 15:55:56 CET schrieb Heiko Stübner: > >> >> I did some tests myself today as well and can confirm your > >> >> hdmi related finding - at least when plugged in on boot. > >> >> > >> >> I tried some combinations of camera vs. hdmi and it seems > >> >> really only when hdmi is plugged in on boot > >> > > >> >as you can see in v2, it should work now even with hdmi > >> >connected on boot. My patch ignored the grf-clock when > >> >doing the grf-based init. > >> > > >> >All clocks are on during boot and I guess the hdmi-driver > >> >did disable it after its probe. The phy_power_on functions > >> >did handle it correctly already, so it was only happening > >> >with hdmi connected on boot. > >> > >> Thank you very much for solving that problem, I've tested the scenarios > >> described below and it works like a charm. (With your V2) > >> > > >> > > >> >Btw. do you plan on submitting your ov13850 driver > >> >soonish? > >> > >> Actually, I have posted the patch already see here: > >> https://patchwork.kernel.org/project/linux-media/patch/20210130182313.32903-2-sebastian.fri...@posteo.net/ > > > >very cool to see > > > >> I currently review the requested changes and questions and will soon > >> post a second version, but I expect quite some time until it is actually > >> merged. > > > >could you Cc me on future versions? > > Sure will do :) by the way, you could also answer the v2 series with a Tested-by: Sebastian Fricke so we get some coverage :-) Thanks Heiko
[PATCH 2/2] phy/rockchip: add Innosilicon-based CSI dphy
From: Heiko Stuebner
The CSI dphy found for example on the rk3326/px30 and rk3368 is based
on an IP design from Innosilicon. Add a driver for it.
Signed-off-by: Heiko Stuebner
---
drivers/phy/rockchip/Kconfig | 9 +
drivers/phy/rockchip/Makefile | 1 +
.../phy/rockchip/phy-rockchip-inno-csidphy.c | 480 ++
3 files changed, 490 insertions(+)
create mode 100644 drivers/phy/rockchip/phy-rockchip-inno-csidphy.c
diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig
index 159285f42e5c..e812adad7242 100644
--- a/drivers/phy/rockchip/Kconfig
+++ b/drivers/phy/rockchip/Kconfig
@@ -48,6 +48,15 @@ config PHY_ROCKCHIP_INNO_USB2
help
Support for Rockchip USB2.0 PHY with Innosilicon IP block.
+config PHY_ROCKCHIP_INNO_CSIDPHY
+ tristate "Rockchip Innosilicon MIPI CSI PHY driver"
+ depends on (ARCH_ROCKCHIP || COMPILE_TEST) && OF
+ select GENERIC_PHY
+ select GENERIC_PHY_MIPI_DPHY
+ help
+ Enable this to support the Rockchip MIPI CSI PHY with
+ Innosilicon IP block.
+
config PHY_ROCKCHIP_INNO_DSIDPHY
tristate "Rockchip Innosilicon MIPI/LVDS/TTL PHY driver"
depends on (ARCH_ROCKCHIP || COMPILE_TEST) && OF
diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile
index c3cfc7f0af5c..f0eec212b2aa 100644
--- a/drivers/phy/rockchip/Makefile
+++ b/drivers/phy/rockchip/Makefile
@@ -2,6 +2,7 @@
obj-$(CONFIG_PHY_ROCKCHIP_DP) += phy-rockchip-dp.o
obj-$(CONFIG_PHY_ROCKCHIP_DPHY_RX0) += phy-rockchip-dphy-rx0.o
obj-$(CONFIG_PHY_ROCKCHIP_EMMC)+= phy-rockchip-emmc.o
+obj-$(CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY)+= phy-rockchip-inno-csidphy.o
obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY)+= phy-rockchip-inno-dsidphy.o
obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI) += phy-rockchip-inno-hdmi.o
obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c
b/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c
new file mode 100644
index ..b30bb2885029
--- /dev/null
+++ b/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c
@@ -0,0 +1,480 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Rockchip MIPI RX Innosilicon DPHY driver
+ *
+ * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* GRF */
+#define RK1808_GRF_PD_VI_CON_OFFSET0x0430
+
+#define RK3326_GRF_PD_VI_CON_OFFSET0x0430
+
+#define RK3368_GRF_SOC_CON6_OFFSET 0x0418
+
+/* PHY */
+#define CSIDPHY_CTRL_LANE_ENABLE 0x00
+#define CSIDPHY_CTRL_LANE_ENABLE_CKBIT(6)
+#define CSIDPHY_CTRL_LANE_ENABLE_LANE3 BIT(5)
+#define CSIDPHY_CTRL_LANE_ENABLE_LANE2 BIT(4)
+#define CSIDPHY_CTRL_LANE_ENABLE_LANE1 BIT(3)
+#define CSIDPHY_CTRL_LANE_ENABLE_LANE0 BIT(2)
+#define CSIDPHY_CTRL_LANE_ENABLE_UNDEFINED BIT(0)
+
+#define CSIDPHY_CTRL_LANE_ENABLE_SHIFT 2
+
+/* not present on all variants */
+#define CSIDPHY_CTRL_PWRCTL0x04
+#define CSIDPHY_CTRL_PWRCTL_UNDEFINED GENMASK(7, 5)
+#define CSIDPHY_CTRL_PWRCTL_SYNCRSTBIT(2)
+#define CSIDPHY_CTRL_PWRCTL_LDO_PD BIT(1)
+#define CSIDPHY_CTRL_PWRCTL_PLL_PD BIT(0)
+
+#define CSIDPHY_CTRL_DIG_RST 0x80
+#define CSIDPHY_CTRL_DIG_RST_UNDEFINED 0x1e
+#define CSIDPHY_CTRL_DIG_RST_RESET BIT(0)
+
+/* offset after ths_settle_offset */
+#define CSIDPHY_CLK_THS_SETTLE 0
+#define CSIDPHY_LANE_THS_SETTLE(n) ((n + 1) * 0x80)
+#define CSIDPHY_THS_SETTLE_MASK0x7f
+
+/* offset after calib_offset */
+#define CSIDPHY_CLK_CALIB_EN 0
+#define CSIDPHY_LANE_CALIB_EN(n) ((n + 1) * 0x80)
+#define CSIDPHY_CALIB_EN BIT(7)
+
+/* Configure the count time of the THS-SETTLE by protocol. */
+#define RK1808_CSIDPHY_CLK_WR_THS_SETTLE 0x160
+#define RK3326_CSIDPHY_CLK_WR_THS_SETTLE 0x100
+#define RK3368_CSIDPHY_CLK_WR_THS_SETTLE 0x100
+
+/* Calibration reception enable */
+#define RK1808_CSIDPHY_CLK_CALIB_EN0x168
+
+#define HIWORD_UPDATE(val, mask) ((val) | (mask) << 16)
+
+enum dphy_reg_id {
+ GRF_DPHY_RX0_TURNDISABLE = 0,
+ GRF_DPHY_RX0_FORCERXMODE,
+ GRF_DPHY_RX0_FORCETXSTOPMODE,
+ GRF_DPHY_RX0_ENABLE,
+ GRF_DPHY_RX0_TURNREQUEST,
+ GRF_DPHY_TX0_TURNDISABLE,
+ GRF_DPHY_TX0_FORCERXMODE,
+ GRF_DPHY_TX0_FORCETXSTOPMODE,
+ GRF_DPHY_TX0_TURNREQUEST,
+ GRF_DPHY_RX1_SRC_SEL,
+ /* rk1808 & rk3326 */
+ GRF_DPHY_CSIPHY_FORCERXMODE,
+ GRF_DPHY_CSIPHY_CLKLANE_EN,
+ GRF_DPHY_CSIPHY_DATALANE_EN,
+};
+
+struct d
[PATCH 1/2] dt-bindings: phy: add yaml binding for rockchip-inno-csi-dphy
From: Heiko Stuebner
Some Rockchip SoCs like the rk3368, rk3326, px30 use a CSI dphy
based on an Innosilicon IP. Add a binding for them.
Signed-off-by: Heiko Stuebner
---
.../bindings/phy/rockchip-inno-csi-dphy.yaml | 79 +++
1 file changed, 79 insertions(+)
create mode 100644
Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml
diff --git a/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml
b/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml
new file mode 100644
index ..b7c5a4027684
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/rockchip-inno-csi-dphy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip SoC MIPI RX0 D-PHY Device Tree Bindings
+
+maintainers:
+ - Heiko Stuebner
+
+description: |
+ The Rockchip SoC has a MIPI CSI D-PHY based on an Innosilicon IP wich
+ connects to the ISP1 (Image Signal Processing unit v1.0) for CSI cameras.
+
+properties:
+ compatible:
+enum:
+ - rockchip,px30-csi-dphy
+ - rockchip,rk1808-csi-dphy
+ - rockchip,rk3326-csi-dphy
+ - rockchip,rk3368-csi-dphy
+
+ reg:
+maxItems: 1
+
+ clocks:
+maxItems: 1
+
+ clock-names:
+const: pclk
+
+ '#phy-cells':
+const: 0
+
+ power-domains:
+description: Video in/out power domain.
+maxItems: 1
+
+ resets:
+items:
+ - description: exclusive PHY reset line
+
+ reset-names:
+items:
+ - const: apb
+
+ rockchip,grf:
+$ref: /schemas/types.yaml#/definitions/phandle
+description:
+ Some additional phy settings are access through GRF regs.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#phy-cells'
+ - power-domains
+ - resets
+ - reset-names
+ - rockchip,grf
+
+additionalProperties: false
+
+examples:
+ - |
+
+csi_dphy: phy@ff2f {
+compatible = "rockchip,px30-csi-dphy";
+reg = <0xff2f 0x4000>;
+clocks = < 1>;
+clock-names = "pclk";
+#phy-cells = <0>;
+power-domains = < 1>;
+resets = < 1>;
+reset-names = "apb";
+rockchip,grf = <>;
+};
--
2.29.2
[PATCH 0/2] phy: rockchip: add Innosilicon-based CSI DPHY
Newer Rockchip SoCs use a different DPHY for camera operation based on an IP block from Innosilicon. This adds a driver for it for px30/rk3326/rk3368/rk1808. Heiko Stuebner (2): dt-bindings: phy: add yaml binding for rockchip-inno-csi-dphy phy/rockchip: add Innosilicon-based CSI dphy .../bindings/phy/rockchip-inno-csi-dphy.yaml | 79 +++ drivers/phy/rockchip/Kconfig | 9 + drivers/phy/rockchip/Makefile | 1 + .../phy/rockchip/phy-rockchip-inno-csidphy.c | 480 ++ 4 files changed, 569 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml create mode 100644 drivers/phy/rockchip/phy-rockchip-inno-csidphy.c -- 2.29.2
[PATCH v2 0/6] Support second Image Signal Processor on rk3399
The rk3399 has two ISPs and right now only the first one is usable. The second ISP is connected to the TXRX dphy on the soc. The phy of ISP1 is only accessible through the DSI controller's io-memory, so this series adds support for simply using the dsi controller is a phy if needed. That solution is needed at least on rk3399 and rk3288 but no-one has looked at camera support on rk3288 at all, so right now only implement the rk3399 specifics. changes in v2: - enable grf-clock also for init callback to not break if for example hdmi is connected on boot and disabled the grf clock during its probe - add Sebastian's Tested-by - add Rob's Ack for the phy-cells property Heiko Stuebner (6): drm/rockchip: dsi: add own additional pclk handling dt-bindings: display: rockchip-dsi: add optional #phy-cells property drm/rockchip: dsi: add ability to work as a phy instead of full dsi arm64: dts: rockchip: add #phy-cells to mipi-dsi1 arm64: dts: rockchip: add cif clk-control pinctrl for rk3399 arm64: dts: rockchip: add isp1 node on rk3399 .../display/rockchip/dw_mipi_dsi_rockchip.txt | 1 + arch/arm64/boot/dts/rockchip/rk3399.dtsi | 39 ++ drivers/gpu/drm/rockchip/Kconfig | 2 + .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 349 ++ 4 files changed, 391 insertions(+) -- 2.29.2
[PATCH 4/6] arm64: dts: rockchip: add #phy-cells to mipi-dsi1
From: Heiko Stuebner
The dsi controller includes access to the dphy which might be used
not only for dsi output but also for csi input on dsi1, so add the
necessary #phy-cells to allow it to be used as phy.
Signed-off-by: Heiko Stuebner
Tested-by: Sebastian Fricke
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index edbbf35fe19e..5d2178cb3e38 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1865,6 +1865,7 @@ mipi_dsi1: mipi@ff968000 {
rockchip,grf = <>;
#address-cells = <1>;
#size-cells = <0>;
+ #phy-cells = <0>;
status = "disabled";
ports {
--
2.29.2
[PATCH 6/6] arm64: dts: rockchip: add isp1 node on rk3399
From: Heiko Stuebner
ISP1 is supplied by the tx1rx1 dphy, that is controlled from
inside the dsi1 controller, so include the necessary phy-link
for it.
Signed-off-by: Heiko Stuebner
Tested-by: Sebastian Fricke
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 26
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 7c661d84df25..98cec9387300 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1756,6 +1756,32 @@ isp0_mmu: iommu@ff914000 {
rockchip,disable-mmu-reset;
};
+ isp1: isp1@ff92 {
+ compatible = "rockchip,rk3399-cif-isp";
+ reg = <0x0 0xff92 0x0 0x4000>;
+ interrupts = ;
+ clocks = < SCLK_ISP1>,
+< ACLK_ISP1_WRAPPER>,
+< HCLK_ISP1_WRAPPER>;
+ clock-names = "isp", "aclk", "hclk";
+ iommus = <_mmu>;
+ phys = <_dsi1>;
+ phy-names = "dphy";
+ power-domains = < RK3399_PD_ISP1>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+ };
+
isp1_mmu: iommu@ff924000 {
compatible = "rockchip,iommu";
reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
--
2.29.2
[PATCH v2 1/6] drm/rockchip: dsi: add own additional pclk handling
From: Heiko Stuebner
In a followup patch, we'll need to access the pclk ourself to enable some
functionality, so get and store it in the rockchip dw-dsi variant as well.
Clocks are refcounted, so possible cascading enablements are
no problem.
Signed-off-by: Heiko Stuebner
Tested-by: Sebastian Fricke
---
drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
index 24a71091759c..18e112e30f6e 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
@@ -223,6 +223,7 @@ struct dw_mipi_dsi_rockchip {
void __iomem *base;
struct regmap *grf_regmap;
+ struct clk *pclk;
struct clk *pllref_clk;
struct clk *grf_clk;
struct clk *phy_cfg_clk;
@@ -1051,6 +1052,13 @@ static int dw_mipi_dsi_rockchip_probe(struct
platform_device *pdev)
return ret;
}
+ dsi->pclk = devm_clk_get(dev, "pclk");
+ if (IS_ERR(dsi->pclk)) {
+ ret = PTR_ERR(dsi->pclk);
+ DRM_DEV_ERROR(dev, "Unable to get pclk: %d\n", ret);
+ return ret;
+ }
+
dsi->pllref_clk = devm_clk_get(dev, "ref");
if (IS_ERR(dsi->pllref_clk)) {
if (dsi->phy) {
--
2.29.2
[PATCH v2 2/6] dt-bindings: display: rockchip-dsi: add optional #phy-cells property
From: Heiko Stuebner The Rockchip DSI controller on some SoCs also controls a bidrectional dphy, which would be connected to an Image Signal Processor as a phy in the rx configuration. So allow a #phy-cells property for the dsi controller. Signed-off-by: Heiko Stuebner Acked-by: Rob Herring Tested-by: Sebastian Fricke --- .../bindings/display/rockchip/dw_mipi_dsi_rockchip.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt index 151be3bba06f..39792f051d2d 100644 --- a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt +++ b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt @@ -23,6 +23,7 @@ Required properties: Optional properties: - phys: from general PHY binding: the phandle for the PHY device. - phy-names: Should be "dphy" if phys references an external phy. +- #phy-cells: Defined when used as ISP phy, should be 0. - power-domains: a phandle to mipi dsi power domain node. - resets: list of phandle + reset specifier pairs, as described in [3]. - reset-names: string reset name, must be "apb". -- 2.29.2
[PATCH 3/6] drm/rockchip: dsi: add ability to work as a phy instead of full dsi
From: Heiko Stuebner
SoCs like the rk3288 and rk3399 have 3 mipi dphys on them. One is TX-
only, one is RX-only and one can be configured to do either TX or RX.
The RX phy is statically connected to the first Image Signal Processor,
the TX phy is statically connected to the first DSI controller and
the TXRX phy is connected to both the second DSI controller as well
as the second ISP.
The RX dphy is controlled externally through registers in the "General
Register Files", while the other two are controlled through the
"Configuration and Test Interface" inside their DSI controller's
io-memory area.
The Rockchip dw-dsi controller already controls these dphys for the
TX case in the driver, but when we want to also allow configuration
for RX to the ISP from the media subsystem we need to expose phy-
functionality instead.
So add a bit of infrastructure to allow the dsi driver to work as a
phy and make sure it can be only one or the other at a time.
Similarly as the dsi-controller will be part of the drm-graph when
active, add an empty component to the drm-graph when in phy-mode
to make the rest of the drm-graph not wait for it.
Signed-off-by: Heiko Stuebner
Tested-by: Sebastian Fricke
---
drivers/gpu/drm/rockchip/Kconfig | 2 +
.../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 341 ++
2 files changed, 343 insertions(+)
diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig
index cb25c0e8fc9b..3094d4533ad6 100644
--- a/drivers/gpu/drm/rockchip/Kconfig
+++ b/drivers/gpu/drm/rockchip/Kconfig
@@ -9,6 +9,8 @@ config DRM_ROCKCHIP
select DRM_ANALOGIX_DP if ROCKCHIP_ANALOGIX_DP
select DRM_DW_HDMI if ROCKCHIP_DW_HDMI
select DRM_DW_MIPI_DSI if ROCKCHIP_DW_MIPI_DSI
+ select GENERIC_PHY if ROCKCHIP_DW_MIPI_DSI
+ select GENERIC_PHY_MIPI_DPHY if ROCKCHIP_DW_MIPI_DSI
select DRM_RGB if ROCKCHIP_RGB
select SND_SOC_HDMI_CODEC if ROCKCHIP_CDN_DP && SND_SOC
help
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
index 18e112e30f6e..e322749a5279 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
@@ -14,6 +14,7 @@
#include
#include
#include
+#include
#include
#include
@@ -125,7 +126,9 @@
#define BANDGAP_AND_BIAS_CONTROL 0x20
#define TERMINATION_RESISTER_CONTROL 0x21
#define AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY0x22
+#define HS_RX_CONTROL_OF_LANE_CLK 0x34
#define HS_RX_CONTROL_OF_LANE_00x44
+#define HS_RX_CONTROL_OF_LANE_10x54
#define HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL0x60
#define HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL0x61
#define HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL0x62
@@ -137,6 +140,9 @@
#define HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL 0x72
#define HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL 0x73
#define HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL0x74
+#define HS_RX_DATA_LANE_THS_SETTLE_CONTROL 0x75
+#define HS_RX_CONTROL_OF_LANE_20x84
+#define HS_RX_CONTROL_OF_LANE_30x94
#define DW_MIPI_NEEDS_PHY_CFG_CLK BIT(0)
#define DW_MIPI_NEEDS_GRF_CLK BIT(1)
@@ -171,11 +177,19 @@
#define RK3399_TXRX_MASTERSLAVEZ BIT(7)
#define RK3399_TXRX_ENABLECLK BIT(6)
#define RK3399_TXRX_BASEDIRBIT(5)
+#define RK3399_TXRX_SRC_SEL_ISP0 BIT(4)
+#define RK3399_TXRX_TURNREQUESTGENMASK(3, 0)
#define HIWORD_UPDATE(val, mask) (val | (mask) << 16)
#define to_dsi(nm) container_of(nm, struct dw_mipi_dsi_rockchip, nm)
+enum {
+ DW_DSI_USAGE_IDLE,
+ DW_DSI_USAGE_DSI,
+ DW_DSI_USAGE_PHY,
+};
+
enum {
BANDGAP_97_07,
BANDGAP_98_05,
@@ -213,6 +227,10 @@ struct rockchip_dw_dsi_chip_data {
u32 lanecfg2_grf_reg;
u32 lanecfg2;
+ int (*dphy_rx_init)(struct phy *phy);
+ int (*dphy_rx_power_on)(struct phy *phy);
+ int (*dphy_rx_power_off)(struct phy *phy);
+
unsigned int flags;
unsigned int max_data_lanes;
};
@@ -236,6 +254,12 @@ struct dw_mipi_dsi_rockchip {
struct phy *phy;
union phy_configure_opts phy_opts;
+ /* being a phy for other mipi hosts */
+ unsigned int usage_mode;
+ struct mutex usage_mutex;
+ struct phy *dphy;
+ struct phy_configure_opts_mipi_dphy dphy_config;
+
unsigned int lane_mbps; /* per lane */
u16 input_div;
u16 feedback_div;
@@ -965,6 +989,17 @@ static int dw_mipi_dsi_rockchip_host_attach(void
*priv_data,
struct device *second;
int ret;
+ mutex_lock(>usage_mutex);
+
+ if (dsi->usage_mode != DW_DSI_USA
[PATCH 5/6] arm64: dts: rockchip: add cif clk-control pinctrl for rk3399
From: Heiko Stuebner
This enables variant a of the clkout signal for camera applications
and also the cifclkin pinctrl setting.
Signed-off-by: Heiko Stuebner
Tested-by: Sebastian Fricke
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 5d2178cb3e38..7c661d84df25 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -2102,6 +2102,18 @@ clk_32k: clk-32k {
};
};
+ cif {
+ cif_clkin: cif-clkin {
+ rockchip,pins =
+ <2 RK_PB2 3 _pull_none>;
+ };
+
+ cif_clkouta: cif-clkouta {
+ rockchip,pins =
+ <2 RK_PB3 3 _pull_none>;
+ };
+ };
+
edp {
edp_hpd: edp-hpd {
rockchip,pins =
--
2.29.2
[PATCH] arm64: dts: rockchip: add phandle to timer0 on rk3368
From: Heiko Stuebner
While the kernel doesn't care su much right now, bootloaders like
u-boot need to refine the node on their side, so to make life easier
for everyone add the timer0 phandle for timer0.
Signed-off-by: Heiko Stuebner
---
arch/arm64/boot/dts/rockchip/rk3368.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index 7af68ec3feae..61b0a2a907f2 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -667,7 +667,7 @@ wdt: watchdog@ff80 {
status = "disabled";
};
- timer@ff81 {
+ timer0: timer@ff81 {
compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
reg = <0x0 0xff81 0x0 0x20>;
interrupts = ;
--
2.29.2
[PATCH] drm/panel: kd35t133: allow using non-continuous dsi clock
The panel is able to work when dsi clock is non-continuous, thus
the system power consumption can be reduced using such feature.
Add MIPI_DSI_CLOCK_NON_CONTINUOUS to panel's mode_flags.
Also the flag actually becomes necessary after
commit c6d94e37bdbb ("drm/bridge/synopsys: dsi: add support for non-continuous
HS clock")
and without it the panel only emits stripes instead of output.
Signed-off-by: Heiko Stuebner
---
drivers/gpu/drm/panel/panel-elida-kd35t133.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/panel/panel-elida-kd35t133.c
b/drivers/gpu/drm/panel/panel-elida-kd35t133.c
index bc36aa3c1123..fe5ac3ef9018 100644
--- a/drivers/gpu/drm/panel/panel-elida-kd35t133.c
+++ b/drivers/gpu/drm/panel/panel-elida-kd35t133.c
@@ -265,7 +265,8 @@ static int kd35t133_probe(struct mipi_dsi_device *dsi)
dsi->lanes = 1;
dsi->format = MIPI_DSI_FMT_RGB888;
dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
- MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET;
+ MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET |
+ MIPI_DSI_CLOCK_NON_CONTINUOUS;
drm_panel_init(>panel, >dev, _funcs,
DRM_MODE_CONNECTOR_DSI);
--
2.29.2
Re: [PATCH 1/5] clk: rockchip: add clock ids for PCLK_DPHYRX and PCLK_DPHYTX0 on rk3368
On Fri, 5 Feb 2021 12:04:58 +0100, Heiko Stuebner wrote: > Needed by the mipi dphys. > The naming follows the clock names in the manual. Applied, thanks! [1/5] clk: rockchip: add clock ids for PCLK_DPHYRX and PCLK_DPHYTX0 on rk3368 commit: 0be10b6f68b217876665031f643e571a5661fc9c [2/5] clk: rockchip: use clock ids for PCLK_DPHYRX and PCLK_DPHYTX0 on rk3368 commit: fabb841c5b16721298cfe649b569a4fa40af28a6 [3/5] clk: rockchip: add clock id for SCLK_VIP_OUT on rk3368 commit: 686458aa752362f86d881d7fa4576c9f175b2d9b [4/5] clk: rockchip: use clock id for SCLK_VIP_OUT on rk3368 commit: ed2243e0038b8afdd7726d117da34ee4577e11ad [5/5] clk: rockchip: fix DPHY gate locations on rk3368 commit: 4bc23b3c83c9a3fc0a7dd8f2f11f451aa92c85cd Best regards, -- Heiko Stuebner
[PATCH 3/5] clk: rockchip: add clock id for SCLK_VIP_OUT on rk3368
From: Heiko Stuebner Needed to provide clocks for cameras. Signed-off-by: Heiko Stuebner --- include/dt-bindings/clock/rk3368-cru.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/clock/rk3368-cru.h b/include/dt-bindings/clock/rk3368-cru.h index f89683295935..83c72a163fd3 100644 --- a/include/dt-bindings/clock/rk3368-cru.h +++ b/include/dt-bindings/clock/rk3368-cru.h @@ -78,6 +78,7 @@ #define SCLK_TIMER13 136 #define SCLK_TIMER14 137 #define SCLK_TIMER15 138 +#define SCLK_VIP_OUT 139 #define DCLK_VOP 190 #define MCLK_CRYPTO191 -- 2.29.2
[PATCH 4/5] clk: rockchip: use clock id for SCLK_VIP_OUT on rk3368
From: Heiko Stuebner
Export the vip-out clock via the newly added clock-id.
Signed-off-by: Heiko Stuebner
---
drivers/clk/rockchip/clk-rk3368.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3368.c
b/drivers/clk/rockchip/clk-rk3368.c
index 76fb04120089..61413be48d1a 100644
--- a/drivers/clk/rockchip/clk-rk3368.c
+++ b/drivers/clk/rockchip/clk-rk3368.c
@@ -474,7 +474,7 @@ static struct rockchip_clk_branch rk3368_clk_branches[]
__initdata = {
COMPOSITE_NODIV(0, "vip_src", mux_pll_src_cpll_gpll_p, 0,
RK3368_CLKSEL_CON(21), 15, 1, MFLAGS,
RK3368_CLKGATE_CON(4), 5, GFLAGS),
- COMPOSITE_NOGATE(0, "sclk_vip_out", mux_vip_out_p, 0,
+ COMPOSITE_NOGATE(SCLK_VIP_OUT, "sclk_vip_out", mux_vip_out_p, 0,
RK3368_CLKSEL_CON(21), 14, 1, MFLAGS, 8, 5, DFLAGS),
COMPOSITE_NODIV(SCLK_EDP_24M, "sclk_edp_24m", mux_edp_24m_p, 0,
--
2.29.2
[PATCH 1/5] clk: rockchip: add clock ids for PCLK_DPHYRX and PCLK_DPHYTX0 on rk3368
From: Heiko Stuebner Needed by the mipi dphys. The naming follows the clock names in the manual. Signed-off-by: Heiko Stuebner --- include/dt-bindings/clock/rk3368-cru.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/clock/rk3368-cru.h b/include/dt-bindings/clock/rk3368-cru.h index 0a06c5f514d7..f89683295935 100644 --- a/include/dt-bindings/clock/rk3368-cru.h +++ b/include/dt-bindings/clock/rk3368-cru.h @@ -148,6 +148,8 @@ #define PCLK_VIP 367 #define PCLK_WDT 368 #define PCLK_EFUSE256 369 +#define PCLK_DPHYRX370 +#define PCLK_DPHYTX0 371 /* hclk gates */ #define HCLK_SFC 448 -- 2.29.2
[PATCH 2/5] clk: rockchip: use clock ids for PCLK_DPHYRX and PCLK_DPHYTX0 on rk3368
From: Heiko Stuebner
Export the clocks via the newly added clock-ids.
Signed-off-by: Heiko Stuebner
---
drivers/clk/rockchip/clk-rk3368.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3368.c
b/drivers/clk/rockchip/clk-rk3368.c
index 55443349439b..76fb04120089 100644
--- a/drivers/clk/rockchip/clk-rk3368.c
+++ b/drivers/clk/rockchip/clk-rk3368.c
@@ -818,8 +818,8 @@ static struct rockchip_clk_branch rk3368_clk_branches[]
__initdata = {
* pclk_vio gates
* pclk_vio comes from the exactly same source as hclk_vio
*/
- GATE(0, "pclk_dphyrx", "hclk_vio", CLK_IGNORE_UNUSED,
RK3368_CLKGATE_CON(14), 8, GFLAGS),
- GATE(0, "pclk_dphytx", "hclk_vio", CLK_IGNORE_UNUSED,
RK3368_CLKGATE_CON(14), 8, GFLAGS),
+ GATE(PCLK_DPHYRX, "pclk_dphyrx", "hclk_vio", CLK_IGNORE_UNUSED,
RK3368_CLKGATE_CON(14), 8, GFLAGS),
+ GATE(PCLK_DPHYTX0, "pclk_dphytx0", "hclk_vio", CLK_IGNORE_UNUSED,
RK3368_CLKGATE_CON(14), 8, GFLAGS),
/* pclk_pd_pmu gates */
GATE(PCLK_PMUGRF, "pclk_pmugrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED,
RK3368_CLKGATE_CON(23), 5, GFLAGS),
--
2.29.2
[PATCH 5/5] clk: rockchip: fix DPHY gate locations on rk3368
From: Heiko Stuebner
Fix the register and bits of the DPHY gate locations.
Signed-off-by: Heiko Stuebner
---
drivers/clk/rockchip/clk-rk3368.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3368.c
b/drivers/clk/rockchip/clk-rk3368.c
index 61413be48d1a..9a0dab9448db 100644
--- a/drivers/clk/rockchip/clk-rk3368.c
+++ b/drivers/clk/rockchip/clk-rk3368.c
@@ -818,8 +818,8 @@ static struct rockchip_clk_branch rk3368_clk_branches[]
__initdata = {
* pclk_vio gates
* pclk_vio comes from the exactly same source as hclk_vio
*/
- GATE(PCLK_DPHYRX, "pclk_dphyrx", "hclk_vio", CLK_IGNORE_UNUSED,
RK3368_CLKGATE_CON(14), 8, GFLAGS),
- GATE(PCLK_DPHYTX0, "pclk_dphytx0", "hclk_vio", CLK_IGNORE_UNUSED,
RK3368_CLKGATE_CON(14), 8, GFLAGS),
+ GATE(PCLK_DPHYRX, "pclk_dphyrx", "hclk_vio", CLK_IGNORE_UNUSED,
RK3368_CLKGATE_CON(22), 11, GFLAGS),
+ GATE(PCLK_DPHYTX0, "pclk_dphytx0", "hclk_vio", CLK_IGNORE_UNUSED,
RK3368_CLKGATE_CON(22), 10, GFLAGS),
/* pclk_pd_pmu gates */
GATE(PCLK_PMUGRF, "pclk_pmugrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED,
RK3368_CLKGATE_CON(23), 5, GFLAGS),
--
2.29.2
[PATCH 6/6] arm64: dts: rockchip: add isp1 node on rk3399
From: Heiko Stuebner
ISP1 is supplied by the tx1rx1 dphy, that is controlled from
inside the dsi1 controller, so include the necessary phy-link
for it.
Signed-off-by: Heiko Stuebner
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 26
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 7c661d84df25..98cec9387300 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1756,6 +1756,32 @@ isp0_mmu: iommu@ff914000 {
rockchip,disable-mmu-reset;
};
+ isp1: isp1@ff92 {
+ compatible = "rockchip,rk3399-cif-isp";
+ reg = <0x0 0xff92 0x0 0x4000>;
+ interrupts = ;
+ clocks = < SCLK_ISP1>,
+< ACLK_ISP1_WRAPPER>,
+< HCLK_ISP1_WRAPPER>;
+ clock-names = "isp", "aclk", "hclk";
+ iommus = <_mmu>;
+ phys = <_dsi1>;
+ phy-names = "dphy";
+ power-domains = < RK3399_PD_ISP1>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+ };
+
isp1_mmu: iommu@ff924000 {
compatible = "rockchip,iommu";
reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
--
2.29.2
[PATCH 4/6] arm64: dts: rockchip: add #phy-cells to mipi-dsi1
From: Heiko Stuebner
The dsi controller includes access to the dphy which might be used
not only for dsi output but also for csi input on dsi1, so add the
necessary #phy-cells to allow it to be used as phy.
Signed-off-by: Heiko Stuebner
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index edbbf35fe19e..5d2178cb3e38 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1865,6 +1865,7 @@ mipi_dsi1: mipi@ff968000 {
rockchip,grf = <>;
#address-cells = <1>;
#size-cells = <0>;
+ #phy-cells = <0>;
status = "disabled";
ports {
--
2.29.2
[PATCH 3/6] drm/rockchip: dsi: add ability to work as a phy instead of full dsi
From: Heiko Stuebner
SoCs like the rk3288 and rk3399 have 3 mipi dphys on them. One is TX-
only, one is RX-only and one can be configured to do either TX or RX.
The RX phy is statically connected to the first Image Signal Processor,
the TX phy is statically connected to the first DSI controller and
the TXRX phy is connected to both the second DSI controller as well
as the second ISP.
The RX dphy is controlled externally through registers in the "General
Register Files", while the other two are controlled through the
"Configuration and Test Interface" inside their DSI controller's
io-memory area.
The Rockchip dw-dsi controller already controls these dphys for the
TX case in the driver, but when we want to also allow configuration
for RX to the ISP from the media subsystem we need to expose phy-
functionality instead.
So add a bit of infrastructure to allow the dsi driver to work as a
phy and make sure it can be only one or the other at a time.
Similarly as the dsi-controller will be part of the drm-graph when
active, add an empty component to the drm-graph when in phy-mode
to make the rest of the drm-graph not wait for it.
Signed-off-by: Heiko Stuebner
---
drivers/gpu/drm/rockchip/Kconfig | 2 +
.../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 334 ++
2 files changed, 336 insertions(+)
diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig
index cb25c0e8fc9b..3094d4533ad6 100644
--- a/drivers/gpu/drm/rockchip/Kconfig
+++ b/drivers/gpu/drm/rockchip/Kconfig
@@ -9,6 +9,8 @@ config DRM_ROCKCHIP
select DRM_ANALOGIX_DP if ROCKCHIP_ANALOGIX_DP
select DRM_DW_HDMI if ROCKCHIP_DW_HDMI
select DRM_DW_MIPI_DSI if ROCKCHIP_DW_MIPI_DSI
+ select GENERIC_PHY if ROCKCHIP_DW_MIPI_DSI
+ select GENERIC_PHY_MIPI_DPHY if ROCKCHIP_DW_MIPI_DSI
select DRM_RGB if ROCKCHIP_RGB
select SND_SOC_HDMI_CODEC if ROCKCHIP_CDN_DP && SND_SOC
help
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
index 18e112e30f6e..5988a105c141 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
@@ -14,6 +14,7 @@
#include
#include
#include
+#include
#include
#include
@@ -125,7 +126,9 @@
#define BANDGAP_AND_BIAS_CONTROL 0x20
#define TERMINATION_RESISTER_CONTROL 0x21
#define AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY0x22
+#define HS_RX_CONTROL_OF_LANE_CLK 0x34
#define HS_RX_CONTROL_OF_LANE_00x44
+#define HS_RX_CONTROL_OF_LANE_10x54
#define HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL0x60
#define HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL0x61
#define HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL0x62
@@ -137,6 +140,9 @@
#define HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL 0x72
#define HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL 0x73
#define HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL0x74
+#define HS_RX_DATA_LANE_THS_SETTLE_CONTROL 0x75
+#define HS_RX_CONTROL_OF_LANE_20x84
+#define HS_RX_CONTROL_OF_LANE_30x94
#define DW_MIPI_NEEDS_PHY_CFG_CLK BIT(0)
#define DW_MIPI_NEEDS_GRF_CLK BIT(1)
@@ -171,11 +177,19 @@
#define RK3399_TXRX_MASTERSLAVEZ BIT(7)
#define RK3399_TXRX_ENABLECLK BIT(6)
#define RK3399_TXRX_BASEDIRBIT(5)
+#define RK3399_TXRX_SRC_SEL_ISP0 BIT(4)
+#define RK3399_TXRX_TURNREQUESTGENMASK(3, 0)
#define HIWORD_UPDATE(val, mask) (val | (mask) << 16)
#define to_dsi(nm) container_of(nm, struct dw_mipi_dsi_rockchip, nm)
+enum {
+ DW_DSI_USAGE_IDLE,
+ DW_DSI_USAGE_DSI,
+ DW_DSI_USAGE_PHY,
+};
+
enum {
BANDGAP_97_07,
BANDGAP_98_05,
@@ -213,6 +227,10 @@ struct rockchip_dw_dsi_chip_data {
u32 lanecfg2_grf_reg;
u32 lanecfg2;
+ int (*dphy_rx_init)(struct phy *phy);
+ int (*dphy_rx_power_on)(struct phy *phy);
+ int (*dphy_rx_power_off)(struct phy *phy);
+
unsigned int flags;
unsigned int max_data_lanes;
};
@@ -236,6 +254,12 @@ struct dw_mipi_dsi_rockchip {
struct phy *phy;
union phy_configure_opts phy_opts;
+ /* being a phy for other mipi hosts */
+ unsigned int usage_mode;
+ struct mutex usage_mutex;
+ struct phy *dphy;
+ struct phy_configure_opts_mipi_dphy dphy_config;
+
unsigned int lane_mbps; /* per lane */
u16 input_div;
u16 feedback_div;
@@ -965,6 +989,17 @@ static int dw_mipi_dsi_rockchip_host_attach(void
*priv_data,
struct device *second;
int ret;
+ mutex_lock(>usage_mutex);
+
+ if (dsi->usage_mode != DW_DSI_USAGE_IDLE) {
+
[PATCH 1/6] drm/rockchip: dsi: add own additional pclk handling
From: Heiko Stuebner
In a followup patch, we'll need to access the pclk ourself to enable some
functionality, so get and store it in the rockchip dw-dsi variant as well.
Clocks are refcounted, so possible cascading enablements are
no problem.
Signed-off-by: Heiko Stuebner
---
drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
index 24a71091759c..18e112e30f6e 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
@@ -223,6 +223,7 @@ struct dw_mipi_dsi_rockchip {
void __iomem *base;
struct regmap *grf_regmap;
+ struct clk *pclk;
struct clk *pllref_clk;
struct clk *grf_clk;
struct clk *phy_cfg_clk;
@@ -1051,6 +1052,13 @@ static int dw_mipi_dsi_rockchip_probe(struct
platform_device *pdev)
return ret;
}
+ dsi->pclk = devm_clk_get(dev, "pclk");
+ if (IS_ERR(dsi->pclk)) {
+ ret = PTR_ERR(dsi->pclk);
+ DRM_DEV_ERROR(dev, "Unable to get pclk: %d\n", ret);
+ return ret;
+ }
+
dsi->pllref_clk = devm_clk_get(dev, "ref");
if (IS_ERR(dsi->pllref_clk)) {
if (dsi->phy) {
--
2.29.2
[PATCH 0/6] Support second Image Signal Processor on rk3399
The rk3399 has two ISPs and right now only the first one is usable. The second ISP is connected to the TXRX dphy on the soc. The phy of ISP1 is only accessible through the DSI controller's io-memory, so this series adds support for simply using the dsi controller is a phy if needed. That solution is needed at least on rk3399 and rk3288 but no-one has looked at camera support on rk3288 at all, so right now only implement the rk3399 specifics. Heiko Stuebner (6): drm/rockchip: dsi: add own additional pclk handling dt-bindings: display: rockchip-dsi: add optional #phy-cells property drm/rockchip: dsi: add ability to work as a phy instead of full dsi arm64: dts: rockchip: add #phy-cells to mipi-dsi1 arm64: dts: rockchip: add cif clk-control pinctrl for rk3399 arm64: dts: rockchip: add isp1 node on rk3399 .../display/rockchip/dw_mipi_dsi_rockchip.txt | 1 + arch/arm64/boot/dts/rockchip/rk3399.dtsi | 39 ++ drivers/gpu/drm/rockchip/Kconfig | 2 + .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 342 ++ 4 files changed, 384 insertions(+) -- 2.29.2
[PATCH 2/6] dt-bindings: display: rockchip-dsi: add optional #phy-cells property
From: Heiko Stuebner The Rockchip DSI controller on some SoCs also controls a bidrectional dphy, which would be connected to an Image Signal Processor as a phy in the rx configuration. So allow a #phy-cells property for the dsi controller. Signed-off-by: Heiko Stuebner --- .../bindings/display/rockchip/dw_mipi_dsi_rockchip.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt index 151be3bba06f..39792f051d2d 100644 --- a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt +++ b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt @@ -23,6 +23,7 @@ Required properties: Optional properties: - phys: from general PHY binding: the phandle for the PHY device. - phy-names: Should be "dphy" if phys references an external phy. +- #phy-cells: Defined when used as ISP phy, should be 0. - power-domains: a phandle to mipi dsi power domain node. - resets: list of phandle + reset specifier pairs, as described in [3]. - reset-names: string reset name, must be "apb". -- 2.29.2
[PATCH 5/6] arm64: dts: rockchip: add cif clk-control pinctrl for rk3399
From: Heiko Stuebner
This enables variant a of the clkout signal for camera applications
and also the cifclkin pinctrl setting.
Signed-off-by: Heiko Stuebner
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 5d2178cb3e38..7c661d84df25 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -2102,6 +2102,18 @@ clk_32k: clk-32k {
};
};
+ cif {
+ cif_clkin: cif-clkin {
+ rockchip,pins =
+ <2 RK_PB2 3 _pull_none>;
+ };
+
+ cif_clkouta: cif-clkouta {
+ rockchip,pins =
+ <2 RK_PB3 3 _pull_none>;
+ };
+ };
+
edp {
edp_hpd: edp-hpd {
rockchip,pins =
--
2.29.2
[PATCH v3] usb: dwc2: Fix endpoint direction check in ep_from_windex
From: Heiko Stuebner
dwc2_hsotg_process_req_status uses ep_from_windex() to retrieve
the endpoint for the index provided in the wIndex request param.
In a test-case with a rndis gadget running and sending a malformed
packet to it like:
dev.ctrl_transfer(
0x82, # bmRequestType
0x00, # bRequest
0x, # wValue
0x0001, # wIndex
0x00 # wLength
)
it is possible to cause a crash:
[ 217.533022] dwc2 ff30.usb: dwc2_hsotg_process_req_status:
USB_REQ_GET_STATUS
[ 217.559003] Unable to handle kernel read from unreadable memory at virtual
address 0088
...
[ 218.313189] Call trace:
[ 218.330217] ep_from_windex+0x3c/0x54
[ 218.348565] usb_gadget_giveback_request+0x10/0x20
[ 218.368056] dwc2_hsotg_complete_request+0x144/0x184
This happens because ep_from_windex wants to compare the endpoint
direction even if index_to_ep() didn't return an endpoint due to
the direction not matching.
The fix is easy insofar that the actual direction check is already
happening when calling index_to_ep() which will return NULL if there
is no endpoint for the targeted direction, so the offending check
can go away completely.
Fixes: c6f5c050e2a7 ("usb: dwc2: gadget: add bi-directional endpoint support")
Reported-by: Gerhard Klostermeier
Signed-off-by: Heiko Stuebner
Cc: sta...@vger.kernel.org
---
changes in v3:
- added Reported-by tag
changes in v2:
- remove unused struct dwc2_hsotg_ep *ep;
drivers/usb/dwc2/gadget.c | 8 +---
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c
index 0a0d11151cfb..ad4c94366dad 100644
--- a/drivers/usb/dwc2/gadget.c
+++ b/drivers/usb/dwc2/gadget.c
@@ -1543,7 +1543,6 @@ static void dwc2_hsotg_complete_oursetup(struct usb_ep
*ep,
static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg,
u32 windex)
{
- struct dwc2_hsotg_ep *ep;
int dir = (windex & USB_DIR_IN) ? 1 : 0;
int idx = windex & 0x7F;
@@ -1553,12 +1552,7 @@ static struct dwc2_hsotg_ep *ep_from_windex(struct
dwc2_hsotg *hsotg,
if (idx > hsotg->num_of_eps)
return NULL;
- ep = index_to_ep(hsotg, idx, dir);
-
- if (idx && ep->dir_in != dir)
- return NULL;
-
- return ep;
+ return index_to_ep(hsotg, idx, dir);
}
/**
--
2.29.2
[PATCH v2] usb: dwc2: Fix endpoint direction check in ep_from_windex
From: Heiko Stuebner
dwc2_hsotg_process_req_status uses ep_from_windex() to retrieve
the endpoint for the index provided in the wIndex request param.
In a test-case with a rndis gadget running and sending a malformed
packet to it like:
dev.ctrl_transfer(
0x82, # bmRequestType
0x00, # bRequest
0x, # wValue
0x0001, # wIndex
0x00 # wLength
)
it is possible to cause a crash:
[ 217.533022] dwc2 ff30.usb: dwc2_hsotg_process_req_status:
USB_REQ_GET_STATUS
[ 217.559003] Unable to handle kernel read from unreadable memory at virtual
address 0088
...
[ 218.313189] Call trace:
[ 218.330217] ep_from_windex+0x3c/0x54
[ 218.348565] usb_gadget_giveback_request+0x10/0x20
[ 218.368056] dwc2_hsotg_complete_request+0x144/0x184
This happens because ep_from_windex wants to compare the endpoint
direction even if index_to_ep() didn't return an endpoint due to
the direction not matching.
The fix is easy insofar that the actual direction check is already
happening when calling index_to_ep() which will return NULL if there
is no endpoint for the targeted direction, so the offending check
can go away completely.
Fixes: c6f5c050e2a7 ("usb: dwc2: gadget: add bi-directional endpoint support")
Signed-off-by: Heiko Stuebner
Cc: sta...@vger.kernel.org
---
changes in v2:
- remove unused struct dwc2_hsotg_ep *ep;
drivers/usb/dwc2/gadget.c | 8 +---
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c
index 0a0d11151cfb..ad4c94366dad 100644
--- a/drivers/usb/dwc2/gadget.c
+++ b/drivers/usb/dwc2/gadget.c
@@ -1543,7 +1543,6 @@ static void dwc2_hsotg_complete_oursetup(struct usb_ep
*ep,
static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg,
u32 windex)
{
- struct dwc2_hsotg_ep *ep;
int dir = (windex & USB_DIR_IN) ? 1 : 0;
int idx = windex & 0x7F;
@@ -1553,12 +1552,7 @@ static struct dwc2_hsotg_ep *ep_from_windex(struct
dwc2_hsotg *hsotg,
if (idx > hsotg->num_of_eps)
return NULL;
- ep = index_to_ep(hsotg, idx, dir);
-
- if (idx && ep->dir_in != dir)
- return NULL;
-
- return ep;
+ return index_to_ep(hsotg, idx, dir);
}
/**
--
2.29.2
Re: [PATCH] arm64: dts: rockchip: more user friendly name of sound nodes
On Mon, 11 Jan 2021 00:19:13 +0900, Katsuhiro Suzuki wrote: > This patch changes device name to more user friendly name of > Analog and SPDIF sound nodes for rk3399-rockpro64. Applied, thanks! [1/1] arm64: dts: rockchip: more user friendly name of sound nodes commit: 5b295839ba3cd78f4142699b8bebc1f23af9a49d Best regards, -- Heiko Stuebner
Re: [PATCH] arm64: dts: rockchip: fix ranges property format for rk3399 pcie node
On Fri, 22 Jan 2021 18:12:43 +0100, Johan Jonker wrote: > A test with the command below gives for example this error: > /arch/arm64/boot/dts/rockchip/rk3399-evb.dt.yaml: pcie@f800: > ranges: 'oneOf' conditional failed, one must be fixed: > > The pcie ranges property is an array. The dt-check expects that > each array item is wrapped with angle brackets, so fix that ranges > property format for the rk3399 pcie node. > > [...] Applied, thanks! [1/1] arm64: dts: rockchip: fix ranges property format for rk3399 pcie node commit: 6b8cc4b3e4c6a968fca48c3ef6477db755a78a3f Best regards, -- Heiko Stuebner
Re: [PATCH v2] arm64: dts: rockchip: cleanup cpu_thermal node of rk3399-rock960.dts
On Mon, 18 Jan 2021 19:00:54 +0100, Johan Jonker wrote: > The cpu_thermal node in the rk3399-rock960.dts file does not > reference _thermal directly to add the board-specific parts, > but also repeats all the SoC default properties. > Clean the whole thing up and fix alignment. > Place new nodes in the correct alphabetical order. > Compered to rk3399.dtsi the temperature property in > cpu_alert0 changes from <7> to <65000>. > A sustainable-power property was added. > The trip property in cooling map0 points to <_alert1> > instead of <_alert0>. Applied, thanks! [1/1] arm64: dts: rockchip: cleanup cpu_thermal node of rk3399-rock960.dts commit: 376e46b5dd0ad9d06f029bbc4a66dd25dd059597 Best regards, -- Heiko Stuebner
Re: (subset) [PATCH 1/5] ARM: dts: rockchip: assign a fixed index to mmc devices on rk322x boards
On Mon, 18 Jan 2021 16:52:38 +0100, Johan Jonker wrote: > Recently introduced async probe on mmc devices can shuffle block IDs. > Pin them to fixed values to ease booting in environments where UUIDs are > not practical. Use newly introduced aliases for mmcblk devices from [1]. > The sort order is based on reg address. > > [1] https://patchwork.kernel.org/patch/11747669/ Applied, thanks! [1/5] ARM: dts: rockchip: assign a fixed index to mmc devices on rk322x boards commit: 94e8a5f6d0dee8e81bdcef6d3e86a027459df225 [2/5] ARM: dts: rockchip: assign a fixed index to mmc devices on rv1108 boards commit: 1034e2b6b8435758c0d699b77761365fd09a5f4a Patches 3-5 as well, just before didn't like the separate branches Best regards, -- Heiko Stuebner
Re: [PATCH] arm64: dts: rockchip: rename pinctrl nodename to gmac2io for nanopi-r2s board
On Sun, 10 Jan 2021 20:48:51 +0100, Johan Jonker wrote: > A test with the command below gives this error: > /arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dt.yaml: > ethernet-phy: 'reg' is a required property > > The pinctrl nodename "ethernet-phy" conflicts with the rules > in the "ethernet-phy.yaml" document, so rename it to "gmac2io". > > [...] Applied, thanks! [1/1] arm64: dts: rockchip: rename pinctrl nodename to gmac2io for nanopi-r2s board commit: 16459ecac6d6bf6a817d9c0cf78d696461fdcd26 Best regards, -- Heiko Stuebner
Re: (subset) [PATCH v4 0/4] arm64: rockchip: Fix PCIe ep-gpios requirement and Add Nanopi M4B
On Fri, 22 Jan 2021 00:23:17 +0800, Chen-Yu Tsai wrote: > This is v4 of my Nanopi M4B series. > > Changes since v3 include: > > - Directly return dev_err_probe() instead of having a separate return > statement > > [...] Applied, thanks! [3/4] arm64: dts: rockchip: nanopi4: Move ep-gpios property to nanopc-t4 commit: 3503376d6cc385b6266f93c24ead9a33d8dfe8cb [4/4] arm64: dts: rockchip: rk3399: Add NanoPi M4B commit: c7b03115003f7f337ab165542cee37148cf30a8a Best regards, -- Heiko Stuebner
Re: (subset) [PATCH 00/20] Rid W=1 warnings from Clock
On Wed, 20 Jan 2021 09:30:20 +, Lee Jones wrote: > This set is part of a larger effort attempting to clean-up W=1 > kernel builds, which are currently overwhelmingly riddled with > niggly little warnings. > > We should have these nailed in ~2 patchsets. > > Lee Jones (20): > clk: rockchip: clk: Demote non-conformant kernel-doc headers > clk: rockchip: clk-cpu: Remove unused/undocumented struct members > clk: rockchip: clk-pll: Demote kernel-doc abuses to standard comment > blocks > clk: rockchip: clk-half-divider: Demote non-conformant kernel-doc > header > clk: bcm: clk-iproc-pll: Demote kernel-doc abuse > clk: sifive: fu540-prci: Declare static const variable > 'prci_clk_fu540' where it's used > clk: socfpga: clk-pll: Remove unused variable 'rc' > clk: socfpga: clk-pll-a10: Remove set but unused variable 'rc' > clk: mvebu: ap-cpu-clk: Demote non-conformant kernel-doc header > clk: imx: clk-imx31: Remove unused static const table 'uart_clks' > clk: st: clkgen-pll: Demote unpopulated kernel-doc header > clk: st: clkgen-fsyn: Fix worthy struct documentation demote partially > filled one > clk: ti: clockdomain: Fix description for 'omap2_init_clk_clkdm's hw > param > clk: sunxi: clk-sunxi: Demote a bunch of non-conformant kernel-doc > headers > clk: ti: dpll: Fix misnaming of '_register_dpll()'s 'user' parameter > clk: ti: gate: Fix possible doc-rot in > 'omap36xx_gate_clk_enable_with_hsdiv_restore' > clk: sunxi: clk-a10-ve: Demote obvious kernel-doc abuse > clk: sunxi: clk-mod0: Demote non-conformant kernel-doc header > clk: versatile: clk-icst: Fix worthy struct documentation block > clk: zynq: clkc: Remove various instances of an unused variable 'clk' > > [...] Applied, thanks! [01/20] clk: rockchip: clk: Demote non-conformant kernel-doc headers commit: 415173712003ad7e54de7198979d68a428440ed6 [02/20] clk: rockchip: clk-cpu: Remove unused/undocumented struct members commit: 274ae6da4b3275fea32f0807e6e20715695dd210 [03/20] clk: rockchip: clk-pll: Demote kernel-doc abuses to standard comment blocks commit: eee7b95589e61bd7250cada52ddd8039c63535ef [04/20] clk: rockchip: clk-half-divider: Demote non-conformant kernel-doc header commit: d48fbef962b095f7cc22017642fb9055d57fdb53 Best regards, -- Heiko Stuebner
Re: [PATCH] arm64: dts: rockchip: add device_type property to rk3399 pcie node
Am Freitag, 22. Januar 2021, 19:05:59 CET schrieb Johan Jonker: > A test with the command below gives for example this error: > /arch/arm64/boot/dts/rockchip/rk3399-rock960.dt.yaml: > pcie@f800: 'device_type' is a required property > > Fix this by adding a device_type property to the rk3399 pcie node. > > make ARCH=arm64 dtbs_check > DT_SCHEMA_FILES=~/.local/lib/python3.5/site-packages/dtschema/ > schemas/pci/pci-bus.yaml > > Signed-off-by: Johan Jonker already done in https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git/commit/?h=v5.11-armsoc/dtsfixes=43f20b1c6140896916f4e91aacc166830a7ba849
Re: [PATCH 1/8] dt-binding: watchdog: add more Rockchip compatibles to snps,dw-wdt.yaml
Hi Guenter, Am Samstag, 23. Januar 2021, 18:34:01 CET schrieb Guenter Roeck: > On Fri, Dec 18, 2020 at 01:05:27PM +0100, Johan Jonker wrote: > > The watchdog compatible strings are suppose to be SoC orientated. > > In the more recently added Rockchip SoC dtsi files only > > the fallback string "snps,dw-wdt" is used, so add the following > > compatible strings: > > > > "rockchip,px30-wdt", "snps,dw-wdt" > > "rockchip,rk3228-wdt", "snps,dw-wdt" > > "rockchip,rk3308-wdt", "snps,dw-wdt" > > "rockchip,rk3328-wdt", "snps,dw-wdt" > > "rockchip,rk3399-wdt", "snps,dw-wdt" > > "rockchip,rv1108-wdt", "snps,dw-wdt" > > > > make ARCH=arm dtbs_check > > DT_SCHEMA_FILES=Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml > > > > make ARCH=arm64 dtbs_check > > DT_SCHEMA_FILES=Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml > > > > Signed-off-by: Johan Jonker > > Acked-by: Rob Herring > > Reviewed-by: Heiko Stuebner > > Reviewed-by: Guenter Roeck just to clarify, do you expect me to pick up the dt-binding patch with the devicetree patches or do you want to take this individual patch through the watchdog tree instead? Thanks Heiko > > --- > > Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml | 6 ++ > > 1 file changed, 6 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml > > b/Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml > > index f7ee9229c..b58596b18 100644 > > --- a/Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml > > +++ b/Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml > > @@ -18,10 +18,16 @@ properties: > >- const: snps,dw-wdt > >- items: > >- enum: > > + - rockchip,px30-wdt > >- rockchip,rk3066-wdt > >- rockchip,rk3188-wdt > > + - rockchip,rk3228-wdt > >- rockchip,rk3288-wdt > > + - rockchip,rk3308-wdt > > + - rockchip,rk3328-wdt > >- rockchip,rk3368-wdt > > + - rockchip,rk3399-wdt > > + - rockchip,rv1108-wdt > >- const: snps,dw-wdt > > > >reg: >
[PATCH] usb: dwc2: Fix endpoint direction check in ep_from_windex
From: Heiko Stuebner
dwc2_hsotg_process_req_status uses ep_from_windex() to retrieve
the endpoint for the index provided in the wIndex request param.
In a test-case with a rndis gadget running and sending a malformed
packet to it like:
dev.ctrl_transfer(
0x82, # bmRequestType
0x00, # bRequest
0x, # wValue
0x0001, # wIndex
0x00 # wLength
)
it is possible to cause a crash:
[ 217.533022] dwc2 ff30.usb: dwc2_hsotg_process_req_status:
USB_REQ_GET_STATUS
[ 217.559003] Unable to handle kernel read from unreadable memory at virtual
address 0088
...
[ 218.313189] Call trace:
[ 218.330217] ep_from_windex+0x3c/0x54
[ 218.348565] usb_gadget_giveback_request+0x10/0x20
[ 218.368056] dwc2_hsotg_complete_request+0x144/0x184
This happens because ep_from_windex wants to compare the endpoint
direction even if index_to_ep() didn't return an endpoint due to
the direction not matching.
The fix is easy insofar that the actual direction check is already
happening when calling index_to_ep() which will return NULL if there
is no endpoint for the targeted direction, so the offending check
can go away completely.
Fixes: c6f5c050e2a7 ("usb: dwc2: gadget: add bi-directional endpoint support")
Signed-off-by: Heiko Stuebner
Cc: sta...@vger.kernel.org
---
drivers/usb/dwc2/gadget.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c
index 70ac47a341ac..a68c01b1dd73 100644
--- a/drivers/usb/dwc2/gadget.c
+++ b/drivers/usb/dwc2/gadget.c
@@ -1553,12 +1553,7 @@ static struct dwc2_hsotg_ep *ep_from_windex(struct
dwc2_hsotg *hsotg,
if (idx > hsotg->num_of_eps)
return NULL;
- ep = index_to_ep(hsotg, idx, dir);
-
- if (idx && ep->dir_in != dir)
- return NULL;
-
- return ep;
+ return index_to_ep(hsotg, idx, dir);
}
/**
--
2.29.2
Re: [PATCH v2 0/3] arm64: rockchip: rk3328: Add Radxa ROCK Pi E
On Sun, 17 Jan 2021 18:07:07 +0800, Chen-Yu Tsai wrote: > This is v2 of my ROCK Pi E support series. > > Changes since v1: > > - Picked up Rob's Ack for the binding > - Dropped comment about LED color > - Dropped max-frequency from emmc node > - Changed pingroup name from "ethernet-phy" to "ephy" to avoid DT binding > check failure > - Dropped cap-mmc-highspeed from sdmmc node > - Fixed regulator properties to have consistent ordering > - Added adc-key for recovery button > - Sorted header files > > [...] Applied, thanks! [1/3] arm64: dts: rockchip: rk3328: Add clock_in_out property to gmac2phy node commit: c6433083f5930fdf52ad47c8c0459719c810dc89 [2/3] dt-bindings: arm: rockchip: Add Radxa ROCK Pi E commit: 31b8e8592f6663c0937d1408f1fd6ed566fbde5c [3/3] arm64: dts: rockchip: rk3328: Add Radxa ROCK Pi E commit: b918e81f2145967f0cadfe9ede38c69c1796fe09 Best regards, -- Heiko Stuebner
Re: [PATCH] arm64: dts: rockchip: remove interrupt-names property from rk3399 vdec node
On Sun, 17 Jan 2021 19:16:53 +0100, Johan Jonker wrote: > A test with the command below gives this error: > /arch/arm64/boot/dts/rockchip/rk3399-evb.dt.yaml: video-codec@ff66: > 'interrupt-names' does not match any of the regexes: 'pinctrl-[0-9]+' > > The rkvdec driver gets it irq with help of the platform_get_irq() > function, so remove the interrupt-names property from the rk3399 > vdec node. > > [...] Applied, thanks! [1/1] arm64: dts: rockchip: remove interrupt-names property from rk3399 vdec node commit: a6b519f5ccecb0a68af788b07fd85b8e91969a53 Best regards, -- Heiko Stuebner
Re: (subset) [PATCH v16 0/8] Add Rockchip NFC drivers for RK3308 and others
On Thu, 10 Dec 2020 08:21:30 +0800, Yifeng Zhao wrote: > Rockchp's NFC(Nand Flash Controller) has four versions: V600, V622, V800 and > V900.This series patch can support all four versions. > > > Changes in v16: > - Fix some comments about 'ret' variable. > > [...] Applied, thanks! [6/8] arm: dts: rockchip: Add NFC node for RV1108 SoC commit: 2525f194f9dc07c48b0a12697128357068c2e04b [7/8] arm: dts: rockchip: Add NFC node for RK2928 and other SoCs commit: 9c2bfe53b2fc4a8a63311f162e80b27978db6c06 [8/8] arm: dts: rockchip: Add NFC node for RK3036 SoC commit: 4cd9a03435bcd20ce6f524e3826fd263951c22fe Best regards, -- Heiko Stuebner
Re: (subset) [PATCH 1/3] ARM: dts: rockchip: rename thermal subnodes for rk3288.dtsi
On Sun, 17 Jan 2021 16:09:51 +0100, Johan Jonker wrote:
> A test with the command below gives for example this error:
> /arch/arm/boot/dts/rk3288-tinker.dt.yaml:
> thermal-zones: 'cpu_thermal', 'gpu_thermal', 'reserve_thermal'
> do not match any of the regexes:
> '^[a-zA-Z][a-zA-Z0-9\\-]{1,12}-thermal$', 'pinctrl-[0-9]+'
>
> Rename Rockchip rk3288 thermal subnodes
> so that it ends with "-thermal"
>
> [...]
Applied, thanks!
[2/3] arm64: dts: rockchip: rename thermal subnodes for rk3368.dtsi
commit: 7c96a5cf680ac733becd454e1f2fd9b258fb
[3/3] arm64: dts: rockchip: rename thermal subnodes for rk3399.dtsi
commit: e58061b59787270a57839397e50bb4400b9e2de9
Best regards,
--
Heiko Stuebner
Re: [PATCH] drm/panel: panel-simple: add bus-format and connector-type to Innolux n116bge
On Sat, 9 Jan 2021 14:09:51 +0100, Heiko Stuebner wrote: > The Innolux n116bge panel has an eDP connector and 3*6 bits bus format. Applied, thanks! [1/1] drm/panel: panel-simple: add bus-format and connector-type to Innolux n116bge commit: 87969bcd49480508568070fd93d7367f03316aa9 Best regards, -- Heiko Stuebner
Re: [PATCH v2] arm64: dts: rockchip: enable HDMI sound nodes for rk3328-rock64
On Mon, 3 Aug 2020 00:42:31 +0900, Katsuhiro Suzuki wrote: > This patch enables HDMI sound (I2S0) and Analog sound (I2S1) which > are defined in rk3328.dtsi, and replace SPDIF nodes. > > We can use SPDIF pass-through with suitable ALSA settings and on > mpv or other media players. > - Settings: > https://github.com/LibreELEC/LibreELEC.tv/blob/master/projects/Rockchip/filesystem/usr/share/alsa/cards/SPDIF.conf > - Ex.: mpv foo.ac3 --audio-spdif=ac3 > --audio-device='alsa/SPDIF.pcm.iec958.0:SPDIF' > > [...] Applied, thanks! [1/1] arm64: dts: rockchip: enable HDMI sound nodes for rk3328-rock64 commit: 25572fb5aa986bdbb35d06c0fb52a9b9d9b3b2c9 Best regards, -- Heiko Stuebner
Re: [PATCH] arm64: dts: rockchip: assign a fixed index to mmc devices on rk3328 boards
On Sat, 19 Dec 2020 22:05:00 +0100, Johan Jonker wrote: > Recently introduced async probe on mmc devices can shuffle block IDs. > Pin them to fixed values to ease booting in environments where UUIDs > are not practical. Use newly introduced aliases for mmcblk devices from [1]. > > [1] https://patchwork.kernel.org/patch/11747669/ Applied, thanks! [1/1] arm64: dts: rockchip: assign a fixed index to mmc devices on rk3328 boards commit: 221c6c042fa004b73b10780fa2aaf177085e2f3f Best regards, -- Heiko Stuebner
Re: [PATCH v2] arm64: defconfig: Enable REGULATOR_MP8859
On Fri, 31 Jul 2020 21:33:24 +0530, Jagan Teki wrote: > RK3399 boards like ROC-RK3399-PC is using MP8859 DC/DC converter > for 12V supply. > > roc-rk3399-pc initially used 12V fixed regulator for this supply, > but the below commit has switched to use MP8859. > > commit <1fc61ed04d309b0b8b3562acf701ab988eee12de> "arm64: dts: rockchip: > Enable mp8859 regulator on rk3399-roc-pc" > > [...] Applied, thanks! [1/1] arm64: defconfig: Enable REGULATOR_MP8859 commit: 3c8e5d51e4c6e5e93d31f59d4a54fb3a14358ee4 Best regards, -- Heiko Stuebner
Re: [PATCH v2] arm64: dts: rockchip: add SPDIF node for rk3399-rockpro64
On Mon, 10 Aug 2020 18:16:19 +0900, Katsuhiro Suzuki wrote: > This patch adds 'disabled' SPDIF sound node and related settings > for rk3399-rockpro64. > > There are 2 reasons: > - All RK3399 dma-bus channels have been already used by I2S0/1/2 > - RockPro64 does not have SPDIF optical nor coaxial connector, > just have 3pins Applied, thanks! [1/1] arm64: dts: rockchip: add SPDIF node for rk3399-rockpro64 commit: 7f02feb56d9dc8ee2fffe00993f7b9aadd8902ba Best regards, -- Heiko Stuebner
Re: (subset) [PATCH 0/2] ARM: dts: rockchip: minor tweaks for rk3288-miqi.This series adds a missing mali GPU node and two additional CPU opp points
On Fri, 8 Jan 2021 17:10:34 +0200, Demetris Ierokipides wrote: > Demetris Ierokipides (2): > ARM: dts: rockchip: add gpu node to rk3288-miqi > ARM: dts: rockchip: add extra cpu opp points to rk3288-miqi > > arch/arm/boot/dts/rk3288-miqi.dts | 17 + > 1 file changed, 17 insertions(+) Applied, thanks! [1/2] ARM: dts: rockchip: add gpu node to rk3288-miqi commit: 36948ec3d4d0d1b9260d87b550a56fab8d86d17d Best regards, -- Heiko Stuebner
Re: (subset) [PATCH 0/2] PCI: rockchip: Fix PCIe probing in 5.9
On Sat, 15 Aug 2020 13:51:10 +0100, Marc Zyngier wrote: > Recent changes to the way PCI DT nodes are parsed are now enforcing > the presence of a "device_type" property, which has been mandated > since... forever. This has the unfortunate effect of breaking > non-compliant systems, and those using the Rockchip PCIe driver are > amongst the victims. Oh well. > > In order to keep users happy as well as my own machines up and > running, let's paper over the problem by detecting a broken DT from > the driver itself, and inserting the missing property at runtime. > > [...] Applied, thanks! [2/2] arm64: dts: rockchip: Fix PCIe DT properties commit: 43f20b1c6140896916f4e91aacc166830a7ba849 Best regards, -- Heiko Stuebner
Re: (subset) [PATCH v2 1/4] ARM: dts: rockchip: add QoS register compatibles for rk3066/rk3188
On Sun, 6 Dec 2020 11:37:08 +0100, Johan Jonker wrote: > With the conversion of syscon.yaml minItems for compatibles > was set to 2. Current Rockchip dtsi files only use "syscon" for > QoS registers. Add Rockchip QoS compatibles for rk3066/rk3188 > to reduce notifications produced with: > > make ARCH=arm dtbs_check > DT_SCHEMA_FILES=Documentation/devicetree/bindings/mfd/syscon.yaml Applied, thanks! [3/4] arm64: dts: rockchip: add QoS register compatibles for rk3399 commit: bd3fd04910ab5e4d571c19f50c341de175597dfa [4/4] arm64: dts: rockchip: add QoS register compatibles for px30 commit: 6c3ae9f9a133d387ef4e1b4297c9df4e9a1c469d Best regards, -- Heiko Stuebner
Re: [PATCH] arm64: dts: rockchip: Pinebook Pro: Use supported PCIe link speed
On Wed, 30 Sep 2020 14:56:27 -0400, Simon South wrote:
> On Pinebook Pro laptops with an NVMe SSD installed, prevent random
> crashes in the NVMe driver by not attempting to use a PCIe link speed
> higher than that supported by the RK3399 SoC.
>
> See commit 712fa1777207 ("arm64: dts: rockchip: add max-link-speed for
> rk3399").
Applied, thanks!
[1/1] arm64: dts: rockchip: Pinebook Pro: Use supported PCIe link speed
commit: 642fb2795290c4abe629ca34fb8ff6d78baa9fd3
Best regards,
--
Heiko Stuebner
[PATCH] drm/panel: panel-simple: add bus-format and connector-type to Innolux n116bge
From: Heiko Stuebner
The Innolux n116bge panel has an eDP connector and 3*6 bits bus format.
Signed-off-by: Heiko Stuebner
---
drivers/gpu/drm/panel/panel-simple.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-simple.c
b/drivers/gpu/drm/panel/panel-simple.c
index 41bbec72b2da..a0b65d263dce 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -2265,6 +2265,8 @@ static const struct panel_desc innolux_n116bge = {
.width = 256,
.height = 144,
},
+ .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
+ .connector_type = DRM_MODE_CONNECTOR_eDP,
};
static const struct drm_display_mode innolux_n125hce_gn1_mode = {
--
2.29.2
Re: [PATCH] PM: AVS: rockchip-io: Fix error return code in rockchip_iodomain_probe()
On Fri, 4 Dec 2020 16:33:25 +0800, Zhang Changzhong wrote: > Fix to return a negative error code from the error handling > case instead of 0, as done elsewhere in this function. Applied, thanks! [1/1] PM: AVS: rockchip-io: Fix error return code in rockchip_iodomain_probe() commit: c2867b2e710fc85bb39c6f6e5948450c48e8a33e Best regards, -- Heiko Stuebner
Re: [PATCH] arm64: dts: rockchip: rk3328: Fix UART pull-ups
On Fri, 4 Dec 2020 14:48:05 +0800, Chen-Yu Tsai wrote: > For UARTs, the local pull-ups should be on the RX pin, not the TX pin. > UARTs transmit active-low, so a disconnected RX pin should be pulled > high instead of left floating to prevent noise being interpreted as > transmissions. > > This gets rid of bogus sysrq events when the UART console is not > connected. Applied, thanks! [1/1] arm64: dts: rockchip: rk3328: Fix UART pull-ups commit: 94dad6bed3c86c00050bf7c2b2ad6b630facae31 Best regards, -- Heiko Stuebner
Re: (subset) [PATCH v6 0/9] move Rockchip ISP bindings out of staging / add ISP DT nodes for RK3399
On Tue, 20 Oct 2020 16:38:41 -0300, Helen Koike wrote: > Move the bindings out of drivers/staging and place them in > Documentation/devicetree/bindings instead. > > Also, add DT nodes for RK3399 and verify with make ARCH=arm64 dtbs_check > and make ARCH=arm64 dt_binding_check. > > Tested by verifying images streamed from Scarlet Chromebook > > [...] Applied, thanks! [8/9] arm64: dts: rockchip: add isp0 node for rk3399 commit: 97a0115cd96a173369ef30eee2290184921b3f24 [9/9] arm64: dts: rockchip: add isp and sensors for Scarlet commit: ef098edc9c245dd1c150001e22c78e6a3ffd7ff8 Best regards, -- Heiko Stuebner
Re: (subset) [PATCH 1/2] arm64: defconfig: Enable RTC_DRV_HYM8563
On Fri, 23 Oct 2020 23:48:13 +0530, Jagan Teki wrote: > RTC HYM8563 used in the ARM64 Rockchip SoC's SDIO power > sequence enablement. > > Enable it as module. Applied both patches, thanks! Best regards, -- Heiko Stuebner
Re: [PATCH] arm64: dts: rockchip: rk3399-orangepi: Properly define the type C connector.
On Thu, 22 Oct 2020 13:35:32 +0200, Alexis Ballier wrote: > Tested: > - USB3 Gigabit adapter > - USB2 mass storage > > The wiring is the same as the pinebook pro according to the schematics, > thus this patch is heavily based on its dts. Applied, thanks! [1/1] arm64: dts: rockchip: rk3399-orangepi: Properly define the type C connector. commit: e56ed188c83053a505041e1a8ad4fba0f3b39089 Best regards, -- Heiko Stuebner
Re: [PATCH] ARM: dts: rockchip: rename wdt nodename to watchdog in rv1108.dtsi
On Mon, 16 Nov 2020 16:07:56 +0100, Johan Jonker wrote: > A test with the command below gives for example this error: > > /arch/arm/boot/dts/rv1108-evb.dt.yaml: > wdt@1036: $nodename:0: 'wdt@1036' > does not match '^watchdog(@.*|-[0-9a-f])?$' > > Fix it by renaming the wdt nodename to watchdog > in the rv1108.dtsi file. > > [...] Applied, thanks! [1/1] ARM: dts: rockchip: rename wdt nodename to watchdog in rv1108.dtsi commit: 06bccda2c13c07d4ac7ebfef766a968c788cbdbf Best regards, -- Heiko Stuebner
Re: [PATCH] arm64: dts: rockchip: rename sdhci nodename to mmc in rk3399.dtsi
On Mon, 16 Nov 2020 14:23:11 +0100, Johan Jonker wrote: > A test with the command below gives for example this error: > > /arch/arm64/boot/dts/rockchip/rk3399-evb.dt.yaml: > sdhci@fe33: $nodename:0: 'sdhci@fe33' > does not match '^mmc(@.*)?$' > > Fix it by renaming sdhci to mmc. > > [...] Applied, thanks! [1/1] arm64: dts: rockchip: rename sdhci nodename to mmc in rk3399.dtsi commit: 9a9f642784074d09efe9337e64b959f76c9f6913 Best regards, -- Heiko Stuebner
Re: (subset) [PATCH v5 0/7] Enable rk3066a HDMI sound
On Wed, 18 Nov 2020 14:58:15 +0100, Johan Jonker wrote: > First fix some legacy things in clk-rk3188.c that was never updated, > because probably nobody used rk3066a I2S before in the mainline kernel. > Update the rk3066a HDMI documents with a #sound-dai-cells property. > Include the code for sound in the HDMI driver. > Add a simple-sound-card compatible node to rk3066a.dtsi, > because I2S0 and HDMI TX are connected internally. > And as last enable rk3066a HDMI sound in the rk3066a-mk808.dts file. > > [...] Applied, thanks! [1/7] clk: rockchip: add CLK_SET_RATE_PARENT to sclk for rk3066a i2s and uart clocks commit: 5868491e1257786628fdd2457dfb77609f49f91d [2/7] clk: rockchip: fix i2s gate bits on rk3066 and rk3188 commit: caa2fd752ecb80faf7a2e1cdadc737187934675e Best regards, -- Heiko Stuebner
Re: [PATCH 0/3] arm64: dts: rockchip: rk3328-roc-cc: Misc improvements
On Thu, 26 Nov 2020 15:33:33 +0800, Chen-Yu Tsai wrote: > Here are some improvements for the ROC-RK3328-CC. > > Patch 1 sets dr_mode to "host" for OTG. Since the board has a type A > host port wired to the OTG controller, setting this is appropriate. > > Patch 2 enables HDMI audio. > > [...] Applied, thanks! [1/3] arm64: dts: rockchip: rk3328-roc-cc: Set dr_mode to "host" for OTG commit: 4076a007bd0f6171434bdb119a0b8797749b0502 [2/3] arm64: dts: rockchip: rk3328-roc-cc: Enable HDMI audio commit: 65f0b420dea7e70d70cd6ef0f12f9ff81ab90d23 [3/3] arm64: dts: rockchip: rk3328-roc-cc: Enable analog audio commit: 5df4d4d16ce4c6e6a5cb9d4b684b187f28258219 Best regards, -- Heiko Stuebner
Re: [PATCH 0/9] arm64: dts: rockchip: Engicam PX30.Core changes
On Mon, 9 Nov 2020 23:40:08 +0530, Jagan Teki wrote: > Series support Engicam PX30.Core SOM changes along with C.TOUCH > Open Frame 10.1" board. > > All respetive LCD panels are in Mainline already. > > thanks, > Jagan. > > [...] Applied, thanks! [1/9] arm64: dts: rockchip: px30-enagicam: Enable USB Host, OTG commit: 4548ea027c900f1e0f07a292b8e10dc3d2725f44 [2/9] arm64: dts: rockchip: px30-engicam-edimm2.2: Enable LVDS panel commit: 87761edeb2cd90b8251f269eb52c4b48152aace8 [3/9] dt-bindings: arm: rockchip: Add Engicam PX30.Core C.TOUCH 2.0 10.1" OF commit: 23708d46101b5d5538c88b84b764d0ed9d8957ca [4/9] arm64: dts: rockchip: Add Engicam PX30.Core C.TOUCH 2.0 10.1" OF commit: 0e418423be1c824b2cda37fd00528f62231cd219 [5/9] arm64: dts: rockchip: px30-engicam: Add WiFi support commit: 93a4e7d12468b0ab46796f3ed8dc5838dc7f63bc [6/9] arm64: dts: rockchip: px30-engicam: Add BT support commit: 1cc1e851d15b4ebd4c6c5f741cfdb58b988a4445 [7/9] arm64: defconfig: Enable ROCKCHIP_LVDS commit: dbb378a59cb2bdb01454098513d9b61355fbe377 [8/9] arm64: defconfig: Enable PHY_ROCKCHIP_INNO_DSIDPHY commit: ec68a66395d9ccedc9b2b2f6452edfd7cb0fdfd5 [9/9] arm64: defconfig: Enable USB_SERIAL_CP210X commit: cf35bff64f79b4ca8785766d67b608b76404d43f Best regards, -- Heiko Stuebner
Re: [PATCH] clk: rockchip: Remove redundant null check before clk_prepare_enable
On Fri, 27 Nov 2020 09:05:51 +, Xu Wang wrote: > Because clk_prepare_enable() already checked NULL clock parameter, > so the additional check is unnecessary, just remove it. Applied, thanks! [1/1] clk: rockchip: Remove redundant null check before clk_prepare_enable commit: 7f5b57a095f3b9532793d143655e83433bb448af Best regards, -- Heiko Stuebner
Re: [PATCH] drm/rockchip: Avoid uninitialized use of endpoint id in LVDS
On Tue, 10 Nov 2020 21:04:30 +0100, Paul Kocialkowski wrote: > In the Rockchip DRM LVDS component driver, the endpoint id provided to > drm_of_find_panel_or_bridge is grabbed from the endpoint's reg property. > > However, the property may be missing in the case of a single endpoint. > Initialize the endpoint_id variable to 0 to avoid using an > uninitialized variable in that case. Applied, thanks! [1/1] drm/rockchip: Avoid uninitialized use of endpoint id in LVDS commit: aec9fe892812ed10d0bffcf309d2a8fc380d8ce6 Best regards, -- Heiko Stuebner
Re: [PATCH 00/25] Rid W=1 warnings in SoC
On Tue, 3 Nov 2020 15:28:13 +, Lee Jones wrote: > This set is part of a larger effort attempting to clean-up W=1 > kernel builds, which are currently overwhelmingly riddled with > niggly little warnings. > > Lee Jones (25): > soc: bcm: brcmstb: pm: pm-arm: Provide prototype for > brcmstb_pm_s3_finish() > soc: qcom: qcom_aoss: Remove set but unused variable 'tlen' > soc: qcom: qcom_aoss: Add missing description for 'cooling_devs' > soc: fsl: dpio: qbman-portal: Fix a bunch of kernel-doc misdemeanours > soc: rockchip: io-domain: Remove incorrect and incomplete comment > header > soc: ti: knav_qmss_queue: Remove set but unchecked variable 'ret' > soc: ti: knav_qmss_queue: Fix a whole host of function documentation > issues > soc: ti: knav_dma: Fix a kernel function doc formatting issue > soc: ti: pm33xx: Remove set but unused variable 'ret' > soc: ti: wkup_m3_ipc: Document 'm3_ipc' parameter throughout > soc: fsl: qe: qe_common: Fix misnamed function attribute 'addr' > soc: qcom: qcom-geni-se: Fix misnamed function parameter 'rx_rfr' > soc: tegra: fuse: speedo-tegra124: Remove some set but unused > variables > soc: samsung: s3c-pm-check: Fix incorrectly named variable 'val' > soc: qcom: rpmh: Fix possible doc-rot in rpmh_write()'s header > soc: qcom: smem: Fix formatting and missing documentation issues > soc: qcom: smsm: Fix some kernel-doc formatting and naming problems > soc: qcom: wcnss_ctrl: Demote non-conformant struct header and fix > function headers > soc: qcom: smp2p: Remove unused struct attribute provide another > soc: qcom: llcc-qcom: Fix expected kernel-doc formatting > soc: qcom: rpmhpd: Provide some missing struct member descriptions > soc: qcom: kryo-l2-accessors: Fix misnaming of 'val' > soc: ti: k3-ringacc: Provide documentation for 'k3_ring's 'state' > soc: tegra: fuse: speedo-tegra210: Remove a group of set but unused > variables > soc: fsl: qbman: qman: Remove unused variable 'dequeue_wq' > > [...] Applied, thanks! [1/1] soc: rockchip: io-domain: Remove incorrect and incomplete comment header commit: a6a3a24c129d229a0eb26b329ab617e2a04245dd Best regards, -- Heiko Stuebner
Re: [PATCH v4 0/7] arm64: dts: rockchip: Add Engicam PX30.Core
Hi, Am Dienstag, 29. September 2020, 10:32:10 CET schrieb Jagan Teki: > PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. > > PX30.Core needs to mount on top of Engicam baseboards for creating > complete platform boards. > > Possible baseboards are, > - EDIMM2.2 Starter Kit > - C.TOUCH 2.0 Carrier Board > > Changes for v4: > - collect Rob A-b > Changes for v3: > - resolved Johan comments about sorting node properties > - add copyright to Amarula Solutions > - update px30 dtsi author > Changes for v2: > - include C.TOUCH 2.0 carrier board > - skip 10" OF LCD as it requires separate dts with panel support. > > Note: These baseboards can be used for i.MX8 SOM's as well. So having > baseboard on respective SoC seems to be easy rather than making it > common across all. > > Any inputs? > Jagan. > > Jagan Teki (6): > dt-bindings: arm: rockchip: Add Engicam PX30.Core EDIMM2.2 Starter Kit > arm64: dts: rockchip: px30: Add Engicam EDIMM2.2 Starter Kit > arm64: dts: rockchip: Add Engicam PX30.Core EDIMM2.2 Starter Kit > dt-bindings: arm: rockchip: Add Engicam PX30.Core C.TOUCH 2.0 > arm64: dts: rockchip: px30: Add Engicam C.TOUCH 2.0 > arm64: dts: rockchip: Add Engicam PX30.Core C.TOUCH 2.0 > > Michael Trimarchi (1): > arm64: dts: rockchip: Add Engicam PX30.Core SOM I've applied the patches for 5.11 with some changes: (1) engicam,px30-px30-core became engicam,px30-core (2) px30-px30-core.dtsi became px30-engicam-px30-core.dtsi That double px30 is unnecessary and confusing in compatibles and the px30-core thingy needed something less generic, as that is not px30-specific but specific to the engicam boards. Heiko
Re: [PATCH] arm64: dts: rockchip: Reorder LED triggers from mmc devices on rk3399-roc-pc.
On Wed, 4 Nov 2020 20:29:31 +0100, Markus Reichl wrote: > After patch [1] SD-card becomes mmc1 and eMMC becomes mmc2. > Correct trigger of LEDs accordingly. > > [1] > https://patchwork.kernel.org/patch/11881427 Applied, thanks! [1/1] arm64: dts: rockchip: Reorder LED triggers from mmc devices on rk3399-roc-pc. commit: 7327c8b98e2e14c47021eea14d1ab268086a6408 Best regards, -- Heiko Stuebner
Re: [PATCH] arm64: dts: rockchip: add adc joystick to Odroid Go Advance
Am Sonntag, 8. November 2020, 01:31:19 CET schrieb Heiko Stuebner: > On Sat, 4 Jul 2020 00:14:13 +0200, Heiko Stuebner wrote: > > Add the now usable adc-joystick node that describes the analog > > joystick connected to two saradc channels from the rk3326 soc. > > Applied, thanks! > > [1/1] arm64: dts: rockchip: add adc joystick to Odroid Go Advance > commit: c20e6dd9a953d62f14399dabf457dce61dd5611f forgot to add, I fixed the things Johans commented on when applying > > Best regards, >
Re: [PATCH] dt-bindings: arm: rockchip: Add Kobol Helios64
On Mon, 2 Nov 2020 16:06:58 +0100, Uwe Kleine-König wrote: > Document the new board by Kobol introduced recently in > rockchip/rk3399-kobol-helios64.dts. Applied, thanks! [1/1] dt-bindings: arm: rockchip: Add Kobol Helios64 commit: 62dbf80fc581a8eed7288ed7aca24446054eb616 Best regards, -- Heiko Stuebner
Re: [PATCH] arm64: dts: rockchip: Assign a fixed index to mmc devices on rk3399 boards.
On Wed, 4 Nov 2020 17:23:55 +0100, Markus Reichl wrote: > Recently introduced async probe on mmc devices can shuffle block IDs. > Pin them to fixed values to ease booting in environments where UUIDs > are not practical. Use newly introduced aliases for mmcblk devices from [1]. > > [1] > https://patchwork.kernel.org/patch/11747669/ Applied, thanks! [1/1] arm64: dts: rockchip: Assign a fixed index to mmc devices on rk3399 boards. commit: 0011c6d182774fc781fb9e115ebe8baa356029ae Best regards, -- Heiko Stuebner
Re: [PATCH] arm64: dts: rockchip: add adc joystick to Odroid Go Advance
On Sat, 4 Jul 2020 00:14:13 +0200, Heiko Stuebner wrote: > Add the now usable adc-joystick node that describes the analog > joystick connected to two saradc channels from the rk3326 soc. Applied, thanks! [1/1] arm64: dts: rockchip: add adc joystick to Odroid Go Advance commit: c20e6dd9a953d62f14399dabf457dce61dd5611f Best regards, -- Heiko Stuebner
Re: [PATCH v4 0/2] arm64: Add basic support for Kobol's Helios64
On Wed, 14 Oct 2020 22:00:28 +0200, Uwe Kleine-König wrote: > in v3 Johan still found some inconsistencies in how I sorted (or didn't > sort) the device tree properties. The rules I applied now are: > > at the beginning of a node: compatible, reg and interrupt stuff > status and #* at the end > i2c-scl-rising-time-ns before i2c-scl-falling-time-ns > regulator-name first among regulator-* > regulator-min-microvolt before regulator-max-microvolt > pinctrl-names before pinctrl-0 > tx_delay grouped with (and after) rx_delay > vcc12* after vcc5* > otherwise alphabetically > > [...] Applied, thanks! [1/2] dt-bindings: vendor-prefixes: Add kobol prefix commit: fa67f2817ff2c9bb07472d30e58d904922f1a538 [2/2] arm64: dts: rockchip: Add basic support for Kobol's Helios64 commit: 09e006cfb43e8ec38afe28278b210dab72e6cac8 Fixed spaces with tabs in the deleted opp area and inserted a blank between the two cluster blocks. Best regards, -- Heiko Stuebner
Re: [PATCH v3 0/3] PWM backlight interpolation adjustments
On Wed, 21 Oct 2020 22:04:42 -0700, Alexandru Stan wrote: > I was trying to adjust the brightness-levels for the trogdor boards: > https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/2291209 > Like on a lot of panels, trogdor's low end needs to be cropped, > and now that we have the interpolation stuff I wanted to make use of it > and bake in even the curve that's customary to have on chromebooks. > > I found the current behavior of the pwm_bl driver a little unintuitive > and non-linear. See patch 1 for a suggested fix for this. > > [...] Applied, thanks! [1/1] ARM: dts: rockchip: Remove 0 point from brightness-levels on rk3288-veyron commit: 225c59b9235a421cdb219be5fbc13126a49714a6 Best regards, -- Heiko Stuebner
Re: [PATCH] Fix poweroff issue on Odroid Go Advance
On Fri, 23 Oct 2020 20:16:29 +0200, Maciej Matuszczyk wrote: > Applied, thanks! [1/1] arm64: dts: rockchip: Remove system-power-controller from pmic on Odroid Go Advance commit: 01fe332800d0d2f94337b45c1973f4cf28ae6195 Best regards, -- Heiko Stuebner
Re: [PATCH v6 9/9] arm64: dts: rockchip: add isp and sensors for Scarlet
Am Dienstag, 20. Oktober 2020, 21:38:50 CET schrieb Helen Koike:
> From: Eddie Cai
>
> Enable ISP and camera sensor ov2685 and ov5695 for Scarlet Chromebook
>
> Verified with:
> make ARCH=arm64 dtbs_check
>
> Signed-off-by: Shunqian Zheng
> Signed-off-by: Eddie Cai
> Signed-off-by: Tomasz Figa
> Signed-off-by: Helen Koike
> Reviewed-by: Tomasz Figa
looks good, and I'd like to apply this one after the drivers/media-patches
of this series got applied.
Thanks
Heiko
> ---
> .../boot/dts/rockchip/rk3399-gru-scarlet.dtsi | 74 +++
> 1 file changed, 74 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi
> b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi
> index 60cd1c18cd4e0..beee5fbb34437 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi
> @@ -296,6 +296,52 @@ camera: {
>
> /* 24M mclk is shared between world and user cameras */
> pinctrl-0 = <_xfer _clkout1>;
> +
> + /* Rear-facing camera */
> + wcam: camera@36 {
> + compatible = "ovti,ov5695";
> + reg = <0x36>;
> + pinctrl-names = "default";
> + pinctrl-0 = <_rst>;
> +
> + clocks = < SCLK_TESTCLKOUT1>;
> + clock-names = "xvclk";
> +
> + avdd-supply = <_cam>;
> + dvdd-supply = <_cam>;
> + dovdd-supply = <_s0>;
> + reset-gpios = < 5 GPIO_ACTIVE_LOW>;
> +
> + port {
> + wcam_out: endpoint {
> + remote-endpoint = <_in_wcam>;
> + data-lanes = <1 2>;
> + };
> + };
> + };
> +
> + /* Front-facing camera */
> + ucam: camera@3c {
> + compatible = "ovti,ov2685";
> + reg = <0x3c>;
> + pinctrl-names = "default";
> + pinctrl-0 = <_rst>;
> +
> + clocks = < SCLK_TESTCLKOUT1>;
> + clock-names = "xvclk";
> +
> + avdd-supply = <_cam>;
> + dovdd-supply = <_s0>;
> + dvdd-supply = <_s0>;
> + reset-gpios = < 3 GPIO_ACTIVE_LOW>;
> +
> + port {
> + ucam_out: endpoint {
> + remote-endpoint = <_in_ucam>;
> + data-lanes = <1>;
> + };
> + };
> + };
> };
>
> _dp {
> @@ -353,10 +399,38 @@ _domains {
> gpio1830-supply = <_s0>; /* APIO4_VDD; 4c 4d */
> };
>
> + {
> + status = "okay";
> +
> + ports {
> + port@0 {
> + mipi_in_wcam: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <_out>;
> + data-lanes = <1 2>;
> + };
> +
> + mipi_in_ucam: endpoint@1 {
> + reg = <1>;
> + remote-endpoint = <_out>;
> + data-lanes = <1>;
> + };
> + };
> + };
> +};
> +
> +_mmu {
> + status = "okay";
> +};
> +
> {
> sdmode-gpios = < 2 GPIO_ACTIVE_HIGH>;
> };
>
> +_dphy_rx0 {
> + status = "okay";
> +};
> +
> _dsi {
> status = "okay";
> clock-master;
>
Re: [PATCH v6 8/9] arm64: dts: rockchip: add isp0 node for rk3399
Am Dienstag, 20. Oktober 2020, 21:38:49 CET schrieb Helen Koike:
> From: Shunqian Zheng
>
> RK3399 has two ISPs, but only isp0 was tested.
> Add isp0 node in rk3399 dtsi
>
> Verified with:
> make ARCH=arm64 dtbs_check
> DT_SCHEMA_FILES=Documentation/devicetree/bindings/media/rockchip-isp1.yaml
>
> Signed-off-by: Shunqian Zheng
> Signed-off-by: Jacob Chen
> Signed-off-by: Helen Koike
looks good, and I'd like to apply this one after the drivers/media-patches
of this series got applied.
Thanks
Heiko
>
> ---
>
> Changes in v6:
> - Add status = "disabled" in the isp0 node
> ---
> arch/arm64/boot/dts/rockchip/rk3399.dtsi | 26
> 1 file changed, 26 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> index ada724b12f014..af5f8e2c5e64d 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> @@ -1723,6 +1723,32 @@ vopb_mmu: iommu@ff903f00 {
> status = "disabled";
> };
>
> + isp0: isp0@ff91 {
> + compatible = "rockchip,rk3399-cif-isp";
> + reg = <0x0 0xff91 0x0 0x4000>;
> + interrupts = ;
> + clocks = < SCLK_ISP0>,
> + < ACLK_ISP0_WRAPPER>,
> + < HCLK_ISP0_WRAPPER>;
> + clock-names = "isp", "aclk", "hclk";
> + iommus = <_mmu>;
> + phys = <_dphy_rx0>;
> + phy-names = "dphy";
> + power-domains = < RK3399_PD_ISP0>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> + };
> +
> isp0_mmu: iommu@ff914000 {
> compatible = "rockchip,iommu";
> reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
>
Re: [PATCH v4 0/6] clk: rockchip: Support module build
On Mon, 14 Sep 2020 10:22:19 +0800, Elaine Zhang wrote: > Export some APIs for module drivers. > Fix the clock config to support module build. > Fix the clk driver init, add module author, description > and license to support building RK3399 SoC clock driver as module. > > Change in V2: > [PATCH v2 1/6]: remove "clk",and check "hw" isn't an error value. > [PATCH v2 6/6]: store a function pointer in the match data. > > [...] Applied, thanks! [1/6] clk: rockchip: Use clk_hw_register_composite instead of clk_register_composite calls commit: 63207c37eac4f15fdebac14685a315c259c0a780 [2/6] clk: rockchip: Export rockchip_clk_register_ddrclk() commit: f73907de3493b94d80af5122bcacc98f0e7b295b [3/6] clk: rockchip: Export rockchip_register_softrst() commit: 37353491d1a8c207685c138c3640bd43864b70d9 [4/6] clk: rockchip: Export some clock common APIs for module drivers commit: ea650c26611dd61adfcc8647d6144f2c9f453d90 [5/6] clk: rockchip: fix the clk config to support module build commit: 4d98ed1e126495016f2a3ef4db6379855c4aacf2 [6/6] clk: rockchip: rk3399: Support module build commit: 70d839e2761d22eba6facdb3b65faea4d57f355d I did some minor tweaks: - in the Kconfig texts "Rk" -> "RK" - made the rk3399 entry bool in patch 5 so that it stays correct when a bisection lands between patches 5 and 6 - made in tristate in patch6 which adds the rest of module elements Best regards, -- Heiko Stuebner
Re: [PATCH] drm/bridge/synopsys: dsi: fix initialization sequence
Am Freitag, 18. September 2020, 13:46:53 CEST schrieb Yannick Fertre:
> The current driver calls drm_bridge_add(), to add the dsi bridge
> to the global bridge list, in dw_mipi_dsi_host_attach().
> Thus, it relies on the probing of panel or bridge sub-nodes to
> trigger the execution of dsi host attach() that will, in turn,
> call dw_mipi_dsi_host_attach().
> This causes an incomplete driver initialization if the panel or
> the next bridge is not present as sub-node, e.g. because it is an
> i2c device, thus sub-node of the respective i2c controller.
Actually the drm_of_find_panel_or_bridge() works on of-graph nodes,
so having an remote-port pointing to the i2c/spi/whatever driver
should just work - and no need for the driver to be a subnode itself.
And while my memory is fuzzy, I think I remember Andrzej requesting
only registering the bridge once we know something is connected,
aka when it calls dsi_attach.
Heiko
>
> Move the relevant code from host attach() to probe(), and the
> corresponding code from detach() to remove().
>
> Signed-off-by: Antonio Borneo
> Signed-off-by: Yannick Fertre
> ---
> drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 73 ---
> 1 file changed, 48 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> index 6b268f9445b3..aa74abddc79f 100644
> --- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> @@ -314,9 +314,7 @@ static int dw_mipi_dsi_host_attach(struct mipi_dsi_host
> *host,
> {
> struct dw_mipi_dsi *dsi = host_to_dsi(host);
> const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data;
> - struct drm_bridge *bridge;
> - struct drm_panel *panel;
> - int ret;
> + int ret = -ENODEV;
>
> if (device->lanes > dsi->plat_data->max_data_lanes) {
> dev_err(dsi->dev, "the number of data lanes(%u) is too many\n",
> @@ -329,22 +327,6 @@ static int dw_mipi_dsi_host_attach(struct mipi_dsi_host
> *host,
> dsi->format = device->format;
> dsi->mode_flags = device->mode_flags;
>
> - ret = drm_of_find_panel_or_bridge(host->dev->of_node, 1, 0,
> - , );
> - if (ret)
> - return ret;
> -
> - if (panel) {
> - bridge = drm_panel_bridge_add_typed(panel,
> - DRM_MODE_CONNECTOR_DSI);
> - if (IS_ERR(bridge))
> - return PTR_ERR(bridge);
> - }
> -
> - dsi->panel_bridge = bridge;
> -
> - drm_bridge_add(>bridge);
> -
> if (pdata->host_ops && pdata->host_ops->attach) {
> ret = pdata->host_ops->attach(pdata->priv_data, device);
> if (ret < 0)
> @@ -367,10 +349,6 @@ static int dw_mipi_dsi_host_detach(struct mipi_dsi_host
> *host,
> return ret;
> }
>
> - drm_of_panel_bridge_remove(host->dev->of_node, 1, 0);
> -
> - drm_bridge_remove(>bridge);
> -
> return 0;
> }
>
> @@ -1105,6 +1083,9 @@ __dw_mipi_dsi_probe(struct platform_device *pdev,
> struct device *dev = >dev;
> struct reset_control *apb_rst;
> struct dw_mipi_dsi *dsi;
> + struct drm_bridge *bridge;
> + struct drm_panel *panel;
> + int i, nb_endpoints;
> int ret;
>
> dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
> @@ -1172,8 +1153,7 @@ __dw_mipi_dsi_probe(struct platform_device *pdev,
> ret = mipi_dsi_host_register(>dsi_host);
> if (ret) {
> dev_err(dev, "Failed to register MIPI host: %d\n", ret);
> - dw_mipi_dsi_debugfs_remove(dsi);
> - return ERR_PTR(ret);
> + goto err_pmr_enable;
> }
>
> dsi->bridge.driver_private = dsi;
> @@ -1182,11 +1162,54 @@ __dw_mipi_dsi_probe(struct platform_device *pdev,
> dsi->bridge.of_node = pdev->dev.of_node;
> #endif
>
> + /* Get number of endpoints */
> + nb_endpoints = of_graph_get_endpoint_count(pdev->dev.of_node);
> + if (!nb_endpoints) {
> + ret = -ENODEV;
> + goto err_host_reg;
> + }
> +
> + for (i = 1; i < nb_endpoints; i++) {
> + ret = drm_of_find_panel_or_bridge(pdev->dev.of_node, i, 0,
> + , );
> + if (!ret)
> + break;
> + else if (ret == -EPROBE_DEFER)
> + goto err_host_reg;
> + }
> +
> + /* check if an error is returned >> no panel or bridge detected */
> + if (ret)
> + goto err_host_reg;
> +
> + if (panel) {
> + bridge = drm_panel_bridge_add_typed(panel,
> DRM_MODE_CONNECTOR_DSI);
> + if (IS_ERR(bridge)) {
> + ret = PTR_ERR(bridge);
> + goto err_host_reg;
> + }
> + }
> +
> + dsi->panel_bridge = bridge;
> +
> +
