RE: [PATCH 5/5] misc: zynqmp: Add afi config driver
Hi Greg,
Please find my response inline.
> -Original Message-
> From: Greg KH
> Sent: Tuesday, April 20, 2021 2:21 PM
> To: Nava kishore Manne
> Cc: robh...@kernel.org; Michal Simek ; Derek Kiernan
> ; Dragan Cvetic ;
> a...@arndb.de; Rajan Vaja ; Jolly Shah
> ; Tejas Patel ; Amit Sunil
> Dhamne ; devicet...@vger.kernel.org; linux-arm-
> ker...@lists.infradead.org; linux-kernel@vger.kernel.org;
> chinnikishore...@gmail.com; git
> Subject: Re: [PATCH 5/5] misc: zynqmp: Add afi config driver
>
> On Tue, Apr 20, 2021 at 01:41:53PM +0530, Nava kishore Manne wrote:
> > This patch adds zynqmp afi config driver.This is useful for the
> > configuration of the PS-PL interface on Zynq US+ MPSoC platform.
> >
> > Signed-off-by: Nava kishore Manne
> > ---
> > drivers/misc/Kconfig | 11 ++
> > drivers/misc/Makefile | 1 +
> > drivers/misc/zynqmp-afi.c | 83
> > +++
> > 3 files changed, 95 insertions(+)
> > create mode 100644 drivers/misc/zynqmp-afi.c
> >
> > diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index
> > 877b43b3377d..d1ea1eeb3ac1 100644
> > --- a/drivers/misc/Kconfig
> > +++ b/drivers/misc/Kconfig
> > @@ -456,6 +456,17 @@ config ZYNQ_AFI
> > between PS and PL, the AXI port data path should be configured
> > with the proper Bus-width values
> >
> > +config ZYNQMP_AFI
> > +tristate "Xilinx ZYNQMP AFI support"
> > +help
> > + ZynqMP AFI driver support for writing to the AFI registers for
> > + configuring PS_PL Bus-width. Xilinx Zynq US+ MPSoC connect the
> > + PS to the programmable logic (PL) through the AXI port. This AXI
> > + port helps to establish the data path between the PS and PL.
> > + In-order to establish the proper communication path between
> > + PS and PL, the AXI port data path should be configured with
> > + the proper Bus-width values
> > +
> > source "drivers/misc/c2port/Kconfig"
> > source "drivers/misc/eeprom/Kconfig"
> > source "drivers/misc/cb710/Kconfig"
> > diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index
> > e9b03843100f..54bd0edc511e 100644
> > --- a/drivers/misc/Makefile
> > +++ b/drivers/misc/Makefile
> > @@ -57,3 +57,4 @@ obj-$(CONFIG_UACCE) += uacce/
> > obj-$(CONFIG_XILINX_SDFEC) += xilinx_sdfec.o
> > obj-$(CONFIG_HISI_HIKEY_USB) += hisi_hikey_usb.o
> > obj-$(CONFIG_ZYNQ_AFI) += zynq-afi.o
> > +obj-$(CONFIG_ZYNQMP_AFI) += zynqmp-afi.o
> > diff --git a/drivers/misc/zynqmp-afi.c b/drivers/misc/zynqmp-afi.c new
> > file mode 100644 index ..a318652576d2
> > --- /dev/null
> > +++ b/drivers/misc/zynqmp-afi.c
> > @@ -0,0 +1,83 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Xilinx FPGA AFI bridge.
> > + * Copyright (c) 2018-2021 Xilinx Inc.
> > + */
> > +
> > +#include
> > +#include #include
> > +#include #include #include
> > + #include
> > +
> > +/**
> > + * struct zynqmp_afi_fpga - AFI register description
> > + * @value: value to be written to the register
> > + * @regid: Register id for the register to be written
> > + */
> > +struct zynqmp_afi_fpga {
> > + u32 value;
> > + u32 regid;
> > +};
> > +
> > +static int zynqmp_afi_fpga_probe(struct platform_device *pdev)
> > +{
> > + struct zynqmp_afi_fpga *zynqmp_afi_fpga;
> > + struct device_node *np = pdev->dev.of_node;
> > + int i, entries, ret;
> > + u32 reg, val;
> > +
> > + zynqmp_afi_fpga = devm_kzalloc(>dev,
> > + sizeof(*zynqmp_afi_fpga), GFP_KERNEL);
> > + if (!zynqmp_afi_fpga)
> > + return -ENOMEM;
> > + platform_set_drvdata(pdev, zynqmp_afi_fpga);
> > +
> > + entries = of_property_count_u32_elems(np, "config-afi");
> > + if (!entries || (entries % 2)) {
> > + dev_err(>dev, "Invalid number of registers\n");
> > + return -EINVAL;
> > + }
> > +
> > + for (i = 0; i < entries / 2; i++) {
> > + ret = of_property_read_u32_index(np, "config-afi", i * 2,
> );
> > + if (ret) {
> > + dev_err(>dev, "failed to read register\n");
> > + return -EINVAL;
> > + }
> > + ret = of_property_read_u32_index(np, "config-afi", i * 2 + 1,
> > +
RE: [PATCH 5/5] misc: zynqmp: Add afi config driver
Hi Greg, Please find my response inline. > -Original Message- > From: Greg KH > Sent: Tuesday, April 20, 2021 2:18 PM > To: Nava kishore Manne > Cc: robh...@kernel.org; Michal Simek ; Derek Kiernan > ; Dragan Cvetic ; > a...@arndb.de; Rajan Vaja ; Jolly Shah > ; Tejas Patel ; Amit Sunil > Dhamne ; devicet...@vger.kernel.org; linux-arm- > ker...@lists.infradead.org; linux-kernel@vger.kernel.org; > chinnikishore...@gmail.com; git > Subject: Re: [PATCH 5/5] misc: zynqmp: Add afi config driver > > On Tue, Apr 20, 2021 at 01:41:53PM +0530, Nava kishore Manne wrote: > > This patch adds zynqmp afi config driver.This is useful for the > > configuration of the PS-PL interface on Zynq US+ MPSoC platform. > > Again, please spell out what those terms mean, as I have no idea :( > Will fix in v2 > > > > Signed-off-by: Nava kishore Manne > > --- > > drivers/misc/Kconfig | 11 ++ > > drivers/misc/Makefile | 1 + > > drivers/misc/zynqmp-afi.c | 83 > > +++ > > 3 files changed, 95 insertions(+) > > create mode 100644 drivers/misc/zynqmp-afi.c > > > > diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index > > 877b43b3377d..d1ea1eeb3ac1 100644 > > --- a/drivers/misc/Kconfig > > +++ b/drivers/misc/Kconfig > > @@ -456,6 +456,17 @@ config ZYNQ_AFI > > between PS and PL, the AXI port data path should be configured > > with the proper Bus-width values > > > > +config ZYNQMP_AFI > > +tristate "Xilinx ZYNQMP AFI support" > > +help > > + ZynqMP AFI driver support for writing to the AFI registers for > > + configuring PS_PL Bus-width. Xilinx Zynq US+ MPSoC connect the > > + PS to the programmable logic (PL) through the AXI port. This AXI > > + port helps to establish the data path between the PS and PL. > > + In-order to establish the proper communication path between > > + PS and PL, the AXI port data path should be configured with > > + the proper Bus-width values > > Please use tabs properly, you mix them above, checkpatch should have > caught that. > Yes, Ideally check patch should report this issue but it's failed to report. Will fix this issue in v2. Regards, Navakishore.
RE: [PATCH 2/5] misc: zynq: Add afi config driver
Hi Greg,
Please find my response inline.
> -Original Message-
> From: Greg KH
> Sent: Tuesday, April 20, 2021 2:17 PM
> To: Nava kishore Manne
> Cc: robh...@kernel.org; Michal Simek ; Derek Kiernan
> ; Dragan Cvetic ;
> a...@arndb.de; Rajan Vaja ; Jolly Shah
> ; Tejas Patel ; Amit Sunil
> Dhamne ; devicet...@vger.kernel.org; linux-arm-
> ker...@lists.infradead.org; linux-kernel@vger.kernel.org;
> chinnikishore...@gmail.com; git
> Subject: Re: [PATCH 2/5] misc: zynq: Add afi config driver
>
> On Tue, Apr 20, 2021 at 01:41:50PM +0530, Nava kishore Manne wrote:
> > This patch adds zynq afi config driver. This is useful for the
> > configuration of the PS-PL interface on zynq platform.
>
> What is "PS-PL"? Can you describe it better please?
>
PS-PL interface is nothing but the interface between processing system(PS)
that contains arm cores and Programmable Logic(PL) i.e FPGA.
Will update the description in v2.
> >
> > Signed-off-by: Nava kishore Manne
> > ---
> > drivers/misc/Kconfig| 11 ++
> > drivers/misc/Makefile | 1 +
> > drivers/misc/zynq-afi.c | 81
> > +
> > 3 files changed, 93 insertions(+)
> > create mode 100644 drivers/misc/zynq-afi.c
> >
> > diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index
> > f532c59bb59b..877b43b3377d 100644
> > --- a/drivers/misc/Kconfig
> > +++ b/drivers/misc/Kconfig
> > @@ -445,6 +445,17 @@ config HISI_HIKEY_USB
> > switching between the dual-role USB-C port and the USB-A host
> ports
> > using only one USB controller.
> >
> > +config ZYNQ_AFI
> > + tristate "Xilinx ZYNQ AFI support"
> > + help
> > + Zynq AFI driver support for writing to the AFI registers
> > + for configuring PS_PL Bus-width. Xilinx Zynq SoC connect
> > + the PS to the programmable logic (PL) through the AXI port.
> > + This AXI port helps to establish the data path between the
> > + PS and PL.In-order to establish the proper communication path
> > + between PS and PL, the AXI port data path should be configured
> > + with the proper Bus-width values
> > +
> > source "drivers/misc/c2port/Kconfig"
> > source "drivers/misc/eeprom/Kconfig"
> > source "drivers/misc/cb710/Kconfig"
> > diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index
> > 99b6f15a3c70..e9b03843100f 100644
> > --- a/drivers/misc/Makefile
> > +++ b/drivers/misc/Makefile
> > @@ -56,3 +56,4 @@ obj-$(CONFIG_HABANA_AI) +=
> habanalabs/
> > obj-$(CONFIG_UACCE)+= uacce/
> > obj-$(CONFIG_XILINX_SDFEC) += xilinx_sdfec.o
> > obj-$(CONFIG_HISI_HIKEY_USB) += hisi_hikey_usb.o
> > +obj-$(CONFIG_ZYNQ_AFI) += zynq-afi.o
> > diff --git a/drivers/misc/zynq-afi.c b/drivers/misc/zynq-afi.c new
> > file mode 100644 index ..04317d1bdb98
> > --- /dev/null
> > +++ b/drivers/misc/zynq-afi.c
> > @@ -0,0 +1,81 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Xilinx ZYNQ AFI driver.
> > + * Copyright (c) 2018-2021 Xilinx Inc.
> > + */
> > +
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +
> > +/* Registers and special values for doing register-based operations */
> > +#define AFI_RDCHAN_CTRL_OFFSET 0x00
> > +#define AFI_WRCHAN_CTRL_OFFSET 0x14
> > +
> > +#define AFI_BUSWIDTH_MASK 0x01
> > +
> > +/**
> > + * struct afi_fpga - AFI register description
> > + * @membase: pointer to register struct
> > + * @afi_width: AFI bus width to be written
> > + */
> > +struct zynq_afi_fpga {
> > + void __iomem*membase;
> > + u32 afi_width;
> > +};
> > +
> > +static int zynq_afi_fpga_probe(struct platform_device *pdev) {
> > + struct zynq_afi_fpga *afi_fpga;
> > + struct resource *res;
> > + u32 reg_val;
> > + u32 val;
> > +
> > + afi_fpga = devm_kzalloc(>dev, sizeof(*afi_fpga),
> GFP_KERNEL);
> > + if (!afi_fpga)
> > + return -ENOMEM;
> > +
> > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > + afi_fpga->membase = devm_ioremap_resource(>dev, res);
> > + if (IS_ERR(afi_fpga->membase))
> > + return PTR_ERR(afi_fpga->membase);
> > +
> > + val = device_property_read_u32(>dev, "xlnx,afi-width",
> > + _fpga->afi_width);
> >
[PATCH 5/5] misc: zynqmp: Add afi config driver
This patch adds zynqmp afi config driver.This is useful for
the configuration of the PS-PL interface on Zynq US+ MPSoC
platform.
Signed-off-by: Nava kishore Manne
---
drivers/misc/Kconfig | 11 ++
drivers/misc/Makefile | 1 +
drivers/misc/zynqmp-afi.c | 83 +++
3 files changed, 95 insertions(+)
create mode 100644 drivers/misc/zynqmp-afi.c
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 877b43b3377d..d1ea1eeb3ac1 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -456,6 +456,17 @@ config ZYNQ_AFI
between PS and PL, the AXI port data path should be configured
with the proper Bus-width values
+config ZYNQMP_AFI
+tristate "Xilinx ZYNQMP AFI support"
+help
+ ZynqMP AFI driver support for writing to the AFI registers for
+ configuring PS_PL Bus-width. Xilinx Zynq US+ MPSoC connect the
+ PS to the programmable logic (PL) through the AXI port. This AXI
+ port helps to establish the data path between the PS and PL.
+ In-order to establish the proper communication path between
+ PS and PL, the AXI port data path should be configured with
+ the proper Bus-width values
+
source "drivers/misc/c2port/Kconfig"
source "drivers/misc/eeprom/Kconfig"
source "drivers/misc/cb710/Kconfig"
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index e9b03843100f..54bd0edc511e 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -57,3 +57,4 @@ obj-$(CONFIG_UACCE) += uacce/
obj-$(CONFIG_XILINX_SDFEC) += xilinx_sdfec.o
obj-$(CONFIG_HISI_HIKEY_USB) += hisi_hikey_usb.o
obj-$(CONFIG_ZYNQ_AFI) += zynq-afi.o
+obj-$(CONFIG_ZYNQMP_AFI) += zynqmp-afi.o
diff --git a/drivers/misc/zynqmp-afi.c b/drivers/misc/zynqmp-afi.c
new file mode 100644
index ..a318652576d2
--- /dev/null
+++ b/drivers/misc/zynqmp-afi.c
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx FPGA AFI bridge.
+ * Copyright (c) 2018-2021 Xilinx Inc.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/**
+ * struct zynqmp_afi_fpga - AFI register description
+ * @value: value to be written to the register
+ * @regid: Register id for the register to be written
+ */
+struct zynqmp_afi_fpga {
+ u32 value;
+ u32 regid;
+};
+
+static int zynqmp_afi_fpga_probe(struct platform_device *pdev)
+{
+ struct zynqmp_afi_fpga *zynqmp_afi_fpga;
+ struct device_node *np = pdev->dev.of_node;
+ int i, entries, ret;
+ u32 reg, val;
+
+ zynqmp_afi_fpga = devm_kzalloc(>dev,
+ sizeof(*zynqmp_afi_fpga), GFP_KERNEL);
+ if (!zynqmp_afi_fpga)
+ return -ENOMEM;
+ platform_set_drvdata(pdev, zynqmp_afi_fpga);
+
+ entries = of_property_count_u32_elems(np, "config-afi");
+ if (!entries || (entries % 2)) {
+ dev_err(>dev, "Invalid number of registers\n");
+ return -EINVAL;
+ }
+
+ for (i = 0; i < entries / 2; i++) {
+ ret = of_property_read_u32_index(np, "config-afi", i * 2, );
+ if (ret) {
+ dev_err(>dev, "failed to read register\n");
+ return -EINVAL;
+ }
+ ret = of_property_read_u32_index(np, "config-afi", i * 2 + 1,
+);
+ if (ret) {
+ dev_err(>dev, "failed to read value\n");
+ return -EINVAL;
+ }
+ ret = zynqmp_pm_afi(reg, val);
+ if (ret < 0) {
+ dev_err(>dev, "AFI register write error %d\n",
+ ret);
+ return ret;
+ }
+ }
+ return 0;
+}
+
+static const struct of_device_id zynqmp_afi_fpga_ids[] = {
+ { .compatible = "xlnx,zynqmp-afi-fpga" },
+ { },
+};
+MODULE_DEVICE_TABLE(of, zynqmp_afi_fpga_ids);
+
+static struct platform_driver zynqmp_afi_fpga_driver = {
+ .driver = {
+ .name = "zynqmp-afi-fpga",
+ .of_match_table = zynqmp_afi_fpga_ids,
+ },
+ .probe = zynqmp_afi_fpga_probe,
+};
+module_platform_driver(zynqmp_afi_fpga_driver);
+
+MODULE_DESCRIPTION("ZYNQMP FPGA afi module");
+MODULE_AUTHOR("Nava kishore Manne ");
+MODULE_LICENSE("GPL v2");
--
2.18.0
[PATCH 4/5] misc: doc: Add binding doc for the zynqmp afi config driver
This patch adds the binding document for the zynqmp afi
config driver.
Signed-off-by: Nava kishore Manne
---
.../bindings/misc/xlnx,zynqmp-afi-fpga.yaml | 136 ++
1 file changed, 136 insertions(+)
create mode 100644
Documentation/devicetree/bindings/misc/xlnx,zynqmp-afi-fpga.yaml
diff --git a/Documentation/devicetree/bindings/misc/xlnx,zynqmp-afi-fpga.yaml
b/Documentation/devicetree/bindings/misc/xlnx,zynqmp-afi-fpga.yaml
new file mode 100644
index ..3ae22096b22a
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/xlnx,zynqmp-afi-fpga.yaml
@@ -0,0 +1,136 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/misc/xlnx,zynqmp-afi-fpga.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx ZynqMP AFI interface Manager.
+
+maintainers:
+ - Nava kishore Manne
+
+description: |
+ The Zynq UltraScale+ MPSoC Processing System core provides access from PL
+ masters to PS internal peripherals, and memory through AXI FIFO
interface(AFI)
+ interfaces.
+
+properties:
+ compatible:
+items:
+ - enum:
+ - xlnx,zynqmp-afi-fpga
+
+ config-afi:
+$ref: /schemas/types.yaml#/definitions/uint32-array
+description: |
+ Pairs of
+ The possible values of regid and values are
+ regid - Regids of the register to be written possible values
+0- AFIFM0_RDCTRL
+1- AFIFM0_WRCTRL
+2- AFIFM1_RDCTRL
+3- AFIFM1_WRCTRL
+4- AFIFM2_RDCTRL
+5- AFIFM2_WRCTRL
+6- AFIFM3_RDCTRL
+7- AFIFM3_WRCTRL
+8- AFIFM4_RDCTRL
+9- AFIFM4_WRCTRL
+10- AFIFM5_RDCTRL
+11- AFIFM5_WRCTRL
+12- AFIFM6_RDCTRL
+13- AFIFM6_WRCTRL
+14- AFIFS
+15- AFIFS_SS2
+ value - Array of values to be written.
+for FM0_RDCTRL(0) the valid values-fabric width
+ 2 - 32-bit
+ 1 - 64-bit
+ 0 - 128-bit
+for FM0_WRCTRL(1) the valid values-fabric width
+ 2 - 32-bit
+ 1 - 64-bit
+ 0 - 128-bit
+for FM1_RDCTRL(2) the valid values-fabric width
+ 2 - 32-bit
+ 1 - 64-bit
+ 0 - 128-bit
+for FM1_WRCTRL(3) the valid values-fabric width
+ 2 - 32-bit
+ 1 - 64-bit
+ 0 - 128-bit
+for FM2_RDCTRL(4) the valid values-fabric width
+ 2 - 32-bit
+ 1 - 64-bit
+ 0 - 128-bit
+for FM2_WRCTRL(5) the valid values-fabric width
+ 2 - 32-bit
+ 1 - 64-bit
+ 0 - 128-bit
+for FM3_RDCTRL(6) the valid values-fabric width
+ 2 - 32-bit
+ 1 - 64-bit
+ 0 - 128-bit
+for FM3_WRCTRL(7) the valid values-fabric width
+ 2 - 32-bit
+ 1 - 64-bit
+ 0 - 128-bit
+for FM4_RDCTRL(8) the valid values-fabric width
+ 2 - 32-bit
+ 1 - 64-bit
+ 0 - 128-bit
+for FM4_WRCTRL(9) the valid values-fabric width
+ 2 - 32-bit
+ 1 - 64-bit
+ 0 - 128-bit
+for FM5_RDCTRL(10) the valid values-fabric width
+ 2 - 32-bit
+ 1 - 64-bit
+ 0 - 128-bit
+for FM5_WRCTRL(11) the valid values-fabric width
+ 2 - 32-bit
+ 1 - 64-bit
+ 0 - 128-bit
+for FM6_RDCTRL(12) the valid values-fabric width
+ 2 - 32-bit
+ 1 - 64-bit
+ 0 - 128-bit
+for FM6_WRCTRL(13) the valid values-fabric width
+ 2 - 32-bit
+ 1 - 64-bit
+ 0 - 128-bit
+for AFI_FA(14)
+ dw_ss1_sel bits (11:10)
+ dw_ss0_sel bits (9:8)
+0x0 - 32-bit AXI data width
+0x1 - 64-bit AXI data width
+0x2 - 128-bit AXI data width
+All other bits are 0 write ignored.
+
+for AFI_FA(15) selects for ss2AXI data width valid values
+ 0x000 - 32-bit AXI data width
+ 0x100 - 64-bit AXI data width
+ 0x200 - 128-bit AXI data width
+minItems: 1
+maxItems: 15
+
+required:
+ - compatible
+ - config-afi
+
+additionalProperties: false
+
+examples:
+ - |
+firmware {
+ zynqmp_firmware: zynqmp-firmware {
+compatible = "xlnx,zynqmp-firmware";
+method = "smc";
+afi0: afi {
+ compatible = "xlnx,afi-fpga";
+ config-afi = <0 2>, <1 1>, <2 1>;
+};
+ };
+};
+
+...
--
2.18.0
[PATCH 2/5] misc: zynq: Add afi config driver
This patch adds zynq afi config driver. This is useful for
the configuration of the PS-PL interface on zynq platform.
Signed-off-by: Nava kishore Manne
---
drivers/misc/Kconfig| 11 ++
drivers/misc/Makefile | 1 +
drivers/misc/zynq-afi.c | 81 +
3 files changed, 93 insertions(+)
create mode 100644 drivers/misc/zynq-afi.c
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index f532c59bb59b..877b43b3377d 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -445,6 +445,17 @@ config HISI_HIKEY_USB
switching between the dual-role USB-C port and the USB-A host ports
using only one USB controller.
+config ZYNQ_AFI
+ tristate "Xilinx ZYNQ AFI support"
+ help
+ Zynq AFI driver support for writing to the AFI registers
+ for configuring PS_PL Bus-width. Xilinx Zynq SoC connect
+ the PS to the programmable logic (PL) through the AXI port.
+ This AXI port helps to establish the data path between the
+ PS and PL.In-order to establish the proper communication path
+ between PS and PL, the AXI port data path should be configured
+ with the proper Bus-width values
+
source "drivers/misc/c2port/Kconfig"
source "drivers/misc/eeprom/Kconfig"
source "drivers/misc/cb710/Kconfig"
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 99b6f15a3c70..e9b03843100f 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -56,3 +56,4 @@ obj-$(CONFIG_HABANA_AI) += habanalabs/
obj-$(CONFIG_UACCE)+= uacce/
obj-$(CONFIG_XILINX_SDFEC) += xilinx_sdfec.o
obj-$(CONFIG_HISI_HIKEY_USB) += hisi_hikey_usb.o
+obj-$(CONFIG_ZYNQ_AFI) += zynq-afi.o
diff --git a/drivers/misc/zynq-afi.c b/drivers/misc/zynq-afi.c
new file mode 100644
index ..04317d1bdb98
--- /dev/null
+++ b/drivers/misc/zynq-afi.c
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx ZYNQ AFI driver.
+ * Copyright (c) 2018-2021 Xilinx Inc.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+/* Registers and special values for doing register-based operations */
+#define AFI_RDCHAN_CTRL_OFFSET 0x00
+#define AFI_WRCHAN_CTRL_OFFSET 0x14
+
+#define AFI_BUSWIDTH_MASK 0x01
+
+/**
+ * struct afi_fpga - AFI register description
+ * @membase: pointer to register struct
+ * @afi_width: AFI bus width to be written
+ */
+struct zynq_afi_fpga {
+ void __iomem*membase;
+ u32 afi_width;
+};
+
+static int zynq_afi_fpga_probe(struct platform_device *pdev)
+{
+ struct zynq_afi_fpga *afi_fpga;
+ struct resource *res;
+ u32 reg_val;
+ u32 val;
+
+ afi_fpga = devm_kzalloc(>dev, sizeof(*afi_fpga), GFP_KERNEL);
+ if (!afi_fpga)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ afi_fpga->membase = devm_ioremap_resource(>dev, res);
+ if (IS_ERR(afi_fpga->membase))
+ return PTR_ERR(afi_fpga->membase);
+
+ val = device_property_read_u32(>dev, "xlnx,afi-width",
+ _fpga->afi_width);
+ if (val) {
+ dev_err(>dev, "failed to get the afi bus width\n");
+ return -EINVAL;
+ }
+
+ reg_val = readl(afi_fpga->membase + AFI_RDCHAN_CTRL_OFFSET);
+ reg_val &= ~AFI_BUSWIDTH_MASK;
+ writel(reg_val | afi_fpga->afi_width,
+ afi_fpga->membase + AFI_RDCHAN_CTRL_OFFSET);
+ reg_val = readl(afi_fpga->membase + AFI_WRCHAN_CTRL_OFFSET);
+ reg_val &= ~AFI_BUSWIDTH_MASK;
+ writel(reg_val | afi_fpga->afi_width,
+ afi_fpga->membase + AFI_WRCHAN_CTRL_OFFSET);
+
+ return 0;
+}
+
+static const struct of_device_id zynq_afi_fpga_ids[] = {
+ { .compatible = "xlnx,zynq-afi-fpga" },
+ { },
+};
+MODULE_DEVICE_TABLE(of, zynq_afi_fpga_ids);
+
+static struct platform_driver zynq_afi_fpga_driver = {
+ .driver = {
+ .name = "zynq-afi-fpga",
+ .of_match_table = zynq_afi_fpga_ids,
+ },
+ .probe = zynq_afi_fpga_probe,
+};
+module_platform_driver(zynq_afi_fpga_driver);
+
+MODULE_DESCRIPTION("ZYNQ FPGA AFI module");
+MODULE_AUTHOR("Nava kishore Manne ");
+MODULE_LICENSE("GPL v2");
--
2.18.0
[PATCH 3/5] firmware: xilinx: Add afi ioctl support
This patch adds afi ioctl to support dynamic PS-PL
bus width settings.
Signed-off-by: Nava kishore Manne
---
drivers/firmware/xilinx/zynqmp.c | 13 +
include/linux/firmware/xlnx-zynqmp.h | 7 +++
2 files changed, 20 insertions(+)
diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
index 7eb9958662dd..ada9eb9e26e3 100644
--- a/drivers/firmware/xilinx/zynqmp.c
+++ b/drivers/firmware/xilinx/zynqmp.c
@@ -713,6 +713,19 @@ int zynqmp_pm_read_pggs(u32 index, u32 *value)
}
EXPORT_SYMBOL_GPL(zynqmp_pm_read_pggs);
+/**
+ * zynqmp_pm_afi() - PM API for setting the PS-PL bus width
+ * @index: Register index value
+ * @value: value to be written into the register
+ *
+ * Return: Returns status, either success or error+reason
+ */
+int zynqmp_pm_afi(u32 index, u32 value)
+{
+ return zynqmp_pm_invoke_fn(PM_IOCTL, 0, IOCTL_AFI, index, value, NULL);
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_afi);
+
/**
* zynqmp_pm_set_boot_health_status() - PM API for setting healthy boot status
* @value: Status value to be written
diff --git a/include/linux/firmware/xlnx-zynqmp.h
b/include/linux/firmware/xlnx-zynqmp.h
index 71177b17eee5..792fb4f5d86f 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -113,6 +113,7 @@ enum pm_ioctl_id {
IOCTL_READ_PGGS = 15,
/* Set healthy bit value */
IOCTL_SET_BOOT_HEALTH_STATUS = 17,
+ IOCTL_AFI = 18,
};
enum pm_query_id {
@@ -353,6 +354,7 @@ int zynqmp_pm_write_pggs(u32 index, u32 value);
int zynqmp_pm_read_pggs(u32 index, u32 *value);
int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype);
int zynqmp_pm_set_boot_health_status(u32 value);
+int zynqmp_pm_afi(u32 index, u32 value);
#else
static inline struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void)
{
@@ -537,6 +539,11 @@ static inline int zynqmp_pm_set_boot_health_status(u32
value)
{
return -ENODEV;
}
+
+static inline int zynqmp_pm_afi(u32 index, u32 value)
+{
+ return -ENODEV;
+}
#endif
#endif /* __FIRMWARE_ZYNQMP_H__ */
--
2.18.0
[PATCH 1/5] misc: doc: Add binding doc for the afi config driver
This patch adds the binding document for the afi config
driver.
Signed-off-by: Nava kishore Manne
---
.../bindings/misc/xlnx,zynq-afi-fpga.yaml | 47 +++
1 file changed, 47 insertions(+)
create mode 100644
Documentation/devicetree/bindings/misc/xlnx,zynq-afi-fpga.yaml
diff --git a/Documentation/devicetree/bindings/misc/xlnx,zynq-afi-fpga.yaml
b/Documentation/devicetree/bindings/misc/xlnx,zynq-afi-fpga.yaml
new file mode 100644
index ..9c20a192d6a6
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/xlnx,zynq-afi-fpga.yaml
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/misc/xlnx,zynq-afi-fpga.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx Zynq AFI interface Manager.
+
+maintainers:
+ - Nava kishore Manne
+
+description: |
+ The Zynq Processing System core provides access from PL masters to PS
+ internal peripherals, and memory through AXI FIFO interface(AFI)
+ interfaces.
+
+properties:
+ compatible:
+items:
+ - enum:
+ - xlnx,zynq-afi-fpga
+ reg:
+maxItems: 1
+
+ xlnx,afi-buswidth:
+$ref: /schemas/types.yaml#/definitions/uint32
+description: |
+Size of the afi bus width.
+0 - 64-bit AXI data width.
+1 - 32-bit AXI data width.
+maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - xlnx,afi-buswidth
+
+additionalProperties: false
+
+examples:
+ - |
+afi0: afi@f8008000 {
+compatible = "xlnx,zynq-afi-fpga";
+reg = <0xf8008000 0x1000>;
+xlnx,afi-buswidth = <1>;
+};
+...
--
2.18.0
[PATCH 0/5]misc: Add afi config drivers support.
Xilinx SoC platforms (Zynq and ZynqMP) connect the PS to the programmable logic (PL) through the AXI port.This AXI port helps to establish the data path between the PS and PL. In-order to establish to proper communication data path between PS and PL the AXI port data path should be configured with the proper Bus-width values This patch series Adds afi config drivers support to handle the PS-PL AXI port bus-width configurations. Nava kishore Manne (5): misc: doc: Add binding doc for the afi config driver misc: zynq: Add afi config driver firmware: xilinx: Add afi ioctl support misc: doc: Add binding doc for the zynqmp afi config driver misc: zynqmp: Add afi config driver .../bindings/misc/xlnx,zynq-afi-fpga.yaml | 47 ++ .../bindings/misc/xlnx,zynqmp-afi-fpga.yaml | 136 ++ drivers/firmware/xilinx/zynqmp.c | 13 ++ drivers/misc/Kconfig | 22 +++ drivers/misc/Makefile | 2 + drivers/misc/zynq-afi.c | 81 +++ drivers/misc/zynqmp-afi.c | 83 +++ include/linux/firmware/xlnx-zynqmp.h | 7 + 8 files changed, 391 insertions(+) create mode 100644 Documentation/devicetree/bindings/misc/xlnx,zynq-afi-fpga.yaml create mode 100644 Documentation/devicetree/bindings/misc/xlnx,zynqmp-afi-fpga.yaml create mode 100644 drivers/misc/zynq-afi.c create mode 100644 drivers/misc/zynqmp-afi.c -- 2.18.0
RE: [PATCH 3/3] fpga: region: Adds runtime PM support
Hi Moritz,
Please find my response inline.
> -Original Message-
> From: Moritz Fischer
> Sent: Saturday, April 10, 2021 3:01 AM
> To: Nava kishore Manne
> Cc: m...@kernel.org; t...@redhat.com; robh...@kernel.org; Michal Simek
> ; linux-f...@vger.kernel.org;
> devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-
> ker...@lists.infradead.org; git
> Subject: Re: [PATCH 3/3] fpga: region: Adds runtime PM support
>
> On Fri, Apr 02, 2021 at 02:50:49PM +0530, Nava kishore Manne wrote:
> > Adds support to handle FPGA/PL power domain. With this patch, the PL
> > power domain will be turned on before loading the bitstream and turned
> > off while removing/unloading the bitstream using overlays.
> > This can be achieved by adding the runtime PM support.
> >
> > Signed-off-by: Nava kishore Manne
> > ---
> > drivers/fpga/of-fpga-region.c | 18 +-
> > 1 file changed, 17 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/fpga/of-fpga-region.c
> > b/drivers/fpga/of-fpga-region.c index e405309baadc..35fc2f3d4bd8
> > 100644
> > --- a/drivers/fpga/of-fpga-region.c
> > +++ b/drivers/fpga/of-fpga-region.c
> > @@ -15,6 +15,7 @@
> > #include
> > #include
> > #include
> > +#include
> >
> > static const struct of_device_id fpga_region_of_match[] = {
> > { .compatible = "fpga-region", },
> > @@ -302,6 +303,7 @@ static int of_fpga_region_notify_pre_apply(struct
> fpga_region *region,
> > }
> >
> > region->info = info;
> > + pm_runtime_get_sync(dev->parent);
> > ret = fpga_region_program_fpga(region);
> > if (ret) {
> > /* error; reject overlay */
> > @@ -324,10 +326,13 @@ static int
> > of_fpga_region_notify_pre_apply(struct fpga_region *region, static void
> of_fpga_region_notify_post_remove(struct fpga_region *region,
> > struct of_overlay_notify_data
> *nd) {
> > + struct device *dev = >dev;
> > +
> > fpga_bridges_disable(>bridge_list);
> > fpga_bridges_put(>bridge_list);
> > fpga_image_info_free(region->info);
> > region->info = NULL;
> > + pm_runtime_put(dev->parent);
> > }
> >
> > /**
> > @@ -411,9 +416,16 @@ static int of_fpga_region_probe(struct
> platform_device *pdev)
> > goto eprobe_mgr_put;
> > }
> >
> > + pm_runtime_enable(>dev);
> > + ret = pm_runtime_get_sync(>dev);
> > + if (ret < 0)
> > + goto err_pm;
> > +
> > + pm_runtime_put(>dev);
> > +
> > ret = fpga_region_register(region);
> > if (ret)
> > - goto eprobe_mgr_put;
> > + goto err_pm;
> >
> > of_platform_populate(np, fpga_region_of_match, NULL,
> >dev);
> > platform_set_drvdata(pdev, region);
> > @@ -422,6 +434,9 @@ static int of_fpga_region_probe(struct
> > platform_device *pdev)
> >
> > return 0;
> >
> > +err_pm:
> > + pm_runtime_put(>dev);
> > + pm_runtime_disable(>dev);
> > eprobe_mgr_put:
> > fpga_mgr_put(mgr);
> > return ret;
> > @@ -434,6 +449,7 @@ static int of_fpga_region_remove(struct
> > platform_device *pdev)
> >
> > fpga_region_unregister(region);
> > fpga_mgr_put(mgr);
> > + pm_runtime_disable(region->dev.parent);
> >
> > return 0;
> > }
> > --
> > 2.18.0
> >
>
> Does this add a dependency on CONFIG_PM?
>
Yes, the newly added functionality has a dependency on CONFIG_PM if it's
disabled the expected power domain (in our cases it's PL) will not powered
ON/OFF dynamically at runtime and this is as an expected behavior. Other than
this it will not impact the any of the driver existing functionality.
Regards,
Navakishore.
RE: [PATCH v3 2/3] dt-bindings: fpga: Add binding doc for versal fpga manager
Hi Rob, Please find my response inline. > -Original Message- > From: Rob Herring > Sent: Wednesday, March 10, 2021 10:50 PM > To: Nava kishore Manne > Cc: m...@kernel.org; t...@redhat.com; Michal Simek ; > gre...@linuxfoundation.org; Jolly Shah ; Rajan Vaja > ; a...@arndb.de; Manish Narani > ; Amit Sunil Dhamne ; Tejas > Patel ; linux-f...@vger.kernel.org; > devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm- > ker...@lists.infradead.org; chinnikishore...@gmail.com; Appana Durga > Kedareswara Rao > Subject: Re: [PATCH v3 2/3] dt-bindings: fpga: Add binding doc for versal fpga > manager > > On Wed, Mar 10, 2021 at 10:12 AM Rob Herring wrote: > > > > On Wed, Mar 10, 2021 at 3:50 AM Nava kishore Manne > wrote: > > > > > > Hi Rob, > > > > > > Thanks for providing the review comments. > > > Please find my response inline. > > > > > > > -Original Message- > > > > From: Rob Herring > > > > Sent: Tuesday, March 9, 2021 1:50 AM > > > > To: Nava kishore Manne > > > > Cc: m...@kernel.org; t...@redhat.com; Michal Simek > > > > ; gre...@linuxfoundation.org; Jolly Shah > > > > ; Rajan Vaja ; > > > > a...@arndb.de; Manish Narani ; Amit Sunil > > > > Dhamne ; Tejas Patel > > > > ; linux-f...@vger.kernel.org; > > > > devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; > > > > linux-arm- ker...@lists.infradead.org; chinnikishore...@gmail.com; > > > > Appana Durga Kedareswara Rao > > > > Subject: Re: [PATCH v3 2/3] dt-bindings: fpga: Add binding doc for > > > > versal fpga manager > > > > > > > > On Thu, Mar 04, 2021 at 12:32:23PM +0530, Nava kishore Manne > wrote: > > > > > From: Appana Durga Kedareswara rao > > > > > > > > > > > This patch adds binding doc for versal fpga manager driver. > > > > > > > > Why do you need a DT entry for this? Can't the Versal firmware > > > > driver instantiate the fpga-mgr device? > > > > > > > This dt entry is need to handle the fpga regions properly for both full > > > and > Partial bitstream loading use cases and it cannot be done by Versal firmware > driver instantiate. > > > > Ah yes, I forgot about that. > > Looking at this some more, please convert xlnx,zynqmp-firmware.txt to > schema and add the node for this there. We don't need a whole other > schema file just for a node and compatible. Also, looks like xlnx,zynqmp- > pcap-fpga.txt is the prior version of the same thing, so it should be handled > in the schema too. > Will fix this in the next version Regards, Navakishore.
RE: [PATCH 1/2] fpga: mgr: Adds secure BitStream loading support
Hi Moritz, Thanks for providing the review comments. Please find my response inline. > -Original Message- > From: Moritz Fischer > Sent: Thursday, March 4, 2021 4:42 AM > To: Moritz Fischer > Cc: Nava kishore Manne ; t...@redhat.com; > robh...@kernel.org; Michal Simek ; linux- > f...@vger.kernel.org; devicet...@vger.kernel.org; linux-arm- > ker...@lists.infradead.org; linux-kernel@vger.kernel.org; git > ; chinnikishore...@gmail.com > Subject: Re: [PATCH 1/2] fpga: mgr: Adds secure BitStream loading support > > Hi Nava, > > On Thu, Jan 21, 2021 at 09:17:10PM -0800, Moritz Fischer wrote: > > On Mon, Jan 18, 2021 at 08:20:57AM +0530, Nava kishore Manne wrote: > > > This commit adds secure flags to the framework to support secure > > > BitStream Loading. > > > > > > Signed-off-by: Nava kishore Manne > > > --- > > > drivers/fpga/of-fpga-region.c | 10 ++ > > > include/linux/fpga/fpga-mgr.h | 12 > > > 2 files changed, 22 insertions(+) > > > > > > diff --git a/drivers/fpga/of-fpga-region.c > > > b/drivers/fpga/of-fpga-region.c index e405309baadc..3a5eb480 > > > 100644 > > > --- a/drivers/fpga/of-fpga-region.c > > > +++ b/drivers/fpga/of-fpga-region.c > > > @@ -228,6 +228,16 @@ static struct fpga_image_info > *of_fpga_region_parse_ov( > > > if (of_property_read_bool(overlay, "encrypted-fpga-config")) > > > info->flags |= FPGA_MGR_ENCRYPTED_BITSTREAM; > > > > > > + if (of_property_read_bool(overlay, "userkey-encrypted-fpga- > config")) > > > + info->flags |= > FPGA_MGR_USERKEY_ENCRYPTED_BITSTREAM; > > > > Can this just be encrypted-fpga-config/FPGA_MGR_ENCRYPTED? > > > + > > > + if (of_property_read_bool(overlay, "ddrmem-authenticated-fpga- > config")) > > > + info->flags |= FPGA_MGR_DDR_MEM_AUTH_BITSTREAM; > > > + > > > + if (of_property_read_bool(overlay, > > > + "securemem-authenticated-fpga-config")) > > > + info->flags |= FPGA_MGR_SECURE_MEM_AUTH_BITSTREAM; > Shouldn't all these get binding docs? I remember Richard adding > authentication support for an Intel platform, too and I'd like to avoid adding > random bindings per vendor. > > Would it be possible to have an 'authentication method / type' that is more > extensible with different methods maybe? > Yes, I agree this flags should not be a vendor specific we should make it as generic. can we have flags something like below . 1) authenticated-fpga-config --> By default it uses kernel memory(DDR) to authenticate the image(FPGA_MGR_MEM_AUTH_BITSTREAM) 2) authenticated-onchip-fpga-config --> It uses the On chip memory to authenticate the image ( FPGA_MGR_AUTH_ON_CHIP_BITSTREAM) if you have any other thoughts let me know will try to adopt the same... Regards, Navakishore.
RE: [PATCH 2/3] fpga: region: Add fpga-region property 'power-domains'
Hi Moritz,
Thanks for the response.
Please find my response inline.
> -Original Message-
> From: Moritz Fischer
> Sent: Friday, April 2, 2021 10:46 PM
> To: Nava kishore Manne
> Cc: m...@kernel.org; t...@redhat.com; robh...@kernel.org; Michal Simek
> ; linux-f...@vger.kernel.org;
> devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-
> ker...@lists.infradead.org; git
> Subject: Re: [PATCH 2/3] fpga: region: Add fpga-region property 'power-
> domains'
>
> On Fri, Apr 02, 2021 at 02:50:48PM +0530, Nava kishore Manne wrote:
> > Add fpga-region property 'power-domains' to allow to handle the
> > FPGA/PL power domins.
> >
> > dt-bindings: fpga: Enable PM generic domain support
> >
> > Signed-off-by: Nava kishore Manne
> > ---
> > .../devicetree/bindings/fpga/fpga-region.txt | 14 ++
> > 1 file changed, 14 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/fpga/fpga-region.txt
> > b/Documentation/devicetree/bindings/fpga/fpga-region.txt
> > index e811cf825019..969ca53bb65e 100644
> > --- a/Documentation/devicetree/bindings/fpga/fpga-region.txt
> > +++ b/Documentation/devicetree/bindings/fpga/fpga-region.txt
> > @@ -196,6 +196,20 @@ Optional properties:
> > - config-complete-timeout-us : The maximum time in microseconds time
> for the
> > FPGA to go to operating mode after the region has been
> programmed.
> > - child nodes : devices in the FPGA after programming.
> > +- power-domains : A phandle and PM domain specifier as defined by
> bindings of
> > + the power controller specified by phandle.
> > +Example:
> > + fpga_full: fpga-full {
> > +compatible = "fpga-region";
> > +fpga-mgr = <_pcap>;
> > +#address-cells = <2>;
> > +#size-cells = <2>;
> > +ranges;
> > +power-domains = <_firmware PL_PD>;
> > +};
> > +
> > + The PL_PD power domain will be turned on before loading the
> > +bitstream and turned off while removing/unloading the bitstream using
> overlays.
>
> Can multiple regions share a power-domain or is this specific to full fpga
> reconfiguration?
>
These are generic changes and not limited to full region. If H/W supports
individual power domains to control the Partial reconfiguration regions we can
control the individual Partial reconfiguration region power domains as well.
Regards,
Navakishore.
[PATCH 0/3]Enable PM generic domain support
Adds support to handle FPGA/PL power Domain to optimize the PL power consumption. Nava kishore Manne (3): dt-bindings: zynqmp: Add new PD_PL macro fpga: region: Add fpga-region property 'power-domains' fpga: region: Adds runtime PM support .../devicetree/bindings/fpga/fpga-region.txt | 14 ++ drivers/fpga/of-fpga-region.c | 18 +- include/dt-bindings/power/xlnx-zynqmp-power.h | 1 + 3 files changed, 32 insertions(+), 1 deletion(-) -- 2.18.0
[PATCH 3/3] fpga: region: Adds runtime PM support
Adds support to handle FPGA/PL power domain. With this patch,
the PL power domain will be turned on before loading the bitstream
and turned off while removing/unloading the bitstream using overlays.
This can be achieved by adding the runtime PM support.
Signed-off-by: Nava kishore Manne
---
drivers/fpga/of-fpga-region.c | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/fpga/of-fpga-region.c b/drivers/fpga/of-fpga-region.c
index e405309baadc..35fc2f3d4bd8 100644
--- a/drivers/fpga/of-fpga-region.c
+++ b/drivers/fpga/of-fpga-region.c
@@ -15,6 +15,7 @@
#include
#include
#include
+#include
static const struct of_device_id fpga_region_of_match[] = {
{ .compatible = "fpga-region", },
@@ -302,6 +303,7 @@ static int of_fpga_region_notify_pre_apply(struct
fpga_region *region,
}
region->info = info;
+ pm_runtime_get_sync(dev->parent);
ret = fpga_region_program_fpga(region);
if (ret) {
/* error; reject overlay */
@@ -324,10 +326,13 @@ static int of_fpga_region_notify_pre_apply(struct
fpga_region *region,
static void of_fpga_region_notify_post_remove(struct fpga_region *region,
struct of_overlay_notify_data *nd)
{
+ struct device *dev = >dev;
+
fpga_bridges_disable(>bridge_list);
fpga_bridges_put(>bridge_list);
fpga_image_info_free(region->info);
region->info = NULL;
+ pm_runtime_put(dev->parent);
}
/**
@@ -411,9 +416,16 @@ static int of_fpga_region_probe(struct platform_device
*pdev)
goto eprobe_mgr_put;
}
+ pm_runtime_enable(>dev);
+ ret = pm_runtime_get_sync(>dev);
+ if (ret < 0)
+ goto err_pm;
+
+ pm_runtime_put(>dev);
+
ret = fpga_region_register(region);
if (ret)
- goto eprobe_mgr_put;
+ goto err_pm;
of_platform_populate(np, fpga_region_of_match, NULL, >dev);
platform_set_drvdata(pdev, region);
@@ -422,6 +434,9 @@ static int of_fpga_region_probe(struct platform_device
*pdev)
return 0;
+err_pm:
+ pm_runtime_put(>dev);
+ pm_runtime_disable(>dev);
eprobe_mgr_put:
fpga_mgr_put(mgr);
return ret;
@@ -434,6 +449,7 @@ static int of_fpga_region_remove(struct platform_device
*pdev)
fpga_region_unregister(region);
fpga_mgr_put(mgr);
+ pm_runtime_disable(region->dev.parent);
return 0;
}
--
2.18.0
[PATCH 2/3] fpga: region: Add fpga-region property 'power-domains'
Add fpga-region property 'power-domains' to allow to handle
the FPGA/PL power domins.
dt-bindings: fpga: Enable PM generic domain support
Signed-off-by: Nava kishore Manne
---
.../devicetree/bindings/fpga/fpga-region.txt | 14 ++
1 file changed, 14 insertions(+)
diff --git a/Documentation/devicetree/bindings/fpga/fpga-region.txt
b/Documentation/devicetree/bindings/fpga/fpga-region.txt
index e811cf825019..969ca53bb65e 100644
--- a/Documentation/devicetree/bindings/fpga/fpga-region.txt
+++ b/Documentation/devicetree/bindings/fpga/fpga-region.txt
@@ -196,6 +196,20 @@ Optional properties:
- config-complete-timeout-us : The maximum time in microseconds time for the
FPGA to go to operating mode after the region has been programmed.
- child nodes : devices in the FPGA after programming.
+- power-domains : A phandle and PM domain specifier as defined by bindings of
+ the power controller specified by phandle.
+Example:
+ fpga_full: fpga-full {
+compatible = "fpga-region";
+fpga-mgr = <_pcap>;
+#address-cells = <2>;
+#size-cells = <2>;
+ranges;
+power-domains = <_firmware PL_PD>;
+};
+
+ The PL_PD power domain will be turned on before loading the bitstream
+and turned off while removing/unloading the bitstream using overlays.
In the example below, when an overlay is applied targeting fpga-region0,
fpga_mgr is used to program the FPGA. Two bridges are controlled during
--
2.18.0
[PATCH 1/3] dt-bindings: zynqmp: Add new PD_PL macro
Add new power domain for PL region. Signed-off-by: Nava kishore Manne --- include/dt-bindings/power/xlnx-zynqmp-power.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/power/xlnx-zynqmp-power.h b/include/dt-bindings/power/xlnx-zynqmp-power.h index 0d9a412fd5e0..5f718759c38f 100644 --- a/include/dt-bindings/power/xlnx-zynqmp-power.h +++ b/include/dt-bindings/power/xlnx-zynqmp-power.h @@ -35,5 +35,6 @@ #definePD_CAN_148 #definePD_GPU 58 #definePD_PCIE 59 +#definePD_PL 69 #endif -- 2.18.0
[PATCH RFC 3/3] fpga: zynqmp: Use the scatterlist interface
Allows drivers to request the Configuration image
be loaded from dma-able continuous buffer to avoid
needless memory pressure and delays due to multiple
copies.
Signed-off-by: Nava kishore Manne
---
drivers/fpga/zynqmp-fpga.c | 35 +++
1 file changed, 35 insertions(+)
diff --git a/drivers/fpga/zynqmp-fpga.c b/drivers/fpga/zynqmp-fpga.c
index 125743c9797f..3bb6bd520d71 100644
--- a/drivers/fpga/zynqmp-fpga.c
+++ b/drivers/fpga/zynqmp-fpga.c
@@ -66,6 +66,40 @@ static int zynqmp_fpga_ops_write(struct fpga_manager *mgr,
return ret;
}
+static unsigned long zynqmp_fpga_get_contiguous_size(struct sg_table *sgt)
+{
+ dma_addr_t expected = sg_dma_address(sgt->sgl);
+ unsigned long size = 0;
+ struct scatterlist *s;
+ unsigned int i;
+
+ for_each_sg(sgt->sgl, s, sgt->nents, i) {
+ if (sg_dma_address(s) != expected)
+ break;
+ expected = sg_dma_address(s) + sg_dma_len(s);
+ size += sg_dma_len(s);
+ }
+
+ return size;
+}
+
+static int zynqmp_fpga_ops_write_sg(struct fpga_manager *mgr,
+ struct sg_table *sgt)
+{
+ struct zynqmp_fpga_priv *priv;
+ unsigned long contig_size;
+ dma_addr_t dma_addr;
+ u32 eemi_flags = 0;
+
+ priv = mgr->priv;
+ dma_addr = sg_dma_address(sgt->sgl);
+ contig_size = zynqmp_fpga_get_contiguous_size(sgt);
+ if (priv->flags & FPGA_MGR_PARTIAL_RECONFIG)
+ eemi_flags |= XILINX_ZYNQMP_PM_FPGA_PARTIAL;
+
+ return zynqmp_pm_fpga_load(dma_addr, contig_size, eemi_flags);
+}
+
static int zynqmp_fpga_ops_write_complete(struct fpga_manager *mgr,
struct fpga_image_info *info)
{
@@ -87,6 +121,7 @@ static const struct fpga_manager_ops zynqmp_fpga_ops = {
.state = zynqmp_fpga_ops_state,
.write_init = zynqmp_fpga_ops_write_init,
.write = zynqmp_fpga_ops_write,
+ .write_sg = zynqmp_fpga_ops_write_sg,
.write_complete = zynqmp_fpga_ops_write_complete,
};
--
2.18.0
[PATCH RFC 1/3] fpga: region: Add fpga-region property 'fpga-config-from-dmabuf'
Add "fpga-config-from-dmabuf" property to allow the bitstream configuration from pre-allocated dma-buffer. Signed-off-by: Nava kishore Manne --- Documentation/devicetree/bindings/fpga/fpga-region.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/fpga/fpga-region.txt b/Documentation/devicetree/bindings/fpga/fpga-region.txt index 969ca53bb65e..c573cf258d60 100644 --- a/Documentation/devicetree/bindings/fpga/fpga-region.txt +++ b/Documentation/devicetree/bindings/fpga/fpga-region.txt @@ -177,6 +177,8 @@ Optional properties: it indicates that the FPGA has already been programmed with this image. If this property is in an overlay targeting a FPGA region, it is a request to program the FPGA with that image. +- fpga-config-from-dmabuf : boolean, set if the FPGA configured done from the + pre-allocated dma-buffer. - fpga-bridges : should contain a list of phandles to FPGA Bridges that must be controlled during FPGA programming along with the parent FPGA bridge. This property is optional if the FPGA Manager handles the bridges. -- 2.18.0
[PATCH RFC 2/3] fpga: support loading from a pre-allocated buffer
Some systems are memory constrained but they need to load very
large Configuration files. The FPGA subsystem allows drivers to
request this Configuration image be loaded from the filesystem,
but this requires that the entire configuration data be loaded
into kernel memory first before it's provided to the driver.
This can lead to a situation where we map the configuration
data twice, once to load the configuration data into kernel
memory and once to copy the configuration data into the final
resting place which is nothing but a dma-able continuous buffer.
This creates needless memory pressure and delays due to multiple
copies. Let's add a dmabuf handling support to the fpga manager
framework that allows drivers to load the Configuration data
directly from a pre-allocated buffer. This skips the intermediate
step of allocating a buffer in kernel memory to hold the
Configuration data.
Signed-off-by: Nava kishore Manne
---
drivers/fpga/fpga-mgr.c | 126 +-
drivers/fpga/of-fpga-region.c | 3 +
include/linux/fpga/fpga-mgr.h | 6 +-
3 files changed, 132 insertions(+), 3 deletions(-)
diff --git a/drivers/fpga/fpga-mgr.c b/drivers/fpga/fpga-mgr.c
index b85bc47c91a9..13faed61af62 100644
--- a/drivers/fpga/fpga-mgr.c
+++ b/drivers/fpga/fpga-mgr.c
@@ -8,6 +8,8 @@
* With code from the mailing list:
* Copyright (C) 2013 Xilinx, Inc.
*/
+#include
+#include
#include
#include
#include
@@ -306,6 +308,51 @@ static int fpga_mgr_buf_load(struct fpga_manager *mgr,
return rc;
}
+/**
+ * fpga_mgr_buf_load - load fpga from image in dma buffer
+ * @mgr:fpga manager
+ * @info: fpga image info
+ *
+ * Step the low level fpga manager through the device-specific steps of getting
+ * an FPGA ready to be configured, writing the image to it, then doing whatever
+ * post-configuration steps necessary. This code assumes the caller got the
+ * mgr pointer from of_fpga_mgr_get() and checked that it is not an error code.
+ *
+ * Return: 0 on success, negative error code otherwise.
+ */
+static int fpga_dmabuf_load(struct fpga_manager *mgr,
+ struct fpga_image_info *info)
+{
+ struct dma_buf_attachment *attach;
+ struct sg_table *sgt;
+ int ret;
+
+ /* create attachment for dmabuf with the user device */
+ attach = dma_buf_attach(mgr->dmabuf, >dev);
+ if (IS_ERR(attach)) {
+ pr_err("failed to attach dmabuf\n");
+ ret = PTR_ERR(attach);
+ goto fail_put;
+ }
+
+ sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
+ if (IS_ERR(sgt)) {
+ ret = PTR_ERR(sgt);
+ goto fail_detach;
+ }
+
+ info->sgt = sgt;
+ ret = fpga_mgr_buf_load_sg(mgr, info, info->sgt);
+ dma_buf_unmap_attachment(attach, sgt, DMA_BIDIRECTIONAL);
+
+fail_detach:
+ dma_buf_detach(mgr->dmabuf, attach);
+fail_put:
+ dma_buf_put(mgr->dmabuf);
+
+ return ret;
+}
+
/**
* fpga_mgr_firmware_load - request firmware and load to fpga
* @mgr: fpga manager
@@ -358,6 +405,8 @@ static int fpga_mgr_firmware_load(struct fpga_manager *mgr,
*/
int fpga_mgr_load(struct fpga_manager *mgr, struct fpga_image_info *info)
{
+ if (info->flags & FPGA_MGR_CONFIG_DMA_BUF)
+ return fpga_dmabuf_load(mgr, info);
if (info->sgt)
return fpga_mgr_buf_load_sg(mgr, info, info->sgt);
if (info->buf && info->count)
@@ -549,6 +598,62 @@ void fpga_mgr_unlock(struct fpga_manager *mgr)
}
EXPORT_SYMBOL_GPL(fpga_mgr_unlock);
+static int fpga_dmabuf_fd_get(struct file *file, char __user *argp)
+{
+ struct fpga_manager *mgr = (struct fpga_manager *)(file->private_data);
+ int buffd;
+
+ if (copy_from_user(, argp, sizeof(buffd)))
+ return -EFAULT;
+
+ mgr->dmabuf = dma_buf_get(buffd);
+ if (IS_ERR_OR_NULL(mgr->dmabuf))
+ return -EINVAL;
+
+ return 0;
+}
+
+static int fpga_device_open(struct inode *inode, struct file *file)
+{
+ struct miscdevice *miscdev = file->private_data;
+ struct fpga_manager *mgr = container_of(miscdev,
+ struct fpga_manager, miscdev);
+
+ file->private_data = mgr;
+
+ return 0;
+}
+
+static int fpga_device_release(struct inode *inode, struct file *file)
+{
+ return 0;
+}
+
+static long fpga_device_ioctl(struct file *file, unsigned int cmd,
+ unsigned long arg)
+{
+ char __user *argp = (char __user *)arg;
+ int err;
+
+ switch (cmd) {
+ case FPGA_IOCTL_LOAD_DMA_BUFF:
+ err = fpga_dmabuf_fd_get(file, argp);
+ break;
+ default:
+ err = -ENOTTY;
+ }
+
+ return err;
+}
+
+static const struct file_operations fpga_fops = {
+ .ow
[PATCH RFC 0/3] Adds support to allow the bitstream configuration from pre-allocated dma-buffer
Nava kishore Manne (3): fpga: region: Add fpga-region property 'fpga-config-from-dmabuf' fpga: support loading from a pre-allocated buffer fpga: zynqmp: Use the scatterlist interface .../devicetree/bindings/fpga/fpga-region.txt | 2 + drivers/fpga/fpga-mgr.c | 126 +- drivers/fpga/of-fpga-region.c | 3 + drivers/fpga/zynqmp-fpga.c| 35 + include/linux/fpga/fpga-mgr.h | 6 +- 5 files changed, 169 insertions(+), 3 deletions(-) -- 2.18.0
RE: [PATCH v3 2/3] dt-bindings: fpga: Add binding doc for versal fpga manager
Hi Rob,
Thanks for providing the review comments.
Please find my response inline.
> -Original Message-
> From: Rob Herring
> Sent: Tuesday, March 9, 2021 1:50 AM
> To: Nava kishore Manne
> Cc: m...@kernel.org; t...@redhat.com; Michal Simek ;
> gre...@linuxfoundation.org; Jolly Shah ; Rajan Vaja
> ; a...@arndb.de; Manish Narani
> ; Amit Sunil Dhamne ; Tejas
> Patel ; linux-f...@vger.kernel.org;
> devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-
> ker...@lists.infradead.org; chinnikishore...@gmail.com; Appana Durga
> Kedareswara Rao
> Subject: Re: [PATCH v3 2/3] dt-bindings: fpga: Add binding doc for versal fpga
> manager
>
> On Thu, Mar 04, 2021 at 12:32:23PM +0530, Nava kishore Manne wrote:
> > From: Appana Durga Kedareswara rao
> >
> > This patch adds binding doc for versal fpga manager driver.
>
> Why do you need a DT entry for this? Can't the Versal firmware driver
> instantiate the fpga-mgr device?
>
This dt entry is need to handle the fpga regions properly for both full and
Partial bitstream loading use cases and it cannot be done by Versal firmware
driver instantiate.
Complete firmware DT node example is shown below for your reference.
Example for full FPGA configuration:
fpga-region0 {
compatible = "fpga-region";
fpga-mgr = <_fpga>;
#address-cells = <0x1>;
#size-cells = <0x1>;
};
firmware {
zynqmp_firmware: zynqmp-firmware {
compatible = "xlnx,zynqmp-firmware";
method = "smc";
versal_fpga: fpga {
compatible = "xlnx,versal-fpga";
};
};
};
Please correct me if my understanding is wrong...
Regards,
Navakishore.
RE: [PATCH v2 0/2] Add DFX AXI Shutdown manager IP support for Xilinx
Ping! > -Original Message- > From: Nava kishore Manne > Sent: Thursday, February 11, 2021 10:42 AM > To: m...@kernel.org; t...@redhat.com; robh...@kernel.org; Michal Simek > ; linux-f...@vger.kernel.org; > devicet...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; linux- > ker...@vger.kernel.org; chinnikishore...@gmail.com > Cc: git ; Nava kishore Manne > Subject: [PATCH v2 0/2] Add DFX AXI Shutdown manager IP support for Xilinx > > Nava kishore Manne (2): > dt-bindings: fpga: Add compatible value for Xilinx DFX AXI shutdown > manager > fpga: Add support for Xilinx DFX AXI Shutdown manager > > .../bindings/fpga/xilinx-pr-decoupler.txt | 24 +++- > drivers/fpga/Kconfig | 9 - > drivers/fpga/xilinx-pr-decoupler.c| 37 --- > 3 files changed, 63 insertions(+), 7 deletions(-) > > -- > 2.18.0
RE: [PATCH v2 0/2] Add DFX AXI Shutdown manager IP support for Xilinx
Ping! > -Original Message- > From: Nava kishore Manne > Sent: Thursday, February 11, 2021 10:42 AM > To: m...@kernel.org; t...@redhat.com; robh...@kernel.org; Michal Simek > ; linux-f...@vger.kernel.org; > devicet...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; linux- > ker...@vger.kernel.org; chinnikishore...@gmail.com > Cc: git ; Nava kishore Manne > Subject: [PATCH v2 0/2] Add DFX AXI Shutdown manager IP support for Xilinx > > Nava kishore Manne (2): > dt-bindings: fpga: Add compatible value for Xilinx DFX AXI shutdown > manager > fpga: Add support for Xilinx DFX AXI Shutdown manager > > .../bindings/fpga/xilinx-pr-decoupler.txt | 24 +++- > drivers/fpga/Kconfig | 9 - > drivers/fpga/xilinx-pr-decoupler.c| 37 --- > 3 files changed, 63 insertions(+), 7 deletions(-) > > -- > 2.18.0
[PATCH v3 2/3] dt-bindings: fpga: Add binding doc for versal fpga manager
From: Appana Durga Kedareswara rao
This patch adds binding doc for versal fpga manager driver.
Signed-off-by: Nava kishore Manne
Signed-off-by: Appana Durga Kedareswara rao
---
Changes for v2:
-Fixed file format and syntax issues.
Changes for v3:
-Removed unwated extra spaces.
.../bindings/fpga/xlnx,versal-fpga.yaml | 33 +++
1 file changed, 33 insertions(+)
create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml
diff --git a/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml
b/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml
new file mode 100644
index ..fec6144766fe
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/fpga/xlnx,versal-fpga.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx Versal FPGA driver.
+
+maintainers:
+ - Nava kishore Manne
+
+description: |
+ Device Tree Versal FPGA bindings for the Versal SoC, controlled
+ using firmware interface.
+
+properties:
+ compatible:
+items:
+ - enum:
+ - xlnx,versal-fpga
+
+required:
+ - compatible
+
+additionalProperties: false
+
+examples:
+ - |
+versal_fpga: fpga {
+ compatible = "xlnx,versal-fpga";
+};
+
+...
--
2.18.0
[PATCH v3 3/3] fpga: versal-fpga: Add versal fpga manager driver
Add support for Xilinx Versal FPGA manager.
PDI source type can be DDR, OCM, QSPI flash etc..
But driver allocates memory always from DDR, Since driver supports only
DDR source type.
Signed-off-by: Appana Durga Kedareswara rao
Signed-off-by: Nava kishore Manne
---
Changes for v2:
-Updated the Fpga Mgr registrations call's
to 5.11
-Fixed some minor coding issues as suggested by
Moritz.
Changes for v3:
-Rewritten the Versal fpga Kconfig contents.
drivers/fpga/Kconfig | 9 +++
drivers/fpga/Makefile | 1 +
drivers/fpga/versal-fpga.c | 117 +
3 files changed, 127 insertions(+)
create mode 100644 drivers/fpga/versal-fpga.c
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index bf85b9a65ec2..c1603c7e1518 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -223,4 +223,13 @@ config FPGA_MGR_ZYNQMP_FPGA
to configure the programmable logic(PL) through PS
on ZynqMP SoC.
+config FPGA_MGR_VERSAL_FPGA
+ tristate "Xilinx Versal FPGA"
+ depends on ARCH_ZYNQMP || COMPILE_TEST
+ help
+ Select this option to enable FPGA manager driver support for
+ Xilinx Versal SoC. This driver uses the firmware interface to
+ configure the programmable logic(PL).
+
+ To compile this as a module, choose M here.
endif # FPGA
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index d8e21dfc6778..40c9adb6a644 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o
obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o
obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o
obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) += zynqmp-fpga.o
+obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA) += versal-fpga.o
obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o
obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT)+= altera-pr-ip-core-plat.o
diff --git a/drivers/fpga/versal-fpga.c b/drivers/fpga/versal-fpga.c
new file mode 100644
index ..5744e44f981d
--- /dev/null
+++ b/drivers/fpga/versal-fpga.c
@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019-2021 Xilinx, Inc.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/**
+ * struct versal_fpga_priv - Private data structure
+ * @dev: Device data structure
+ */
+struct versal_fpga_priv {
+ struct device *dev;
+};
+
+static int versal_fpga_ops_write_init(struct fpga_manager *mgr,
+ struct fpga_image_info *info,
+ const char *buf, size_t size)
+{
+ return 0;
+}
+
+static int versal_fpga_ops_write(struct fpga_manager *mgr,
+const char *buf, size_t size)
+{
+ struct versal_fpga_priv *priv;
+ dma_addr_t dma_addr = 0;
+ char *kbuf;
+ int ret;
+
+ priv = mgr->priv;
+
+ kbuf = dma_alloc_coherent(priv->dev, size, _addr, GFP_KERNEL);
+ if (!kbuf)
+ return -ENOMEM;
+
+ memcpy(kbuf, buf, size);
+
+ wmb(); /* ensure all writes are done before initiate FW call */
+
+ ret = zynqmp_pm_load_pdi(PDI_SRC_DDR, dma_addr);
+
+ dma_free_coherent(priv->dev, size, kbuf, dma_addr);
+
+ return ret;
+}
+
+static int versal_fpga_ops_write_complete(struct fpga_manager *mgr,
+ struct fpga_image_info *info)
+{
+ return 0;
+}
+
+static enum fpga_mgr_states versal_fpga_ops_state(struct fpga_manager *mgr)
+{
+ return FPGA_MGR_STATE_UNKNOWN;
+}
+
+static const struct fpga_manager_ops versal_fpga_ops = {
+ .state = versal_fpga_ops_state,
+ .write_init = versal_fpga_ops_write_init,
+ .write = versal_fpga_ops_write,
+ .write_complete = versal_fpga_ops_write_complete,
+};
+
+static int versal_fpga_probe(struct platform_device *pdev)
+{
+ struct device *dev = >dev;
+ struct versal_fpga_priv *priv;
+ struct fpga_manager *mgr;
+ int ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->dev = dev;
+ ret = dma_set_mask_and_coherent(>dev, DMA_BIT_MASK(32));
+ if (ret < 0) {
+ dev_err(dev, "no usable DMA configuration\n");
+ return ret;
+ }
+
+ mgr = devm_fpga_mgr_create(dev, "Xilinx Versal FPGA Manager",
+ _fpga_ops, priv);
+ if (!mgr)
+ return -ENOMEM;
+
+ return devm_fpga_mgr_register(dev, mgr);
+}
+
+static const struct of_device_id versal_fpga_of_match[] = {
+ { .compatible = "xlnx,versal-fpga", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, versal_fpga_of_match);
+
+static struct platform_dri
[PATCH v3 1/3] drivers: firmware: Add PDI load API support
This patch adds load PDI API support to enable full/partial PDI loading
from linux. Programmable Device Image (PDI) is combination of headers,
images and bitstream files to be loaded.
Signed-off-by: Nava kishore Manne
---
Changes for v2:
-Updated API Doc and commit msg.
No functional changes.
Changes for v3:
-Added PDI_SRC_DDR macro in the firmware.h file.
drivers/firmware/xilinx/zynqmp.c | 17 +
include/linux/firmware/xlnx-zynqmp.h | 10 ++
2 files changed, 27 insertions(+)
diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
index 7eb9958662dd..9ee02655db89 100644
--- a/drivers/firmware/xilinx/zynqmp.c
+++ b/drivers/firmware/xilinx/zynqmp.c
@@ -897,6 +897,23 @@ int zynqmp_pm_set_requirement(const u32 node, const u32
capabilities,
}
EXPORT_SYMBOL_GPL(zynqmp_pm_set_requirement);
+/**
+ * zynqmp_pm_load_pdi - Load and process PDI
+ * @src: Source device where PDI is located
+ * @address: PDI src address
+ *
+ * This function provides support to load PDI from linux
+ *
+ * Return: Returns status, either success or error+reason
+ */
+int zynqmp_pm_load_pdi(const u32 src, const u64 address)
+{
+ return zynqmp_pm_invoke_fn(PM_LOAD_PDI, src,
+ lower_32_bits(address),
+ upper_32_bits(address), 0, NULL);
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_load_pdi);
+
/**
* zynqmp_pm_aes - Access AES hardware to encrypt/decrypt the data using
* AES-GCM core.
diff --git a/include/linux/firmware/xlnx-zynqmp.h
b/include/linux/firmware/xlnx-zynqmp.h
index 2a0da841c942..3eba9d5c7640 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -52,6 +52,10 @@
#defineZYNQMP_PM_CAPABILITY_WAKEUP 0x4U
#defineZYNQMP_PM_CAPABILITY_UNUSABLE 0x8U
+/* Loader commands */
+#define PM_LOAD_PDI0x701
+#define PDI_SRC_DDR0xF
+
/*
* Firmware FPGA Manager flags
* XILINX_ZYNQMP_PM_FPGA_FULL: FPGA full reconfiguration
@@ -354,6 +358,7 @@ int zynqmp_pm_write_pggs(u32 index, u32 value);
int zynqmp_pm_read_pggs(u32 index, u32 *value);
int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype);
int zynqmp_pm_set_boot_health_status(u32 value);
+int zynqmp_pm_load_pdi(const u32 src, const u64 address);
#else
static inline struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void)
{
@@ -538,6 +543,11 @@ static inline int zynqmp_pm_set_boot_health_status(u32
value)
{
return -ENODEV;
}
+
+static inline int zynqmp_pm_load_pdi(const u32 src, const u64 address)
+{
+ return -ENODEV;
+}
#endif
#endif /* __FIRMWARE_ZYNQMP_H__ */
--
2.18.0
[PATCH v3 0/3] Add Bitstream configuration support for Versal
This series adds FPGA Manager support for the Xilinx Versal chip. Appana Durga Kedareswara rao (1): dt-bindings: fpga: Add binding doc for versal fpga manager Nava kishore Manne (2): drivers: firmware: Add PDI load API support fpga: versal-fpga: Add versal fpga manager driver .../bindings/fpga/xlnx,versal-fpga.yaml | 33 + drivers/firmware/xilinx/zynqmp.c | 17 +++ drivers/fpga/Kconfig | 9 ++ drivers/fpga/Makefile | 1 + drivers/fpga/versal-fpga.c| 117 ++ include/linux/firmware/xlnx-zynqmp.h | 10 ++ 6 files changed, 187 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml create mode 100644 drivers/fpga/versal-fpga.c -- 2.18.0
RE: [PATCH 1/2] fpga: mgr: Adds secure BitStream loading support
Ping! > -Original Message- > From: Nava kishore Manne > Sent: Wednesday, January 27, 2021 2:43 PM > To: Moritz Fischer > Cc: t...@redhat.com; robh...@kernel.org; Michal Simek > ; linux-f...@vger.kernel.org; > devicet...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; linux- > ker...@vger.kernel.org; git ; chinnikishore...@gmail.com > Subject: RE: [PATCH 1/2] fpga: mgr: Adds secure BitStream loading support > > Hi Moritz, > > Thanks for the review. > Please find my response inline. > > > -Original Message- > > From: Moritz Fischer > > Sent: Friday, January 22, 2021 10:47 AM > > To: Nava kishore Manne > > Cc: m...@kernel.org; t...@redhat.com; robh...@kernel.org; Michal Simek > > ; linux-f...@vger.kernel.org; > > devicet...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > > linux- ker...@vger.kernel.org; git ; > > chinnikishore...@gmail.com > > Subject: Re: [PATCH 1/2] fpga: mgr: Adds secure BitStream loading > > support > > > > On Mon, Jan 18, 2021 at 08:20:57AM +0530, Nava kishore Manne wrote: > > > This commit adds secure flags to the framework to support secure > > > BitStream Loading. > > > > > > Signed-off-by: Nava kishore Manne > > > --- > > > drivers/fpga/of-fpga-region.c | 10 ++ > > > include/linux/fpga/fpga-mgr.h | 12 > > > 2 files changed, 22 insertions(+) > > > > > > diff --git a/drivers/fpga/of-fpga-region.c > > > b/drivers/fpga/of-fpga-region.c index e405309baadc..3a5eb480 > > > 100644 > > > --- a/drivers/fpga/of-fpga-region.c > > > +++ b/drivers/fpga/of-fpga-region.c > > > @@ -228,6 +228,16 @@ static struct fpga_image_info > > *of_fpga_region_parse_ov( > > > if (of_property_read_bool(overlay, "encrypted-fpga-config")) > > > info->flags |= FPGA_MGR_ENCRYPTED_BITSTREAM; > > > > > > + if (of_property_read_bool(overlay, "userkey-encrypted-fpga- > > config")) > > > + info->flags |= > > FPGA_MGR_USERKEY_ENCRYPTED_BITSTREAM; > > > > Can this just be encrypted-fpga-config/FPGA_MGR_ENCRYPTED? > > In Encryption we have two kinds of use case one is Encrypted Bitstream > loading with Device-key and Other one is Encrypted Bitstream loading with > User-key. To differentiate both the use cases this Changes are needed. > > Regards, > Navakishore.
RE: [PATCH v2 2/3] dt-bindings: fpga: Add binding doc for versal fpga manager
Hi Rob, Please find my response inline. > -Original Message- > From: Rob Herring > Sent: Thursday, February 11, 2021 8:26 PM > To: Nava kishore Manne > Cc: linux-arm-ker...@lists.infradead.org; m...@kernel.org; linux- > f...@vger.kernel.org; git ; Appana Durga Kedareswara Rao > ; devicet...@vger.kernel.org; robh...@kernel.org; > chinnikishore...@gmail.com; linux-kernel@vger.kernel.org; > t...@redhat.com; Michal Simek > Subject: Re: [PATCH v2 2/3] dt-bindings: fpga: Add binding doc for versal fpga > manager > > On Thu, 11 Feb 2021 11:35:31 +0530, Nava kishore Manne wrote: > > From: Appana Durga Kedareswara rao > > > > This patch adds binding doc for versal fpga manager driver. > > > > Signed-off-by: Nava kishore Manne > > Signed-off-by: Appana Durga Kedareswara rao > > > > --- > > Changes for v2: > > -Fixed file format and syntax issues. > > > > .../bindings/fpga/xlnx,versal-fpga.yaml | 33 +++ > > 1 file changed, 33 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml > > > > My bot found errors running 'make dt_binding_check' on your patch: > > yamllint warnings/errors: > ./Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml:12:14: > [warning] too many spaces after colon (colons) > ./Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml:20:9: > [warning] wrong indentation: expected 10 but found 8 (indentation) > > dtschema/dtc warnings/errors: > > See https://patchwork.ozlabs.org/patch/1439305 > > This check can fail if there are any dependencies. The base for a patch series > is generally the most recent rc1. > > If you already ran 'make dt_binding_check' and didn't see the above error(s), > then make sure 'yamllint' is installed and dt-schema is up to > date: > > pip3 install dtschema --upgrade > > Please check and re-submit. Initially, I couldn't see any issue when I run. After installing yamllint and with upgraded dt-schema, I am able to reproduce the above pointed issues. Is there any prerequisite(Other than yamllint) I need to follow to run dt-schema? Regards, Navakishore.
[PATCH v2 3/3] fpga: versal-fpga: Add versal fpga manager driver
Add support for Xilinx Versal FPGA manager.
PDI source type can be DDR, OCM, QSPI flash etc..
But driver allocates memory always from DDR, Since driver supports only
DDR source type.
Signed-off-by: Appana Durga Kedareswara rao
Signed-off-by: Nava kishore Manne
---
Changes for v2:
-Updated the Fpga Mgr registrations call's
to 5.11
-Fixed some minor coding issues as suggested by
Moritz.
drivers/fpga/Kconfig | 8 +++
drivers/fpga/Makefile | 1 +
drivers/fpga/versal-fpga.c | 120 +
3 files changed, 129 insertions(+)
create mode 100644 drivers/fpga/versal-fpga.c
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index bf85b9a65ec2..dcd2ed5a7956 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -223,4 +223,12 @@ config FPGA_MGR_ZYNQMP_FPGA
to configure the programmable logic(PL) through PS
on ZynqMP SoC.
+config FPGA_MGR_VERSAL_FPGA
+tristate "Xilinx Versal FPGA"
+depends on ARCH_ZYNQMP || COMPILE_TEST
+help
+ Select this option to enable FPGA manager driver support for
+ Xilinx Versal SOC. This driver uses the versal soc firmware
+ interface to load programmable logic(PL) images
+ on versal soc.
endif # FPGA
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index d8e21dfc6778..40c9adb6a644 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o
obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o
obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o
obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) += zynqmp-fpga.o
+obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA) += versal-fpga.o
obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o
obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT)+= altera-pr-ip-core-plat.o
diff --git a/drivers/fpga/versal-fpga.c b/drivers/fpga/versal-fpga.c
new file mode 100644
index ..22d0bfb7b1e6
--- /dev/null
+++ b/drivers/fpga/versal-fpga.c
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019-2021 Xilinx, Inc.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* Constant Definitions */
+#define PDI_SOURCE_TYPE0xF
+
+/**
+ * struct versal_fpga_priv - Private data structure
+ * @dev: Device data structure
+ */
+struct versal_fpga_priv {
+ struct device *dev;
+};
+
+static int versal_fpga_ops_write_init(struct fpga_manager *mgr,
+ struct fpga_image_info *info,
+ const char *buf, size_t size)
+{
+ return 0;
+}
+
+static int versal_fpga_ops_write(struct fpga_manager *mgr,
+const char *buf, size_t size)
+{
+ struct versal_fpga_priv *priv;
+ dma_addr_t dma_addr = 0;
+ char *kbuf;
+ int ret;
+
+ priv = mgr->priv;
+
+ kbuf = dma_alloc_coherent(priv->dev, size, _addr, GFP_KERNEL);
+ if (!kbuf)
+ return -ENOMEM;
+
+ memcpy(kbuf, buf, size);
+
+ wmb(); /* ensure all writes are done before initiate FW call */
+
+ ret = zynqmp_pm_load_pdi(PDI_SOURCE_TYPE, dma_addr);
+
+ dma_free_coherent(priv->dev, size, kbuf, dma_addr);
+
+ return ret;
+}
+
+static int versal_fpga_ops_write_complete(struct fpga_manager *mgr,
+ struct fpga_image_info *info)
+{
+ return 0;
+}
+
+static enum fpga_mgr_states versal_fpga_ops_state(struct fpga_manager *mgr)
+{
+ return FPGA_MGR_STATE_UNKNOWN;
+}
+
+static const struct fpga_manager_ops versal_fpga_ops = {
+ .state = versal_fpga_ops_state,
+ .write_init = versal_fpga_ops_write_init,
+ .write = versal_fpga_ops_write,
+ .write_complete = versal_fpga_ops_write_complete,
+};
+
+static int versal_fpga_probe(struct platform_device *pdev)
+{
+ struct device *dev = >dev;
+ struct versal_fpga_priv *priv;
+ struct fpga_manager *mgr;
+ int ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->dev = dev;
+ ret = dma_set_mask_and_coherent(>dev, DMA_BIT_MASK(32));
+ if (ret < 0) {
+ dev_err(dev, "no usable DMA configuration\n");
+ return ret;
+ }
+
+ mgr = devm_fpga_mgr_create(dev, "Xilinx Versal FPGA Manager",
+ _fpga_ops, priv);
+ if (!mgr)
+ return -ENOMEM;
+
+ return devm_fpga_mgr_register(dev, mgr);
+}
+
+static const struct of_device_id versal_fpga_of_match[] = {
+ { .compatible = "xlnx,versal-fpga", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, versal_fpga_of_match);
+
+static struct platform_driver versal_fpga_d
[PATCH v2 1/3] drivers: firmware: Add PDI load API support
This patch adds load PDI API support to enable PDI/partial loading from
linux. Programmable Device Image (PDI) is combination of headers, images
and bitstream files to be loaded. Partial PDI is partial set of image/
images to be loaded.
Signed-off-by: Nava kishore Manne
---
Changes for v2:
-Updated API Doc and commit msg.
No functional changes.
drivers/firmware/xilinx/zynqmp.c | 17 +
include/linux/firmware/xlnx-zynqmp.h | 9 +
2 files changed, 26 insertions(+)
diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
index 7eb9958662dd..9ee02655db89 100644
--- a/drivers/firmware/xilinx/zynqmp.c
+++ b/drivers/firmware/xilinx/zynqmp.c
@@ -897,6 +897,23 @@ int zynqmp_pm_set_requirement(const u32 node, const u32
capabilities,
}
EXPORT_SYMBOL_GPL(zynqmp_pm_set_requirement);
+/**
+ * zynqmp_pm_load_pdi - Load and process PDI
+ * @src: Source device where PDI is located
+ * @address: PDI src address
+ *
+ * This function provides support to load PDI from linux
+ *
+ * Return: Returns status, either success or error+reason
+ */
+int zynqmp_pm_load_pdi(const u32 src, const u64 address)
+{
+ return zynqmp_pm_invoke_fn(PM_LOAD_PDI, src,
+ lower_32_bits(address),
+ upper_32_bits(address), 0, NULL);
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_load_pdi);
+
/**
* zynqmp_pm_aes - Access AES hardware to encrypt/decrypt the data using
* AES-GCM core.
diff --git a/include/linux/firmware/xlnx-zynqmp.h
b/include/linux/firmware/xlnx-zynqmp.h
index 2a0da841c942..87114ee645b1 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -52,6 +52,9 @@
#defineZYNQMP_PM_CAPABILITY_WAKEUP 0x4U
#defineZYNQMP_PM_CAPABILITY_UNUSABLE 0x8U
+/* Loader commands */
+#define PM_LOAD_PDI0x701
+
/*
* Firmware FPGA Manager flags
* XILINX_ZYNQMP_PM_FPGA_FULL: FPGA full reconfiguration
@@ -354,6 +357,7 @@ int zynqmp_pm_write_pggs(u32 index, u32 value);
int zynqmp_pm_read_pggs(u32 index, u32 *value);
int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype);
int zynqmp_pm_set_boot_health_status(u32 value);
+int zynqmp_pm_load_pdi(const u32 src, const u64 address);
#else
static inline struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void)
{
@@ -538,6 +542,11 @@ static inline int zynqmp_pm_set_boot_health_status(u32
value)
{
return -ENODEV;
}
+
+static inline int zynqmp_pm_load_pdi(const u32 src, const u64 address)
+{
+ return -ENODEV;
+}
#endif
#endif /* __FIRMWARE_ZYNQMP_H__ */
--
2.18.0
[PATCH v2 2/3] dt-bindings: fpga: Add binding doc for versal fpga manager
From: Appana Durga Kedareswara rao
This patch adds binding doc for versal fpga manager driver.
Signed-off-by: Nava kishore Manne
Signed-off-by: Appana Durga Kedareswara rao
---
Changes for v2:
-Fixed file format and syntax issues.
.../bindings/fpga/xlnx,versal-fpga.yaml | 33 +++
1 file changed, 33 insertions(+)
create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml
diff --git a/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml
b/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml
new file mode 100644
index ..65d6877b913e
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/fpga/xlnx,versal-fpga.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx Versal FPGA driver.
+
+maintainers:
+ - Nava kishore Manne
+
+description: |
+ Device Tree Versal FPGA bindings for the Versal SoC, controlled
+ using firmware interface.
+
+properties:
+ compatible:
+items:
+ - enum:
+- xlnx,versal-fpga
+
+required:
+ - compatible
+
+additionalProperties: false
+
+examples:
+ - |
+versal_fpga: fpga {
+ compatible = "xlnx,versal-fpga";
+};
+
+...
--
2.18.0
[PATCH v2 0/3] Add Bitstream configuration support for Versal
Appana Durga Kedareswara rao (1): dt-bindings: fpga: Add binding doc for versal fpga manager Nava kishore Manne (2): drivers: firmware: Add PDI load API support fpga: versal-fpga: Add versal fpga manager driver .../bindings/fpga/xlnx,versal-fpga.yaml | 33 + drivers/firmware/xilinx/zynqmp.c | 17 +++ drivers/fpga/Kconfig | 8 ++ drivers/fpga/Makefile | 1 + drivers/fpga/versal-fpga.c| 120 ++ include/linux/firmware/xlnx-zynqmp.h | 9 ++ 6 files changed, 188 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml create mode 100644 drivers/fpga/versal-fpga.c -- 2.18.0
[PATCH v2 1/2] dt-bindings: fpga: Add compatible value for Xilinx DFX AXI shutdown manager
This patch Adds compatible value for Xilinx Dynamic Function eXchnage(DFX)
AXI Shutdown manager IP.
Signed-off-by: Nava kishore Manne
---
Changes for v2:
-Modified the doc and added DFX axi shutdown manager node
example node as suggested by Tom Rix.
.../bindings/fpga/xilinx-pr-decoupler.txt | 24 ++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt
b/Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt
index 4284d293fa61..0acdfa6d62a4 100644
--- a/Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt
+++ b/Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt
@@ -7,13 +7,24 @@ changes from passing through the bridge. The controller can
also
couple / enable the bridges which allows traffic to pass through the
bridge normally.
+Xilinx LogiCORE Dynamic Function eXchange(DFX) AXI shutdown manager
+Softcore is compatible with the Xilinx LogiCORE pr-decoupler.
+
+The Dynamic Function eXchange AXI shutdown manager prevents AXI traffic
+from passing through the bridge. The controller safely handles AXI4MM
+and AXI4-Lite interfaces on a Reconfigurable Partition when it is
+undergoing dynamic reconfiguration, preventing the system deadlock
+that can occur if AXI transactions are interrupted by DFX
+
The Driver supports only MMIO handling. A PR region can have multiple
PR Decouplers which can be handled independently or chained via decouple/
decouple_status signals.
Required properties:
- compatible : Should contain "xlnx,pr-decoupler-1.00" followed by
- "xlnx,pr-decoupler"
+ "xlnx,pr-decoupler" or
+ "xlnx,dfx-axi-shutdown-manager-1.00" followed by
+ "xlnx,dfx-axi-shutdown-manager"
- regs : base address and size for decoupler module
- clocks : input clock to IP
- clock-names : should contain "aclk"
@@ -22,6 +33,7 @@ See Documentation/devicetree/bindings/fpga/fpga-region.txt and
Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
Example:
+Partial Reconfig Decoupler:
fpga-bridge@10450 {
compatible = "xlnx,pr-decoupler-1.00",
"xlnx-pr-decoupler";
@@ -30,3 +42,13 @@ Example:
clock-names = "aclk";
bridge-enable = <0>;
};
+
+Dynamic Function eXchange AXI shutdown manager:
+ fpga-bridge@10450 {
+ compatible = "xlnx,dfx-axi-shutdown-manager-1.00",
+"xlnx,dfx-axi-shutdown-manager";
+ regs = <0x1045 0x10>;
+ clocks = < 15>;
+ clock-names = "aclk";
+ bridge-enable = <0>;
+ };
--
2.18.0
[PATCH v2 2/2] fpga: Add support for Xilinx DFX AXI Shutdown manager
This patch adds support for Xilinx Dynamic Function eXchange(DFX) AXI
shutdown manager IP. It can be used to safely handling the AXI traffic
on a Reconfigurable Partition when it is undergoing dynamic reconfiguration
and there by preventing system deadlock that may occur if AXI transactions
are interrupted during reconfiguration.
PR-Decoupler and AXI shutdown manager are completely different IPs.
But both the IP registers are compatible and also both belong to the
same sub-system (fpga-bridge).So using same driver for both IP's.
Signed-off-by: Nava kishore Manne
---
Changes for v2:
-Fixed some minor coding issues as suggested by
Tom Rix.
drivers/fpga/Kconfig | 9 +++-
drivers/fpga/xilinx-pr-decoupler.c | 37 ++
2 files changed, 40 insertions(+), 6 deletions(-)
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index 5645226ca3ce..bf85b9a65ec2 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -118,10 +118,17 @@ config XILINX_PR_DECOUPLER
depends on FPGA_BRIDGE
depends on HAS_IOMEM
help
- Say Y to enable drivers for Xilinx LogiCORE PR Decoupler.
+ Say Y to enable drivers for Xilinx LogiCORE PR Decoupler
+ or Xilinx Dynamic Function eXchnage AIX Shutdown Manager.
The PR Decoupler exists in the FPGA fabric to isolate one
region of the FPGA from the busses while that region is
being reprogrammed during partial reconfig.
+ The Dynamic Function eXchange AXI shutdown manager prevents
+ AXI traffic from passing through the bridge. The controller
+ safely handles AXI4MM and AXI4-Lite interfaces on a
+ Reconfigurable Partition when it is undergoing dynamic
+ reconfiguration, preventing the system deadlock that can
+ occur if AXI transactions are interrupted by DFX.
config FPGA_REGION
tristate "FPGA Region"
diff --git a/drivers/fpga/xilinx-pr-decoupler.c
b/drivers/fpga/xilinx-pr-decoupler.c
index 7d69af230567..78a6f5324193 100644
--- a/drivers/fpga/xilinx-pr-decoupler.c
+++ b/drivers/fpga/xilinx-pr-decoupler.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2017, National Instruments Corp.
- * Copyright (c) 2017, Xilix Inc
+ * Copyright (c) 2017, Xilinx Inc
*
* FPGA Bridge Driver for the Xilinx LogiCORE Partial Reconfiguration
* Decoupler IP Core.
@@ -18,7 +18,12 @@
#define CTRL_CMD_COUPLE0
#define CTRL_OFFSET0
+struct xlnx_config_data {
+ const char *name;
+};
+
struct xlnx_pr_decoupler_data {
+ const struct xlnx_config_data *ipconfig;
void __iomem *io_base;
struct clk *clk;
};
@@ -76,15 +81,28 @@ static const struct fpga_bridge_ops
xlnx_pr_decoupler_br_ops = {
.enable_show = xlnx_pr_decoupler_enable_show,
};
+static const struct xlnx_config_data decoupler_config = {
+ .name = "Xilinx PR Decoupler",
+};
+
+static const struct xlnx_config_data shutdown_config = {
+ .name = "Xilinx DFX AXI Shutdown Manager",
+};
+
static const struct of_device_id xlnx_pr_decoupler_of_match[] = {
- { .compatible = "xlnx,pr-decoupler-1.00", },
- { .compatible = "xlnx,pr-decoupler", },
+ { .compatible = "xlnx,pr-decoupler-1.00", .data = _config },
+ { .compatible = "xlnx,pr-decoupler", .data = _config },
+ { .compatible = "xlnx,dfx-axi-shutdown-manager-1.00",
+ .data = _config },
+ { .compatible = "xlnx,dfx-axi-shutdown-manager",
+ .data = _config },
{},
};
MODULE_DEVICE_TABLE(of, xlnx_pr_decoupler_of_match);
static int xlnx_pr_decoupler_probe(struct platform_device *pdev)
{
+ struct device_node *np = pdev->dev.of_node;
struct xlnx_pr_decoupler_data *priv;
struct fpga_bridge *br;
int err;
@@ -94,6 +112,14 @@ static int xlnx_pr_decoupler_probe(struct platform_device
*pdev)
if (!priv)
return -ENOMEM;
+ if (np) {
+ const struct of_device_id *match;
+
+ match = of_match_node(xlnx_pr_decoupler_of_match, np);
+ if (match && match->data)
+ priv->ipconfig = match->data;
+ }
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
priv->io_base = devm_ioremap_resource(>dev, res);
if (IS_ERR(priv->io_base))
@@ -114,7 +140,7 @@ static int xlnx_pr_decoupler_probe(struct platform_device
*pdev)
clk_disable(priv->clk);
- br = devm_fpga_bridge_create(>dev, "Xilinx PR Decoupler",
+ br = devm_fpga_bridge_create(>dev, priv->ipconfig->name,
_pr_decoupler_br_ops, priv);
if (!br) {
[PATCH v2 0/2] Add DFX AXI Shutdown manager IP support for Xilinx
Nava kishore Manne (2): dt-bindings: fpga: Add compatible value for Xilinx DFX AXI shutdown manager fpga: Add support for Xilinx DFX AXI Shutdown manager .../bindings/fpga/xilinx-pr-decoupler.txt | 24 +++- drivers/fpga/Kconfig | 9 - drivers/fpga/xilinx-pr-decoupler.c| 37 --- 3 files changed, 63 insertions(+), 7 deletions(-) -- 2.18.0
RE: [PATCH 3/3] fpga: versal-fpga: Add versal fpga manager driver
Hi, > -Original Message- > From: Moritz Fischer > Sent: Thursday, January 28, 2021 3:15 AM > To: Michal Simek > Cc: Nava kishore Manne ; Moritz Fischer > ; t...@redhat.com; robh...@kernel.org; linux- > f...@vger.kernel.org; devicet...@vger.kernel.org; linux-arm- > ker...@lists.infradead.org; linux-kernel@vger.kernel.org; git > ; chinnikishore...@gmail.com; Appana Durga Kedareswara > Rao > Subject: Re: [PATCH 3/3] fpga: versal-fpga: Add versal fpga manager driver > > On Wed, Jan 27, 2021 at 10:16:32AM +0100, Michal Simek wrote: > > Hi > > > > On 1/27/21 9:57 AM, Nava kishore Manne wrote: > > > Hi Moritz, > > > > > > Please find my response inline. > > > > > >> -Original Message- > > >> From: Moritz Fischer > > >> Sent: Sunday, January 24, 2021 5:04 AM > > >> To: Nava kishore Manne > > >> Cc: Moritz Fischer ; t...@redhat.com; > > >> robh...@kernel.org; Michal Simek ; linux- > > >> f...@vger.kernel.org; devicet...@vger.kernel.org; linux-arm- > > >> ker...@lists.infradead.org; linux-kernel@vger.kernel.org; git > > >> ; chinnikishore...@gmail.com; Appana Durga > > >> Kedareswara Rao > > >> Subject: Re: [PATCH 3/3] fpga: versal-fpga: Add versal fpga manager > > >> driver > > >> > > >> Hi Nava, > > >> > > >> On Fri, Jan 22, 2021 at 10:34:15AM +0000, Nava kishore Manne wrote: > > >>> Hi Moritz, > > >>> > > >>> Thanks for the review. > > >>> Please find my response inline. > > >>> > > >>>> -Original Message- > > >>>> From: Moritz Fischer > > >>>> Sent: Tuesday, January 19, 2021 6:03 AM > > >>>> To: Nava kishore Manne > > >>>> Cc: m...@kernel.org; t...@redhat.com; robh...@kernel.org; Michal > > >>>> Simek ; linux-f...@vger.kernel.org; > > >>>> devicet...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > > >>>> linux- ker...@vger.kernel.org; git ; > > >>>> chinnikishore...@gmail.com; Appana Durga Kedareswara Rao > > >>>> > > >>>> Subject: Re: [PATCH 3/3] fpga: versal-fpga: Add versal fpga > > >>>> manager driver > > >>>> > > >>>> Hi Nava, > > >>>> > > >>>> On Mon, Jan 18, 2021 at 08:13:18AM +0530, Nava kishore Manne > wrote: > > >>>>> This patch adds driver for versal fpga manager. > > >>>> Nit: Add support for Xilinx Versal FPGA manager > > >>> > > >>> Will fix in v2. > > >>> > > >>>>> > > >>>>> PDI source type can be DDR, OCM, QSPI flash etc.. > > >>>> No idea what PDI is :) > > >>> > > >>> Programmable device image (PDI). > > >>> This file is generated by Xilinx Vivado tool and it contains > > >>> configuration data > > >> objects. > > >>> > > >>>>> But driver allocates memory always from DDR, Since driver > > >>>>> supports only DDR source type. > > >>>>> > > >>>>> Signed-off-by: Appana Durga Kedareswara rao > > >>>>> > > >>>>> Signed-off-by: Nava kishore Manne > > >>>>> --- > > >>>>> drivers/fpga/Kconfig | 8 ++ > > >>>>> drivers/fpga/Makefile | 1 + > > >>>>> drivers/fpga/versal-fpga.c | 149 > > >>>>> + > > >>>>> 3 files changed, 158 insertions(+) create mode 100644 > > >>>>> drivers/fpga/versal-fpga.c > > >>>>> > > >>>>> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index > > >>>>> 5645226ca3ce..9f779c3a6739 100644 > > >>>>> --- a/drivers/fpga/Kconfig > > >>>>> +++ b/drivers/fpga/Kconfig > > >>>>> @@ -216,4 +216,12 @@ config FPGA_MGR_ZYNQMP_FPGA > > >>>>> to configure the programmable logic(PL) through PS > > >>>>> on ZynqMP SoC. > > >>>>> > > >>>>> +config FPGA_MGR_VERSAL_FPGA > > >>>>> +tristate "Xilinx Versal FPGA" > > >>>>> +depends on ARCH_
RE: [PATCH 1/2] fpga: mgr: Adds secure BitStream loading support
Hi Moritz, Thanks for the review. Please find my response inline. > -Original Message- > From: Moritz Fischer > Sent: Friday, January 22, 2021 10:47 AM > To: Nava kishore Manne > Cc: m...@kernel.org; t...@redhat.com; robh...@kernel.org; Michal Simek > ; linux-f...@vger.kernel.org; > devicet...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; linux- > ker...@vger.kernel.org; git ; chinnikishore...@gmail.com > Subject: Re: [PATCH 1/2] fpga: mgr: Adds secure BitStream loading support > > On Mon, Jan 18, 2021 at 08:20:57AM +0530, Nava kishore Manne wrote: > > This commit adds secure flags to the framework to support secure > > BitStream Loading. > > > > Signed-off-by: Nava kishore Manne > > --- > > drivers/fpga/of-fpga-region.c | 10 ++ > > include/linux/fpga/fpga-mgr.h | 12 > > 2 files changed, 22 insertions(+) > > > > diff --git a/drivers/fpga/of-fpga-region.c > > b/drivers/fpga/of-fpga-region.c index e405309baadc..3a5eb480 > > 100644 > > --- a/drivers/fpga/of-fpga-region.c > > +++ b/drivers/fpga/of-fpga-region.c > > @@ -228,6 +228,16 @@ static struct fpga_image_info > *of_fpga_region_parse_ov( > > if (of_property_read_bool(overlay, "encrypted-fpga-config")) > > info->flags |= FPGA_MGR_ENCRYPTED_BITSTREAM; > > > > + if (of_property_read_bool(overlay, "userkey-encrypted-fpga- > config")) > > + info->flags |= > FPGA_MGR_USERKEY_ENCRYPTED_BITSTREAM; > > Can this just be encrypted-fpga-config/FPGA_MGR_ENCRYPTED? In Encryption we have two kinds of use case one is Encrypted Bitstream loading with Device-key and Other one is Encrypted Bitstream loading with User-key. To differentiate both the use cases this Changes are needed. Regards, Navakishore.
RE: [PATCH 3/3] fpga: versal-fpga: Add versal fpga manager driver
Hi Moritz, Please find my response inline. > -Original Message- > From: Moritz Fischer > Sent: Sunday, January 24, 2021 5:04 AM > To: Nava kishore Manne > Cc: Moritz Fischer ; t...@redhat.com; > robh...@kernel.org; Michal Simek ; linux- > f...@vger.kernel.org; devicet...@vger.kernel.org; linux-arm- > ker...@lists.infradead.org; linux-kernel@vger.kernel.org; git > ; chinnikishore...@gmail.com; Appana Durga Kedareswara > Rao > Subject: Re: [PATCH 3/3] fpga: versal-fpga: Add versal fpga manager driver > > Hi Nava, > > On Fri, Jan 22, 2021 at 10:34:15AM +, Nava kishore Manne wrote: > > Hi Moritz, > > > > Thanks for the review. > > Please find my response inline. > > > > > -Original Message- > > > From: Moritz Fischer > > > Sent: Tuesday, January 19, 2021 6:03 AM > > > To: Nava kishore Manne > > > Cc: m...@kernel.org; t...@redhat.com; robh...@kernel.org; Michal > > > Simek ; linux-f...@vger.kernel.org; > > > devicet...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > > > linux- ker...@vger.kernel.org; git ; > > > chinnikishore...@gmail.com; Appana Durga Kedareswara Rao > > > > > > Subject: Re: [PATCH 3/3] fpga: versal-fpga: Add versal fpga manager > > > driver > > > > > > Hi Nava, > > > > > > On Mon, Jan 18, 2021 at 08:13:18AM +0530, Nava kishore Manne wrote: > > > > This patch adds driver for versal fpga manager. > > > Nit: Add support for Xilinx Versal FPGA manager > > > > Will fix in v2. > > > > > > > > > > PDI source type can be DDR, OCM, QSPI flash etc.. > > > No idea what PDI is :) > > > > Programmable device image (PDI). > > This file is generated by Xilinx Vivado tool and it contains configuration > > data > objects. > > > > > > But driver allocates memory always from DDR, Since driver supports > > > > only DDR source type. > > > > > > > > Signed-off-by: Appana Durga Kedareswara rao > > > > > > > > Signed-off-by: Nava kishore Manne > > > > --- > > > > drivers/fpga/Kconfig | 8 ++ > > > > drivers/fpga/Makefile | 1 + > > > > drivers/fpga/versal-fpga.c | 149 > > > > + > > > > 3 files changed, 158 insertions(+) create mode 100644 > > > > drivers/fpga/versal-fpga.c > > > > > > > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index > > > > 5645226ca3ce..9f779c3a6739 100644 > > > > --- a/drivers/fpga/Kconfig > > > > +++ b/drivers/fpga/Kconfig > > > > @@ -216,4 +216,12 @@ config FPGA_MGR_ZYNQMP_FPGA > > > > to configure the programmable logic(PL) through PS > > > > on ZynqMP SoC. > > > > > > > > +config FPGA_MGR_VERSAL_FPGA > > > > +tristate "Xilinx Versal FPGA" > > > > +depends on ARCH_ZYNQMP || COMPILE_TEST > > > > +help > > > > + Select this option to enable FPGA manager driver support for > > > > + Xilinx Versal SOC. This driver uses the versal soc firmware > > > > + interface to load programmable logic(PL) images > > > > + on versal soc. > > > > endif # FPGA > > > > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index > > > > d8e21dfc6778..40c9adb6a644 100644 > > > > --- a/drivers/fpga/Makefile > > > > +++ b/drivers/fpga/Makefile > > > > @@ -18,6 +18,7 @@ obj-$(CONFIG_FPGA_MGR_TS73XX) += > > > ts73xx-fpga.o > > > > obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o > > > > obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o > > > > obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) += zynqmp-fpga.o > > > > +obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA) += versal-fpga.o > > > > obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o > > > > obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT)+= altera-pr-ip-core-plat.o > > > > > > > > diff --git a/drivers/fpga/versal-fpga.c > > > > b/drivers/fpga/versal-fpga.c new file mode 100644 index > > > > ..2a42aa78b182 > > > > --- /dev/null > > > > +++ b/drivers/fpga/versal-fpga.c > > > > @@ -0,0 +1,149 @@ > > > > +// SPDX-License-Identifier: GPL-2.0+ > > > > +/* > > > > + * Copyright (C) 2021 Xilinx,
RE: [PATCH 2/2] fpga: Add support for Xilinx DFX AXI Shutdown manager
Hi Moritz, Please find my response inline. > -Original Message- > From: Moritz Fischer > Sent: Friday, January 22, 2021 10:45 AM > To: Nava kishore Manne > Cc: Moritz Fischer ; t...@redhat.com; > robh...@kernel.org; Michal Simek ; linux- > f...@vger.kernel.org; devicet...@vger.kernel.org; linux-arm- > ker...@lists.infradead.org; linux-kernel@vger.kernel.org; git > ; chinnikishore...@gmail.com > Subject: Re: [PATCH 2/2] fpga: Add support for Xilinx DFX AXI Shutdown > manager > > On Tue, Jan 19, 2021 at 06:34:54AM +, Nava kishore Manne wrote: > > Hi Moritz, > > > > Thanks for the review. > > Please find my response inline. > > > > > -Original Message- > > > From: Moritz Fischer > > > Sent: Saturday, January 16, 2021 8:28 AM > > > To: Nava kishore Manne > > > Cc: m...@kernel.org; t...@redhat.com; robh...@kernel.org; Michal > > > Simek ; linux-f...@vger.kernel.org; > > > devicet...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; > > > linux- ker...@vger.kernel.org; git ; > > > chinnikishore...@gmail.com > > > Subject: Re: [PATCH 2/2] fpga: Add support for Xilinx DFX AXI > > > Shutdown manager > > > > > > Hi, > > > > > > On Fri, Jan 15, 2021 at 07:04:31AM +0530, Nava kishore Manne wrote: > > > > This patch adds support for Xilinx Dynamic Function eXchange(DFX) > > > > AXI shutdown manager IP. It can be used to safely handling the AXI > > > > traffic on a Reconfigurable Partition when it is undergoing > > > > dynamic reconfiguration and there by preventing system deadlock > > > > that may occur if AXI transactions are interrupted during > reconfiguration. > > > > > > > > PR-Decoupler and AXI shutdown manager are completely different IPs. > > > > But both the IP registers are compatible and also both belong to > > > > the same sub-system (fpga-bridge).So using same driver for both IP's. > > > > > > I'm a bit confused, the whole goal here is to give the thing a different > name? > > > > > > Both the PR Decoupler and AXI Shutdown IP manager IP's are follows same > register spec. > > Most of the code is common so we thought of reusing same driver for AXI > shutdown manager as well. > > What are the differences, though other than it shows a different name? The PR-Decoupler And Axi Shut down manager are different IP's PR-Decoupler IP can be used to make the interface between a Reconfigurable Partition and the static logic safe while Partial Reconfiguration is occurring. When active, user-selected signals crossing between the Reconfigurable Partition and the static logic are driven to user configurable values. When inactive, signals are passed unaltered. Coming to the Axi Shutdown manager IP it's safely handles AXI4MM and AXI4-Lite interfaces on a Reconfigurable Partition when it is undergoing dynamic reconfiguration (DFX), preventing system deadlock that can occur if AXI transactions are interrupted by DFX. For more details please refer the below links: https://www.xilinx.com/support/documentation/ip_documentation/pr_decoupler/v1_0/pg227-pr-decoupler.pdf https://www.xilinx.com/support/documentation/ip_documentation/dfx_axi_shutdown_manager/v1_0/pg377-dfx-axi-shutdown-manager.pdf Both the IP functionality's are different but the IP's registers spec is same and also they fall under the same bridge drivers category and most of the code is common except the naming conventions. So we thought of using the same driver for both the IP's with different naming conventions. Regards, Navakishore.
RE: [PATCH 3/3] fpga: versal-fpga: Add versal fpga manager driver
Hi Moritz,
Thanks for the review.
Please find my response inline.
> -Original Message-
> From: Moritz Fischer
> Sent: Tuesday, January 19, 2021 6:03 AM
> To: Nava kishore Manne
> Cc: m...@kernel.org; t...@redhat.com; robh...@kernel.org; Michal Simek
> ; linux-f...@vger.kernel.org;
> devicet...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; linux-
> ker...@vger.kernel.org; git ; chinnikishore...@gmail.com;
> Appana Durga Kedareswara Rao
> Subject: Re: [PATCH 3/3] fpga: versal-fpga: Add versal fpga manager driver
>
> Hi Nava,
>
> On Mon, Jan 18, 2021 at 08:13:18AM +0530, Nava kishore Manne wrote:
> > This patch adds driver for versal fpga manager.
> Nit: Add support for Xilinx Versal FPGA manager
Will fix in v2.
> >
> > PDI source type can be DDR, OCM, QSPI flash etc..
> No idea what PDI is :)
Programmable device image (PDI).
This file is generated by Xilinx Vivado tool and it contains configuration data
objects.
> > But driver allocates memory always from DDR, Since driver supports
> > only DDR source type.
> >
> > Signed-off-by: Appana Durga Kedareswara rao
> >
> > Signed-off-by: Nava kishore Manne
> > ---
> > drivers/fpga/Kconfig | 8 ++
> > drivers/fpga/Makefile | 1 +
> > drivers/fpga/versal-fpga.c | 149
> > +
> > 3 files changed, 158 insertions(+)
> > create mode 100644 drivers/fpga/versal-fpga.c
> >
> > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index
> > 5645226ca3ce..9f779c3a6739 100644
> > --- a/drivers/fpga/Kconfig
> > +++ b/drivers/fpga/Kconfig
> > @@ -216,4 +216,12 @@ config FPGA_MGR_ZYNQMP_FPGA
> > to configure the programmable logic(PL) through PS
> > on ZynqMP SoC.
> >
> > +config FPGA_MGR_VERSAL_FPGA
> > +tristate "Xilinx Versal FPGA"
> > +depends on ARCH_ZYNQMP || COMPILE_TEST
> > +help
> > + Select this option to enable FPGA manager driver support for
> > + Xilinx Versal SOC. This driver uses the versal soc firmware
> > + interface to load programmable logic(PL) images
> > + on versal soc.
> > endif # FPGA
> > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index
> > d8e21dfc6778..40c9adb6a644 100644
> > --- a/drivers/fpga/Makefile
> > +++ b/drivers/fpga/Makefile
> > @@ -18,6 +18,7 @@ obj-$(CONFIG_FPGA_MGR_TS73XX) +=
> ts73xx-fpga.o
> > obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o
> > obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o
> > obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) += zynqmp-fpga.o
> > +obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA) += versal-fpga.o
> > obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o
> > obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT)+= altera-pr-ip-core-plat.o
> >
> > diff --git a/drivers/fpga/versal-fpga.c b/drivers/fpga/versal-fpga.c
> > new file mode 100644 index ..2a42aa78b182
> > --- /dev/null
> > +++ b/drivers/fpga/versal-fpga.c
> > @@ -0,0 +1,149 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (C) 2021 Xilinx, Inc.
> > + */
> > +
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +
> > +/* Constant Definitions */
> > +#define PDI_SOURCE_TYPE0xF
> > +
> > +/**
> > + * struct versal_fpga_priv - Private data structure
> > + * @dev: Device data structure
> > + * @flags: flags which is used to identify the PL Image type
> > + */
> > +struct versal_fpga_priv {
> > + struct device *dev;
> > + u32 flags;
> This seems unused ... please introduce them when/if you start using them.
Will fix in v2.
> > +};
> > +
> > +static int versal_fpga_ops_write_init(struct fpga_manager *mgr,
> > + struct fpga_image_info *info,
> > + const char *buf, size_t size) {
> > + struct versal_fpga_priv *priv;
> > +
> > + priv = mgr->priv;
> > + priv->flags = info->flags;
> ? What uses this ? It seems this function could just be 'return 0' right now.
Will fix in v2.
> > +
> > + return 0;
> > +}
> > +
> > +static int versal_fpga_ops_write(struct fpga_manager *mgr,
> > +const char *buf, size_t size)
> > +{
> > + struct versal_fpga_priv *priv;
> > + dma_addr_t dma_addr = 0;
> > + char *kbuf;
> > + int ret
RE: [PATCH 2/3] dt-bindings: fpga: Add binding doc for versal fpga manager
Hi Michal,
Thanks for the review.
Please find my response inline.
> -Original Message-
> From: Michal Simek
> Sent: Monday, January 18, 2021 2:22 PM
> To: Nava kishore Manne ; m...@kernel.org;
> t...@redhat.com; robh...@kernel.org; Michal Simek ;
> linux-f...@vger.kernel.org; devicet...@vger.kernel.org; linux-arm-
> ker...@lists.infradead.org; linux-kernel@vger.kernel.org
> Cc: git ; chinnikishore...@gmail.com; Appana Durga
> Kedareswara Rao
> Subject: Re: [PATCH 2/3] dt-bindings: fpga: Add binding doc for versal fpga
> manager
>
>
>
> On 1/18/21 3:43 AM, Nava kishore Manne wrote:
> > From: Appana Durga Kedareswara rao
> >
> > This patch adds binding doc for versal fpga manager driver.
> >
> > Signed-off-by: Nava kishore Manne
> > Signed-off-by: Appana Durga Kedareswara rao
> >
> > ---
> > .../bindings/fpga/xlnx,versal-fpga.yaml | 33 +++
> > 1 file changed, 33 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml
> > b/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml
> > new file mode 100644
> > index ..cf3aa7917488
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml
> > @@ -0,0 +1,33 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +
> > +$id: http://devicetree.org/schemas/fpga/xilinx/xlnx,versal-fpga.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Xilinx versal-fpga driver.
> > +
> > +maintainers:
> > + - Nava kishore Manne
> > +
> > +description: |
> > +Device Tree versal-fpga bindings for the Versal SOC, Controlled using
> > +Versal SoC firmware interface.
> > +
> > +properties:
> > + compatible:
> > +items:
> > + - enum:
> > +- xlnx,versal-fpga
> > +
> > +required:
> > + - compatible
> > +
> > +Required properties:
> > +- compatible: should contain "xlnx,versal-fpga"
> > +
> > +examples:
> > + - |
> > +versal_fpga: fpga {
> > + compatible = "xlnx,versal-fpga";
> > +};
> >
>
> There are issues with the binding
> Run
> make
> DT_SCHEMA_FILES=Documentation/devicetree/bindings/fpga/xlnx,versal-
> fpga.yaml
> dt_binding_check
>
Thanks for pointing it. Will fix in v2.
> and fix
> ./Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml:15:1:
> [error] syntax error: could not find expected ':' (syntax) and maybe others.
>
Will fix in v2.
Regards,
Navakishore.
RE: [PATCH 2/2] fpga: Add support for Xilinx DFX AXI Shutdown manager
Hi Moritz,
Thanks for the review.
Please find my response inline.
> -Original Message-
> From: Moritz Fischer
> Sent: Saturday, January 16, 2021 8:28 AM
> To: Nava kishore Manne
> Cc: m...@kernel.org; t...@redhat.com; robh...@kernel.org; Michal Simek
> ; linux-f...@vger.kernel.org;
> devicet...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; linux-
> ker...@vger.kernel.org; git ; chinnikishore...@gmail.com
> Subject: Re: [PATCH 2/2] fpga: Add support for Xilinx DFX AXI Shutdown
> manager
>
> Hi,
>
> On Fri, Jan 15, 2021 at 07:04:31AM +0530, Nava kishore Manne wrote:
> > This patch adds support for Xilinx Dynamic Function eXchange(DFX) AXI
> > shutdown manager IP. It can be used to safely handling the AXI traffic
> > on a Reconfigurable Partition when it is undergoing dynamic
> > reconfiguration and there by preventing system deadlock that may occur
> > if AXI transactions are interrupted during reconfiguration.
> >
> > PR-Decoupler and AXI shutdown manager are completely different IPs.
> > But both the IP registers are compatible and also both belong to the
> > same sub-system (fpga-bridge).So using same driver for both IP's.
>
> I'm a bit confused, the whole goal here is to give the thing a different name?
Both the PR Decoupler and AXI Shutdown IP manager IP's are follows same
register spec.
Most of the code is common so we thought of reusing same driver for AXI
shutdown manager as well.
> >
> > Signed-off-by: Nava kishore Manne
> > ---
> > drivers/fpga/xilinx-pr-decoupler.c | 35
> > ++
> > 1 file changed, 31 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/fpga/xilinx-pr-decoupler.c
> > b/drivers/fpga/xilinx-pr-decoupler.c
> > index 7d69af230567..c95f3d065ccb 100644
> > --- a/drivers/fpga/xilinx-pr-decoupler.c
> > +++ b/drivers/fpga/xilinx-pr-decoupler.c
> > @@ -19,10 +19,15 @@
> > #define CTRL_OFFSET0
> >
> > struct xlnx_pr_decoupler_data {
> > + const struct xlnx_config_data *ipconfig;
> > void __iomem *io_base;
> > struct clk *clk;
> > };
> >
> > +struct xlnx_config_data {
> > + char *name;
> > +};
> > +
> > static inline void xlnx_pr_decoupler_write(struct xlnx_pr_decoupler_data
> *d,
> >u32 offset, u32 val)
> > {
> > @@ -76,15 +81,28 @@ static const struct fpga_bridge_ops
> xlnx_pr_decoupler_br_ops = {
> > .enable_show = xlnx_pr_decoupler_enable_show, };
> >
> > +static const struct xlnx_config_data decoupler_config = {
> > + .name = "Xilinx PR Decoupler",
> > +};
> > +
> > +static const struct xlnx_config_data shutdown_config = {
> > + .name = "Xilinx DFX AXI shutdown mgr", };
>
> If it's just the strings, why not store them as is?
In order to differentiate the IP's at probe time we are using this name filed.
> > +
> > static const struct of_device_id xlnx_pr_decoupler_of_match[] = {
> > - { .compatible = "xlnx,pr-decoupler-1.00", },
> > - { .compatible = "xlnx,pr-decoupler", },
> > + { .compatible = "xlnx,pr-decoupler-1.00", .data = _config
> },
> > + { .compatible = "xlnx,pr-decoupler", .data = _config },
> > + { .compatible = "xlnx,dfx-axi-shutdown-manager-1.00",
> > + .data = _config },
> > + { .compatible = "xlnx,dfx-axi-shutdown-manager",
> > + .data = _config },
> > {},
> > };
> > MODULE_DEVICE_TABLE(of, xlnx_pr_decoupler_of_match);
> >
> > static int xlnx_pr_decoupler_probe(struct platform_device *pdev) {
> > + struct device_node *np = pdev->dev.of_node;
> > struct xlnx_pr_decoupler_data *priv;
> > struct fpga_bridge *br;
> > int err;
> > @@ -94,6 +112,14 @@ static int xlnx_pr_decoupler_probe(struct
> platform_device *pdev)
> > if (!priv)
> > return -ENOMEM;
> >
> > + if (np) {
> > + const struct of_device_id *match;
> > +
> > + match = of_match_node(xlnx_pr_decoupler_of_match, np);
> > + if (match && match->data)
> > + priv->ipconfig = match->data;
> > + }
> > +
> > res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > priv->io_base = devm_ioremap_resource(>dev, res);
> > if (IS_ERR(priv->io_base))
> > @@ -114,7 +140,7 @@ static int xlnx_pr_decoupler_probe(struct
> > plat
RE: [PATCH 2/2] fpga: Add support for Xilinx DFX AXI Shutdown manager
Hi Tom,
Thanks for the review.
Please find my response inline.
> -Original Message-
> From: Tom Rix
> Sent: Friday, January 15, 2021 11:56 PM
> To: Nava kishore Manne ; m...@kernel.org;
> robh...@kernel.org; Michal Simek ; linux-
> f...@vger.kernel.org; devicet...@vger.kernel.org; linux-arm-
> ker...@lists.infradead.org; linux-kernel@vger.kernel.org
> Cc: git ; chinnikishore...@gmail.com
> Subject: Re: [PATCH 2/2] fpga: Add support for Xilinx DFX AXI Shutdown
> manager
>
>
> On 1/14/21 5:34 PM, Nava kishore Manne wrote:
> > This patch adds support for Xilinx Dynamic Function eXchange(DFX) AXI
> > shutdown manager IP. It can be used to safely handling the AXI traffic
> > on a Reconfigurable Partition when it is undergoing dynamic
> > reconfiguration and there by preventing system deadlock that may occur
> > if AXI transactions are interrupted during reconfiguration.
> >
> > PR-Decoupler and AXI shutdown manager are completely different IPs.
> > But both the IP registers are compatible and also both belong to the
> > same sub-system (fpga-bridge).So using same driver for both IP's.
> >
> > Signed-off-by: Nava kishore Manne
> > ---
> > drivers/fpga/xilinx-pr-decoupler.c | 35
> > ++
>
> It looks like the copyright is wrong, please review spelling of Xilix
>
> Â * Copyright (c) 2017, Xilix Inc
>
Will fix in v2.
>
> > 1 file changed, 31 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/fpga/xilinx-pr-decoupler.c
> > b/drivers/fpga/xilinx-pr-decoupler.c
> > index 7d69af230567..c95f3d065ccb 100644
> > --- a/drivers/fpga/xilinx-pr-decoupler.c
> > +++ b/drivers/fpga/xilinx-pr-decoupler.c
> > @@ -19,10 +19,15 @@
> > #define CTRL_OFFSET0
> >
> > struct xlnx_pr_decoupler_data {
> > + const struct xlnx_config_data *ipconfig;
> > void __iomem *io_base;
> > struct clk *clk;
> > };
> >
> > +struct xlnx_config_data {
> > + char *name;
> > +};
>
> Move xlnx_config_data above xlnx_pr_decouple_data.
>
Will fix in v2.
> could you 'const' char *name ?
>
Will fix in v2.
> > +
> > static inline void xlnx_pr_decoupler_write(struct xlnx_pr_decoupler_data
> *d,
> >u32 offset, u32 val)
> > {
> > @@ -76,15 +81,28 @@ static const struct fpga_bridge_ops
> xlnx_pr_decoupler_br_ops = {
> > .enable_show = xlnx_pr_decoupler_enable_show, };
> >
> > +static const struct xlnx_config_data decoupler_config = {
> > + .name = "Xilinx PR Decoupler",
> > +};
> > +
> > +static const struct xlnx_config_data shutdown_config = {
> > + .name = "Xilinx DFX AXI shutdown mgr",
>
> To be consistent with decoupler name,
>
> shutdown mgr -> Shutdown Manager
>
Will fix in v2.
> > +};
> > +
> > static const struct of_device_id xlnx_pr_decoupler_of_match[] = {
> > - { .compatible = "xlnx,pr-decoupler-1.00", },
> > - { .compatible = "xlnx,pr-decoupler", },
> > + { .compatible = "xlnx,pr-decoupler-1.00", .data = _config
> },
> > + { .compatible = "xlnx,pr-decoupler", .data = _config },
> > + { .compatible = "xlnx,dfx-axi-shutdown-manager-1.00",
> > + .data = _config },
> > + { .compatible = "xlnx,dfx-axi-shutdown-manager",
> > + .data = _config },
> > {},
> > };
> > MODULE_DEVICE_TABLE(of, xlnx_pr_decoupler_of_match);
> >
> > static int xlnx_pr_decoupler_probe(struct platform_device *pdev) {
> > + struct device_node *np = pdev->dev.of_node;
> > struct xlnx_pr_decoupler_data *priv;
> > struct fpga_bridge *br;
> > int err;
> > @@ -94,6 +112,14 @@ static int xlnx_pr_decoupler_probe(struct
> platform_device *pdev)
> > if (!priv)
> > return -ENOMEM;
> >
> > + if (np) {
> > + const struct of_device_id *match;
> > +
> > + match = of_match_node(xlnx_pr_decoupler_of_match, np);
> > + if (match && match->data)
> > + priv->ipconfig = match->data;
> > + }
> > +
> > res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > priv->io_base = devm_ioremap_resource(>dev, res);
> > if (IS_ERR(priv->io_base))
> > @@ -114,7 +140,7 @@ static int xlnx_pr_decoupler_probe(struct
> > platform_device *pdev)
> >
> > clk_disable(priv->clk)
RE: [PATCH 1/2] dt-bindings: fpga: Add compatible value for Xilinx DFX AXI shutdown manger
Hi Tom, Thanks for the review. Please find my response inline. > -Original Message- > From: Tom Rix > Sent: Friday, January 15, 2021 11:37 PM > To: Nava kishore Manne ; m...@kernel.org; > robh...@kernel.org; Michal Simek ; linux- > f...@vger.kernel.org; devicet...@vger.kernel.org; linux-arm- > ker...@lists.infradead.org; linux-kernel@vger.kernel.org > Cc: git ; chinnikishore...@gmail.com > Subject: Re: [PATCH 1/2] dt-bindings: fpga: Add compatible value for Xilinx > DFX AXI shutdown manger > > > On 1/14/21 5:34 PM, Nava kishore Manne wrote: > > This patch Adds compatible value for Xilinx Dynamic Function > > eXchnage(DFX) AXI Shutdown manager IP. > > A multi patch set should have a cover letter. > > Use git format-patch --cover-letter > Will fix in v2. > > Signed-off-by: Nava kishore Manne > > --- > > .../bindings/fpga/xilinx-pr-decoupler.txt | 19 --- > > 1 file changed, 16 insertions(+), 3 deletions(-) > > > > diff --git > > a/Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt > > b/Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt > > index 4284d293fa61..42fca058a5f4 100644 > > --- a/Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt > > +++ b/Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt > > @@ -7,13 +7,26 @@ changes from passing through the bridge. The > > controller can also couple / enable the bridges which allows traffic > > to pass through the bridge normally. > Below is some wordsmithing to make the compatibility explicit and remove > unneeded words Will fix in v2 > > > > +Xilinx LogiCORE Dynamic Function eXchange(DFX) AXI shutdown manager > > +Softcore > is compatible with the Xilinx LogiCORE pr-decoupler. Yes, Both IP's are compatible with respect to the IP registers spec. > > + > > +The Xilinx LogiCORE Dynamic Function eXchange(DFX) AXI shutdown > > +manager manages one or more shutdown managers / fpga bridges. > > +The controller can shutdown/passthrough the bridges which prevents > > Delete 4 lines above. > Will fix in v2. > The DFX AXI shutdown manager prevents > Will fix in v2. > > +AXI traffic from passing through the bridge. The controller safely > > +handles AXI4MM and AXI4-Lite interfaces on a Reconfigurable Partition > > +when it is undergoing dynamic reconfiguration (DFX), preventing > > +system > > I don't know about the use of '(DFX)' here, above it is Dynamic Function > eXchange' > > Here it is dynamic reconfiguration, maybe just delete the '(DFX)' > Will fix in v2. > > +deadlock that can occur if AXI transactions are interrupted by DFX > > + > > The Driver supports only MMIO handling. A PR region can have multiple > > -PR Decouplers which can be handled independently or chained via > > decouple/ -decouple_status signals. > > +PR Decouplers/AXI shutdown manager which can be handled > independently > > +or chained via decouple/ decouple_status signals. > Being compatible, i don't think it is necessary to add to / change this > section. > > > > Required properties: > > - compatible : Should contain "xlnx,pr-decoupler-1.00" > > followed > by > > - "xlnx,pr-decoupler" > > + "xlnx,pr-decoupler" or > > + "xlnx,dfx-axi-shutdown-manager-1.00" followed by > > + "xlnx,dfx-axi-shutdown-manager" > > - regs : base address and size for decoupler module > > - clocks : input clock to IP > > - clock-names : should contain "aclk" > > Adding an example similar to the existing would be helpful. > Will fix in v2. Regards, Navakishore.
[PATCH 2/2] fpga: zynqmp: Adds secure BitStream loading support for Xilinx
This commit adds secure BitStream Loading support for the Xilinx
ZynqMp chip.
Signed-off-by: Nava kishore Manne
---
drivers/fpga/zynqmp-fpga.c | 8
include/linux/firmware/xlnx-zynqmp.h | 3 +++
2 files changed, 11 insertions(+)
diff --git a/drivers/fpga/zynqmp-fpga.c b/drivers/fpga/zynqmp-fpga.c
index 125743c9797f..0ce34553944b 100644
--- a/drivers/fpga/zynqmp-fpga.c
+++ b/drivers/fpga/zynqmp-fpga.c
@@ -56,6 +56,14 @@ static int zynqmp_fpga_ops_write(struct fpga_manager *mgr,
wmb(); /* ensure all writes are done before initiate FW call */
+ if (priv->flags & FPGA_MGR_ENCRYPTED_BITSTREAM)
+ eemi_flags |= XILINX_ZYNQMP_PM_FPGA_ENCRYPTION_DEVKEY;
+
+ if (priv->flags & FPGA_MGR_DDR_MEM_AUTH_BITSTREAM)
+ eemi_flags |= XILINX_ZYNQMP_PM_FPGA_AUTHENTICATION_DDR;
+ else if (priv->flags & FPGA_MGR_SECURE_MEM_AUTH_BITSTREAM)
+ eemi_flags |= XILINX_ZYNQMP_PM_FPGA_AUTHENTICATION_OCM;
+
if (priv->flags & FPGA_MGR_PARTIAL_RECONFIG)
eemi_flags |= XILINX_ZYNQMP_PM_FPGA_PARTIAL;
diff --git a/include/linux/firmware/xlnx-zynqmp.h
b/include/linux/firmware/xlnx-zynqmp.h
index 87114ee645b1..8a4038bf85e2 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -62,6 +62,9 @@
*/
#define XILINX_ZYNQMP_PM_FPGA_FULL 0x0U
#define XILINX_ZYNQMP_PM_FPGA_PARTIAL BIT(0)
+#define XILINX_ZYNQMP_PM_FPGA_AUTHENTICATION_DDR BIT(1)
+#define XILINX_ZYNQMP_PM_FPGA_AUTHENTICATION_OCM BIT(2)
+#define XILINX_ZYNQMP_PM_FPGA_ENCRYPTION_DEVKEYBIT(4)
enum pm_api_id {
PM_GET_API_VERSION = 1,
--
2.18.0
[PATCH 1/2] fpga: mgr: Adds secure BitStream loading support
This commit adds secure flags to the framework to support
secure BitStream Loading.
Signed-off-by: Nava kishore Manne
---
drivers/fpga/of-fpga-region.c | 10 ++
include/linux/fpga/fpga-mgr.h | 12
2 files changed, 22 insertions(+)
diff --git a/drivers/fpga/of-fpga-region.c b/drivers/fpga/of-fpga-region.c
index e405309baadc..3a5eb480 100644
--- a/drivers/fpga/of-fpga-region.c
+++ b/drivers/fpga/of-fpga-region.c
@@ -228,6 +228,16 @@ static struct fpga_image_info *of_fpga_region_parse_ov(
if (of_property_read_bool(overlay, "encrypted-fpga-config"))
info->flags |= FPGA_MGR_ENCRYPTED_BITSTREAM;
+ if (of_property_read_bool(overlay, "userkey-encrypted-fpga-config"))
+ info->flags |= FPGA_MGR_USERKEY_ENCRYPTED_BITSTREAM;
+
+ if (of_property_read_bool(overlay, "ddrmem-authenticated-fpga-config"))
+ info->flags |= FPGA_MGR_DDR_MEM_AUTH_BITSTREAM;
+
+ if (of_property_read_bool(overlay,
+ "securemem-authenticated-fpga-config"))
+ info->flags |= FPGA_MGR_SECURE_MEM_AUTH_BITSTREAM;
+
if (!of_property_read_string(overlay, "firmware-name",
_name)) {
info->firmware_name = devm_kstrdup(dev, firmware_name,
diff --git a/include/linux/fpga/fpga-mgr.h b/include/linux/fpga/fpga-mgr.h
index 2bc3030a69e5..2f7455a60666 100644
--- a/include/linux/fpga/fpga-mgr.h
+++ b/include/linux/fpga/fpga-mgr.h
@@ -67,12 +67,24 @@ enum fpga_mgr_states {
* %FPGA_MGR_BITSTREAM_LSB_FIRST: SPI bitstream bit order is LSB first
*
* %FPGA_MGR_COMPRESSED_BITSTREAM: FPGA bitstream is compressed
+ *
+ * %FPGA_MGR_USERKEY_ENCRYPTED_BITSTREAM: indicates bitstream is encrypted with
+ *user key
+ *
+ * %FPGA_MGR_DDR_MEM_AUTH_BITSTREAM: do bitstream authentication using DDR
+ * memory if supported
+ *
+ * %FPGA_MGR_SECURE_MEM_AUTH_BITSTREAM: do bitstream authentication using
secure
+ * memory if supported
*/
#define FPGA_MGR_PARTIAL_RECONFIG BIT(0)
#define FPGA_MGR_EXTERNAL_CONFIG BIT(1)
#define FPGA_MGR_ENCRYPTED_BITSTREAM BIT(2)
#define FPGA_MGR_BITSTREAM_LSB_FIRST BIT(3)
#define FPGA_MGR_COMPRESSED_BITSTREAM BIT(4)
+#define FPGA_MGR_USERKEY_ENCRYPTED_BITSTREAM BIT(5)
+#define FPGA_MGR_DDR_MEM_AUTH_BITSTREAMBIT(6)
+#define FPGA_MGR_SECURE_MEM_AUTH_BITSTREAM BIT(7)
/**
* struct fpga_image_info - information specific to a FPGA image
--
2.18.0
[PATCH 2/3] dt-bindings: fpga: Add binding doc for versal fpga manager
From: Appana Durga Kedareswara rao
This patch adds binding doc for versal fpga manager driver.
Signed-off-by: Nava kishore Manne
Signed-off-by: Appana Durga Kedareswara rao
---
.../bindings/fpga/xlnx,versal-fpga.yaml | 33 +++
1 file changed, 33 insertions(+)
create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml
diff --git a/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml
b/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml
new file mode 100644
index ..cf3aa7917488
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+
+$id: http://devicetree.org/schemas/fpga/xilinx/xlnx,versal-fpga.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx versal-fpga driver.
+
+maintainers:
+ - Nava kishore Manne
+
+description: |
+Device Tree versal-fpga bindings for the Versal SOC, Controlled
+using Versal SoC firmware interface.
+
+properties:
+ compatible:
+items:
+ - enum:
+- xlnx,versal-fpga
+
+required:
+ - compatible
+
+Required properties:
+- compatible: should contain "xlnx,versal-fpga"
+
+examples:
+ - |
+versal_fpga: fpga {
+ compatible = "xlnx,versal-fpga";
+};
--
2.18.0
[PATCH 1/3] drivers: firmware: Add Pdi load API support
This patch adds load pdi api support to enable pdi/partial loading from
linux. Programmable Device Image (PDI) is combination of headers, images
and bitstream files to be loaded. Partial PDI is partial set of image/
images to be loaded.
Signed-off-by: Nava kishore Manne
---
drivers/firmware/xilinx/zynqmp.c | 17 +
include/linux/firmware/xlnx-zynqmp.h | 9 +
2 files changed, 26 insertions(+)
diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
index 7eb9958662dd..a466225b9f9e 100644
--- a/drivers/firmware/xilinx/zynqmp.c
+++ b/drivers/firmware/xilinx/zynqmp.c
@@ -897,6 +897,23 @@ int zynqmp_pm_set_requirement(const u32 node, const u32
capabilities,
}
EXPORT_SYMBOL_GPL(zynqmp_pm_set_requirement);
+/**
+ * zynqmp_pm_load_pdi - Load and process pdi
+ * @src: Source device where PDI is located
+ * @address: Pdi src address
+ *
+ * This function provides support to load pdi from linux
+ *
+ * Return: Returns status, either success or error+reason
+ */
+int zynqmp_pm_load_pdi(const u32 src, const u64 address)
+{
+ return zynqmp_pm_invoke_fn(PM_LOAD_PDI, src,
+ lower_32_bits(address),
+ upper_32_bits(address), 0, NULL);
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_load_pdi);
+
/**
* zynqmp_pm_aes - Access AES hardware to encrypt/decrypt the data using
* AES-GCM core.
diff --git a/include/linux/firmware/xlnx-zynqmp.h
b/include/linux/firmware/xlnx-zynqmp.h
index 2a0da841c942..87114ee645b1 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -52,6 +52,9 @@
#defineZYNQMP_PM_CAPABILITY_WAKEUP 0x4U
#defineZYNQMP_PM_CAPABILITY_UNUSABLE 0x8U
+/* Loader commands */
+#define PM_LOAD_PDI0x701
+
/*
* Firmware FPGA Manager flags
* XILINX_ZYNQMP_PM_FPGA_FULL: FPGA full reconfiguration
@@ -354,6 +357,7 @@ int zynqmp_pm_write_pggs(u32 index, u32 value);
int zynqmp_pm_read_pggs(u32 index, u32 *value);
int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype);
int zynqmp_pm_set_boot_health_status(u32 value);
+int zynqmp_pm_load_pdi(const u32 src, const u64 address);
#else
static inline struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void)
{
@@ -538,6 +542,11 @@ static inline int zynqmp_pm_set_boot_health_status(u32
value)
{
return -ENODEV;
}
+
+static inline int zynqmp_pm_load_pdi(const u32 src, const u64 address)
+{
+ return -ENODEV;
+}
#endif
#endif /* __FIRMWARE_ZYNQMP_H__ */
--
2.18.0
[PATCH 3/3] fpga: versal-fpga: Add versal fpga manager driver
This patch adds driver for versal fpga manager.
PDI source type can be DDR, OCM, QSPI flash etc..
But driver allocates memory always from DDR, Since driver supports only
DDR source type.
Signed-off-by: Appana Durga Kedareswara rao
Signed-off-by: Nava kishore Manne
---
drivers/fpga/Kconfig | 8 ++
drivers/fpga/Makefile | 1 +
drivers/fpga/versal-fpga.c | 149 +
3 files changed, 158 insertions(+)
create mode 100644 drivers/fpga/versal-fpga.c
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index 5645226ca3ce..9f779c3a6739 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -216,4 +216,12 @@ config FPGA_MGR_ZYNQMP_FPGA
to configure the programmable logic(PL) through PS
on ZynqMP SoC.
+config FPGA_MGR_VERSAL_FPGA
+tristate "Xilinx Versal FPGA"
+depends on ARCH_ZYNQMP || COMPILE_TEST
+help
+ Select this option to enable FPGA manager driver support for
+ Xilinx Versal SOC. This driver uses the versal soc firmware
+ interface to load programmable logic(PL) images
+ on versal soc.
endif # FPGA
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index d8e21dfc6778..40c9adb6a644 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o
obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o
obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o
obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) += zynqmp-fpga.o
+obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA) += versal-fpga.o
obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o
obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT)+= altera-pr-ip-core-plat.o
diff --git a/drivers/fpga/versal-fpga.c b/drivers/fpga/versal-fpga.c
new file mode 100644
index ..2a42aa78b182
--- /dev/null
+++ b/drivers/fpga/versal-fpga.c
@@ -0,0 +1,149 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 Xilinx, Inc.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* Constant Definitions */
+#define PDI_SOURCE_TYPE0xF
+
+/**
+ * struct versal_fpga_priv - Private data structure
+ * @dev: Device data structure
+ * @flags: flags which is used to identify the PL Image type
+ */
+struct versal_fpga_priv {
+ struct device *dev;
+ u32 flags;
+};
+
+static int versal_fpga_ops_write_init(struct fpga_manager *mgr,
+ struct fpga_image_info *info,
+ const char *buf, size_t size)
+{
+ struct versal_fpga_priv *priv;
+
+ priv = mgr->priv;
+ priv->flags = info->flags;
+
+ return 0;
+}
+
+static int versal_fpga_ops_write(struct fpga_manager *mgr,
+const char *buf, size_t size)
+{
+ struct versal_fpga_priv *priv;
+ dma_addr_t dma_addr = 0;
+ char *kbuf;
+ int ret;
+
+ priv = mgr->priv;
+
+ kbuf = dma_alloc_coherent(priv->dev, size, _addr, GFP_KERNEL);
+ if (!kbuf)
+ return -ENOMEM;
+
+ memcpy(kbuf, buf, size);
+
+ wmb(); /* ensure all writes are done before initiate FW call */
+
+ ret = zynqmp_pm_load_pdi(PDI_SOURCE_TYPE, dma_addr);
+
+ dma_free_coherent(priv->dev, size, kbuf, dma_addr);
+
+ return ret;
+}
+
+static int versal_fpga_ops_write_complete(struct fpga_manager *mgr,
+ struct fpga_image_info *info)
+{
+ return 0;
+}
+
+static enum fpga_mgr_states versal_fpga_ops_state(struct fpga_manager *mgr)
+{
+ return FPGA_MGR_STATE_OPERATING;
+}
+
+static const struct fpga_manager_ops versal_fpga_ops = {
+ .state = versal_fpga_ops_state,
+ .write_init = versal_fpga_ops_write_init,
+ .write = versal_fpga_ops_write,
+ .write_complete = versal_fpga_ops_write_complete,
+};
+
+static int versal_fpga_probe(struct platform_device *pdev)
+{
+ struct device *dev = >dev;
+ struct versal_fpga_priv *priv;
+ struct fpga_manager *mgr;
+ int err, ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->dev = dev;
+ ret = dma_set_mask_and_coherent(>dev, DMA_BIT_MASK(32));
+ if (ret < 0) {
+ dev_err(dev, "no usable DMA configuration");
+ return ret;
+ }
+
+ mgr = devm_fpga_mgr_create(dev, "Xilinx Versal FPGA Manager",
+ _fpga_ops, priv);
+ if (!mgr)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, mgr);
+
+ err = fpga_mgr_register(mgr);
+ if (err) {
+ dev_err(dev, "unable to register FPGA manager");
+ fpga_mgr_free(mgr);
+ return err;
+ }
+
+ return 0;
+}
+
+static
[PATCH 2/2] fpga: Add support for Xilinx DFX AXI Shutdown manager
This patch adds support for Xilinx Dynamic Function eXchange(DFX) AXI
shutdown manager IP. It can be used to safely handling the AXI traffic
on a Reconfigurable Partition when it is undergoing dynamic reconfiguration
and there by preventing system deadlock that may occur if AXI transactions
are interrupted during reconfiguration.
PR-Decoupler and AXI shutdown manager are completely different IPs.
But both the IP registers are compatible and also both belong to the
same sub-system (fpga-bridge).So using same driver for both IP's.
Signed-off-by: Nava kishore Manne
---
drivers/fpga/xilinx-pr-decoupler.c | 35 ++
1 file changed, 31 insertions(+), 4 deletions(-)
diff --git a/drivers/fpga/xilinx-pr-decoupler.c
b/drivers/fpga/xilinx-pr-decoupler.c
index 7d69af230567..c95f3d065ccb 100644
--- a/drivers/fpga/xilinx-pr-decoupler.c
+++ b/drivers/fpga/xilinx-pr-decoupler.c
@@ -19,10 +19,15 @@
#define CTRL_OFFSET0
struct xlnx_pr_decoupler_data {
+ const struct xlnx_config_data *ipconfig;
void __iomem *io_base;
struct clk *clk;
};
+struct xlnx_config_data {
+ char *name;
+};
+
static inline void xlnx_pr_decoupler_write(struct xlnx_pr_decoupler_data *d,
u32 offset, u32 val)
{
@@ -76,15 +81,28 @@ static const struct fpga_bridge_ops
xlnx_pr_decoupler_br_ops = {
.enable_show = xlnx_pr_decoupler_enable_show,
};
+static const struct xlnx_config_data decoupler_config = {
+ .name = "Xilinx PR Decoupler",
+};
+
+static const struct xlnx_config_data shutdown_config = {
+ .name = "Xilinx DFX AXI shutdown mgr",
+};
+
static const struct of_device_id xlnx_pr_decoupler_of_match[] = {
- { .compatible = "xlnx,pr-decoupler-1.00", },
- { .compatible = "xlnx,pr-decoupler", },
+ { .compatible = "xlnx,pr-decoupler-1.00", .data = _config },
+ { .compatible = "xlnx,pr-decoupler", .data = _config },
+ { .compatible = "xlnx,dfx-axi-shutdown-manager-1.00",
+ .data = _config },
+ { .compatible = "xlnx,dfx-axi-shutdown-manager",
+ .data = _config },
{},
};
MODULE_DEVICE_TABLE(of, xlnx_pr_decoupler_of_match);
static int xlnx_pr_decoupler_probe(struct platform_device *pdev)
{
+ struct device_node *np = pdev->dev.of_node;
struct xlnx_pr_decoupler_data *priv;
struct fpga_bridge *br;
int err;
@@ -94,6 +112,14 @@ static int xlnx_pr_decoupler_probe(struct platform_device
*pdev)
if (!priv)
return -ENOMEM;
+ if (np) {
+ const struct of_device_id *match;
+
+ match = of_match_node(xlnx_pr_decoupler_of_match, np);
+ if (match && match->data)
+ priv->ipconfig = match->data;
+ }
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
priv->io_base = devm_ioremap_resource(>dev, res);
if (IS_ERR(priv->io_base))
@@ -114,7 +140,7 @@ static int xlnx_pr_decoupler_probe(struct platform_device
*pdev)
clk_disable(priv->clk);
- br = devm_fpga_bridge_create(>dev, "Xilinx PR Decoupler",
+ br = devm_fpga_bridge_create(>dev, priv->ipconfig->name,
_pr_decoupler_br_ops, priv);
if (!br) {
err = -ENOMEM;
@@ -125,7 +151,8 @@ static int xlnx_pr_decoupler_probe(struct platform_device
*pdev)
err = fpga_bridge_register(br);
if (err) {
- dev_err(>dev, "unable to register Xilinx PR Decoupler");
+ dev_err(>dev, "unable to register %s",
+ priv->ipconfig->name);
goto err_clk;
}
--
2.18.0
[PATCH 1/2] dt-bindings: fpga: Add compatible value for Xilinx DFX AXI shutdown manger
This patch Adds compatible value for Xilinx Dynamic Function eXchnage(DFX) AXI Shutdown manager IP. Signed-off-by: Nava kishore Manne --- .../bindings/fpga/xilinx-pr-decoupler.txt | 19 --- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt b/Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt index 4284d293fa61..42fca058a5f4 100644 --- a/Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt +++ b/Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt @@ -7,13 +7,26 @@ changes from passing through the bridge. The controller can also couple / enable the bridges which allows traffic to pass through the bridge normally. +Xilinx LogiCORE Dynamic Function eXchange(DFX) AXI shutdown manager +Softcore + +The Xilinx LogiCORE Dynamic Function eXchange(DFX) AXI shutdown manager +manages one or more shutdown managers / fpga bridges. +The controller can shutdown/passthrough the bridges which prevents +AXI traffic from passing through the bridge. The controller safely +handles AXI4MM and AXI4-Lite interfaces on a Reconfigurable Partition +when it is undergoing dynamic reconfiguration (DFX), preventing system +deadlock that can occur if AXI transactions are interrupted by DFX + The Driver supports only MMIO handling. A PR region can have multiple -PR Decouplers which can be handled independently or chained via decouple/ -decouple_status signals. +PR Decouplers/AXI shutdown manager which can be handled independently +or chained via decouple/ decouple_status signals. Required properties: - compatible : Should contain "xlnx,pr-decoupler-1.00" followed by - "xlnx,pr-decoupler" + "xlnx,pr-decoupler" or + "xlnx,dfx-axi-shutdown-manager-1.00" followed by + "xlnx,dfx-axi-shutdown-manager" - regs : base address and size for decoupler module - clocks : input clock to IP - clock-names : should contain "aclk" -- 2.18.0
RE: [PATCH 2/2] fpga: zynq: Add AFI config driver
Corrected typo
> -Original Message-
> From: Nava kishore Manne
> Sent: Monday, May 4, 2020 5:25 PM
> To: 'Moritz Fischer'
> Cc: Michal Simek ; linux-f...@vger.kernel.org; linux-arm-
> ker...@lists.infradead.org; linux-kernel@vger.kernel.org;
> chinnikishore...@gmail.com
> Subject: RE: [PATCH 2/2] fpga: zynq: Add AFI config driver
>
> Hi Moritz,
>
> Thanks for proving the comments.
> Please find my response inline.
>
> > -Original Message-
> > From: Moritz Fischer [mailto:m...@kernel.org]
> > Sent: Thursday, April 23, 2020 8:59 AM
> > To: Nava kishore Manne
> > Cc: m...@kernel.org; Michal Simek ; linux-
> > f...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; linux-
> > ker...@vger.kernel.org; chinnikishore...@gmail.com
> > Subject: Re: [PATCH 2/2] fpga: zynq: Add AFI config driver
> >
> > Hi Nava,
> >
> > On Wed, Apr 15, 2020 at 03:54:50PM +0530, Nava kishore Manne wrote:
> > > This patch Adds AFI config driver. This is useful for the PS to PL
> > > configuration for the fpga manager On zynq platform.
> > >
> > > Signed-off-by: Nava kishore Manne
> > > ---
> > > drivers/fpga/Kconfig| 8 +
> > > drivers/fpga/Makefile | 1 +
> > > drivers/fpga/zynq-afi.c | 81
> > > +
> > > 3 files changed, 90 insertions(+)
> > > create mode 100644 drivers/fpga/zynq-afi.c
> > >
> > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index
> > > 474f304e..60982a0 100644
> > > --- a/drivers/fpga/Kconfig
> > > +++ b/drivers/fpga/Kconfig
> > > @@ -214,4 +214,12 @@ config FPGA_MGR_ZYNQMP_FPGA
> > > to configure the programmable logic(PL) through PS
> > > on ZynqMP SoC.
> > >
> > > +config FPGA_MGR_ZYNQ_AFI_FPGA
> > > + bool "Xilinx AFI FPGA"
> > > + depends on FPGA_MGR_ZYNQ_FPGA
> > Curious. How does this dependency play in here?
> > > + help
> > > + Zynq AFI driver support for writing to the AFI registers
> > > + for configuring the PS_PL interface. For some of the bitstream
> > > + or designs to work the PS to PL interfaces need to be configured
> > > + like the data bus-width etc.
> > > endif # FPGA
> > > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index
> > > 312b937..d115e29 100644
> > > --- a/drivers/fpga/Makefile
> > > +++ b/drivers/fpga/Makefile
> > > @@ -26,6 +26,7 @@ obj-$(CONFIG_FPGA_BRIDGE) += fpga-
> > bridge.o
> > > obj-$(CONFIG_SOCFPGA_FPGA_BRIDGE)+= altera-hps2fpga.o altera-
> > fpga2sdram.o
> > > obj-$(CONFIG_ALTERA_FREEZE_BRIDGE) += altera-freeze-bridge.o
> > > obj-$(CONFIG_XILINX_PR_DECOUPLER)+= xilinx-pr-decoupler.o
> > > +obj-$(CONFIG_FPGA_MGR_ZYNQ_AFI_FPGA) += zynq-afi.o
> > >
> > > # High Level Interfaces
> > > obj-$(CONFIG_FPGA_REGION)+= fpga-region.o
> > > diff --git a/drivers/fpga/zynq-afi.c b/drivers/fpga/zynq-afi.c new
> > > file mode 100644 index 000..7ce0d08
> > > --- /dev/null
> > > +++ b/drivers/fpga/zynq-afi.c
> > > @@ -0,0 +1,81 @@
> > > +// SPDX-License-Identifier: GPL-2.0
> > > +/*
> > > + * Xilinx FPGA AFI driver.
> > > + * Copyright (c) 2018 Xilinx Inc.
> > > + */
> > > +
> > > +#include
> > > +#include
> > > +#include
> > > +#include
> > > +#include
> > > +
> > > +/* Registers and special values for doing register-based operations */
> > > +#define AFI_RDCHAN_CTRL_OFFSET 0x00
> > > +#define AFI_WRCHAN_CTRL_OFFSET 0x14
> > > +
> > > +#define AFI_BUSWIDTH_MASK0x01
> > > +
> > > +/**
> > > + * struct afi_fpga - AFI register description
> > > + * @membase: pointer to register struct
> > > + * @afi_width: AFI bus width to be written
> > > + */
> > > +struct zynq_afi_fpga {
> > > + void __iomem*membase;
> > > + u32 afi_width;
> > > +};
> > > +
> > > +static int zynq_afi_fpga_probe(struct platform_device *pdev) {
> > > + struct zynq_afi_fpga *afi_fpga;
> > > + struct resource *res;
> > > + u32 reg_val;
> > > + u32 val;
> > > +
> > > + afi_fpga = devm_kzalloc(>dev, sizeof(*afi_fpga), GFP_KERNEL);
> > > + if (!afi_fpga)
> > > + return -ENOMEM;
> > > +
&g
RE: [PATCH 2/2] fpga: zynq: Add AFI config driver
Hi Mortiz,
Thanks for proving the comments.
Please find my response inline.
> -Original Message-
> From: Moritz Fischer [mailto:m...@kernel.org]
> Sent: Thursday, April 23, 2020 8:59 AM
> To: Nava kishore Manne
> Cc: m...@kernel.org; Michal Simek ; linux-
> f...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; linux-
> ker...@vger.kernel.org; chinnikishore...@gmail.com
> Subject: Re: [PATCH 2/2] fpga: zynq: Add AFI config driver
>
> Hi Nava,
>
> On Wed, Apr 15, 2020 at 03:54:50PM +0530, Nava kishore Manne wrote:
> > This patch Adds AFI config driver. This is useful for the PS to PL
> > configuration for the fpga manager On zynq platform.
> >
> > Signed-off-by: Nava kishore Manne
> > ---
> > drivers/fpga/Kconfig| 8 +
> > drivers/fpga/Makefile | 1 +
> > drivers/fpga/zynq-afi.c | 81
> > +
> > 3 files changed, 90 insertions(+)
> > create mode 100644 drivers/fpga/zynq-afi.c
> >
> > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index
> > 474f304e..60982a0 100644
> > --- a/drivers/fpga/Kconfig
> > +++ b/drivers/fpga/Kconfig
> > @@ -214,4 +214,12 @@ config FPGA_MGR_ZYNQMP_FPGA
> > to configure the programmable logic(PL) through PS
> > on ZynqMP SoC.
> >
> > +config FPGA_MGR_ZYNQ_AFI_FPGA
> > + bool "Xilinx AFI FPGA"
> > + depends on FPGA_MGR_ZYNQ_FPGA
> Curious. How does this dependency play in here?
> > + help
> > + Zynq AFI driver support for writing to the AFI registers
> > + for configuring the PS_PL interface. For some of the bitstream
> > + or designs to work the PS to PL interfaces need to be configured
> > + like the data bus-width etc.
> > endif # FPGA
> > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index
> > 312b937..d115e29 100644
> > --- a/drivers/fpga/Makefile
> > +++ b/drivers/fpga/Makefile
> > @@ -26,6 +26,7 @@ obj-$(CONFIG_FPGA_BRIDGE) += fpga-
> bridge.o
> > obj-$(CONFIG_SOCFPGA_FPGA_BRIDGE) += altera-hps2fpga.o altera-
> fpga2sdram.o
> > obj-$(CONFIG_ALTERA_FREEZE_BRIDGE) += altera-freeze-bridge.o
> > obj-$(CONFIG_XILINX_PR_DECOUPLER) += xilinx-pr-decoupler.o
> > +obj-$(CONFIG_FPGA_MGR_ZYNQ_AFI_FPGA) += zynq-afi.o
> >
> > # High Level Interfaces
> > obj-$(CONFIG_FPGA_REGION) += fpga-region.o
> > diff --git a/drivers/fpga/zynq-afi.c b/drivers/fpga/zynq-afi.c new
> > file mode 100644 index 000..7ce0d08
> > --- /dev/null
> > +++ b/drivers/fpga/zynq-afi.c
> > @@ -0,0 +1,81 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Xilinx FPGA AFI driver.
> > + * Copyright (c) 2018 Xilinx Inc.
> > + */
> > +
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +
> > +/* Registers and special values for doing register-based operations */
> > +#define AFI_RDCHAN_CTRL_OFFSET 0x00
> > +#define AFI_WRCHAN_CTRL_OFFSET 0x14
> > +
> > +#define AFI_BUSWIDTH_MASK 0x01
> > +
> > +/**
> > + * struct afi_fpga - AFI register description
> > + * @membase: pointer to register struct
> > + * @afi_width: AFI bus width to be written
> > + */
> > +struct zynq_afi_fpga {
> > + void __iomem*membase;
> > + u32 afi_width;
> > +};
> > +
> > +static int zynq_afi_fpga_probe(struct platform_device *pdev) {
> > + struct zynq_afi_fpga *afi_fpga;
> > + struct resource *res;
> > + u32 reg_val;
> > + u32 val;
> > +
> > + afi_fpga = devm_kzalloc(>dev, sizeof(*afi_fpga), GFP_KERNEL);
> > + if (!afi_fpga)
> > + return -ENOMEM;
> > +
> > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > + afi_fpga->membase = devm_ioremap_resource(>dev, res);
> > + if (IS_ERR(afi_fpga->membase))
> > + return PTR_ERR(afi_fpga->membase);
> > +
> > + val = device_property_read_u32(>dev, "xlnx,afi-width",
> > + _fpga->afi_width);
> > + if (val) {
> > + dev_err(>dev, "Fail to get the afi bus width\n");
> > + return -EINVAL;
> > + }
> > +
> > + reg_val = readl(afi_fpga->membase + AFI_RDCHAN_CTRL_OFFSET);
> > + reg_val &= ~AFI_BUSWIDTH_MASK;
> > + writel(reg_val | afi_fpga->afi_width,
> > + afi_fpga->membase + AFI_RDCHAN_CTRL_OFFSET);
> > + reg_val = readl(afi_fpga->membase + AFI_W
[PATCH v5 3/3] fpga manager: Adding FPGA Manager support for Xilinx zynqmp
This patch adds FPGA Manager support for the Xilinx
ZynqMP chip.
Signed-off-by: Nava kishore Manne
Reviewed-by: Moritz Fischer
Acked-by: Alan Tull
---
Changes for v5:
-Removed hardcoded macro values and used BIT(x)
as suggested by Moritz.
drivers/fpga/Kconfig | 9 +++
drivers/fpga/Makefile | 1 +
drivers/fpga/zynqmp-fpga.c | 159 +
3 files changed, 169 insertions(+)
create mode 100644 drivers/fpga/zynqmp-fpga.c
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index c20445b867ae..d892f3efcd76 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -204,4 +204,13 @@ config FPGA_DFL_PCI
To compile this as a module, choose M here.
+config FPGA_MGR_ZYNQMP_FPGA
+ tristate "Xilinx ZynqMP FPGA"
+ depends on ARCH_ZYNQMP || COMPILE_TEST
+ help
+ FPGA manager driver support for Xilinx ZynqMP FPGAs.
+ This driver uses the processor configuration port(PCAP)
+ to configure the programmable logic(PL) through PS
+ on ZynqMP SoC.
+
endif # FPGA
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index c0dd4c82fbdb..312b9371742f 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_FPGA_MGR_STRATIX10_SOC) += stratix10-soc.o
obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o
obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o
obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o
+obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) += zynqmp-fpga.o
obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o
obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT)+= altera-pr-ip-core-plat.o
diff --git a/drivers/fpga/zynqmp-fpga.c b/drivers/fpga/zynqmp-fpga.c
new file mode 100644
index ..f7cbaadf49ab
--- /dev/null
+++ b/drivers/fpga/zynqmp-fpga.c
@@ -0,0 +1,159 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Xilinx, Inc.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* Constant Definitions */
+#define IXR_FPGA_DONE_MASK BIT(3)
+
+/**
+ * struct zynqmp_fpga_priv - Private data structure
+ * @dev: Device data structure
+ * @flags: flags which is used to identify the bitfile type
+ */
+struct zynqmp_fpga_priv {
+ struct device *dev;
+ u32 flags;
+};
+
+static int zynqmp_fpga_ops_write_init(struct fpga_manager *mgr,
+ struct fpga_image_info *info,
+ const char *buf, size_t size)
+{
+ struct zynqmp_fpga_priv *priv;
+
+ priv = mgr->priv;
+ priv->flags = info->flags;
+
+ return 0;
+}
+
+static int zynqmp_fpga_ops_write(struct fpga_manager *mgr,
+const char *buf, size_t size)
+{
+ const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
+ struct zynqmp_fpga_priv *priv;
+ dma_addr_t dma_addr;
+ u32 eemi_flags = 0;
+ char *kbuf;
+ int ret;
+
+ if (!eemi_ops || !eemi_ops->fpga_load)
+ return -ENXIO;
+
+ priv = mgr->priv;
+
+ kbuf = dma_alloc_coherent(priv->dev, size, _addr, GFP_KERNEL);
+ if (!kbuf)
+ return -ENOMEM;
+
+ memcpy(kbuf, buf, size);
+
+ wmb(); /* ensure all writes are done before initiate FW call */
+
+ if (priv->flags & FPGA_MGR_PARTIAL_RECONFIG)
+ eemi_flags |= XILINX_ZYNQMP_PM_FPGA_PARTIAL;
+
+ ret = eemi_ops->fpga_load(dma_addr, size, eemi_flags);
+
+ dma_free_coherent(priv->dev, size, kbuf, dma_addr);
+
+ return ret;
+}
+
+static int zynqmp_fpga_ops_write_complete(struct fpga_manager *mgr,
+ struct fpga_image_info *info)
+{
+ return 0;
+}
+
+static enum fpga_mgr_states zynqmp_fpga_ops_state(struct fpga_manager *mgr)
+{
+ const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
+ u32 status;
+
+ if (!eemi_ops || !eemi_ops->fpga_get_status)
+ return FPGA_MGR_STATE_UNKNOWN;
+
+ eemi_ops->fpga_get_status();
+ if (status & IXR_FPGA_DONE_MASK)
+ return FPGA_MGR_STATE_OPERATING;
+
+ return FPGA_MGR_STATE_UNKNOWN;
+}
+
+static const struct fpga_manager_ops zynqmp_fpga_ops = {
+ .state = zynqmp_fpga_ops_state,
+ .write_init = zynqmp_fpga_ops_write_init,
+ .write = zynqmp_fpga_ops_write,
+ .write_complete = zynqmp_fpga_ops_write_complete,
+};
+
+static int zynqmp_fpga_probe(struct platform_device *pdev)
+{
+ struct device *dev = >dev;
+ struct zynqmp_fpga_priv *priv;
+ struct fpga_manager *mgr;
+ int ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->dev = dev;
+
+ mgr = devm_fpga_mgr_create(dev, "Xilinx ZynqMP FPG
[PATCH v5 1/3] firmware: xilinx: Add fpga API's
This Patch Adds fpga API's to support the Bitstream loading
by using firmware interface.
Signed-off-by: Nava kishore Manne
Reviewed-by: Moritz Fischer
---
Changes for v5:
-Modified API's doc as suggested by Moritz.
drivers/firmware/xilinx/zynqmp.c | 45
include/linux/firmware/xlnx-zynqmp.h | 12
2 files changed, 57 insertions(+)
diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
index 98f936125643..f355ad42917c 100644
--- a/drivers/firmware/xilinx/zynqmp.c
+++ b/drivers/firmware/xilinx/zynqmp.c
@@ -537,6 +537,49 @@ static int zynqmp_pm_reset_get_status(const enum
zynqmp_pm_reset reset,
return ret;
}
+/*
+ * zynqmp_pm_fpga_load - Perform the fpga load
+ * @address: Address to write to
+ * @size: pl bitstream size
+ * @flags: Bitstream type
+ * -XILINX_ZYNQMP_PM_FPGA_FULL: FPGA full reconfiguration
+ * -XILINX_ZYNQMP_PM_FPGA_PARTIAL: FPGA partial reconfiguration
+ *
+ * This function provides access to pmufw. To transfer
+ * the required bitstream into PL.
+ *
+ * Return: Returns status, either success or error+reason
+ */
+static int zynqmp_pm_fpga_load(const u64 address, const u32 size,
+ const u32 flags)
+{
+ return zynqmp_pm_invoke_fn(PM_FPGA_LOAD, lower_32_bits(address),
+ upper_32_bits(address), size, flags, NULL);
+}
+
+/**
+ * zynqmp_pm_fpga_get_status - Read value from PCAP status register
+ * @value: Value to read
+ *
+ * This function provides access to the pmufw to get the PCAP
+ * status
+ *
+ * Return: Returns status, either success or error+reason
+ */
+static int zynqmp_pm_fpga_get_status(u32 *value)
+{
+ u32 ret_payload[PAYLOAD_ARG_CNT];
+ int ret;
+
+ if (!value)
+ return -EINVAL;
+
+ ret = zynqmp_pm_invoke_fn(PM_FPGA_GET_STATUS, 0, 0, 0, 0, ret_payload);
+ *value = ret_payload[1];
+
+ return ret;
+}
+
/**
* zynqmp_pm_init_finalize() - PM call to inform firmware that the caller
*master has initialized its own power management
@@ -640,6 +683,8 @@ static const struct zynqmp_eemi_ops eemi_ops = {
.request_node = zynqmp_pm_request_node,
.release_node = zynqmp_pm_release_node,
.set_requirement = zynqmp_pm_set_requirement,
+ .fpga_load = zynqmp_pm_fpga_load,
+ .fpga_get_status = zynqmp_pm_fpga_get_status,
};
/**
diff --git a/include/linux/firmware/xlnx-zynqmp.h
b/include/linux/firmware/xlnx-zynqmp.h
index 642dab10f65d..1b1de5539036 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -48,6 +48,14 @@
#defineZYNQMP_PM_CAPABILITY_WAKEUP 0x4U
#defineZYNQMP_PM_CAPABILITY_POWER 0x8U
+/*
+ * Firmware FPGA Manager flags
+ * XILINX_ZYNQMP_PM_FPGA_FULL: FPGA full reconfiguration
+ * XILINX_ZYNQMP_PM_FPGA_PARTIAL: FPGA partial reconfiguration
+ */
+#define XILINX_ZYNQMP_PM_FPGA_FULL 0x0U
+#define XILINX_ZYNQMP_PM_FPGA_PARTIAL BIT(0)
+
enum pm_api_id {
PM_GET_API_VERSION = 1,
PM_REQUEST_NODE = 13,
@@ -56,6 +64,8 @@ enum pm_api_id {
PM_RESET_ASSERT = 17,
PM_RESET_GET_STATUS,
PM_PM_INIT_FINALIZE = 21,
+ PM_FPGA_LOAD,
+ PM_FPGA_GET_STATUS,
PM_GET_CHIPID = 24,
PM_IOCTL = 34,
PM_QUERY_DATA,
@@ -258,6 +268,8 @@ struct zynqmp_pm_query_data {
struct zynqmp_eemi_ops {
int (*get_api_version)(u32 *version);
int (*get_chipid)(u32 *idcode, u32 *version);
+ int (*fpga_load)(const u64 address, const u32 size, const u32 flags);
+ int (*fpga_get_status)(u32 *value);
int (*query_data)(struct zynqmp_pm_query_data qdata, u32 *out);
int (*clock_enable)(u32 clock_id);
int (*clock_disable)(u32 clock_id);
--
2.18.0
[PATCH v5 2/3] dt-bindings: fpga: Add bindings for ZynqMP fpga driver
Add documentation to describe Xilinx ZynqMP fpga driver
bindings.
Signed-off-by: Nava kishore Manne
Reviewed-by: Rob Herring
Acked-by: Alan Tull
Acked-by: Moritz Fischer
---
Changes for v5:
-None.
.../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt | 25 +++
1 file changed, 25 insertions(+)
create mode 100644
Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
diff --git a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
new file mode 100644
index ..3052bf619dd5
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
@@ -0,0 +1,25 @@
+Devicetree bindings for Zynq Ultrascale MPSoC FPGA Manager.
+The ZynqMP SoC uses the PCAP (Processor configuration Port) to configure the
+Programmable Logic (PL). The configuration uses the firmware interface.
+
+Required properties:
+- compatible: should contain "xlnx,zynqmp-pcap-fpga"
+
+Example for full FPGA configuration:
+
+ fpga-region0 {
+ compatible = "fpga-region";
+ fpga-mgr = <_pcap>;
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ };
+
+ firmware {
+ zynqmp_firmware: zynqmp-firmware {
+ compatible = "xlnx,zynqmp-firmware";
+ method = "smc";
+ zynqmp_pcap: pcap {
+ compatible = "xlnx,zynqmp-pcap-fpga";
+ };
+ };
+ };
--
2.18.0
[PATCH v5 0/3]Add Bitstream configuration support for ZynqMP
Nava kishore Manne (3): firmware: xilinx: Add fpga API's dt-bindings: fpga: Add bindings for ZynqMP fpga driver fpga manager: Adding FPGA Manager support for Xilinx zynqmp .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt | 25 +++ drivers/firmware/xilinx/zynqmp.c | 45 + drivers/fpga/Kconfig | 9 + drivers/fpga/Makefile | 1 + drivers/fpga/zynqmp-fpga.c| 159 ++ include/linux/firmware/xlnx-zynqmp.h | 12 ++ 6 files changed, 251 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt create mode 100644 drivers/fpga/zynqmp-fpga.c -- 2.18.0
RE: [PATCH v4 1/3] firmware: xilinx: Add fpga API's
Hi Moritz,
Thanks for the quick response.
Please find my response inline
> -Original Message-
> From: Michal Simek [mailto:michal.si...@xilinx.com]
> Sent: Tuesday, April 9, 2019 12:04 PM
> To: Moritz Fischer ; Nava kishore Manne
>
> Cc: at...@kernel.org; robh...@kernel.org; mark.rutl...@arm.com; Michal
> Simek ; Rajan Vaja ; Jolly Shah
> ; linux-f...@vger.kernel.org; devicet...@vger.kernel.org;
> linux-arm-ker...@lists.infradead.org; linux-kernel@vger.kernel.org;
> chinnikishore...@gmail.com
> Subject: Re: [PATCH v4 1/3] firmware: xilinx: Add fpga API's
>
> On 08. 04. 19 19:14, Moritz Fischer wrote:
> > Hi Nava,
> >
> > On Tue, Apr 02, 2019 at 06:01:21PM +0530, Nava kishore Manne wrote:
> >> This Patch Adds fpga API's to support the Bitstream loading by using
> >> firmware interface.
> >>
> >> Signed-off-by: Nava kishore Manne
> >> ---
> >> Changes for v4:
> >>-None.
> >>
> >> Chnages for v3:
> >>-Created patches on top of 5.0-rc5.
> >> No functional changes.
> >>
> >> Changes for v2:
> >>-Added Firmware FPGA Manager flags As suggested by
> >> Moritz.
> >>
> >> Changes for v1:
> >>-None.
> >>
> >> Changes for RFC-V2:
> >>-New Patch
> >>
> >> drivers/firmware/xilinx/zynqmp.c | 46
> >> include/linux/firmware/xlnx-zynqmp.h | 10 ++
> >> 2 files changed, 56 insertions(+)
> >>
> >> diff --git a/drivers/firmware/xilinx/zynqmp.c
> >> b/drivers/firmware/xilinx/zynqmp.c
> >> index 98f936125643..7159a90abc44 100644
> >> --- a/drivers/firmware/xilinx/zynqmp.c
> >> +++ b/drivers/firmware/xilinx/zynqmp.c
> >> @@ -537,6 +537,50 @@ static int zynqmp_pm_reset_get_status(const enum
> zynqmp_pm_reset reset,
> >>return ret;
> >> }
> >>
> >> +/*
> >> + * zynqmp_pm_fpga_load - Perform the fpga load
> >> + * @address: Address to write to
> >> + * @size: pl bitstream size
> >> + * @flags:
> >> + *BIT(0) - Bit-stream type.
> >> + * 0 - Full Bitstream.
> >> + * 1 - Partial Bitstream.
> >> + *
> >> + * This function provides access to pmufw. To transfer
> >> + * the required bitstream into PL.
> >> + *
> >> + * Return: Returns status, either success or error+reason */ static
> >> +int zynqmp_pm_fpga_load(const u64 address, const u32 size,
> >> + const u32 flags)
> >> +{
> >> + return zynqmp_pm_invoke_fn(PM_FPGA_LOAD, lower_32_bits(address),
> >> + upper_32_bits(address), size, flags, NULL); }
> >> +
> >> +/**
> >> + * zynqmp_pm_fpga_get_status - Read value from PCAP status register
> >> + * @value: Value to read
> >> + *
> >> + * This function provides access to the xilfpga library to get
> >
> > xilfpga? Is that PMU firmware you're talking about?
Xilfpga is a library and it’s a part of PMUFW BSP.
It will follow the below flow to configure the PL from Linux environment.
Linux -Fpga Manager framework <--> Linux-Firmware Driver <- -smc call-->ATF
<--IPI call--> PMUFW<--> Xilfpga library.
> >
> >> + * the PCAP status
> >> + *
> >> + * Return: Returns status, either success or error+reason */ static
> >> +int zynqmp_pm_fpga_get_status(u32 *value) {
> >> + u32 ret_payload[PAYLOAD_ARG_CNT];
> >> + int ret;
> >> +
> >> + if (!value)
> >> + return -EINVAL;
> >> +
> >> + ret = zynqmp_pm_invoke_fn(PM_FPGA_GET_STATUS, 0, 0, 0, 0,
> ret_payload);
> >> + *value = ret_payload[1];
> >> +
> >> + return ret;
> >> +}
> >> +
> >> /**
> >> * zynqmp_pm_init_finalize() - PM call to inform firmware that the caller
> >> * master has initialized its own power
> >> management
> >> @@ -640,6 +684,8 @@ static const struct zynqmp_eemi_ops eemi_ops = {
> >>.request_node = zynqmp_pm_request_node,
> >>.release_node = zynqmp_pm_release_node,
> >>.set_requirement = zynqmp_pm_set_requirement,
> >> + .fpga_load = zynqmp_pm_fpga_load,
> >> + .fpga_get_status = zynqmp_pm_fpga_get_status,
> >> };
> >>
> >> /**
> >> diff --git a/include/linux/firmware/xlnx-zynqmp.h
> >
RE: [PATCH v4 3/3] fpga manager: Adding FPGA Manager support for Xilinx zynqmp
Hi Alan, Thanks for the response. Please find my response inline. > -Original Message- > From: Alan Tull [mailto:at...@kernel.org] > Sent: Tuesday, April 9, 2019 1:57 AM > To: Moritz Fischer > Cc: Michal Simek ; Nava kishore Manne > ; Rob Herring ; Mark Rutland > ; Rajan Vaja ; Jolly Shah > ; linux-f...@vger.kernel.org; open list:OPEN FIRMWARE > AND FLATTENED DEVICE TREE BINDINGS ; > moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE ker...@lists.infradead.org>; linux-kernel ; > kishore m > Subject: Re: [PATCH v4 3/3] fpga manager: Adding FPGA Manager support for > Xilinx zynqmp > > On Mon, Apr 8, 2019 at 11:51 AM Moritz Fischer wrote: > > > > Hi Michal, > > > > On Mon, Apr 08, 2019 at 04:36:15PM +0200, Michal Simek wrote: > > > On 08. 04. 19 16:17, Alan Tull wrote: > > > > On Mon, Apr 8, 2019 at 7:39 AM Nava kishore Manne > wrote: > > > >> > > > >> Hi Alan, > > > >> > > > >> Thanks for look into it and providing the ACK. > > > >> I got one minor comments from Moritz Fischer do you want me fix that > issue now or I can fix it later as it’s a minor comment? > > > > > > > > Please fix for Moritz comment. Will fix in the next version. Regards, Navakishore.
RE: [PATCH v4 3/3] fpga manager: Adding FPGA Manager support for Xilinx zynqmp
Hi Alan, Thanks for look into it and providing the ACK. I got one minor comments from Moritz Fischer do you want me fix that issue now or I can fix it later as it’s a minor comment? In which kernel version i can expect this driver changes?? Regards, Navakishore. > -Original Message- > From: Alan Tull [mailto:at...@kernel.org] > Sent: Tuesday, April 2, 2019 11:57 PM > To: Nava kishore Manne > Cc: Moritz Fischer ; Rob Herring ; Mark > Rutland ; Michal Simek ; Rajan > Vaja ; Jolly Shah ; linux- > f...@vger.kernel.org; open list:OPEN FIRMWARE AND FLATTENED DEVICE > TREE BINDINGS ; moderated list:ARM/FREESCALE > IMX / MXC ARM ARCHITECTURE ; linux- > kernel ; kishore m > > Subject: Re: [PATCH v4 3/3] fpga manager: Adding FPGA Manager support for > Xilinx zynqmp > > On Tue, Apr 2, 2019 at 7:32 AM Nava kishore Manne > wrote: > > Hi Nava, > > Looks good. > > > > > This patch adds FPGA Manager support for the Xilinx ZynqMP chip. > > > > Signed-off-by: Nava kishore Manne > Acked-by: Alan Tull > > > --- > > Changes for v4: > > -Updated the Fpga Mgr registrations call's > > to 5.0 > > -Removed dma_set_mask_and_coherent() As the FW > > supports only 32-bit address operations. > > > > Changes for v3: > > -Created patches on top of 5.0-rc5. > > No functional changes. > > > > Changes for v2: > > -Fixed some minor coding issues as suggested by > > Moritz > > > > Changes for v1: > > -None. > > > > Changes for RFC-V2: > > -Updated the Fpga Mgr registrations call's > > to 4.18 > > Thanks, > Alan
[PATCH v4 3/3] fpga manager: Adding FPGA Manager support for Xilinx zynqmp
This patch adds FPGA Manager support for the Xilinx
ZynqMP chip.
Signed-off-by: Nava kishore Manne
---
Changes for v4:
-Updated the Fpga Mgr registrations call's
to 5.0
-Removed dma_set_mask_and_coherent() As the FW
supports only 32-bit address operations.
Changes for v3:
-Created patches on top of 5.0-rc5.
No functional changes.
Changes for v2:
-Fixed some minor coding issues as suggested by
Moritz
Changes for v1:
-None.
Changes for RFC-V2:
-Updated the Fpga Mgr registrations call's
to 4.18
drivers/fpga/Kconfig | 9 +++
drivers/fpga/Makefile | 1 +
drivers/fpga/zynqmp-fpga.c | 159 +
3 files changed, 169 insertions(+)
create mode 100644 drivers/fpga/zynqmp-fpga.c
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index c20445b867ae..d892f3efcd76 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -204,4 +204,13 @@ config FPGA_DFL_PCI
To compile this as a module, choose M here.
+config FPGA_MGR_ZYNQMP_FPGA
+ tristate "Xilinx ZynqMP FPGA"
+ depends on ARCH_ZYNQMP || COMPILE_TEST
+ help
+ FPGA manager driver support for Xilinx ZynqMP FPGAs.
+ This driver uses the processor configuration port(PCAP)
+ to configure the programmable logic(PL) through PS
+ on ZynqMP SoC.
+
endif # FPGA
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index c0dd4c82fbdb..312b9371742f 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_FPGA_MGR_STRATIX10_SOC) += stratix10-soc.o
obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o
obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o
obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o
+obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) += zynqmp-fpga.o
obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o
obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT)+= altera-pr-ip-core-plat.o
diff --git a/drivers/fpga/zynqmp-fpga.c b/drivers/fpga/zynqmp-fpga.c
new file mode 100644
index ..f6e35fe95adb
--- /dev/null
+++ b/drivers/fpga/zynqmp-fpga.c
@@ -0,0 +1,159 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Xilinx, Inc.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* Constant Definitions */
+#define IXR_FPGA_DONE_MASK 0X0008U
+
+/**
+ * struct zynqmp_fpga_priv - Private data structure
+ * @dev: Device data structure
+ * @flags: flags which is used to identify the bitfile type
+ */
+struct zynqmp_fpga_priv {
+ struct device *dev;
+ u32 flags;
+};
+
+static int zynqmp_fpga_ops_write_init(struct fpga_manager *mgr,
+ struct fpga_image_info *info,
+ const char *buf, size_t size)
+{
+ struct zynqmp_fpga_priv *priv;
+
+ priv = mgr->priv;
+ priv->flags = info->flags;
+
+ return 0;
+}
+
+static int zynqmp_fpga_ops_write(struct fpga_manager *mgr,
+const char *buf, size_t size)
+{
+ const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
+ struct zynqmp_fpga_priv *priv;
+ dma_addr_t dma_addr;
+ u32 eemi_flags = 0;
+ char *kbuf;
+ int ret;
+
+ if (!eemi_ops || !eemi_ops->fpga_load)
+ return -ENXIO;
+
+ priv = mgr->priv;
+
+ kbuf = dma_alloc_coherent(priv->dev, size, _addr, GFP_KERNEL);
+ if (!kbuf)
+ return -ENOMEM;
+
+ memcpy(kbuf, buf, size);
+
+ wmb(); /* ensure all writes are done before initiate FW call */
+
+ if (priv->flags & FPGA_MGR_PARTIAL_RECONFIG)
+ eemi_flags |= XILINX_ZYNQMP_PM_FPGA_PARTIAL;
+
+ ret = eemi_ops->fpga_load(dma_addr, size, eemi_flags);
+
+ dma_free_coherent(priv->dev, size, kbuf, dma_addr);
+
+ return ret;
+}
+
+static int zynqmp_fpga_ops_write_complete(struct fpga_manager *mgr,
+ struct fpga_image_info *info)
+{
+ return 0;
+}
+
+static enum fpga_mgr_states zynqmp_fpga_ops_state(struct fpga_manager *mgr)
+{
+ const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
+ u32 status;
+
+ if (!eemi_ops || !eemi_ops->fpga_get_status)
+ return FPGA_MGR_STATE_UNKNOWN;
+
+ eemi_ops->fpga_get_status();
+ if (status & IXR_FPGA_DONE_MASK)
+ return FPGA_MGR_STATE_OPERATING;
+
+ return FPGA_MGR_STATE_UNKNOWN;
+}
+
+static const struct fpga_manager_ops zynqmp_fpga_ops = {
+ .state = zynqmp_fpga_ops_state,
+ .write_init = zynqmp_fpga_ops_write_init,
+ .write = zynqmp_fpga_ops_write,
+ .write_complete = zynqmp_fpga_ops_write_complete,
+};
+
+
[PATCH v4 1/3] firmware: xilinx: Add fpga API's
This Patch Adds fpga API's to support the Bitstream loading
by using firmware interface.
Signed-off-by: Nava kishore Manne
---
Changes for v4:
-None.
Chnages for v3:
-Created patches on top of 5.0-rc5.
No functional changes.
Changes for v2:
-Added Firmware FPGA Manager flags As suggested by
Moritz.
Changes for v1:
-None.
Changes for RFC-V2:
-New Patch
drivers/firmware/xilinx/zynqmp.c | 46
include/linux/firmware/xlnx-zynqmp.h | 10 ++
2 files changed, 56 insertions(+)
diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
index 98f936125643..7159a90abc44 100644
--- a/drivers/firmware/xilinx/zynqmp.c
+++ b/drivers/firmware/xilinx/zynqmp.c
@@ -537,6 +537,50 @@ static int zynqmp_pm_reset_get_status(const enum
zynqmp_pm_reset reset,
return ret;
}
+/*
+ * zynqmp_pm_fpga_load - Perform the fpga load
+ * @address: Address to write to
+ * @size: pl bitstream size
+ * @flags:
+ * BIT(0) - Bit-stream type.
+ * 0 - Full Bitstream.
+ * 1 - Partial Bitstream.
+ *
+ * This function provides access to pmufw. To transfer
+ * the required bitstream into PL.
+ *
+ * Return: Returns status, either success or error+reason
+ */
+static int zynqmp_pm_fpga_load(const u64 address, const u32 size,
+ const u32 flags)
+{
+ return zynqmp_pm_invoke_fn(PM_FPGA_LOAD, lower_32_bits(address),
+ upper_32_bits(address), size, flags, NULL);
+}
+
+/**
+ * zynqmp_pm_fpga_get_status - Read value from PCAP status register
+ * @value: Value to read
+ *
+ * This function provides access to the xilfpga library to get
+ * the PCAP status
+ *
+ * Return: Returns status, either success or error+reason
+ */
+static int zynqmp_pm_fpga_get_status(u32 *value)
+{
+ u32 ret_payload[PAYLOAD_ARG_CNT];
+ int ret;
+
+ if (!value)
+ return -EINVAL;
+
+ ret = zynqmp_pm_invoke_fn(PM_FPGA_GET_STATUS, 0, 0, 0, 0, ret_payload);
+ *value = ret_payload[1];
+
+ return ret;
+}
+
/**
* zynqmp_pm_init_finalize() - PM call to inform firmware that the caller
*master has initialized its own power management
@@ -640,6 +684,8 @@ static const struct zynqmp_eemi_ops eemi_ops = {
.request_node = zynqmp_pm_request_node,
.release_node = zynqmp_pm_release_node,
.set_requirement = zynqmp_pm_set_requirement,
+ .fpga_load = zynqmp_pm_fpga_load,
+ .fpga_get_status = zynqmp_pm_fpga_get_status,
};
/**
diff --git a/include/linux/firmware/xlnx-zynqmp.h
b/include/linux/firmware/xlnx-zynqmp.h
index 642dab10f65d..4df226b6ab0f 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -48,6 +48,12 @@
#defineZYNQMP_PM_CAPABILITY_WAKEUP 0x4U
#defineZYNQMP_PM_CAPABILITY_POWER 0x8U
+/*
+ * Firmware FPGA Manager flags
+ * XILINX_ZYNQMP_PM_FPGA_PARTIAL: FPGA partial reconfiguration
+ */
+#define XILINX_ZYNQMP_PM_FPGA_PARTIAL BIT(0)
+
enum pm_api_id {
PM_GET_API_VERSION = 1,
PM_REQUEST_NODE = 13,
@@ -56,6 +62,8 @@ enum pm_api_id {
PM_RESET_ASSERT = 17,
PM_RESET_GET_STATUS,
PM_PM_INIT_FINALIZE = 21,
+ PM_FPGA_LOAD = 22,
+ PM_FPGA_GET_STATUS,
PM_GET_CHIPID = 24,
PM_IOCTL = 34,
PM_QUERY_DATA,
@@ -258,6 +266,8 @@ struct zynqmp_pm_query_data {
struct zynqmp_eemi_ops {
int (*get_api_version)(u32 *version);
int (*get_chipid)(u32 *idcode, u32 *version);
+ int (*fpga_load)(const u64 address, const u32 size, const u32 flags);
+ int (*fpga_get_status)(u32 *value);
int (*query_data)(struct zynqmp_pm_query_data qdata, u32 *out);
int (*clock_enable)(u32 clock_id);
int (*clock_disable)(u32 clock_id);
--
2.18.0
[PATCH v4 2/3] dt-bindings: fpga: Add bindings for ZynqMP fpga driver
Add documentation to describe Xilinx ZynqMP fpga driver
bindings.
Signed-off-by: Nava kishore Manne
Reviewed-by: Rob Herring
Acked-by: Alan Tull
Acked-by: Moritz Fischer
---
.../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt | 25 +++
1 file changed, 25 insertions(+)
create mode 100644
Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
diff --git a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
new file mode 100644
index ..3052bf619dd5
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
@@ -0,0 +1,25 @@
+Devicetree bindings for Zynq Ultrascale MPSoC FPGA Manager.
+The ZynqMP SoC uses the PCAP (Processor configuration Port) to configure the
+Programmable Logic (PL). The configuration uses the firmware interface.
+
+Required properties:
+- compatible: should contain "xlnx,zynqmp-pcap-fpga"
+
+Example for full FPGA configuration:
+
+ fpga-region0 {
+ compatible = "fpga-region";
+ fpga-mgr = <_pcap>;
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ };
+
+ firmware {
+ zynqmp_firmware: zynqmp-firmware {
+ compatible = "xlnx,zynqmp-firmware";
+ method = "smc";
+ zynqmp_pcap: pcap {
+ compatible = "xlnx,zynqmp-pcap-fpga";
+ };
+ };
+ };
--
2.18.0
[PATCH v4 0/3] Add Bitstream configuration support for ZynqMP
Nava kishore Manne (3): firmware: xilinx: Add fpga API's dt-bindings: fpga: Add bindings for ZynqMP fpga driver fpga manager: Adding FPGA Manager support for Xilinx zynqmp .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt | 25 +++ drivers/firmware/xilinx/zynqmp.c | 46 + drivers/fpga/Kconfig | 9 + drivers/fpga/Makefile | 1 + drivers/fpga/zynqmp-fpga.c| 159 ++ include/linux/firmware/xlnx-zynqmp.h | 10 ++ 6 files changed, 250 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt create mode 100644 drivers/fpga/zynqmp-fpga.c -- 2.18.0
[PATCH v5 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga driver
Add documentation to describe Xilinx ZynqMP fpga driver
bindings.
Signed-off-by: Nava kishore Manne
---
Changes for v5:
-Moved pcap node as a child to firwmare
node as suggested by Rob.
Changes for v4:
-Modified binding description as suggested by Moritz Fischer.
Changes for v3:
-Removed PCAP as a child node to the FW and Created
an independent node since PCAP driver is a consumer
not a provider.
.../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt | 25 +++
1 file changed, 25 insertions(+)
create mode 100644
Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
diff --git a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
new file mode 100644
index ..3052bf619dd5
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
@@ -0,0 +1,25 @@
+Devicetree bindings for Zynq Ultrascale MPSoC FPGA Manager.
+The ZynqMP SoC uses the PCAP (Processor configuration Port) to configure the
+Programmable Logic (PL). The configuration uses the firmware interface.
+
+Required properties:
+- compatible: should contain "xlnx,zynqmp-pcap-fpga"
+
+Example for full FPGA configuration:
+
+ fpga-region0 {
+ compatible = "fpga-region";
+ fpga-mgr = <_pcap>;
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ };
+
+ firmware {
+ zynqmp_firmware: zynqmp-firmware {
+ compatible = "xlnx,zynqmp-firmware";
+ method = "smc";
+ zynqmp_pcap: pcap {
+ compatible = "xlnx,zynqmp-pcap-fpga";
+ };
+ };
+ };
--
2.18.0
[PATCH v5 4/6] dt-bindings: pinctrl: Add ZynqMP pin controller bindings
From: Rajan Vaja Add documentation to describe Xilinx ZynqMP pin controller bindings. Signed-off-by: Rajan Vaja Signed-off-by: Jolly Shah Reviewed-by: Rob Herring --- .../bindings/pinctrl/xlnx,zynqmp-pinctrl.txt | 275 ++ 1 file changed, 275 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.txt diff --git a/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.txt new file mode 100644 index ..acf44a5d3778 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.txt @@ -0,0 +1,275 @@ + Binding for Xilinx ZynqMP Pinctrl + +Required properties: +- compatible: "xlnx,zynqmp-pinctrl" + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +ZynqMP's pin configuration nodes act as a container for an arbitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those pin(s)/group(s), and various pin configuration +parameters, such as pull-up, slew rate, etc. + +Each configuration node can consist of multiple nodes describing the pinmux and +pinconf options. Those nodes can be pinmux nodes or pinconf nodes. + +The name of each subnode is not important; all subnodes should be enumerated +and processed purely based on their content. + +Required properties for pinmux nodes are: + - groups: A list of pinmux groups. + - function: The name of a pinmux function to activate for the specified set + of groups. + +Required properties for configuration nodes: +One of: + - pins: A list of pin names + - groups: A list of pinmux groups. + +The following generic properties as defined in pinctrl-bindings.txt are valid +to specify in a pinmux subnode: + groups, function + +The following generic properties as defined in pinctrl-bindings.txt are valid +to specify in a pinconf subnode: + groups, pins, bias-disable, bias-pull-up, bias-pull-down, slew-rate + + Valid arguments for 'slew-rate' are 'SLEW_RATE_SLOW' and 'SLEW_RATE_FAST' to + select between slow and fast respectively. + + Valid values for groups are: + ethernet0_0_grp, ethernet1_0_grp, ethernet2_0_grp, + ethernet3_0_grp, gemtsu0_0_grp, gemtsu0_1_grp, + gemtsu0_2_grp, mdio0_0_grp, mdio1_0_grp, + mdio1_1_grp, mdio2_0_grp, mdio3_0_grp, + qspi0_0_grp, qspi_ss_0_grp, qspi_fbclk_0_grp, + spi0_0_grp, spi0_ss_0_grp, spi0_ss_1_grp, + spi0_ss_2_grp, spi0_1_grp, spi0_ss_3_grp, + spi0_ss_4_grp, spi0_ss_5_grp, spi0_2_grp, + spi0_ss_6_grp, spi0_ss_7_grp, spi0_ss_8_grp, + spi0_3_grp, spi0_ss_9_grp, spi0_ss_10_grp, + spi0_ss_11_grp, spi0_4_grp, spi0_ss_12_grp, + spi0_ss_13_grp, spi0_ss_14_grp, spi0_5_grp, + spi0_ss_15_grp, spi0_ss_16_grp, spi0_ss_17_grp, + spi1_0_grp, spi1_ss_0_grp, spi1_ss_1_grp, + spi1_ss_2_grp, spi1_1_grp, spi1_ss_3_grp, + spi1_ss_4_grp, spi1_ss_5_grp, spi1_2_grp, + spi1_ss_6_grp, spi1_ss_7_grp, spi1_ss_8_grp, + spi1_3_grp, spi1_ss_9_grp, spi1_ss_10_grp, + spi1_ss_11_grp, spi1_4_grp, spi1_ss_12_grp, + spi1_ss_13_grp, spi1_ss_14_grp, spi1_5_grp, + spi1_ss_15_grp, spi1_ss_16_grp, spi1_ss_17_grp, + sdio0_0_grp, sdio0_1_grp, sdio0_2_grp, + sdio0_3_grp, sdio0_4_grp, sdio0_5_grp, + sdio0_6_grp, sdio0_7_grp, sdio0_8_grp, + sdio0_9_grp, sdio0_10_grp, sdio0_11_grp, + sdio0_12_grp, sdio0_13_grp, sdio0_14_grp, + sdio0_15_grp, sdio0_16_grp, sdio0_17_grp, + sdio0_18_grp, sdio0_19_grp, sdio0_20_grp, + sdio0_21_grp, sdio0_22_grp, sdio0_23_grp, + sdio0_24_grp, sdio0_25_grp, sdio0_26_grp, + sdio0_27_grp, sdio0_28_grp, sdio0_29_grp, + sdio0_30_grp, sdio0_31_grp, sdio0_32_grp, + sdio0_pc_0_grp, sdio0_cd_0_grp, sdio0_wp_0_grp, + sdio0_pc_1_grp, sdio0_cd_1_grp, sdio0_wp_1_grp, + sdio0_pc_2_grp, sdio0_cd_2_grp, sdio0_wp_2_grp, + sdio1_0_grp, sdio1_1_grp, sdio1_2_grp, + sdio1_3_grp, sdio1_4_grp, sdio1_5_grp, + sdio1_6_grp, sdio1_7_grp, sdio1_8_grp, + sdio1_9_grp, sdio1_10_grp, sdio1_11_grp, + sdio1_12_grp, sdio1_13_grp, sdio1_14_grp, + sdio1_15_grp, sdio1_pc_0_grp, sdio1_cd_0_grp, + sdio1_wp_0_grp, sdio1_pc_1_grp, sdio1_cd_1_grp, + sdio1_wp_1_grp, nand0_0_grp, nand0_ce_0_grp, + nand0_rb_0_grp, nand0_dqs_0_grp, nand0_ce_1_grp, + nand0_rb_1_grp, nand0_dqs_1_grp, can0_0_grp, + can0_1_grp, can0_2_grp, can0_3_grp, + can0_4_grp, can0_5_grp, can0_6_grp, + can0_7_grp, can0_8_grp, can0_9_grp, + can0_10_grp, can0_11_grp, can0_12_grp, + can0_13_grp, can0_14_grp, can0_15_grp, + can0_16_grp, can0_17_grp, can0_18_grp, + can1_0_grp, can1_1_grp, can1_2_grp, + can1_3_grp, can1_4_grp, can1_5_grp, + can1_6_grp, can1_7_grp, can1_8_grp, + can1_9_grp, can1_10_grp, can1_11_grp, + can1_12_grp, can1_13_grp, can1_14_grp, + can1_15_grp, can1_16_grp, can1_17_grp, + can1_18_grp, can1_19_grp, uart0_0_grp, + uart0_1_grp, uart0_2_grp, uart0_3_grp, + uart0_4_grp,
[PATCH v5 5/6] dt-bindings: nvmem: Add bindings for ZynqMP nvmem driver
Add documentation to describe Xilinx ZynqMP nvmem driver
bindings.
Signed-off-by: Nava kishore Manne
Reviewed-by: Rob Herring
---
.../bindings/nvmem/xlnx,zynqmp-nvmem.txt | 47 +++
1 file changed, 47 insertions(+)
create mode 100644
Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt
diff --git a/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt
b/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt
new file mode 100644
index ..2043c8284f8c
--- /dev/null
+++ b/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt
@@ -0,0 +1,47 @@
+--
+= Zynq UltraScale+ MPSoC nvmem firmware driver binding =
+--
+The nvmem_firmware node provides access to the hardware related data
+like soc revision, IDCODE... etc, By using the firmware interface.
+
+Required properties:
+- compatible: should be "xlnx,zynqmp-nvmem-fw"
+
+= Data cells =
+Are child nodes of silicon id, bindings of which as described in
+bindings/nvmem/nvmem.txt
+
+---
+ Example
+---
+firmware {
+ zynqmp_firmware: zynqmp-firmware {
+ compatible = "xlnx,zynqmp-firmware";
+ method = "smc";
+
+ nvmem_firmware {
+ compatible = "xlnx,zynqmp-nvmem-fw";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* Data cells */
+ soc_revision: soc_revision {
+ reg = <0x0 0x4>;
+ };
+ };
+ };
+};
+
+= Data consumers =
+Are device nodes which consume nvmem data cells.
+
+For example:
+ pcap {
+ ...
+
+ nvmem-cells = <_revision>;
+ nvmem-cell-names = "soc_revision";
+
+ ...
+ };
+
--
2.18.0
[PATCH v5 3/6] dt-bindings: reset: Add bindings for ZynqMP reset driver
Add documentation to describe Xilinx ZynqMP reset driver
bindings.
Signed-off-by: Nava kishore Manne
Signed-off-by: Jolly Shah
Reviewed-by: Rob Herring
---
.../bindings/reset/xlnx,zynqmp-reset.txt | 52 +++
.../dt-bindings/reset/xlnx-zynqmp-resets.h| 130 ++
2 files changed, 182 insertions(+)
create mode 100644
Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt
create mode 100644 include/dt-bindings/reset/xlnx-zynqmp-resets.h
diff --git a/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt
b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt
new file mode 100644
index ..27a45fe5ecf1
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt
@@ -0,0 +1,52 @@
+--
+ = Zynq UltraScale+ MPSoC reset driver binding =
+--
+The Zynq UltraScale+ MPSoC has several different resets.
+
+See Chapter 36 of the Zynq UltraScale+ MPSoC TRM (UG) for more information
+about zynqmp resets.
+
+Please also refer to reset.txt in this directory for common reset
+controller binding usage.
+
+Required Properties:
+- compatible: "xlnx,zynqmp-reset"
+- #reset-cells:Specifies the number of cells needed to encode reset
+ line, should be 1
+
+---
+Example
+---
+
+firmware {
+ zynqmp_firmware: zynqmp-firmware {
+ compatible = "xlnx,zynqmp-firmware";
+ method = "smc";
+
+ zynqmp_reset: reset-controller {
+ compatible = "xlnx,zynqmp-reset";
+ #reset-cells = <1>;
+ };
+ };
+};
+
+Specifying reset lines connected to IP modules
+==
+
+Device nodes that need access to reset lines should
+specify them as a reset phandle in their corresponding node as
+specified in reset.txt.
+
+For list of all valid reset indicies see
+
+
+Example:
+
+serdes: zynqmp_phy@fd40 {
+ ...
+
+ resets = <_reset ZYNQMP_RESET_SATA>;
+ reset-names = "sata_rst";
+
+ ...
+};
diff --git a/include/dt-bindings/reset/xlnx-zynqmp-resets.h
b/include/dt-bindings/reset/xlnx-zynqmp-resets.h
new file mode 100644
index ..e295fd5d824e
--- /dev/null
+++ b/include/dt-bindings/reset/xlnx-zynqmp-resets.h
@@ -0,0 +1,130 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 Xilinx, Inc.
+ */
+
+#ifndef _DT_BINDINGS_ZYNQMP_RESETS_H
+#define _DT_BINDINGS_ZYNQMP_RESETS_H
+
+#defineZYNQMP_RESET_PCIE_CFG 0
+#defineZYNQMP_RESET_PCIE_BRIDGE1
+#defineZYNQMP_RESET_PCIE_CTRL 2
+#defineZYNQMP_RESET_DP 3
+#defineZYNQMP_RESET_SWDT_CRF 4
+#defineZYNQMP_RESET_AFI_FM55
+#defineZYNQMP_RESET_AFI_FM46
+#defineZYNQMP_RESET_AFI_FM37
+#defineZYNQMP_RESET_AFI_FM28
+#defineZYNQMP_RESET_AFI_FM19
+#defineZYNQMP_RESET_AFI_FM010
+#defineZYNQMP_RESET_GDMA 11
+#defineZYNQMP_RESET_GPU_PP112
+#defineZYNQMP_RESET_GPU_PP013
+#defineZYNQMP_RESET_GPU14
+#defineZYNQMP_RESET_GT 15
+#defineZYNQMP_RESET_SATA 16
+#defineZYNQMP_RESET_ACPU3_PWRON17
+#defineZYNQMP_RESET_ACPU2_PWRON18
+#defineZYNQMP_RESET_ACPU1_PWRON19
+#defineZYNQMP_RESET_ACPU0_PWRON20
+#defineZYNQMP_RESET_APU_L2 21
+#defineZYNQMP_RESET_ACPU3 22
+#defineZYNQMP_RESET_ACPU2 23
+#defineZYNQMP_RESET_ACPU1 24
+#defineZYNQMP_RESET_ACPU0 25
+#defineZYNQMP_RESET_DDR26
+#defineZYNQMP_RESET_APM_FPD27
+#defineZYNQMP_RESET_SOFT 28
+#defineZYNQMP_RESET_GEM0 29
+#defineZYNQMP_RESET_GEM1 30
+#defineZYNQMP_RESET_GEM2 31
+#defineZYNQMP_RESET_GEM3 32
+#defineZYNQMP_RESET_QSPI 33
+#defineZYNQMP_RESET_UART0 34
+#defineZYNQMP_RESET_UART1 35
+#defineZYNQMP_RESET_SPI0 36
+#defineZYNQMP_RESET_SPI1 37
+#defineZYNQMP_RESET_SDIO0 38
+#def
[PATCH v5 1/6] dt-bindings: power: Add ZynqMP power domain bindings
From: Rajan Vaja
Add documentation to describe ZynqMP power domain bindings.
Signed-off-by: Rajan Vaja
Signed-off-by: Jolly Shah
Reviewed-by: Rob Herring
---
.../bindings/power/xlnx,zynqmp-genpd.txt | 34
include/dt-bindings/power/xlnx-zynqmp-power.h | 39 +++
2 files changed, 73 insertions(+)
create mode 100644
Documentation/devicetree/bindings/power/xlnx,zynqmp-genpd.txt
create mode 100644 include/dt-bindings/power/xlnx-zynqmp-power.h
diff --git a/Documentation/devicetree/bindings/power/xlnx,zynqmp-genpd.txt
b/Documentation/devicetree/bindings/power/xlnx,zynqmp-genpd.txt
new file mode 100644
index ..3c7f2378e146
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/xlnx,zynqmp-genpd.txt
@@ -0,0 +1,34 @@
+---
+Device Tree Bindings for the Xilinx Zynq MPSoC PM domains
+---
+The binding for zynqmp-power-controller follow the common
+generic PM domain binding[1].
+
+[1] Documentation/devicetree/bindings/power/power_domain.txt
+
+== Zynq MPSoC Generic PM Domain Node ==
+
+Required property:
+ - Below property should be in zynqmp-firmware node.
+ - #power-domain-cells:Number of cells in a PM domain specifier. Must
be 1.
+
+Power domain ID indexes are mentioned in
+include/dt-bindings/power/xlnx-zynqmp-power.h.
+
+---
+Example
+---
+
+firmware {
+ zynqmp_firmware: zynqmp-firmware {
+ ...
+ #power-domain-cells = <1>;
+ ...
+ };
+};
+
+sata {
+ ...
+ power-domains = <_firmware 2>;
+ ...
+};
diff --git a/include/dt-bindings/power/xlnx-zynqmp-power.h
b/include/dt-bindings/power/xlnx-zynqmp-power.h
new file mode 100644
index ..1bc9636098ca
--- /dev/null
+++ b/include/dt-bindings/power/xlnx-zynqmp-power.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 Xilinx, Inc.
+ */
+
+#ifndef _DT_BINDINGS_ZYNQMP_POWER_H
+#define _DT_BINDINGS_ZYNQMP_POWER_H
+
+#definePD_USB_00
+#definePD_USB_11
+#definePD_SATA 2
+#definePD_SPI_03
+#definePD_SPI_14
+#definePD_UART_0 5
+#definePD_UART_1 6
+#definePD_ETH_07
+#definePD_ETH_18
+#definePD_ETH_29
+#definePD_ETH_310
+#definePD_I2C_011
+#definePD_I2C_112
+#definePD_DP 13
+#definePD_GDMA 14
+#definePD_ADMA 15
+#definePD_TTC_016
+#definePD_TTC_117
+#definePD_TTC_218
+#definePD_TTC_319
+#definePD_SD_0 20
+#definePD_SD_1 21
+#definePD_NAND 22
+#definePD_QSPI 23
+#definePD_GPIO 24
+#definePD_CAN_025
+#definePD_CAN_126
+#definePD_PCIE 27
+#definePD_GPU 28
+
+#endif
--
2.18.0
[PATCH v5 2/6] dt-bindings: soc: Add ZynqMP PM bindings
From: Rajan Vaja
Add documentation to describe Xilinx ZynqMP power management
bindings.
Signed-off-by: Rajan Vaja
Signed-off-by: Jolly Shah
Reviewed-by: Rob Herring
---
.../power/reset/xlnx,zynqmp-power.txt | 25 +++
1 file changed, 25 insertions(+)
create mode 100644
Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt
diff --git
a/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt
b/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt
new file mode 100644
index ..d366f1eb623a
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt
@@ -0,0 +1,25 @@
+
+Device Tree Bindings for the Xilinx Zynq MPSoC Power Management
+
+The zynqmp-power node describes the power management configurations.
+It will control remote suspend/shutdown interfaces.
+
+Required properties:
+ - compatible: Must contain: "xlnx,zynqmp-power"
+ - interrupts: Interrupt specifier
+
+---
+Example
+---
+
+firmware {
+ zynqmp_firmware: zynqmp-firmware {
+ compatible = "xlnx,zynqmp-firmware";
+ method = "smc";
+
+ zynqmp_power: zynqmp-power {
+ compatible = "xlnx,zynqmp-power";
+ interrupts = <0 35 4>;
+ };
+ };
+};
--
2.18.0
[PATCH v5 0/6]dt-bindings: Firmware node binding for ZynqMP core
Base firmware node and clock child node binding are part of mainline kernel.
This patchset adds documentation to describe rest of the firmware child node
bindings.
Complete firmware DT node example is shown below for ease of understanding:
firmware {
zynqmp_firmware: zynqmp-firmware {
compatible = "xlnx,zynqmp-firmware";
method = "smc";
#power-domain-cells = <1>;
#reset-cells = <1>;
zynqmp_clk: clock-controller {
#clock-cells = <1>;
compatible = "xlnx,zynqmp-clk";
clocks = <_ref_clk>, <_clk>,
<_alt_ref_clk>, <_ref_clk>, <_crx_ref_clk>;
clock-names = "pss_ref_clk", "video_clk",
"pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk";
};
zynqmp_power: zynqmp-power {
compatible = "xlnx,zynqmp-power";
interrupts = <0 35 4>;
};
zynqmp_reset: reset-controller {
compatible = "xlnx,zynqmp-reset";
#reset-cells = <1>;
};
nvmem_firmware {
compatible = "xlnx,zynqmp-nvmem-fw";
#address-cells = <1>;
#size-cells = <1>;
/* Data cells */
soc_revision: soc_revision {
reg = <0x0 0x4>;
};
};
pinctrl0: pinctrl@ff18 {
compatible = "xlnx,zynqmp-pinctrl";
pinctrl_uart1_default: uart1-default {
mux {
groups = "uart0_4_grp";
function = "uart0";
};
conf {
groups = "uart0_4_grp";
slew-rate = ;
io-standard = ;
};
conf-rx {
pins = "MIO18";
bias-high-impedance;
};
conf-tx {
pins = "MIO19";
bias-disable;
schmitt-cmos = ;
};
};
};
zynqmp_pcap: pcap {
compatible = "xlnx,zynqmp-pcap-fpga";
};
};
};
Nava kishore Manne (3):
dt-bindings: reset: Add bindings for ZynqMP reset driver
dt-bindings: nvmem: Add bindings for ZynqMP nvmem driver
dt-bindings: fpga: Add bindings for ZynqMP fpga driver
Rajan Vaja (3):
dt-bindings: power: Add ZynqMP power domain bindings
dt-bindings: soc: Add ZynqMP PM bindings
dt-bindings: pinctrl: Add ZynqMP pin controller bindings
.../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt | 25 ++
.../bindings/nvmem/xlnx,zynqmp-nvmem.txt | 47 +++
.../bindings/pinctrl/xlnx,zynqmp-pinctrl.txt | 275 ++
.../power/reset/xlnx,zynqmp-power.txt | 25 ++
.../bindings/power/xlnx,zynqmp-genpd.txt | 34 +++
.../bindings/reset/xlnx,zynqmp-reset.txt | 52
include/dt-bindings/power/xlnx-zynqmp-power.h | 39 +++
.../dt-bindings/reset/xlnx-zynqmp-resets.h| 130 +
8 files changed, 627 insertions(+)
create mode 100644
Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
create mode 100644
Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt
create mode 100644
Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.txt
create mode 100644
Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt
create mode 100644
Documentation/devicetree/bindings/power/xlnx,zynqmp-genpd.txt
create mode 100644
Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt
create mode 100644 include/dt-bindings/power/xlnx-zynqmp-power.h
create mode 100644 include/dt-bindings/reset/xlnx-zynqmp-resets.h
--
2.18.0
RE: [PATCH v4 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga driver
Hi Rob, Thanks for the response. Please find my response inline. > -Original Message- > From: Rob Herring [mailto:r...@kernel.org] > Sent: Tuesday, March 26, 2019 12:49 AM > To: Nava kishore Manne > Cc: at...@kernel.org; m...@kernel.org; mark.rutl...@arm.com; Michal Simek > ; Rajan Vaja ; Jolly Shah > ; linux-f...@vger.kernel.org; devicet...@vger.kernel.org; > linux-arm-ker...@lists.infradead.org; linux-kernel@vger.kernel.org; > chinnikishore...@gmail.com > Subject: Re: [PATCH v4 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga > driver > > On Thu, Mar 14, 2019 at 07:31:22PM +0530, Nava kishore Manne wrote: > > Add documentation to describe Xilinx ZynqMP fpga driver bindings. > > > > Signed-off-by: Nava kishore Manne > > --- > > Changes for v4: > > -Modified binding description as suggested by Moritz Fischer. > > Changes for v3: > > -Removed PCAP as a child node to the FW and Created > > an independent node since PCAP driver is a consumer > > not a provider. > > Huh? > > It was the fpga-regions that I suggested should perhaps be at the top-level. > As > long as pcap is a function exposed by the firmware it should be a child of it. > Thanks for providing the clarification. Will address the above comments in the next version. Regards, Navakishore.
RE: [PATCH v4 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga driver
Ping!!
> -Original Message-
> From: Nava kishore Manne [mailto:nava.ma...@xilinx.com]
> Sent: Thursday, March 14, 2019 7:31 PM
> To: at...@kernel.org; m...@kernel.org; robh...@kernel.org;
> mark.rutl...@arm.com; Michal Simek ; Rajan Vaja
> ; Jolly Shah ; Nava kishore Manne
> ; linux-f...@vger.kernel.org; devicet...@vger.kernel.org;
> linux-arm-ker...@lists.infradead.org; linux-kernel@vger.kernel.org;
> chinnikishore...@gmail.com
> Subject: [PATCH v4 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga driver
>
> Add documentation to describe Xilinx ZynqMP fpga driver bindings.
>
> Signed-off-by: Nava kishore Manne
> ---
> Changes for v4:
> -Modified binding description as suggested by Moritz Fischer.
> Changes for v3:
> -Removed PCAP as a child node to the FW and Created
>an independent node since PCAP driver is a consumer
>not a provider.
>
> .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt | 11 +++
> 1 file changed, 11 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,zynqmp-
> pcap-fpga.txt
>
> diff --git a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> new file mode 100644
> index ..6d7f10775d9b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> @@ -0,0 +1,11 @@
> +Devicetree bindings for Zynq Ultrascale MPSoC FPGA Manager.
> +The ZynqMP SoC uses the PCAP (Processor configuration Port) to
> +configure the Programmable Logic (PL). The configuration uses the firmware
> interface.
> +
> +Required properties:
> +- compatible: should contain "xlnx,zynqmp-pcap-fpga"
> +
> +Example:
> + zynqmp_pcap: pcap {
> + compatible = "xlnx,zynqmp-pcap-fpga";
> + };
> --
> 2.18.0
[PATCH v4 5/6] dt-bindings: nvmem: Add bindings for ZynqMP nvmem driver
Add documentation to describe Xilinx ZynqMP nvmem driver
bindings.
Signed-off-by: Nava kishore Manne
Reviewed-by: Rob Herring
---
.../bindings/nvmem/xlnx,zynqmp-nvmem.txt | 47 +++
1 file changed, 47 insertions(+)
create mode 100644
Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt
diff --git a/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt
b/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt
new file mode 100644
index ..2043c8284f8c
--- /dev/null
+++ b/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt
@@ -0,0 +1,47 @@
+--
+= Zynq UltraScale+ MPSoC nvmem firmware driver binding =
+--
+The nvmem_firmware node provides access to the hardware related data
+like soc revision, IDCODE... etc, By using the firmware interface.
+
+Required properties:
+- compatible: should be "xlnx,zynqmp-nvmem-fw"
+
+= Data cells =
+Are child nodes of silicon id, bindings of which as described in
+bindings/nvmem/nvmem.txt
+
+---
+ Example
+---
+firmware {
+ zynqmp_firmware: zynqmp-firmware {
+ compatible = "xlnx,zynqmp-firmware";
+ method = "smc";
+
+ nvmem_firmware {
+ compatible = "xlnx,zynqmp-nvmem-fw";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* Data cells */
+ soc_revision: soc_revision {
+ reg = <0x0 0x4>;
+ };
+ };
+ };
+};
+
+= Data consumers =
+Are device nodes which consume nvmem data cells.
+
+For example:
+ pcap {
+ ...
+
+ nvmem-cells = <_revision>;
+ nvmem-cell-names = "soc_revision";
+
+ ...
+ };
+
--
2.18.0
[PATCH v4 4/6] dt-bindings: pinctrl: Add ZynqMP pin controller bindings
From: Rajan Vaja Add documentation to describe Xilinx ZynqMP pin controller bindings. Signed-off-by: Rajan Vaja Signed-off-by: Jolly Shah Reviewed-by: Rob Herring --- .../bindings/pinctrl/xlnx,zynqmp-pinctrl.txt | 275 ++ 1 file changed, 275 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.txt diff --git a/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.txt new file mode 100644 index ..acf44a5d3778 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.txt @@ -0,0 +1,275 @@ + Binding for Xilinx ZynqMP Pinctrl + +Required properties: +- compatible: "xlnx,zynqmp-pinctrl" + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +ZynqMP's pin configuration nodes act as a container for an arbitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those pin(s)/group(s), and various pin configuration +parameters, such as pull-up, slew rate, etc. + +Each configuration node can consist of multiple nodes describing the pinmux and +pinconf options. Those nodes can be pinmux nodes or pinconf nodes. + +The name of each subnode is not important; all subnodes should be enumerated +and processed purely based on their content. + +Required properties for pinmux nodes are: + - groups: A list of pinmux groups. + - function: The name of a pinmux function to activate for the specified set + of groups. + +Required properties for configuration nodes: +One of: + - pins: A list of pin names + - groups: A list of pinmux groups. + +The following generic properties as defined in pinctrl-bindings.txt are valid +to specify in a pinmux subnode: + groups, function + +The following generic properties as defined in pinctrl-bindings.txt are valid +to specify in a pinconf subnode: + groups, pins, bias-disable, bias-pull-up, bias-pull-down, slew-rate + + Valid arguments for 'slew-rate' are 'SLEW_RATE_SLOW' and 'SLEW_RATE_FAST' to + select between slow and fast respectively. + + Valid values for groups are: + ethernet0_0_grp, ethernet1_0_grp, ethernet2_0_grp, + ethernet3_0_grp, gemtsu0_0_grp, gemtsu0_1_grp, + gemtsu0_2_grp, mdio0_0_grp, mdio1_0_grp, + mdio1_1_grp, mdio2_0_grp, mdio3_0_grp, + qspi0_0_grp, qspi_ss_0_grp, qspi_fbclk_0_grp, + spi0_0_grp, spi0_ss_0_grp, spi0_ss_1_grp, + spi0_ss_2_grp, spi0_1_grp, spi0_ss_3_grp, + spi0_ss_4_grp, spi0_ss_5_grp, spi0_2_grp, + spi0_ss_6_grp, spi0_ss_7_grp, spi0_ss_8_grp, + spi0_3_grp, spi0_ss_9_grp, spi0_ss_10_grp, + spi0_ss_11_grp, spi0_4_grp, spi0_ss_12_grp, + spi0_ss_13_grp, spi0_ss_14_grp, spi0_5_grp, + spi0_ss_15_grp, spi0_ss_16_grp, spi0_ss_17_grp, + spi1_0_grp, spi1_ss_0_grp, spi1_ss_1_grp, + spi1_ss_2_grp, spi1_1_grp, spi1_ss_3_grp, + spi1_ss_4_grp, spi1_ss_5_grp, spi1_2_grp, + spi1_ss_6_grp, spi1_ss_7_grp, spi1_ss_8_grp, + spi1_3_grp, spi1_ss_9_grp, spi1_ss_10_grp, + spi1_ss_11_grp, spi1_4_grp, spi1_ss_12_grp, + spi1_ss_13_grp, spi1_ss_14_grp, spi1_5_grp, + spi1_ss_15_grp, spi1_ss_16_grp, spi1_ss_17_grp, + sdio0_0_grp, sdio0_1_grp, sdio0_2_grp, + sdio0_3_grp, sdio0_4_grp, sdio0_5_grp, + sdio0_6_grp, sdio0_7_grp, sdio0_8_grp, + sdio0_9_grp, sdio0_10_grp, sdio0_11_grp, + sdio0_12_grp, sdio0_13_grp, sdio0_14_grp, + sdio0_15_grp, sdio0_16_grp, sdio0_17_grp, + sdio0_18_grp, sdio0_19_grp, sdio0_20_grp, + sdio0_21_grp, sdio0_22_grp, sdio0_23_grp, + sdio0_24_grp, sdio0_25_grp, sdio0_26_grp, + sdio0_27_grp, sdio0_28_grp, sdio0_29_grp, + sdio0_30_grp, sdio0_31_grp, sdio0_32_grp, + sdio0_pc_0_grp, sdio0_cd_0_grp, sdio0_wp_0_grp, + sdio0_pc_1_grp, sdio0_cd_1_grp, sdio0_wp_1_grp, + sdio0_pc_2_grp, sdio0_cd_2_grp, sdio0_wp_2_grp, + sdio1_0_grp, sdio1_1_grp, sdio1_2_grp, + sdio1_3_grp, sdio1_4_grp, sdio1_5_grp, + sdio1_6_grp, sdio1_7_grp, sdio1_8_grp, + sdio1_9_grp, sdio1_10_grp, sdio1_11_grp, + sdio1_12_grp, sdio1_13_grp, sdio1_14_grp, + sdio1_15_grp, sdio1_pc_0_grp, sdio1_cd_0_grp, + sdio1_wp_0_grp, sdio1_pc_1_grp, sdio1_cd_1_grp, + sdio1_wp_1_grp, nand0_0_grp, nand0_ce_0_grp, + nand0_rb_0_grp, nand0_dqs_0_grp, nand0_ce_1_grp, + nand0_rb_1_grp, nand0_dqs_1_grp, can0_0_grp, + can0_1_grp, can0_2_grp, can0_3_grp, + can0_4_grp, can0_5_grp, can0_6_grp, + can0_7_grp, can0_8_grp, can0_9_grp, + can0_10_grp, can0_11_grp, can0_12_grp, + can0_13_grp, can0_14_grp, can0_15_grp, + can0_16_grp, can0_17_grp, can0_18_grp, + can1_0_grp, can1_1_grp, can1_2_grp, + can1_3_grp, can1_4_grp, can1_5_grp, + can1_6_grp, can1_7_grp, can1_8_grp, + can1_9_grp, can1_10_grp, can1_11_grp, + can1_12_grp, can1_13_grp, can1_14_grp, + can1_15_grp, can1_16_grp, can1_17_grp, + can1_18_grp, can1_19_grp, uart0_0_grp, + uart0_1_grp, uart0_2_grp, uart0_3_grp, + uart0_4_grp,
[PATCH v4 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga driver
Add documentation to describe Xilinx ZynqMP fpga driver
bindings.
Signed-off-by: Nava kishore Manne
---
Changes for v4:
-Modified binding description as suggested by Moritz Fischer.
Changes for v3:
-Removed PCAP as a child node to the FW and Created
an independent node since PCAP driver is a consumer
not a provider.
.../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt | 11 +++
1 file changed, 11 insertions(+)
create mode 100644
Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
diff --git a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
new file mode 100644
index ..6d7f10775d9b
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
@@ -0,0 +1,11 @@
+Devicetree bindings for Zynq Ultrascale MPSoC FPGA Manager.
+The ZynqMP SoC uses the PCAP (Processor configuration Port) to configure the
+Programmable Logic (PL). The configuration uses the firmware interface.
+
+Required properties:
+- compatible: should contain "xlnx,zynqmp-pcap-fpga"
+
+Example:
+ zynqmp_pcap: pcap {
+ compatible = "xlnx,zynqmp-pcap-fpga";
+ };
--
2.18.0
[PATCH v4 1/6] dt-bindings: power: Add ZynqMP power domain bindings
From: Rajan Vaja
Add documentation to describe ZynqMP power domain bindings.
Signed-off-by: Rajan Vaja
Signed-off-by: Jolly Shah
Reviewed-by: Rob Herring
---
.../bindings/power/xlnx,zynqmp-genpd.txt | 34
include/dt-bindings/power/xlnx-zynqmp-power.h | 39 +++
2 files changed, 73 insertions(+)
create mode 100644
Documentation/devicetree/bindings/power/xlnx,zynqmp-genpd.txt
create mode 100644 include/dt-bindings/power/xlnx-zynqmp-power.h
diff --git a/Documentation/devicetree/bindings/power/xlnx,zynqmp-genpd.txt
b/Documentation/devicetree/bindings/power/xlnx,zynqmp-genpd.txt
new file mode 100644
index ..3c7f2378e146
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/xlnx,zynqmp-genpd.txt
@@ -0,0 +1,34 @@
+---
+Device Tree Bindings for the Xilinx Zynq MPSoC PM domains
+---
+The binding for zynqmp-power-controller follow the common
+generic PM domain binding[1].
+
+[1] Documentation/devicetree/bindings/power/power_domain.txt
+
+== Zynq MPSoC Generic PM Domain Node ==
+
+Required property:
+ - Below property should be in zynqmp-firmware node.
+ - #power-domain-cells:Number of cells in a PM domain specifier. Must
be 1.
+
+Power domain ID indexes are mentioned in
+include/dt-bindings/power/xlnx-zynqmp-power.h.
+
+---
+Example
+---
+
+firmware {
+ zynqmp_firmware: zynqmp-firmware {
+ ...
+ #power-domain-cells = <1>;
+ ...
+ };
+};
+
+sata {
+ ...
+ power-domains = <_firmware 2>;
+ ...
+};
diff --git a/include/dt-bindings/power/xlnx-zynqmp-power.h
b/include/dt-bindings/power/xlnx-zynqmp-power.h
new file mode 100644
index ..1bc9636098ca
--- /dev/null
+++ b/include/dt-bindings/power/xlnx-zynqmp-power.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 Xilinx, Inc.
+ */
+
+#ifndef _DT_BINDINGS_ZYNQMP_POWER_H
+#define _DT_BINDINGS_ZYNQMP_POWER_H
+
+#definePD_USB_00
+#definePD_USB_11
+#definePD_SATA 2
+#definePD_SPI_03
+#definePD_SPI_14
+#definePD_UART_0 5
+#definePD_UART_1 6
+#definePD_ETH_07
+#definePD_ETH_18
+#definePD_ETH_29
+#definePD_ETH_310
+#definePD_I2C_011
+#definePD_I2C_112
+#definePD_DP 13
+#definePD_GDMA 14
+#definePD_ADMA 15
+#definePD_TTC_016
+#definePD_TTC_117
+#definePD_TTC_218
+#definePD_TTC_319
+#definePD_SD_0 20
+#definePD_SD_1 21
+#definePD_NAND 22
+#definePD_QSPI 23
+#definePD_GPIO 24
+#definePD_CAN_025
+#definePD_CAN_126
+#definePD_PCIE 27
+#definePD_GPU 28
+
+#endif
--
2.18.0
[PATCH v4 3/6] dt-bindings: reset: Add bindings for ZynqMP reset driver
Add documentation to describe Xilinx ZynqMP reset driver
bindings.
Signed-off-by: Nava kishore Manne
Signed-off-by: Jolly Shah
Reviewed-by: Rob Herring
---
.../bindings/reset/xlnx,zynqmp-reset.txt | 52 +++
.../dt-bindings/reset/xlnx-zynqmp-resets.h| 130 ++
2 files changed, 182 insertions(+)
create mode 100644
Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt
create mode 100644 include/dt-bindings/reset/xlnx-zynqmp-resets.h
diff --git a/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt
b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt
new file mode 100644
index ..27a45fe5ecf1
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt
@@ -0,0 +1,52 @@
+--
+ = Zynq UltraScale+ MPSoC reset driver binding =
+--
+The Zynq UltraScale+ MPSoC has several different resets.
+
+See Chapter 36 of the Zynq UltraScale+ MPSoC TRM (UG) for more information
+about zynqmp resets.
+
+Please also refer to reset.txt in this directory for common reset
+controller binding usage.
+
+Required Properties:
+- compatible: "xlnx,zynqmp-reset"
+- #reset-cells:Specifies the number of cells needed to encode reset
+ line, should be 1
+
+---
+Example
+---
+
+firmware {
+ zynqmp_firmware: zynqmp-firmware {
+ compatible = "xlnx,zynqmp-firmware";
+ method = "smc";
+
+ zynqmp_reset: reset-controller {
+ compatible = "xlnx,zynqmp-reset";
+ #reset-cells = <1>;
+ };
+ };
+};
+
+Specifying reset lines connected to IP modules
+==
+
+Device nodes that need access to reset lines should
+specify them as a reset phandle in their corresponding node as
+specified in reset.txt.
+
+For list of all valid reset indicies see
+
+
+Example:
+
+serdes: zynqmp_phy@fd40 {
+ ...
+
+ resets = <_reset ZYNQMP_RESET_SATA>;
+ reset-names = "sata_rst";
+
+ ...
+};
diff --git a/include/dt-bindings/reset/xlnx-zynqmp-resets.h
b/include/dt-bindings/reset/xlnx-zynqmp-resets.h
new file mode 100644
index ..e295fd5d824e
--- /dev/null
+++ b/include/dt-bindings/reset/xlnx-zynqmp-resets.h
@@ -0,0 +1,130 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 Xilinx, Inc.
+ */
+
+#ifndef _DT_BINDINGS_ZYNQMP_RESETS_H
+#define _DT_BINDINGS_ZYNQMP_RESETS_H
+
+#defineZYNQMP_RESET_PCIE_CFG 0
+#defineZYNQMP_RESET_PCIE_BRIDGE1
+#defineZYNQMP_RESET_PCIE_CTRL 2
+#defineZYNQMP_RESET_DP 3
+#defineZYNQMP_RESET_SWDT_CRF 4
+#defineZYNQMP_RESET_AFI_FM55
+#defineZYNQMP_RESET_AFI_FM46
+#defineZYNQMP_RESET_AFI_FM37
+#defineZYNQMP_RESET_AFI_FM28
+#defineZYNQMP_RESET_AFI_FM19
+#defineZYNQMP_RESET_AFI_FM010
+#defineZYNQMP_RESET_GDMA 11
+#defineZYNQMP_RESET_GPU_PP112
+#defineZYNQMP_RESET_GPU_PP013
+#defineZYNQMP_RESET_GPU14
+#defineZYNQMP_RESET_GT 15
+#defineZYNQMP_RESET_SATA 16
+#defineZYNQMP_RESET_ACPU3_PWRON17
+#defineZYNQMP_RESET_ACPU2_PWRON18
+#defineZYNQMP_RESET_ACPU1_PWRON19
+#defineZYNQMP_RESET_ACPU0_PWRON20
+#defineZYNQMP_RESET_APU_L2 21
+#defineZYNQMP_RESET_ACPU3 22
+#defineZYNQMP_RESET_ACPU2 23
+#defineZYNQMP_RESET_ACPU1 24
+#defineZYNQMP_RESET_ACPU0 25
+#defineZYNQMP_RESET_DDR26
+#defineZYNQMP_RESET_APM_FPD27
+#defineZYNQMP_RESET_SOFT 28
+#defineZYNQMP_RESET_GEM0 29
+#defineZYNQMP_RESET_GEM1 30
+#defineZYNQMP_RESET_GEM2 31
+#defineZYNQMP_RESET_GEM3 32
+#defineZYNQMP_RESET_QSPI 33
+#defineZYNQMP_RESET_UART0 34
+#defineZYNQMP_RESET_UART1 35
+#defineZYNQMP_RESET_SPI0 36
+#defineZYNQMP_RESET_SPI1 37
+#defineZYNQMP_RESET_SDIO0 38
+#def
[PATCH v4 0/6]dt-bindings: Firmware node binding for ZynqMP core
Base firmware node and clock child node binding are part of mainline kernel.
This patchset adds documentation to describe rest of the firmware child node
bindings.
Complete firmware DT node example is shown below for ease of understanding:
firmware {
zynqmp_firmware: zynqmp-firmware {
compatible = "xlnx,zynqmp-firmware";
method = "smc";
#power-domain-cells = <1>;
#reset-cells = <1>;
zynqmp_clk: clock-controller {
#clock-cells = <1>;
compatible = "xlnx,zynqmp-clk";
clocks = <_ref_clk>, <_clk>,
<_alt_ref_clk>, <_ref_clk>, <_crx_ref_clk>;
clock-names = "pss_ref_clk", "video_clk",
"pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk";
};
zynqmp_power: zynqmp-power {
compatible = "xlnx,zynqmp-power";
interrupts = <0 35 4>;
};
zynqmp_reset: reset-controller {
compatible = "xlnx,zynqmp-reset";
#reset-cells = <1>;
};
nvmem_firmware {
compatible = "xlnx,zynqmp-nvmem-fw";
#address-cells = <1>;
#size-cells = <1>;
/* Data cells */
soc_revision: soc_revision {
reg = <0x0 0x4>;
};
};
pinctrl0: pinctrl@ff18 {
compatible = "xlnx,zynqmp-pinctrl";
pinctrl_uart1_default: uart1-default {
mux {
groups = "uart0_4_grp";
function = "uart0";
};
conf {
groups = "uart0_4_grp";
slew-rate = ;
io-standard = ;
};
conf-rx {
pins = "MIO18";
bias-high-impedance;
};
conf-tx {
pins = "MIO19";
bias-disable;
schmitt-cmos = ;
};
};
};
};
};
Nava kishore Manne (3):
dt-bindings: reset: Add bindings for ZynqMP reset driver
dt-bindings: nvmem: Add bindings for ZynqMP nvmem driver
dt-bindings: fpga: Add bindings for ZynqMP fpga driver
Rajan Vaja (3):
dt-bindings: power: Add ZynqMP power domain bindings
dt-bindings: soc: Add ZynqMP PM bindings
dt-bindings: pinctrl: Add ZynqMP pin controller bindings
.../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt | 11 +
.../bindings/nvmem/xlnx,zynqmp-nvmem.txt | 47 +++
.../bindings/pinctrl/xlnx,zynqmp-pinctrl.txt | 275 ++
.../power/reset/xlnx,zynqmp-power.txt | 25 ++
.../bindings/power/xlnx,zynqmp-genpd.txt | 34 +++
.../bindings/reset/xlnx,zynqmp-reset.txt | 52
include/dt-bindings/power/xlnx-zynqmp-power.h | 39 +++
.../dt-bindings/reset/xlnx-zynqmp-resets.h| 130 +
8 files changed, 613 insertions(+)
create mode 100644
Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
create mode 100644
Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt
create mode 100644
Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.txt
create mode 100644
Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt
create mode 100644
Documentation/devicetree/bindings/power/xlnx,zynqmp-genpd.txt
create mode 100644
Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt
create mode 100644 include/dt-bindings/power/xlnx-zynqmp-power.h
create mode 100644 include/dt-bindings/reset/xlnx-zynqmp-resets.h
--
2.18.0
[PATCH v4 2/6] dt-bindings: soc: Add ZynqMP PM bindings
From: Rajan Vaja
Add documentation to describe Xilinx ZynqMP power management
bindings.
Signed-off-by: Rajan Vaja
Signed-off-by: Jolly Shah
Reviewed-by: Rob Herring
---
.../power/reset/xlnx,zynqmp-power.txt | 25 +++
1 file changed, 25 insertions(+)
create mode 100644
Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt
diff --git
a/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt
b/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt
new file mode 100644
index ..d366f1eb623a
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt
@@ -0,0 +1,25 @@
+
+Device Tree Bindings for the Xilinx Zynq MPSoC Power Management
+
+The zynqmp-power node describes the power management configurations.
+It will control remote suspend/shutdown interfaces.
+
+Required properties:
+ - compatible: Must contain: "xlnx,zynqmp-power"
+ - interrupts: Interrupt specifier
+
+---
+Example
+---
+
+firmware {
+ zynqmp_firmware: zynqmp-firmware {
+ compatible = "xlnx,zynqmp-firmware";
+ method = "smc";
+
+ zynqmp_power: zynqmp-power {
+ compatible = "xlnx,zynqmp-power";
+ interrupts = <0 35 4>;
+ };
+ };
+};
--
2.18.0
RE: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga driver
Ping !! > -Original Message- > From: Nava kishore Manne > Sent: Tuesday, March 5, 2019 3:12 PM > To: 'Rob Herring' > Cc: mark.rutl...@arm.com; Michal Simek ; Rajan Vaja > ; linux-arm-ker...@lists.infradead.org; linux- > ker...@vger.kernel.org; devicet...@vger.kernel.org; Jolly Shah > ; chinnikishore...@gmail.com; 'Alan Tull' > ; Moritz Fischer > Subject: RE: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga > driver > > Hi Rob, > > Thanks for the quick response. > Please find my response inline. > > > -Original Message- > > From: Rob Herring [mailto:r...@kernel.org] > > Sent: Monday, March 4, 2019 10:57 PM > > To: Nava kishore Manne > > Cc: mark.rutl...@arm.com; Michal Simek ; Rajan > > Vaja ; linux-arm-ker...@lists.infradead.org; linux- > > ker...@vger.kernel.org; devicet...@vger.kernel.org; Jolly Shah > > ; chinnikishore...@gmail.com > > Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP > > fpga driver > > > > On Mon, Mar 4, 2019 at 5:35 AM Nava kishore Manne > > wrote: > > > > > > Hi Rob, > > > > > > Thanks for providing the review comments.. > > > Please find my response inline. > > > > > > > -Original Message- > > > > From: Rob Herring [mailto:r...@kernel.org] > > > > Sent: Saturday, February 23, 2019 2:01 AM > > > > To: Nava kishore Manne > > > > Cc: mark.rutl...@arm.com; Michal Simek ; Rajan > > > > Vaja ; linux-arm-ker...@lists.infradead.org; > > > > linux- ker...@vger.kernel.org; devicet...@vger.kernel.org; Jolly > > > > Shah ; chinnikishore...@gmail.com > > > > Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for > > > > ZynqMP fpga driver > > > > > > > > On Wed, Jan 23, 2019 at 2:46 PM Nava kishore Manne > > > > > > > > wrote: > > > > > > > > > > Hi Rob, > > > > > > > > > > > > > > > > > > > > Thanks for providing the comments... > > > > > > > > Please fix your mailer to send plain text emails to mail lists. > > > > > > > Thanks for pointing it.. > > > > > > > > > > > > > -Original Message- > > > > > > > > > > > From: Rob Herring [mailto:r...@kernel.org] > > > > > > > > > > > Sent: Monday, January 21, 2019 9:19 PM > > > > > > > > > > > To: Nava kishore Manne > > > > > > > > > > > Cc: mark.rutl...@arm.com; Michal Simek ; > > > > > > Rajan Vaja > > > > > > > > > > > ; linux-arm-ker...@lists.infradead.org; > > > > > > linux- > > > > > > > > > > > ker...@vger.kernel.org; devicet...@vger.kernel.org; Jolly Shah > > > > > > > > > > > ; chinnikishore...@gmail.com > > > > > > > > > > > Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings > > > > > > for ZynqMP fpga > > > > > > > > > > > driver > > > > > > > > > > > > > > > > > > > > > > On Mon, Jan 21, 2019 at 11:08:35PM +0530, Nava kishore Manne > wrote: > > > > > > > > > > > > Add documentation to describe Xilinx ZynqMP fpga driver bindings. > > > > > > > > > > > > > > > > > > > > > > > > Signed-off-by: Nava kishore Manne > > > > > > > > > > > > --- > > > > > > > > > > > > Changes for v3: > > > > > > > > > > > > -Removed PCAP as a child node to the > > > > > > > FW and Created > > > > > > > > > > > > an independent node since PCAP > > > > > > > driver is a consumer > > > > > > > > > > > > not a provider. > > > > > > > > > > > > > > > > > > > > > > > > .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt | 13 > + > > > > > > > > > > > > 1 file changed, 13 insertions(+) > > > > > > > > > > > > create mode 100644 > > > > > &
RE: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga driver
Hi Rob, Thanks for the quick response. Please find my response inline. > -Original Message- > From: Rob Herring [mailto:r...@kernel.org] > Sent: Monday, March 4, 2019 10:57 PM > To: Nava kishore Manne > Cc: mark.rutl...@arm.com; Michal Simek ; Rajan Vaja > ; linux-arm-ker...@lists.infradead.org; linux- > ker...@vger.kernel.org; devicet...@vger.kernel.org; Jolly Shah > ; chinnikishore...@gmail.com > Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga > driver > > On Mon, Mar 4, 2019 at 5:35 AM Nava kishore Manne > wrote: > > > > Hi Rob, > > > > Thanks for providing the review comments.. > > Please find my response inline. > > > > > -Original Message- > > > From: Rob Herring [mailto:r...@kernel.org] > > > Sent: Saturday, February 23, 2019 2:01 AM > > > To: Nava kishore Manne > > > Cc: mark.rutl...@arm.com; Michal Simek ; Rajan > > > Vaja ; linux-arm-ker...@lists.infradead.org; > > > linux- ker...@vger.kernel.org; devicet...@vger.kernel.org; Jolly > > > Shah ; chinnikishore...@gmail.com > > > Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for > > > ZynqMP fpga driver > > > > > > On Wed, Jan 23, 2019 at 2:46 PM Nava kishore Manne > > > > > > wrote: > > > > > > > > Hi Rob, > > > > > > > > > > > > > > > > Thanks for providing the comments... > > > > > > Please fix your mailer to send plain text emails to mail lists. > > > > > Thanks for pointing it.. > > > > > > > > > > -Original Message- > > > > > > > > > From: Rob Herring [mailto:r...@kernel.org] > > > > > > > > > Sent: Monday, January 21, 2019 9:19 PM > > > > > > > > > To: Nava kishore Manne > > > > > > > > > Cc: mark.rutl...@arm.com; Michal Simek ; > > > > > Rajan Vaja > > > > > > > > > ; linux-arm-ker...@lists.infradead.org; > > > > > linux- > > > > > > > > > ker...@vger.kernel.org; devicet...@vger.kernel.org; Jolly Shah > > > > > > > > > ; chinnikishore...@gmail.com > > > > > > > > > Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for > > > > > ZynqMP fpga > > > > > > > > > driver > > > > > > > > > > > > > > > > > > On Mon, Jan 21, 2019 at 11:08:35PM +0530, Nava kishore Manne wrote: > > > > > > > > > > Add documentation to describe Xilinx ZynqMP fpga driver bindings. > > > > > > > > > > > > > > > > > > > > Signed-off-by: Nava kishore Manne > > > > > > > > > > --- > > > > > > > > > > Changes for v3: > > > > > > > > > > -Removed PCAP as a child node to the > > > > > > FW and Created > > > > > > > > > > an independent node since PCAP driver > > > > > > is a consumer > > > > > > > > > > not a provider. > > > > > > > > > > > > > > > > > > > > .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt | 13 > > > > > > + > > > > > > > > > > 1 file changed, 13 insertions(+) > > > > > > > > > > create mode 100644 > > > > > > > > > > Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.t > > > > > > xt > > > > > > > > > > > > > > > > > > > > diff --git > > > > > > > > > > a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga > > > > > > .txt > > > > > > > > > > b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga > > > > > > .txt > > > > > > > > > > new file mode 100644 > > > > > > > > > > index ..1f6f58872311 > > > > > > > > > > --- /dev/null > > > > > > > > > > +++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap- > > > > > > +++ fpga > > > > > > +++ .txt > > > > > > > > > > @@ -0,0 +1,13 @@ > >
RE: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga driver
Hi Rob,
Thanks for providing the review comments..
Please find my response inline.
> -Original Message-
> From: Rob Herring [mailto:r...@kernel.org]
> Sent: Saturday, February 23, 2019 2:01 AM
> To: Nava kishore Manne
> Cc: mark.rutl...@arm.com; Michal Simek ; Rajan Vaja
> ; linux-arm-ker...@lists.infradead.org; linux-
> ker...@vger.kernel.org; devicet...@vger.kernel.org; Jolly Shah
> ; chinnikishore...@gmail.com
> Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga
> driver
>
> On Wed, Jan 23, 2019 at 2:46 PM Nava kishore Manne
> wrote:
> >
> > Hi Rob,
> >
> >
> >
> > Thanks for providing the comments...
>
> Please fix your mailer to send plain text emails to mail lists.
>
Thanks for pointing it..
>
> > > -Original Message-
> >
> > > From: Rob Herring [mailto:r...@kernel.org]
> >
> > > Sent: Monday, January 21, 2019 9:19 PM
> >
> > > To: Nava kishore Manne
> >
> > > Cc: mark.rutl...@arm.com; Michal Simek ; Rajan
> > > Vaja
> >
> > > ; linux-arm-ker...@lists.infradead.org; linux-
> >
> > > ker...@vger.kernel.org; devicet...@vger.kernel.org; Jolly Shah
> >
> > > ; chinnikishore...@gmail.com
> >
> > > Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for
> > > ZynqMP fpga
> >
> > > driver
> >
> > >
> >
> > > On Mon, Jan 21, 2019 at 11:08:35PM +0530, Nava kishore Manne wrote:
> >
> > > > Add documentation to describe Xilinx ZynqMP fpga driver bindings.
> >
> > > >
> >
> > > > Signed-off-by: Nava kishore Manne
> >
> > > > ---
> >
> > > > Changes for v3:
> >
> > > > -Removed PCAP as a child node to the FW
> > > > and Created
> >
> > > > an independent node since PCAP driver is a
> > > > consumer
> >
> > > > not a provider.
> >
> > > >
> >
> > > > .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt | 13 +
> >
> > > > 1 file changed, 13 insertions(+)
> >
> > > > create mode 100644
> >
> > > > Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> >
> > > >
> >
> > > > diff --git
> >
> > > > a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> >
> > > > b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> >
> > > > new file mode 100644
> >
> > > > index ..1f6f58872311
> >
> > > > --- /dev/null
> >
> > > > +++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga
> > > > +++ .txt
> >
> > > > @@ -0,0 +1,13 @@
> >
> > > > +Device Tree zynqmp-fpga bindings for the Zynq Ultrascale+ MPSoC
> >
> > > > +controlled using ZynqMP SoC firmware interface For Bitstream
> >
> > > > +configuration on ZynqMp Soc uses processor configuration
> >
> > > > +port(PCAP) to configure the programmable logic(PL) through PS by
> >
> > > > +using FW interface.
> >
> > > > +
> >
> > > > +Required properties:
> >
> > > > +- compatible: should contain "xlnx,zynqmp-pcap-fpga"
> >
> > > > +
> >
> > > > +Example:
> >
> > > > + zynqmp_pcap: pcap {
> >
> > > > + compatible = "xlnx,zynqmp-pcap-fpga";
> >
> > > > + };
> >
> > >
> >
> > > There's no need for a DT node. Just make the firware driver create a
> > > platform
> >
> > > device for pcap.
> >
> > >
> >
> >
> >
> > This driver being used by the FPGA manager framework(fpga-region) to apply
> overlay's so this node is needed AFAIK.
>
> The binding says nothing about child nodes and what they are. Please define
> that.
>
Do you mean I need to add the example usage of the pcap node like as below in
the binding doc?
Device Tree Example for Full Reconfiguration
Live Device Tree contains:
zynqmp_pcap: pcap {
compatible = "xlnx,zynqmp-pcap-fpga";
};
fpga_region0: fpga-region0 {
compatible = "fpga-region";
fpga-mgr = <_pcap>;
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;
};
DT Overlay contains:
/dts-v1/ /plugin/;
/ {
fragment@0 {
target = <_region0>;
#address-cells = <1>;
#size-cells = <1>;
__overlay__ {
#address-cells = <1>;
#size-cells = <1>;
firmware-name = "zynqmp-gpio.bin";
gpio1: gpio@4000 {
compatible = "xlnx,xps-gpio-1.00.a";
reg = <0x4000 0x1>;
gpio-controller;
#gpio-cells = <0x2>;
xlnx,gpio-width= <0x6>;
};
};
};
Please correct me if my understanding is wrong.
Regards,
Navakishore.
[PATCH v3 2/3] dt-bindings: fpga: Add bindings for ZynqMP fpga driver
Add documentation to describe Xilinx ZynqMP fpga driver
bindings.
Signed-off-by: Nava kishore Manne
---
Changes for v3:
-Created patches on top of 5.0-rc5.
No functional changes.
Changes for v2:
-Removed "" separators.
Changes for v1:
-Created a Seperate(New) DT binding file as
suggested by Rob.
Changes for RFC-V2:
-Moved pcap node as a child to firwmare
node as suggested by Rob.
.../devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt | 13 +
1 file changed, 13 insertions(+)
create mode 100644
Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
diff --git a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
new file mode 100644
index 000..1f6f588
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
@@ -0,0 +1,13 @@
+Device Tree zynqmp-fpga bindings for the Zynq Ultrascale+ MPSoC controlled
+using ZynqMP SoC firmware interface
+For Bitstream configuration on ZynqMp Soc uses processor configuration
+port(PCAP) to configure the programmable logic(PL) through PS by using
+FW interface.
+
+Required properties:
+- compatible: should contain "xlnx,zynqmp-pcap-fpga"
+
+Example:
+ zynqmp_pcap: pcap {
+ compatible = "xlnx,zynqmp-pcap-fpga";
+ };
--
2.7.4
[PATCH v3 3/3] fpga manager: Adding FPGA Manager support for Xilinx zynqmp
This patch adds FPGA Manager support for the Xilinx
ZynqMP chip.
Signed-off-by: Nava kishore Manne
---
Changes for v3:
-Created patches on top of 5.0-rc5.
No functional changes.
Changes for v2:
-Fixed some minor coding issues as suggested by
Moritz
Changes for v1:
-None.
Changes for RFC-V2:
-Updated the Fpga Mgr registrations call's
to 4.18
drivers/fpga/Kconfig | 9 +++
drivers/fpga/Makefile | 1 +
drivers/fpga/zynqmp-fpga.c | 165 +
3 files changed, 175 insertions(+)
create mode 100644 drivers/fpga/zynqmp-fpga.c
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index 0bb7b5c..9f17203 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -204,4 +204,13 @@ config FPGA_DFL_PCI
To compile this as a module, choose M here.
+config FPGA_MGR_ZYNQMP_FPGA
+ tristate "Xilinx ZynqMP FPGA"
+ depends on ARCH_ZYNQMP || COMPILE_TEST
+ help
+ FPGA manager driver support for Xilinx ZynqMP FPGAs.
+ This driver uses the processor configuration port(PCAP)
+ to configure the programmable logic(PL) through PS
+ on ZynqMP SoC.
+
endif # FPGA
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index c0dd4c8..312b937 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_FPGA_MGR_STRATIX10_SOC) += stratix10-soc.o
obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o
obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o
obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o
+obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) += zynqmp-fpga.o
obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o
obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT)+= altera-pr-ip-core-plat.o
diff --git a/drivers/fpga/zynqmp-fpga.c b/drivers/fpga/zynqmp-fpga.c
new file mode 100644
index 000..f40c3bb
--- /dev/null
+++ b/drivers/fpga/zynqmp-fpga.c
@@ -0,0 +1,165 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Xilinx, Inc.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* Constant Definitions */
+#define IXR_FPGA_DONE_MASK 0X0008U
+
+/**
+ * struct zynqmp_fpga_priv - Private data structure
+ * @dev: Device data structure
+ * @flags: flags which is used to identify the bitfile type
+ */
+struct zynqmp_fpga_priv {
+ struct device *dev;
+ u32 flags;
+};
+
+static int zynqmp_fpga_ops_write_init(struct fpga_manager *mgr,
+ struct fpga_image_info *info,
+ const char *buf, size_t size)
+{
+ struct zynqmp_fpga_priv *priv;
+
+ priv = mgr->priv;
+ priv->flags = info->flags;
+
+ return 0;
+}
+
+static int zynqmp_fpga_ops_write(struct fpga_manager *mgr,
+const char *buf, size_t size)
+{
+ const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
+ struct zynqmp_fpga_priv *priv;
+ dma_addr_t dma_addr;
+ u32 eemi_flags = 0;
+ char *kbuf;
+ int ret;
+
+ if (!eemi_ops || !eemi_ops->fpga_load)
+ return -ENXIO;
+
+ priv = mgr->priv;
+
+ kbuf = dma_alloc_coherent(priv->dev, size, _addr, GFP_KERNEL);
+ if (!kbuf)
+ return -ENOMEM;
+
+ memcpy(kbuf, buf, size);
+
+ wmb(); /* ensure all writes are done before initiate FW call */
+
+ if (priv->flags & FPGA_MGR_PARTIAL_RECONFIG)
+ eemi_flags |= XILINX_ZYNQMP_PM_FPGA_PARTIAL;
+
+ ret = eemi_ops->fpga_load(dma_addr, size, eemi_flags);
+
+ dma_free_coherent(priv->dev, size, kbuf, dma_addr);
+
+ return ret;
+}
+
+static int zynqmp_fpga_ops_write_complete(struct fpga_manager *mgr,
+ struct fpga_image_info *info)
+{
+ return 0;
+}
+
+static enum fpga_mgr_states zynqmp_fpga_ops_state(struct fpga_manager *mgr)
+{
+ const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
+ u32 status;
+
+ if (!eemi_ops || !eemi_ops->fpga_get_status)
+ return FPGA_MGR_STATE_UNKNOWN;
+
+ eemi_ops->fpga_get_status();
+ if (status & IXR_FPGA_DONE_MASK)
+ return FPGA_MGR_STATE_OPERATING;
+
+ return FPGA_MGR_STATE_UNKNOWN;
+}
+
+static const struct fpga_manager_ops zynqmp_fpga_ops = {
+ .state = zynqmp_fpga_ops_state,
+ .write_init = zynqmp_fpga_ops_write_init,
+ .write = zynqmp_fpga_ops_write,
+ .write_complete = zynqmp_fpga_ops_write_complete,
+};
+
+static int zynqmp_fpga_probe(struct platform_device *pdev)
+{
+ struct device *dev = >dev;
+ struct zynqmp_fpga_priv *priv;
+ struct fpga_manager *mgr;
+ int err, ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv),
[PATCH v3 1/3] firmware: xilinx: Add fpga API's
This Patch Adds fpga API's to support the Bitstream loading
by using firmware interface.
Signed-off-by: Nava kishore Manne
---
Chnages for v3:
-Created patches on top of 5.0-rc5.
No functional changes.
Changes for v2:
-Added Firmware FPGA Manager flags As suggested by
Moritz.
Changes for v1:
-None.
Changes for RFC-V2:
-New Patch.
drivers/firmware/xilinx/zynqmp.c | 46
include/linux/firmware/xlnx-zynqmp.h | 12 ++
2 files changed, 58 insertions(+)
diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
index 9a1c72a..366441a 100644
--- a/drivers/firmware/xilinx/zynqmp.c
+++ b/drivers/firmware/xilinx/zynqmp.c
@@ -469,6 +469,50 @@ static int zynqmp_pm_ioctl(u32 node_id, u32 ioctl_id, u32
arg1, u32 arg2,
arg1, arg2, out);
}
+/*
+ * zynqmp_pm_fpga_load - Perform the fpga load
+ * @address: Address to write to
+ * @size: pl bitstream size
+ * @flags:
+ * BIT(0) - Bit-stream type.
+ * 0 - Full Bitstream.
+ * 1 - Partial Bitstream.
+ *
+ * This function provides access to pmufw. To transfer
+ * the required bitstream into PL.
+ *
+ * Return: Returns status, either success or error+reason
+ */
+static int zynqmp_pm_fpga_load(const u64 address, const u32 size,
+ const u32 flags)
+{
+ return zynqmp_pm_invoke_fn(PM_FPGA_LOAD, lower_32_bits(address),
+ upper_32_bits(address), size, flags, NULL);
+}
+
+/**
+ * zynqmp_pm_fpga_get_status - Read value from PCAP status register
+ * @value: Value to read
+ *
+ * This function provides access to the xilfpga library to get
+ * the PCAP status
+ *
+ * Return: Returns status, either success or error+reason
+ */
+static int zynqmp_pm_fpga_get_status(u32 *value)
+{
+ u32 ret_payload[PAYLOAD_ARG_CNT];
+ int ret;
+
+ if (!value)
+ return -EINVAL;
+
+ ret = zynqmp_pm_invoke_fn(PM_FPGA_GET_STATUS, 0, 0, 0, 0, ret_payload);
+ *value = ret_payload[1];
+
+ return ret;
+}
+
static const struct zynqmp_eemi_ops eemi_ops = {
.get_api_version = zynqmp_pm_get_api_version,
.query_data = zynqmp_pm_query_data,
@@ -482,6 +526,8 @@ static const struct zynqmp_eemi_ops eemi_ops = {
.clock_setparent = zynqmp_pm_clock_setparent,
.clock_getparent = zynqmp_pm_clock_getparent,
.ioctl = zynqmp_pm_ioctl,
+ .fpga_load = zynqmp_pm_fpga_load,
+ .fpga_get_status = zynqmp_pm_fpga_get_status,
};
/**
diff --git a/include/linux/firmware/xlnx-zynqmp.h
b/include/linux/firmware/xlnx-zynqmp.h
index 3c3c28e..16d4042 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -32,8 +32,18 @@
/* Number of 32bits values in payload */
#define PAYLOAD_ARG_CNT4U
+/*
+ * Firmware FPGA Manager flags
+ * XILINX_ZYNQMP_PM_FPGA_PARTIAL: FPGA partial reconfiguration
+ */
+#define XILINX_ZYNQMP_PM_FPGA_PARTIAL BIT(0)
+
+
+
enum pm_api_id {
PM_GET_API_VERSION = 1,
+ PM_FPGA_LOAD = 22,
+ PM_FPGA_GET_STATUS,
PM_IOCTL = 34,
PM_QUERY_DATA,
PM_CLOCK_ENABLE,
@@ -91,6 +101,8 @@ struct zynqmp_pm_query_data {
struct zynqmp_eemi_ops {
int (*get_api_version)(u32 *version);
+ int (*fpga_load)(const u64 address, const u32 size, const u32 flags);
+ int (*fpga_get_status)(u32 *value);
int (*query_data)(struct zynqmp_pm_query_data qdata, u32 *out);
int (*clock_enable)(u32 clock_id);
int (*clock_disable)(u32 clock_id);
--
2.7.4
[PATCH v3 0/3] Add Bitstream configuration support for ZynqMP
Nava kishore Manne (3): firmware: xilinx: Add fpga API's dt-bindings: fpga: Add bindings for ZynqMP fpga driver fpga manager: Adding FPGA Manager support for Xilinx zynqmp .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt| 13 ++ drivers/firmware/xilinx/zynqmp.c | 46 ++ drivers/fpga/Kconfig | 9 ++ drivers/fpga/Makefile | 1 + drivers/fpga/zynqmp-fpga.c | 165 + include/linux/firmware/xlnx-zynqmp.h | 12 ++ 6 files changed, 246 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt create mode 100644 drivers/fpga/zynqmp-fpga.c -- 2.7.4
[PATCH v3 1/3] firmware: xilinx: Add zynqmp_pm_get_chipid() API
This patch adds a new API to provide access to the
hardware related data like soc revision, IDCODE... etc.
Signed-off-by: Nava kishore Manne
---
Changes for v3:
-None.
Changes for v2:
-None.
Changes for v1:
-None.
Changes for RFC-V3:
-corrected typo error in commit msg.
Changes for RFC-v2:
-New Patch.
drivers/firmware/xilinx/zynqmp.c | 24
include/linux/firmware/xlnx-zynqmp.h | 2 ++
2 files changed, 26 insertions(+)
diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
index 9a1c72a9280f..af2a209fc2da 100644
--- a/drivers/firmware/xilinx/zynqmp.c
+++ b/drivers/firmware/xilinx/zynqmp.c
@@ -186,6 +186,29 @@ static int zynqmp_pm_get_api_version(u32 *version)
return ret;
}
+/**
+ * zynqmp_pm_get_chipid - Get silicon ID registers
+ * @idcode: IDCODE register
+ * @version:version register
+ *
+ * Return: Returns the status of the operation and the idcode and version
+ * registers in @idcode and @version.
+ */
+static int zynqmp_pm_get_chipid(u32 *idcode, u32 *version)
+{
+ u32 ret_payload[PAYLOAD_ARG_CNT];
+ int ret;
+
+ if (!idcode || !version)
+ return -EINVAL;
+
+ ret = zynqmp_pm_invoke_fn(PM_GET_CHIPID, 0, 0, 0, 0, ret_payload);
+ *idcode = ret_payload[1];
+ *version = ret_payload[2];
+
+ return ret;
+}
+
/**
* zynqmp_pm_get_trustzone_version() - Get secure trustzone firmware version
* @version: Returned version value
@@ -471,6 +494,7 @@ static int zynqmp_pm_ioctl(u32 node_id, u32 ioctl_id, u32
arg1, u32 arg2,
static const struct zynqmp_eemi_ops eemi_ops = {
.get_api_version = zynqmp_pm_get_api_version,
+ .get_chipid = zynqmp_pm_get_chipid,
.query_data = zynqmp_pm_query_data,
.clock_enable = zynqmp_pm_clock_enable,
.clock_disable = zynqmp_pm_clock_disable,
diff --git a/include/linux/firmware/xlnx-zynqmp.h
b/include/linux/firmware/xlnx-zynqmp.h
index 3c3c28eff56a..c435f4b35adf 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -34,6 +34,7 @@
enum pm_api_id {
PM_GET_API_VERSION = 1,
+ PM_GET_CHIPID = 22,
PM_IOCTL = 34,
PM_QUERY_DATA,
PM_CLOCK_ENABLE,
@@ -91,6 +92,7 @@ struct zynqmp_pm_query_data {
struct zynqmp_eemi_ops {
int (*get_api_version)(u32 *version);
+ int (*get_chipid)(u32 *idcode, u32 *version);
int (*query_data)(struct zynqmp_pm_query_data qdata, u32 *out);
int (*clock_enable)(u32 clock_id);
int (*clock_disable)(u32 clock_id);
--
2.18.0
[PATCH v3 3/3] nvmem: zynqmp: Added zynqmp nvmem firmware driver
This patch adds zynqmp nvmem firmware driver to access the
SoC revision information from the hardware register.
Signed-off-by: Nava kishore Manne
---
Changes for v3:
-Removed irrelevant changes from Kconfig and
Make files.
Changes for v2:
-None.
Changes for v1:
-None.
Changes for RFC-V3:
-Changed nvmem_register() to devm_nvmem_register()
and pr_debug() to dev_dbg() as suggested by srinivas.
Changes for RFC-V2:
-None.
drivers/nvmem/Kconfig| 10 +
drivers/nvmem/Makefile | 2 +
drivers/nvmem/zynqmp_nvmem.c | 86
3 files changed, 98 insertions(+)
create mode 100644 drivers/nvmem/zynqmp_nvmem.c
diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig
index 0a7a470ee859..4ad846ceac7c 100644
--- a/drivers/nvmem/Kconfig
+++ b/drivers/nvmem/Kconfig
@@ -192,4 +192,14 @@ config SC27XX_EFUSE
This driver can also be built as a module. If so, the module
will be called nvmem-sc27xx-efuse.
+config NVMEM_ZYNQMP
+ bool "Xilinx ZYNQMP SoC nvmem firmware support"
+ depends on ARCH_ZYNQMP
+ help
+ This is a driver to access hardware related data like
+ soc revision, IDCODE... etc by using the firmware
+ interface.
+
+ If sure, say yes. If unsure, say no.
+
endif
diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile
index 4e8c61628f1a..2ece8dda 100644
--- a/drivers/nvmem/Makefile
+++ b/drivers/nvmem/Makefile
@@ -41,3 +41,5 @@ obj-$(CONFIG_RAVE_SP_EEPROM) += nvmem-rave-sp-eeprom.o
nvmem-rave-sp-eeprom-y := rave-sp-eeprom.o
obj-$(CONFIG_SC27XX_EFUSE) += nvmem-sc27xx-efuse.o
nvmem-sc27xx-efuse-y := sc27xx-efuse.o
+obj-$(CONFIG_NVMEM_ZYNQMP) += nvmem_zynqmp_nvmem.o
+nvmem_zynqmp_nvmem-y := zynqmp_nvmem.o
diff --git a/drivers/nvmem/zynqmp_nvmem.c b/drivers/nvmem/zynqmp_nvmem.c
new file mode 100644
index ..490c8fcaec80
--- /dev/null
+++ b/drivers/nvmem/zynqmp_nvmem.c
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Xilinx, Inc.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#define SILICON_REVISION_MASK 0xF
+
+struct zynqmp_nvmem_data {
+ struct device *dev;
+ struct nvmem_device *nvmem;
+};
+
+static int zynqmp_nvmem_read(void *context, unsigned int offset,
+void *val, size_t bytes)
+{
+ int ret;
+ int idcode, version;
+ struct zynqmp_nvmem_data *priv = context;
+
+ const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
+
+ if (!eemi_ops || !eemi_ops->get_chipid)
+ return -ENXIO;
+
+ ret = eemi_ops->get_chipid(, );
+ if (ret < 0)
+ return ret;
+
+ dev_dbg(priv->dev, "Read chipid val %x %x\n", idcode, version);
+ *(int *)val = version & SILICON_REVISION_MASK;
+
+ return 0;
+}
+
+static struct nvmem_config econfig = {
+ .name = "zynqmp-nvmem",
+ .owner = THIS_MODULE,
+ .word_size = 1,
+ .size = 1,
+ .read_only = true,
+};
+
+static const struct of_device_id zynqmp_nvmem_match[] = {
+ { .compatible = "xlnx,zynqmp-nvmem-fw", },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, zynqmp_nvmem_match);
+
+static int zynqmp_nvmem_probe(struct platform_device *pdev)
+{
+ struct device *dev = >dev;
+ struct zynqmp_nvmem_data *priv;
+
+ priv = devm_kzalloc(dev, sizeof(struct zynqmp_nvmem_data), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->dev = dev;
+ econfig.dev = dev;
+ econfig.reg_read = zynqmp_nvmem_read;
+ econfig.priv = priv;
+
+ priv->nvmem = devm_nvmem_register(dev, );
+
+ return PTR_ERR_OR_ZERO(priv->nvmem);
+}
+
+static struct platform_driver zynqmp_nvmem_driver = {
+ .probe = zynqmp_nvmem_probe,
+ .driver = {
+ .name = "zynqmp-nvmem",
+ .of_match_table = zynqmp_nvmem_match,
+ },
+};
+
+module_platform_driver(zynqmp_nvmem_driver);
+
+MODULE_AUTHOR("Michal Simek , Nava kishore Manne
");
+MODULE_DESCRIPTION("ZynqMP NVMEM driver");
+MODULE_LICENSE("GPL");
--
2.18.0
[PATCH v3 0/3] Add nvmem driver support for ZynqMP
Nava kishore Manne (3): firmware: xilinx: Add zynqmp_pm_get_chipid() API dt-bindings: nvmem: Add bindings for ZynqMP nvmem driver nvmem: zynqmp: Added zynqmp nvmem firmware driver .../bindings/nvmem/xlnx,zynqmp-nvmem.txt | 47 ++ drivers/firmware/xilinx/zynqmp.c | 24 ++ drivers/nvmem/Kconfig | 10 +++ drivers/nvmem/Makefile| 2 + drivers/nvmem/zynqmp_nvmem.c | 86 +++ include/linux/firmware/xlnx-zynqmp.h | 2 + 6 files changed, 171 insertions(+) create mode 100644 Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt create mode 100644 drivers/nvmem/zynqmp_nvmem.c -- 2.18.0
[PATCH v3 2/3] dt-bindings: nvmem: Add bindings for ZynqMP nvmem driver
Add documentation to describe Xilinx ZynqMP nvmem driver
bindings.
Signed-off-by: Nava kishore Manne
Reviewed-by: Rob Herring
---
.../bindings/nvmem/xlnx,zynqmp-nvmem.txt | 47 +++
1 file changed, 47 insertions(+)
create mode 100644
Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt
diff --git a/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt
b/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt
new file mode 100644
index ..2043c8284f8c
--- /dev/null
+++ b/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt
@@ -0,0 +1,47 @@
+--
+= Zynq UltraScale+ MPSoC nvmem firmware driver binding =
+--
+The nvmem_firmware node provides access to the hardware related data
+like soc revision, IDCODE... etc, By using the firmware interface.
+
+Required properties:
+- compatible: should be "xlnx,zynqmp-nvmem-fw"
+
+= Data cells =
+Are child nodes of silicon id, bindings of which as described in
+bindings/nvmem/nvmem.txt
+
+---
+ Example
+---
+firmware {
+ zynqmp_firmware: zynqmp-firmware {
+ compatible = "xlnx,zynqmp-firmware";
+ method = "smc";
+
+ nvmem_firmware {
+ compatible = "xlnx,zynqmp-nvmem-fw";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* Data cells */
+ soc_revision: soc_revision {
+ reg = <0x0 0x4>;
+ };
+ };
+ };
+};
+
+= Data consumers =
+Are device nodes which consume nvmem data cells.
+
+For example:
+ pcap {
+ ...
+
+ nvmem-cells = <_revision>;
+ nvmem-cell-names = "soc_revision";
+
+ ...
+ };
+
--
2.18.0
[PATCH v2 2/3] dt-bindings: nvmem: Add bindings for ZynqMP nvmem driver
Add documentation to describe Xilinx ZynqMP nvmem driver
bindings.
Signed-off-by: Nava kishore Manne
Reviewed-by: Rob Herring
---
.../bindings/nvmem/xlnx,zynqmp-nvmem.txt | 47 +++
1 file changed, 47 insertions(+)
create mode 100644
Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt
diff --git a/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt
b/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt
new file mode 100644
index ..2043c8284f8c
--- /dev/null
+++ b/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt
@@ -0,0 +1,47 @@
+--
+= Zynq UltraScale+ MPSoC nvmem firmware driver binding =
+--
+The nvmem_firmware node provides access to the hardware related data
+like soc revision, IDCODE... etc, By using the firmware interface.
+
+Required properties:
+- compatible: should be "xlnx,zynqmp-nvmem-fw"
+
+= Data cells =
+Are child nodes of silicon id, bindings of which as described in
+bindings/nvmem/nvmem.txt
+
+---
+ Example
+---
+firmware {
+ zynqmp_firmware: zynqmp-firmware {
+ compatible = "xlnx,zynqmp-firmware";
+ method = "smc";
+
+ nvmem_firmware {
+ compatible = "xlnx,zynqmp-nvmem-fw";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* Data cells */
+ soc_revision: soc_revision {
+ reg = <0x0 0x4>;
+ };
+ };
+ };
+};
+
+= Data consumers =
+Are device nodes which consume nvmem data cells.
+
+For example:
+ pcap {
+ ...
+
+ nvmem-cells = <_revision>;
+ nvmem-cell-names = "soc_revision";
+
+ ...
+ };
+
--
2.18.0
[PATCH v2 3/3] nvmem: zynqmp: Added zynqmp nvmem firmware driver
This patch adds zynqmp nvmem firmware driver to access the
SoC revision information from the hardware register.
Signed-off-by: Nava kishore Manne
---
Changes for v2:
-None.
Changes for v1:
-None.
Changes for RFC-V3:
-Changed nvmem_register() to devm_nvmem_register()
and pr_debug() to dev_dbg() as suggested by srinivas.
Changes for RFC-V2:
-None.
drivers/nvmem/Kconfig| 15 +++
drivers/nvmem/Makefile | 5 ++-
drivers/nvmem/zynqmp_nvmem.c | 86
3 files changed, 96 insertions(+), 10 deletions(-)
create mode 100644 drivers/nvmem/zynqmp_nvmem.c
diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig
index 0a7a470ee859..2edb1428ef6d 100644
--- a/drivers/nvmem/Kconfig
+++ b/drivers/nvmem/Kconfig
@@ -181,15 +181,14 @@ config RAVE_SP_EEPROM
help
Say y here to enable Rave SP EEPROM support.
-config SC27XX_EFUSE
- tristate "Spreadtrum SC27XX eFuse Support"
- depends on MFD_SC27XX_PMIC || COMPILE_TEST
- depends on HAS_IOMEM
+config NVMEM_ZYNQMP
+ bool "Xilinx ZYNQMP SoC nvmem firmware support"
+ depends on ARCH_ZYNQMP
help
- This is a simple driver to dump specified values of Spreadtrum
- SC27XX PMICs from eFuse.
+ This is a driver to access hardware related data like
+ soc revision, IDCODE... etc by using the firmware
+ interface.
- This driver can also be built as a module. If so, the module
- will be called nvmem-sc27xx-efuse.
+ If sure, say yes. If unsure, say no.
endif
diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile
index 4e8c61628f1a..0b3abd7f5d02 100644
--- a/drivers/nvmem/Makefile
+++ b/drivers/nvmem/Makefile
@@ -39,5 +39,6 @@ obj-$(CONFIG_NVMEM_SNVS_LPGPR)+= nvmem_snvs_lpgpr.o
nvmem_snvs_lpgpr-y := snvs_lpgpr.o
obj-$(CONFIG_RAVE_SP_EEPROM) += nvmem-rave-sp-eeprom.o
nvmem-rave-sp-eeprom-y := rave-sp-eeprom.o
-obj-$(CONFIG_SC27XX_EFUSE) += nvmem-sc27xx-efuse.o
-nvmem-sc27xx-efuse-y := sc27xx-efuse.o
+obj-$(CONFIG_NVMEM_ZYNQMP) += nvmem_zynqmp_nvmem.o
+nvmem_zynqmp_nvmem-y := zynqmp_nvmem.o
+
diff --git a/drivers/nvmem/zynqmp_nvmem.c b/drivers/nvmem/zynqmp_nvmem.c
new file mode 100644
index ..b910864e91b7
--- /dev/null
+++ b/drivers/nvmem/zynqmp_nvmem.c
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Xilinx, Inc.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#define SILICON_REVISION_MASK 0xF
+
+struct zynqmp_nvmem_data {
+ struct device *dev;
+ struct nvmem_device *nvmem;
+};
+
+static int zynqmp_nvmem_read(void *context, unsigned int offset,
+void *val, size_t bytes)
+{
+ int ret;
+ int idcode, version;
+ struct zynqmp_nvmem_data *priv = context;
+
+ const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
+
+ if (!eemi_ops || !eemi_ops->get_chipid)
+ return -ENXIO;
+
+ ret = eemi_ops->get_chipid(, );
+ if (ret < 0)
+ return ret;
+
+ dev_dbg(priv->dev, "Read chipid val %x %x\n", idcode, version);
+ *(int *)val = version & SILICON_REVISION_MASK;
+
+ return 0;
+}
+
+static struct nvmem_config econfig = {
+ .name = "zynqmp-nvmem",
+ .owner = THIS_MODULE,
+ .word_size = 1,
+ .size = 1,
+ .read_only = true,
+};
+
+static const struct of_device_id zynqmp_nvmem_match[] = {
+ { .compatible = "xlnx,zynqmp-nvmem-fw", },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, zynqmp_nvmem_match);
+
+static int zynqmp_nvmem_probe(struct platform_device *pdev)
+{
+ struct device *dev = >dev;
+ struct zynqmp_nvmem_data *priv;
+
+ priv = devm_kzalloc(dev, sizeof(struct zynqmp_nvmem_data), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->dev = dev;
+ econfig.dev = dev;
+ econfig.reg_read = zynqmp_nvmem_read;
+ econfig.priv = priv;
+
+ priv->nvmem = devm_nvmem_register(dev, );
+
+ return PTR_ERR_OR_ZERO(priv->nvmem);
+}
+
+static struct platform_driver zynqmp_nvmem_driver = {
+ .probe = zynqmp_nvmem_probe,
+ .driver = {
+ .name = "zynqmp-nvmem",
+ .of_match_table = zynqmp_nvmem_match,
+ },
+};
+
+module_platform_driver(zynqmp_nvmem_driver);
+
+MODULE_AUTHOR("Michal Simek , Nava kishore Manne
");
+MODULE_DESCRIPTION("ZynqMP NVMEM driver");
+MODULE_LICENSE("GPL");
--
2.18.0
[PATCH v2 0/3] Add nvmem driver support for ZynqMP
Nava kishore Manne (3): firmware: xilinx: Add zynqmp_pm_get_chipid() API dt-bindings: nvmem: Add bindings for ZynqMP nvmem driver nvmem: zynqmp: Added zynqmp nvmem firmware driver .../bindings/nvmem/xlnx,zynqmp-nvmem.txt | 47 ++ drivers/firmware/xilinx/zynqmp.c | 24 ++ drivers/nvmem/Kconfig | 15 ++-- drivers/nvmem/Makefile| 5 +- drivers/nvmem/zynqmp_nvmem.c | 86 +++ include/linux/firmware/xlnx-zynqmp.h | 2 + 6 files changed, 169 insertions(+), 10 deletions(-) create mode 100644 Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt create mode 100644 drivers/nvmem/zynqmp_nvmem.c -- 2.18.0
[PATCH v2 1/3] firmware: xilinx: Add zynqmp_pm_get_chipid() API
This patch adds a new API to provide access to the
hardware related data like soc revision, IDCODE... etc.
Signed-off-by: Nava kishore Manne
---
Changes for v2:
-None.
Changes for v1:
-None.
Changes for RFC-V3:
-corrected typo error in commit msg.
Changes for RFC-v2:
-New Patch.
drivers/firmware/xilinx/zynqmp.c | 24
include/linux/firmware/xlnx-zynqmp.h | 2 ++
2 files changed, 26 insertions(+)
diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
index 9a1c72a9280f..af2a209fc2da 100644
--- a/drivers/firmware/xilinx/zynqmp.c
+++ b/drivers/firmware/xilinx/zynqmp.c
@@ -186,6 +186,29 @@ static int zynqmp_pm_get_api_version(u32 *version)
return ret;
}
+/**
+ * zynqmp_pm_get_chipid - Get silicon ID registers
+ * @idcode: IDCODE register
+ * @version:version register
+ *
+ * Return: Returns the status of the operation and the idcode and version
+ * registers in @idcode and @version.
+ */
+static int zynqmp_pm_get_chipid(u32 *idcode, u32 *version)
+{
+ u32 ret_payload[PAYLOAD_ARG_CNT];
+ int ret;
+
+ if (!idcode || !version)
+ return -EINVAL;
+
+ ret = zynqmp_pm_invoke_fn(PM_GET_CHIPID, 0, 0, 0, 0, ret_payload);
+ *idcode = ret_payload[1];
+ *version = ret_payload[2];
+
+ return ret;
+}
+
/**
* zynqmp_pm_get_trustzone_version() - Get secure trustzone firmware version
* @version: Returned version value
@@ -471,6 +494,7 @@ static int zynqmp_pm_ioctl(u32 node_id, u32 ioctl_id, u32
arg1, u32 arg2,
static const struct zynqmp_eemi_ops eemi_ops = {
.get_api_version = zynqmp_pm_get_api_version,
+ .get_chipid = zynqmp_pm_get_chipid,
.query_data = zynqmp_pm_query_data,
.clock_enable = zynqmp_pm_clock_enable,
.clock_disable = zynqmp_pm_clock_disable,
diff --git a/include/linux/firmware/xlnx-zynqmp.h
b/include/linux/firmware/xlnx-zynqmp.h
index 3c3c28eff56a..c435f4b35adf 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -34,6 +34,7 @@
enum pm_api_id {
PM_GET_API_VERSION = 1,
+ PM_GET_CHIPID = 22,
PM_IOCTL = 34,
PM_QUERY_DATA,
PM_CLOCK_ENABLE,
@@ -91,6 +92,7 @@ struct zynqmp_pm_query_data {
struct zynqmp_eemi_ops {
int (*get_api_version)(u32 *version);
+ int (*get_chipid)(u32 *idcode, u32 *version);
int (*query_data)(struct zynqmp_pm_query_data qdata, u32 *out);
int (*clock_enable)(u32 clock_id);
int (*clock_disable)(u32 clock_id);
--
2.18.0
[PATCH v3 3/3] reset: reset-zynqmp: Adding support for Xilinx zynqmp reset controller.
Add a reset controller driver for Xilinx Zynq UltraScale+ MPSoC.
The zynqmp reset-controller has the ability to reset lines
connected to different blocks and peripheral in the Soc.
Signed-off-by: Nava kishore Manne
---
Changes for v3:
-Fixed some minor coding issues as suggested
by philipp and vesa.
Changes for v2:
-Fixed some minor coding issues as suggested
by philipp.
Changes for v1:
-None.
Changes for RFC-V3:
-None.
Changes for RFC-V2:
-Moved eemi_ops into a priv struct as suggested
by philipp.
drivers/reset/Makefile | 1 +
drivers/reset/reset-zynqmp.c | 114 +++
2 files changed, 115 insertions(+)
create mode 100644 drivers/reset/reset-zynqmp.c
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index dc7874df78d9..573b8386d901 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -26,4 +26,5 @@ obj-$(CONFIG_RESET_TI_SYSCON) += reset-ti-syscon.o
obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
obj-$(CONFIG_RESET_UNIPHIER_GLUE) += reset-uniphier-glue.o
obj-$(CONFIG_RESET_ZYNQ) += reset-zynq.o
+obj-$(CONFIG_ARCH_ZYNQMP) += reset-zynqmp.o
diff --git a/drivers/reset/reset-zynqmp.c b/drivers/reset/reset-zynqmp.c
new file mode 100644
index ..2ef1f13aa47b
--- /dev/null
+++ b/drivers/reset/reset-zynqmp.c
@@ -0,0 +1,114 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Xilinx, Inc.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#define ZYNQMP_NR_RESETS (ZYNQMP_PM_RESET_END - ZYNQMP_PM_RESET_START)
+#define ZYNQMP_RESET_ID ZYNQMP_PM_RESET_START
+
+struct zynqmp_reset_data {
+ struct reset_controller_dev rcdev;
+ const struct zynqmp_eemi_ops *eemi_ops;
+};
+
+static inline struct zynqmp_reset_data *
+to_zynqmp_reset_data(struct reset_controller_dev *rcdev)
+{
+ return container_of(rcdev, struct zynqmp_reset_data, rcdev);
+}
+
+static int zynqmp_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct zynqmp_reset_data *priv = to_zynqmp_reset_data(rcdev);
+
+ return priv->eemi_ops->reset_assert(ZYNQMP_RESET_ID + id,
+ PM_RESET_ACTION_ASSERT);
+}
+
+static int zynqmp_reset_deassert(struct reset_controller_dev *rcdev,
+unsigned long id)
+{
+ struct zynqmp_reset_data *priv = to_zynqmp_reset_data(rcdev);
+
+ return priv->eemi_ops->reset_assert(ZYNQMP_RESET_ID + id,
+ PM_RESET_ACTION_RELEASE);
+}
+
+static int zynqmp_reset_status(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct zynqmp_reset_data *priv = to_zynqmp_reset_data(rcdev);
+ int val, err;
+
+ err = priv->eemi_ops->reset_get_status(ZYNQMP_RESET_ID + id, );
+ if (err)
+ return err;
+
+ return val;
+}
+
+static int zynqmp_reset_reset(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct zynqmp_reset_data *priv = to_zynqmp_reset_data(rcdev);
+
+ return priv->eemi_ops->reset_assert(ZYNQMP_RESET_ID + id,
+ PM_RESET_ACTION_PULSE);
+}
+
+static struct reset_control_ops zynqmp_reset_ops = {
+ .reset = zynqmp_reset_reset,
+ .assert = zynqmp_reset_assert,
+ .deassert = zynqmp_reset_deassert,
+ .status = zynqmp_reset_status,
+};
+
+static int zynqmp_reset_probe(struct platform_device *pdev)
+{
+ struct zynqmp_reset_data *priv;
+
+ priv = devm_kzalloc(>dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, priv);
+
+ priv->eemi_ops = zynqmp_pm_get_eemi_ops();
+ if (!priv->eemi_ops)
+ return -ENXIO;
+
+ priv->rcdev.ops = _reset_ops;
+ priv->rcdev.owner = THIS_MODULE;
+ priv->rcdev.of_node = pdev->dev.of_node;
+ priv->rcdev.nr_resets = ZYNQMP_NR_RESETS;
+
+ return devm_reset_controller_register(>dev, >rcdev);
+}
+
+static const struct of_device_id zynqmp_reset_dt_ids[] = {
+ { .compatible = "xlnx,zynqmp-reset", },
+ { /* sentinel */ },
+};
+
+static struct platform_driver zynqmp_reset_driver = {
+ .probe = zynqmp_reset_probe,
+ .driver = {
+ .name = KBUILD_MODNAME,
+ .of_match_table = zynqmp_reset_dt_ids,
+ },
+};
+
+static int __init zynqmp_reset_init(void)
+{
+ return platform_driver_register(_reset_driver);
+}
+
+arch_initcall(zynqmp_reset_init);
--
2.18.0
[PATCH v3 2/3] dt-bindings: reset: Add bindings for ZynqMP reset driver
Add documentation to describe Xilinx ZynqMP reset driver
bindings.
Signed-off-by: Nava kishore Manne
Signed-off-by: Jolly Shah
Reviewed-by: Rob Herring
---
.../bindings/reset/xlnx,zynqmp-reset.txt | 52 +++
.../dt-bindings/reset/xlnx-zynqmp-resets.h| 130 ++
2 files changed, 182 insertions(+)
create mode 100644
Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt
create mode 100644 include/dt-bindings/reset/xlnx-zynqmp-resets.h
diff --git a/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt
b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt
new file mode 100644
index ..27a45fe5ecf1
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt
@@ -0,0 +1,52 @@
+--
+ = Zynq UltraScale+ MPSoC reset driver binding =
+--
+The Zynq UltraScale+ MPSoC has several different resets.
+
+See Chapter 36 of the Zynq UltraScale+ MPSoC TRM (UG) for more information
+about zynqmp resets.
+
+Please also refer to reset.txt in this directory for common reset
+controller binding usage.
+
+Required Properties:
+- compatible: "xlnx,zynqmp-reset"
+- #reset-cells:Specifies the number of cells needed to encode reset
+ line, should be 1
+
+---
+Example
+---
+
+firmware {
+ zynqmp_firmware: zynqmp-firmware {
+ compatible = "xlnx,zynqmp-firmware";
+ method = "smc";
+
+ zynqmp_reset: reset-controller {
+ compatible = "xlnx,zynqmp-reset";
+ #reset-cells = <1>;
+ };
+ };
+};
+
+Specifying reset lines connected to IP modules
+==
+
+Device nodes that need access to reset lines should
+specify them as a reset phandle in their corresponding node as
+specified in reset.txt.
+
+For list of all valid reset indicies see
+
+
+Example:
+
+serdes: zynqmp_phy@fd40 {
+ ...
+
+ resets = <_reset ZYNQMP_RESET_SATA>;
+ reset-names = "sata_rst";
+
+ ...
+};
diff --git a/include/dt-bindings/reset/xlnx-zynqmp-resets.h
b/include/dt-bindings/reset/xlnx-zynqmp-resets.h
new file mode 100644
index ..d44525b9f8db
--- /dev/null
+++ b/include/dt-bindings/reset/xlnx-zynqmp-resets.h
@@ -0,0 +1,130 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 Xilinx, Inc.
+ */
+
+#ifndef _DT_BINDINGS_ZYNQMP_RESETS_H
+#define _DT_BINDINGS_ZYNQMP_RESETS_H
+
+#defineZYNQMP_RESET_PCIE_CFG 0
+#defineZYNQMP_RESET_PCIE_BRIDGE1
+#defineZYNQMP_RESET_PCIE_CTRL 2
+#defineZYNQMP_RESET_DP 3
+#defineZYNQMP_RESET_SWDT_CRF 4
+#defineZYNQMP_RESET_AFI_FM55
+#defineZYNQMP_RESET_AFI_FM46
+#defineZYNQMP_RESET_AFI_FM37
+#defineZYNQMP_RESET_AFI_FM28
+#defineZYNQMP_RESET_AFI_FM19
+#defineZYNQMP_RESET_AFI_FM010
+#defineZYNQMP_RESET_GDMA 11
+#defineZYNQMP_RESET_GPU_PP112
+#defineZYNQMP_RESET_GPU_PP013
+#defineZYNQMP_RESET_GPU14
+#defineZYNQMP_RESET_GT 15
+#defineZYNQMP_RESET_SATA 16
+#defineZYNQMP_RESET_ACPU3_PWRON17
+#defineZYNQMP_RESET_ACPU2_PWRON18
+#defineZYNQMP_RESET_ACPU1_PWRON19
+#defineZYNQMP_RESET_ACPU0_PWRON20
+#defineZYNQMP_RESET_APU_L2 21
+#defineZYNQMP_RESET_ACPU3 22
+#defineZYNQMP_RESET_ACPU2 23
+#defineZYNQMP_RESET_ACPU1 24
+#defineZYNQMP_RESET_ACPU0 25
+#defineZYNQMP_RESET_DDR26
+#defineZYNQMP_RESET_APM_FPD27
+#defineZYNQMP_RESET_SOFT 28
+#defineZYNQMP_RESET_GEM0 29
+#defineZYNQMP_RESET_GEM1 30
+#defineZYNQMP_RESET_GEM2 31
+#defineZYNQMP_RESET_GEM3 32
+#defineZYNQMP_RESET_QSPI 33
+#defineZYNQMP_RESET_UART0 34
+#defineZYNQMP_RESET_UART1 35
+#defineZYNQMP_RESET_SPI0 36
+#defineZYNQMP_RESET_SPI1 37
+#defineZYNQMP_RESET_SDIO0 38
+#def
[PATCH v3 0/3] Add reset driver support for ZynqMP
Nava kishore Manne (3): firmware: xilinx: Add reset API's dt-bindings: reset: Add bindings for ZynqMP reset driver reset: reset-zynqmp: Adding support for Xilinx zynqmp reset controller. .../bindings/reset/xlnx,zynqmp-reset.txt | 52 +++ drivers/firmware/xilinx/zynqmp.c | 40 ++ drivers/reset/Makefile| 1 + drivers/reset/reset-zynqmp.c | 114 +++ .../dt-bindings/reset/xlnx-zynqmp-resets.h| 130 + include/linux/firmware/xlnx-zynqmp.h | 136 ++ 6 files changed, 473 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt create mode 100644 drivers/reset/reset-zynqmp.c create mode 100644 include/dt-bindings/reset/xlnx-zynqmp-resets.h -- 2.18.0
